drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47
  48 #ifdef RTL8169_DEBUG
  49 #define assert(expr) \
  50         if (!(expr)) {                                  \
  51                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  52                 #expr,__FILE__,__func__,__LINE__);              \
  53         }
  54 #define dprintk(fmt, args...) \
  55         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  56 #else
  57 #define assert(expr) do {} while (0)
  58 #define dprintk(fmt, args...)   do {} while (0)
  59 #endif /* RTL8169_DEBUG */
  60
  61 #define R8169_MSG_DEFAULT \
  62         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  63
  64 #define TX_SLOTS_AVAIL(tp) \
  65         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  66
  67 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  68 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  69         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  70
  71 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  72    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  73 static const int multicast_filter_limit = 32;
  74
  75 #define MAX_READ_REQUEST_SHIFT  12
  76 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  77 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  78 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  79
  80 #define R8169_REGS_SIZE         256
  81 #define R8169_NAPI_WEIGHT       64
  82 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  83 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  84 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  85 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  86 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  87
  88 #define RTL8169_TX_TIMEOUT      (6*HZ)
  89 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  90
  91 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  92 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  93 #define RTL_EEPROM_SIG_ADDR     0x0000
  94
  95 /* write/read MMIO register */
  96 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  97 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  98 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  99 #define RTL_R8(reg)             readb (ioaddr + (reg))
 100 #define RTL_R16(reg)            readw (ioaddr + (reg))
 101 #define RTL_R32(reg)            readl (ioaddr + (reg))
 102
 103 enum mac_version {
 104         RTL_GIGA_MAC_VER_01 = 0,
 105         RTL_GIGA_MAC_VER_02,
 106         RTL_GIGA_MAC_VER_03,
 107         RTL_GIGA_MAC_VER_04,
 108         RTL_GIGA_MAC_VER_05,
 109         RTL_GIGA_MAC_VER_06,
 110         RTL_GIGA_MAC_VER_07,
 111         RTL_GIGA_MAC_VER_08,
 112         RTL_GIGA_MAC_VER_09,
 113         RTL_GIGA_MAC_VER_10,
 114         RTL_GIGA_MAC_VER_11,
 115         RTL_GIGA_MAC_VER_12,
 116         RTL_GIGA_MAC_VER_13,
 117         RTL_GIGA_MAC_VER_14,
 118         RTL_GIGA_MAC_VER_15,
 119         RTL_GIGA_MAC_VER_16,
 120         RTL_GIGA_MAC_VER_17,
 121         RTL_GIGA_MAC_VER_18,
 122         RTL_GIGA_MAC_VER_19,
 123         RTL_GIGA_MAC_VER_20,
 124         RTL_GIGA_MAC_VER_21,
 125         RTL_GIGA_MAC_VER_22,
 126         RTL_GIGA_MAC_VER_23,
 127         RTL_GIGA_MAC_VER_24,
 128         RTL_GIGA_MAC_VER_25,
 129         RTL_GIGA_MAC_VER_26,
 130         RTL_GIGA_MAC_VER_27,
 131         RTL_GIGA_MAC_VER_28,
 132         RTL_GIGA_MAC_VER_29,
 133         RTL_GIGA_MAC_VER_30,
 134         RTL_GIGA_MAC_VER_31,
 135         RTL_GIGA_MAC_VER_32,
 136         RTL_GIGA_MAC_VER_33,
 137         RTL_GIGA_MAC_VER_34,
 138         RTL_GIGA_MAC_VER_35,
 139         RTL_GIGA_MAC_VER_36,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 enum rtl_tx_desc_version {
 144         RTL_TD_0        = 0,
 145         RTL_TD_1        = 1,
 146 };
 147
 148 #define JUMBO_1K        ETH_DATA_LEN
 149 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 150 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 151 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 152 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 153
 154 #define _R(NAME,TD,FW,SZ,B) {   \
 155         .name = NAME,           \
 156         .txd_version = TD,      \
 157         .fw_name = FW,          \
 158         .jumbo_max = SZ,        \
 159         .jumbo_tx_csum = B      \
 160 }
 161
 162 static const struct {
 163         const char *name;
 164         enum rtl_tx_desc_version txd_version;
 165         const char *fw_name;
 166         u16 jumbo_max;
 167         bool jumbo_tx_csum;
 168 } rtl_chip_infos[] = {
 169         /* PCI devices. */
 170         [RTL_GIGA_MAC_VER_01] =
 171                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 172         [RTL_GIGA_MAC_VER_02] =
 173                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 174         [RTL_GIGA_MAC_VER_03] =
 175                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_04] =
 177                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_05] =
 179                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_06] =
 181                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 182         /* PCI-E devices. */
 183         [RTL_GIGA_MAC_VER_07] =
 184                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 185         [RTL_GIGA_MAC_VER_08] =
 186                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 187         [RTL_GIGA_MAC_VER_09] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 189         [RTL_GIGA_MAC_VER_10] =
 190                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_11] =
 192                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 193         [RTL_GIGA_MAC_VER_12] =
 194                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 195         [RTL_GIGA_MAC_VER_13] =
 196                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_14] =
 198                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 199         [RTL_GIGA_MAC_VER_15] =
 200                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_16] =
 202                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_17] =
 204                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 205         [RTL_GIGA_MAC_VER_18] =
 206                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 207         [RTL_GIGA_MAC_VER_19] =
 208                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 209         [RTL_GIGA_MAC_VER_20] =
 210                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_21] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_22] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_23] =
 216                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_24] =
 218                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_25] =
 220                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 221                                                         JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_26] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 224                                                         JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_27] =
 226                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 227         [RTL_GIGA_MAC_VER_28] =
 228                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_29] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 231                                                         JUMBO_1K, true),
 232         [RTL_GIGA_MAC_VER_30] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 234                                                         JUMBO_1K, true),
 235         [RTL_GIGA_MAC_VER_31] =
 236                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_32] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 239                                                         JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_33] =
 241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_34] =
 244                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_35] =
 247                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_36] =
 250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 251                                                         JUMBO_9K, false),
 252 };
 253 #undef _R
 254
 255 enum cfg_version {
 256         RTL_CFG_0 = 0x00,
 257         RTL_CFG_1,
 258         RTL_CFG_2
 259 };
 260
 261 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 262         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 263         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 264         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 265         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 266         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 267         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 268         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 269         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 270         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 271         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 272                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 273         { 0x0001,                               0x8168,
 274                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 275         {0,},
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 279
 280 static int rx_buf_sz = 16383;
 281 static int use_dac;
 282 static struct {
 283         u32 msg_enable;
 284 } debug = { -1 };
 285
 286 enum rtl_registers {
 287         MAC0            = 0,    /* Ethernet hardware address. */
 288         MAC4            = 4,
 289         MAR0            = 8,    /* Multicast filter. */
 290         CounterAddrLow          = 0x10,
 291         CounterAddrHigh         = 0x14,
 292         TxDescStartAddrLow      = 0x20,
 293         TxDescStartAddrHigh     = 0x24,
 294         TxHDescStartAddrLow     = 0x28,
 295         TxHDescStartAddrHigh    = 0x2c,
 296         FLASH           = 0x30,
 297         ERSR            = 0x36,
 298         ChipCmd         = 0x37,
 299         TxPoll          = 0x38,
 300         IntrMask        = 0x3c,
 301         IntrStatus      = 0x3e,
 302
 303         TxConfig        = 0x40,
 304 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 305 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 306
 307         RxConfig        = 0x44,
 308 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 309 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 310 #define RXCFG_FIFO_SHIFT                13
 311                                         /* No threshold before first PCI xfer */
 312 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 313 #define RXCFG_DMA_SHIFT                 8
 314                                         /* Unlimited maximum PCI burst. */
 315 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 316
 317         RxMissed        = 0x4c,
 318         Cfg9346         = 0x50,
 319         Config0         = 0x51,
 320         Config1         = 0x52,
 321         Config2         = 0x53,
 322         Config3         = 0x54,
 323         Config4         = 0x55,
 324         Config5         = 0x56,
 325         MultiIntr       = 0x5c,
 326         PHYAR           = 0x60,
 327         PHYstatus       = 0x6c,
 328         RxMaxSize       = 0xda,
 329         CPlusCmd        = 0xe0,
 330         IntrMitigate    = 0xe2,
 331         RxDescAddrLow   = 0xe4,
 332         RxDescAddrHigh  = 0xe8,
 333         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 334
 335 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 336
 337         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 338
 339 #define TxPacketMax     (8064 >> 7)
 340 #define EarlySize       0x27
 341
 342         FuncEvent       = 0xf0,
 343         FuncEventMask   = 0xf4,
 344         FuncPresetState = 0xf8,
 345         FuncForceEvent  = 0xfc,
 346 };
 347
 348 enum rtl8110_registers {
 349         TBICSR                  = 0x64,
 350         TBI_ANAR                = 0x68,
 351         TBI_LPAR                = 0x6a,
 352 };
 353
 354 enum rtl8168_8101_registers {
 355         CSIDR                   = 0x64,
 356         CSIAR                   = 0x68,
 357 #define CSIAR_FLAG                      0x80000000
 358 #define CSIAR_WRITE_CMD                 0x80000000
 359 #define CSIAR_BYTE_ENABLE               0x0f
 360 #define CSIAR_BYTE_ENABLE_SHIFT         12
 361 #define CSIAR_ADDR_MASK                 0x0fff
 362         PMCH                    = 0x6f,
 363         EPHYAR                  = 0x80,
 364 #define EPHYAR_FLAG                     0x80000000
 365 #define EPHYAR_WRITE_CMD                0x80000000
 366 #define EPHYAR_REG_MASK                 0x1f
 367 #define EPHYAR_REG_SHIFT                16
 368 #define EPHYAR_DATA_MASK                0xffff
 369         DLLPR                   = 0xd0,
 370 #define PFM_EN                          (1 << 6)
 371         DBG_REG                 = 0xd1,
 372 #define FIX_NAK_1                       (1 << 4)
 373 #define FIX_NAK_2                       (1 << 3)
 374         TWSI                    = 0xd2,
 375         MCU                     = 0xd3,
 376 #define NOW_IS_OOB                      (1 << 7)
 377 #define EN_NDP                          (1 << 3)
 378 #define EN_OOB_RESET                    (1 << 2)
 379         EFUSEAR                 = 0xdc,
 380 #define EFUSEAR_FLAG                    0x80000000
 381 #define EFUSEAR_WRITE_CMD               0x80000000
 382 #define EFUSEAR_READ_CMD                0x00000000
 383 #define EFUSEAR_REG_MASK                0x03ff
 384 #define EFUSEAR_REG_SHIFT               8
 385 #define EFUSEAR_DATA_MASK               0xff
 386 };
 387
 388 enum rtl8168_registers {
 389         LED_FREQ                = 0x1a,
 390         EEE_LED                 = 0x1b,
 391         ERIDR                   = 0x70,
 392         ERIAR                   = 0x74,
 393 #define ERIAR_FLAG                      0x80000000
 394 #define ERIAR_WRITE_CMD                 0x80000000
 395 #define ERIAR_READ_CMD                  0x00000000
 396 #define ERIAR_ADDR_BYTE_ALIGN           4
 397 #define ERIAR_TYPE_SHIFT                16
 398 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 399 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 400 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 401 #define ERIAR_MASK_SHIFT                12
 402 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 403 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 404 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 405         EPHY_RXER_NUM           = 0x7c,
 406         OCPDR                   = 0xb0, /* OCP GPHY access */
 407 #define OCPDR_WRITE_CMD                 0x80000000
 408 #define OCPDR_READ_CMD                  0x00000000
 409 #define OCPDR_REG_MASK                  0x7f
 410 #define OCPDR_GPHY_REG_SHIFT            16
 411 #define OCPDR_DATA_MASK                 0xffff
 412         OCPAR                   = 0xb4,
 413 #define OCPAR_FLAG                      0x80000000
 414 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 415 #define OCPAR_GPHY_READ_CMD             0x0000f060
 416         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 417         MISC                    = 0xf0, /* 8168e only. */
 418 #define TXPLA_RST                       (1 << 29)
 419 #define PWM_EN                          (1 << 22)
 420 };
 421
 422 enum rtl_register_content {
 423         /* InterruptStatusBits */
 424         SYSErr          = 0x8000,
 425         PCSTimeout      = 0x4000,
 426         SWInt           = 0x0100,
 427         TxDescUnavail   = 0x0080,
 428         RxFIFOOver      = 0x0040,
 429         LinkChg         = 0x0020,
 430         RxOverflow      = 0x0010,
 431         TxErr           = 0x0008,
 432         TxOK            = 0x0004,
 433         RxErr           = 0x0002,
 434         RxOK            = 0x0001,
 435
 436         /* RxStatusDesc */
 437         RxBOVF  = (1 << 24),
 438         RxFOVF  = (1 << 23),
 439         RxRWT   = (1 << 22),
 440         RxRES   = (1 << 21),
 441         RxRUNT  = (1 << 20),
 442         RxCRC   = (1 << 19),
 443
 444         /* ChipCmdBits */
 445         StopReq         = 0x80,
 446         CmdReset        = 0x10,
 447         CmdRxEnb        = 0x08,
 448         CmdTxEnb        = 0x04,
 449         RxBufEmpty      = 0x01,
 450
 451         /* TXPoll register p.5 */
 452         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 453         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 454         FSWInt          = 0x01,         /* Forced software interrupt */
 455
 456         /* Cfg9346Bits */
 457         Cfg9346_Lock    = 0x00,
 458         Cfg9346_Unlock  = 0xc0,
 459
 460         /* rx_mode_bits */
 461         AcceptErr       = 0x20,
 462         AcceptRunt      = 0x10,
 463         AcceptBroadcast = 0x08,
 464         AcceptMulticast = 0x04,
 465         AcceptMyPhys    = 0x02,
 466         AcceptAllPhys   = 0x01,
 467 #define RX_CONFIG_ACCEPT_MASK           0x3f
 468
 469         /* TxConfigBits */
 470         TxInterFrameGapShift = 24,
 471         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 472
 473         /* Config1 register p.24 */
 474         LEDS1           = (1 << 7),
 475         LEDS0           = (1 << 6),
 476         Speed_down      = (1 << 4),
 477         MEMMAP          = (1 << 3),
 478         IOMAP           = (1 << 2),
 479         VPD             = (1 << 1),
 480         PMEnable        = (1 << 0),     /* Power Management Enable */
 481
 482         /* Config2 register p. 25 */
 483         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 484         PCI_Clock_66MHz = 0x01,
 485         PCI_Clock_33MHz = 0x00,
 486
 487         /* Config3 register p.25 */
 488         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 489         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 490         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 491         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 492
 493         /* Config4 register */
 494         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 495
 496         /* Config5 register p.27 */
 497         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 498         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 499         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 500         Spi_en          = (1 << 3),
 501         LanWake         = (1 << 1),     /* LanWake enable/disable */
 502         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 503
 504         /* TBICSR p.28 */
 505         TBIReset        = 0x80000000,
 506         TBILoopback     = 0x40000000,
 507         TBINwEnable     = 0x20000000,
 508         TBINwRestart    = 0x10000000,
 509         TBILinkOk       = 0x02000000,
 510         TBINwComplete   = 0x01000000,
 511
 512         /* CPlusCmd p.31 */
 513         EnableBist      = (1 << 15),    // 8168 8101
 514         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 515         Normal_mode     = (1 << 13),    // unused
 516         Force_half_dup  = (1 << 12),    // 8168 8101
 517         Force_rxflow_en = (1 << 11),    // 8168 8101
 518         Force_txflow_en = (1 << 10),    // 8168 8101
 519         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 520         ASF             = (1 << 8),     // 8168 8101
 521         PktCntrDisable  = (1 << 7),     // 8168 8101
 522         Mac_dbgo_sel    = 0x001c,       // 8168
 523         RxVlan          = (1 << 6),
 524         RxChkSum        = (1 << 5),
 525         PCIDAC          = (1 << 4),
 526         PCIMulRW        = (1 << 3),
 527         INTT_0          = 0x0000,       // 8168
 528         INTT_1          = 0x0001,       // 8168
 529         INTT_2          = 0x0002,       // 8168
 530         INTT_3          = 0x0003,       // 8168
 531
 532         /* rtl8169_PHYstatus */
 533         TBI_Enable      = 0x80,
 534         TxFlowCtrl      = 0x40,
 535         RxFlowCtrl      = 0x20,
 536         _1000bpsF       = 0x10,
 537         _100bps         = 0x08,
 538         _10bps          = 0x04,
 539         LinkStatus      = 0x02,
 540         FullDup         = 0x01,
 541
 542         /* _TBICSRBit */
 543         TBILinkOK       = 0x02000000,
 544
 545         /* DumpCounterCommand */
 546         CounterDump     = 0x8,
 547 };
 548
 549 enum rtl_desc_bit {
 550         /* First doubleword. */
 551         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 552         RingEnd         = (1 << 30), /* End of descriptor ring */
 553         FirstFrag       = (1 << 29), /* First segment of a packet */
 554         LastFrag        = (1 << 28), /* Final segment of a packet */
 555 };
 556
 557 /* Generic case. */
 558 enum rtl_tx_desc_bit {
 559         /* First doubleword. */
 560         TD_LSO          = (1 << 27),            /* Large Send Offload */
 561 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 562
 563         /* Second doubleword. */
 564         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 565 };
 566
 567 /* 8169, 8168b and 810x except 8102e. */
 568 enum rtl_tx_desc_bit_0 {
 569         /* First doubleword. */
 570 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 571         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 572         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 573         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 574 };
 575
 576 /* 8102e, 8168c and beyond. */
 577 enum rtl_tx_desc_bit_1 {
 578         /* Second doubleword. */
 579 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 580         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 581         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 582         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 583 };
 584
 585 static const struct rtl_tx_desc_info {
 586         struct {
 587                 u32 udp;
 588                 u32 tcp;
 589         } checksum;
 590         u16 mss_shift;
 591         u16 opts_offset;
 592 } tx_desc_info [] = {
 593         [RTL_TD_0] = {
 594                 .checksum = {
 595                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 596                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 597                 },
 598                 .mss_shift      = TD0_MSS_SHIFT,
 599                 .opts_offset    = 0
 600         },
 601         [RTL_TD_1] = {
 602                 .checksum = {
 603                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 604                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 605                 },
 606                 .mss_shift      = TD1_MSS_SHIFT,
 607                 .opts_offset    = 1
 608         }
 609 };
 610
 611 enum rtl_rx_desc_bit {
 612         /* Rx private */
 613         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 614         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 615
 616 #define RxProtoUDP      (PID1)
 617 #define RxProtoTCP      (PID0)
 618 #define RxProtoIP       (PID1 | PID0)
 619 #define RxProtoMask     RxProtoIP
 620
 621         IPFail          = (1 << 16), /* IP checksum failed */
 622         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 623         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 624         RxVlanTag       = (1 << 16), /* VLAN tag available */
 625 };
 626
 627 #define RsvdMask        0x3fffc000
 628
 629 struct TxDesc {
 630         __le32 opts1;
 631         __le32 opts2;
 632         __le64 addr;
 633 };
 634
 635 struct RxDesc {
 636         __le32 opts1;
 637         __le32 opts2;
 638         __le64 addr;
 639 };
 640
 641 struct ring_info {
 642         struct sk_buff  *skb;
 643         u32             len;
 644         u8              __pad[sizeof(void *) - sizeof(u32)];
 645 };
 646
 647 enum features {
 648         RTL_FEATURE_WOL         = (1 << 0),
 649         RTL_FEATURE_MSI         = (1 << 1),
 650         RTL_FEATURE_GMII        = (1 << 2),
 651 };
 652
 653 struct rtl8169_counters {
 654         __le64  tx_packets;
 655         __le64  rx_packets;
 656         __le64  tx_errors;
 657         __le32  rx_errors;
 658         __le16  rx_missed;
 659         __le16  align_errors;
 660         __le32  tx_one_collision;
 661         __le32  tx_multi_collision;
 662         __le64  rx_unicast;
 663         __le64  rx_broadcast;
 664         __le32  rx_multicast;
 665         __le16  tx_aborted;
 666         __le16  tx_underun;
 667 };
 668
 669 enum rtl_flag {
 670         RTL_FLAG_TASK_ENABLED,
 671         RTL_FLAG_TASK_SLOW_PENDING,
 672         RTL_FLAG_TASK_RESET_PENDING,
 673         RTL_FLAG_TASK_PHY_PENDING,
 674         RTL_FLAG_MAX
 675 };
 676
 677 struct rtl8169_stats {
 678         u64                     packets;
 679         u64                     bytes;
 680         struct u64_stats_sync   syncp;
 681 };
 682
 683 struct rtl8169_private {
 684         void __iomem *mmio_addr;        /* memory map physical address */
 685         struct pci_dev *pci_dev;
 686         struct net_device *dev;
 687         struct napi_struct napi;
 688         u32 msg_enable;
 689         u16 txd_version;
 690         u16 mac_version;
 691         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 692         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 693         u32 dirty_rx;
 694         u32 dirty_tx;
 695         struct rtl8169_stats rx_stats;
 696         struct rtl8169_stats tx_stats;
 697         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 698         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 699         dma_addr_t TxPhyAddr;
 700         dma_addr_t RxPhyAddr;
 701         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 702         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 703         struct timer_list timer;
 704         u16 cp_cmd;
 705
 706         u16 event_slow;
 707
 708         struct mdio_ops {
 709                 void (*write)(void __iomem *, int, int);
 710                 int (*read)(void __iomem *, int);
 711         } mdio_ops;
 712
 713         struct pll_power_ops {
 714                 void (*down)(struct rtl8169_private *);
 715                 void (*up)(struct rtl8169_private *);
 716         } pll_power_ops;
 717
 718         struct jumbo_ops {
 719                 void (*enable)(struct rtl8169_private *);
 720                 void (*disable)(struct rtl8169_private *);
 721         } jumbo_ops;
 722
 723         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 724         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 725         void (*phy_reset_enable)(struct rtl8169_private *tp);
 726         void (*hw_start)(struct net_device *);
 727         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 728         unsigned int (*link_ok)(void __iomem *);
 729         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 730
 731         struct {
 732                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 733                 struct mutex mutex;
 734                 struct work_struct work;
 735         } wk;
 736
 737         unsigned features;
 738
 739         struct mii_if_info mii;
 740         struct rtl8169_counters counters;
 741         u32 saved_wolopts;
 742         u32 opts1_mask;
 743
 744         struct rtl_fw {
 745                 const struct firmware *fw;
 746
 747 #define RTL_VER_SIZE            32
 748
 749                 char version[RTL_VER_SIZE];
 750
 751                 struct rtl_fw_phy_action {
 752                         __le32 *code;
 753                         size_t size;
 754                 } phy_action;
 755         } *rtl_fw;
 756 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 757 };
 758
 759 static int aspm_disable = 0;
 760 module_param(aspm_disable, bool, 0444);
 761 MODULE_PARM_DESC(aspm_disable, "Disable ASPM completely.");
 762
 763 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 764 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 765 module_param(use_dac, int, 0);
 766 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 767 module_param_named(debug, debug.msg_enable, int, 0);
 768 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 769 MODULE_LICENSE("GPL");
 770 MODULE_VERSION(RTL8169_VERSION);
 771 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 772 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 773 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 774 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 775 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 776 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 777 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 778 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 779
 780 static void rtl_lock_work(struct rtl8169_private *tp)
 781 {
 782         mutex_lock(&tp->wk.mutex);
 783 }
 784
 785 static void rtl_unlock_work(struct rtl8169_private *tp)
 786 {
 787         mutex_unlock(&tp->wk.mutex);
 788 }
 789
 790 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 791 {
 792         int cap = pci_pcie_cap(pdev);
 793
 794         if (cap) {
 795                 u16 ctl;
 796
 797                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 798                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 799                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 800         }
 801 }
 802
 803 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 804 {
 805         void __iomem *ioaddr = tp->mmio_addr;
 806         int i;
 807
 808         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 809         for (i = 0; i < 20; i++) {
 810                 udelay(100);
 811                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 812                         break;
 813         }
 814         return RTL_R32(OCPDR);
 815 }
 816
 817 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 818 {
 819         void __iomem *ioaddr = tp->mmio_addr;
 820         int i;
 821
 822         RTL_W32(OCPDR, data);
 823         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 824         for (i = 0; i < 20; i++) {
 825                 udelay(100);
 826                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 827                         break;
 828         }
 829 }
 830
 831 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 832 {
 833         void __iomem *ioaddr = tp->mmio_addr;
 834         int i;
 835
 836         RTL_W8(ERIDR, cmd);
 837         RTL_W32(ERIAR, 0x800010e8);
 838         msleep(2);
 839         for (i = 0; i < 5; i++) {
 840                 udelay(100);
 841                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 842                         break;
 843         }
 844
 845         ocp_write(tp, 0x1, 0x30, 0x00000001);
 846 }
 847
 848 #define OOB_CMD_RESET           0x00
 849 #define OOB_CMD_DRIVER_START    0x05
 850 #define OOB_CMD_DRIVER_STOP     0x06
 851
 852 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 853 {
 854         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 855 }
 856
 857 static void rtl8168_driver_start(struct rtl8169_private *tp)
 858 {
 859         u16 reg;
 860         int i;
 861
 862         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 863
 864         reg = rtl8168_get_ocp_reg(tp);
 865
 866         for (i = 0; i < 10; i++) {
 867                 msleep(10);
 868                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 869                         break;
 870         }
 871 }
 872
 873 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 874 {
 875         u16 reg;
 876         int i;
 877
 878         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 879
 880         reg = rtl8168_get_ocp_reg(tp);
 881
 882         for (i = 0; i < 10; i++) {
 883                 msleep(10);
 884                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 885                         break;
 886         }
 887 }
 888
 889 static int r8168dp_check_dash(struct rtl8169_private *tp)
 890 {
 891         u16 reg = rtl8168_get_ocp_reg(tp);
 892
 893         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 894 }
 895
 896 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 897 {
 898         int i;
 899
 900         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 901
 902         for (i = 20; i > 0; i--) {
 903                 /*
 904                  * Check if the RTL8169 has completed writing to the specified
 905                  * MII register.
 906                  */
 907                 if (!(RTL_R32(PHYAR) & 0x80000000))
 908                         break;
 909                 udelay(25);
 910         }
 911         /*
 912          * According to hardware specs a 20us delay is required after write
 913          * complete indication, but before sending next command.
 914          */
 915         udelay(20);
 916 }
 917
 918 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 919 {
 920         int i, value = -1;
 921
 922         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 923
 924         for (i = 20; i > 0; i--) {
 925                 /*
 926                  * Check if the RTL8169 has completed retrieving data from
 927                  * the specified MII register.
 928                  */
 929                 if (RTL_R32(PHYAR) & 0x80000000) {
 930                         value = RTL_R32(PHYAR) & 0xffff;
 931                         break;
 932                 }
 933                 udelay(25);
 934         }
 935         /*
 936          * According to hardware specs a 20us delay is required after read
 937          * complete indication, but before sending next command.
 938          */
 939         udelay(20);
 940
 941         return value;
 942 }
 943
 944 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 945 {
 946         int i;
 947
 948         RTL_W32(OCPDR, data |
 949                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 950         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 951         RTL_W32(EPHY_RXER_NUM, 0);
 952
 953         for (i = 0; i < 100; i++) {
 954                 mdelay(1);
 955                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 956                         break;
 957         }
 958 }
 959
 960 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 961 {
 962         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 963                 (value & OCPDR_DATA_MASK));
 964 }
 965
 966 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 967 {
 968         int i;
 969
 970         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 971
 972         mdelay(1);
 973         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 974         RTL_W32(EPHY_RXER_NUM, 0);
 975
 976         for (i = 0; i < 100; i++) {
 977                 mdelay(1);
 978                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 979                         break;
 980         }
 981
 982         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 983 }
 984
 985 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 986
 987 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 988 {
 989         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 990 }
 991
 992 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 993 {
 994         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 995 }
 996
 997 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 998 {
 999         r8168dp_2_mdio_start(ioaddr);
1000
1001         r8169_mdio_write(ioaddr, reg_addr, value);
1002
1003         r8168dp_2_mdio_stop(ioaddr);
1004 }
1005
1006 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
1007 {
1008         int value;
1009
1010         r8168dp_2_mdio_start(ioaddr);
1011
1012         value = r8169_mdio_read(ioaddr, reg_addr);
1013
1014         r8168dp_2_mdio_stop(ioaddr);
1015
1016         return value;
1017 }
1018
1019 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1020 {
1021         tp->mdio_ops.write(tp->mmio_addr, location, val);
1022 }
1023
1024 static int rtl_readphy(struct rtl8169_private *tp, int location)
1025 {
1026         return tp->mdio_ops.read(tp->mmio_addr, location);
1027 }
1028
1029 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1030 {
1031         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1032 }
1033
1034 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1035 {
1036         int val;
1037
1038         val = rtl_readphy(tp, reg_addr);
1039         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1040 }
1041
1042 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1043                            int val)
1044 {
1045         struct rtl8169_private *tp = netdev_priv(dev);
1046
1047         rtl_writephy(tp, location, val);
1048 }
1049
1050 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1051 {
1052         struct rtl8169_private *tp = netdev_priv(dev);
1053
1054         return rtl_readphy(tp, location);
1055 }
1056
1057 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1058 {
1059         unsigned int i;
1060
1061         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1062                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1063
1064         for (i = 0; i < 100; i++) {
1065                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1066                         break;
1067                 udelay(10);
1068         }
1069 }
1070
1071 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1072 {
1073         u16 value = 0xffff;
1074         unsigned int i;
1075
1076         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1077
1078         for (i = 0; i < 100; i++) {
1079                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1080                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1081                         break;
1082                 }
1083                 udelay(10);
1084         }
1085
1086         return value;
1087 }
1088
1089 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1090 {
1091         unsigned int i;
1092
1093         RTL_W32(CSIDR, value);
1094         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1095                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1096
1097         for (i = 0; i < 100; i++) {
1098                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1099                         break;
1100                 udelay(10);
1101         }
1102 }
1103
1104 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1105 {
1106         u32 value = ~0x00;
1107         unsigned int i;
1108
1109         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1110                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1111
1112         for (i = 0; i < 100; i++) {
1113                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1114                         value = RTL_R32(CSIDR);
1115                         break;
1116                 }
1117                 udelay(10);
1118         }
1119
1120         return value;
1121 }
1122
1123 static
1124 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1125 {
1126         unsigned int i;
1127
1128         BUG_ON((addr & 3) || (mask == 0));
1129         RTL_W32(ERIDR, val);
1130         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1131
1132         for (i = 0; i < 100; i++) {
1133                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1134                         break;
1135                 udelay(100);
1136         }
1137 }
1138
1139 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1140 {
1141         u32 value = ~0x00;
1142         unsigned int i;
1143
1144         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1145
1146         for (i = 0; i < 100; i++) {
1147                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1148                         value = RTL_R32(ERIDR);
1149                         break;
1150                 }
1151                 udelay(100);
1152         }
1153
1154         return value;
1155 }
1156
1157 static void
1158 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1159 {
1160         u32 val;
1161
1162         val = rtl_eri_read(ioaddr, addr, type);
1163         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1164 }
1165
1166 struct exgmac_reg {
1167         u16 addr;
1168         u16 mask;
1169         u32 val;
1170 };
1171
1172 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1173                                    const struct exgmac_reg *r, int len)
1174 {
1175         while (len-- > 0) {
1176                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1177                 r++;
1178         }
1179 }
1180
1181 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1182 {
1183         u8 value = 0xff;
1184         unsigned int i;
1185
1186         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1187
1188         for (i = 0; i < 300; i++) {
1189                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1190                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1191                         break;
1192                 }
1193                 udelay(100);
1194         }
1195
1196         return value;
1197 }
1198
1199 static u16 rtl_get_events(struct rtl8169_private *tp)
1200 {
1201         void __iomem *ioaddr = tp->mmio_addr;
1202
1203         return RTL_R16(IntrStatus);
1204 }
1205
1206 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1207 {
1208         void __iomem *ioaddr = tp->mmio_addr;
1209
1210         RTL_W16(IntrStatus, bits);
1211         mmiowb();
1212 }
1213
1214 static void rtl_irq_disable(struct rtl8169_private *tp)
1215 {
1216         void __iomem *ioaddr = tp->mmio_addr;
1217
1218         RTL_W16(IntrMask, 0);
1219         mmiowb();
1220 }
1221
1222 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1223 {
1224         void __iomem *ioaddr = tp->mmio_addr;
1225
1226         RTL_W16(IntrMask, bits);
1227 }
1228
1229 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1230 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1231 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1232
1233 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1234 {
1235         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1236 }
1237
1238 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1239 {
1240         void __iomem *ioaddr = tp->mmio_addr;
1241
1242         rtl_irq_disable(tp);
1243         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1244         RTL_R8(ChipCmd);
1245 }
1246
1247 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1248 {
1249         void __iomem *ioaddr = tp->mmio_addr;
1250
1251         return RTL_R32(TBICSR) & TBIReset;
1252 }
1253
1254 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1255 {
1256         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1257 }
1258
1259 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1260 {
1261         return RTL_R32(TBICSR) & TBILinkOk;
1262 }
1263
1264 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1265 {
1266         return RTL_R8(PHYstatus) & LinkStatus;
1267 }
1268
1269 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1270 {
1271         void __iomem *ioaddr = tp->mmio_addr;
1272
1273         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1274 }
1275
1276 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1277 {
1278         unsigned int val;
1279
1280         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1281         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1282 }
1283
1284 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1285 {
1286         void __iomem *ioaddr = tp->mmio_addr;
1287         struct net_device *dev = tp->dev;
1288
1289         if (!netif_running(dev))
1290                 return;
1291
1292         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1293                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1294                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1295                                       0x00000011, ERIAR_EXGMAC);
1296                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1297                                       0x00000005, ERIAR_EXGMAC);
1298                 } else if (RTL_R8(PHYstatus) & _100bps) {
1299                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1300                                       0x0000001f, ERIAR_EXGMAC);
1301                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1302                                       0x00000005, ERIAR_EXGMAC);
1303                 } else {
1304                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1305                                       0x0000001f, ERIAR_EXGMAC);
1306                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1307                                       0x0000003f, ERIAR_EXGMAC);
1308                 }
1309                 /* Reset packet filter */
1310                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1311                              ERIAR_EXGMAC);
1312                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1313                              ERIAR_EXGMAC);
1314         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1315                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1316                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1317                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1318                                       0x00000011, ERIAR_EXGMAC);
1319                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1320                                       0x00000005, ERIAR_EXGMAC);
1321                 } else {
1322                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1323                                       0x0000001f, ERIAR_EXGMAC);
1324                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1325                                       0x0000003f, ERIAR_EXGMAC);
1326                 }
1327         }
1328 }
1329
1330 static void __rtl8169_check_link_status(struct net_device *dev,
1331                                         struct rtl8169_private *tp,
1332                                         void __iomem *ioaddr, bool pm)
1333 {
1334         if (tp->link_ok(ioaddr)) {
1335                 rtl_link_chg_patch(tp);
1336                 /* This is to cancel a scheduled suspend if there's one. */
1337                 if (pm)
1338                         pm_request_resume(&tp->pci_dev->dev);
1339                 netif_carrier_on(dev);
1340                 if (net_ratelimit())
1341                         netif_info(tp, ifup, dev, "link up\n");
1342         } else {
1343                 netif_carrier_off(dev);
1344                 netif_info(tp, ifdown, dev, "link down\n");
1345                 if (pm)
1346                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1347         }
1348 }
1349
1350 static void rtl8169_check_link_status(struct net_device *dev,
1351                                       struct rtl8169_private *tp,
1352                                       void __iomem *ioaddr)
1353 {
1354         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1355 }
1356
1357 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1358
1359 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1360 {
1361         void __iomem *ioaddr = tp->mmio_addr;
1362         u8 options;
1363         u32 wolopts = 0;
1364
1365         options = RTL_R8(Config1);
1366         if (!(options & PMEnable))
1367                 return 0;
1368
1369         options = RTL_R8(Config3);
1370         if (options & LinkUp)
1371                 wolopts |= WAKE_PHY;
1372         if (options & MagicPacket)
1373                 wolopts |= WAKE_MAGIC;
1374
1375         options = RTL_R8(Config5);
1376         if (options & UWF)
1377                 wolopts |= WAKE_UCAST;
1378         if (options & BWF)
1379                 wolopts |= WAKE_BCAST;
1380         if (options & MWF)
1381                 wolopts |= WAKE_MCAST;
1382
1383         return wolopts;
1384 }
1385
1386 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1387 {
1388         struct rtl8169_private *tp = netdev_priv(dev);
1389
1390         rtl_lock_work(tp);
1391
1392         wol->supported = WAKE_ANY;
1393         wol->wolopts = __rtl8169_get_wol(tp);
1394
1395         rtl_unlock_work(tp);
1396 }
1397
1398 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1399 {
1400         void __iomem *ioaddr = tp->mmio_addr;
1401         unsigned int i;
1402         static const struct {
1403                 u32 opt;
1404                 u16 reg;
1405                 u8  mask;
1406         } cfg[] = {
1407                 { WAKE_ANY,   Config1, PMEnable },
1408                 { WAKE_PHY,   Config3, LinkUp },
1409                 { WAKE_MAGIC, Config3, MagicPacket },
1410                 { WAKE_UCAST, Config5, UWF },
1411                 { WAKE_BCAST, Config5, BWF },
1412                 { WAKE_MCAST, Config5, MWF },
1413                 { WAKE_ANY,   Config5, LanWake }
1414         };
1415
1416         RTL_W8(Cfg9346, Cfg9346_Unlock);
1417
1418         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1419                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1420                 if (wolopts & cfg[i].opt)
1421                         options |= cfg[i].mask;
1422                 RTL_W8(cfg[i].reg, options);
1423         }
1424
1425         RTL_W8(Cfg9346, Cfg9346_Lock);
1426 }
1427
1428 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1429 {
1430         struct rtl8169_private *tp = netdev_priv(dev);
1431
1432         rtl_lock_work(tp);
1433
1434         if (wol->wolopts)
1435                 tp->features |= RTL_FEATURE_WOL;
1436         else
1437                 tp->features &= ~RTL_FEATURE_WOL;
1438         __rtl8169_set_wol(tp, wol->wolopts);
1439
1440         rtl_unlock_work(tp);
1441
1442         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1443
1444         return 0;
1445 }
1446
1447 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1448 {
1449         return rtl_chip_infos[tp->mac_version].fw_name;
1450 }
1451
1452 static void rtl8169_get_drvinfo(struct net_device *dev,
1453                                 struct ethtool_drvinfo *info)
1454 {
1455         struct rtl8169_private *tp = netdev_priv(dev);
1456         struct rtl_fw *rtl_fw = tp->rtl_fw;
1457
1458         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1459         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1460         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1461         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1462         if (!IS_ERR_OR_NULL(rtl_fw))
1463                 strlcpy(info->fw_version, rtl_fw->version,
1464                         sizeof(info->fw_version));
1465 }
1466
1467 static int rtl8169_get_regs_len(struct net_device *dev)
1468 {
1469         return R8169_REGS_SIZE;
1470 }
1471
1472 static int rtl8169_set_speed_tbi(struct net_device *dev,
1473                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1474 {
1475         struct rtl8169_private *tp = netdev_priv(dev);
1476         void __iomem *ioaddr = tp->mmio_addr;
1477         int ret = 0;
1478         u32 reg;
1479
1480         reg = RTL_R32(TBICSR);
1481         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1482             (duplex == DUPLEX_FULL)) {
1483                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1484         } else if (autoneg == AUTONEG_ENABLE)
1485                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1486         else {
1487                 netif_warn(tp, link, dev,
1488                            "incorrect speed setting refused in TBI mode\n");
1489                 ret = -EOPNOTSUPP;
1490         }
1491
1492         return ret;
1493 }
1494
1495 static int rtl8169_set_speed_xmii(struct net_device *dev,
1496                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1497 {
1498         struct rtl8169_private *tp = netdev_priv(dev);
1499         int giga_ctrl, bmcr;
1500         int rc = -EINVAL;
1501
1502         rtl_writephy(tp, 0x1f, 0x0000);
1503
1504         if (autoneg == AUTONEG_ENABLE) {
1505                 int auto_nego;
1506
1507                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1508                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1509                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1510
1511                 if (adv & ADVERTISED_10baseT_Half)
1512                         auto_nego |= ADVERTISE_10HALF;
1513                 if (adv & ADVERTISED_10baseT_Full)
1514                         auto_nego |= ADVERTISE_10FULL;
1515                 if (adv & ADVERTISED_100baseT_Half)
1516                         auto_nego |= ADVERTISE_100HALF;
1517                 if (adv & ADVERTISED_100baseT_Full)
1518                         auto_nego |= ADVERTISE_100FULL;
1519
1520                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1521
1522                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1523                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1524
1525                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1526                 if (tp->mii.supports_gmii) {
1527                         if (adv & ADVERTISED_1000baseT_Half)
1528                                 giga_ctrl |= ADVERTISE_1000HALF;
1529                         if (adv & ADVERTISED_1000baseT_Full)
1530                                 giga_ctrl |= ADVERTISE_1000FULL;
1531                 } else if (adv & (ADVERTISED_1000baseT_Half |
1532                                   ADVERTISED_1000baseT_Full)) {
1533                         netif_info(tp, link, dev,
1534                                    "PHY does not support 1000Mbps\n");
1535                         goto out;
1536                 }
1537
1538                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1539
1540                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1541                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1542         } else {
1543                 giga_ctrl = 0;
1544
1545                 if (speed == SPEED_10)
1546                         bmcr = 0;
1547                 else if (speed == SPEED_100)
1548                         bmcr = BMCR_SPEED100;
1549                 else
1550                         goto out;
1551
1552                 if (duplex == DUPLEX_FULL)
1553                         bmcr |= BMCR_FULLDPLX;
1554         }
1555
1556         rtl_writephy(tp, MII_BMCR, bmcr);
1557
1558         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1559             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1560                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1561                         rtl_writephy(tp, 0x17, 0x2138);
1562                         rtl_writephy(tp, 0x0e, 0x0260);
1563                 } else {
1564                         rtl_writephy(tp, 0x17, 0x2108);
1565                         rtl_writephy(tp, 0x0e, 0x0000);
1566                 }
1567         }
1568
1569         rc = 0;
1570 out:
1571         return rc;
1572 }
1573
1574 static int rtl8169_set_speed(struct net_device *dev,
1575                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1576 {
1577         struct rtl8169_private *tp = netdev_priv(dev);
1578         int ret;
1579
1580         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1581         if (ret < 0)
1582                 goto out;
1583
1584         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1585             (advertising & ADVERTISED_1000baseT_Full)) {
1586                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1587         }
1588 out:
1589         return ret;
1590 }
1591
1592 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1593 {
1594         struct rtl8169_private *tp = netdev_priv(dev);
1595         int ret;
1596
1597         del_timer_sync(&tp->timer);
1598
1599         rtl_lock_work(tp);
1600         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1601                                 cmd->duplex, cmd->advertising);
1602         rtl_unlock_work(tp);
1603
1604         return ret;
1605 }
1606
1607 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1608         netdev_features_t features)
1609 {
1610         struct rtl8169_private *tp = netdev_priv(dev);
1611
1612         if (dev->mtu > TD_MSS_MAX)
1613                 features &= ~NETIF_F_ALL_TSO;
1614
1615         if (dev->mtu > JUMBO_1K &&
1616             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1617                 features &= ~NETIF_F_IP_CSUM;
1618
1619         return features;
1620 }
1621
1622 static void __rtl8169_set_features(struct net_device *dev,
1623                                    netdev_features_t features)
1624 {
1625         struct rtl8169_private *tp = netdev_priv(dev);
1626         netdev_features_t changed = features ^ dev->features;
1627         void __iomem *ioaddr = tp->mmio_addr;
1628
1629         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
1630                 return;
1631
1632         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
1633                 if (features & NETIF_F_RXCSUM)
1634                         tp->cp_cmd |= RxChkSum;
1635                 else
1636                         tp->cp_cmd &= ~RxChkSum;
1637
1638                 if (dev->features & NETIF_F_HW_VLAN_RX)
1639                         tp->cp_cmd |= RxVlan;
1640                 else
1641                         tp->cp_cmd &= ~RxVlan;
1642
1643                 RTL_W16(CPlusCmd, tp->cp_cmd);
1644                 RTL_R16(CPlusCmd);
1645         }
1646         if (changed & NETIF_F_RXALL) {
1647                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1648                 if (features & NETIF_F_RXALL)
1649                         tmp |= (AcceptErr | AcceptRunt);
1650                 RTL_W32(RxConfig, tmp);
1651         }
1652 }
1653
1654 static int rtl8169_set_features(struct net_device *dev,
1655                                 netdev_features_t features)
1656 {
1657         struct rtl8169_private *tp = netdev_priv(dev);
1658
1659         rtl_lock_work(tp);
1660         __rtl8169_set_features(dev, features);
1661         rtl_unlock_work(tp);
1662
1663         return 0;
1664 }
1665
1666
1667 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1668                                       struct sk_buff *skb)
1669 {
1670         return (vlan_tx_tag_present(skb)) ?
1671                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1672 }
1673
1674 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1675 {
1676         u32 opts2 = le32_to_cpu(desc->opts2);
1677
1678         if (opts2 & RxVlanTag)
1679                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1680
1681         desc->opts2 = 0;
1682 }
1683
1684 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1685 {
1686         struct rtl8169_private *tp = netdev_priv(dev);
1687         void __iomem *ioaddr = tp->mmio_addr;
1688         u32 status;
1689
1690         cmd->supported =
1691                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1692         cmd->port = PORT_FIBRE;
1693         cmd->transceiver = XCVR_INTERNAL;
1694
1695         status = RTL_R32(TBICSR);
1696         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1697         cmd->autoneg = !!(status & TBINwEnable);
1698
1699         ethtool_cmd_speed_set(cmd, SPEED_1000);
1700         cmd->duplex = DUPLEX_FULL; /* Always set */
1701
1702         return 0;
1703 }
1704
1705 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1706 {
1707         struct rtl8169_private *tp = netdev_priv(dev);
1708
1709         return mii_ethtool_gset(&tp->mii, cmd);
1710 }
1711
1712 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1713 {
1714         struct rtl8169_private *tp = netdev_priv(dev);
1715         int rc;
1716
1717         rtl_lock_work(tp);
1718         rc = tp->get_settings(dev, cmd);
1719         rtl_unlock_work(tp);
1720
1721         return rc;
1722 }
1723
1724 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1725                              void *p)
1726 {
1727         struct rtl8169_private *tp = netdev_priv(dev);
1728
1729         if (regs->len > R8169_REGS_SIZE)
1730                 regs->len = R8169_REGS_SIZE;
1731
1732         rtl_lock_work(tp);
1733         memcpy_fromio(p, tp->mmio_addr, regs->len);
1734         rtl_unlock_work(tp);
1735 }
1736
1737 static u32 rtl8169_get_msglevel(struct net_device *dev)
1738 {
1739         struct rtl8169_private *tp = netdev_priv(dev);
1740
1741         return tp->msg_enable;
1742 }
1743
1744 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1745 {
1746         struct rtl8169_private *tp = netdev_priv(dev);
1747
1748         tp->msg_enable = value;
1749 }
1750
1751 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1752         "tx_packets",
1753         "rx_packets",
1754         "tx_errors",
1755         "rx_errors",
1756         "rx_missed",
1757         "align_errors",
1758         "tx_single_collisions",
1759         "tx_multi_collisions",
1760         "unicast",
1761         "broadcast",
1762         "multicast",
1763         "tx_aborted",
1764         "tx_underrun",
1765 };
1766
1767 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1768 {
1769         switch (sset) {
1770         case ETH_SS_STATS:
1771                 return ARRAY_SIZE(rtl8169_gstrings);
1772         default:
1773                 return -EOPNOTSUPP;
1774         }
1775 }
1776
1777 static void rtl8169_update_counters(struct net_device *dev)
1778 {
1779         struct rtl8169_private *tp = netdev_priv(dev);
1780         void __iomem *ioaddr = tp->mmio_addr;
1781         struct device *d = &tp->pci_dev->dev;
1782         struct rtl8169_counters *counters;
1783         dma_addr_t paddr;
1784         u32 cmd;
1785         int wait = 1000;
1786
1787         /*
1788          * Some chips are unable to dump tally counters when the receiver
1789          * is disabled.
1790          */
1791         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1792                 return;
1793
1794         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1795         if (!counters)
1796                 return;
1797
1798         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1799         cmd = (u64)paddr & DMA_BIT_MASK(32);
1800         RTL_W32(CounterAddrLow, cmd);
1801         RTL_W32(CounterAddrLow, cmd | CounterDump);
1802
1803         while (wait--) {
1804                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1805                         memcpy(&tp->counters, counters, sizeof(*counters));
1806                         break;
1807                 }
1808                 udelay(10);
1809         }
1810
1811         RTL_W32(CounterAddrLow, 0);
1812         RTL_W32(CounterAddrHigh, 0);
1813
1814         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1815 }
1816
1817 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1818                                       struct ethtool_stats *stats, u64 *data)
1819 {
1820         struct rtl8169_private *tp = netdev_priv(dev);
1821
1822         ASSERT_RTNL();
1823
1824         rtl8169_update_counters(dev);
1825
1826         data[0] = le64_to_cpu(tp->counters.tx_packets);
1827         data[1] = le64_to_cpu(tp->counters.rx_packets);
1828         data[2] = le64_to_cpu(tp->counters.tx_errors);
1829         data[3] = le32_to_cpu(tp->counters.rx_errors);
1830         data[4] = le16_to_cpu(tp->counters.rx_missed);
1831         data[5] = le16_to_cpu(tp->counters.align_errors);
1832         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1833         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1834         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1835         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1836         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1837         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1838         data[12] = le16_to_cpu(tp->counters.tx_underun);
1839 }
1840
1841 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1842 {
1843         switch(stringset) {
1844         case ETH_SS_STATS:
1845                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1846                 break;
1847         }
1848 }
1849
1850 static const struct ethtool_ops rtl8169_ethtool_ops = {
1851         .get_drvinfo            = rtl8169_get_drvinfo,
1852         .get_regs_len           = rtl8169_get_regs_len,
1853         .get_link               = ethtool_op_get_link,
1854         .get_settings           = rtl8169_get_settings,
1855         .set_settings           = rtl8169_set_settings,
1856         .get_msglevel           = rtl8169_get_msglevel,
1857         .set_msglevel           = rtl8169_set_msglevel,
1858         .get_regs               = rtl8169_get_regs,
1859         .get_wol                = rtl8169_get_wol,
1860         .set_wol                = rtl8169_set_wol,
1861         .get_strings            = rtl8169_get_strings,
1862         .get_sset_count         = rtl8169_get_sset_count,
1863         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1864 };
1865
1866 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1867                                     struct net_device *dev, u8 default_version)
1868 {
1869         void __iomem *ioaddr = tp->mmio_addr;
1870         /*
1871          * The driver currently handles the 8168Bf and the 8168Be identically
1872          * but they can be identified more specifically through the test below
1873          * if needed:
1874          *
1875          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1876          *
1877          * Same thing for the 8101Eb and the 8101Ec:
1878          *
1879          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1880          */
1881         static const struct rtl_mac_info {
1882                 u32 mask;
1883                 u32 val;
1884                 int mac_version;
1885         } mac_info[] = {
1886                 /* 8168F family. */
1887                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1888                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1889
1890                 /* 8168E family. */
1891                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1892                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1893                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1894                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1895
1896                 /* 8168D family. */
1897                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1898                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1899                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1900
1901                 /* 8168DP family. */
1902                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1903                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1904                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1905
1906                 /* 8168C family. */
1907                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1908                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1909                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1910                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1911                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1912                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1913                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1914                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1915                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1916
1917                 /* 8168B family. */
1918                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1919                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1920                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1921                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1922
1923                 /* 8101 family. */
1924                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1925                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1926                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1927                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1928                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1929                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1930                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1931                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1932                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1933                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1934                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1935                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1936                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1937                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1938                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1939                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1940                 /* FIXME: where did these entries come from ? -- FR */
1941                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1942                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1943
1944                 /* 8110 family. */
1945                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1946                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1947                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1948                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1949                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1950                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1951
1952                 /* Catch-all */
1953                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1954         };
1955         const struct rtl_mac_info *p = mac_info;
1956         u32 reg;
1957
1958         reg = RTL_R32(TxConfig);
1959         while ((reg & p->mask) != p->val)
1960                 p++;
1961         tp->mac_version = p->mac_version;
1962
1963         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1964                 netif_notice(tp, probe, dev,
1965                              "unknown MAC, using family default\n");
1966                 tp->mac_version = default_version;
1967         }
1968 }
1969
1970 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1971 {
1972         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1973 }
1974
1975 struct phy_reg {
1976         u16 reg;
1977         u16 val;
1978 };
1979
1980 static void rtl_writephy_batch(struct rtl8169_private *tp,
1981                                const struct phy_reg *regs, int len)
1982 {
1983         while (len-- > 0) {
1984                 rtl_writephy(tp, regs->reg, regs->val);
1985                 regs++;
1986         }
1987 }
1988
1989 #define PHY_READ                0x00000000
1990 #define PHY_DATA_OR             0x10000000
1991 #define PHY_DATA_AND            0x20000000
1992 #define PHY_BJMPN               0x30000000
1993 #define PHY_READ_EFUSE          0x40000000
1994 #define PHY_READ_MAC_BYTE       0x50000000
1995 #define PHY_WRITE_MAC_BYTE      0x60000000
1996 #define PHY_CLEAR_READCOUNT     0x70000000
1997 #define PHY_WRITE               0x80000000
1998 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1999 #define PHY_COMP_EQ_SKIPN       0xa0000000
2000 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2001 #define PHY_WRITE_PREVIOUS      0xc0000000
2002 #define PHY_SKIPN               0xd0000000
2003 #define PHY_DELAY_MS            0xe0000000
2004 #define PHY_WRITE_ERI_WORD      0xf0000000
2005
2006 struct fw_info {
2007         u32     magic;
2008         char    version[RTL_VER_SIZE];
2009         __le32  fw_start;
2010         __le32  fw_len;
2011         u8      chksum;
2012 } __packed;
2013
2014 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2015
2016 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2017 {
2018         const struct firmware *fw = rtl_fw->fw;
2019         struct fw_info *fw_info = (struct fw_info *)fw->data;
2020         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2021         char *version = rtl_fw->version;
2022         bool rc = false;
2023
2024         if (fw->size < FW_OPCODE_SIZE)
2025                 goto out;
2026
2027         if (!fw_info->magic) {
2028                 size_t i, size, start;
2029                 u8 checksum = 0;
2030
2031                 if (fw->size < sizeof(*fw_info))
2032                         goto out;
2033
2034                 for (i = 0; i < fw->size; i++)
2035                         checksum += fw->data[i];
2036                 if (checksum != 0)
2037                         goto out;
2038
2039                 start = le32_to_cpu(fw_info->fw_start);
2040                 if (start > fw->size)
2041                         goto out;
2042
2043                 size = le32_to_cpu(fw_info->fw_len);
2044                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2045                         goto out;
2046
2047                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2048
2049                 pa->code = (__le32 *)(fw->data + start);
2050                 pa->size = size;
2051         } else {
2052                 if (fw->size % FW_OPCODE_SIZE)
2053                         goto out;
2054
2055                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2056
2057                 pa->code = (__le32 *)fw->data;
2058                 pa->size = fw->size / FW_OPCODE_SIZE;
2059         }
2060         version[RTL_VER_SIZE - 1] = 0;
2061
2062         rc = true;
2063 out:
2064         return rc;
2065 }
2066
2067 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2068                            struct rtl_fw_phy_action *pa)
2069 {
2070         bool rc = false;
2071         size_t index;
2072
2073         for (index = 0; index < pa->size; index++) {
2074                 u32 action = le32_to_cpu(pa->code[index]);
2075                 u32 regno = (action & 0x0fff0000) >> 16;
2076
2077                 switch(action & 0xf0000000) {
2078                 case PHY_READ:
2079                 case PHY_DATA_OR:
2080                 case PHY_DATA_AND:
2081                 case PHY_READ_EFUSE:
2082                 case PHY_CLEAR_READCOUNT:
2083                 case PHY_WRITE:
2084                 case PHY_WRITE_PREVIOUS:
2085                 case PHY_DELAY_MS:
2086                         break;
2087
2088                 case PHY_BJMPN:
2089                         if (regno > index) {
2090                                 netif_err(tp, ifup, tp->dev,
2091                                           "Out of range of firmware\n");
2092                                 goto out;
2093                         }
2094                         break;
2095                 case PHY_READCOUNT_EQ_SKIP:
2096                         if (index + 2 >= pa->size) {
2097                                 netif_err(tp, ifup, tp->dev,
2098                                           "Out of range of firmware\n");
2099                                 goto out;
2100                         }
2101                         break;
2102                 case PHY_COMP_EQ_SKIPN:
2103                 case PHY_COMP_NEQ_SKIPN:
2104                 case PHY_SKIPN:
2105                         if (index + 1 + regno >= pa->size) {
2106                                 netif_err(tp, ifup, tp->dev,
2107                                           "Out of range of firmware\n");
2108                                 goto out;
2109                         }
2110                         break;
2111
2112                 case PHY_READ_MAC_BYTE:
2113                 case PHY_WRITE_MAC_BYTE:
2114                 case PHY_WRITE_ERI_WORD:
2115                 default:
2116                         netif_err(tp, ifup, tp->dev,
2117                                   "Invalid action 0x%08x\n", action);
2118                         goto out;
2119                 }
2120         }
2121         rc = true;
2122 out:
2123         return rc;
2124 }
2125
2126 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2127 {
2128         struct net_device *dev = tp->dev;
2129         int rc = -EINVAL;
2130
2131         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2132                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2133                 goto out;
2134         }
2135
2136         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2137                 rc = 0;
2138 out:
2139         return rc;
2140 }
2141
2142 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2143 {
2144         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2145         u32 predata, count;
2146         size_t index;
2147
2148         predata = count = 0;
2149
2150         for (index = 0; index < pa->size; ) {
2151                 u32 action = le32_to_cpu(pa->code[index]);
2152                 u32 data = action & 0x0000ffff;
2153                 u32 regno = (action & 0x0fff0000) >> 16;
2154
2155                 if (!action)
2156                         break;
2157
2158                 switch(action & 0xf0000000) {
2159                 case PHY_READ:
2160                         predata = rtl_readphy(tp, regno);
2161                         count++;
2162                         index++;
2163                         break;
2164                 case PHY_DATA_OR:
2165                         predata |= data;
2166                         index++;
2167                         break;
2168                 case PHY_DATA_AND:
2169                         predata &= data;
2170                         index++;
2171                         break;
2172                 case PHY_BJMPN:
2173                         index -= regno;
2174                         break;
2175                 case PHY_READ_EFUSE:
2176                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2177                         index++;
2178                         break;
2179                 case PHY_CLEAR_READCOUNT:
2180                         count = 0;
2181                         index++;
2182                         break;
2183                 case PHY_WRITE:
2184                         rtl_writephy(tp, regno, data);
2185                         index++;
2186                         break;
2187                 case PHY_READCOUNT_EQ_SKIP:
2188                         index += (count == data) ? 2 : 1;
2189                         break;
2190                 case PHY_COMP_EQ_SKIPN:
2191                         if (predata == data)
2192                                 index += regno;
2193                         index++;
2194                         break;
2195                 case PHY_COMP_NEQ_SKIPN:
2196                         if (predata != data)
2197                                 index += regno;
2198                         index++;
2199                         break;
2200                 case PHY_WRITE_PREVIOUS:
2201                         rtl_writephy(tp, regno, predata);
2202                         index++;
2203                         break;
2204                 case PHY_SKIPN:
2205                         index += regno + 1;
2206                         break;
2207                 case PHY_DELAY_MS:
2208                         mdelay(data);
2209                         index++;
2210                         break;
2211
2212                 case PHY_READ_MAC_BYTE:
2213                 case PHY_WRITE_MAC_BYTE:
2214                 case PHY_WRITE_ERI_WORD:
2215                 default:
2216                         BUG();
2217                 }
2218         }
2219 }
2220
2221 static void rtl_release_firmware(struct rtl8169_private *tp)
2222 {
2223         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2224                 release_firmware(tp->rtl_fw->fw);
2225                 kfree(tp->rtl_fw);
2226         }
2227         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2228 }
2229
2230 static void rtl_apply_firmware(struct rtl8169_private *tp)
2231 {
2232         struct rtl_fw *rtl_fw = tp->rtl_fw;
2233
2234         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2235         if (!IS_ERR_OR_NULL(rtl_fw))
2236                 rtl_phy_write_fw(tp, rtl_fw);
2237 }
2238
2239 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2240 {
2241         if (rtl_readphy(tp, reg) != val)
2242                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2243         else
2244                 rtl_apply_firmware(tp);
2245 }
2246
2247 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2248 {
2249         static const struct phy_reg phy_reg_init[] = {
2250                 { 0x1f, 0x0001 },
2251                 { 0x06, 0x006e },
2252                 { 0x08, 0x0708 },
2253                 { 0x15, 0x4000 },
2254                 { 0x18, 0x65c7 },
2255
2256                 { 0x1f, 0x0001 },
2257                 { 0x03, 0x00a1 },
2258                 { 0x02, 0x0008 },
2259                 { 0x01, 0x0120 },
2260                 { 0x00, 0x1000 },
2261                 { 0x04, 0x0800 },
2262                 { 0x04, 0x0000 },
2263
2264                 { 0x03, 0xff41 },
2265                 { 0x02, 0xdf60 },
2266                 { 0x01, 0x0140 },
2267                 { 0x00, 0x0077 },
2268                 { 0x04, 0x7800 },
2269                 { 0x04, 0x7000 },
2270
2271                 { 0x03, 0x802f },
2272                 { 0x02, 0x4f02 },
2273                 { 0x01, 0x0409 },
2274                 { 0x00, 0xf0f9 },
2275                 { 0x04, 0x9800 },
2276                 { 0x04, 0x9000 },
2277
2278                 { 0x03, 0xdf01 },
2279                 { 0x02, 0xdf20 },
2280                 { 0x01, 0xff95 },
2281                 { 0x00, 0xba00 },
2282                 { 0x04, 0xa800 },
2283                 { 0x04, 0xa000 },
2284
2285                 { 0x03, 0xff41 },
2286                 { 0x02, 0xdf20 },
2287                 { 0x01, 0x0140 },
2288                 { 0x00, 0x00bb },
2289                 { 0x04, 0xb800 },
2290                 { 0x04, 0xb000 },
2291
2292                 { 0x03, 0xdf41 },
2293                 { 0x02, 0xdc60 },
2294                 { 0x01, 0x6340 },
2295                 { 0x00, 0x007d },
2296                 { 0x04, 0xd800 },
2297                 { 0x04, 0xd000 },
2298
2299                 { 0x03, 0xdf01 },
2300                 { 0x02, 0xdf20 },
2301                 { 0x01, 0x100a },
2302                 { 0x00, 0xa0ff },
2303                 { 0x04, 0xf800 },
2304                 { 0x04, 0xf000 },
2305
2306                 { 0x1f, 0x0000 },
2307                 { 0x0b, 0x0000 },
2308                 { 0x00, 0x9200 }
2309         };
2310
2311         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2312 }
2313
2314 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2315 {
2316         static const struct phy_reg phy_reg_init[] = {
2317                 { 0x1f, 0x0002 },
2318                 { 0x01, 0x90d0 },
2319                 { 0x1f, 0x0000 }
2320         };
2321
2322         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2323 }
2324
2325 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2326 {
2327         struct pci_dev *pdev = tp->pci_dev;
2328
2329         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2330             (pdev->subsystem_device != 0xe000))
2331                 return;
2332
2333         rtl_writephy(tp, 0x1f, 0x0001);
2334         rtl_writephy(tp, 0x10, 0xf01b);
2335         rtl_writephy(tp, 0x1f, 0x0000);
2336 }
2337
2338 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2339 {
2340         static const struct phy_reg phy_reg_init[] = {
2341                 { 0x1f, 0x0001 },
2342                 { 0x04, 0x0000 },
2343                 { 0x03, 0x00a1 },
2344                 { 0x02, 0x0008 },
2345                 { 0x01, 0x0120 },
2346                 { 0x00, 0x1000 },
2347                 { 0x04, 0x0800 },
2348                 { 0x04, 0x9000 },
2349                 { 0x03, 0x802f },
2350                 { 0x02, 0x4f02 },
2351                 { 0x01, 0x0409 },
2352                 { 0x00, 0xf099 },
2353                 { 0x04, 0x9800 },
2354                 { 0x04, 0xa000 },
2355                 { 0x03, 0xdf01 },
2356                 { 0x02, 0xdf20 },
2357                 { 0x01, 0xff95 },
2358                 { 0x00, 0xba00 },
2359                 { 0x04, 0xa800 },
2360                 { 0x04, 0xf000 },
2361                 { 0x03, 0xdf01 },
2362                 { 0x02, 0xdf20 },
2363                 { 0x01, 0x101a },
2364                 { 0x00, 0xa0ff },
2365                 { 0x04, 0xf800 },
2366                 { 0x04, 0x0000 },
2367                 { 0x1f, 0x0000 },
2368
2369                 { 0x1f, 0x0001 },
2370                 { 0x10, 0xf41b },
2371                 { 0x14, 0xfb54 },
2372                 { 0x18, 0xf5c7 },
2373                 { 0x1f, 0x0000 },
2374
2375                 { 0x1f, 0x0001 },
2376                 { 0x17, 0x0cc0 },
2377                 { 0x1f, 0x0000 }
2378         };
2379
2380         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2381
2382         rtl8169scd_hw_phy_config_quirk(tp);
2383 }
2384
2385 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2386 {
2387         static const struct phy_reg phy_reg_init[] = {
2388                 { 0x1f, 0x0001 },
2389                 { 0x04, 0x0000 },
2390                 { 0x03, 0x00a1 },
2391                 { 0x02, 0x0008 },
2392                 { 0x01, 0x0120 },
2393                 { 0x00, 0x1000 },
2394                 { 0x04, 0x0800 },
2395                 { 0x04, 0x9000 },
2396                 { 0x03, 0x802f },
2397                 { 0x02, 0x4f02 },
2398                 { 0x01, 0x0409 },
2399                 { 0x00, 0xf099 },
2400                 { 0x04, 0x9800 },
2401                 { 0x04, 0xa000 },
2402                 { 0x03, 0xdf01 },
2403                 { 0x02, 0xdf20 },
2404                 { 0x01, 0xff95 },
2405                 { 0x00, 0xba00 },
2406                 { 0x04, 0xa800 },
2407                 { 0x04, 0xf000 },
2408                 { 0x03, 0xdf01 },
2409                 { 0x02, 0xdf20 },
2410                 { 0x01, 0x101a },
2411                 { 0x00, 0xa0ff },
2412                 { 0x04, 0xf800 },
2413                 { 0x04, 0x0000 },
2414                 { 0x1f, 0x0000 },
2415
2416                 { 0x1f, 0x0001 },
2417                 { 0x0b, 0x8480 },
2418                 { 0x1f, 0x0000 },
2419
2420                 { 0x1f, 0x0001 },
2421                 { 0x18, 0x67c7 },
2422                 { 0x04, 0x2000 },
2423                 { 0x03, 0x002f },
2424                 { 0x02, 0x4360 },
2425                 { 0x01, 0x0109 },
2426                 { 0x00, 0x3022 },
2427                 { 0x04, 0x2800 },
2428                 { 0x1f, 0x0000 },
2429
2430                 { 0x1f, 0x0001 },
2431                 { 0x17, 0x0cc0 },
2432                 { 0x1f, 0x0000 }
2433         };
2434
2435         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2436 }
2437
2438 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2439 {
2440         static const struct phy_reg phy_reg_init[] = {
2441                 { 0x10, 0xf41b },
2442                 { 0x1f, 0x0000 }
2443         };
2444
2445         rtl_writephy(tp, 0x1f, 0x0001);
2446         rtl_patchphy(tp, 0x16, 1 << 0);
2447
2448         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2449 }
2450
2451 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2452 {
2453         static const struct phy_reg phy_reg_init[] = {
2454                 { 0x1f, 0x0001 },
2455                 { 0x10, 0xf41b },
2456                 { 0x1f, 0x0000 }
2457         };
2458
2459         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2460 }
2461
2462 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2463 {
2464         static const struct phy_reg phy_reg_init[] = {
2465                 { 0x1f, 0x0000 },
2466                 { 0x1d, 0x0f00 },
2467                 { 0x1f, 0x0002 },
2468                 { 0x0c, 0x1ec8 },
2469                 { 0x1f, 0x0000 }
2470         };
2471
2472         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2473 }
2474
2475 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2476 {
2477         static const struct phy_reg phy_reg_init[] = {
2478                 { 0x1f, 0x0001 },
2479                 { 0x1d, 0x3d98 },
2480                 { 0x1f, 0x0000 }
2481         };
2482
2483         rtl_writephy(tp, 0x1f, 0x0000);
2484         rtl_patchphy(tp, 0x14, 1 << 5);
2485         rtl_patchphy(tp, 0x0d, 1 << 5);
2486
2487         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2488 }
2489
2490 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2491 {
2492         static const struct phy_reg phy_reg_init[] = {
2493                 { 0x1f, 0x0001 },
2494                 { 0x12, 0x2300 },
2495                 { 0x1f, 0x0002 },
2496                 { 0x00, 0x88d4 },
2497                 { 0x01, 0x82b1 },
2498                 { 0x03, 0x7002 },
2499                 { 0x08, 0x9e30 },
2500                 { 0x09, 0x01f0 },
2501                 { 0x0a, 0x5500 },
2502                 { 0x0c, 0x00c8 },
2503                 { 0x1f, 0x0003 },
2504                 { 0x12, 0xc096 },
2505                 { 0x16, 0x000a },
2506                 { 0x1f, 0x0000 },
2507                 { 0x1f, 0x0000 },
2508                 { 0x09, 0x2000 },
2509                 { 0x09, 0x0000 }
2510         };
2511
2512         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2513
2514         rtl_patchphy(tp, 0x14, 1 << 5);
2515         rtl_patchphy(tp, 0x0d, 1 << 5);
2516         rtl_writephy(tp, 0x1f, 0x0000);
2517 }
2518
2519 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2520 {
2521         static const struct phy_reg phy_reg_init[] = {
2522                 { 0x1f, 0x0001 },
2523                 { 0x12, 0x2300 },
2524                 { 0x03, 0x802f },
2525                 { 0x02, 0x4f02 },
2526                 { 0x01, 0x0409 },
2527                 { 0x00, 0xf099 },
2528                 { 0x04, 0x9800 },
2529                 { 0x04, 0x9000 },
2530                 { 0x1d, 0x3d98 },
2531                 { 0x1f, 0x0002 },
2532                 { 0x0c, 0x7eb8 },
2533                 { 0x06, 0x0761 },
2534                 { 0x1f, 0x0003 },
2535                 { 0x16, 0x0f0a },
2536                 { 0x1f, 0x0000 }
2537         };
2538
2539         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2540
2541         rtl_patchphy(tp, 0x16, 1 << 0);
2542         rtl_patchphy(tp, 0x14, 1 << 5);
2543         rtl_patchphy(tp, 0x0d, 1 << 5);
2544         rtl_writephy(tp, 0x1f, 0x0000);
2545 }
2546
2547 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2548 {
2549         static const struct phy_reg phy_reg_init[] = {
2550                 { 0x1f, 0x0001 },
2551                 { 0x12, 0x2300 },
2552                 { 0x1d, 0x3d98 },
2553                 { 0x1f, 0x0002 },
2554                 { 0x0c, 0x7eb8 },
2555                 { 0x06, 0x5461 },
2556                 { 0x1f, 0x0003 },
2557                 { 0x16, 0x0f0a },
2558                 { 0x1f, 0x0000 }
2559         };
2560
2561         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2562
2563         rtl_patchphy(tp, 0x16, 1 << 0);
2564         rtl_patchphy(tp, 0x14, 1 << 5);
2565         rtl_patchphy(tp, 0x0d, 1 << 5);
2566         rtl_writephy(tp, 0x1f, 0x0000);
2567 }
2568
2569 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2570 {
2571         rtl8168c_3_hw_phy_config(tp);
2572 }
2573
2574 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2575 {
2576         static const struct phy_reg phy_reg_init_0[] = {
2577                 /* Channel Estimation */
2578                 { 0x1f, 0x0001 },
2579                 { 0x06, 0x4064 },
2580                 { 0x07, 0x2863 },
2581                 { 0x08, 0x059c },
2582                 { 0x09, 0x26b4 },
2583                 { 0x0a, 0x6a19 },
2584                 { 0x0b, 0xdcc8 },
2585                 { 0x10, 0xf06d },
2586                 { 0x14, 0x7f68 },
2587                 { 0x18, 0x7fd9 },
2588                 { 0x1c, 0xf0ff },
2589                 { 0x1d, 0x3d9c },
2590                 { 0x1f, 0x0003 },
2591                 { 0x12, 0xf49f },
2592                 { 0x13, 0x070b },
2593                 { 0x1a, 0x05ad },
2594                 { 0x14, 0x94c0 },
2595
2596                 /*
2597                  * Tx Error Issue
2598                  * Enhance line driver power
2599                  */
2600                 { 0x1f, 0x0002 },
2601                 { 0x06, 0x5561 },
2602                 { 0x1f, 0x0005 },
2603                 { 0x05, 0x8332 },
2604                 { 0x06, 0x5561 },
2605
2606                 /*
2607                  * Can not link to 1Gbps with bad cable
2608                  * Decrease SNR threshold form 21.07dB to 19.04dB
2609                  */
2610                 { 0x1f, 0x0001 },
2611                 { 0x17, 0x0cc0 },
2612
2613                 { 0x1f, 0x0000 },
2614                 { 0x0d, 0xf880 }
2615         };
2616         void __iomem *ioaddr = tp->mmio_addr;
2617
2618         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2619
2620         /*
2621          * Rx Error Issue
2622          * Fine Tune Switching regulator parameter
2623          */
2624         rtl_writephy(tp, 0x1f, 0x0002);
2625         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2626         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2627
2628         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2629                 static const struct phy_reg phy_reg_init[] = {
2630                         { 0x1f, 0x0002 },
2631                         { 0x05, 0x669a },
2632                         { 0x1f, 0x0005 },
2633                         { 0x05, 0x8330 },
2634                         { 0x06, 0x669a },
2635                         { 0x1f, 0x0002 }
2636                 };
2637                 int val;
2638
2639                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2640
2641                 val = rtl_readphy(tp, 0x0d);
2642
2643                 if ((val & 0x00ff) != 0x006c) {
2644                         static const u32 set[] = {
2645                                 0x0065, 0x0066, 0x0067, 0x0068,
2646                                 0x0069, 0x006a, 0x006b, 0x006c
2647                         };
2648                         int i;
2649
2650                         rtl_writephy(tp, 0x1f, 0x0002);
2651
2652                         val &= 0xff00;
2653                         for (i = 0; i < ARRAY_SIZE(set); i++)
2654                                 rtl_writephy(tp, 0x0d, val | set[i]);
2655                 }
2656         } else {
2657                 static const struct phy_reg phy_reg_init[] = {
2658                         { 0x1f, 0x0002 },
2659                         { 0x05, 0x6662 },
2660                         { 0x1f, 0x0005 },
2661                         { 0x05, 0x8330 },
2662                         { 0x06, 0x6662 }
2663                 };
2664
2665                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2666         }
2667
2668         /* RSET couple improve */
2669         rtl_writephy(tp, 0x1f, 0x0002);
2670         rtl_patchphy(tp, 0x0d, 0x0300);
2671         rtl_patchphy(tp, 0x0f, 0x0010);
2672
2673         /* Fine tune PLL performance */
2674         rtl_writephy(tp, 0x1f, 0x0002);
2675         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2676         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2677
2678         rtl_writephy(tp, 0x1f, 0x0005);
2679         rtl_writephy(tp, 0x05, 0x001b);
2680
2681         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2682
2683         rtl_writephy(tp, 0x1f, 0x0000);
2684 }
2685
2686 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2687 {
2688         static const struct phy_reg phy_reg_init_0[] = {
2689                 /* Channel Estimation */
2690                 { 0x1f, 0x0001 },
2691                 { 0x06, 0x4064 },
2692                 { 0x07, 0x2863 },
2693                 { 0x08, 0x059c },
2694                 { 0x09, 0x26b4 },
2695                 { 0x0a, 0x6a19 },
2696                 { 0x0b, 0xdcc8 },
2697                 { 0x10, 0xf06d },
2698                 { 0x14, 0x7f68 },
2699                 { 0x18, 0x7fd9 },
2700                 { 0x1c, 0xf0ff },
2701                 { 0x1d, 0x3d9c },
2702                 { 0x1f, 0x0003 },
2703                 { 0x12, 0xf49f },
2704                 { 0x13, 0x070b },
2705                 { 0x1a, 0x05ad },
2706                 { 0x14, 0x94c0 },
2707
2708                 /*
2709                  * Tx Error Issue
2710                  * Enhance line driver power
2711                  */
2712                 { 0x1f, 0x0002 },
2713                 { 0x06, 0x5561 },
2714                 { 0x1f, 0x0005 },
2715                 { 0x05, 0x8332 },
2716                 { 0x06, 0x5561 },
2717
2718                 /*
2719                  * Can not link to 1Gbps with bad cable
2720                  * Decrease SNR threshold form 21.07dB to 19.04dB
2721                  */
2722                 { 0x1f, 0x0001 },
2723                 { 0x17, 0x0cc0 },
2724
2725                 { 0x1f, 0x0000 },
2726                 { 0x0d, 0xf880 }
2727         };
2728         void __iomem *ioaddr = tp->mmio_addr;
2729
2730         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2731
2732         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2733                 static const struct phy_reg phy_reg_init[] = {
2734                         { 0x1f, 0x0002 },
2735                         { 0x05, 0x669a },
2736                         { 0x1f, 0x0005 },
2737                         { 0x05, 0x8330 },
2738                         { 0x06, 0x669a },
2739
2740                         { 0x1f, 0x0002 }
2741                 };
2742                 int val;
2743
2744                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2745
2746                 val = rtl_readphy(tp, 0x0d);
2747                 if ((val & 0x00ff) != 0x006c) {
2748                         static const u32 set[] = {
2749                                 0x0065, 0x0066, 0x0067, 0x0068,
2750                                 0x0069, 0x006a, 0x006b, 0x006c
2751                         };
2752                         int i;
2753
2754                         rtl_writephy(tp, 0x1f, 0x0002);
2755
2756                         val &= 0xff00;
2757                         for (i = 0; i < ARRAY_SIZE(set); i++)
2758                                 rtl_writephy(tp, 0x0d, val | set[i]);
2759                 }
2760         } else {
2761                 static const struct phy_reg phy_reg_init[] = {
2762                         { 0x1f, 0x0002 },
2763                         { 0x05, 0x2642 },
2764                         { 0x1f, 0x0005 },
2765                         { 0x05, 0x8330 },
2766                         { 0x06, 0x2642 }
2767                 };
2768
2769                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2770         }
2771
2772         /* Fine tune PLL performance */
2773         rtl_writephy(tp, 0x1f, 0x0002);
2774         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2775         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2776
2777         /* Switching regulator Slew rate */
2778         rtl_writephy(tp, 0x1f, 0x0002);
2779         rtl_patchphy(tp, 0x0f, 0x0017);
2780
2781         rtl_writephy(tp, 0x1f, 0x0005);
2782         rtl_writephy(tp, 0x05, 0x001b);
2783
2784         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2785
2786         rtl_writephy(tp, 0x1f, 0x0000);
2787 }
2788
2789 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2790 {
2791         static const struct phy_reg phy_reg_init[] = {
2792                 { 0x1f, 0x0002 },
2793                 { 0x10, 0x0008 },
2794                 { 0x0d, 0x006c },
2795
2796                 { 0x1f, 0x0000 },
2797                 { 0x0d, 0xf880 },
2798
2799                 { 0x1f, 0x0001 },
2800                 { 0x17, 0x0cc0 },
2801
2802                 { 0x1f, 0x0001 },
2803                 { 0x0b, 0xa4d8 },
2804                 { 0x09, 0x281c },
2805                 { 0x07, 0x2883 },
2806                 { 0x0a, 0x6b35 },
2807                 { 0x1d, 0x3da4 },
2808                 { 0x1c, 0xeffd },
2809                 { 0x14, 0x7f52 },
2810                 { 0x18, 0x7fc6 },
2811                 { 0x08, 0x0601 },
2812                 { 0x06, 0x4063 },
2813                 { 0x10, 0xf074 },
2814                 { 0x1f, 0x0003 },
2815                 { 0x13, 0x0789 },
2816                 { 0x12, 0xf4bd },
2817                 { 0x1a, 0x04fd },
2818                 { 0x14, 0x84b0 },
2819                 { 0x1f, 0x0000 },
2820                 { 0x00, 0x9200 },
2821
2822                 { 0x1f, 0x0005 },
2823                 { 0x01, 0x0340 },
2824                 { 0x1f, 0x0001 },
2825                 { 0x04, 0x4000 },
2826                 { 0x03, 0x1d21 },
2827                 { 0x02, 0x0c32 },
2828                 { 0x01, 0x0200 },
2829                 { 0x00, 0x5554 },
2830                 { 0x04, 0x4800 },
2831                 { 0x04, 0x4000 },
2832                 { 0x04, 0xf000 },
2833                 { 0x03, 0xdf01 },
2834                 { 0x02, 0xdf20 },
2835                 { 0x01, 0x101a },
2836                 { 0x00, 0xa0ff },
2837                 { 0x04, 0xf800 },
2838                 { 0x04, 0xf000 },
2839                 { 0x1f, 0x0000 },
2840
2841                 { 0x1f, 0x0007 },
2842                 { 0x1e, 0x0023 },
2843                 { 0x16, 0x0000 },
2844                 { 0x1f, 0x0000 }
2845         };
2846
2847         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2848 }
2849
2850 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2851 {
2852         static const struct phy_reg phy_reg_init[] = {
2853                 { 0x1f, 0x0001 },
2854                 { 0x17, 0x0cc0 },
2855
2856                 { 0x1f, 0x0007 },
2857                 { 0x1e, 0x002d },
2858                 { 0x18, 0x0040 },
2859                 { 0x1f, 0x0000 }
2860         };
2861
2862         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2863         rtl_patchphy(tp, 0x0d, 1 << 5);
2864 }
2865
2866 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2867 {
2868         static const struct phy_reg phy_reg_init[] = {
2869                 /* Enable Delay cap */
2870                 { 0x1f, 0x0005 },
2871                 { 0x05, 0x8b80 },
2872                 { 0x06, 0xc896 },
2873                 { 0x1f, 0x0000 },
2874
2875                 /* Channel estimation fine tune */
2876                 { 0x1f, 0x0001 },
2877                 { 0x0b, 0x6c20 },
2878                 { 0x07, 0x2872 },
2879                 { 0x1c, 0xefff },
2880                 { 0x1f, 0x0003 },
2881                 { 0x14, 0x6420 },
2882                 { 0x1f, 0x0000 },
2883
2884                 /* Update PFM & 10M TX idle timer */
2885                 { 0x1f, 0x0007 },
2886                 { 0x1e, 0x002f },
2887                 { 0x15, 0x1919 },
2888                 { 0x1f, 0x0000 },
2889
2890                 { 0x1f, 0x0007 },
2891                 { 0x1e, 0x00ac },
2892                 { 0x18, 0x0006 },
2893                 { 0x1f, 0x0000 }
2894         };
2895
2896         rtl_apply_firmware(tp);
2897
2898         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2899
2900         /* DCO enable for 10M IDLE Power */
2901         rtl_writephy(tp, 0x1f, 0x0007);
2902         rtl_writephy(tp, 0x1e, 0x0023);
2903         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2904         rtl_writephy(tp, 0x1f, 0x0000);
2905
2906         /* For impedance matching */
2907         rtl_writephy(tp, 0x1f, 0x0002);
2908         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2909         rtl_writephy(tp, 0x1f, 0x0000);
2910
2911         /* PHY auto speed down */
2912         rtl_writephy(tp, 0x1f, 0x0007);
2913         rtl_writephy(tp, 0x1e, 0x002d);
2914         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2915         rtl_writephy(tp, 0x1f, 0x0000);
2916         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2917
2918         rtl_writephy(tp, 0x1f, 0x0005);
2919         rtl_writephy(tp, 0x05, 0x8b86);
2920         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2921         rtl_writephy(tp, 0x1f, 0x0000);
2922
2923         rtl_writephy(tp, 0x1f, 0x0005);
2924         rtl_writephy(tp, 0x05, 0x8b85);
2925         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2926         rtl_writephy(tp, 0x1f, 0x0007);
2927         rtl_writephy(tp, 0x1e, 0x0020);
2928         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2929         rtl_writephy(tp, 0x1f, 0x0006);
2930         rtl_writephy(tp, 0x00, 0x5a00);
2931         rtl_writephy(tp, 0x1f, 0x0000);
2932         rtl_writephy(tp, 0x0d, 0x0007);
2933         rtl_writephy(tp, 0x0e, 0x003c);
2934         rtl_writephy(tp, 0x0d, 0x4007);
2935         rtl_writephy(tp, 0x0e, 0x0000);
2936         rtl_writephy(tp, 0x0d, 0x0000);
2937 }
2938
2939 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2940 {
2941         static const struct phy_reg phy_reg_init[] = {
2942                 /* Enable Delay cap */
2943                 { 0x1f, 0x0004 },
2944                 { 0x1f, 0x0007 },
2945                 { 0x1e, 0x00ac },
2946                 { 0x18, 0x0006 },
2947                 { 0x1f, 0x0002 },
2948                 { 0x1f, 0x0000 },
2949                 { 0x1f, 0x0000 },
2950
2951                 /* Channel estimation fine tune */
2952                 { 0x1f, 0x0003 },
2953                 { 0x09, 0xa20f },
2954                 { 0x1f, 0x0000 },
2955                 { 0x1f, 0x0000 },
2956
2957                 /* Green Setting */
2958                 { 0x1f, 0x0005 },
2959                 { 0x05, 0x8b5b },
2960                 { 0x06, 0x9222 },
2961                 { 0x05, 0x8b6d },
2962                 { 0x06, 0x8000 },
2963                 { 0x05, 0x8b76 },
2964                 { 0x06, 0x8000 },
2965                 { 0x1f, 0x0000 }
2966         };
2967
2968         rtl_apply_firmware(tp);
2969
2970         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2971
2972         /* For 4-corner performance improve */
2973         rtl_writephy(tp, 0x1f, 0x0005);
2974         rtl_writephy(tp, 0x05, 0x8b80);
2975         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2976         rtl_writephy(tp, 0x1f, 0x0000);
2977
2978         /* PHY auto speed down */
2979         rtl_writephy(tp, 0x1f, 0x0004);
2980         rtl_writephy(tp, 0x1f, 0x0007);
2981         rtl_writephy(tp, 0x1e, 0x002d);
2982         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2983         rtl_writephy(tp, 0x1f, 0x0002);
2984         rtl_writephy(tp, 0x1f, 0x0000);
2985         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2986
2987         /* improve 10M EEE waveform */
2988         rtl_writephy(tp, 0x1f, 0x0005);
2989         rtl_writephy(tp, 0x05, 0x8b86);
2990         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2991         rtl_writephy(tp, 0x1f, 0x0000);
2992
2993         /* Improve 2-pair detection performance */
2994         rtl_writephy(tp, 0x1f, 0x0005);
2995         rtl_writephy(tp, 0x05, 0x8b85);
2996         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2997         rtl_writephy(tp, 0x1f, 0x0000);
2998
2999         /* EEE setting */
3000         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
3001                      ERIAR_EXGMAC);
3002         rtl_writephy(tp, 0x1f, 0x0005);
3003         rtl_writephy(tp, 0x05, 0x8b85);
3004         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3005         rtl_writephy(tp, 0x1f, 0x0004);
3006         rtl_writephy(tp, 0x1f, 0x0007);
3007         rtl_writephy(tp, 0x1e, 0x0020);
3008         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3009         rtl_writephy(tp, 0x1f, 0x0002);
3010         rtl_writephy(tp, 0x1f, 0x0000);
3011         rtl_writephy(tp, 0x0d, 0x0007);
3012         rtl_writephy(tp, 0x0e, 0x003c);
3013         rtl_writephy(tp, 0x0d, 0x4007);
3014         rtl_writephy(tp, 0x0e, 0x0000);
3015         rtl_writephy(tp, 0x0d, 0x0000);
3016
3017         /* Green feature */
3018         rtl_writephy(tp, 0x1f, 0x0003);
3019         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3020         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3021         rtl_writephy(tp, 0x1f, 0x0000);
3022 }
3023
3024 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3025 {
3026         static const struct phy_reg phy_reg_init[] = {
3027                 /* Channel estimation fine tune */
3028                 { 0x1f, 0x0003 },
3029                 { 0x09, 0xa20f },
3030                 { 0x1f, 0x0000 },
3031
3032                 /* Modify green table for giga & fnet */
3033                 { 0x1f, 0x0005 },
3034                 { 0x05, 0x8b55 },
3035                 { 0x06, 0x0000 },
3036                 { 0x05, 0x8b5e },
3037                 { 0x06, 0x0000 },
3038                 { 0x05, 0x8b67 },
3039                 { 0x06, 0x0000 },
3040                 { 0x05, 0x8b70 },
3041                 { 0x06, 0x0000 },
3042                 { 0x1f, 0x0000 },
3043                 { 0x1f, 0x0007 },
3044                 { 0x1e, 0x0078 },
3045                 { 0x17, 0x0000 },
3046                 { 0x19, 0x00fb },
3047                 { 0x1f, 0x0000 },
3048
3049                 /* Modify green table for 10M */
3050                 { 0x1f, 0x0005 },
3051                 { 0x05, 0x8b79 },
3052                 { 0x06, 0xaa00 },
3053                 { 0x1f, 0x0000 },
3054
3055                 /* Disable hiimpedance detection (RTCT) */
3056                 { 0x1f, 0x0003 },
3057                 { 0x01, 0x328a },
3058                 { 0x1f, 0x0000 }
3059         };
3060
3061         rtl_apply_firmware(tp);
3062
3063         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3064
3065         /* For 4-corner performance improve */
3066         rtl_writephy(tp, 0x1f, 0x0005);
3067         rtl_writephy(tp, 0x05, 0x8b80);
3068         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3069         rtl_writephy(tp, 0x1f, 0x0000);
3070
3071         /* PHY auto speed down */
3072         rtl_writephy(tp, 0x1f, 0x0007);
3073         rtl_writephy(tp, 0x1e, 0x002d);
3074         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3075         rtl_writephy(tp, 0x1f, 0x0000);
3076         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3077
3078         /* Improve 10M EEE waveform */
3079         rtl_writephy(tp, 0x1f, 0x0005);
3080         rtl_writephy(tp, 0x05, 0x8b86);
3081         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3082         rtl_writephy(tp, 0x1f, 0x0000);
3083
3084         /* Improve 2-pair detection performance */
3085         rtl_writephy(tp, 0x1f, 0x0005);
3086         rtl_writephy(tp, 0x05, 0x8b85);
3087         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3088         rtl_writephy(tp, 0x1f, 0x0000);
3089 }
3090
3091 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3092 {
3093         rtl_apply_firmware(tp);
3094
3095         /* For 4-corner performance improve */
3096         rtl_writephy(tp, 0x1f, 0x0005);
3097         rtl_writephy(tp, 0x05, 0x8b80);
3098         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3099         rtl_writephy(tp, 0x1f, 0x0000);
3100
3101         /* PHY auto speed down */
3102         rtl_writephy(tp, 0x1f, 0x0007);
3103         rtl_writephy(tp, 0x1e, 0x002d);
3104         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3105         rtl_writephy(tp, 0x1f, 0x0000);
3106         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3107
3108         /* Improve 10M EEE waveform */
3109         rtl_writephy(tp, 0x1f, 0x0005);
3110         rtl_writephy(tp, 0x05, 0x8b86);
3111         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3112         rtl_writephy(tp, 0x1f, 0x0000);
3113 }
3114
3115 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3116 {
3117         static const struct phy_reg phy_reg_init[] = {
3118                 { 0x1f, 0x0003 },
3119                 { 0x08, 0x441d },
3120                 { 0x01, 0x9100 },
3121                 { 0x1f, 0x0000 }
3122         };
3123
3124         rtl_writephy(tp, 0x1f, 0x0000);
3125         rtl_patchphy(tp, 0x11, 1 << 12);
3126         rtl_patchphy(tp, 0x19, 1 << 13);
3127         rtl_patchphy(tp, 0x10, 1 << 15);
3128
3129         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3130 }
3131
3132 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3133 {
3134         static const struct phy_reg phy_reg_init[] = {
3135                 { 0x1f, 0x0005 },
3136                 { 0x1a, 0x0000 },
3137                 { 0x1f, 0x0000 },
3138
3139                 { 0x1f, 0x0004 },
3140                 { 0x1c, 0x0000 },
3141                 { 0x1f, 0x0000 },
3142
3143                 { 0x1f, 0x0001 },
3144                 { 0x15, 0x7701 },
3145                 { 0x1f, 0x0000 }
3146         };
3147
3148         /* Disable ALDPS before ram code */
3149         rtl_writephy(tp, 0x1f, 0x0000);
3150         rtl_writephy(tp, 0x18, 0x0310);
3151         msleep(100);
3152
3153         rtl_apply_firmware(tp);
3154
3155         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3156 }
3157
3158 static void rtl_hw_phy_config(struct net_device *dev)
3159 {
3160         struct rtl8169_private *tp = netdev_priv(dev);
3161
3162         rtl8169_print_mac_version(tp);
3163
3164         switch (tp->mac_version) {
3165         case RTL_GIGA_MAC_VER_01:
3166                 break;
3167         case RTL_GIGA_MAC_VER_02:
3168         case RTL_GIGA_MAC_VER_03:
3169                 rtl8169s_hw_phy_config(tp);
3170                 break;
3171         case RTL_GIGA_MAC_VER_04:
3172                 rtl8169sb_hw_phy_config(tp);
3173                 break;
3174         case RTL_GIGA_MAC_VER_05:
3175                 rtl8169scd_hw_phy_config(tp);
3176                 break;
3177         case RTL_GIGA_MAC_VER_06:
3178                 rtl8169sce_hw_phy_config(tp);
3179                 break;
3180         case RTL_GIGA_MAC_VER_07:
3181         case RTL_GIGA_MAC_VER_08:
3182         case RTL_GIGA_MAC_VER_09:
3183                 rtl8102e_hw_phy_config(tp);
3184                 break;
3185         case RTL_GIGA_MAC_VER_11:
3186                 rtl8168bb_hw_phy_config(tp);
3187                 break;
3188         case RTL_GIGA_MAC_VER_12:
3189                 rtl8168bef_hw_phy_config(tp);
3190                 break;
3191         case RTL_GIGA_MAC_VER_17:
3192                 rtl8168bef_hw_phy_config(tp);
3193                 break;
3194         case RTL_GIGA_MAC_VER_18:
3195                 rtl8168cp_1_hw_phy_config(tp);
3196                 break;
3197         case RTL_GIGA_MAC_VER_19:
3198                 rtl8168c_1_hw_phy_config(tp);
3199                 break;
3200         case RTL_GIGA_MAC_VER_20:
3201                 rtl8168c_2_hw_phy_config(tp);
3202                 break;
3203         case RTL_GIGA_MAC_VER_21:
3204                 rtl8168c_3_hw_phy_config(tp);
3205                 break;
3206         case RTL_GIGA_MAC_VER_22:
3207                 rtl8168c_4_hw_phy_config(tp);
3208                 break;
3209         case RTL_GIGA_MAC_VER_23:
3210         case RTL_GIGA_MAC_VER_24:
3211                 rtl8168cp_2_hw_phy_config(tp);
3212                 break;
3213         case RTL_GIGA_MAC_VER_25:
3214                 rtl8168d_1_hw_phy_config(tp);
3215                 break;
3216         case RTL_GIGA_MAC_VER_26:
3217                 rtl8168d_2_hw_phy_config(tp);
3218                 break;
3219         case RTL_GIGA_MAC_VER_27:
3220                 rtl8168d_3_hw_phy_config(tp);
3221                 break;
3222         case RTL_GIGA_MAC_VER_28:
3223                 rtl8168d_4_hw_phy_config(tp);
3224                 break;
3225         case RTL_GIGA_MAC_VER_29:
3226         case RTL_GIGA_MAC_VER_30:
3227                 rtl8105e_hw_phy_config(tp);
3228                 break;
3229         case RTL_GIGA_MAC_VER_31:
3230                 /* None. */
3231                 break;
3232         case RTL_GIGA_MAC_VER_32:
3233         case RTL_GIGA_MAC_VER_33:
3234                 rtl8168e_1_hw_phy_config(tp);
3235                 break;
3236         case RTL_GIGA_MAC_VER_34:
3237                 rtl8168e_2_hw_phy_config(tp);
3238                 break;
3239         case RTL_GIGA_MAC_VER_35:
3240                 rtl8168f_1_hw_phy_config(tp);
3241                 break;
3242         case RTL_GIGA_MAC_VER_36:
3243                 rtl8168f_2_hw_phy_config(tp);
3244                 break;
3245
3246         default:
3247                 break;
3248         }
3249 }
3250
3251 static void rtl_phy_work(struct rtl8169_private *tp)
3252 {
3253         struct timer_list *timer = &tp->timer;
3254         void __iomem *ioaddr = tp->mmio_addr;
3255         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3256
3257         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3258
3259         if (tp->phy_reset_pending(tp)) {
3260                 /*
3261                  * A busy loop could burn quite a few cycles on nowadays CPU.
3262                  * Let's delay the execution of the timer for a few ticks.
3263                  */
3264                 timeout = HZ/10;
3265                 goto out_mod_timer;
3266         }
3267
3268         if (tp->link_ok(ioaddr))
3269                 return;
3270
3271         netif_warn(tp, link, tp->dev, "PHY reset until link up\n");
3272
3273         tp->phy_reset_enable(tp);
3274
3275 out_mod_timer:
3276         mod_timer(timer, jiffies + timeout);
3277 }
3278
3279 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3280 {
3281         if (!test_and_set_bit(flag, tp->wk.flags))
3282                 schedule_work(&tp->wk.work);
3283 }
3284
3285 static void rtl8169_phy_timer(unsigned long __opaque)
3286 {
3287         struct net_device *dev = (struct net_device *)__opaque;
3288         struct rtl8169_private *tp = netdev_priv(dev);
3289
3290         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3291 }
3292
3293 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3294                                   void __iomem *ioaddr)
3295 {
3296         iounmap(ioaddr);
3297         pci_release_regions(pdev);
3298         pci_clear_mwi(pdev);
3299         pci_disable_device(pdev);
3300         free_netdev(dev);
3301 }
3302
3303 static void rtl8169_phy_reset(struct net_device *dev,
3304                               struct rtl8169_private *tp)
3305 {
3306         unsigned int i;
3307
3308         tp->phy_reset_enable(tp);
3309         for (i = 0; i < 100; i++) {
3310                 if (!tp->phy_reset_pending(tp))
3311                         return;
3312                 msleep(1);
3313         }
3314         netif_err(tp, link, dev, "PHY reset failed\n");
3315 }
3316
3317 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3318 {
3319         void __iomem *ioaddr = tp->mmio_addr;
3320
3321         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3322             (RTL_R8(PHYstatus) & TBI_Enable);
3323 }
3324
3325 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3326 {
3327         void __iomem *ioaddr = tp->mmio_addr;
3328
3329         rtl_hw_phy_config(dev);
3330
3331         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3332                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3333                 RTL_W8(0x82, 0x01);
3334         }
3335
3336         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3337
3338         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3339                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3340
3341         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3342                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3343                 RTL_W8(0x82, 0x01);
3344                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3345                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3346         }
3347
3348         rtl8169_phy_reset(dev, tp);
3349
3350         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3351                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3352                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3353                           (tp->mii.supports_gmii ?
3354                            ADVERTISED_1000baseT_Half |
3355                            ADVERTISED_1000baseT_Full : 0));
3356
3357         if (rtl_tbi_enabled(tp))
3358                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3359 }
3360
3361 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3362 {
3363         void __iomem *ioaddr = tp->mmio_addr;
3364         u32 high;
3365         u32 low;
3366
3367         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3368         high = addr[4] | (addr[5] << 8);
3369
3370         rtl_lock_work(tp);
3371
3372         RTL_W8(Cfg9346, Cfg9346_Unlock);
3373
3374         RTL_W32(MAC4, high);
3375         RTL_R32(MAC4);
3376
3377         RTL_W32(MAC0, low);
3378         RTL_R32(MAC0);
3379
3380         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3381                 const struct exgmac_reg e[] = {
3382                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3383                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3384                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3385                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3386                                                                 low  >> 16 },
3387                 };
3388
3389                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3390         }
3391
3392         RTL_W8(Cfg9346, Cfg9346_Lock);
3393
3394         rtl_unlock_work(tp);
3395 }
3396
3397 static int rtl_set_mac_address(struct net_device *dev, void *p)
3398 {
3399         struct rtl8169_private *tp = netdev_priv(dev);
3400         struct sockaddr *addr = p;
3401
3402         if (!is_valid_ether_addr(addr->sa_data))
3403                 return -EADDRNOTAVAIL;
3404
3405         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3406
3407         rtl_rar_set(tp, dev->dev_addr);
3408
3409         return 0;
3410 }
3411
3412 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3413 {
3414         struct rtl8169_private *tp = netdev_priv(dev);
3415         struct mii_ioctl_data *data = if_mii(ifr);
3416
3417         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3418 }
3419
3420 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3421                           struct mii_ioctl_data *data, int cmd)
3422 {
3423         switch (cmd) {
3424         case SIOCGMIIPHY:
3425                 data->phy_id = 32; /* Internal PHY */
3426                 return 0;
3427
3428         case SIOCGMIIREG:
3429                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3430                 return 0;
3431
3432         case SIOCSMIIREG:
3433                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3434                 return 0;
3435         }
3436         return -EOPNOTSUPP;
3437 }
3438
3439 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3440 {
3441         return -EOPNOTSUPP;
3442 }
3443
3444 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3445 {
3446         if (tp->features & RTL_FEATURE_MSI) {
3447                 pci_disable_msi(pdev);
3448                 tp->features &= ~RTL_FEATURE_MSI;
3449         }
3450 }
3451
3452 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3453 {
3454         struct mdio_ops *ops = &tp->mdio_ops;
3455
3456         switch (tp->mac_version) {
3457         case RTL_GIGA_MAC_VER_27:
3458                 ops->write      = r8168dp_1_mdio_write;
3459                 ops->read       = r8168dp_1_mdio_read;
3460                 break;
3461         case RTL_GIGA_MAC_VER_28:
3462         case RTL_GIGA_MAC_VER_31:
3463                 ops->write      = r8168dp_2_mdio_write;
3464                 ops->read       = r8168dp_2_mdio_read;
3465                 break;
3466         default:
3467                 ops->write      = r8169_mdio_write;
3468                 ops->read       = r8169_mdio_read;
3469                 break;
3470         }
3471 }
3472
3473 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3474 {
3475         void __iomem *ioaddr = tp->mmio_addr;
3476
3477         switch (tp->mac_version) {
3478         case RTL_GIGA_MAC_VER_29:
3479         case RTL_GIGA_MAC_VER_30:
3480         case RTL_GIGA_MAC_VER_32:
3481         case RTL_GIGA_MAC_VER_33:
3482         case RTL_GIGA_MAC_VER_34:
3483                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3484                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3485                 break;
3486         default:
3487                 break;
3488         }
3489 }
3490
3491 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3492 {
3493         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3494                 return false;
3495
3496         rtl_writephy(tp, 0x1f, 0x0000);
3497         rtl_writephy(tp, MII_BMCR, 0x0000);
3498
3499         rtl_wol_suspend_quirk(tp);
3500
3501         return true;
3502 }
3503
3504 static void r810x_phy_power_down(struct rtl8169_private *tp)
3505 {
3506         rtl_writephy(tp, 0x1f, 0x0000);
3507         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3508 }
3509
3510 static void r810x_phy_power_up(struct rtl8169_private *tp)
3511 {
3512         rtl_writephy(tp, 0x1f, 0x0000);
3513         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3514 }
3515
3516 static void r810x_pll_power_down(struct rtl8169_private *tp)
3517 {
3518         if (rtl_wol_pll_power_down(tp))
3519                 return;
3520
3521         r810x_phy_power_down(tp);
3522 }
3523
3524 static void r810x_pll_power_up(struct rtl8169_private *tp)
3525 {
3526         r810x_phy_power_up(tp);
3527 }
3528
3529 static void r8168_phy_power_up(struct rtl8169_private *tp)
3530 {
3531         rtl_writephy(tp, 0x1f, 0x0000);
3532         switch (tp->mac_version) {
3533         case RTL_GIGA_MAC_VER_11:
3534         case RTL_GIGA_MAC_VER_12:
3535         case RTL_GIGA_MAC_VER_17:
3536         case RTL_GIGA_MAC_VER_18:
3537         case RTL_GIGA_MAC_VER_19:
3538         case RTL_GIGA_MAC_VER_20:
3539         case RTL_GIGA_MAC_VER_21:
3540         case RTL_GIGA_MAC_VER_22:
3541         case RTL_GIGA_MAC_VER_23:
3542         case RTL_GIGA_MAC_VER_24:
3543         case RTL_GIGA_MAC_VER_25:
3544         case RTL_GIGA_MAC_VER_26:
3545         case RTL_GIGA_MAC_VER_27:
3546         case RTL_GIGA_MAC_VER_28:
3547         case RTL_GIGA_MAC_VER_31:
3548                 rtl_writephy(tp, 0x0e, 0x0000);
3549                 break;
3550         default:
3551                 break;
3552         }
3553         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3554 }
3555
3556 static void r8168_phy_power_down(struct rtl8169_private *tp)
3557 {
3558         rtl_writephy(tp, 0x1f, 0x0000);
3559         switch (tp->mac_version) {
3560         case RTL_GIGA_MAC_VER_32:
3561         case RTL_GIGA_MAC_VER_33:
3562                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3563                 break;
3564
3565         case RTL_GIGA_MAC_VER_11:
3566         case RTL_GIGA_MAC_VER_12:
3567         case RTL_GIGA_MAC_VER_17:
3568         case RTL_GIGA_MAC_VER_18:
3569         case RTL_GIGA_MAC_VER_19:
3570         case RTL_GIGA_MAC_VER_20:
3571         case RTL_GIGA_MAC_VER_21:
3572         case RTL_GIGA_MAC_VER_22:
3573         case RTL_GIGA_MAC_VER_23:
3574         case RTL_GIGA_MAC_VER_24:
3575         case RTL_GIGA_MAC_VER_25:
3576         case RTL_GIGA_MAC_VER_26:
3577         case RTL_GIGA_MAC_VER_27:
3578         case RTL_GIGA_MAC_VER_28:
3579         case RTL_GIGA_MAC_VER_31:
3580                 rtl_writephy(tp, 0x0e, 0x0200);
3581         default:
3582                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3583                 break;
3584         }
3585 }
3586
3587 static void r8168_pll_power_down(struct rtl8169_private *tp)
3588 {
3589         void __iomem *ioaddr = tp->mmio_addr;
3590
3591         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3592              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3593              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3594             r8168dp_check_dash(tp)) {
3595                 return;
3596         }
3597
3598         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3599              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3600             (RTL_R16(CPlusCmd) & ASF)) {
3601                 return;
3602         }
3603
3604         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3605             tp->mac_version == RTL_GIGA_MAC_VER_33)
3606                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3607
3608         if (rtl_wol_pll_power_down(tp))
3609                 return;
3610
3611         r8168_phy_power_down(tp);
3612
3613         switch (tp->mac_version) {
3614         case RTL_GIGA_MAC_VER_25:
3615         case RTL_GIGA_MAC_VER_26:
3616         case RTL_GIGA_MAC_VER_27:
3617         case RTL_GIGA_MAC_VER_28:
3618         case RTL_GIGA_MAC_VER_31:
3619         case RTL_GIGA_MAC_VER_32:
3620         case RTL_GIGA_MAC_VER_33:
3621                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3622                 break;
3623         }
3624 }
3625
3626 static void r8168_pll_power_up(struct rtl8169_private *tp)
3627 {
3628         void __iomem *ioaddr = tp->mmio_addr;
3629
3630         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3631              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3632              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3633             r8168dp_check_dash(tp)) {
3634                 return;
3635         }
3636
3637         switch (tp->mac_version) {
3638         case RTL_GIGA_MAC_VER_25:
3639         case RTL_GIGA_MAC_VER_26:
3640         case RTL_GIGA_MAC_VER_27:
3641         case RTL_GIGA_MAC_VER_28:
3642         case RTL_GIGA_MAC_VER_31:
3643         case RTL_GIGA_MAC_VER_32:
3644         case RTL_GIGA_MAC_VER_33:
3645                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3646                 break;
3647         }
3648
3649         r8168_phy_power_up(tp);
3650 }
3651
3652 static void rtl_generic_op(struct rtl8169_private *tp,
3653                            void (*op)(struct rtl8169_private *))
3654 {
3655         if (op)
3656                 op(tp);
3657 }
3658
3659 static void rtl_pll_power_down(struct rtl8169_private *tp)
3660 {
3661         rtl_generic_op(tp, tp->pll_power_ops.down);
3662 }
3663
3664 static void rtl_pll_power_up(struct rtl8169_private *tp)
3665 {
3666         rtl_generic_op(tp, tp->pll_power_ops.up);
3667 }
3668
3669 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3670 {
3671         struct pll_power_ops *ops = &tp->pll_power_ops;
3672
3673         switch (tp->mac_version) {
3674         case RTL_GIGA_MAC_VER_07:
3675         case RTL_GIGA_MAC_VER_08:
3676         case RTL_GIGA_MAC_VER_09:
3677         case RTL_GIGA_MAC_VER_10:
3678         case RTL_GIGA_MAC_VER_16:
3679         case RTL_GIGA_MAC_VER_29:
3680         case RTL_GIGA_MAC_VER_30:
3681                 ops->down       = r810x_pll_power_down;
3682                 ops->up         = r810x_pll_power_up;
3683                 break;
3684
3685         case RTL_GIGA_MAC_VER_11:
3686         case RTL_GIGA_MAC_VER_12:
3687         case RTL_GIGA_MAC_VER_17:
3688         case RTL_GIGA_MAC_VER_18:
3689         case RTL_GIGA_MAC_VER_19:
3690         case RTL_GIGA_MAC_VER_20:
3691         case RTL_GIGA_MAC_VER_21:
3692         case RTL_GIGA_MAC_VER_22:
3693         case RTL_GIGA_MAC_VER_23:
3694         case RTL_GIGA_MAC_VER_24:
3695         case RTL_GIGA_MAC_VER_25:
3696         case RTL_GIGA_MAC_VER_26:
3697         case RTL_GIGA_MAC_VER_27:
3698         case RTL_GIGA_MAC_VER_28:
3699         case RTL_GIGA_MAC_VER_31:
3700         case RTL_GIGA_MAC_VER_32:
3701         case RTL_GIGA_MAC_VER_33:
3702         case RTL_GIGA_MAC_VER_34:
3703         case RTL_GIGA_MAC_VER_35:
3704         case RTL_GIGA_MAC_VER_36:
3705                 ops->down       = r8168_pll_power_down;
3706                 ops->up         = r8168_pll_power_up;
3707                 break;
3708
3709         default:
3710                 ops->down       = NULL;
3711                 ops->up         = NULL;
3712                 break;
3713         }
3714 }
3715
3716 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3717 {
3718         void __iomem *ioaddr = tp->mmio_addr;
3719
3720         switch (tp->mac_version) {
3721         case RTL_GIGA_MAC_VER_01:
3722         case RTL_GIGA_MAC_VER_02:
3723         case RTL_GIGA_MAC_VER_03:
3724         case RTL_GIGA_MAC_VER_04:
3725         case RTL_GIGA_MAC_VER_05:
3726         case RTL_GIGA_MAC_VER_06:
3727         case RTL_GIGA_MAC_VER_10:
3728         case RTL_GIGA_MAC_VER_11:
3729         case RTL_GIGA_MAC_VER_12:
3730         case RTL_GIGA_MAC_VER_13:
3731         case RTL_GIGA_MAC_VER_14:
3732         case RTL_GIGA_MAC_VER_15:
3733         case RTL_GIGA_MAC_VER_16:
3734         case RTL_GIGA_MAC_VER_17:
3735                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3736                 break;
3737         case RTL_GIGA_MAC_VER_18:
3738         case RTL_GIGA_MAC_VER_19:
3739         case RTL_GIGA_MAC_VER_20:
3740         case RTL_GIGA_MAC_VER_21:
3741         case RTL_GIGA_MAC_VER_22:
3742         case RTL_GIGA_MAC_VER_23:
3743         case RTL_GIGA_MAC_VER_24:
3744                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3745                 break;
3746         default:
3747                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3748                 break;
3749         }
3750 }
3751
3752 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3753 {
3754         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3755 }
3756
3757 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3758 {
3759         void __iomem *ioaddr = tp->mmio_addr;
3760
3761         RTL_W8(Cfg9346, Cfg9346_Unlock);
3762         rtl_generic_op(tp, tp->jumbo_ops.enable);
3763         RTL_W8(Cfg9346, Cfg9346_Lock);
3764 }
3765
3766 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3767 {
3768         void __iomem *ioaddr = tp->mmio_addr;
3769
3770         RTL_W8(Cfg9346, Cfg9346_Unlock);
3771         rtl_generic_op(tp, tp->jumbo_ops.disable);
3772         RTL_W8(Cfg9346, Cfg9346_Lock);
3773 }
3774
3775 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3776 {
3777         void __iomem *ioaddr = tp->mmio_addr;
3778
3779         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3780         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3781         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3782 }
3783
3784 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3785 {
3786         void __iomem *ioaddr = tp->mmio_addr;
3787
3788         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3789         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3790         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3791 }
3792
3793 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3794 {
3795         void __iomem *ioaddr = tp->mmio_addr;
3796
3797         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3798 }
3799
3800 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3801 {
3802         void __iomem *ioaddr = tp->mmio_addr;
3803
3804         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3805 }
3806
3807 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3808 {
3809         void __iomem *ioaddr = tp->mmio_addr;
3810
3811         RTL_W8(MaxTxPacketSize, 0x3f);
3812         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3813         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3814         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3815 }
3816
3817 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3818 {
3819         void __iomem *ioaddr = tp->mmio_addr;
3820
3821         RTL_W8(MaxTxPacketSize, 0x0c);
3822         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3823         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3824         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3825 }
3826
3827 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3828 {
3829         rtl_tx_performance_tweak(tp->pci_dev,
3830                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3831 }
3832
3833 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3834 {
3835         rtl_tx_performance_tweak(tp->pci_dev,
3836                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3837 }
3838
3839 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3840 {
3841         void __iomem *ioaddr = tp->mmio_addr;
3842
3843         r8168b_0_hw_jumbo_enable(tp);
3844
3845         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3846 }
3847
3848 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3849 {
3850         void __iomem *ioaddr = tp->mmio_addr;
3851
3852         r8168b_0_hw_jumbo_disable(tp);
3853
3854         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3855 }
3856
3857 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3858 {
3859         struct jumbo_ops *ops = &tp->jumbo_ops;
3860
3861         switch (tp->mac_version) {
3862         case RTL_GIGA_MAC_VER_11:
3863                 ops->disable    = r8168b_0_hw_jumbo_disable;
3864                 ops->enable     = r8168b_0_hw_jumbo_enable;
3865                 break;
3866         case RTL_GIGA_MAC_VER_12:
3867         case RTL_GIGA_MAC_VER_17:
3868                 ops->disable    = r8168b_1_hw_jumbo_disable;
3869                 ops->enable     = r8168b_1_hw_jumbo_enable;
3870                 break;
3871         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3872         case RTL_GIGA_MAC_VER_19:
3873         case RTL_GIGA_MAC_VER_20:
3874         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3875         case RTL_GIGA_MAC_VER_22:
3876         case RTL_GIGA_MAC_VER_23:
3877         case RTL_GIGA_MAC_VER_24:
3878         case RTL_GIGA_MAC_VER_25:
3879         case RTL_GIGA_MAC_VER_26:
3880                 ops->disable    = r8168c_hw_jumbo_disable;
3881                 ops->enable     = r8168c_hw_jumbo_enable;
3882                 break;
3883         case RTL_GIGA_MAC_VER_27:
3884         case RTL_GIGA_MAC_VER_28:
3885                 ops->disable    = r8168dp_hw_jumbo_disable;
3886                 ops->enable     = r8168dp_hw_jumbo_enable;
3887                 break;
3888         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3889         case RTL_GIGA_MAC_VER_32:
3890         case RTL_GIGA_MAC_VER_33:
3891         case RTL_GIGA_MAC_VER_34:
3892                 ops->disable    = r8168e_hw_jumbo_disable;
3893                 ops->enable     = r8168e_hw_jumbo_enable;
3894                 break;
3895
3896         /*
3897          * No action needed for jumbo frames with 8169.
3898          * No jumbo for 810x at all.
3899          */
3900         default:
3901                 ops->disable    = NULL;
3902                 ops->enable     = NULL;
3903                 break;
3904         }
3905 }
3906
3907 static void rtl_hw_reset(struct rtl8169_private *tp)
3908 {
3909         void __iomem *ioaddr = tp->mmio_addr;
3910         int i;
3911
3912         /* Soft reset the chip. */
3913         RTL_W8(ChipCmd, CmdReset);
3914
3915         /* Check that the chip has finished the reset. */
3916         for (i = 0; i < 100; i++) {
3917                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3918                         break;
3919                 udelay(100);
3920         }
3921 }
3922
3923 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3924 {
3925         struct rtl_fw *rtl_fw;
3926         const char *name;
3927         int rc = -ENOMEM;
3928
3929         name = rtl_lookup_firmware_name(tp);
3930         if (!name)
3931                 goto out_no_firmware;
3932
3933         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3934         if (!rtl_fw)
3935                 goto err_warn;
3936
3937         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3938         if (rc < 0)
3939                 goto err_free;
3940
3941         rc = rtl_check_firmware(tp, rtl_fw);
3942         if (rc < 0)
3943                 goto err_release_firmware;
3944
3945         tp->rtl_fw = rtl_fw;
3946 out:
3947         return;
3948
3949 err_release_firmware:
3950         release_firmware(rtl_fw->fw);
3951 err_free:
3952         kfree(rtl_fw);
3953 err_warn:
3954         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3955                    name, rc);
3956 out_no_firmware:
3957         tp->rtl_fw = NULL;
3958         goto out;
3959 }
3960
3961 static void rtl_request_firmware(struct rtl8169_private *tp)
3962 {
3963         if (IS_ERR(tp->rtl_fw))
3964                 rtl_request_uncached_firmware(tp);
3965 }
3966
3967 static void rtl_rx_close(struct rtl8169_private *tp)
3968 {
3969         void __iomem *ioaddr = tp->mmio_addr;
3970
3971         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3972 }
3973
3974 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3975 {
3976         void __iomem *ioaddr = tp->mmio_addr;
3977
3978         /* Disable interrupts */
3979         rtl8169_irq_mask_and_ack(tp);
3980
3981         rtl_rx_close(tp);
3982
3983         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3984             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3985             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3986                 while (RTL_R8(TxPoll) & NPQ)
3987                         udelay(20);
3988         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
3989                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
3990                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
3991                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3992                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3993                         udelay(100);
3994         } else {
3995                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3996                 udelay(100);
3997         }
3998
3999         rtl_hw_reset(tp);
4000 }
4001
4002 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4003 {
4004         void __iomem *ioaddr = tp->mmio_addr;
4005
4006         /* Set DMA burst size and Interframe Gap Time */
4007         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4008                 (InterFrameGap << TxInterFrameGapShift));
4009 }
4010
4011 static void rtl_hw_start(struct net_device *dev)
4012 {
4013         struct rtl8169_private *tp = netdev_priv(dev);
4014
4015         tp->hw_start(dev);
4016
4017         rtl_irq_enable_all(tp);
4018 }
4019
4020 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4021                                          void __iomem *ioaddr)
4022 {
4023         /*
4024          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4025          * register to be written before TxDescAddrLow to work.
4026          * Switching from MMIO to I/O access fixes the issue as well.
4027          */
4028         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4029         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4030         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4031         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4032 }
4033
4034 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4035 {
4036         u16 cmd;
4037
4038         cmd = RTL_R16(CPlusCmd);
4039         RTL_W16(CPlusCmd, cmd);
4040         return cmd;
4041 }
4042
4043 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4044 {
4045         /* Low hurts. Let's disable the filtering. */
4046         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4047 }
4048
4049 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4050 {
4051         static const struct rtl_cfg2_info {
4052                 u32 mac_version;
4053                 u32 clk;
4054                 u32 val;
4055         } cfg2_info [] = {
4056                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4057                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4058                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4059                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4060         };
4061         const struct rtl_cfg2_info *p = cfg2_info;
4062         unsigned int i;
4063         u32 clk;
4064
4065         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4066         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4067                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4068                         RTL_W32(0x7c, p->val);
4069                         break;
4070                 }
4071         }
4072 }
4073
4074 static void rtl_set_rx_mode(struct net_device *dev)
4075 {
4076         struct rtl8169_private *tp = netdev_priv(dev);
4077         void __iomem *ioaddr = tp->mmio_addr;
4078         u32 mc_filter[2];       /* Multicast hash filter */
4079         int rx_mode;
4080         u32 tmp = 0;
4081
4082         if (dev->flags & IFF_PROMISC) {
4083                 /* Unconditionally log net taps. */
4084                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4085                 rx_mode =
4086                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4087                     AcceptAllPhys;
4088                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4089         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4090                    (dev->flags & IFF_ALLMULTI)) {
4091                 /* Too many to filter perfectly -- accept all multicasts. */
4092                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4093                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4094         } else {
4095                 struct netdev_hw_addr *ha;
4096
4097                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4098                 mc_filter[1] = mc_filter[0] = 0;
4099                 netdev_for_each_mc_addr(ha, dev) {
4100                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4101                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4102                         rx_mode |= AcceptMulticast;
4103                 }
4104         }
4105
4106         if (dev->features & NETIF_F_RXALL)
4107                 rx_mode |= (AcceptErr | AcceptRunt);
4108
4109         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4110
4111         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4112                 u32 data = mc_filter[0];
4113
4114                 mc_filter[0] = swab32(mc_filter[1]);
4115                 mc_filter[1] = swab32(data);
4116         }
4117
4118         RTL_W32(MAR0 + 4, mc_filter[1]);
4119         RTL_W32(MAR0 + 0, mc_filter[0]);
4120
4121         RTL_W32(RxConfig, tmp);
4122 }
4123
4124 static void rtl_hw_start_8169(struct net_device *dev)
4125 {
4126         struct rtl8169_private *tp = netdev_priv(dev);
4127         void __iomem *ioaddr = tp->mmio_addr;
4128         struct pci_dev *pdev = tp->pci_dev;
4129
4130         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4131                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4132                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4133         }
4134
4135         RTL_W8(Cfg9346, Cfg9346_Unlock);
4136         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4137             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4138             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4139             tp->mac_version == RTL_GIGA_MAC_VER_04)
4140                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4141
4142         rtl_init_rxcfg(tp);
4143
4144         RTL_W8(EarlyTxThres, NoEarlyTx);
4145
4146         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4147
4148         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4149             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4150             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4151             tp->mac_version == RTL_GIGA_MAC_VER_04)
4152                 rtl_set_rx_tx_config_registers(tp);
4153
4154         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4155
4156         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4157             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4158                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4159                         "Bit-3 and bit-14 MUST be 1\n");
4160                 tp->cp_cmd |= (1 << 14);
4161         }
4162
4163         RTL_W16(CPlusCmd, tp->cp_cmd);
4164
4165         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4166
4167         /*
4168          * Undocumented corner. Supposedly:
4169          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4170          */
4171         RTL_W16(IntrMitigate, 0x0000);
4172
4173         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4174
4175         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4176             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4177             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4178             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4179                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4180                 rtl_set_rx_tx_config_registers(tp);
4181         }
4182
4183         RTL_W8(Cfg9346, Cfg9346_Lock);
4184
4185         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4186         RTL_R8(IntrMask);
4187
4188         RTL_W32(RxMissed, 0);
4189
4190         rtl_set_rx_mode(dev);
4191
4192         /* no early-rx interrupts */
4193         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4194 }
4195
4196 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4197 {
4198         u32 csi;
4199
4200         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4201         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4202 }
4203
4204 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4205 {
4206         rtl_csi_access_enable(ioaddr, 0x17000000);
4207 }
4208
4209 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4210 {
4211         rtl_csi_access_enable(ioaddr, 0x27000000);
4212 }
4213
4214 struct ephy_info {
4215         unsigned int offset;
4216         u16 mask;
4217         u16 bits;
4218 };
4219
4220 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4221 {
4222         u16 w;
4223
4224         while (len-- > 0) {
4225                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4226                 rtl_ephy_write(ioaddr, e->offset, w);
4227                 e++;
4228         }
4229 }
4230
4231 static void rtl_disable_clock_request(struct pci_dev *pdev)
4232 {
4233         int cap = pci_pcie_cap(pdev);
4234
4235         if (cap) {
4236                 u16 ctl;
4237
4238                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4239                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4240                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4241         }
4242 }
4243
4244 static void rtl_enable_clock_request(struct pci_dev *pdev)
4245 {
4246         int cap = pci_pcie_cap(pdev);
4247
4248         if (cap) {
4249                 u16 ctl;
4250
4251                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4252                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4253                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4254         }
4255 }
4256
4257 #define R8168_CPCMD_QUIRK_MASK (\
4258         EnableBist | \
4259         Mac_dbgo_oe | \
4260         Force_half_dup | \
4261         Force_rxflow_en | \
4262         Force_txflow_en | \
4263         Cxpl_dbg_sel | \
4264         ASF | \
4265         PktCntrDisable | \
4266         Mac_dbgo_sel)
4267
4268 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4269 {
4270         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4271
4272         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4273
4274         rtl_tx_performance_tweak(pdev,
4275                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4276 }
4277
4278 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4279 {
4280         rtl_hw_start_8168bb(ioaddr, pdev);
4281
4282         RTL_W8(MaxTxPacketSize, TxPacketMax);
4283
4284         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4285 }
4286
4287 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4288 {
4289         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4290
4291         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4292
4293         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4294
4295         rtl_disable_clock_request(pdev);
4296
4297         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4298 }
4299
4300 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4301 {
4302         static const struct ephy_info e_info_8168cp[] = {
4303                 { 0x01, 0,      0x0001 },
4304                 { 0x02, 0x0800, 0x1000 },
4305                 { 0x03, 0,      0x0042 },
4306                 { 0x06, 0x0080, 0x0000 },
4307                 { 0x07, 0,      0x2000 }
4308         };
4309
4310         rtl_csi_access_enable_2(ioaddr);
4311
4312         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4313
4314         __rtl_hw_start_8168cp(ioaddr, pdev);
4315 }
4316
4317 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4318 {
4319         rtl_csi_access_enable_2(ioaddr);
4320
4321         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4322
4323         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4324
4325         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4326 }
4327
4328 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4329 {
4330         rtl_csi_access_enable_2(ioaddr);
4331
4332         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4333
4334         /* Magic. */
4335         RTL_W8(DBG_REG, 0x20);
4336
4337         RTL_W8(MaxTxPacketSize, TxPacketMax);
4338
4339         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4340
4341         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4342 }
4343
4344 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4345 {
4346         static const struct ephy_info e_info_8168c_1[] = {
4347                 { 0x02, 0x0800, 0x1000 },
4348                 { 0x03, 0,      0x0002 },
4349                 { 0x06, 0x0080, 0x0000 }
4350         };
4351
4352         rtl_csi_access_enable_2(ioaddr);
4353
4354         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4355
4356         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4357
4358         __rtl_hw_start_8168cp(ioaddr, pdev);
4359 }
4360
4361 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4362 {
4363         static const struct ephy_info e_info_8168c_2[] = {
4364                 { 0x01, 0,      0x0001 },
4365                 { 0x03, 0x0400, 0x0220 }
4366         };
4367
4368         rtl_csi_access_enable_2(ioaddr);
4369
4370         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4371
4372         __rtl_hw_start_8168cp(ioaddr, pdev);
4373 }
4374
4375 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4376 {
4377         rtl_hw_start_8168c_2(ioaddr, pdev);
4378 }
4379
4380 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4381 {
4382         rtl_csi_access_enable_2(ioaddr);
4383
4384         __rtl_hw_start_8168cp(ioaddr, pdev);
4385 }
4386
4387 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4388 {
4389         rtl_csi_access_enable_2(ioaddr);
4390
4391         rtl_disable_clock_request(pdev);
4392
4393         RTL_W8(MaxTxPacketSize, TxPacketMax);
4394
4395         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4396
4397         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4398 }
4399
4400 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4401 {
4402         rtl_csi_access_enable_1(ioaddr);
4403
4404         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4405
4406         RTL_W8(MaxTxPacketSize, TxPacketMax);
4407
4408         rtl_disable_clock_request(pdev);
4409 }
4410
4411 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4412 {
4413         static const struct ephy_info e_info_8168d_4[] = {
4414                 { 0x0b, ~0,     0x48 },
4415                 { 0x19, 0x20,   0x50 },
4416                 { 0x0c, ~0,     0x20 }
4417         };
4418         int i;
4419
4420         rtl_csi_access_enable_1(ioaddr);
4421
4422         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4423
4424         RTL_W8(MaxTxPacketSize, TxPacketMax);
4425
4426         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4427                 const struct ephy_info *e = e_info_8168d_4 + i;
4428                 u16 w;
4429
4430                 w = rtl_ephy_read(ioaddr, e->offset);
4431                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4432         }
4433
4434         rtl_enable_clock_request(pdev);
4435 }
4436
4437 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4438 {
4439         static const struct ephy_info e_info_8168e_1[] = {
4440                 { 0x00, 0x0200, 0x0100 },
4441                 { 0x00, 0x0000, 0x0004 },
4442                 { 0x06, 0x0002, 0x0001 },
4443                 { 0x06, 0x0000, 0x0030 },
4444                 { 0x07, 0x0000, 0x2000 },
4445                 { 0x00, 0x0000, 0x0020 },
4446                 { 0x03, 0x5800, 0x2000 },
4447                 { 0x03, 0x0000, 0x0001 },
4448                 { 0x01, 0x0800, 0x1000 },
4449                 { 0x07, 0x0000, 0x4000 },
4450                 { 0x1e, 0x0000, 0x2000 },
4451                 { 0x19, 0xffff, 0xfe6c },
4452                 { 0x0a, 0x0000, 0x0040 }
4453         };
4454
4455         rtl_csi_access_enable_2(ioaddr);
4456
4457         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4458
4459         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4460
4461         RTL_W8(MaxTxPacketSize, TxPacketMax);
4462
4463         rtl_disable_clock_request(pdev);
4464
4465         /* Reset tx FIFO pointer */
4466         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4467         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4468
4469         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4470 }
4471
4472 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4473 {
4474         static const struct ephy_info e_info_8168e_2[] = {
4475                 { 0x09, 0x0000, 0x0080 },
4476                 { 0x19, 0x0000, 0x0224 }
4477         };
4478
4479         rtl_csi_access_enable_1(ioaddr);
4480
4481         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4482
4483         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4484
4485         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4486         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4487         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4488         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4489         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4490         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4491         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4492         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4493                      ERIAR_EXGMAC);
4494
4495         RTL_W8(MaxTxPacketSize, EarlySize);
4496
4497         rtl_disable_clock_request(pdev);
4498
4499         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4500         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4501
4502         /* Adjust EEE LED frequency */
4503         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4504
4505         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4506         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4507         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4508 }
4509
4510 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4511 {
4512         static const struct ephy_info e_info_8168f_1[] = {
4513                 { 0x06, 0x00c0, 0x0020 },
4514                 { 0x08, 0x0001, 0x0002 },
4515                 { 0x09, 0x0000, 0x0080 },
4516                 { 0x19, 0x0000, 0x0224 }
4517         };
4518
4519         rtl_csi_access_enable_1(ioaddr);
4520
4521         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4522
4523         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4524
4525         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4526         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4527         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4528         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4529         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4530         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4531         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4532         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4533         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4534         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4535         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4536                      ERIAR_EXGMAC);
4537
4538         RTL_W8(MaxTxPacketSize, EarlySize);
4539
4540         rtl_disable_clock_request(pdev);
4541
4542         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4543         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4544
4545         /* Adjust EEE LED frequency */
4546         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4547
4548         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4549         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4550         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4551 }
4552
4553 static void rtl_hw_start_8168(struct net_device *dev)
4554 {
4555         struct rtl8169_private *tp = netdev_priv(dev);
4556         void __iomem *ioaddr = tp->mmio_addr;
4557         struct pci_dev *pdev = tp->pci_dev;
4558
4559         RTL_W8(Cfg9346, Cfg9346_Unlock);
4560
4561         RTL_W8(MaxTxPacketSize, TxPacketMax);
4562
4563         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4564
4565         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4566
4567         RTL_W16(CPlusCmd, tp->cp_cmd);
4568
4569         RTL_W16(IntrMitigate, 0x5151);
4570
4571         /* Work around for RxFIFO overflow. */
4572         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4573                 tp->event_slow |= RxFIFOOver | PCSTimeout;
4574                 tp->event_slow &= ~RxOverflow;
4575         }
4576
4577         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4578
4579         rtl_set_rx_mode(dev);
4580
4581         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4582                 (InterFrameGap << TxInterFrameGapShift));
4583
4584         RTL_R8(IntrMask);
4585
4586         switch (tp->mac_version) {
4587         case RTL_GIGA_MAC_VER_11:
4588                 rtl_hw_start_8168bb(ioaddr, pdev);
4589                 break;
4590
4591         case RTL_GIGA_MAC_VER_12:
4592         case RTL_GIGA_MAC_VER_17:
4593                 rtl_hw_start_8168bef(ioaddr, pdev);
4594                 break;
4595
4596         case RTL_GIGA_MAC_VER_18:
4597                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4598                 break;
4599
4600         case RTL_GIGA_MAC_VER_19:
4601                 rtl_hw_start_8168c_1(ioaddr, pdev);
4602                 break;
4603
4604         case RTL_GIGA_MAC_VER_20:
4605                 rtl_hw_start_8168c_2(ioaddr, pdev);
4606                 break;
4607
4608         case RTL_GIGA_MAC_VER_21:
4609                 rtl_hw_start_8168c_3(ioaddr, pdev);
4610                 break;
4611
4612         case RTL_GIGA_MAC_VER_22:
4613                 rtl_hw_start_8168c_4(ioaddr, pdev);
4614                 break;
4615
4616         case RTL_GIGA_MAC_VER_23:
4617                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4618                 break;
4619
4620         case RTL_GIGA_MAC_VER_24:
4621                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4622                 break;
4623
4624         case RTL_GIGA_MAC_VER_25:
4625         case RTL_GIGA_MAC_VER_26:
4626         case RTL_GIGA_MAC_VER_27:
4627                 rtl_hw_start_8168d(ioaddr, pdev);
4628                 break;
4629
4630         case RTL_GIGA_MAC_VER_28:
4631                 rtl_hw_start_8168d_4(ioaddr, pdev);
4632                 break;
4633
4634         case RTL_GIGA_MAC_VER_31:
4635                 rtl_hw_start_8168dp(ioaddr, pdev);
4636                 break;
4637
4638         case RTL_GIGA_MAC_VER_32:
4639         case RTL_GIGA_MAC_VER_33:
4640                 rtl_hw_start_8168e_1(ioaddr, pdev);
4641                 break;
4642         case RTL_GIGA_MAC_VER_34:
4643                 rtl_hw_start_8168e_2(ioaddr, pdev);
4644                 break;
4645
4646         case RTL_GIGA_MAC_VER_35:
4647         case RTL_GIGA_MAC_VER_36:
4648                 rtl_hw_start_8168f_1(ioaddr, pdev);
4649                 break;
4650
4651         default:
4652                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4653                         dev->name, tp->mac_version);
4654                 break;
4655         }
4656
4657         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4658
4659         RTL_W8(Cfg9346, Cfg9346_Lock);
4660
4661         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4662 }
4663
4664 #define R810X_CPCMD_QUIRK_MASK (\
4665         EnableBist | \
4666         Mac_dbgo_oe | \
4667         Force_half_dup | \
4668         Force_rxflow_en | \
4669         Force_txflow_en | \
4670         Cxpl_dbg_sel | \
4671         ASF | \
4672         PktCntrDisable | \
4673         Mac_dbgo_sel)
4674
4675 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4676 {
4677         static const struct ephy_info e_info_8102e_1[] = {
4678                 { 0x01, 0, 0x6e65 },
4679                 { 0x02, 0, 0x091f },
4680                 { 0x03, 0, 0xc2f9 },
4681                 { 0x06, 0, 0xafb5 },
4682                 { 0x07, 0, 0x0e00 },
4683                 { 0x19, 0, 0xec80 },
4684                 { 0x01, 0, 0x2e65 },
4685                 { 0x01, 0, 0x6e65 }
4686         };
4687         u8 cfg1;
4688
4689         rtl_csi_access_enable_2(ioaddr);
4690
4691         RTL_W8(DBG_REG, FIX_NAK_1);
4692
4693         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4694
4695         RTL_W8(Config1,
4696                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4697         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4698
4699         cfg1 = RTL_R8(Config1);
4700         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4701                 RTL_W8(Config1, cfg1 & ~LEDS0);
4702
4703         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4704 }
4705
4706 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4707 {
4708         rtl_csi_access_enable_2(ioaddr);
4709
4710         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4711
4712         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4713         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4714 }
4715
4716 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4717 {
4718         rtl_hw_start_8102e_2(ioaddr, pdev);
4719
4720         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4721 }
4722
4723 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4724 {
4725         static const struct ephy_info e_info_8105e_1[] = {
4726                 { 0x07, 0, 0x4000 },
4727                 { 0x19, 0, 0x0200 },
4728                 { 0x19, 0, 0x0020 },
4729                 { 0x1e, 0, 0x2000 },
4730                 { 0x03, 0, 0x0001 },
4731                 { 0x19, 0, 0x0100 },
4732                 { 0x19, 0, 0x0004 },
4733                 { 0x0a, 0, 0x0020 }
4734         };
4735
4736         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4737         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4738
4739         /* Disable Early Tally Counter */
4740         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4741
4742         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4743         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4744
4745         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4746 }
4747
4748 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4749 {
4750         rtl_hw_start_8105e_1(ioaddr, pdev);
4751         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4752 }
4753
4754 static void rtl_hw_start_8101(struct net_device *dev)
4755 {
4756         struct rtl8169_private *tp = netdev_priv(dev);
4757         void __iomem *ioaddr = tp->mmio_addr;
4758         struct pci_dev *pdev = tp->pci_dev;
4759
4760         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
4761                 tp->event_slow &= ~RxFIFOOver;
4762
4763         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4764             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4765                 int cap = pci_pcie_cap(pdev);
4766
4767                 if (cap) {
4768                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4769                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4770                 }
4771         }
4772
4773         RTL_W8(Cfg9346, Cfg9346_Unlock);
4774
4775         switch (tp->mac_version) {
4776         case RTL_GIGA_MAC_VER_07:
4777                 rtl_hw_start_8102e_1(ioaddr, pdev);
4778                 break;
4779
4780         case RTL_GIGA_MAC_VER_08:
4781                 rtl_hw_start_8102e_3(ioaddr, pdev);
4782                 break;
4783
4784         case RTL_GIGA_MAC_VER_09:
4785                 rtl_hw_start_8102e_2(ioaddr, pdev);
4786                 break;
4787
4788         case RTL_GIGA_MAC_VER_29:
4789                 rtl_hw_start_8105e_1(ioaddr, pdev);
4790                 break;
4791         case RTL_GIGA_MAC_VER_30:
4792                 rtl_hw_start_8105e_2(ioaddr, pdev);
4793                 break;
4794         }
4795
4796         RTL_W8(Cfg9346, Cfg9346_Lock);
4797
4798         RTL_W8(MaxTxPacketSize, TxPacketMax);
4799
4800         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4801
4802         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4803         RTL_W16(CPlusCmd, tp->cp_cmd);
4804
4805         RTL_W16(IntrMitigate, 0x0000);
4806
4807         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4808
4809         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4810         rtl_set_rx_tx_config_registers(tp);
4811
4812         RTL_R8(IntrMask);
4813
4814         rtl_set_rx_mode(dev);
4815
4816         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4817 }
4818
4819 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4820 {
4821         struct rtl8169_private *tp = netdev_priv(dev);
4822
4823         if (new_mtu < ETH_ZLEN ||
4824             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4825                 return -EINVAL;
4826
4827         if (new_mtu > ETH_DATA_LEN)
4828                 rtl_hw_jumbo_enable(tp);
4829         else
4830                 rtl_hw_jumbo_disable(tp);
4831
4832         dev->mtu = new_mtu;
4833         netdev_update_features(dev);
4834
4835         return 0;
4836 }
4837
4838 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4839 {
4840         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4841         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4842 }
4843
4844 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4845                                      void **data_buff, struct RxDesc *desc)
4846 {
4847         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4848                          DMA_FROM_DEVICE);
4849
4850         kfree(*data_buff);
4851         *data_buff = NULL;
4852         rtl8169_make_unusable_by_asic(desc);
4853 }
4854
4855 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4856 {
4857         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4858
4859         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4860 }
4861
4862 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4863                                        u32 rx_buf_sz)
4864 {
4865         desc->addr = cpu_to_le64(mapping);
4866         wmb();
4867         rtl8169_mark_to_asic(desc, rx_buf_sz);
4868 }
4869
4870 static inline void *rtl8169_align(void *data)
4871 {
4872         return (void *)ALIGN((long)data, 16);
4873 }
4874
4875 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4876                                              struct RxDesc *desc)
4877 {
4878         void *data;
4879         dma_addr_t mapping;
4880         struct device *d = &tp->pci_dev->dev;
4881         struct net_device *dev = tp->dev;
4882         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4883
4884         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4885         if (!data)
4886                 return NULL;
4887
4888         if (rtl8169_align(data) != data) {
4889                 kfree(data);
4890                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4891                 if (!data)
4892                         return NULL;
4893         }
4894
4895         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4896                                  DMA_FROM_DEVICE);
4897         if (unlikely(dma_mapping_error(d, mapping))) {
4898                 if (net_ratelimit())
4899                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4900                 goto err_out;
4901         }
4902
4903         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4904         return data;
4905
4906 err_out:
4907         kfree(data);
4908         return NULL;
4909 }
4910
4911 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4912 {
4913         unsigned int i;
4914
4915         for (i = 0; i < NUM_RX_DESC; i++) {
4916                 if (tp->Rx_databuff[i]) {
4917                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4918                                             tp->RxDescArray + i);
4919                 }
4920         }
4921 }
4922
4923 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4924 {
4925         desc->opts1 |= cpu_to_le32(RingEnd);
4926 }
4927
4928 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4929 {
4930         unsigned int i;
4931
4932         for (i = 0; i < NUM_RX_DESC; i++) {
4933                 void *data;
4934
4935                 if (tp->Rx_databuff[i])
4936                         continue;
4937
4938                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4939                 if (!data) {
4940                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4941                         goto err_out;
4942                 }
4943                 tp->Rx_databuff[i] = data;
4944         }
4945
4946         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4947         return 0;
4948
4949 err_out:
4950         rtl8169_rx_clear(tp);
4951         return -ENOMEM;
4952 }
4953
4954 static int rtl8169_init_ring(struct net_device *dev)
4955 {
4956         struct rtl8169_private *tp = netdev_priv(dev);
4957
4958         rtl8169_init_ring_indexes(tp);
4959
4960         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4961         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4962
4963         return rtl8169_rx_fill(tp);
4964 }
4965
4966 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4967                                  struct TxDesc *desc)
4968 {
4969         unsigned int len = tx_skb->len;
4970
4971         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4972
4973         desc->opts1 = 0x00;
4974         desc->opts2 = 0x00;
4975         desc->addr = 0x00;
4976         tx_skb->len = 0;
4977 }
4978
4979 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4980                                    unsigned int n)
4981 {
4982         unsigned int i;
4983
4984         for (i = 0; i < n; i++) {
4985                 unsigned int entry = (start + i) % NUM_TX_DESC;
4986                 struct ring_info *tx_skb = tp->tx_skb + entry;
4987                 unsigned int len = tx_skb->len;
4988
4989                 if (len) {
4990                         struct sk_buff *skb = tx_skb->skb;
4991
4992                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4993                                              tp->TxDescArray + entry);
4994                         if (skb) {
4995                                 tp->dev->stats.tx_dropped++;
4996                                 dev_kfree_skb(skb);
4997                                 tx_skb->skb = NULL;
4998                         }
4999                 }
5000         }
5001 }
5002
5003 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5004 {
5005         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5006         tp->cur_tx = tp->dirty_tx = 0;
5007         netdev_reset_queue(tp->dev);
5008 }
5009
5010 static void rtl_reset_work(struct rtl8169_private *tp)
5011 {
5012         struct net_device *dev = tp->dev;
5013         int i;
5014
5015         napi_disable(&tp->napi);
5016         netif_stop_queue(dev);
5017         synchronize_sched();
5018
5019         rtl8169_hw_reset(tp);
5020
5021         for (i = 0; i < NUM_RX_DESC; i++)
5022                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5023
5024         rtl8169_tx_clear(tp);
5025         rtl8169_init_ring_indexes(tp);
5026
5027         napi_enable(&tp->napi);
5028         rtl_hw_start(dev);
5029         netif_wake_queue(dev);
5030         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5031 }
5032
5033 static void rtl8169_tx_timeout(struct net_device *dev)
5034 {
5035         struct rtl8169_private *tp = netdev_priv(dev);
5036
5037         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5038 }
5039
5040 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5041                               u32 *opts)
5042 {
5043         struct skb_shared_info *info = skb_shinfo(skb);
5044         unsigned int cur_frag, entry;
5045         struct TxDesc * uninitialized_var(txd);
5046         struct device *d = &tp->pci_dev->dev;
5047
5048         entry = tp->cur_tx;
5049         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5050                 const skb_frag_t *frag = info->frags + cur_frag;
5051                 dma_addr_t mapping;
5052                 u32 status, len;
5053                 void *addr;
5054
5055                 entry = (entry + 1) % NUM_TX_DESC;
5056
5057                 txd = tp->TxDescArray + entry;
5058                 len = skb_frag_size(frag);
5059                 addr = skb_frag_address(frag);
5060                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5061                 if (unlikely(dma_mapping_error(d, mapping))) {
5062                         if (net_ratelimit())
5063                                 netif_err(tp, drv, tp->dev,
5064                                           "Failed to map TX fragments DMA!\n");
5065                         goto err_out;
5066                 }
5067
5068                 /* Anti gcc 2.95.3 bugware (sic) */
5069                 status = opts[0] | len |
5070                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5071
5072                 txd->opts1 = cpu_to_le32(status);
5073                 txd->opts2 = cpu_to_le32(opts[1]);
5074                 txd->addr = cpu_to_le64(mapping);
5075
5076                 tp->tx_skb[entry].len = len;
5077         }
5078
5079         if (cur_frag) {
5080                 tp->tx_skb[entry].skb = skb;
5081                 txd->opts1 |= cpu_to_le32(LastFrag);
5082         }
5083
5084         return cur_frag;
5085
5086 err_out:
5087         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5088         return -EIO;
5089 }
5090
5091 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5092                                     struct sk_buff *skb, u32 *opts)
5093 {
5094         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5095         u32 mss = skb_shinfo(skb)->gso_size;
5096         int offset = info->opts_offset;
5097
5098         if (mss) {
5099                 opts[0] |= TD_LSO;
5100                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5101         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5102                 const struct iphdr *ip = ip_hdr(skb);
5103
5104                 if (ip->protocol == IPPROTO_TCP)
5105                         opts[offset] |= info->checksum.tcp;
5106                 else if (ip->protocol == IPPROTO_UDP)
5107                         opts[offset] |= info->checksum.udp;
5108                 else
5109                         WARN_ON_ONCE(1);
5110         }
5111 }
5112
5113 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5114                                       struct net_device *dev)
5115 {
5116         struct rtl8169_private *tp = netdev_priv(dev);
5117         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5118         struct TxDesc *txd = tp->TxDescArray + entry;
5119         void __iomem *ioaddr = tp->mmio_addr;
5120         struct device *d = &tp->pci_dev->dev;
5121         dma_addr_t mapping;
5122         u32 status, len;
5123         u32 opts[2];
5124         int frags;
5125
5126         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5127                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5128                 goto err_stop_0;
5129         }
5130
5131         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5132                 goto err_stop_0;
5133
5134         len = skb_headlen(skb);
5135         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5136         if (unlikely(dma_mapping_error(d, mapping))) {
5137                 if (net_ratelimit())
5138                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5139                 goto err_dma_0;
5140         }
5141
5142         tp->tx_skb[entry].len = len;
5143         txd->addr = cpu_to_le64(mapping);
5144
5145         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5146         opts[0] = DescOwn;
5147
5148         rtl8169_tso_csum(tp, skb, opts);
5149
5150         frags = rtl8169_xmit_frags(tp, skb, opts);
5151         if (frags < 0)
5152                 goto err_dma_1;
5153         else if (frags)
5154                 opts[0] |= FirstFrag;
5155         else {
5156                 opts[0] |= FirstFrag | LastFrag;
5157                 tp->tx_skb[entry].skb = skb;
5158         }
5159
5160         txd->opts2 = cpu_to_le32(opts[1]);
5161
5162         netdev_sent_queue(dev, skb->len);
5163
5164         skb_tx_timestamp(skb);
5165
5166         wmb();
5167
5168         /* Anti gcc 2.95.3 bugware (sic) */
5169         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5170         txd->opts1 = cpu_to_le32(status);
5171
5172         tp->cur_tx += frags + 1;
5173
5174         wmb();
5175
5176         RTL_W8(TxPoll, NPQ);
5177
5178         mmiowb();
5179
5180         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5181                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5182                  * not miss a ring update when it notices a stopped queue.
5183                  */
5184                 smp_wmb();
5185                 netif_stop_queue(dev);
5186                 /* Sync with rtl_tx:
5187                  * - publish queue status and cur_tx ring index (write barrier)
5188                  * - refresh dirty_tx ring index (read barrier).
5189                  * May the current thread have a pessimistic view of the ring
5190                  * status and forget to wake up queue, a racing rtl_tx thread
5191                  * can't.
5192                  */
5193                 smp_mb();
5194                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
5195                         netif_wake_queue(dev);
5196         }
5197
5198         return NETDEV_TX_OK;
5199
5200 err_dma_1:
5201         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5202 err_dma_0:
5203         dev_kfree_skb(skb);
5204         dev->stats.tx_dropped++;
5205         return NETDEV_TX_OK;
5206
5207 err_stop_0:
5208         netif_stop_queue(dev);
5209         dev->stats.tx_dropped++;
5210         return NETDEV_TX_BUSY;
5211 }
5212
5213 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5214 {
5215         struct rtl8169_private *tp = netdev_priv(dev);
5216         struct pci_dev *pdev = tp->pci_dev;
5217         u16 pci_status, pci_cmd;
5218
5219         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5220         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5221
5222         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5223                   pci_cmd, pci_status);
5224
5225         /*
5226          * The recovery sequence below admits a very elaborated explanation:
5227          * - it seems to work;
5228          * - I did not see what else could be done;
5229          * - it makes iop3xx happy.
5230          *
5231          * Feel free to adjust to your needs.
5232          */
5233         if (pdev->broken_parity_status)
5234                 pci_cmd &= ~PCI_COMMAND_PARITY;
5235         else
5236                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5237
5238         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5239
5240         pci_write_config_word(pdev, PCI_STATUS,
5241                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5242                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5243                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5244
5245         /* The infamous DAC f*ckup only happens at boot time */
5246         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5247                 void __iomem *ioaddr = tp->mmio_addr;
5248
5249                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5250                 tp->cp_cmd &= ~PCIDAC;
5251                 RTL_W16(CPlusCmd, tp->cp_cmd);
5252                 dev->features &= ~NETIF_F_HIGHDMA;
5253         }
5254
5255         rtl8169_hw_reset(tp);
5256
5257         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5258 }
5259
5260 struct rtl_txc {
5261         int packets;
5262         int bytes;
5263 };
5264
5265 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
5266 {
5267         struct rtl8169_stats *tx_stats = &tp->tx_stats;
5268         unsigned int dirty_tx, tx_left;
5269         struct rtl_txc txc = { 0, 0 };
5270
5271         dirty_tx = tp->dirty_tx;
5272         smp_rmb();
5273         tx_left = tp->cur_tx - dirty_tx;
5274
5275         while (tx_left > 0) {
5276                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5277                 struct ring_info *tx_skb = tp->tx_skb + entry;
5278                 u32 status;
5279
5280                 rmb();
5281                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5282                 if (status & DescOwn)
5283                         break;
5284
5285                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5286                                      tp->TxDescArray + entry);
5287                 if (status & LastFrag) {
5288                         struct sk_buff *skb = tx_skb->skb;
5289
5290                         txc.packets++;
5291                         txc.bytes += skb->len;
5292                         dev_kfree_skb(skb);
5293                         tx_skb->skb = NULL;
5294                 }
5295                 dirty_tx++;
5296                 tx_left--;
5297         }
5298
5299         u64_stats_update_begin(&tx_stats->syncp);
5300         tx_stats->packets += txc.packets;
5301         tx_stats->bytes += txc.bytes;
5302         u64_stats_update_end(&tx_stats->syncp);
5303
5304         netdev_completed_queue(dev, txc.packets, txc.bytes);
5305
5306         if (tp->dirty_tx != dirty_tx) {
5307                 tp->dirty_tx = dirty_tx;
5308                 /* Sync with rtl8169_start_xmit:
5309                  * - publish dirty_tx ring index (write barrier)
5310                  * - refresh cur_tx ring index and queue status (read barrier)
5311                  * May the current thread miss the stopped queue condition,
5312                  * a racing xmit thread can only have a right view of the
5313                  * ring status.
5314                  */
5315                 smp_mb();
5316                 if (netif_queue_stopped(dev) &&
5317                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5318                         netif_wake_queue(dev);
5319                 }
5320                 /*
5321                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5322                  * too close. Let's kick an extra TxPoll request when a burst
5323                  * of start_xmit activity is detected (if it is not detected,
5324                  * it is slow enough). -- FR
5325                  */
5326                 if (tp->cur_tx != dirty_tx) {
5327                         void __iomem *ioaddr = tp->mmio_addr;
5328
5329                         RTL_W8(TxPoll, NPQ);
5330                 }
5331         }
5332 }
5333
5334 static inline int rtl8169_fragmented_frame(u32 status)
5335 {
5336         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5337 }
5338
5339 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5340 {
5341         u32 status = opts1 & RxProtoMask;
5342
5343         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5344             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5345                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5346         else
5347                 skb_checksum_none_assert(skb);
5348 }
5349
5350 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5351                                            struct rtl8169_private *tp,
5352                                            int pkt_size,
5353                                            dma_addr_t addr)
5354 {
5355         struct sk_buff *skb;
5356         struct device *d = &tp->pci_dev->dev;
5357
5358         data = rtl8169_align(data);
5359         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5360         prefetch(data);
5361         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5362         if (skb)
5363                 memcpy(skb->data, data, pkt_size);
5364         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5365
5366         return skb;
5367 }
5368
5369 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5370 {
5371         unsigned int cur_rx, rx_left;
5372         unsigned int count;
5373
5374         cur_rx = tp->cur_rx;
5375         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5376         rx_left = min(rx_left, budget);
5377
5378         for (; rx_left > 0; rx_left--, cur_rx++) {
5379                 unsigned int entry = cur_rx % NUM_RX_DESC;
5380                 struct RxDesc *desc = tp->RxDescArray + entry;
5381                 u32 status;
5382
5383                 rmb();
5384                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5385
5386                 if (status & DescOwn)
5387                         break;
5388                 if (unlikely(status & RxRES)) {
5389                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5390                                    status);
5391                         dev->stats.rx_errors++;
5392                         if (status & (RxRWT | RxRUNT))
5393                                 dev->stats.rx_length_errors++;
5394                         if (status & RxCRC)
5395                                 dev->stats.rx_crc_errors++;
5396                         if (status & RxFOVF) {
5397                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5398                                 dev->stats.rx_fifo_errors++;
5399                         }
5400                         if ((status & (RxRUNT | RxCRC)) &&
5401                             !(status & (RxRWT | RxFOVF)) &&
5402                             (dev->features & NETIF_F_RXALL))
5403                                 goto process_pkt;
5404
5405                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5406                 } else {
5407                         struct sk_buff *skb;
5408                         dma_addr_t addr;
5409                         int pkt_size;
5410
5411 process_pkt:
5412                         addr = le64_to_cpu(desc->addr);
5413                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5414                                 pkt_size = (status & 0x00003fff) - 4;
5415                         else
5416                                 pkt_size = status & 0x00003fff;
5417
5418                         /*
5419                          * The driver does not support incoming fragmented
5420                          * frames. They are seen as a symptom of over-mtu
5421                          * sized frames.
5422                          */
5423                         if (unlikely(rtl8169_fragmented_frame(status))) {
5424                                 dev->stats.rx_dropped++;
5425                                 dev->stats.rx_length_errors++;
5426                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5427                                 continue;
5428                         }
5429
5430                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5431                                                   tp, pkt_size, addr);
5432                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5433                         if (!skb) {
5434                                 dev->stats.rx_dropped++;
5435                                 continue;
5436                         }
5437
5438                         rtl8169_rx_csum(skb, status);
5439                         skb_put(skb, pkt_size);
5440                         skb->protocol = eth_type_trans(skb, dev);
5441
5442                         rtl8169_rx_vlan_tag(desc, skb);
5443
5444                         napi_gro_receive(&tp->napi, skb);
5445
5446                         u64_stats_update_begin(&tp->rx_stats.syncp);
5447                         tp->rx_stats.packets++;
5448                         tp->rx_stats.bytes += pkt_size;
5449                         u64_stats_update_end(&tp->rx_stats.syncp);
5450                 }
5451
5452                 /* Work around for AMD plateform. */
5453                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5454                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5455                         desc->opts2 = 0;
5456                         cur_rx++;
5457                 }
5458         }
5459
5460         count = cur_rx - tp->cur_rx;
5461         tp->cur_rx = cur_rx;
5462
5463         tp->dirty_rx += count;
5464
5465         return count;
5466 }
5467
5468 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5469 {
5470         struct net_device *dev = dev_instance;
5471         struct rtl8169_private *tp = netdev_priv(dev);
5472         int handled = 0;
5473         u16 status;
5474
5475         status = rtl_get_events(tp);
5476         if (status && status != 0xffff) {
5477                 status &= RTL_EVENT_NAPI | tp->event_slow;
5478                 if (status) {
5479                         handled = 1;
5480
5481                         rtl_irq_disable(tp);
5482                         napi_schedule(&tp->napi);
5483                 }
5484         }
5485         return IRQ_RETVAL(handled);
5486 }
5487
5488 /*
5489  * Workqueue context.
5490  */
5491 static void rtl_slow_event_work(struct rtl8169_private *tp)
5492 {
5493         struct net_device *dev = tp->dev;
5494         u16 status;
5495
5496         status = rtl_get_events(tp) & tp->event_slow;
5497         rtl_ack_events(tp, status);
5498
5499         if (unlikely(status & RxFIFOOver)) {
5500                 switch (tp->mac_version) {
5501                 /* Work around for rx fifo overflow */
5502                 case RTL_GIGA_MAC_VER_11:
5503                         netif_stop_queue(dev);
5504                         /* XXX - Hack alert. See rtl_task(). */
5505                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
5506                 default:
5507                         break;
5508                 }
5509         }
5510
5511         if (unlikely(status & SYSErr))
5512                 rtl8169_pcierr_interrupt(dev);
5513
5514         if (status & LinkChg)
5515                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5516
5517         napi_disable(&tp->napi);
5518         rtl_irq_disable(tp);
5519
5520         napi_enable(&tp->napi);
5521         napi_schedule(&tp->napi);
5522 }
5523
5524 static void rtl_task(struct work_struct *work)
5525 {
5526         static const struct {
5527                 int bitnr;
5528                 void (*action)(struct rtl8169_private *);
5529         } rtl_work[] = {
5530                 /* XXX - keep rtl_slow_event_work() as first element. */
5531                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
5532                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
5533                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
5534         };
5535         struct rtl8169_private *tp =
5536                 container_of(work, struct rtl8169_private, wk.work);
5537         struct net_device *dev = tp->dev;
5538         int i;
5539
5540         rtl_lock_work(tp);
5541
5542         if (!netif_running(dev) ||
5543             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
5544                 goto out_unlock;
5545
5546         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
5547                 bool pending;
5548
5549                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
5550                 if (pending)
5551                         rtl_work[i].action(tp);
5552         }
5553
5554 out_unlock:
5555         rtl_unlock_work(tp);
5556 }
5557
5558 static int rtl8169_poll(struct napi_struct *napi, int budget)
5559 {
5560         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5561         struct net_device *dev = tp->dev;
5562         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
5563         int work_done= 0;
5564         u16 status;
5565
5566         status = rtl_get_events(tp);
5567         rtl_ack_events(tp, status & ~tp->event_slow);
5568
5569         if (status & RTL_EVENT_NAPI_RX)
5570                 work_done = rtl_rx(dev, tp, (u32) budget);
5571
5572         if (status & RTL_EVENT_NAPI_TX)
5573                 rtl_tx(dev, tp);
5574
5575         if (status & tp->event_slow) {
5576                 enable_mask &= ~tp->event_slow;
5577
5578                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
5579         }
5580
5581         if (work_done < budget) {
5582                 napi_complete(napi);
5583
5584                 rtl_irq_enable(tp, enable_mask);
5585                 mmiowb();
5586         }
5587
5588         return work_done;
5589 }
5590
5591 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5592 {
5593         struct rtl8169_private *tp = netdev_priv(dev);
5594
5595         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5596                 return;
5597
5598         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5599         RTL_W32(RxMissed, 0);
5600 }
5601
5602 static void rtl8169_down(struct net_device *dev)
5603 {
5604         struct rtl8169_private *tp = netdev_priv(dev);
5605         void __iomem *ioaddr = tp->mmio_addr;
5606
5607         del_timer_sync(&tp->timer);
5608
5609         napi_disable(&tp->napi);
5610         netif_stop_queue(dev);
5611
5612         rtl8169_hw_reset(tp);
5613         /*
5614          * At this point device interrupts can not be enabled in any function,
5615          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5616          * and napi is disabled (rtl8169_poll).
5617          */
5618         rtl8169_rx_missed(dev, ioaddr);
5619
5620         /* Give a racing hard_start_xmit a few cycles to complete. */
5621         synchronize_sched();
5622
5623         rtl8169_tx_clear(tp);
5624
5625         rtl8169_rx_clear(tp);
5626
5627         rtl_pll_power_down(tp);
5628 }
5629
5630 static int rtl8169_close(struct net_device *dev)
5631 {
5632         struct rtl8169_private *tp = netdev_priv(dev);
5633         struct pci_dev *pdev = tp->pci_dev;
5634
5635         pm_runtime_get_sync(&pdev->dev);
5636
5637         /* Update counters before going down */
5638         rtl8169_update_counters(dev);
5639
5640         rtl_lock_work(tp);
5641         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5642
5643         rtl8169_down(dev);
5644         rtl_unlock_work(tp);
5645
5646         free_irq(pdev->irq, dev);
5647
5648         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5649                           tp->RxPhyAddr);
5650         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5651                           tp->TxPhyAddr);
5652         tp->TxDescArray = NULL;
5653         tp->RxDescArray = NULL;
5654
5655         pm_runtime_put_sync(&pdev->dev);
5656
5657         return 0;
5658 }
5659
5660 #ifdef CONFIG_NET_POLL_CONTROLLER
5661 static void rtl8169_netpoll(struct net_device *dev)
5662 {
5663         struct rtl8169_private *tp = netdev_priv(dev);
5664
5665         rtl8169_interrupt(tp->pci_dev->irq, dev);
5666 }
5667 #endif
5668
5669 static int rtl_open(struct net_device *dev)
5670 {
5671         struct rtl8169_private *tp = netdev_priv(dev);
5672         void __iomem *ioaddr = tp->mmio_addr;
5673         struct pci_dev *pdev = tp->pci_dev;
5674         int retval = -ENOMEM;
5675
5676         pm_runtime_get_sync(&pdev->dev);
5677
5678         /*
5679          * Rx and Tx desscriptors needs 256 bytes alignment.
5680          * dma_alloc_coherent provides more.
5681          */
5682         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
5683                                              &tp->TxPhyAddr, GFP_KERNEL);
5684         if (!tp->TxDescArray)
5685                 goto err_pm_runtime_put;
5686
5687         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
5688                                              &tp->RxPhyAddr, GFP_KERNEL);
5689         if (!tp->RxDescArray)
5690                 goto err_free_tx_0;
5691
5692         retval = rtl8169_init_ring(dev);
5693         if (retval < 0)
5694                 goto err_free_rx_1;
5695
5696         INIT_WORK(&tp->wk.work, rtl_task);
5697
5698         smp_mb();
5699
5700         rtl_request_firmware(tp);
5701
5702         retval = request_irq(pdev->irq, rtl8169_interrupt,
5703                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
5704                              dev->name, dev);
5705         if (retval < 0)
5706                 goto err_release_fw_2;
5707
5708         rtl_lock_work(tp);
5709
5710         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5711
5712         napi_enable(&tp->napi);
5713
5714         rtl8169_init_phy(dev, tp);
5715
5716         __rtl8169_set_features(dev, dev->features);
5717
5718         rtl_pll_power_up(tp);
5719
5720         rtl_hw_start(dev);
5721
5722         netif_start_queue(dev);
5723
5724         rtl_unlock_work(tp);
5725
5726         tp->saved_wolopts = 0;
5727         pm_runtime_put_noidle(&pdev->dev);
5728
5729         rtl8169_check_link_status(dev, tp, ioaddr);
5730 out:
5731         return retval;
5732
5733 err_release_fw_2:
5734         rtl_release_firmware(tp);
5735         rtl8169_rx_clear(tp);
5736 err_free_rx_1:
5737         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5738                           tp->RxPhyAddr);
5739         tp->RxDescArray = NULL;
5740 err_free_tx_0:
5741         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5742                           tp->TxPhyAddr);
5743         tp->TxDescArray = NULL;
5744 err_pm_runtime_put:
5745         pm_runtime_put_noidle(&pdev->dev);
5746         goto out;
5747 }
5748
5749 static struct rtnl_link_stats64 *
5750 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5751 {
5752         struct rtl8169_private *tp = netdev_priv(dev);
5753         void __iomem *ioaddr = tp->mmio_addr;
5754         unsigned int start;
5755
5756         if (netif_running(dev))
5757                 rtl8169_rx_missed(dev, ioaddr);
5758
5759         do {
5760                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
5761                 stats->rx_packets = tp->rx_stats.packets;
5762                 stats->rx_bytes = tp->rx_stats.bytes;
5763         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
5764
5765
5766         do {
5767                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
5768                 stats->tx_packets = tp->tx_stats.packets;
5769                 stats->tx_bytes = tp->tx_stats.bytes;
5770         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
5771
5772         stats->rx_dropped       = dev->stats.rx_dropped;
5773         stats->tx_dropped       = dev->stats.tx_dropped;
5774         stats->rx_length_errors = dev->stats.rx_length_errors;
5775         stats->rx_errors        = dev->stats.rx_errors;
5776         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
5777         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
5778         stats->rx_missed_errors = dev->stats.rx_missed_errors;
5779
5780         return stats;
5781 }
5782
5783 static void rtl8169_net_suspend(struct net_device *dev)
5784 {
5785         struct rtl8169_private *tp = netdev_priv(dev);
5786
5787         if (!netif_running(dev))
5788                 return;
5789
5790         netif_device_detach(dev);
5791         netif_stop_queue(dev);
5792
5793         rtl_lock_work(tp);
5794         napi_disable(&tp->napi);
5795         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5796         rtl_unlock_work(tp);
5797
5798         rtl_pll_power_down(tp);
5799 }
5800
5801 #ifdef CONFIG_PM
5802
5803 static int rtl8169_suspend(struct device *device)
5804 {
5805         struct pci_dev *pdev = to_pci_dev(device);
5806         struct net_device *dev = pci_get_drvdata(pdev);
5807
5808         rtl8169_net_suspend(dev);
5809
5810         return 0;
5811 }
5812
5813 static void __rtl8169_resume(struct net_device *dev)
5814 {
5815         struct rtl8169_private *tp = netdev_priv(dev);
5816
5817         netif_device_attach(dev);
5818
5819         rtl_pll_power_up(tp);
5820
5821         rtl_lock_work(tp);
5822         napi_enable(&tp->napi);
5823         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
5824         rtl_unlock_work(tp);
5825
5826         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5827 }
5828
5829 static int rtl8169_resume(struct device *device)
5830 {
5831         struct pci_dev *pdev = to_pci_dev(device);
5832         struct net_device *dev = pci_get_drvdata(pdev);
5833         struct rtl8169_private *tp = netdev_priv(dev);
5834
5835         rtl8169_init_phy(dev, tp);
5836
5837         if (netif_running(dev))
5838                 __rtl8169_resume(dev);
5839
5840         return 0;
5841 }
5842
5843 static int rtl8169_runtime_suspend(struct device *device)
5844 {
5845         struct pci_dev *pdev = to_pci_dev(device);
5846         struct net_device *dev = pci_get_drvdata(pdev);
5847         struct rtl8169_private *tp = netdev_priv(dev);
5848
5849         if (!tp->TxDescArray)
5850                 return 0;
5851
5852         rtl_lock_work(tp);
5853         tp->saved_wolopts = __rtl8169_get_wol(tp);
5854         __rtl8169_set_wol(tp, WAKE_ANY);
5855         rtl_unlock_work(tp);
5856
5857         rtl8169_net_suspend(dev);
5858
5859         return 0;
5860 }
5861
5862 static int rtl8169_runtime_resume(struct device *device)
5863 {
5864         struct pci_dev *pdev = to_pci_dev(device);
5865         struct net_device *dev = pci_get_drvdata(pdev);
5866         struct rtl8169_private *tp = netdev_priv(dev);
5867
5868         if (!tp->TxDescArray)
5869                 return 0;
5870
5871         rtl_lock_work(tp);
5872         __rtl8169_set_wol(tp, tp->saved_wolopts);
5873         tp->saved_wolopts = 0;
5874         rtl_unlock_work(tp);
5875
5876         rtl8169_init_phy(dev, tp);
5877
5878         __rtl8169_resume(dev);
5879
5880         return 0;
5881 }
5882
5883 static int rtl8169_runtime_idle(struct device *device)
5884 {
5885         struct pci_dev *pdev = to_pci_dev(device);
5886         struct net_device *dev = pci_get_drvdata(pdev);
5887         struct rtl8169_private *tp = netdev_priv(dev);
5888
5889         __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
5890         return tp->TxDescArray ? -EBUSY : 0;
5891 }
5892
5893 static const struct dev_pm_ops rtl8169_pm_ops = {
5894         .suspend                = rtl8169_suspend,
5895         .resume                 = rtl8169_resume,
5896         .freeze                 = rtl8169_suspend,
5897         .thaw                   = rtl8169_resume,
5898         .poweroff               = rtl8169_suspend,
5899         .restore                = rtl8169_resume,
5900         .runtime_suspend        = rtl8169_runtime_suspend,
5901         .runtime_resume         = rtl8169_runtime_resume,
5902         .runtime_idle           = rtl8169_runtime_idle,
5903 };
5904
5905 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5906
5907 #else /* !CONFIG_PM */
5908
5909 #define RTL8169_PM_OPS  NULL
5910
5911 #endif /* !CONFIG_PM */
5912
5913 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5914 {
5915         void __iomem *ioaddr = tp->mmio_addr;
5916
5917         /* WoL fails with 8168b when the receiver is disabled. */
5918         switch (tp->mac_version) {
5919         case RTL_GIGA_MAC_VER_11:
5920         case RTL_GIGA_MAC_VER_12:
5921         case RTL_GIGA_MAC_VER_17:
5922                 pci_clear_master(tp->pci_dev);
5923
5924                 RTL_W8(ChipCmd, CmdRxEnb);
5925                 /* PCI commit */
5926                 RTL_R8(ChipCmd);
5927                 break;
5928         default:
5929                 break;
5930         }
5931 }
5932
5933 static void rtl_shutdown(struct pci_dev *pdev)
5934 {
5935         struct net_device *dev = pci_get_drvdata(pdev);
5936         struct rtl8169_private *tp = netdev_priv(dev);
5937         struct device *d = &pdev->dev;
5938
5939         pm_runtime_get_sync(d);
5940
5941         rtl8169_net_suspend(dev);
5942
5943         /* Restore original MAC address */
5944         rtl_rar_set(tp, dev->perm_addr);
5945
5946         rtl8169_hw_reset(tp);
5947
5948         if (system_state == SYSTEM_POWER_OFF) {
5949                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
5950                         rtl_wol_suspend_quirk(tp);
5951                         rtl_wol_shutdown_quirk(tp);
5952                 }
5953
5954                 pci_wake_from_d3(pdev, true);
5955                 pci_set_power_state(pdev, PCI_D3hot);
5956         }
5957
5958         pm_runtime_put_noidle(d);
5959 }
5960
5961 static void __devexit rtl_remove_one(struct pci_dev *pdev)
5962 {
5963         struct net_device *dev = pci_get_drvdata(pdev);
5964         struct rtl8169_private *tp = netdev_priv(dev);
5965
5966         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5967             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5968             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5969                 rtl8168_driver_stop(tp);
5970         }
5971
5972         cancel_work_sync(&tp->wk.work);
5973
5974         unregister_netdev(dev);
5975
5976         rtl_release_firmware(tp);
5977
5978         if (pci_dev_run_wake(pdev))
5979                 pm_runtime_get_noresume(&pdev->dev);
5980
5981         /* restore original MAC address */
5982         rtl_rar_set(tp, dev->perm_addr);
5983
5984         rtl_disable_msi(pdev, tp);
5985         rtl8169_release_board(pdev, dev, tp->mmio_addr);
5986         pci_set_drvdata(pdev, NULL);
5987 }
5988
5989 static const struct net_device_ops rtl_netdev_ops = {
5990         .ndo_open               = rtl_open,
5991         .ndo_stop               = rtl8169_close,
5992         .ndo_get_stats64        = rtl8169_get_stats64,
5993         .ndo_start_xmit         = rtl8169_start_xmit,
5994         .ndo_tx_timeout         = rtl8169_tx_timeout,
5995         .ndo_validate_addr      = eth_validate_addr,
5996         .ndo_change_mtu         = rtl8169_change_mtu,
5997         .ndo_fix_features       = rtl8169_fix_features,
5998         .ndo_set_features       = rtl8169_set_features,
5999         .ndo_set_mac_address    = rtl_set_mac_address,
6000         .ndo_do_ioctl           = rtl8169_ioctl,
6001         .ndo_set_rx_mode        = rtl_set_rx_mode,
6002 #ifdef CONFIG_NET_POLL_CONTROLLER
6003         .ndo_poll_controller    = rtl8169_netpoll,
6004 #endif
6005
6006 };
6007
6008 static const struct rtl_cfg_info {
6009         void (*hw_start)(struct net_device *);
6010         unsigned int region;
6011         unsigned int align;
6012         u16 event_slow;
6013         unsigned features;
6014         u8 default_ver;
6015 } rtl_cfg_infos [] = {
6016         [RTL_CFG_0] = {
6017                 .hw_start       = rtl_hw_start_8169,
6018                 .region         = 1,
6019                 .align          = 0,
6020                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6021                 .features       = RTL_FEATURE_GMII,
6022                 .default_ver    = RTL_GIGA_MAC_VER_01,
6023         },
6024         [RTL_CFG_1] = {
6025                 .hw_start       = rtl_hw_start_8168,
6026                 .region         = 2,
6027                 .align          = 8,
6028                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6029                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6030                 .default_ver    = RTL_GIGA_MAC_VER_11,
6031         },
6032         [RTL_CFG_2] = {
6033                 .hw_start       = rtl_hw_start_8101,
6034                 .region         = 2,
6035                 .align          = 8,
6036                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6037                                   PCSTimeout,
6038                 .features       = RTL_FEATURE_MSI,
6039                 .default_ver    = RTL_GIGA_MAC_VER_13,
6040         }
6041 };
6042
6043 /* Cfg9346_Unlock assumed. */
6044 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6045                             const struct rtl_cfg_info *cfg)
6046 {
6047         void __iomem *ioaddr = tp->mmio_addr;
6048         unsigned msi = 0;
6049         u8 cfg2;
6050
6051         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6052         if (cfg->features & RTL_FEATURE_MSI) {
6053                 if (pci_enable_msi(tp->pci_dev)) {
6054                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6055                 } else {
6056                         cfg2 |= MSIEnable;
6057                         msi = RTL_FEATURE_MSI;
6058                 }
6059         }
6060         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6061                 RTL_W8(Config2, cfg2);
6062         return msi;
6063 }
6064
6065 static int __devinit
6066 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6067 {
6068         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6069         const unsigned int region = cfg->region;
6070         struct rtl8169_private *tp;
6071         struct mii_if_info *mii;
6072         struct net_device *dev;
6073         void __iomem *ioaddr;
6074         int chipset, i;
6075         int rc;
6076
6077         if (netif_msg_drv(&debug)) {
6078                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6079                        MODULENAME, RTL8169_VERSION);
6080         }
6081
6082         dev = alloc_etherdev(sizeof (*tp));
6083         if (!dev) {
6084                 rc = -ENOMEM;
6085                 goto out;
6086         }
6087
6088         SET_NETDEV_DEV(dev, &pdev->dev);
6089         dev->netdev_ops = &rtl_netdev_ops;
6090         tp = netdev_priv(dev);
6091         tp->dev = dev;
6092         tp->pci_dev = pdev;
6093         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6094
6095         mii = &tp->mii;
6096         mii->dev = dev;
6097         mii->mdio_read = rtl_mdio_read;
6098         mii->mdio_write = rtl_mdio_write;
6099         mii->phy_id_mask = 0x1f;
6100         mii->reg_num_mask = 0x1f;
6101         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6102
6103         /* disable ASPM completely as that cause random device stop working
6104          * problems as well as full system hangs for some PCIe devices users */
6105         if (aspm_disable) {
6106                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6107                                        PCIE_LINK_STATE_L1 |
6108                                        PCIE_LINK_STATE_CLKPM);
6109                 dprintk("ASPM disabled");
6110         }
6111
6112         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6113         rc = pci_enable_device(pdev);
6114         if (rc < 0) {
6115                 netif_err(tp, probe, dev, "enable failure\n");
6116                 goto err_out_free_dev_1;
6117         }
6118
6119         if (pci_set_mwi(pdev) < 0)
6120                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
6121
6122         /* make sure PCI base addr 1 is MMIO */
6123         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
6124                 netif_err(tp, probe, dev,
6125                           "region #%d not an MMIO resource, aborting\n",
6126                           region);
6127                 rc = -ENODEV;
6128                 goto err_out_mwi_2;
6129         }
6130
6131         /* check for weird/broken PCI region reporting */
6132         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6133                 netif_err(tp, probe, dev,
6134                           "Invalid PCI region size(s), aborting\n");
6135                 rc = -ENODEV;
6136                 goto err_out_mwi_2;
6137         }
6138
6139         rc = pci_request_regions(pdev, MODULENAME);
6140         if (rc < 0) {
6141                 netif_err(tp, probe, dev, "could not request regions\n");
6142                 goto err_out_mwi_2;
6143         }
6144
6145         tp->cp_cmd = RxChkSum;
6146
6147         if ((sizeof(dma_addr_t) > 4) &&
6148             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
6149                 tp->cp_cmd |= PCIDAC;
6150                 dev->features |= NETIF_F_HIGHDMA;
6151         } else {
6152                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6153                 if (rc < 0) {
6154                         netif_err(tp, probe, dev, "DMA configuration failed\n");
6155                         goto err_out_free_res_3;
6156                 }
6157         }
6158
6159         /* ioremap MMIO region */
6160         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
6161         if (!ioaddr) {
6162                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
6163                 rc = -EIO;
6164                 goto err_out_free_res_3;
6165         }
6166         tp->mmio_addr = ioaddr;
6167
6168         if (!pci_is_pcie(pdev))
6169                 netif_info(tp, probe, dev, "not PCI Express\n");
6170
6171         /* Identify chip attached to board */
6172         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
6173
6174         rtl_init_rxcfg(tp);
6175
6176         rtl_irq_disable(tp);
6177
6178         rtl_hw_reset(tp);
6179
6180         rtl_ack_events(tp, 0xffff);
6181
6182         pci_set_master(pdev);
6183
6184         /*
6185          * Pretend we are using VLANs; This bypasses a nasty bug where
6186          * Interrupts stop flowing on high load on 8110SCd controllers.
6187          */
6188         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6189                 tp->cp_cmd |= RxVlan;
6190
6191         rtl_init_mdio_ops(tp);
6192         rtl_init_pll_power_ops(tp);
6193         rtl_init_jumbo_ops(tp);
6194
6195         rtl8169_print_mac_version(tp);
6196
6197         chipset = tp->mac_version;
6198         tp->txd_version = rtl_chip_infos[chipset].txd_version;
6199
6200         RTL_W8(Cfg9346, Cfg9346_Unlock);
6201         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
6202         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
6203         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
6204                 tp->features |= RTL_FEATURE_WOL;
6205         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
6206                 tp->features |= RTL_FEATURE_WOL;
6207         tp->features |= rtl_try_msi(tp, cfg);
6208         RTL_W8(Cfg9346, Cfg9346_Lock);
6209
6210         if (rtl_tbi_enabled(tp)) {
6211                 tp->set_speed = rtl8169_set_speed_tbi;
6212                 tp->get_settings = rtl8169_gset_tbi;
6213                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
6214                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
6215                 tp->link_ok = rtl8169_tbi_link_ok;
6216                 tp->do_ioctl = rtl_tbi_ioctl;
6217         } else {
6218                 tp->set_speed = rtl8169_set_speed_xmii;
6219                 tp->get_settings = rtl8169_gset_xmii;
6220                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
6221                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
6222                 tp->link_ok = rtl8169_xmii_link_ok;
6223                 tp->do_ioctl = rtl_xmii_ioctl;
6224         }
6225
6226         mutex_init(&tp->wk.mutex);
6227
6228         /* Get MAC address */
6229         for (i = 0; i < ETH_ALEN; i++)
6230                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6231         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
6232
6233         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
6234         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
6235
6236         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
6237
6238         /* don't enable SG, IP_CSUM and TSO by default - it might not work
6239          * properly for all devices */
6240         dev->features |= NETIF_F_RXCSUM |
6241                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6242
6243         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6244                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6245         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6246                 NETIF_F_HIGHDMA;
6247
6248         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6249                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6250                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
6251
6252         dev->hw_features |= NETIF_F_RXALL;
6253         dev->hw_features |= NETIF_F_RXFCS;
6254
6255         tp->hw_start = cfg->hw_start;
6256         tp->event_slow = cfg->event_slow;
6257
6258         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
6259                 ~(RxBOVF | RxFOVF) : ~0;
6260
6261         init_timer(&tp->timer);
6262         tp->timer.data = (unsigned long) dev;
6263         tp->timer.function = rtl8169_phy_timer;
6264
6265         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
6266
6267         rc = register_netdev(dev);
6268         if (rc < 0)
6269                 goto err_out_msi_4;
6270
6271         pci_set_drvdata(pdev, dev);
6272
6273         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6274                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
6275                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
6276         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
6277                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
6278                            "tx checksumming: %s]\n",
6279                            rtl_chip_infos[chipset].jumbo_max,
6280                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
6281         }
6282
6283         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6284             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6285             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6286                 rtl8168_driver_start(tp);
6287         }
6288
6289         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
6290
6291         if (pci_dev_run_wake(pdev))
6292                 pm_runtime_put_noidle(&pdev->dev);
6293
6294         netif_carrier_off(dev);
6295
6296 out:
6297         return rc;
6298
6299 err_out_msi_4:
6300         rtl_disable_msi(pdev, tp);
6301         iounmap(ioaddr);
6302 err_out_free_res_3:
6303         pci_release_regions(pdev);
6304 err_out_mwi_2:
6305         pci_clear_mwi(pdev);
6306         pci_disable_device(pdev);
6307 err_out_free_dev_1:
6308         free_netdev(dev);
6309         goto out;
6310 }
6311
6312 static struct pci_driver rtl8169_pci_driver = {
6313         .name           = MODULENAME,
6314         .id_table       = rtl8169_pci_tbl,
6315         .probe          = rtl_init_one,
6316         .remove         = __devexit_p(rtl_remove_one),
6317         .shutdown       = rtl_shutdown,
6318         .driver.pm      = RTL8169_PM_OPS,
6319 };
6320
6321 static int __init rtl8169_init_module(void)
6322 {
6323         return pci_register_driver(&rtl8169_pci_driver);
6324 }
6325
6326 static void __exit rtl8169_cleanup_module(void)
6327 {
6328         pci_unregister_driver(&rtl8169_pci_driver);
6329 }
6330
6331 module_init(rtl8169_init_module);
6332 module_exit(rtl8169_cleanup_module);