drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33
  34 #define RTL8169_VERSION "2.3LK-NAPI"
  35 #define MODULENAME "r8169"
  36 #define PFX MODULENAME ": "
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53
  54 #ifdef RTL8169_DEBUG
  55 #define assert(expr) \
  56         if (!(expr)) {                                  \
  57                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  58                 #expr,__FILE__,__func__,__LINE__);              \
  59         }
  60 #define dprintk(fmt, args...) \
  61         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  62 #else
  63 #define assert(expr) do {} while (0)
  64 #define dprintk(fmt, args...)   do {} while (0)
  65 #endif /* RTL8169_DEBUG */
  66
  67 #define R8169_MSG_DEFAULT \
  68         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  69
  70 #define TX_SLOTS_AVAIL(tp) \
  71         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  72
  73 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  74 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  75         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  76
  77 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  78    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  79 static const int multicast_filter_limit = 32;
  80
  81 #define MAX_READ_REQUEST_SHIFT  12
  82 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  83 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  84
  85 #define R8169_REGS_SIZE         256
  86 #define R8169_NAPI_WEIGHT       64
  87 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  88 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  89 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  90 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  91
  92 #define RTL8169_TX_TIMEOUT      (6*HZ)
  93 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  94
  95 /* write/read MMIO register */
  96 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  97 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  98 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  99 #define RTL_R8(reg)             readb (ioaddr + (reg))
 100 #define RTL_R16(reg)            readw (ioaddr + (reg))
 101 #define RTL_R32(reg)            readl (ioaddr + (reg))
 102
 103 enum mac_version {
 104         RTL_GIGA_MAC_VER_01 = 0,
 105         RTL_GIGA_MAC_VER_02,
 106         RTL_GIGA_MAC_VER_03,
 107         RTL_GIGA_MAC_VER_04,
 108         RTL_GIGA_MAC_VER_05,
 109         RTL_GIGA_MAC_VER_06,
 110         RTL_GIGA_MAC_VER_07,
 111         RTL_GIGA_MAC_VER_08,
 112         RTL_GIGA_MAC_VER_09,
 113         RTL_GIGA_MAC_VER_10,
 114         RTL_GIGA_MAC_VER_11,
 115         RTL_GIGA_MAC_VER_12,
 116         RTL_GIGA_MAC_VER_13,
 117         RTL_GIGA_MAC_VER_14,
 118         RTL_GIGA_MAC_VER_15,
 119         RTL_GIGA_MAC_VER_16,
 120         RTL_GIGA_MAC_VER_17,
 121         RTL_GIGA_MAC_VER_18,
 122         RTL_GIGA_MAC_VER_19,
 123         RTL_GIGA_MAC_VER_20,
 124         RTL_GIGA_MAC_VER_21,
 125         RTL_GIGA_MAC_VER_22,
 126         RTL_GIGA_MAC_VER_23,
 127         RTL_GIGA_MAC_VER_24,
 128         RTL_GIGA_MAC_VER_25,
 129         RTL_GIGA_MAC_VER_26,
 130         RTL_GIGA_MAC_VER_27,
 131         RTL_GIGA_MAC_VER_28,
 132         RTL_GIGA_MAC_VER_29,
 133         RTL_GIGA_MAC_VER_30,
 134         RTL_GIGA_MAC_VER_31,
 135         RTL_GIGA_MAC_VER_32,
 136         RTL_GIGA_MAC_VER_33,
 137         RTL_GIGA_MAC_VER_34,
 138         RTL_GIGA_MAC_VER_35,
 139         RTL_GIGA_MAC_VER_36,
 140         RTL_GIGA_MAC_VER_37,
 141         RTL_GIGA_MAC_VER_38,
 142         RTL_GIGA_MAC_VER_39,
 143         RTL_GIGA_MAC_VER_40,
 144         RTL_GIGA_MAC_VER_41,
 145         RTL_GIGA_MAC_VER_42,
 146         RTL_GIGA_MAC_VER_43,
 147         RTL_GIGA_MAC_VER_44,
 148         RTL_GIGA_MAC_NONE   = 0xff,
 149 };
 150
 151 enum rtl_tx_desc_version {
 152         RTL_TD_0        = 0,
 153         RTL_TD_1        = 1,
 154 };
 155
 156 #define JUMBO_1K        ETH_DATA_LEN
 157 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 158 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 159 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 160 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 161
 162 #define _R(NAME,TD,FW,SZ,B) {   \
 163         .name = NAME,           \
 164         .txd_version = TD,      \
 165         .fw_name = FW,          \
 166         .jumbo_max = SZ,        \
 167         .jumbo_tx_csum = B      \
 168 }
 169
 170 static const struct {
 171         const char *name;
 172         enum rtl_tx_desc_version txd_version;
 173         const char *fw_name;
 174         u16 jumbo_max;
 175         bool jumbo_tx_csum;
 176 } rtl_chip_infos[] = {
 177         /* PCI devices. */
 178         [RTL_GIGA_MAC_VER_01] =
 179                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_02] =
 181                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 182         [RTL_GIGA_MAC_VER_03] =
 183                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 184         [RTL_GIGA_MAC_VER_04] =
 185                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 186         [RTL_GIGA_MAC_VER_05] =
 187                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 188         [RTL_GIGA_MAC_VER_06] =
 189                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 190         /* PCI-E devices. */
 191         [RTL_GIGA_MAC_VER_07] =
 192                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 193         [RTL_GIGA_MAC_VER_08] =
 194                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 195         [RTL_GIGA_MAC_VER_09] =
 196                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_10] =
 198                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 199         [RTL_GIGA_MAC_VER_11] =
 200                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 201         [RTL_GIGA_MAC_VER_12] =
 202                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 203         [RTL_GIGA_MAC_VER_13] =
 204                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 205         [RTL_GIGA_MAC_VER_14] =
 206                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_15] =
 208                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 209         [RTL_GIGA_MAC_VER_16] =
 210                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 211         [RTL_GIGA_MAC_VER_17] =
 212                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 213         [RTL_GIGA_MAC_VER_18] =
 214                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_19] =
 216                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_20] =
 218                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_21] =
 220                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 221         [RTL_GIGA_MAC_VER_22] =
 222                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 223         [RTL_GIGA_MAC_VER_23] =
 224                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 225         [RTL_GIGA_MAC_VER_24] =
 226                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 227         [RTL_GIGA_MAC_VER_25] =
 228                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 229                                                         JUMBO_9K, false),
 230         [RTL_GIGA_MAC_VER_26] =
 231                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 232                                                         JUMBO_9K, false),
 233         [RTL_GIGA_MAC_VER_27] =
 234                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 235         [RTL_GIGA_MAC_VER_28] =
 236                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_29] =
 238                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 239                                                         JUMBO_1K, true),
 240         [RTL_GIGA_MAC_VER_30] =
 241                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 242                                                         JUMBO_1K, true),
 243         [RTL_GIGA_MAC_VER_31] =
 244                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 245         [RTL_GIGA_MAC_VER_32] =
 246                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 247                                                         JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_33] =
 249                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 250                                                         JUMBO_9K, false),
 251         [RTL_GIGA_MAC_VER_34] =
 252                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 253                                                         JUMBO_9K, false),
 254         [RTL_GIGA_MAC_VER_35] =
 255                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 256                                                         JUMBO_9K, false),
 257         [RTL_GIGA_MAC_VER_36] =
 258                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 259                                                         JUMBO_9K, false),
 260         [RTL_GIGA_MAC_VER_37] =
 261                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 262                                                         JUMBO_1K, true),
 263         [RTL_GIGA_MAC_VER_38] =
 264                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 265                                                         JUMBO_9K, false),
 266         [RTL_GIGA_MAC_VER_39] =
 267                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 268                                                         JUMBO_1K, true),
 269         [RTL_GIGA_MAC_VER_40] =
 270                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 271                                                         JUMBO_9K, false),
 272         [RTL_GIGA_MAC_VER_41] =
 273                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 274         [RTL_GIGA_MAC_VER_42] =
 275                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 276                                                         JUMBO_9K, false),
 277         [RTL_GIGA_MAC_VER_43] =
 278                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 279                                                         JUMBO_1K, true),
 280         [RTL_GIGA_MAC_VER_44] =
 281                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 282                                                         JUMBO_9K, false),
 283 };
 284 #undef _R
 285
 286 enum cfg_version {
 287         RTL_CFG_0 = 0x00,
 288         RTL_CFG_1,
 289         RTL_CFG_2
 290 };
 291
 292 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 293         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 294         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 295         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 296         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 297         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 298         { PCI_VENDOR_ID_DLINK,                  0x4300,
 299                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 300         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 301         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 302         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 303         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 304         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 305                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 306         { 0x0001,                               0x8168,
 307                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 308         {0,},
 309 };
 310
 311 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 312
 313 static int rx_buf_sz = 16383;
 314 static int use_dac;
 315 static struct {
 316         u32 msg_enable;
 317 } debug = { -1 };
 318
 319 enum rtl_registers {
 320         MAC0            = 0,    /* Ethernet hardware address. */
 321         MAC4            = 4,
 322         MAR0            = 8,    /* Multicast filter. */
 323         CounterAddrLow          = 0x10,
 324         CounterAddrHigh         = 0x14,
 325         TxDescStartAddrLow      = 0x20,
 326         TxDescStartAddrHigh     = 0x24,
 327         TxHDescStartAddrLow     = 0x28,
 328         TxHDescStartAddrHigh    = 0x2c,
 329         FLASH           = 0x30,
 330         ERSR            = 0x36,
 331         ChipCmd         = 0x37,
 332         TxPoll          = 0x38,
 333         IntrMask        = 0x3c,
 334         IntrStatus      = 0x3e,
 335
 336         TxConfig        = 0x40,
 337 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 338 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 339
 340         RxConfig        = 0x44,
 341 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 342 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 343 #define RXCFG_FIFO_SHIFT                13
 344                                         /* No threshold before first PCI xfer */
 345 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 346 #define RX_EARLY_OFF                    (1 << 11)
 347 #define RXCFG_DMA_SHIFT                 8
 348                                         /* Unlimited maximum PCI burst. */
 349 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 350
 351         RxMissed        = 0x4c,
 352         Cfg9346         = 0x50,
 353         Config0         = 0x51,
 354         Config1         = 0x52,
 355         Config2         = 0x53,
 356 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 357
 358         Config3         = 0x54,
 359         Config4         = 0x55,
 360         Config5         = 0x56,
 361         MultiIntr       = 0x5c,
 362         PHYAR           = 0x60,
 363         PHYstatus       = 0x6c,
 364         RxMaxSize       = 0xda,
 365         CPlusCmd        = 0xe0,
 366         IntrMitigate    = 0xe2,
 367         RxDescAddrLow   = 0xe4,
 368         RxDescAddrHigh  = 0xe8,
 369         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 370
 371 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 372
 373         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 374
 375 #define TxPacketMax     (8064 >> 7)
 376 #define EarlySize       0x27
 377
 378         FuncEvent       = 0xf0,
 379         FuncEventMask   = 0xf4,
 380         FuncPresetState = 0xf8,
 381         FuncForceEvent  = 0xfc,
 382 };
 383
 384 enum rtl8110_registers {
 385         TBICSR                  = 0x64,
 386         TBI_ANAR                = 0x68,
 387         TBI_LPAR                = 0x6a,
 388 };
 389
 390 enum rtl8168_8101_registers {
 391         CSIDR                   = 0x64,
 392         CSIAR                   = 0x68,
 393 #define CSIAR_FLAG                      0x80000000
 394 #define CSIAR_WRITE_CMD                 0x80000000
 395 #define CSIAR_BYTE_ENABLE               0x0f
 396 #define CSIAR_BYTE_ENABLE_SHIFT         12
 397 #define CSIAR_ADDR_MASK                 0x0fff
 398 #define CSIAR_FUNC_CARD                 0x00000000
 399 #define CSIAR_FUNC_SDIO                 0x00010000
 400 #define CSIAR_FUNC_NIC                  0x00020000
 401 #define CSIAR_FUNC_NIC2                 0x00010000
 402         PMCH                    = 0x6f,
 403         EPHYAR                  = 0x80,
 404 #define EPHYAR_FLAG                     0x80000000
 405 #define EPHYAR_WRITE_CMD                0x80000000
 406 #define EPHYAR_REG_MASK                 0x1f
 407 #define EPHYAR_REG_SHIFT                16
 408 #define EPHYAR_DATA_MASK                0xffff
 409         DLLPR                   = 0xd0,
 410 #define PFM_EN                          (1 << 6)
 411         DBG_REG                 = 0xd1,
 412 #define FIX_NAK_1                       (1 << 4)
 413 #define FIX_NAK_2                       (1 << 3)
 414         TWSI                    = 0xd2,
 415         MCU                     = 0xd3,
 416 #define NOW_IS_OOB                      (1 << 7)
 417 #define TX_EMPTY                        (1 << 5)
 418 #define RX_EMPTY                        (1 << 4)
 419 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 420 #define EN_NDP                          (1 << 3)
 421 #define EN_OOB_RESET                    (1 << 2)
 422 #define LINK_LIST_RDY                   (1 << 1)
 423         EFUSEAR                 = 0xdc,
 424 #define EFUSEAR_FLAG                    0x80000000
 425 #define EFUSEAR_WRITE_CMD               0x80000000
 426 #define EFUSEAR_READ_CMD                0x00000000
 427 #define EFUSEAR_REG_MASK                0x03ff
 428 #define EFUSEAR_REG_SHIFT               8
 429 #define EFUSEAR_DATA_MASK               0xff
 430 };
 431
 432 enum rtl8168_registers {
 433         LED_FREQ                = 0x1a,
 434         EEE_LED                 = 0x1b,
 435         ERIDR                   = 0x70,
 436         ERIAR                   = 0x74,
 437 #define ERIAR_FLAG                      0x80000000
 438 #define ERIAR_WRITE_CMD                 0x80000000
 439 #define ERIAR_READ_CMD                  0x00000000
 440 #define ERIAR_ADDR_BYTE_ALIGN           4
 441 #define ERIAR_TYPE_SHIFT                16
 442 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 443 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 444 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 445 #define ERIAR_MASK_SHIFT                12
 446 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 447 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 448 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 449 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 450         EPHY_RXER_NUM           = 0x7c,
 451         OCPDR                   = 0xb0, /* OCP GPHY access */
 452 #define OCPDR_WRITE_CMD                 0x80000000
 453 #define OCPDR_READ_CMD                  0x00000000
 454 #define OCPDR_REG_MASK                  0x7f
 455 #define OCPDR_GPHY_REG_SHIFT            16
 456 #define OCPDR_DATA_MASK                 0xffff
 457         OCPAR                   = 0xb4,
 458 #define OCPAR_FLAG                      0x80000000
 459 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 460 #define OCPAR_GPHY_READ_CMD             0x0000f060
 461         GPHY_OCP                = 0xb8,
 462         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 463         MISC                    = 0xf0, /* 8168e only. */
 464 #define TXPLA_RST                       (1 << 29)
 465 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 466 #define PWM_EN                          (1 << 22)
 467 #define RXDV_GATED_EN                   (1 << 19)
 468 #define EARLY_TALLY_EN                  (1 << 16)
 469 };
 470
 471 enum rtl_register_content {
 472         /* InterruptStatusBits */
 473         SYSErr          = 0x8000,
 474         PCSTimeout      = 0x4000,
 475         SWInt           = 0x0100,
 476         TxDescUnavail   = 0x0080,
 477         RxFIFOOver      = 0x0040,
 478         LinkChg         = 0x0020,
 479         RxOverflow      = 0x0010,
 480         TxErr           = 0x0008,
 481         TxOK            = 0x0004,
 482         RxErr           = 0x0002,
 483         RxOK            = 0x0001,
 484
 485         /* RxStatusDesc */
 486         RxBOVF  = (1 << 24),
 487         RxFOVF  = (1 << 23),
 488         RxRWT   = (1 << 22),
 489         RxRES   = (1 << 21),
 490         RxRUNT  = (1 << 20),
 491         RxCRC   = (1 << 19),
 492
 493         /* ChipCmdBits */
 494         StopReq         = 0x80,
 495         CmdReset        = 0x10,
 496         CmdRxEnb        = 0x08,
 497         CmdTxEnb        = 0x04,
 498         RxBufEmpty      = 0x01,
 499
 500         /* TXPoll register p.5 */
 501         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 502         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 503         FSWInt          = 0x01,         /* Forced software interrupt */
 504
 505         /* Cfg9346Bits */
 506         Cfg9346_Lock    = 0x00,
 507         Cfg9346_Unlock  = 0xc0,
 508
 509         /* rx_mode_bits */
 510         AcceptErr       = 0x20,
 511         AcceptRunt      = 0x10,
 512         AcceptBroadcast = 0x08,
 513         AcceptMulticast = 0x04,
 514         AcceptMyPhys    = 0x02,
 515         AcceptAllPhys   = 0x01,
 516 #define RX_CONFIG_ACCEPT_MASK           0x3f
 517
 518         /* TxConfigBits */
 519         TxInterFrameGapShift = 24,
 520         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 521
 522         /* Config1 register p.24 */
 523         LEDS1           = (1 << 7),
 524         LEDS0           = (1 << 6),
 525         Speed_down      = (1 << 4),
 526         MEMMAP          = (1 << 3),
 527         IOMAP           = (1 << 2),
 528         VPD             = (1 << 1),
 529         PMEnable        = (1 << 0),     /* Power Management Enable */
 530
 531         /* Config2 register p. 25 */
 532         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 533         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 534         PCI_Clock_66MHz = 0x01,
 535         PCI_Clock_33MHz = 0x00,
 536
 537         /* Config3 register p.25 */
 538         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 539         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 540         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 541         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 542
 543         /* Config4 register */
 544         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 545
 546         /* Config5 register p.27 */
 547         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 548         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 549         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 550         Spi_en          = (1 << 3),
 551         LanWake         = (1 << 1),     /* LanWake enable/disable */
 552         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 553         ASPM_en         = (1 << 0),     /* ASPM enable */
 554
 555         /* TBICSR p.28 */
 556         TBIReset        = 0x80000000,
 557         TBILoopback     = 0x40000000,
 558         TBINwEnable     = 0x20000000,
 559         TBINwRestart    = 0x10000000,
 560         TBILinkOk       = 0x02000000,
 561         TBINwComplete   = 0x01000000,
 562
 563         /* CPlusCmd p.31 */
 564         EnableBist      = (1 << 15),    // 8168 8101
 565         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 566         Normal_mode     = (1 << 13),    // unused
 567         Force_half_dup  = (1 << 12),    // 8168 8101
 568         Force_rxflow_en = (1 << 11),    // 8168 8101
 569         Force_txflow_en = (1 << 10),    // 8168 8101
 570         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 571         ASF             = (1 << 8),     // 8168 8101
 572         PktCntrDisable  = (1 << 7),     // 8168 8101
 573         Mac_dbgo_sel    = 0x001c,       // 8168
 574         RxVlan          = (1 << 6),
 575         RxChkSum        = (1 << 5),
 576         PCIDAC          = (1 << 4),
 577         PCIMulRW        = (1 << 3),
 578         INTT_0          = 0x0000,       // 8168
 579         INTT_1          = 0x0001,       // 8168
 580         INTT_2          = 0x0002,       // 8168
 581         INTT_3          = 0x0003,       // 8168
 582
 583         /* rtl8169_PHYstatus */
 584         TBI_Enable      = 0x80,
 585         TxFlowCtrl      = 0x40,
 586         RxFlowCtrl      = 0x20,
 587         _1000bpsF       = 0x10,
 588         _100bps         = 0x08,
 589         _10bps          = 0x04,
 590         LinkStatus      = 0x02,
 591         FullDup         = 0x01,
 592
 593         /* _TBICSRBit */
 594         TBILinkOK       = 0x02000000,
 595
 596         /* DumpCounterCommand */
 597         CounterDump     = 0x8,
 598 };
 599
 600 enum rtl_desc_bit {
 601         /* First doubleword. */
 602         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 603         RingEnd         = (1 << 30), /* End of descriptor ring */
 604         FirstFrag       = (1 << 29), /* First segment of a packet */
 605         LastFrag        = (1 << 28), /* Final segment of a packet */
 606 };
 607
 608 /* Generic case. */
 609 enum rtl_tx_desc_bit {
 610         /* First doubleword. */
 611         TD_LSO          = (1 << 27),            /* Large Send Offload */
 612 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 613
 614         /* Second doubleword. */
 615         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 616 };
 617
 618 /* 8169, 8168b and 810x except 8102e. */
 619 enum rtl_tx_desc_bit_0 {
 620         /* First doubleword. */
 621 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 622         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 623         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 624         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 625 };
 626
 627 /* 8102e, 8168c and beyond. */
 628 enum rtl_tx_desc_bit_1 {
 629         /* First doubleword. */
 630         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 631 #define GTTCPHO_SHIFT                   18
 632
 633         /* Second doubleword. */
 634 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 635         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 636         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 637         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 638 };
 639
 640 enum rtl_rx_desc_bit {
 641         /* Rx private */
 642         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 643         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 644
 645 #define RxProtoUDP      (PID1)
 646 #define RxProtoTCP      (PID0)
 647 #define RxProtoIP       (PID1 | PID0)
 648 #define RxProtoMask     RxProtoIP
 649
 650         IPFail          = (1 << 16), /* IP checksum failed */
 651         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 652         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 653         RxVlanTag       = (1 << 16), /* VLAN tag available */
 654 };
 655
 656 #define RsvdMask        0x3fffc000
 657
 658 struct TxDesc {
 659         __le32 opts1;
 660         __le32 opts2;
 661         __le64 addr;
 662 };
 663
 664 struct RxDesc {
 665         __le32 opts1;
 666         __le32 opts2;
 667         __le64 addr;
 668 };
 669
 670 struct ring_info {
 671         struct sk_buff  *skb;
 672         u32             len;
 673         u8              __pad[sizeof(void *) - sizeof(u32)];
 674 };
 675
 676 enum features {
 677         RTL_FEATURE_WOL         = (1 << 0),
 678         RTL_FEATURE_MSI         = (1 << 1),
 679         RTL_FEATURE_GMII        = (1 << 2),
 680 };
 681
 682 struct rtl8169_counters {
 683         __le64  tx_packets;
 684         __le64  rx_packets;
 685         __le64  tx_errors;
 686         __le32  rx_errors;
 687         __le16  rx_missed;
 688         __le16  align_errors;
 689         __le32  tx_one_collision;
 690         __le32  tx_multi_collision;
 691         __le64  rx_unicast;
 692         __le64  rx_broadcast;
 693         __le32  rx_multicast;
 694         __le16  tx_aborted;
 695         __le16  tx_underun;
 696 };
 697
 698 enum rtl_flag {
 699         RTL_FLAG_TASK_ENABLED,
 700         RTL_FLAG_TASK_SLOW_PENDING,
 701         RTL_FLAG_TASK_RESET_PENDING,
 702         RTL_FLAG_TASK_PHY_PENDING,
 703         RTL_FLAG_MAX
 704 };
 705
 706 struct rtl8169_stats {
 707         u64                     packets;
 708         u64                     bytes;
 709         struct u64_stats_sync   syncp;
 710 };
 711
 712 struct rtl8169_private {
 713         void __iomem *mmio_addr;        /* memory map physical address */
 714         struct pci_dev *pci_dev;
 715         struct net_device *dev;
 716         struct napi_struct napi;
 717         u32 msg_enable;
 718         u16 txd_version;
 719         u16 mac_version;
 720         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 721         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 722         u32 dirty_tx;
 723         struct rtl8169_stats rx_stats;
 724         struct rtl8169_stats tx_stats;
 725         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 726         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 727         dma_addr_t TxPhyAddr;
 728         dma_addr_t RxPhyAddr;
 729         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 730         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 731         struct timer_list timer;
 732         u16 cp_cmd;
 733
 734         u16 event_slow;
 735
 736         struct mdio_ops {
 737                 void (*write)(struct rtl8169_private *, int, int);
 738                 int (*read)(struct rtl8169_private *, int);
 739         } mdio_ops;
 740
 741         struct pll_power_ops {
 742                 void (*down)(struct rtl8169_private *);
 743                 void (*up)(struct rtl8169_private *);
 744         } pll_power_ops;
 745
 746         struct jumbo_ops {
 747                 void (*enable)(struct rtl8169_private *);
 748                 void (*disable)(struct rtl8169_private *);
 749         } jumbo_ops;
 750
 751         struct csi_ops {
 752                 void (*write)(struct rtl8169_private *, int, int);
 753                 u32 (*read)(struct rtl8169_private *, int);
 754         } csi_ops;
 755
 756         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 757         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 758         void (*phy_reset_enable)(struct rtl8169_private *tp);
 759         void (*hw_start)(struct net_device *);
 760         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 761         unsigned int (*link_ok)(void __iomem *);
 762         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 763         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 764
 765         struct {
 766                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 767                 struct mutex mutex;
 768                 struct work_struct work;
 769         } wk;
 770
 771         unsigned features;
 772
 773         struct mii_if_info mii;
 774         struct rtl8169_counters counters;
 775         u32 saved_wolopts;
 776         u32 opts1_mask;
 777
 778         struct rtl_fw {
 779                 const struct firmware *fw;
 780
 781 #define RTL_VER_SIZE            32
 782
 783                 char version[RTL_VER_SIZE];
 784
 785                 struct rtl_fw_phy_action {
 786                         __le32 *code;
 787                         size_t size;
 788                 } phy_action;
 789         } *rtl_fw;
 790 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 791
 792         u32 ocp_base;
 793 };
 794
 795 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 796 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 797 module_param(use_dac, int, 0);
 798 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 799 module_param_named(debug, debug.msg_enable, int, 0);
 800 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 801 MODULE_LICENSE("GPL");
 802 MODULE_VERSION(RTL8169_VERSION);
 803 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 804 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 805 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 806 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 807 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 808 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 809 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 810 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 811 MODULE_FIRMWARE(FIRMWARE_8402_1);
 812 MODULE_FIRMWARE(FIRMWARE_8411_1);
 813 MODULE_FIRMWARE(FIRMWARE_8411_2);
 814 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 815 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 816 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 817 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 818
 819 static void rtl_lock_work(struct rtl8169_private *tp)
 820 {
 821         mutex_lock(&tp->wk.mutex);
 822 }
 823
 824 static void rtl_unlock_work(struct rtl8169_private *tp)
 825 {
 826         mutex_unlock(&tp->wk.mutex);
 827 }
 828
 829 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 830 {
 831         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 832                                            PCI_EXP_DEVCTL_READRQ, force);
 833 }
 834
 835 struct rtl_cond {
 836         bool (*check)(struct rtl8169_private *);
 837         const char *msg;
 838 };
 839
 840 static void rtl_udelay(unsigned int d)
 841 {
 842         udelay(d);
 843 }
 844
 845 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 846                           void (*delay)(unsigned int), unsigned int d, int n,
 847                           bool high)
 848 {
 849         int i;
 850
 851         for (i = 0; i < n; i++) {
 852                 delay(d);
 853                 if (c->check(tp) == high)
 854                         return true;
 855         }
 856         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 857                   c->msg, !high, n, d);
 858         return false;
 859 }
 860
 861 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 862                                       const struct rtl_cond *c,
 863                                       unsigned int d, int n)
 864 {
 865         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 866 }
 867
 868 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 869                                      const struct rtl_cond *c,
 870                                      unsigned int d, int n)
 871 {
 872         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 873 }
 874
 875 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 876                                       const struct rtl_cond *c,
 877                                       unsigned int d, int n)
 878 {
 879         return rtl_loop_wait(tp, c, msleep, d, n, true);
 880 }
 881
 882 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 883                                      const struct rtl_cond *c,
 884                                      unsigned int d, int n)
 885 {
 886         return rtl_loop_wait(tp, c, msleep, d, n, false);
 887 }
 888
 889 #define DECLARE_RTL_COND(name)                          \
 890 static bool name ## _check(struct rtl8169_private *);   \
 891                                                         \
 892 static const struct rtl_cond name = {                   \
 893         .check  = name ## _check,                       \
 894         .msg    = #name                                 \
 895 };                                                      \
 896                                                         \
 897 static bool name ## _check(struct rtl8169_private *tp)
 898
 899 DECLARE_RTL_COND(rtl_ocpar_cond)
 900 {
 901         void __iomem *ioaddr = tp->mmio_addr;
 902
 903         return RTL_R32(OCPAR) & OCPAR_FLAG;
 904 }
 905
 906 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 907 {
 908         void __iomem *ioaddr = tp->mmio_addr;
 909
 910         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 911
 912         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
 913                 RTL_R32(OCPDR) : ~0;
 914 }
 915
 916 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 917 {
 918         void __iomem *ioaddr = tp->mmio_addr;
 919
 920         RTL_W32(OCPDR, data);
 921         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 922
 923         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
 924 }
 925
 926 DECLARE_RTL_COND(rtl_eriar_cond)
 927 {
 928         void __iomem *ioaddr = tp->mmio_addr;
 929
 930         return RTL_R32(ERIAR) & ERIAR_FLAG;
 931 }
 932
 933 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 934 {
 935         void __iomem *ioaddr = tp->mmio_addr;
 936
 937         RTL_W8(ERIDR, cmd);
 938         RTL_W32(ERIAR, 0x800010e8);
 939         msleep(2);
 940
 941         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
 942                 return;
 943
 944         ocp_write(tp, 0x1, 0x30, 0x00000001);
 945 }
 946
 947 #define OOB_CMD_RESET           0x00
 948 #define OOB_CMD_DRIVER_START    0x05
 949 #define OOB_CMD_DRIVER_STOP     0x06
 950
 951 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 952 {
 953         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 954 }
 955
 956 DECLARE_RTL_COND(rtl_ocp_read_cond)
 957 {
 958         u16 reg;
 959
 960         reg = rtl8168_get_ocp_reg(tp);
 961
 962         return ocp_read(tp, 0x0f, reg) & 0x00000800;
 963 }
 964
 965 static void rtl8168_driver_start(struct rtl8169_private *tp)
 966 {
 967         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 968
 969         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
 970 }
 971
 972 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 973 {
 974         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 975
 976         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
 977 }
 978
 979 static int r8168dp_check_dash(struct rtl8169_private *tp)
 980 {
 981         u16 reg = rtl8168_get_ocp_reg(tp);
 982
 983         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 984 }
 985
 986 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 987 {
 988         if (reg & 0xffff0001) {
 989                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 990                 return true;
 991         }
 992         return false;
 993 }
 994
 995 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 996 {
 997         void __iomem *ioaddr = tp->mmio_addr;
 998
 999         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1000 }
1001
1002 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1003 {
1004         void __iomem *ioaddr = tp->mmio_addr;
1005
1006         if (rtl_ocp_reg_failure(tp, reg))
1007                 return;
1008
1009         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1010
1011         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1012 }
1013
1014 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1015 {
1016         void __iomem *ioaddr = tp->mmio_addr;
1017
1018         if (rtl_ocp_reg_failure(tp, reg))
1019                 return 0;
1020
1021         RTL_W32(GPHY_OCP, reg << 15);
1022
1023         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1024                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1025 }
1026
1027 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1028 {
1029         void __iomem *ioaddr = tp->mmio_addr;
1030
1031         if (rtl_ocp_reg_failure(tp, reg))
1032                 return;
1033
1034         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1035 }
1036
1037 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1038 {
1039         void __iomem *ioaddr = tp->mmio_addr;
1040
1041         if (rtl_ocp_reg_failure(tp, reg))
1042                 return 0;
1043
1044         RTL_W32(OCPDR, reg << 15);
1045
1046         return RTL_R32(OCPDR);
1047 }
1048
1049 #define OCP_STD_PHY_BASE        0xa400
1050
1051 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1052 {
1053         if (reg == 0x1f) {
1054                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1055                 return;
1056         }
1057
1058         if (tp->ocp_base != OCP_STD_PHY_BASE)
1059                 reg -= 0x10;
1060
1061         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1062 }
1063
1064 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1065 {
1066         if (tp->ocp_base != OCP_STD_PHY_BASE)
1067                 reg -= 0x10;
1068
1069         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1070 }
1071
1072 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1073 {
1074         if (reg == 0x1f) {
1075                 tp->ocp_base = value << 4;
1076                 return;
1077         }
1078
1079         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1080 }
1081
1082 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1083 {
1084         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1085 }
1086
1087 DECLARE_RTL_COND(rtl_phyar_cond)
1088 {
1089         void __iomem *ioaddr = tp->mmio_addr;
1090
1091         return RTL_R32(PHYAR) & 0x80000000;
1092 }
1093
1094 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1095 {
1096         void __iomem *ioaddr = tp->mmio_addr;
1097
1098         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1099
1100         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1101         /*
1102          * According to hardware specs a 20us delay is required after write
1103          * complete indication, but before sending next command.
1104          */
1105         udelay(20);
1106 }
1107
1108 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1109 {
1110         void __iomem *ioaddr = tp->mmio_addr;
1111         int value;
1112
1113         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1114
1115         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1116                 RTL_R32(PHYAR) & 0xffff : ~0;
1117
1118         /*
1119          * According to hardware specs a 20us delay is required after read
1120          * complete indication, but before sending next command.
1121          */
1122         udelay(20);
1123
1124         return value;
1125 }
1126
1127 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1128 {
1129         void __iomem *ioaddr = tp->mmio_addr;
1130
1131         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1132         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1133         RTL_W32(EPHY_RXER_NUM, 0);
1134
1135         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1136 }
1137
1138 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1139 {
1140         r8168dp_1_mdio_access(tp, reg,
1141                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1142 }
1143
1144 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1145 {
1146         void __iomem *ioaddr = tp->mmio_addr;
1147
1148         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1149
1150         mdelay(1);
1151         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1152         RTL_W32(EPHY_RXER_NUM, 0);
1153
1154         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1155                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1156 }
1157
1158 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1159
1160 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1161 {
1162         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1163 }
1164
1165 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1166 {
1167         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1168 }
1169
1170 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1171 {
1172         void __iomem *ioaddr = tp->mmio_addr;
1173
1174         r8168dp_2_mdio_start(ioaddr);
1175
1176         r8169_mdio_write(tp, reg, value);
1177
1178         r8168dp_2_mdio_stop(ioaddr);
1179 }
1180
1181 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1182 {
1183         void __iomem *ioaddr = tp->mmio_addr;
1184         int value;
1185
1186         r8168dp_2_mdio_start(ioaddr);
1187
1188         value = r8169_mdio_read(tp, reg);
1189
1190         r8168dp_2_mdio_stop(ioaddr);
1191
1192         return value;
1193 }
1194
1195 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1196 {
1197         tp->mdio_ops.write(tp, location, val);
1198 }
1199
1200 static int rtl_readphy(struct rtl8169_private *tp, int location)
1201 {
1202         return tp->mdio_ops.read(tp, location);
1203 }
1204
1205 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1206 {
1207         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1208 }
1209
1210 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1211 {
1212         int val;
1213
1214         val = rtl_readphy(tp, reg_addr);
1215         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1216 }
1217
1218 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1219                            int val)
1220 {
1221         struct rtl8169_private *tp = netdev_priv(dev);
1222
1223         rtl_writephy(tp, location, val);
1224 }
1225
1226 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1227 {
1228         struct rtl8169_private *tp = netdev_priv(dev);
1229
1230         return rtl_readphy(tp, location);
1231 }
1232
1233 DECLARE_RTL_COND(rtl_ephyar_cond)
1234 {
1235         void __iomem *ioaddr = tp->mmio_addr;
1236
1237         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1238 }
1239
1240 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1241 {
1242         void __iomem *ioaddr = tp->mmio_addr;
1243
1244         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1245                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1246
1247         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1248
1249         udelay(10);
1250 }
1251
1252 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1253 {
1254         void __iomem *ioaddr = tp->mmio_addr;
1255
1256         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1257
1258         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1259                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1260 }
1261
1262 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1263                           u32 val, int type)
1264 {
1265         void __iomem *ioaddr = tp->mmio_addr;
1266
1267         BUG_ON((addr & 3) || (mask == 0));
1268         RTL_W32(ERIDR, val);
1269         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1270
1271         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1272 }
1273
1274 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1275 {
1276         void __iomem *ioaddr = tp->mmio_addr;
1277
1278         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1279
1280         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1281                 RTL_R32(ERIDR) : ~0;
1282 }
1283
1284 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1285                          u32 m, int type)
1286 {
1287         u32 val;
1288
1289         val = rtl_eri_read(tp, addr, type);
1290         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1291 }
1292
1293 struct exgmac_reg {
1294         u16 addr;
1295         u16 mask;
1296         u32 val;
1297 };
1298
1299 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1300                                    const struct exgmac_reg *r, int len)
1301 {
1302         while (len-- > 0) {
1303                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1304                 r++;
1305         }
1306 }
1307
1308 DECLARE_RTL_COND(rtl_efusear_cond)
1309 {
1310         void __iomem *ioaddr = tp->mmio_addr;
1311
1312         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1313 }
1314
1315 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1316 {
1317         void __iomem *ioaddr = tp->mmio_addr;
1318
1319         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1320
1321         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1322                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1323 }
1324
1325 static u16 rtl_get_events(struct rtl8169_private *tp)
1326 {
1327         void __iomem *ioaddr = tp->mmio_addr;
1328
1329         return RTL_R16(IntrStatus);
1330 }
1331
1332 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1333 {
1334         void __iomem *ioaddr = tp->mmio_addr;
1335
1336         RTL_W16(IntrStatus, bits);
1337         mmiowb();
1338 }
1339
1340 static void rtl_irq_disable(struct rtl8169_private *tp)
1341 {
1342         void __iomem *ioaddr = tp->mmio_addr;
1343
1344         RTL_W16(IntrMask, 0);
1345         mmiowb();
1346 }
1347
1348 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1349 {
1350         void __iomem *ioaddr = tp->mmio_addr;
1351
1352         RTL_W16(IntrMask, bits);
1353 }
1354
1355 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1356 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1357 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1358
1359 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1360 {
1361         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1362 }
1363
1364 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1365 {
1366         void __iomem *ioaddr = tp->mmio_addr;
1367
1368         rtl_irq_disable(tp);
1369         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1370         RTL_R8(ChipCmd);
1371 }
1372
1373 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1374 {
1375         void __iomem *ioaddr = tp->mmio_addr;
1376
1377         return RTL_R32(TBICSR) & TBIReset;
1378 }
1379
1380 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1381 {
1382         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1383 }
1384
1385 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1386 {
1387         return RTL_R32(TBICSR) & TBILinkOk;
1388 }
1389
1390 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1391 {
1392         return RTL_R8(PHYstatus) & LinkStatus;
1393 }
1394
1395 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1396 {
1397         void __iomem *ioaddr = tp->mmio_addr;
1398
1399         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1400 }
1401
1402 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1403 {
1404         unsigned int val;
1405
1406         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1407         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1408 }
1409
1410 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1411 {
1412         void __iomem *ioaddr = tp->mmio_addr;
1413         struct net_device *dev = tp->dev;
1414
1415         if (!netif_running(dev))
1416                 return;
1417
1418         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1419             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1420                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1421                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1422                                       ERIAR_EXGMAC);
1423                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1424                                       ERIAR_EXGMAC);
1425                 } else if (RTL_R8(PHYstatus) & _100bps) {
1426                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1427                                       ERIAR_EXGMAC);
1428                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1429                                       ERIAR_EXGMAC);
1430                 } else {
1431                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1432                                       ERIAR_EXGMAC);
1433                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1434                                       ERIAR_EXGMAC);
1435                 }
1436                 /* Reset packet filter */
1437                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1438                              ERIAR_EXGMAC);
1439                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1440                              ERIAR_EXGMAC);
1441         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1442                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1443                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1444                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1445                                       ERIAR_EXGMAC);
1446                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1447                                       ERIAR_EXGMAC);
1448                 } else {
1449                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1450                                       ERIAR_EXGMAC);
1451                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1452                                       ERIAR_EXGMAC);
1453                 }
1454         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1455                 if (RTL_R8(PHYstatus) & _10bps) {
1456                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1457                                       ERIAR_EXGMAC);
1458                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1459                                       ERIAR_EXGMAC);
1460                 } else {
1461                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1462                                       ERIAR_EXGMAC);
1463                 }
1464         }
1465 }
1466
1467 static void __rtl8169_check_link_status(struct net_device *dev,
1468                                         struct rtl8169_private *tp,
1469                                         void __iomem *ioaddr, bool pm)
1470 {
1471         if (tp->link_ok(ioaddr)) {
1472                 rtl_link_chg_patch(tp);
1473                 /* This is to cancel a scheduled suspend if there's one. */
1474                 if (pm)
1475                         pm_request_resume(&tp->pci_dev->dev);
1476                 netif_carrier_on(dev);
1477                 if (net_ratelimit())
1478                         netif_info(tp, ifup, dev, "link up\n");
1479         } else {
1480                 netif_carrier_off(dev);
1481                 netif_info(tp, ifdown, dev, "link down\n");
1482                 if (pm)
1483                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1484         }
1485 }
1486
1487 static void rtl8169_check_link_status(struct net_device *dev,
1488                                       struct rtl8169_private *tp,
1489                                       void __iomem *ioaddr)
1490 {
1491         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1492 }
1493
1494 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1495
1496 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1497 {
1498         void __iomem *ioaddr = tp->mmio_addr;
1499         u8 options;
1500         u32 wolopts = 0;
1501
1502         options = RTL_R8(Config1);
1503         if (!(options & PMEnable))
1504                 return 0;
1505
1506         options = RTL_R8(Config3);
1507         if (options & LinkUp)
1508                 wolopts |= WAKE_PHY;
1509         if (options & MagicPacket)
1510                 wolopts |= WAKE_MAGIC;
1511
1512         options = RTL_R8(Config5);
1513         if (options & UWF)
1514                 wolopts |= WAKE_UCAST;
1515         if (options & BWF)
1516                 wolopts |= WAKE_BCAST;
1517         if (options & MWF)
1518                 wolopts |= WAKE_MCAST;
1519
1520         return wolopts;
1521 }
1522
1523 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1524 {
1525         struct rtl8169_private *tp = netdev_priv(dev);
1526
1527         rtl_lock_work(tp);
1528
1529         wol->supported = WAKE_ANY;
1530         wol->wolopts = __rtl8169_get_wol(tp);
1531
1532         rtl_unlock_work(tp);
1533 }
1534
1535 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1536 {
1537         void __iomem *ioaddr = tp->mmio_addr;
1538         unsigned int i;
1539         static const struct {
1540                 u32 opt;
1541                 u16 reg;
1542                 u8  mask;
1543         } cfg[] = {
1544                 { WAKE_PHY,   Config3, LinkUp },
1545                 { WAKE_MAGIC, Config3, MagicPacket },
1546                 { WAKE_UCAST, Config5, UWF },
1547                 { WAKE_BCAST, Config5, BWF },
1548                 { WAKE_MCAST, Config5, MWF },
1549                 { WAKE_ANY,   Config5, LanWake }
1550         };
1551         u8 options;
1552
1553         RTL_W8(Cfg9346, Cfg9346_Unlock);
1554
1555         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1556                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1557                 if (wolopts & cfg[i].opt)
1558                         options |= cfg[i].mask;
1559                 RTL_W8(cfg[i].reg, options);
1560         }
1561
1562         switch (tp->mac_version) {
1563         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1564                 options = RTL_R8(Config1) & ~PMEnable;
1565                 if (wolopts)
1566                         options |= PMEnable;
1567                 RTL_W8(Config1, options);
1568                 break;
1569         default:
1570                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1571                 if (wolopts)
1572                         options |= PME_SIGNAL;
1573                 RTL_W8(Config2, options);
1574                 break;
1575         }
1576
1577         RTL_W8(Cfg9346, Cfg9346_Lock);
1578 }
1579
1580 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1581 {
1582         struct rtl8169_private *tp = netdev_priv(dev);
1583
1584         rtl_lock_work(tp);
1585
1586         if (wol->wolopts)
1587                 tp->features |= RTL_FEATURE_WOL;
1588         else
1589                 tp->features &= ~RTL_FEATURE_WOL;
1590         __rtl8169_set_wol(tp, wol->wolopts);
1591
1592         rtl_unlock_work(tp);
1593
1594         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1595
1596         return 0;
1597 }
1598
1599 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1600 {
1601         return rtl_chip_infos[tp->mac_version].fw_name;
1602 }
1603
1604 static void rtl8169_get_drvinfo(struct net_device *dev,
1605                                 struct ethtool_drvinfo *info)
1606 {
1607         struct rtl8169_private *tp = netdev_priv(dev);
1608         struct rtl_fw *rtl_fw = tp->rtl_fw;
1609
1610         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1611         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1612         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1613         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1614         if (!IS_ERR_OR_NULL(rtl_fw))
1615                 strlcpy(info->fw_version, rtl_fw->version,
1616                         sizeof(info->fw_version));
1617 }
1618
1619 static int rtl8169_get_regs_len(struct net_device *dev)
1620 {
1621         return R8169_REGS_SIZE;
1622 }
1623
1624 static int rtl8169_set_speed_tbi(struct net_device *dev,
1625                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1626 {
1627         struct rtl8169_private *tp = netdev_priv(dev);
1628         void __iomem *ioaddr = tp->mmio_addr;
1629         int ret = 0;
1630         u32 reg;
1631
1632         reg = RTL_R32(TBICSR);
1633         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1634             (duplex == DUPLEX_FULL)) {
1635                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1636         } else if (autoneg == AUTONEG_ENABLE)
1637                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1638         else {
1639                 netif_warn(tp, link, dev,
1640                            "incorrect speed setting refused in TBI mode\n");
1641                 ret = -EOPNOTSUPP;
1642         }
1643
1644         return ret;
1645 }
1646
1647 static int rtl8169_set_speed_xmii(struct net_device *dev,
1648                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1649 {
1650         struct rtl8169_private *tp = netdev_priv(dev);
1651         int giga_ctrl, bmcr;
1652         int rc = -EINVAL;
1653
1654         rtl_writephy(tp, 0x1f, 0x0000);
1655
1656         if (autoneg == AUTONEG_ENABLE) {
1657                 int auto_nego;
1658
1659                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1660                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1661                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1662
1663                 if (adv & ADVERTISED_10baseT_Half)
1664                         auto_nego |= ADVERTISE_10HALF;
1665                 if (adv & ADVERTISED_10baseT_Full)
1666                         auto_nego |= ADVERTISE_10FULL;
1667                 if (adv & ADVERTISED_100baseT_Half)
1668                         auto_nego |= ADVERTISE_100HALF;
1669                 if (adv & ADVERTISED_100baseT_Full)
1670                         auto_nego |= ADVERTISE_100FULL;
1671
1672                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1673
1674                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1675                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1676
1677                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1678                 if (tp->mii.supports_gmii) {
1679                         if (adv & ADVERTISED_1000baseT_Half)
1680                                 giga_ctrl |= ADVERTISE_1000HALF;
1681                         if (adv & ADVERTISED_1000baseT_Full)
1682                                 giga_ctrl |= ADVERTISE_1000FULL;
1683                 } else if (adv & (ADVERTISED_1000baseT_Half |
1684                                   ADVERTISED_1000baseT_Full)) {
1685                         netif_info(tp, link, dev,
1686                                    "PHY does not support 1000Mbps\n");
1687                         goto out;
1688                 }
1689
1690                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1691
1692                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1693                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1694         } else {
1695                 giga_ctrl = 0;
1696
1697                 if (speed == SPEED_10)
1698                         bmcr = 0;
1699                 else if (speed == SPEED_100)
1700                         bmcr = BMCR_SPEED100;
1701                 else
1702                         goto out;
1703
1704                 if (duplex == DUPLEX_FULL)
1705                         bmcr |= BMCR_FULLDPLX;
1706         }
1707
1708         rtl_writephy(tp, MII_BMCR, bmcr);
1709
1710         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1711             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1712                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1713                         rtl_writephy(tp, 0x17, 0x2138);
1714                         rtl_writephy(tp, 0x0e, 0x0260);
1715                 } else {
1716                         rtl_writephy(tp, 0x17, 0x2108);
1717                         rtl_writephy(tp, 0x0e, 0x0000);
1718                 }
1719         }
1720
1721         rc = 0;
1722 out:
1723         return rc;
1724 }
1725
1726 static int rtl8169_set_speed(struct net_device *dev,
1727                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1728 {
1729         struct rtl8169_private *tp = netdev_priv(dev);
1730         int ret;
1731
1732         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1733         if (ret < 0)
1734                 goto out;
1735
1736         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1737             (advertising & ADVERTISED_1000baseT_Full)) {
1738                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1739         }
1740 out:
1741         return ret;
1742 }
1743
1744 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1745 {
1746         struct rtl8169_private *tp = netdev_priv(dev);
1747         int ret;
1748
1749         del_timer_sync(&tp->timer);
1750
1751         rtl_lock_work(tp);
1752         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1753                                 cmd->duplex, cmd->advertising);
1754         rtl_unlock_work(tp);
1755
1756         return ret;
1757 }
1758
1759 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1760         netdev_features_t features)
1761 {
1762         struct rtl8169_private *tp = netdev_priv(dev);
1763
1764         if (dev->mtu > TD_MSS_MAX)
1765                 features &= ~NETIF_F_ALL_TSO;
1766
1767         if (dev->mtu > JUMBO_1K &&
1768             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1769                 features &= ~NETIF_F_IP_CSUM;
1770
1771         return features;
1772 }
1773
1774 static void __rtl8169_set_features(struct net_device *dev,
1775                                    netdev_features_t features)
1776 {
1777         struct rtl8169_private *tp = netdev_priv(dev);
1778         netdev_features_t changed = features ^ dev->features;
1779         void __iomem *ioaddr = tp->mmio_addr;
1780
1781         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1782                          NETIF_F_HW_VLAN_CTAG_RX)))
1783                 return;
1784
1785         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
1786                 if (features & NETIF_F_RXCSUM)
1787                         tp->cp_cmd |= RxChkSum;
1788                 else
1789                         tp->cp_cmd &= ~RxChkSum;
1790
1791                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
1792                         tp->cp_cmd |= RxVlan;
1793                 else
1794                         tp->cp_cmd &= ~RxVlan;
1795
1796                 RTL_W16(CPlusCmd, tp->cp_cmd);
1797                 RTL_R16(CPlusCmd);
1798         }
1799         if (changed & NETIF_F_RXALL) {
1800                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1801                 if (features & NETIF_F_RXALL)
1802                         tmp |= (AcceptErr | AcceptRunt);
1803                 RTL_W32(RxConfig, tmp);
1804         }
1805 }
1806
1807 static int rtl8169_set_features(struct net_device *dev,
1808                                 netdev_features_t features)
1809 {
1810         struct rtl8169_private *tp = netdev_priv(dev);
1811
1812         rtl_lock_work(tp);
1813         __rtl8169_set_features(dev, features);
1814         rtl_unlock_work(tp);
1815
1816         return 0;
1817 }
1818
1819
1820 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1821 {
1822         return (vlan_tx_tag_present(skb)) ?
1823                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1824 }
1825
1826 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1827 {
1828         u32 opts2 = le32_to_cpu(desc->opts2);
1829
1830         if (opts2 & RxVlanTag)
1831                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1832 }
1833
1834 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1835 {
1836         struct rtl8169_private *tp = netdev_priv(dev);
1837         void __iomem *ioaddr = tp->mmio_addr;
1838         u32 status;
1839
1840         cmd->supported =
1841                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1842         cmd->port = PORT_FIBRE;
1843         cmd->transceiver = XCVR_INTERNAL;
1844
1845         status = RTL_R32(TBICSR);
1846         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1847         cmd->autoneg = !!(status & TBINwEnable);
1848
1849         ethtool_cmd_speed_set(cmd, SPEED_1000);
1850         cmd->duplex = DUPLEX_FULL; /* Always set */
1851
1852         return 0;
1853 }
1854
1855 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1856 {
1857         struct rtl8169_private *tp = netdev_priv(dev);
1858
1859         return mii_ethtool_gset(&tp->mii, cmd);
1860 }
1861
1862 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1863 {
1864         struct rtl8169_private *tp = netdev_priv(dev);
1865         int rc;
1866
1867         rtl_lock_work(tp);
1868         rc = tp->get_settings(dev, cmd);
1869         rtl_unlock_work(tp);
1870
1871         return rc;
1872 }
1873
1874 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1875                              void *p)
1876 {
1877         struct rtl8169_private *tp = netdev_priv(dev);
1878         u32 __iomem *data = tp->mmio_addr;
1879         u32 *dw = p;
1880         int i;
1881
1882         rtl_lock_work(tp);
1883         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1884                 memcpy_fromio(dw++, data++, 4);
1885         rtl_unlock_work(tp);
1886 }
1887
1888 static u32 rtl8169_get_msglevel(struct net_device *dev)
1889 {
1890         struct rtl8169_private *tp = netdev_priv(dev);
1891
1892         return tp->msg_enable;
1893 }
1894
1895 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1896 {
1897         struct rtl8169_private *tp = netdev_priv(dev);
1898
1899         tp->msg_enable = value;
1900 }
1901
1902 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1903         "tx_packets",
1904         "rx_packets",
1905         "tx_errors",
1906         "rx_errors",
1907         "rx_missed",
1908         "align_errors",
1909         "tx_single_collisions",
1910         "tx_multi_collisions",
1911         "unicast",
1912         "broadcast",
1913         "multicast",
1914         "tx_aborted",
1915         "tx_underrun",
1916 };
1917
1918 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1919 {
1920         switch (sset) {
1921         case ETH_SS_STATS:
1922                 return ARRAY_SIZE(rtl8169_gstrings);
1923         default:
1924                 return -EOPNOTSUPP;
1925         }
1926 }
1927
1928 DECLARE_RTL_COND(rtl_counters_cond)
1929 {
1930         void __iomem *ioaddr = tp->mmio_addr;
1931
1932         return RTL_R32(CounterAddrLow) & CounterDump;
1933 }
1934
1935 static void rtl8169_update_counters(struct net_device *dev)
1936 {
1937         struct rtl8169_private *tp = netdev_priv(dev);
1938         void __iomem *ioaddr = tp->mmio_addr;
1939         struct device *d = &tp->pci_dev->dev;
1940         struct rtl8169_counters *counters;
1941         dma_addr_t paddr;
1942         u32 cmd;
1943
1944         /*
1945          * Some chips are unable to dump tally counters when the receiver
1946          * is disabled.
1947          */
1948         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1949                 return;
1950
1951         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1952         if (!counters)
1953                 return;
1954
1955         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1956         cmd = (u64)paddr & DMA_BIT_MASK(32);
1957         RTL_W32(CounterAddrLow, cmd);
1958         RTL_W32(CounterAddrLow, cmd | CounterDump);
1959
1960         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1961                 memcpy(&tp->counters, counters, sizeof(*counters));
1962
1963         RTL_W32(CounterAddrLow, 0);
1964         RTL_W32(CounterAddrHigh, 0);
1965
1966         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1967 }
1968
1969 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1970                                       struct ethtool_stats *stats, u64 *data)
1971 {
1972         struct rtl8169_private *tp = netdev_priv(dev);
1973
1974         ASSERT_RTNL();
1975
1976         rtl8169_update_counters(dev);
1977
1978         data[0] = le64_to_cpu(tp->counters.tx_packets);
1979         data[1] = le64_to_cpu(tp->counters.rx_packets);
1980         data[2] = le64_to_cpu(tp->counters.tx_errors);
1981         data[3] = le32_to_cpu(tp->counters.rx_errors);
1982         data[4] = le16_to_cpu(tp->counters.rx_missed);
1983         data[5] = le16_to_cpu(tp->counters.align_errors);
1984         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1985         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1986         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1987         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1988         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1989         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1990         data[12] = le16_to_cpu(tp->counters.tx_underun);
1991 }
1992
1993 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1994 {
1995         switch(stringset) {
1996         case ETH_SS_STATS:
1997                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1998                 break;
1999         }
2000 }
2001
2002 static const struct ethtool_ops rtl8169_ethtool_ops = {
2003         .get_drvinfo            = rtl8169_get_drvinfo,
2004         .get_regs_len           = rtl8169_get_regs_len,
2005         .get_link               = ethtool_op_get_link,
2006         .get_settings           = rtl8169_get_settings,
2007         .set_settings           = rtl8169_set_settings,
2008         .get_msglevel           = rtl8169_get_msglevel,
2009         .set_msglevel           = rtl8169_set_msglevel,
2010         .get_regs               = rtl8169_get_regs,
2011         .get_wol                = rtl8169_get_wol,
2012         .set_wol                = rtl8169_set_wol,
2013         .get_strings            = rtl8169_get_strings,
2014         .get_sset_count         = rtl8169_get_sset_count,
2015         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2016         .get_ts_info            = ethtool_op_get_ts_info,
2017 };
2018
2019 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2020                                     struct net_device *dev, u8 default_version)
2021 {
2022         void __iomem *ioaddr = tp->mmio_addr;
2023         /*
2024          * The driver currently handles the 8168Bf and the 8168Be identically
2025          * but they can be identified more specifically through the test below
2026          * if needed:
2027          *
2028          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2029          *
2030          * Same thing for the 8101Eb and the 8101Ec:
2031          *
2032          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2033          */
2034         static const struct rtl_mac_info {
2035                 u32 mask;
2036                 u32 val;
2037                 int mac_version;
2038         } mac_info[] = {
2039                 /* 8168G family. */
2040                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2041                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2042                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2043                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2044
2045                 /* 8168F family. */
2046                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2047                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2048                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2049
2050                 /* 8168E family. */
2051                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2052                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2053                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2054                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2055
2056                 /* 8168D family. */
2057                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2058                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2059                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2060
2061                 /* 8168DP family. */
2062                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2063                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2064                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2065
2066                 /* 8168C family. */
2067                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2068                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2069                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2070                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2071                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2072                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2073                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2074                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2075                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2076
2077                 /* 8168B family. */
2078                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2079                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2080                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2081                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2082
2083                 /* 8101 family. */
2084                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2085                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2086                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2087                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2088                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2089                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2090                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2091                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2092                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2093                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2094                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2095                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2096                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2097                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2098                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2099                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2100                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2101                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2102                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2103                 /* FIXME: where did these entries come from ? -- FR */
2104                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2105                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2106
2107                 /* 8110 family. */
2108                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2109                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2110                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2111                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2112                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2113                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2114
2115                 /* Catch-all */
2116                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2117         };
2118         const struct rtl_mac_info *p = mac_info;
2119         u32 reg;
2120
2121         reg = RTL_R32(TxConfig);
2122         while ((reg & p->mask) != p->val)
2123                 p++;
2124         tp->mac_version = p->mac_version;
2125
2126         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2127                 netif_notice(tp, probe, dev,
2128                              "unknown MAC, using family default\n");
2129                 tp->mac_version = default_version;
2130         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2131                 tp->mac_version = tp->mii.supports_gmii ?
2132                                   RTL_GIGA_MAC_VER_42 :
2133                                   RTL_GIGA_MAC_VER_43;
2134         }
2135 }
2136
2137 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2138 {
2139         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2140 }
2141
2142 struct phy_reg {
2143         u16 reg;
2144         u16 val;
2145 };
2146
2147 static void rtl_writephy_batch(struct rtl8169_private *tp,
2148                                const struct phy_reg *regs, int len)
2149 {
2150         while (len-- > 0) {
2151                 rtl_writephy(tp, regs->reg, regs->val);
2152                 regs++;
2153         }
2154 }
2155
2156 #define PHY_READ                0x00000000
2157 #define PHY_DATA_OR             0x10000000
2158 #define PHY_DATA_AND            0x20000000
2159 #define PHY_BJMPN               0x30000000
2160 #define PHY_MDIO_CHG            0x40000000
2161 #define PHY_CLEAR_READCOUNT     0x70000000
2162 #define PHY_WRITE               0x80000000
2163 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2164 #define PHY_COMP_EQ_SKIPN       0xa0000000
2165 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2166 #define PHY_WRITE_PREVIOUS      0xc0000000
2167 #define PHY_SKIPN               0xd0000000
2168 #define PHY_DELAY_MS            0xe0000000
2169
2170 struct fw_info {
2171         u32     magic;
2172         char    version[RTL_VER_SIZE];
2173         __le32  fw_start;
2174         __le32  fw_len;
2175         u8      chksum;
2176 } __packed;
2177
2178 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2179
2180 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2181 {
2182         const struct firmware *fw = rtl_fw->fw;
2183         struct fw_info *fw_info = (struct fw_info *)fw->data;
2184         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2185         char *version = rtl_fw->version;
2186         bool rc = false;
2187
2188         if (fw->size < FW_OPCODE_SIZE)
2189                 goto out;
2190
2191         if (!fw_info->magic) {
2192                 size_t i, size, start;
2193                 u8 checksum = 0;
2194
2195                 if (fw->size < sizeof(*fw_info))
2196                         goto out;
2197
2198                 for (i = 0; i < fw->size; i++)
2199                         checksum += fw->data[i];
2200                 if (checksum != 0)
2201                         goto out;
2202
2203                 start = le32_to_cpu(fw_info->fw_start);
2204                 if (start > fw->size)
2205                         goto out;
2206
2207                 size = le32_to_cpu(fw_info->fw_len);
2208                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2209                         goto out;
2210
2211                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2212
2213                 pa->code = (__le32 *)(fw->data + start);
2214                 pa->size = size;
2215         } else {
2216                 if (fw->size % FW_OPCODE_SIZE)
2217                         goto out;
2218
2219                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2220
2221                 pa->code = (__le32 *)fw->data;
2222                 pa->size = fw->size / FW_OPCODE_SIZE;
2223         }
2224         version[RTL_VER_SIZE - 1] = 0;
2225
2226         rc = true;
2227 out:
2228         return rc;
2229 }
2230
2231 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2232                            struct rtl_fw_phy_action *pa)
2233 {
2234         bool rc = false;
2235         size_t index;
2236
2237         for (index = 0; index < pa->size; index++) {
2238                 u32 action = le32_to_cpu(pa->code[index]);
2239                 u32 regno = (action & 0x0fff0000) >> 16;
2240
2241                 switch(action & 0xf0000000) {
2242                 case PHY_READ:
2243                 case PHY_DATA_OR:
2244                 case PHY_DATA_AND:
2245                 case PHY_MDIO_CHG:
2246                 case PHY_CLEAR_READCOUNT:
2247                 case PHY_WRITE:
2248                 case PHY_WRITE_PREVIOUS:
2249                 case PHY_DELAY_MS:
2250                         break;
2251
2252                 case PHY_BJMPN:
2253                         if (regno > index) {
2254                                 netif_err(tp, ifup, tp->dev,
2255                                           "Out of range of firmware\n");
2256                                 goto out;
2257                         }
2258                         break;
2259                 case PHY_READCOUNT_EQ_SKIP:
2260                         if (index + 2 >= pa->size) {
2261                                 netif_err(tp, ifup, tp->dev,
2262                                           "Out of range of firmware\n");
2263                                 goto out;
2264                         }
2265                         break;
2266                 case PHY_COMP_EQ_SKIPN:
2267                 case PHY_COMP_NEQ_SKIPN:
2268                 case PHY_SKIPN:
2269                         if (index + 1 + regno >= pa->size) {
2270                                 netif_err(tp, ifup, tp->dev,
2271                                           "Out of range of firmware\n");
2272                                 goto out;
2273                         }
2274                         break;
2275
2276                 default:
2277                         netif_err(tp, ifup, tp->dev,
2278                                   "Invalid action 0x%08x\n", action);
2279                         goto out;
2280                 }
2281         }
2282         rc = true;
2283 out:
2284         return rc;
2285 }
2286
2287 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2288 {
2289         struct net_device *dev = tp->dev;
2290         int rc = -EINVAL;
2291
2292         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2293                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2294                 goto out;
2295         }
2296
2297         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2298                 rc = 0;
2299 out:
2300         return rc;
2301 }
2302
2303 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2304 {
2305         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2306         struct mdio_ops org, *ops = &tp->mdio_ops;
2307         u32 predata, count;
2308         size_t index;
2309
2310         predata = count = 0;
2311         org.write = ops->write;
2312         org.read = ops->read;
2313
2314         for (index = 0; index < pa->size; ) {
2315                 u32 action = le32_to_cpu(pa->code[index]);
2316                 u32 data = action & 0x0000ffff;
2317                 u32 regno = (action & 0x0fff0000) >> 16;
2318
2319                 if (!action)
2320                         break;
2321
2322                 switch(action & 0xf0000000) {
2323                 case PHY_READ:
2324                         predata = rtl_readphy(tp, regno);
2325                         count++;
2326                         index++;
2327                         break;
2328                 case PHY_DATA_OR:
2329                         predata |= data;
2330                         index++;
2331                         break;
2332                 case PHY_DATA_AND:
2333                         predata &= data;
2334                         index++;
2335                         break;
2336                 case PHY_BJMPN:
2337                         index -= regno;
2338                         break;
2339                 case PHY_MDIO_CHG:
2340                         if (data == 0) {
2341                                 ops->write = org.write;
2342                                 ops->read = org.read;
2343                         } else if (data == 1) {
2344                                 ops->write = mac_mcu_write;
2345                                 ops->read = mac_mcu_read;
2346                         }
2347
2348                         index++;
2349                         break;
2350                 case PHY_CLEAR_READCOUNT:
2351                         count = 0;
2352                         index++;
2353                         break;
2354                 case PHY_WRITE:
2355                         rtl_writephy(tp, regno, data);
2356                         index++;
2357                         break;
2358                 case PHY_READCOUNT_EQ_SKIP:
2359                         index += (count == data) ? 2 : 1;
2360                         break;
2361                 case PHY_COMP_EQ_SKIPN:
2362                         if (predata == data)
2363                                 index += regno;
2364                         index++;
2365                         break;
2366                 case PHY_COMP_NEQ_SKIPN:
2367                         if (predata != data)
2368                                 index += regno;
2369                         index++;
2370                         break;
2371                 case PHY_WRITE_PREVIOUS:
2372                         rtl_writephy(tp, regno, predata);
2373                         index++;
2374                         break;
2375                 case PHY_SKIPN:
2376                         index += regno + 1;
2377                         break;
2378                 case PHY_DELAY_MS:
2379                         mdelay(data);
2380                         index++;
2381                         break;
2382
2383                 default:
2384                         BUG();
2385                 }
2386         }
2387
2388         ops->write = org.write;
2389         ops->read = org.read;
2390 }
2391
2392 static void rtl_release_firmware(struct rtl8169_private *tp)
2393 {
2394         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2395                 release_firmware(tp->rtl_fw->fw);
2396                 kfree(tp->rtl_fw);
2397         }
2398         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2399 }
2400
2401 static void rtl_apply_firmware(struct rtl8169_private *tp)
2402 {
2403         struct rtl_fw *rtl_fw = tp->rtl_fw;
2404
2405         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2406         if (!IS_ERR_OR_NULL(rtl_fw))
2407                 rtl_phy_write_fw(tp, rtl_fw);
2408 }
2409
2410 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2411 {
2412         if (rtl_readphy(tp, reg) != val)
2413                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2414         else
2415                 rtl_apply_firmware(tp);
2416 }
2417
2418 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2419 {
2420         static const struct phy_reg phy_reg_init[] = {
2421                 { 0x1f, 0x0001 },
2422                 { 0x06, 0x006e },
2423                 { 0x08, 0x0708 },
2424                 { 0x15, 0x4000 },
2425                 { 0x18, 0x65c7 },
2426
2427                 { 0x1f, 0x0001 },
2428                 { 0x03, 0x00a1 },
2429                 { 0x02, 0x0008 },
2430                 { 0x01, 0x0120 },
2431                 { 0x00, 0x1000 },
2432                 { 0x04, 0x0800 },
2433                 { 0x04, 0x0000 },
2434
2435                 { 0x03, 0xff41 },
2436                 { 0x02, 0xdf60 },
2437                 { 0x01, 0x0140 },
2438                 { 0x00, 0x0077 },
2439                 { 0x04, 0x7800 },
2440                 { 0x04, 0x7000 },
2441
2442                 { 0x03, 0x802f },
2443                 { 0x02, 0x4f02 },
2444                 { 0x01, 0x0409 },
2445                 { 0x00, 0xf0f9 },
2446                 { 0x04, 0x9800 },
2447                 { 0x04, 0x9000 },
2448
2449                 { 0x03, 0xdf01 },
2450                 { 0x02, 0xdf20 },
2451                 { 0x01, 0xff95 },
2452                 { 0x00, 0xba00 },
2453                 { 0x04, 0xa800 },
2454                 { 0x04, 0xa000 },
2455
2456                 { 0x03, 0xff41 },
2457                 { 0x02, 0xdf20 },
2458                 { 0x01, 0x0140 },
2459                 { 0x00, 0x00bb },
2460                 { 0x04, 0xb800 },
2461                 { 0x04, 0xb000 },
2462
2463                 { 0x03, 0xdf41 },
2464                 { 0x02, 0xdc60 },
2465                 { 0x01, 0x6340 },
2466                 { 0x00, 0x007d },
2467                 { 0x04, 0xd800 },
2468                 { 0x04, 0xd000 },
2469
2470                 { 0x03, 0xdf01 },
2471                 { 0x02, 0xdf20 },
2472                 { 0x01, 0x100a },
2473                 { 0x00, 0xa0ff },
2474                 { 0x04, 0xf800 },
2475                 { 0x04, 0xf000 },
2476
2477                 { 0x1f, 0x0000 },
2478                 { 0x0b, 0x0000 },
2479                 { 0x00, 0x9200 }
2480         };
2481
2482         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2483 }
2484
2485 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2486 {
2487         static const struct phy_reg phy_reg_init[] = {
2488                 { 0x1f, 0x0002 },
2489                 { 0x01, 0x90d0 },
2490                 { 0x1f, 0x0000 }
2491         };
2492
2493         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2494 }
2495
2496 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2497 {
2498         struct pci_dev *pdev = tp->pci_dev;
2499
2500         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2501             (pdev->subsystem_device != 0xe000))
2502                 return;
2503
2504         rtl_writephy(tp, 0x1f, 0x0001);
2505         rtl_writephy(tp, 0x10, 0xf01b);
2506         rtl_writephy(tp, 0x1f, 0x0000);
2507 }
2508
2509 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2510 {
2511         static const struct phy_reg phy_reg_init[] = {
2512                 { 0x1f, 0x0001 },
2513                 { 0x04, 0x0000 },
2514                 { 0x03, 0x00a1 },
2515                 { 0x02, 0x0008 },
2516                 { 0x01, 0x0120 },
2517                 { 0x00, 0x1000 },
2518                 { 0x04, 0x0800 },
2519                 { 0x04, 0x9000 },
2520                 { 0x03, 0x802f },
2521                 { 0x02, 0x4f02 },
2522                 { 0x01, 0x0409 },
2523                 { 0x00, 0xf099 },
2524                 { 0x04, 0x9800 },
2525                 { 0x04, 0xa000 },
2526                 { 0x03, 0xdf01 },
2527                 { 0x02, 0xdf20 },
2528                 { 0x01, 0xff95 },
2529                 { 0x00, 0xba00 },
2530                 { 0x04, 0xa800 },
2531                 { 0x04, 0xf000 },
2532                 { 0x03, 0xdf01 },
2533                 { 0x02, 0xdf20 },
2534                 { 0x01, 0x101a },
2535                 { 0x00, 0xa0ff },
2536                 { 0x04, 0xf800 },
2537                 { 0x04, 0x0000 },
2538                 { 0x1f, 0x0000 },
2539
2540                 { 0x1f, 0x0001 },
2541                 { 0x10, 0xf41b },
2542                 { 0x14, 0xfb54 },
2543                 { 0x18, 0xf5c7 },
2544                 { 0x1f, 0x0000 },
2545
2546                 { 0x1f, 0x0001 },
2547                 { 0x17, 0x0cc0 },
2548                 { 0x1f, 0x0000 }
2549         };
2550
2551         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2552
2553         rtl8169scd_hw_phy_config_quirk(tp);
2554 }
2555
2556 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2557 {
2558         static const struct phy_reg phy_reg_init[] = {
2559                 { 0x1f, 0x0001 },
2560                 { 0x04, 0x0000 },
2561                 { 0x03, 0x00a1 },
2562                 { 0x02, 0x0008 },
2563                 { 0x01, 0x0120 },
2564                 { 0x00, 0x1000 },
2565                 { 0x04, 0x0800 },
2566                 { 0x04, 0x9000 },
2567                 { 0x03, 0x802f },
2568                 { 0x02, 0x4f02 },
2569                 { 0x01, 0x0409 },
2570                 { 0x00, 0xf099 },
2571                 { 0x04, 0x9800 },
2572                 { 0x04, 0xa000 },
2573                 { 0x03, 0xdf01 },
2574                 { 0x02, 0xdf20 },
2575                 { 0x01, 0xff95 },
2576                 { 0x00, 0xba00 },
2577                 { 0x04, 0xa800 },
2578                 { 0x04, 0xf000 },
2579                 { 0x03, 0xdf01 },
2580                 { 0x02, 0xdf20 },
2581                 { 0x01, 0x101a },
2582                 { 0x00, 0xa0ff },
2583                 { 0x04, 0xf800 },
2584                 { 0x04, 0x0000 },
2585                 { 0x1f, 0x0000 },
2586
2587                 { 0x1f, 0x0001 },
2588                 { 0x0b, 0x8480 },
2589                 { 0x1f, 0x0000 },
2590
2591                 { 0x1f, 0x0001 },
2592                 { 0x18, 0x67c7 },
2593                 { 0x04, 0x2000 },
2594                 { 0x03, 0x002f },
2595                 { 0x02, 0x4360 },
2596                 { 0x01, 0x0109 },
2597                 { 0x00, 0x3022 },
2598                 { 0x04, 0x2800 },
2599                 { 0x1f, 0x0000 },
2600
2601                 { 0x1f, 0x0001 },
2602                 { 0x17, 0x0cc0 },
2603                 { 0x1f, 0x0000 }
2604         };
2605
2606         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2607 }
2608
2609 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2610 {
2611         static const struct phy_reg phy_reg_init[] = {
2612                 { 0x10, 0xf41b },
2613                 { 0x1f, 0x0000 }
2614         };
2615
2616         rtl_writephy(tp, 0x1f, 0x0001);
2617         rtl_patchphy(tp, 0x16, 1 << 0);
2618
2619         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2620 }
2621
2622 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2623 {
2624         static const struct phy_reg phy_reg_init[] = {
2625                 { 0x1f, 0x0001 },
2626                 { 0x10, 0xf41b },
2627                 { 0x1f, 0x0000 }
2628         };
2629
2630         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2631 }
2632
2633 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2634 {
2635         static const struct phy_reg phy_reg_init[] = {
2636                 { 0x1f, 0x0000 },
2637                 { 0x1d, 0x0f00 },
2638                 { 0x1f, 0x0002 },
2639                 { 0x0c, 0x1ec8 },
2640                 { 0x1f, 0x0000 }
2641         };
2642
2643         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2644 }
2645
2646 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2647 {
2648         static const struct phy_reg phy_reg_init[] = {
2649                 { 0x1f, 0x0001 },
2650                 { 0x1d, 0x3d98 },
2651                 { 0x1f, 0x0000 }
2652         };
2653
2654         rtl_writephy(tp, 0x1f, 0x0000);
2655         rtl_patchphy(tp, 0x14, 1 << 5);
2656         rtl_patchphy(tp, 0x0d, 1 << 5);
2657
2658         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2659 }
2660
2661 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2662 {
2663         static const struct phy_reg phy_reg_init[] = {
2664                 { 0x1f, 0x0001 },
2665                 { 0x12, 0x2300 },
2666                 { 0x1f, 0x0002 },
2667                 { 0x00, 0x88d4 },
2668                 { 0x01, 0x82b1 },
2669                 { 0x03, 0x7002 },
2670                 { 0x08, 0x9e30 },
2671                 { 0x09, 0x01f0 },
2672                 { 0x0a, 0x5500 },
2673                 { 0x0c, 0x00c8 },
2674                 { 0x1f, 0x0003 },
2675                 { 0x12, 0xc096 },
2676                 { 0x16, 0x000a },
2677                 { 0x1f, 0x0000 },
2678                 { 0x1f, 0x0000 },
2679                 { 0x09, 0x2000 },
2680                 { 0x09, 0x0000 }
2681         };
2682
2683         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2684
2685         rtl_patchphy(tp, 0x14, 1 << 5);
2686         rtl_patchphy(tp, 0x0d, 1 << 5);
2687         rtl_writephy(tp, 0x1f, 0x0000);
2688 }
2689
2690 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2691 {
2692         static const struct phy_reg phy_reg_init[] = {
2693                 { 0x1f, 0x0001 },
2694                 { 0x12, 0x2300 },
2695                 { 0x03, 0x802f },
2696                 { 0x02, 0x4f02 },
2697                 { 0x01, 0x0409 },
2698                 { 0x00, 0xf099 },
2699                 { 0x04, 0x9800 },
2700                 { 0x04, 0x9000 },
2701                 { 0x1d, 0x3d98 },
2702                 { 0x1f, 0x0002 },
2703                 { 0x0c, 0x7eb8 },
2704                 { 0x06, 0x0761 },
2705                 { 0x1f, 0x0003 },
2706                 { 0x16, 0x0f0a },
2707                 { 0x1f, 0x0000 }
2708         };
2709
2710         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2711
2712         rtl_patchphy(tp, 0x16, 1 << 0);
2713         rtl_patchphy(tp, 0x14, 1 << 5);
2714         rtl_patchphy(tp, 0x0d, 1 << 5);
2715         rtl_writephy(tp, 0x1f, 0x0000);
2716 }
2717
2718 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2719 {
2720         static const struct phy_reg phy_reg_init[] = {
2721                 { 0x1f, 0x0001 },
2722                 { 0x12, 0x2300 },
2723                 { 0x1d, 0x3d98 },
2724                 { 0x1f, 0x0002 },
2725                 { 0x0c, 0x7eb8 },
2726                 { 0x06, 0x5461 },
2727                 { 0x1f, 0x0003 },
2728                 { 0x16, 0x0f0a },
2729                 { 0x1f, 0x0000 }
2730         };
2731
2732         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2733
2734         rtl_patchphy(tp, 0x16, 1 << 0);
2735         rtl_patchphy(tp, 0x14, 1 << 5);
2736         rtl_patchphy(tp, 0x0d, 1 << 5);
2737         rtl_writephy(tp, 0x1f, 0x0000);
2738 }
2739
2740 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2741 {
2742         rtl8168c_3_hw_phy_config(tp);
2743 }
2744
2745 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2746 {
2747         static const struct phy_reg phy_reg_init_0[] = {
2748                 /* Channel Estimation */
2749                 { 0x1f, 0x0001 },
2750                 { 0x06, 0x4064 },
2751                 { 0x07, 0x2863 },
2752                 { 0x08, 0x059c },
2753                 { 0x09, 0x26b4 },
2754                 { 0x0a, 0x6a19 },
2755                 { 0x0b, 0xdcc8 },
2756                 { 0x10, 0xf06d },
2757                 { 0x14, 0x7f68 },
2758                 { 0x18, 0x7fd9 },
2759                 { 0x1c, 0xf0ff },
2760                 { 0x1d, 0x3d9c },
2761                 { 0x1f, 0x0003 },
2762                 { 0x12, 0xf49f },
2763                 { 0x13, 0x070b },
2764                 { 0x1a, 0x05ad },
2765                 { 0x14, 0x94c0 },
2766
2767                 /*
2768                  * Tx Error Issue
2769                  * Enhance line driver power
2770                  */
2771                 { 0x1f, 0x0002 },
2772                 { 0x06, 0x5561 },
2773                 { 0x1f, 0x0005 },
2774                 { 0x05, 0x8332 },
2775                 { 0x06, 0x5561 },
2776
2777                 /*
2778                  * Can not link to 1Gbps with bad cable
2779                  * Decrease SNR threshold form 21.07dB to 19.04dB
2780                  */
2781                 { 0x1f, 0x0001 },
2782                 { 0x17, 0x0cc0 },
2783
2784                 { 0x1f, 0x0000 },
2785                 { 0x0d, 0xf880 }
2786         };
2787
2788         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2789
2790         /*
2791          * Rx Error Issue
2792          * Fine Tune Switching regulator parameter
2793          */
2794         rtl_writephy(tp, 0x1f, 0x0002);
2795         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2796         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2797
2798         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2799                 static const struct phy_reg phy_reg_init[] = {
2800                         { 0x1f, 0x0002 },
2801                         { 0x05, 0x669a },
2802                         { 0x1f, 0x0005 },
2803                         { 0x05, 0x8330 },
2804                         { 0x06, 0x669a },
2805                         { 0x1f, 0x0002 }
2806                 };
2807                 int val;
2808
2809                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2810
2811                 val = rtl_readphy(tp, 0x0d);
2812
2813                 if ((val & 0x00ff) != 0x006c) {
2814                         static const u32 set[] = {
2815                                 0x0065, 0x0066, 0x0067, 0x0068,
2816                                 0x0069, 0x006a, 0x006b, 0x006c
2817                         };
2818                         int i;
2819
2820                         rtl_writephy(tp, 0x1f, 0x0002);
2821
2822                         val &= 0xff00;
2823                         for (i = 0; i < ARRAY_SIZE(set); i++)
2824                                 rtl_writephy(tp, 0x0d, val | set[i]);
2825                 }
2826         } else {
2827                 static const struct phy_reg phy_reg_init[] = {
2828                         { 0x1f, 0x0002 },
2829                         { 0x05, 0x6662 },
2830                         { 0x1f, 0x0005 },
2831                         { 0x05, 0x8330 },
2832                         { 0x06, 0x6662 }
2833                 };
2834
2835                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2836         }
2837
2838         /* RSET couple improve */
2839         rtl_writephy(tp, 0x1f, 0x0002);
2840         rtl_patchphy(tp, 0x0d, 0x0300);
2841         rtl_patchphy(tp, 0x0f, 0x0010);
2842
2843         /* Fine tune PLL performance */
2844         rtl_writephy(tp, 0x1f, 0x0002);
2845         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2846         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2847
2848         rtl_writephy(tp, 0x1f, 0x0005);
2849         rtl_writephy(tp, 0x05, 0x001b);
2850
2851         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2852
2853         rtl_writephy(tp, 0x1f, 0x0000);
2854 }
2855
2856 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2857 {
2858         static const struct phy_reg phy_reg_init_0[] = {
2859                 /* Channel Estimation */
2860                 { 0x1f, 0x0001 },
2861                 { 0x06, 0x4064 },
2862                 { 0x07, 0x2863 },
2863                 { 0x08, 0x059c },
2864                 { 0x09, 0x26b4 },
2865                 { 0x0a, 0x6a19 },
2866                 { 0x0b, 0xdcc8 },
2867                 { 0x10, 0xf06d },
2868                 { 0x14, 0x7f68 },
2869                 { 0x18, 0x7fd9 },
2870                 { 0x1c, 0xf0ff },
2871                 { 0x1d, 0x3d9c },
2872                 { 0x1f, 0x0003 },
2873                 { 0x12, 0xf49f },
2874                 { 0x13, 0x070b },
2875                 { 0x1a, 0x05ad },
2876                 { 0x14, 0x94c0 },
2877
2878                 /*
2879                  * Tx Error Issue
2880                  * Enhance line driver power
2881                  */
2882                 { 0x1f, 0x0002 },
2883                 { 0x06, 0x5561 },
2884                 { 0x1f, 0x0005 },
2885                 { 0x05, 0x8332 },
2886                 { 0x06, 0x5561 },
2887
2888                 /*
2889                  * Can not link to 1Gbps with bad cable
2890                  * Decrease SNR threshold form 21.07dB to 19.04dB
2891                  */
2892                 { 0x1f, 0x0001 },
2893                 { 0x17, 0x0cc0 },
2894
2895                 { 0x1f, 0x0000 },
2896                 { 0x0d, 0xf880 }
2897         };
2898
2899         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2900
2901         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2902                 static const struct phy_reg phy_reg_init[] = {
2903                         { 0x1f, 0x0002 },
2904                         { 0x05, 0x669a },
2905                         { 0x1f, 0x0005 },
2906                         { 0x05, 0x8330 },
2907                         { 0x06, 0x669a },
2908
2909                         { 0x1f, 0x0002 }
2910                 };
2911                 int val;
2912
2913                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2914
2915                 val = rtl_readphy(tp, 0x0d);
2916                 if ((val & 0x00ff) != 0x006c) {
2917                         static const u32 set[] = {
2918                                 0x0065, 0x0066, 0x0067, 0x0068,
2919                                 0x0069, 0x006a, 0x006b, 0x006c
2920                         };
2921                         int i;
2922
2923                         rtl_writephy(tp, 0x1f, 0x0002);
2924
2925                         val &= 0xff00;
2926                         for (i = 0; i < ARRAY_SIZE(set); i++)
2927                                 rtl_writephy(tp, 0x0d, val | set[i]);
2928                 }
2929         } else {
2930                 static const struct phy_reg phy_reg_init[] = {
2931                         { 0x1f, 0x0002 },
2932                         { 0x05, 0x2642 },
2933                         { 0x1f, 0x0005 },
2934                         { 0x05, 0x8330 },
2935                         { 0x06, 0x2642 }
2936                 };
2937
2938                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2939         }
2940
2941         /* Fine tune PLL performance */
2942         rtl_writephy(tp, 0x1f, 0x0002);
2943         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2944         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2945
2946         /* Switching regulator Slew rate */
2947         rtl_writephy(tp, 0x1f, 0x0002);
2948         rtl_patchphy(tp, 0x0f, 0x0017);
2949
2950         rtl_writephy(tp, 0x1f, 0x0005);
2951         rtl_writephy(tp, 0x05, 0x001b);
2952
2953         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2954
2955         rtl_writephy(tp, 0x1f, 0x0000);
2956 }
2957
2958 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2959 {
2960         static const struct phy_reg phy_reg_init[] = {
2961                 { 0x1f, 0x0002 },
2962                 { 0x10, 0x0008 },
2963                 { 0x0d, 0x006c },
2964
2965                 { 0x1f, 0x0000 },
2966                 { 0x0d, 0xf880 },
2967
2968                 { 0x1f, 0x0001 },
2969                 { 0x17, 0x0cc0 },
2970
2971                 { 0x1f, 0x0001 },
2972                 { 0x0b, 0xa4d8 },
2973                 { 0x09, 0x281c },
2974                 { 0x07, 0x2883 },
2975                 { 0x0a, 0x6b35 },
2976                 { 0x1d, 0x3da4 },
2977                 { 0x1c, 0xeffd },
2978                 { 0x14, 0x7f52 },
2979                 { 0x18, 0x7fc6 },
2980                 { 0x08, 0x0601 },
2981                 { 0x06, 0x4063 },
2982                 { 0x10, 0xf074 },
2983                 { 0x1f, 0x0003 },
2984                 { 0x13, 0x0789 },
2985                 { 0x12, 0xf4bd },
2986                 { 0x1a, 0x04fd },
2987                 { 0x14, 0x84b0 },
2988                 { 0x1f, 0x0000 },
2989                 { 0x00, 0x9200 },
2990
2991                 { 0x1f, 0x0005 },
2992                 { 0x01, 0x0340 },
2993                 { 0x1f, 0x0001 },
2994                 { 0x04, 0x4000 },
2995                 { 0x03, 0x1d21 },
2996                 { 0x02, 0x0c32 },
2997                 { 0x01, 0x0200 },
2998                 { 0x00, 0x5554 },
2999                 { 0x04, 0x4800 },
3000                 { 0x04, 0x4000 },
3001                 { 0x04, 0xf000 },
3002                 { 0x03, 0xdf01 },
3003                 { 0x02, 0xdf20 },
3004                 { 0x01, 0x101a },
3005                 { 0x00, 0xa0ff },
3006                 { 0x04, 0xf800 },
3007                 { 0x04, 0xf000 },
3008                 { 0x1f, 0x0000 },
3009
3010                 { 0x1f, 0x0007 },
3011                 { 0x1e, 0x0023 },
3012                 { 0x16, 0x0000 },
3013                 { 0x1f, 0x0000 }
3014         };
3015
3016         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3017 }
3018
3019 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3020 {
3021         static const struct phy_reg phy_reg_init[] = {
3022                 { 0x1f, 0x0001 },
3023                 { 0x17, 0x0cc0 },
3024
3025                 { 0x1f, 0x0007 },
3026                 { 0x1e, 0x002d },
3027                 { 0x18, 0x0040 },
3028                 { 0x1f, 0x0000 }
3029         };
3030
3031         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3032         rtl_patchphy(tp, 0x0d, 1 << 5);
3033 }
3034
3035 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3036 {
3037         static const struct phy_reg phy_reg_init[] = {
3038                 /* Enable Delay cap */
3039                 { 0x1f, 0x0005 },
3040                 { 0x05, 0x8b80 },
3041                 { 0x06, 0xc896 },
3042                 { 0x1f, 0x0000 },
3043
3044                 /* Channel estimation fine tune */
3045                 { 0x1f, 0x0001 },
3046                 { 0x0b, 0x6c20 },
3047                 { 0x07, 0x2872 },
3048                 { 0x1c, 0xefff },
3049                 { 0x1f, 0x0003 },
3050                 { 0x14, 0x6420 },
3051                 { 0x1f, 0x0000 },
3052
3053                 /* Update PFM & 10M TX idle timer */
3054                 { 0x1f, 0x0007 },
3055                 { 0x1e, 0x002f },
3056                 { 0x15, 0x1919 },
3057                 { 0x1f, 0x0000 },
3058
3059                 { 0x1f, 0x0007 },
3060                 { 0x1e, 0x00ac },
3061                 { 0x18, 0x0006 },
3062                 { 0x1f, 0x0000 }
3063         };
3064
3065         rtl_apply_firmware(tp);
3066
3067         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3068
3069         /* DCO enable for 10M IDLE Power */
3070         rtl_writephy(tp, 0x1f, 0x0007);
3071         rtl_writephy(tp, 0x1e, 0x0023);
3072         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3073         rtl_writephy(tp, 0x1f, 0x0000);
3074
3075         /* For impedance matching */
3076         rtl_writephy(tp, 0x1f, 0x0002);
3077         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3078         rtl_writephy(tp, 0x1f, 0x0000);
3079
3080         /* PHY auto speed down */
3081         rtl_writephy(tp, 0x1f, 0x0007);
3082         rtl_writephy(tp, 0x1e, 0x002d);
3083         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3084         rtl_writephy(tp, 0x1f, 0x0000);
3085         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3086
3087         rtl_writephy(tp, 0x1f, 0x0005);
3088         rtl_writephy(tp, 0x05, 0x8b86);
3089         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3090         rtl_writephy(tp, 0x1f, 0x0000);
3091
3092         rtl_writephy(tp, 0x1f, 0x0005);
3093         rtl_writephy(tp, 0x05, 0x8b85);
3094         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3095         rtl_writephy(tp, 0x1f, 0x0007);
3096         rtl_writephy(tp, 0x1e, 0x0020);
3097         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3098         rtl_writephy(tp, 0x1f, 0x0006);
3099         rtl_writephy(tp, 0x00, 0x5a00);
3100         rtl_writephy(tp, 0x1f, 0x0000);
3101         rtl_writephy(tp, 0x0d, 0x0007);
3102         rtl_writephy(tp, 0x0e, 0x003c);
3103         rtl_writephy(tp, 0x0d, 0x4007);
3104         rtl_writephy(tp, 0x0e, 0x0000);
3105         rtl_writephy(tp, 0x0d, 0x0000);
3106 }
3107
3108 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3109 {
3110         const u16 w[] = {
3111                 addr[0] | (addr[1] << 8),
3112                 addr[2] | (addr[3] << 8),
3113                 addr[4] | (addr[5] << 8)
3114         };
3115         const struct exgmac_reg e[] = {
3116                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3117                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3118                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3119                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3120         };
3121
3122         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3123 }
3124
3125 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3126 {
3127         static const struct phy_reg phy_reg_init[] = {
3128                 /* Enable Delay cap */
3129                 { 0x1f, 0x0004 },
3130                 { 0x1f, 0x0007 },
3131                 { 0x1e, 0x00ac },
3132                 { 0x18, 0x0006 },
3133                 { 0x1f, 0x0002 },
3134                 { 0x1f, 0x0000 },
3135                 { 0x1f, 0x0000 },
3136
3137                 /* Channel estimation fine tune */
3138                 { 0x1f, 0x0003 },
3139                 { 0x09, 0xa20f },
3140                 { 0x1f, 0x0000 },
3141                 { 0x1f, 0x0000 },
3142
3143                 /* Green Setting */
3144                 { 0x1f, 0x0005 },
3145                 { 0x05, 0x8b5b },
3146                 { 0x06, 0x9222 },
3147                 { 0x05, 0x8b6d },
3148                 { 0x06, 0x8000 },
3149                 { 0x05, 0x8b76 },
3150                 { 0x06, 0x8000 },
3151                 { 0x1f, 0x0000 }
3152         };
3153
3154         rtl_apply_firmware(tp);
3155
3156         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3157
3158         /* For 4-corner performance improve */
3159         rtl_writephy(tp, 0x1f, 0x0005);
3160         rtl_writephy(tp, 0x05, 0x8b80);
3161         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3162         rtl_writephy(tp, 0x1f, 0x0000);
3163
3164         /* PHY auto speed down */
3165         rtl_writephy(tp, 0x1f, 0x0004);
3166         rtl_writephy(tp, 0x1f, 0x0007);
3167         rtl_writephy(tp, 0x1e, 0x002d);
3168         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3169         rtl_writephy(tp, 0x1f, 0x0002);
3170         rtl_writephy(tp, 0x1f, 0x0000);
3171         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3172
3173         /* improve 10M EEE waveform */
3174         rtl_writephy(tp, 0x1f, 0x0005);
3175         rtl_writephy(tp, 0x05, 0x8b86);
3176         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3177         rtl_writephy(tp, 0x1f, 0x0000);
3178
3179         /* Improve 2-pair detection performance */
3180         rtl_writephy(tp, 0x1f, 0x0005);
3181         rtl_writephy(tp, 0x05, 0x8b85);
3182         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3183         rtl_writephy(tp, 0x1f, 0x0000);
3184
3185         /* EEE setting */
3186         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3187         rtl_writephy(tp, 0x1f, 0x0005);
3188         rtl_writephy(tp, 0x05, 0x8b85);
3189         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3190         rtl_writephy(tp, 0x1f, 0x0004);
3191         rtl_writephy(tp, 0x1f, 0x0007);
3192         rtl_writephy(tp, 0x1e, 0x0020);
3193         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3194         rtl_writephy(tp, 0x1f, 0x0002);
3195         rtl_writephy(tp, 0x1f, 0x0000);
3196         rtl_writephy(tp, 0x0d, 0x0007);
3197         rtl_writephy(tp, 0x0e, 0x003c);
3198         rtl_writephy(tp, 0x0d, 0x4007);
3199         rtl_writephy(tp, 0x0e, 0x0000);
3200         rtl_writephy(tp, 0x0d, 0x0000);
3201
3202         /* Green feature */
3203         rtl_writephy(tp, 0x1f, 0x0003);
3204         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3205         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3206         rtl_writephy(tp, 0x1f, 0x0000);
3207
3208         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3209         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3210 }
3211
3212 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3213 {
3214         /* For 4-corner performance improve */
3215         rtl_writephy(tp, 0x1f, 0x0005);
3216         rtl_writephy(tp, 0x05, 0x8b80);
3217         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3218         rtl_writephy(tp, 0x1f, 0x0000);
3219
3220         /* PHY auto speed down */
3221         rtl_writephy(tp, 0x1f, 0x0007);
3222         rtl_writephy(tp, 0x1e, 0x002d);
3223         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3224         rtl_writephy(tp, 0x1f, 0x0000);
3225         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3226
3227         /* Improve 10M EEE waveform */
3228         rtl_writephy(tp, 0x1f, 0x0005);
3229         rtl_writephy(tp, 0x05, 0x8b86);
3230         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3231         rtl_writephy(tp, 0x1f, 0x0000);
3232 }
3233
3234 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3235 {
3236         static const struct phy_reg phy_reg_init[] = {
3237                 /* Channel estimation fine tune */
3238                 { 0x1f, 0x0003 },
3239                 { 0x09, 0xa20f },
3240                 { 0x1f, 0x0000 },
3241
3242                 /* Modify green table for giga & fnet */
3243                 { 0x1f, 0x0005 },
3244                 { 0x05, 0x8b55 },
3245                 { 0x06, 0x0000 },
3246                 { 0x05, 0x8b5e },
3247                 { 0x06, 0x0000 },
3248                 { 0x05, 0x8b67 },
3249                 { 0x06, 0x0000 },
3250                 { 0x05, 0x8b70 },
3251                 { 0x06, 0x0000 },
3252                 { 0x1f, 0x0000 },
3253                 { 0x1f, 0x0007 },
3254                 { 0x1e, 0x0078 },
3255                 { 0x17, 0x0000 },
3256                 { 0x19, 0x00fb },
3257                 { 0x1f, 0x0000 },
3258
3259                 /* Modify green table for 10M */
3260                 { 0x1f, 0x0005 },
3261                 { 0x05, 0x8b79 },
3262                 { 0x06, 0xaa00 },
3263                 { 0x1f, 0x0000 },
3264
3265                 /* Disable hiimpedance detection (RTCT) */
3266                 { 0x1f, 0x0003 },
3267                 { 0x01, 0x328a },
3268                 { 0x1f, 0x0000 }
3269         };
3270
3271         rtl_apply_firmware(tp);
3272
3273         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3274
3275         rtl8168f_hw_phy_config(tp);
3276
3277         /* Improve 2-pair detection performance */
3278         rtl_writephy(tp, 0x1f, 0x0005);
3279         rtl_writephy(tp, 0x05, 0x8b85);
3280         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3281         rtl_writephy(tp, 0x1f, 0x0000);
3282 }
3283
3284 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3285 {
3286         rtl_apply_firmware(tp);
3287
3288         rtl8168f_hw_phy_config(tp);
3289 }
3290
3291 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3292 {
3293         static const struct phy_reg phy_reg_init[] = {
3294                 /* Channel estimation fine tune */
3295                 { 0x1f, 0x0003 },
3296                 { 0x09, 0xa20f },
3297                 { 0x1f, 0x0000 },
3298
3299                 /* Modify green table for giga & fnet */
3300                 { 0x1f, 0x0005 },
3301                 { 0x05, 0x8b55 },
3302                 { 0x06, 0x0000 },
3303                 { 0x05, 0x8b5e },
3304                 { 0x06, 0x0000 },
3305                 { 0x05, 0x8b67 },
3306                 { 0x06, 0x0000 },
3307                 { 0x05, 0x8b70 },
3308                 { 0x06, 0x0000 },
3309                 { 0x1f, 0x0000 },
3310                 { 0x1f, 0x0007 },
3311                 { 0x1e, 0x0078 },
3312                 { 0x17, 0x0000 },
3313                 { 0x19, 0x00aa },
3314                 { 0x1f, 0x0000 },
3315
3316                 /* Modify green table for 10M */
3317                 { 0x1f, 0x0005 },
3318                 { 0x05, 0x8b79 },
3319                 { 0x06, 0xaa00 },
3320                 { 0x1f, 0x0000 },
3321
3322                 /* Disable hiimpedance detection (RTCT) */
3323                 { 0x1f, 0x0003 },
3324                 { 0x01, 0x328a },
3325                 { 0x1f, 0x0000 }
3326         };
3327
3328
3329         rtl_apply_firmware(tp);
3330
3331         rtl8168f_hw_phy_config(tp);
3332
3333         /* Improve 2-pair detection performance */
3334         rtl_writephy(tp, 0x1f, 0x0005);
3335         rtl_writephy(tp, 0x05, 0x8b85);
3336         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3337         rtl_writephy(tp, 0x1f, 0x0000);
3338
3339         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3340
3341         /* Modify green table for giga */
3342         rtl_writephy(tp, 0x1f, 0x0005);
3343         rtl_writephy(tp, 0x05, 0x8b54);
3344         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3345         rtl_writephy(tp, 0x05, 0x8b5d);
3346         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3347         rtl_writephy(tp, 0x05, 0x8a7c);
3348         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3349         rtl_writephy(tp, 0x05, 0x8a7f);
3350         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3351         rtl_writephy(tp, 0x05, 0x8a82);
3352         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3353         rtl_writephy(tp, 0x05, 0x8a85);
3354         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3355         rtl_writephy(tp, 0x05, 0x8a88);
3356         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3357         rtl_writephy(tp, 0x1f, 0x0000);
3358
3359         /* uc same-seed solution */
3360         rtl_writephy(tp, 0x1f, 0x0005);
3361         rtl_writephy(tp, 0x05, 0x8b85);
3362         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3363         rtl_writephy(tp, 0x1f, 0x0000);
3364
3365         /* eee setting */
3366         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3367         rtl_writephy(tp, 0x1f, 0x0005);
3368         rtl_writephy(tp, 0x05, 0x8b85);
3369         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3370         rtl_writephy(tp, 0x1f, 0x0004);
3371         rtl_writephy(tp, 0x1f, 0x0007);
3372         rtl_writephy(tp, 0x1e, 0x0020);
3373         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3374         rtl_writephy(tp, 0x1f, 0x0000);
3375         rtl_writephy(tp, 0x0d, 0x0007);
3376         rtl_writephy(tp, 0x0e, 0x003c);
3377         rtl_writephy(tp, 0x0d, 0x4007);
3378         rtl_writephy(tp, 0x0e, 0x0000);
3379         rtl_writephy(tp, 0x0d, 0x0000);
3380
3381         /* Green feature */
3382         rtl_writephy(tp, 0x1f, 0x0003);
3383         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3384         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3385         rtl_writephy(tp, 0x1f, 0x0000);
3386 }
3387
3388 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3389 {
3390         rtl_apply_firmware(tp);
3391
3392         rtl_writephy(tp, 0x1f, 0x0a46);
3393         if (rtl_readphy(tp, 0x10) & 0x0100) {
3394                 rtl_writephy(tp, 0x1f, 0x0bcc);
3395                 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3396         } else {
3397                 rtl_writephy(tp, 0x1f, 0x0bcc);
3398                 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3399         }
3400
3401         rtl_writephy(tp, 0x1f, 0x0a46);
3402         if (rtl_readphy(tp, 0x13) & 0x0100) {
3403                 rtl_writephy(tp, 0x1f, 0x0c41);
3404                 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3405         } else {
3406                 rtl_writephy(tp, 0x1f, 0x0c41);
3407                 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3408         }
3409
3410         /* Enable PHY auto speed down */
3411         rtl_writephy(tp, 0x1f, 0x0a44);
3412         rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3413
3414         rtl_writephy(tp, 0x1f, 0x0bcc);
3415         rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3416         rtl_writephy(tp, 0x1f, 0x0a44);
3417         rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3418         rtl_writephy(tp, 0x1f, 0x0a43);
3419         rtl_writephy(tp, 0x13, 0x8084);
3420         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3421         rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3422
3423         /* EEE auto-fallback function */
3424         rtl_writephy(tp, 0x1f, 0x0a4b);
3425         rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3426
3427         /* Enable UC LPF tune function */
3428         rtl_writephy(tp, 0x1f, 0x0a43);
3429         rtl_writephy(tp, 0x13, 0x8012);
3430         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3431
3432         rtl_writephy(tp, 0x1f, 0x0c42);
3433         rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3434
3435         /* Improve SWR Efficiency */
3436         rtl_writephy(tp, 0x1f, 0x0bcd);
3437         rtl_writephy(tp, 0x14, 0x5065);
3438         rtl_writephy(tp, 0x14, 0xd065);
3439         rtl_writephy(tp, 0x1f, 0x0bc8);
3440         rtl_writephy(tp, 0x11, 0x5655);
3441         rtl_writephy(tp, 0x1f, 0x0bcd);
3442         rtl_writephy(tp, 0x14, 0x1065);
3443         rtl_writephy(tp, 0x14, 0x9065);
3444         rtl_writephy(tp, 0x14, 0x1065);
3445
3446         /* Check ALDPS bit, disable it if enabled */
3447         rtl_writephy(tp, 0x1f, 0x0a43);
3448         if (rtl_readphy(tp, 0x10) & 0x0004)
3449                 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3450
3451         rtl_writephy(tp, 0x1f, 0x0000);
3452 }
3453
3454 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3455 {
3456         rtl_apply_firmware(tp);
3457 }
3458
3459 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3460 {
3461         static const struct phy_reg phy_reg_init[] = {
3462                 { 0x1f, 0x0003 },
3463                 { 0x08, 0x441d },
3464                 { 0x01, 0x9100 },
3465                 { 0x1f, 0x0000 }
3466         };
3467
3468         rtl_writephy(tp, 0x1f, 0x0000);
3469         rtl_patchphy(tp, 0x11, 1 << 12);
3470         rtl_patchphy(tp, 0x19, 1 << 13);
3471         rtl_patchphy(tp, 0x10, 1 << 15);
3472
3473         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3474 }
3475
3476 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3477 {
3478         static const struct phy_reg phy_reg_init[] = {
3479                 { 0x1f, 0x0005 },
3480                 { 0x1a, 0x0000 },
3481                 { 0x1f, 0x0000 },
3482
3483                 { 0x1f, 0x0004 },
3484                 { 0x1c, 0x0000 },
3485                 { 0x1f, 0x0000 },
3486
3487                 { 0x1f, 0x0001 },
3488                 { 0x15, 0x7701 },
3489                 { 0x1f, 0x0000 }
3490         };
3491
3492         /* Disable ALDPS before ram code */
3493         rtl_writephy(tp, 0x1f, 0x0000);
3494         rtl_writephy(tp, 0x18, 0x0310);
3495         msleep(100);
3496
3497         rtl_apply_firmware(tp);
3498
3499         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3500 }
3501
3502 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3503 {
3504         /* Disable ALDPS before setting firmware */
3505         rtl_writephy(tp, 0x1f, 0x0000);
3506         rtl_writephy(tp, 0x18, 0x0310);
3507         msleep(20);
3508
3509         rtl_apply_firmware(tp);
3510
3511         /* EEE setting */
3512         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3513         rtl_writephy(tp, 0x1f, 0x0004);
3514         rtl_writephy(tp, 0x10, 0x401f);
3515         rtl_writephy(tp, 0x19, 0x7030);
3516         rtl_writephy(tp, 0x1f, 0x0000);
3517 }
3518
3519 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3520 {
3521         static const struct phy_reg phy_reg_init[] = {
3522                 { 0x1f, 0x0004 },
3523                 { 0x10, 0xc07f },
3524                 { 0x19, 0x7030 },
3525                 { 0x1f, 0x0000 }
3526         };
3527
3528         /* Disable ALDPS before ram code */
3529         rtl_writephy(tp, 0x1f, 0x0000);
3530         rtl_writephy(tp, 0x18, 0x0310);
3531         msleep(100);
3532
3533         rtl_apply_firmware(tp);
3534
3535         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3536         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3537
3538         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3539 }
3540
3541 static void rtl_hw_phy_config(struct net_device *dev)
3542 {
3543         struct rtl8169_private *tp = netdev_priv(dev);
3544
3545         rtl8169_print_mac_version(tp);
3546
3547         switch (tp->mac_version) {
3548         case RTL_GIGA_MAC_VER_01:
3549                 break;
3550         case RTL_GIGA_MAC_VER_02:
3551         case RTL_GIGA_MAC_VER_03:
3552                 rtl8169s_hw_phy_config(tp);
3553                 break;
3554         case RTL_GIGA_MAC_VER_04:
3555                 rtl8169sb_hw_phy_config(tp);
3556                 break;
3557         case RTL_GIGA_MAC_VER_05:
3558                 rtl8169scd_hw_phy_config(tp);
3559                 break;
3560         case RTL_GIGA_MAC_VER_06:
3561                 rtl8169sce_hw_phy_config(tp);
3562                 break;
3563         case RTL_GIGA_MAC_VER_07:
3564         case RTL_GIGA_MAC_VER_08:
3565         case RTL_GIGA_MAC_VER_09:
3566                 rtl8102e_hw_phy_config(tp);
3567                 break;
3568         case RTL_GIGA_MAC_VER_11:
3569                 rtl8168bb_hw_phy_config(tp);
3570                 break;
3571         case RTL_GIGA_MAC_VER_12:
3572                 rtl8168bef_hw_phy_config(tp);
3573                 break;
3574         case RTL_GIGA_MAC_VER_17:
3575                 rtl8168bef_hw_phy_config(tp);
3576                 break;
3577         case RTL_GIGA_MAC_VER_18:
3578                 rtl8168cp_1_hw_phy_config(tp);
3579                 break;
3580         case RTL_GIGA_MAC_VER_19:
3581                 rtl8168c_1_hw_phy_config(tp);
3582                 break;
3583         case RTL_GIGA_MAC_VER_20:
3584                 rtl8168c_2_hw_phy_config(tp);
3585                 break;
3586         case RTL_GIGA_MAC_VER_21:
3587                 rtl8168c_3_hw_phy_config(tp);
3588                 break;
3589         case RTL_GIGA_MAC_VER_22:
3590                 rtl8168c_4_hw_phy_config(tp);
3591                 break;
3592         case RTL_GIGA_MAC_VER_23:
3593         case RTL_GIGA_MAC_VER_24:
3594                 rtl8168cp_2_hw_phy_config(tp);
3595                 break;
3596         case RTL_GIGA_MAC_VER_25:
3597                 rtl8168d_1_hw_phy_config(tp);
3598                 break;
3599         case RTL_GIGA_MAC_VER_26:
3600                 rtl8168d_2_hw_phy_config(tp);
3601                 break;
3602         case RTL_GIGA_MAC_VER_27:
3603                 rtl8168d_3_hw_phy_config(tp);
3604                 break;
3605         case RTL_GIGA_MAC_VER_28:
3606                 rtl8168d_4_hw_phy_config(tp);
3607                 break;
3608         case RTL_GIGA_MAC_VER_29:
3609         case RTL_GIGA_MAC_VER_30:
3610                 rtl8105e_hw_phy_config(tp);
3611                 break;
3612         case RTL_GIGA_MAC_VER_31:
3613                 /* None. */
3614                 break;
3615         case RTL_GIGA_MAC_VER_32:
3616         case RTL_GIGA_MAC_VER_33:
3617                 rtl8168e_1_hw_phy_config(tp);
3618                 break;
3619         case RTL_GIGA_MAC_VER_34:
3620                 rtl8168e_2_hw_phy_config(tp);
3621                 break;
3622         case RTL_GIGA_MAC_VER_35:
3623                 rtl8168f_1_hw_phy_config(tp);
3624                 break;
3625         case RTL_GIGA_MAC_VER_36:
3626                 rtl8168f_2_hw_phy_config(tp);
3627                 break;
3628
3629         case RTL_GIGA_MAC_VER_37:
3630                 rtl8402_hw_phy_config(tp);
3631                 break;
3632
3633         case RTL_GIGA_MAC_VER_38:
3634                 rtl8411_hw_phy_config(tp);
3635                 break;
3636
3637         case RTL_GIGA_MAC_VER_39:
3638                 rtl8106e_hw_phy_config(tp);
3639                 break;
3640
3641         case RTL_GIGA_MAC_VER_40:
3642                 rtl8168g_1_hw_phy_config(tp);
3643                 break;
3644         case RTL_GIGA_MAC_VER_42:
3645         case RTL_GIGA_MAC_VER_43:
3646         case RTL_GIGA_MAC_VER_44:
3647                 rtl8168g_2_hw_phy_config(tp);
3648                 break;
3649
3650         case RTL_GIGA_MAC_VER_41:
3651         default:
3652                 break;
3653         }
3654 }
3655
3656 static void rtl_phy_work(struct rtl8169_private *tp)
3657 {
3658         struct timer_list *timer = &tp->timer;
3659         void __iomem *ioaddr = tp->mmio_addr;
3660         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3661
3662         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3663
3664         if (tp->phy_reset_pending(tp)) {
3665                 /*
3666                  * A busy loop could burn quite a few cycles on nowadays CPU.
3667                  * Let's delay the execution of the timer for a few ticks.
3668                  */
3669                 timeout = HZ/10;
3670                 goto out_mod_timer;
3671         }
3672
3673         if (tp->link_ok(ioaddr))
3674                 return;
3675
3676         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
3677
3678         tp->phy_reset_enable(tp);
3679
3680 out_mod_timer:
3681         mod_timer(timer, jiffies + timeout);
3682 }
3683
3684 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3685 {
3686         if (!test_and_set_bit(flag, tp->wk.flags))
3687                 schedule_work(&tp->wk.work);
3688 }
3689
3690 static void rtl8169_phy_timer(unsigned long __opaque)
3691 {
3692         struct net_device *dev = (struct net_device *)__opaque;
3693         struct rtl8169_private *tp = netdev_priv(dev);
3694
3695         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3696 }
3697
3698 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3699                                   void __iomem *ioaddr)
3700 {
3701         iounmap(ioaddr);
3702         pci_release_regions(pdev);
3703         pci_clear_mwi(pdev);
3704         pci_disable_device(pdev);
3705         free_netdev(dev);
3706 }
3707
3708 DECLARE_RTL_COND(rtl_phy_reset_cond)
3709 {
3710         return tp->phy_reset_pending(tp);
3711 }
3712
3713 static void rtl8169_phy_reset(struct net_device *dev,
3714                               struct rtl8169_private *tp)
3715 {
3716         tp->phy_reset_enable(tp);
3717         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3718 }
3719
3720 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3721 {
3722         void __iomem *ioaddr = tp->mmio_addr;
3723
3724         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3725             (RTL_R8(PHYstatus) & TBI_Enable);
3726 }
3727
3728 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3729 {
3730         void __iomem *ioaddr = tp->mmio_addr;
3731
3732         rtl_hw_phy_config(dev);
3733
3734         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3735                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3736                 RTL_W8(0x82, 0x01);
3737         }
3738
3739         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3740
3741         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3742                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3743
3744         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3745                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3746                 RTL_W8(0x82, 0x01);
3747                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3748                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3749         }
3750
3751         rtl8169_phy_reset(dev, tp);
3752
3753         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3754                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3755                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3756                           (tp->mii.supports_gmii ?
3757                            ADVERTISED_1000baseT_Half |
3758                            ADVERTISED_1000baseT_Full : 0));
3759
3760         if (rtl_tbi_enabled(tp))
3761                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3762 }
3763
3764 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3765 {
3766         void __iomem *ioaddr = tp->mmio_addr;
3767
3768         rtl_lock_work(tp);
3769
3770         RTL_W8(Cfg9346, Cfg9346_Unlock);
3771
3772         RTL_W32(MAC4, addr[4] | addr[5] << 8);
3773         RTL_R32(MAC4);
3774
3775         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3776         RTL_R32(MAC0);
3777
3778         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3779                 rtl_rar_exgmac_set(tp, addr);
3780
3781         RTL_W8(Cfg9346, Cfg9346_Lock);
3782
3783         rtl_unlock_work(tp);
3784 }
3785
3786 static int rtl_set_mac_address(struct net_device *dev, void *p)
3787 {
3788         struct rtl8169_private *tp = netdev_priv(dev);
3789         struct sockaddr *addr = p;
3790
3791         if (!is_valid_ether_addr(addr->sa_data))
3792                 return -EADDRNOTAVAIL;
3793
3794         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3795
3796         rtl_rar_set(tp, dev->dev_addr);
3797
3798         return 0;
3799 }
3800
3801 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3802 {
3803         struct rtl8169_private *tp = netdev_priv(dev);
3804         struct mii_ioctl_data *data = if_mii(ifr);
3805
3806         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3807 }
3808
3809 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3810                           struct mii_ioctl_data *data, int cmd)
3811 {
3812         switch (cmd) {
3813         case SIOCGMIIPHY:
3814                 data->phy_id = 32; /* Internal PHY */
3815                 return 0;
3816
3817         case SIOCGMIIREG:
3818                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3819                 return 0;
3820
3821         case SIOCSMIIREG:
3822                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3823                 return 0;
3824         }
3825         return -EOPNOTSUPP;
3826 }
3827
3828 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3829 {
3830         return -EOPNOTSUPP;
3831 }
3832
3833 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3834 {
3835         if (tp->features & RTL_FEATURE_MSI) {
3836                 pci_disable_msi(pdev);
3837                 tp->features &= ~RTL_FEATURE_MSI;
3838         }
3839 }
3840
3841 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3842 {
3843         struct mdio_ops *ops = &tp->mdio_ops;
3844
3845         switch (tp->mac_version) {
3846         case RTL_GIGA_MAC_VER_27:
3847                 ops->write      = r8168dp_1_mdio_write;
3848                 ops->read       = r8168dp_1_mdio_read;
3849                 break;
3850         case RTL_GIGA_MAC_VER_28:
3851         case RTL_GIGA_MAC_VER_31:
3852                 ops->write      = r8168dp_2_mdio_write;
3853                 ops->read       = r8168dp_2_mdio_read;
3854                 break;
3855         case RTL_GIGA_MAC_VER_40:
3856         case RTL_GIGA_MAC_VER_41:
3857         case RTL_GIGA_MAC_VER_42:
3858         case RTL_GIGA_MAC_VER_43:
3859         case RTL_GIGA_MAC_VER_44:
3860                 ops->write      = r8168g_mdio_write;
3861                 ops->read       = r8168g_mdio_read;
3862                 break;
3863         default:
3864                 ops->write      = r8169_mdio_write;
3865                 ops->read       = r8169_mdio_read;
3866                 break;
3867         }
3868 }
3869
3870 static void rtl_speed_down(struct rtl8169_private *tp)
3871 {
3872         u32 adv;
3873         int lpa;
3874
3875         rtl_writephy(tp, 0x1f, 0x0000);
3876         lpa = rtl_readphy(tp, MII_LPA);
3877
3878         if (lpa & (LPA_10HALF | LPA_10FULL))
3879                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3880         else if (lpa & (LPA_100HALF | LPA_100FULL))
3881                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3882                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3883         else
3884                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3885                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3886                       (tp->mii.supports_gmii ?
3887                        ADVERTISED_1000baseT_Half |
3888                        ADVERTISED_1000baseT_Full : 0);
3889
3890         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3891                           adv);
3892 }
3893
3894 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3895 {
3896         void __iomem *ioaddr = tp->mmio_addr;
3897
3898         switch (tp->mac_version) {
3899         case RTL_GIGA_MAC_VER_25:
3900         case RTL_GIGA_MAC_VER_26:
3901         case RTL_GIGA_MAC_VER_29:
3902         case RTL_GIGA_MAC_VER_30:
3903         case RTL_GIGA_MAC_VER_32:
3904         case RTL_GIGA_MAC_VER_33:
3905         case RTL_GIGA_MAC_VER_34:
3906         case RTL_GIGA_MAC_VER_37:
3907         case RTL_GIGA_MAC_VER_38:
3908         case RTL_GIGA_MAC_VER_39:
3909         case RTL_GIGA_MAC_VER_40:
3910         case RTL_GIGA_MAC_VER_41:
3911         case RTL_GIGA_MAC_VER_42:
3912         case RTL_GIGA_MAC_VER_43:
3913         case RTL_GIGA_MAC_VER_44:
3914                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3915                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3916                 break;
3917         default:
3918                 break;
3919         }
3920 }
3921
3922 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3923 {
3924         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3925                 return false;
3926
3927         rtl_speed_down(tp);
3928         rtl_wol_suspend_quirk(tp);
3929
3930         return true;
3931 }
3932
3933 static void r810x_phy_power_down(struct rtl8169_private *tp)
3934 {
3935         rtl_writephy(tp, 0x1f, 0x0000);
3936         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3937 }
3938
3939 static void r810x_phy_power_up(struct rtl8169_private *tp)
3940 {
3941         rtl_writephy(tp, 0x1f, 0x0000);
3942         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3943 }
3944
3945 static void r810x_pll_power_down(struct rtl8169_private *tp)
3946 {
3947         void __iomem *ioaddr = tp->mmio_addr;
3948
3949         if (rtl_wol_pll_power_down(tp))
3950                 return;
3951
3952         r810x_phy_power_down(tp);
3953
3954         switch (tp->mac_version) {
3955         case RTL_GIGA_MAC_VER_07:
3956         case RTL_GIGA_MAC_VER_08:
3957         case RTL_GIGA_MAC_VER_09:
3958         case RTL_GIGA_MAC_VER_10:
3959         case RTL_GIGA_MAC_VER_13:
3960         case RTL_GIGA_MAC_VER_16:
3961                 break;
3962         default:
3963                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3964                 break;
3965         }
3966 }
3967
3968 static void r810x_pll_power_up(struct rtl8169_private *tp)
3969 {
3970         void __iomem *ioaddr = tp->mmio_addr;
3971
3972         r810x_phy_power_up(tp);
3973
3974         switch (tp->mac_version) {
3975         case RTL_GIGA_MAC_VER_07:
3976         case RTL_GIGA_MAC_VER_08:
3977         case RTL_GIGA_MAC_VER_09:
3978         case RTL_GIGA_MAC_VER_10:
3979         case RTL_GIGA_MAC_VER_13:
3980         case RTL_GIGA_MAC_VER_16:
3981                 break;
3982         default:
3983                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3984                 break;
3985         }
3986 }
3987
3988 static void r8168_phy_power_up(struct rtl8169_private *tp)
3989 {
3990         rtl_writephy(tp, 0x1f, 0x0000);
3991         switch (tp->mac_version) {
3992         case RTL_GIGA_MAC_VER_11:
3993         case RTL_GIGA_MAC_VER_12:
3994         case RTL_GIGA_MAC_VER_17:
3995         case RTL_GIGA_MAC_VER_18:
3996         case RTL_GIGA_MAC_VER_19:
3997         case RTL_GIGA_MAC_VER_20:
3998         case RTL_GIGA_MAC_VER_21:
3999         case RTL_GIGA_MAC_VER_22:
4000         case RTL_GIGA_MAC_VER_23:
4001         case RTL_GIGA_MAC_VER_24:
4002         case RTL_GIGA_MAC_VER_25:
4003         case RTL_GIGA_MAC_VER_26:
4004         case RTL_GIGA_MAC_VER_27:
4005         case RTL_GIGA_MAC_VER_28:
4006         case RTL_GIGA_MAC_VER_31:
4007                 rtl_writephy(tp, 0x0e, 0x0000);
4008                 break;
4009         default:
4010                 break;
4011         }
4012         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4013 }
4014
4015 static void r8168_phy_power_down(struct rtl8169_private *tp)
4016 {
4017         rtl_writephy(tp, 0x1f, 0x0000);
4018         switch (tp->mac_version) {
4019         case RTL_GIGA_MAC_VER_32:
4020         case RTL_GIGA_MAC_VER_33:
4021         case RTL_GIGA_MAC_VER_40:
4022         case RTL_GIGA_MAC_VER_41:
4023                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4024                 break;
4025
4026         case RTL_GIGA_MAC_VER_11:
4027         case RTL_GIGA_MAC_VER_12:
4028         case RTL_GIGA_MAC_VER_17:
4029         case RTL_GIGA_MAC_VER_18:
4030         case RTL_GIGA_MAC_VER_19:
4031         case RTL_GIGA_MAC_VER_20:
4032         case RTL_GIGA_MAC_VER_21:
4033         case RTL_GIGA_MAC_VER_22:
4034         case RTL_GIGA_MAC_VER_23:
4035         case RTL_GIGA_MAC_VER_24:
4036         case RTL_GIGA_MAC_VER_25:
4037         case RTL_GIGA_MAC_VER_26:
4038         case RTL_GIGA_MAC_VER_27:
4039         case RTL_GIGA_MAC_VER_28:
4040         case RTL_GIGA_MAC_VER_31:
4041                 rtl_writephy(tp, 0x0e, 0x0200);
4042         default:
4043                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4044                 break;
4045         }
4046 }
4047
4048 static void r8168_pll_power_down(struct rtl8169_private *tp)
4049 {
4050         void __iomem *ioaddr = tp->mmio_addr;
4051
4052         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4053              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4054              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4055             r8168dp_check_dash(tp)) {
4056                 return;
4057         }
4058
4059         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4060              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4061             (RTL_R16(CPlusCmd) & ASF)) {
4062                 return;
4063         }
4064
4065         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4066             tp->mac_version == RTL_GIGA_MAC_VER_33)
4067                 rtl_ephy_write(tp, 0x19, 0xff64);
4068
4069         if (rtl_wol_pll_power_down(tp))
4070                 return;
4071
4072         r8168_phy_power_down(tp);
4073
4074         switch (tp->mac_version) {
4075         case RTL_GIGA_MAC_VER_25:
4076         case RTL_GIGA_MAC_VER_26:
4077         case RTL_GIGA_MAC_VER_27:
4078         case RTL_GIGA_MAC_VER_28:
4079         case RTL_GIGA_MAC_VER_31:
4080         case RTL_GIGA_MAC_VER_32:
4081         case RTL_GIGA_MAC_VER_33:
4082                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4083                 break;
4084         case RTL_GIGA_MAC_VER_40:
4085         case RTL_GIGA_MAC_VER_41:
4086                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4087                              0xfc000000, ERIAR_EXGMAC);
4088                 break;
4089         }
4090 }
4091
4092 static void r8168_pll_power_up(struct rtl8169_private *tp)
4093 {
4094         void __iomem *ioaddr = tp->mmio_addr;
4095
4096         switch (tp->mac_version) {
4097         case RTL_GIGA_MAC_VER_25:
4098         case RTL_GIGA_MAC_VER_26:
4099         case RTL_GIGA_MAC_VER_27:
4100         case RTL_GIGA_MAC_VER_28:
4101         case RTL_GIGA_MAC_VER_31:
4102         case RTL_GIGA_MAC_VER_32:
4103         case RTL_GIGA_MAC_VER_33:
4104                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4105                 break;
4106         case RTL_GIGA_MAC_VER_40:
4107         case RTL_GIGA_MAC_VER_41:
4108                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4109                              0x00000000, ERIAR_EXGMAC);
4110                 break;
4111         }
4112
4113         r8168_phy_power_up(tp);
4114 }
4115
4116 static void rtl_generic_op(struct rtl8169_private *tp,
4117                            void (*op)(struct rtl8169_private *))
4118 {
4119         if (op)
4120                 op(tp);
4121 }
4122
4123 static void rtl_pll_power_down(struct rtl8169_private *tp)
4124 {
4125         rtl_generic_op(tp, tp->pll_power_ops.down);
4126 }
4127
4128 static void rtl_pll_power_up(struct rtl8169_private *tp)
4129 {
4130         rtl_generic_op(tp, tp->pll_power_ops.up);
4131 }
4132
4133 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4134 {
4135         struct pll_power_ops *ops = &tp->pll_power_ops;
4136
4137         switch (tp->mac_version) {
4138         case RTL_GIGA_MAC_VER_07:
4139         case RTL_GIGA_MAC_VER_08:
4140         case RTL_GIGA_MAC_VER_09:
4141         case RTL_GIGA_MAC_VER_10:
4142         case RTL_GIGA_MAC_VER_16:
4143         case RTL_GIGA_MAC_VER_29:
4144         case RTL_GIGA_MAC_VER_30:
4145         case RTL_GIGA_MAC_VER_37:
4146         case RTL_GIGA_MAC_VER_39:
4147         case RTL_GIGA_MAC_VER_43:
4148                 ops->down       = r810x_pll_power_down;
4149                 ops->up         = r810x_pll_power_up;
4150                 break;
4151
4152         case RTL_GIGA_MAC_VER_11:
4153         case RTL_GIGA_MAC_VER_12:
4154         case RTL_GIGA_MAC_VER_17:
4155         case RTL_GIGA_MAC_VER_18:
4156         case RTL_GIGA_MAC_VER_19:
4157         case RTL_GIGA_MAC_VER_20:
4158         case RTL_GIGA_MAC_VER_21:
4159         case RTL_GIGA_MAC_VER_22:
4160         case RTL_GIGA_MAC_VER_23:
4161         case RTL_GIGA_MAC_VER_24:
4162         case RTL_GIGA_MAC_VER_25:
4163         case RTL_GIGA_MAC_VER_26:
4164         case RTL_GIGA_MAC_VER_27:
4165         case RTL_GIGA_MAC_VER_28:
4166         case RTL_GIGA_MAC_VER_31:
4167         case RTL_GIGA_MAC_VER_32:
4168         case RTL_GIGA_MAC_VER_33:
4169         case RTL_GIGA_MAC_VER_34:
4170         case RTL_GIGA_MAC_VER_35:
4171         case RTL_GIGA_MAC_VER_36:
4172         case RTL_GIGA_MAC_VER_38:
4173         case RTL_GIGA_MAC_VER_40:
4174         case RTL_GIGA_MAC_VER_41:
4175         case RTL_GIGA_MAC_VER_42:
4176         case RTL_GIGA_MAC_VER_44:
4177                 ops->down       = r8168_pll_power_down;
4178                 ops->up         = r8168_pll_power_up;
4179                 break;
4180
4181         default:
4182                 ops->down       = NULL;
4183                 ops->up         = NULL;
4184                 break;
4185         }
4186 }
4187
4188 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4189 {
4190         void __iomem *ioaddr = tp->mmio_addr;
4191
4192         switch (tp->mac_version) {
4193         case RTL_GIGA_MAC_VER_01:
4194         case RTL_GIGA_MAC_VER_02:
4195         case RTL_GIGA_MAC_VER_03:
4196         case RTL_GIGA_MAC_VER_04:
4197         case RTL_GIGA_MAC_VER_05:
4198         case RTL_GIGA_MAC_VER_06:
4199         case RTL_GIGA_MAC_VER_10:
4200         case RTL_GIGA_MAC_VER_11:
4201         case RTL_GIGA_MAC_VER_12:
4202         case RTL_GIGA_MAC_VER_13:
4203         case RTL_GIGA_MAC_VER_14:
4204         case RTL_GIGA_MAC_VER_15:
4205         case RTL_GIGA_MAC_VER_16:
4206         case RTL_GIGA_MAC_VER_17:
4207                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4208                 break;
4209         case RTL_GIGA_MAC_VER_18:
4210         case RTL_GIGA_MAC_VER_19:
4211         case RTL_GIGA_MAC_VER_20:
4212         case RTL_GIGA_MAC_VER_21:
4213         case RTL_GIGA_MAC_VER_22:
4214         case RTL_GIGA_MAC_VER_23:
4215         case RTL_GIGA_MAC_VER_24:
4216         case RTL_GIGA_MAC_VER_34:
4217         case RTL_GIGA_MAC_VER_35:
4218                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4219                 break;
4220         case RTL_GIGA_MAC_VER_40:
4221         case RTL_GIGA_MAC_VER_41:
4222         case RTL_GIGA_MAC_VER_42:
4223         case RTL_GIGA_MAC_VER_43:
4224         case RTL_GIGA_MAC_VER_44:
4225                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4226                 break;
4227         default:
4228                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4229                 break;
4230         }
4231 }
4232
4233 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4234 {
4235         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4236 }
4237
4238 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4239 {
4240         void __iomem *ioaddr = tp->mmio_addr;
4241
4242         RTL_W8(Cfg9346, Cfg9346_Unlock);
4243         rtl_generic_op(tp, tp->jumbo_ops.enable);
4244         RTL_W8(Cfg9346, Cfg9346_Lock);
4245 }
4246
4247 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4248 {
4249         void __iomem *ioaddr = tp->mmio_addr;
4250
4251         RTL_W8(Cfg9346, Cfg9346_Unlock);
4252         rtl_generic_op(tp, tp->jumbo_ops.disable);
4253         RTL_W8(Cfg9346, Cfg9346_Lock);
4254 }
4255
4256 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4257 {
4258         void __iomem *ioaddr = tp->mmio_addr;
4259
4260         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4261         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4262         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4263 }
4264
4265 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4266 {
4267         void __iomem *ioaddr = tp->mmio_addr;
4268
4269         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4270         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4271         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4272 }
4273
4274 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4275 {
4276         void __iomem *ioaddr = tp->mmio_addr;
4277
4278         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4279 }
4280
4281 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4282 {
4283         void __iomem *ioaddr = tp->mmio_addr;
4284
4285         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4286 }
4287
4288 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4289 {
4290         void __iomem *ioaddr = tp->mmio_addr;
4291
4292         RTL_W8(MaxTxPacketSize, 0x3f);
4293         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4294         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4295         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4296 }
4297
4298 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4299 {
4300         void __iomem *ioaddr = tp->mmio_addr;
4301
4302         RTL_W8(MaxTxPacketSize, 0x0c);
4303         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4304         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4305         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4306 }
4307
4308 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4309 {
4310         rtl_tx_performance_tweak(tp->pci_dev,
4311                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4312 }
4313
4314 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4315 {
4316         rtl_tx_performance_tweak(tp->pci_dev,
4317                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4318 }
4319
4320 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4321 {
4322         void __iomem *ioaddr = tp->mmio_addr;
4323
4324         r8168b_0_hw_jumbo_enable(tp);
4325
4326         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4327 }
4328
4329 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4330 {
4331         void __iomem *ioaddr = tp->mmio_addr;
4332
4333         r8168b_0_hw_jumbo_disable(tp);
4334
4335         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4336 }
4337
4338 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4339 {
4340         struct jumbo_ops *ops = &tp->jumbo_ops;
4341
4342         switch (tp->mac_version) {
4343         case RTL_GIGA_MAC_VER_11:
4344                 ops->disable    = r8168b_0_hw_jumbo_disable;
4345                 ops->enable     = r8168b_0_hw_jumbo_enable;
4346                 break;
4347         case RTL_GIGA_MAC_VER_12:
4348         case RTL_GIGA_MAC_VER_17:
4349                 ops->disable    = r8168b_1_hw_jumbo_disable;
4350                 ops->enable     = r8168b_1_hw_jumbo_enable;
4351                 break;
4352         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4353         case RTL_GIGA_MAC_VER_19:
4354         case RTL_GIGA_MAC_VER_20:
4355         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4356         case RTL_GIGA_MAC_VER_22:
4357         case RTL_GIGA_MAC_VER_23:
4358         case RTL_GIGA_MAC_VER_24:
4359         case RTL_GIGA_MAC_VER_25:
4360         case RTL_GIGA_MAC_VER_26:
4361                 ops->disable    = r8168c_hw_jumbo_disable;
4362                 ops->enable     = r8168c_hw_jumbo_enable;
4363                 break;
4364         case RTL_GIGA_MAC_VER_27:
4365         case RTL_GIGA_MAC_VER_28:
4366                 ops->disable    = r8168dp_hw_jumbo_disable;
4367                 ops->enable     = r8168dp_hw_jumbo_enable;
4368                 break;
4369         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4370         case RTL_GIGA_MAC_VER_32:
4371         case RTL_GIGA_MAC_VER_33:
4372         case RTL_GIGA_MAC_VER_34:
4373                 ops->disable    = r8168e_hw_jumbo_disable;
4374                 ops->enable     = r8168e_hw_jumbo_enable;
4375                 break;
4376
4377         /*
4378          * No action needed for jumbo frames with 8169.
4379          * No jumbo for 810x at all.
4380          */
4381         case RTL_GIGA_MAC_VER_40:
4382         case RTL_GIGA_MAC_VER_41:
4383         case RTL_GIGA_MAC_VER_42:
4384         case RTL_GIGA_MAC_VER_43:
4385         case RTL_GIGA_MAC_VER_44:
4386         default:
4387                 ops->disable    = NULL;
4388                 ops->enable     = NULL;
4389                 break;
4390         }
4391 }
4392
4393 DECLARE_RTL_COND(rtl_chipcmd_cond)
4394 {
4395         void __iomem *ioaddr = tp->mmio_addr;
4396
4397         return RTL_R8(ChipCmd) & CmdReset;
4398 }
4399
4400 static void rtl_hw_reset(struct rtl8169_private *tp)
4401 {
4402         void __iomem *ioaddr = tp->mmio_addr;
4403
4404         RTL_W8(ChipCmd, CmdReset);
4405
4406         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4407 }
4408
4409 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4410 {
4411         struct rtl_fw *rtl_fw;
4412         const char *name;
4413         int rc = -ENOMEM;
4414
4415         name = rtl_lookup_firmware_name(tp);
4416         if (!name)
4417                 goto out_no_firmware;
4418
4419         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4420         if (!rtl_fw)
4421                 goto err_warn;
4422
4423         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4424         if (rc < 0)
4425                 goto err_free;
4426
4427         rc = rtl_check_firmware(tp, rtl_fw);
4428         if (rc < 0)
4429                 goto err_release_firmware;
4430
4431         tp->rtl_fw = rtl_fw;
4432 out:
4433         return;
4434
4435 err_release_firmware:
4436         release_firmware(rtl_fw->fw);
4437 err_free:
4438         kfree(rtl_fw);
4439 err_warn:
4440         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4441                    name, rc);
4442 out_no_firmware:
4443         tp->rtl_fw = NULL;
4444         goto out;
4445 }
4446
4447 static void rtl_request_firmware(struct rtl8169_private *tp)
4448 {
4449         if (IS_ERR(tp->rtl_fw))
4450                 rtl_request_uncached_firmware(tp);
4451 }
4452
4453 static void rtl_rx_close(struct rtl8169_private *tp)
4454 {
4455         void __iomem *ioaddr = tp->mmio_addr;
4456
4457         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4458 }
4459
4460 DECLARE_RTL_COND(rtl_npq_cond)
4461 {
4462         void __iomem *ioaddr = tp->mmio_addr;
4463
4464         return RTL_R8(TxPoll) & NPQ;
4465 }
4466
4467 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4468 {
4469         void __iomem *ioaddr = tp->mmio_addr;
4470
4471         return RTL_R32(TxConfig) & TXCFG_EMPTY;
4472 }
4473
4474 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4475 {
4476         void __iomem *ioaddr = tp->mmio_addr;
4477
4478         /* Disable interrupts */
4479         rtl8169_irq_mask_and_ack(tp);
4480
4481         rtl_rx_close(tp);
4482
4483         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4484             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4485             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4486                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4487         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4488                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4489                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4490                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4491                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4492                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4493                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4494                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4495                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4496                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4497                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4498                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4499         } else {
4500                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4501                 udelay(100);
4502         }
4503
4504         rtl_hw_reset(tp);
4505 }
4506
4507 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4508 {
4509         void __iomem *ioaddr = tp->mmio_addr;
4510
4511         /* Set DMA burst size and Interframe Gap Time */
4512         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4513                 (InterFrameGap << TxInterFrameGapShift));
4514 }
4515
4516 static void rtl_hw_start(struct net_device *dev)
4517 {
4518         struct rtl8169_private *tp = netdev_priv(dev);
4519
4520         tp->hw_start(dev);
4521
4522         rtl_irq_enable_all(tp);
4523 }
4524
4525 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4526                                          void __iomem *ioaddr)
4527 {
4528         /*
4529          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4530          * register to be written before TxDescAddrLow to work.
4531          * Switching from MMIO to I/O access fixes the issue as well.
4532          */
4533         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4534         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4535         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4536         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4537 }
4538
4539 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4540 {
4541         u16 cmd;
4542
4543         cmd = RTL_R16(CPlusCmd);
4544         RTL_W16(CPlusCmd, cmd);
4545         return cmd;
4546 }
4547
4548 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4549 {
4550         /* Low hurts. Let's disable the filtering. */
4551         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4552 }
4553
4554 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4555 {
4556         static const struct rtl_cfg2_info {
4557                 u32 mac_version;
4558                 u32 clk;
4559                 u32 val;
4560         } cfg2_info [] = {
4561                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4562                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4563                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4564                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4565         };
4566         const struct rtl_cfg2_info *p = cfg2_info;
4567         unsigned int i;
4568         u32 clk;
4569
4570         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4571         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4572                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4573                         RTL_W32(0x7c, p->val);
4574                         break;
4575                 }
4576         }
4577 }
4578
4579 static void rtl_set_rx_mode(struct net_device *dev)
4580 {
4581         struct rtl8169_private *tp = netdev_priv(dev);
4582         void __iomem *ioaddr = tp->mmio_addr;
4583         u32 mc_filter[2];       /* Multicast hash filter */
4584         int rx_mode;
4585         u32 tmp = 0;
4586
4587         if (dev->flags & IFF_PROMISC) {
4588                 /* Unconditionally log net taps. */
4589                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4590                 rx_mode =
4591                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4592                     AcceptAllPhys;
4593                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4594         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4595                    (dev->flags & IFF_ALLMULTI)) {
4596                 /* Too many to filter perfectly -- accept all multicasts. */
4597                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4598                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4599         } else {
4600                 struct netdev_hw_addr *ha;
4601
4602                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4603                 mc_filter[1] = mc_filter[0] = 0;
4604                 netdev_for_each_mc_addr(ha, dev) {
4605                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4606                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4607                         rx_mode |= AcceptMulticast;
4608                 }
4609         }
4610
4611         if (dev->features & NETIF_F_RXALL)
4612                 rx_mode |= (AcceptErr | AcceptRunt);
4613
4614         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4615
4616         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4617                 u32 data = mc_filter[0];
4618
4619                 mc_filter[0] = swab32(mc_filter[1]);
4620                 mc_filter[1] = swab32(data);
4621         }
4622
4623         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4624                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4625
4626         RTL_W32(MAR0 + 4, mc_filter[1]);
4627         RTL_W32(MAR0 + 0, mc_filter[0]);
4628
4629         RTL_W32(RxConfig, tmp);
4630 }
4631
4632 static void rtl_hw_start_8169(struct net_device *dev)
4633 {
4634         struct rtl8169_private *tp = netdev_priv(dev);
4635         void __iomem *ioaddr = tp->mmio_addr;
4636         struct pci_dev *pdev = tp->pci_dev;
4637
4638         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4639                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4640                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4641         }
4642
4643         RTL_W8(Cfg9346, Cfg9346_Unlock);
4644         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4645             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4646             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4647             tp->mac_version == RTL_GIGA_MAC_VER_04)
4648                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4649
4650         rtl_init_rxcfg(tp);
4651
4652         RTL_W8(EarlyTxThres, NoEarlyTx);
4653
4654         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4655
4656         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4657             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4658             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4659             tp->mac_version == RTL_GIGA_MAC_VER_04)
4660                 rtl_set_rx_tx_config_registers(tp);
4661
4662         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4663
4664         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4665             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4666                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4667                         "Bit-3 and bit-14 MUST be 1\n");
4668                 tp->cp_cmd |= (1 << 14);
4669         }
4670
4671         RTL_W16(CPlusCmd, tp->cp_cmd);
4672
4673         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4674
4675         /*
4676          * Undocumented corner. Supposedly:
4677          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4678          */
4679         RTL_W16(IntrMitigate, 0x0000);
4680
4681         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4682
4683         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4684             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4685             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4686             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4687                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4688                 rtl_set_rx_tx_config_registers(tp);
4689         }
4690
4691         RTL_W8(Cfg9346, Cfg9346_Lock);
4692
4693         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4694         RTL_R8(IntrMask);
4695
4696         RTL_W32(RxMissed, 0);
4697
4698         rtl_set_rx_mode(dev);
4699
4700         /* no early-rx interrupts */
4701         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4702 }
4703
4704 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4705 {
4706         if (tp->csi_ops.write)
4707                 tp->csi_ops.write(tp, addr, value);
4708 }
4709
4710 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4711 {
4712         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4713 }
4714
4715 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4716 {
4717         u32 csi;
4718
4719         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4720         rtl_csi_write(tp, 0x070c, csi | bits);
4721 }
4722
4723 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4724 {
4725         rtl_csi_access_enable(tp, 0x17000000);
4726 }
4727
4728 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4729 {
4730         rtl_csi_access_enable(tp, 0x27000000);
4731 }
4732
4733 DECLARE_RTL_COND(rtl_csiar_cond)
4734 {
4735         void __iomem *ioaddr = tp->mmio_addr;
4736
4737         return RTL_R32(CSIAR) & CSIAR_FLAG;
4738 }
4739
4740 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4741 {
4742         void __iomem *ioaddr = tp->mmio_addr;
4743
4744         RTL_W32(CSIDR, value);
4745         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4746                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4747
4748         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4749 }
4750
4751 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4752 {
4753         void __iomem *ioaddr = tp->mmio_addr;
4754
4755         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4756                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4757
4758         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4759                 RTL_R32(CSIDR) : ~0;
4760 }
4761
4762 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4763 {
4764         void __iomem *ioaddr = tp->mmio_addr;
4765
4766         RTL_W32(CSIDR, value);
4767         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4768                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4769                 CSIAR_FUNC_NIC);
4770
4771         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4772 }
4773
4774 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4775 {
4776         void __iomem *ioaddr = tp->mmio_addr;
4777
4778         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4779                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4780
4781         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4782                 RTL_R32(CSIDR) : ~0;
4783 }
4784
4785 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
4786 {
4787         void __iomem *ioaddr = tp->mmio_addr;
4788
4789         RTL_W32(CSIDR, value);
4790         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4791                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4792                 CSIAR_FUNC_NIC2);
4793
4794         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4795 }
4796
4797 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
4798 {
4799         void __iomem *ioaddr = tp->mmio_addr;
4800
4801         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
4802                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4803
4804         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4805                 RTL_R32(CSIDR) : ~0;
4806 }
4807
4808 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4809 {
4810         struct csi_ops *ops = &tp->csi_ops;
4811
4812         switch (tp->mac_version) {
4813         case RTL_GIGA_MAC_VER_01:
4814         case RTL_GIGA_MAC_VER_02:
4815         case RTL_GIGA_MAC_VER_03:
4816         case RTL_GIGA_MAC_VER_04:
4817         case RTL_GIGA_MAC_VER_05:
4818         case RTL_GIGA_MAC_VER_06:
4819         case RTL_GIGA_MAC_VER_10:
4820         case RTL_GIGA_MAC_VER_11:
4821         case RTL_GIGA_MAC_VER_12:
4822         case RTL_GIGA_MAC_VER_13:
4823         case RTL_GIGA_MAC_VER_14:
4824         case RTL_GIGA_MAC_VER_15:
4825         case RTL_GIGA_MAC_VER_16:
4826         case RTL_GIGA_MAC_VER_17:
4827                 ops->write      = NULL;
4828                 ops->read       = NULL;
4829                 break;
4830
4831         case RTL_GIGA_MAC_VER_37:
4832         case RTL_GIGA_MAC_VER_38:
4833                 ops->write      = r8402_csi_write;
4834                 ops->read       = r8402_csi_read;
4835                 break;
4836
4837         case RTL_GIGA_MAC_VER_44:
4838                 ops->write      = r8411_csi_write;
4839                 ops->read       = r8411_csi_read;
4840                 break;
4841
4842         default:
4843                 ops->write      = r8169_csi_write;
4844                 ops->read       = r8169_csi_read;
4845                 break;
4846         }
4847 }
4848
4849 struct ephy_info {
4850         unsigned int offset;
4851         u16 mask;
4852         u16 bits;
4853 };
4854
4855 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4856                           int len)
4857 {
4858         u16 w;
4859
4860         while (len-- > 0) {
4861                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4862                 rtl_ephy_write(tp, e->offset, w);
4863                 e++;
4864         }
4865 }
4866
4867 static void rtl_disable_clock_request(struct pci_dev *pdev)
4868 {
4869         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4870                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4871 }
4872
4873 static void rtl_enable_clock_request(struct pci_dev *pdev)
4874 {
4875         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4876                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4877 }
4878
4879 #define R8168_CPCMD_QUIRK_MASK (\
4880         EnableBist | \
4881         Mac_dbgo_oe | \
4882         Force_half_dup | \
4883         Force_rxflow_en | \
4884         Force_txflow_en | \
4885         Cxpl_dbg_sel | \
4886         ASF | \
4887         PktCntrDisable | \
4888         Mac_dbgo_sel)
4889
4890 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4891 {
4892         void __iomem *ioaddr = tp->mmio_addr;
4893         struct pci_dev *pdev = tp->pci_dev;
4894
4895         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4896
4897         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4898
4899         if (tp->dev->mtu <= ETH_DATA_LEN) {
4900                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4901                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4902         }
4903 }
4904
4905 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4906 {
4907         void __iomem *ioaddr = tp->mmio_addr;
4908
4909         rtl_hw_start_8168bb(tp);
4910
4911         RTL_W8(MaxTxPacketSize, TxPacketMax);
4912
4913         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4914 }
4915
4916 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4917 {
4918         void __iomem *ioaddr = tp->mmio_addr;
4919         struct pci_dev *pdev = tp->pci_dev;
4920
4921         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4922
4923         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4924
4925         if (tp->dev->mtu <= ETH_DATA_LEN)
4926                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4927
4928         rtl_disable_clock_request(pdev);
4929
4930         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4931 }
4932
4933 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4934 {
4935         static const struct ephy_info e_info_8168cp[] = {
4936                 { 0x01, 0,      0x0001 },
4937                 { 0x02, 0x0800, 0x1000 },
4938                 { 0x03, 0,      0x0042 },
4939                 { 0x06, 0x0080, 0x0000 },
4940                 { 0x07, 0,      0x2000 }
4941         };
4942
4943         rtl_csi_access_enable_2(tp);
4944
4945         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4946
4947         __rtl_hw_start_8168cp(tp);
4948 }
4949
4950 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4951 {
4952         void __iomem *ioaddr = tp->mmio_addr;
4953         struct pci_dev *pdev = tp->pci_dev;
4954
4955         rtl_csi_access_enable_2(tp);
4956
4957         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4958
4959         if (tp->dev->mtu <= ETH_DATA_LEN)
4960                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4961
4962         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4963 }
4964
4965 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4966 {
4967         void __iomem *ioaddr = tp->mmio_addr;
4968         struct pci_dev *pdev = tp->pci_dev;
4969
4970         rtl_csi_access_enable_2(tp);
4971
4972         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4973
4974         /* Magic. */
4975         RTL_W8(DBG_REG, 0x20);
4976
4977         RTL_W8(MaxTxPacketSize, TxPacketMax);
4978
4979         if (tp->dev->mtu <= ETH_DATA_LEN)
4980                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4981
4982         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4983 }
4984
4985 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4986 {
4987         void __iomem *ioaddr = tp->mmio_addr;
4988         static const struct ephy_info e_info_8168c_1[] = {
4989                 { 0x02, 0x0800, 0x1000 },
4990                 { 0x03, 0,      0x0002 },
4991                 { 0x06, 0x0080, 0x0000 }
4992         };
4993
4994         rtl_csi_access_enable_2(tp);
4995
4996         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4997
4998         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4999
5000         __rtl_hw_start_8168cp(tp);
5001 }
5002
5003 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5004 {
5005         static const struct ephy_info e_info_8168c_2[] = {
5006                 { 0x01, 0,      0x0001 },
5007                 { 0x03, 0x0400, 0x0220 }
5008         };
5009
5010         rtl_csi_access_enable_2(tp);
5011
5012         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5013
5014         __rtl_hw_start_8168cp(tp);
5015 }
5016
5017 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5018 {
5019         rtl_hw_start_8168c_2(tp);
5020 }
5021
5022 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5023 {
5024         rtl_csi_access_enable_2(tp);
5025
5026         __rtl_hw_start_8168cp(tp);
5027 }
5028
5029 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5030 {
5031         void __iomem *ioaddr = tp->mmio_addr;
5032         struct pci_dev *pdev = tp->pci_dev;
5033
5034         rtl_csi_access_enable_2(tp);
5035
5036         rtl_disable_clock_request(pdev);
5037
5038         RTL_W8(MaxTxPacketSize, TxPacketMax);
5039
5040         if (tp->dev->mtu <= ETH_DATA_LEN)
5041                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5042
5043         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5044 }
5045
5046 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5047 {
5048         void __iomem *ioaddr = tp->mmio_addr;
5049         struct pci_dev *pdev = tp->pci_dev;
5050
5051         rtl_csi_access_enable_1(tp);
5052
5053         if (tp->dev->mtu <= ETH_DATA_LEN)
5054                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5055
5056         RTL_W8(MaxTxPacketSize, TxPacketMax);
5057
5058         rtl_disable_clock_request(pdev);
5059 }
5060
5061 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5062 {
5063         void __iomem *ioaddr = tp->mmio_addr;
5064         struct pci_dev *pdev = tp->pci_dev;
5065         static const struct ephy_info e_info_8168d_4[] = {
5066                 { 0x0b, ~0,     0x48 },
5067                 { 0x19, 0x20,   0x50 },
5068                 { 0x0c, ~0,     0x20 }
5069         };
5070         int i;
5071
5072         rtl_csi_access_enable_1(tp);
5073
5074         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5075
5076         RTL_W8(MaxTxPacketSize, TxPacketMax);
5077
5078         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5079                 const struct ephy_info *e = e_info_8168d_4 + i;
5080                 u16 w;
5081
5082                 w = rtl_ephy_read(tp, e->offset);
5083                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5084         }
5085
5086         rtl_enable_clock_request(pdev);
5087 }
5088
5089 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5090 {
5091         void __iomem *ioaddr = tp->mmio_addr;
5092         struct pci_dev *pdev = tp->pci_dev;
5093         static const struct ephy_info e_info_8168e_1[] = {
5094                 { 0x00, 0x0200, 0x0100 },
5095                 { 0x00, 0x0000, 0x0004 },
5096                 { 0x06, 0x0002, 0x0001 },
5097                 { 0x06, 0x0000, 0x0030 },
5098                 { 0x07, 0x0000, 0x2000 },
5099                 { 0x00, 0x0000, 0x0020 },
5100                 { 0x03, 0x5800, 0x2000 },
5101                 { 0x03, 0x0000, 0x0001 },
5102                 { 0x01, 0x0800, 0x1000 },
5103                 { 0x07, 0x0000, 0x4000 },
5104                 { 0x1e, 0x0000, 0x2000 },
5105                 { 0x19, 0xffff, 0xfe6c },
5106                 { 0x0a, 0x0000, 0x0040 }
5107         };
5108
5109         rtl_csi_access_enable_2(tp);
5110
5111         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5112
5113         if (tp->dev->mtu <= ETH_DATA_LEN)
5114                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5115
5116         RTL_W8(MaxTxPacketSize, TxPacketMax);
5117
5118         rtl_disable_clock_request(pdev);
5119
5120         /* Reset tx FIFO pointer */
5121         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5122         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5123
5124         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5125 }
5126
5127 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5128 {
5129         void __iomem *ioaddr = tp->mmio_addr;
5130         struct pci_dev *pdev = tp->pci_dev;
5131         static const struct ephy_info e_info_8168e_2[] = {
5132                 { 0x09, 0x0000, 0x0080 },
5133                 { 0x19, 0x0000, 0x0224 }
5134         };
5135
5136         rtl_csi_access_enable_1(tp);
5137
5138         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5139
5140         if (tp->dev->mtu <= ETH_DATA_LEN)
5141                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5142
5143         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5144         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5145         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5146         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5147         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5148         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5149         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5150         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5151
5152         RTL_W8(MaxTxPacketSize, EarlySize);
5153
5154         rtl_disable_clock_request(pdev);
5155
5156         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5157         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5158
5159         /* Adjust EEE LED frequency */
5160         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5161
5162         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5163         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5164         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5165 }
5166
5167 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5168 {
5169         void __iomem *ioaddr = tp->mmio_addr;
5170         struct pci_dev *pdev = tp->pci_dev;
5171
5172         rtl_csi_access_enable_2(tp);
5173
5174         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5175
5176         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5177         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5178         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5179         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5180         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5181         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5182         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5183         rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5184         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5185         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5186
5187         RTL_W8(MaxTxPacketSize, EarlySize);
5188
5189         rtl_disable_clock_request(pdev);
5190
5191         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5192         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5193         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5194         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5195         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5196 }
5197
5198 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5199 {
5200         void __iomem *ioaddr = tp->mmio_addr;
5201         static const struct ephy_info e_info_8168f_1[] = {
5202                 { 0x06, 0x00c0, 0x0020 },
5203                 { 0x08, 0x0001, 0x0002 },
5204                 { 0x09, 0x0000, 0x0080 },
5205                 { 0x19, 0x0000, 0x0224 }
5206         };
5207
5208         rtl_hw_start_8168f(tp);
5209
5210         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5211
5212         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5213
5214         /* Adjust EEE LED frequency */
5215         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5216 }
5217
5218 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5219 {
5220         static const struct ephy_info e_info_8168f_1[] = {
5221                 { 0x06, 0x00c0, 0x0020 },
5222                 { 0x0f, 0xffff, 0x5200 },
5223                 { 0x1e, 0x0000, 0x4000 },
5224                 { 0x19, 0x0000, 0x0224 }
5225         };
5226
5227         rtl_hw_start_8168f(tp);
5228
5229         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5230
5231         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5232 }
5233
5234 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5235 {
5236         void __iomem *ioaddr = tp->mmio_addr;
5237         struct pci_dev *pdev = tp->pci_dev;
5238
5239         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5240
5241         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5242         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5243         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5244         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5245
5246         rtl_csi_access_enable_1(tp);
5247
5248         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5249
5250         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5251         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5252         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5253
5254         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5255         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5256         RTL_W8(MaxTxPacketSize, EarlySize);
5257
5258         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5259         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5260
5261         /* Adjust EEE LED frequency */
5262         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5263
5264         rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5265         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5266 }
5267
5268 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5269 {
5270         void __iomem *ioaddr = tp->mmio_addr;
5271         static const struct ephy_info e_info_8168g_2[] = {
5272                 { 0x00, 0x0000, 0x0008 },
5273                 { 0x0c, 0x3df0, 0x0200 },
5274                 { 0x19, 0xffff, 0xfc00 },
5275                 { 0x1e, 0xffff, 0x20eb }
5276         };
5277
5278         rtl_hw_start_8168g_1(tp);
5279
5280         /* disable aspm and clock request before access ephy */
5281         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5282         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5283         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5284 }
5285
5286 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5287 {
5288         void __iomem *ioaddr = tp->mmio_addr;
5289         static const struct ephy_info e_info_8411_2[] = {
5290                 { 0x00, 0x0000, 0x0008 },
5291                 { 0x0c, 0x3df0, 0x0200 },
5292                 { 0x0f, 0xffff, 0x5200 },
5293                 { 0x19, 0x0020, 0x0000 },
5294                 { 0x1e, 0x0000, 0x2000 }
5295         };
5296
5297         rtl_hw_start_8168g_1(tp);
5298
5299         /* disable aspm and clock request before access ephy */
5300         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5301         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5302         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5303 }
5304
5305 static void rtl_hw_start_8168(struct net_device *dev)
5306 {
5307         struct rtl8169_private *tp = netdev_priv(dev);
5308         void __iomem *ioaddr = tp->mmio_addr;
5309
5310         RTL_W8(Cfg9346, Cfg9346_Unlock);
5311
5312         RTL_W8(MaxTxPacketSize, TxPacketMax);
5313
5314         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5315
5316         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5317
5318         RTL_W16(CPlusCmd, tp->cp_cmd);
5319
5320         RTL_W16(IntrMitigate, 0x5151);
5321
5322         /* Work around for RxFIFO overflow. */
5323         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5324                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5325                 tp->event_slow &= ~RxOverflow;
5326         }
5327
5328         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5329
5330         rtl_set_rx_tx_config_registers(tp);
5331
5332         RTL_R8(IntrMask);
5333
5334         switch (tp->mac_version) {
5335         case RTL_GIGA_MAC_VER_11:
5336                 rtl_hw_start_8168bb(tp);
5337                 break;
5338
5339         case RTL_GIGA_MAC_VER_12:
5340         case RTL_GIGA_MAC_VER_17:
5341                 rtl_hw_start_8168bef(tp);
5342                 break;
5343
5344         case RTL_GIGA_MAC_VER_18:
5345                 rtl_hw_start_8168cp_1(tp);
5346                 break;
5347
5348         case RTL_GIGA_MAC_VER_19:
5349                 rtl_hw_start_8168c_1(tp);
5350                 break;
5351
5352         case RTL_GIGA_MAC_VER_20:
5353                 rtl_hw_start_8168c_2(tp);
5354                 break;
5355
5356         case RTL_GIGA_MAC_VER_21:
5357                 rtl_hw_start_8168c_3(tp);
5358                 break;
5359
5360         case RTL_GIGA_MAC_VER_22:
5361                 rtl_hw_start_8168c_4(tp);
5362                 break;
5363
5364         case RTL_GIGA_MAC_VER_23:
5365                 rtl_hw_start_8168cp_2(tp);
5366                 break;
5367
5368         case RTL_GIGA_MAC_VER_24:
5369                 rtl_hw_start_8168cp_3(tp);
5370                 break;
5371
5372         case RTL_GIGA_MAC_VER_25:
5373         case RTL_GIGA_MAC_VER_26:
5374         case RTL_GIGA_MAC_VER_27:
5375                 rtl_hw_start_8168d(tp);
5376                 break;
5377
5378         case RTL_GIGA_MAC_VER_28:
5379                 rtl_hw_start_8168d_4(tp);
5380                 break;
5381
5382         case RTL_GIGA_MAC_VER_31:
5383                 rtl_hw_start_8168dp(tp);
5384                 break;
5385
5386         case RTL_GIGA_MAC_VER_32:
5387         case RTL_GIGA_MAC_VER_33:
5388                 rtl_hw_start_8168e_1(tp);
5389                 break;
5390         case RTL_GIGA_MAC_VER_34:
5391                 rtl_hw_start_8168e_2(tp);
5392                 break;
5393
5394         case RTL_GIGA_MAC_VER_35:
5395         case RTL_GIGA_MAC_VER_36:
5396                 rtl_hw_start_8168f_1(tp);
5397                 break;
5398
5399         case RTL_GIGA_MAC_VER_38:
5400                 rtl_hw_start_8411(tp);
5401                 break;
5402
5403         case RTL_GIGA_MAC_VER_40:
5404         case RTL_GIGA_MAC_VER_41:
5405                 rtl_hw_start_8168g_1(tp);
5406                 break;
5407         case RTL_GIGA_MAC_VER_42:
5408                 rtl_hw_start_8168g_2(tp);
5409                 break;
5410
5411         case RTL_GIGA_MAC_VER_44:
5412                 rtl_hw_start_8411_2(tp);
5413                 break;
5414
5415         default:
5416                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5417                         dev->name, tp->mac_version);
5418                 break;
5419         }
5420
5421         RTL_W8(Cfg9346, Cfg9346_Lock);
5422
5423         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5424
5425         rtl_set_rx_mode(dev);
5426
5427         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5428 }
5429
5430 #define R810X_CPCMD_QUIRK_MASK (\
5431         EnableBist | \
5432         Mac_dbgo_oe | \
5433         Force_half_dup | \
5434         Force_rxflow_en | \
5435         Force_txflow_en | \
5436         Cxpl_dbg_sel | \
5437         ASF | \
5438         PktCntrDisable | \
5439         Mac_dbgo_sel)
5440
5441 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5442 {
5443         void __iomem *ioaddr = tp->mmio_addr;
5444         struct pci_dev *pdev = tp->pci_dev;
5445         static const struct ephy_info e_info_8102e_1[] = {
5446                 { 0x01, 0, 0x6e65 },
5447                 { 0x02, 0, 0x091f },
5448                 { 0x03, 0, 0xc2f9 },
5449                 { 0x06, 0, 0xafb5 },
5450                 { 0x07, 0, 0x0e00 },
5451                 { 0x19, 0, 0xec80 },
5452                 { 0x01, 0, 0x2e65 },
5453                 { 0x01, 0, 0x6e65 }
5454         };
5455         u8 cfg1;
5456
5457         rtl_csi_access_enable_2(tp);
5458
5459         RTL_W8(DBG_REG, FIX_NAK_1);
5460
5461         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5462
5463         RTL_W8(Config1,
5464                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5465         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5466
5467         cfg1 = RTL_R8(Config1);
5468         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5469                 RTL_W8(Config1, cfg1 & ~LEDS0);
5470
5471         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5472 }
5473
5474 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5475 {
5476         void __iomem *ioaddr = tp->mmio_addr;
5477         struct pci_dev *pdev = tp->pci_dev;
5478
5479         rtl_csi_access_enable_2(tp);
5480
5481         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5482
5483         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5484         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5485 }
5486
5487 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5488 {
5489         rtl_hw_start_8102e_2(tp);
5490
5491         rtl_ephy_write(tp, 0x03, 0xc2f9);
5492 }
5493
5494 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5495 {
5496         void __iomem *ioaddr = tp->mmio_addr;
5497         static const struct ephy_info e_info_8105e_1[] = {
5498                 { 0x07, 0, 0x4000 },
5499                 { 0x19, 0, 0x0200 },
5500                 { 0x19, 0, 0x0020 },
5501                 { 0x1e, 0, 0x2000 },
5502                 { 0x03, 0, 0x0001 },
5503                 { 0x19, 0, 0x0100 },
5504                 { 0x19, 0, 0x0004 },
5505                 { 0x0a, 0, 0x0020 }
5506         };
5507
5508         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5509         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5510
5511         /* Disable Early Tally Counter */
5512         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5513
5514         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5515         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5516
5517         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5518 }
5519
5520 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5521 {
5522         rtl_hw_start_8105e_1(tp);
5523         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5524 }
5525
5526 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5527 {
5528         void __iomem *ioaddr = tp->mmio_addr;
5529         static const struct ephy_info e_info_8402[] = {
5530                 { 0x19, 0xffff, 0xff64 },
5531                 { 0x1e, 0, 0x4000 }
5532         };
5533
5534         rtl_csi_access_enable_2(tp);
5535
5536         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5537         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5538
5539         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5540         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5541
5542         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5543
5544         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5545
5546         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5547         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5548         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5549         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5550         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5551         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5552         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5553 }
5554
5555 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5556 {
5557         void __iomem *ioaddr = tp->mmio_addr;
5558
5559         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5560         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5561
5562         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5563         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5564         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5565 }
5566
5567 static void rtl_hw_start_8101(struct net_device *dev)
5568 {
5569         struct rtl8169_private *tp = netdev_priv(dev);
5570         void __iomem *ioaddr = tp->mmio_addr;
5571         struct pci_dev *pdev = tp->pci_dev;
5572
5573         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5574                 tp->event_slow &= ~RxFIFOOver;
5575
5576         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5577             tp->mac_version == RTL_GIGA_MAC_VER_16)
5578                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5579                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5580
5581         RTL_W8(Cfg9346, Cfg9346_Unlock);
5582
5583         RTL_W8(MaxTxPacketSize, TxPacketMax);
5584
5585         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5586
5587         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5588         RTL_W16(CPlusCmd, tp->cp_cmd);
5589
5590         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5591
5592         rtl_set_rx_tx_config_registers(tp);
5593
5594         switch (tp->mac_version) {
5595         case RTL_GIGA_MAC_VER_07:
5596                 rtl_hw_start_8102e_1(tp);
5597                 break;
5598
5599         case RTL_GIGA_MAC_VER_08:
5600                 rtl_hw_start_8102e_3(tp);
5601                 break;
5602
5603         case RTL_GIGA_MAC_VER_09:
5604                 rtl_hw_start_8102e_2(tp);
5605                 break;
5606
5607         case RTL_GIGA_MAC_VER_29:
5608                 rtl_hw_start_8105e_1(tp);
5609                 break;
5610         case RTL_GIGA_MAC_VER_30:
5611                 rtl_hw_start_8105e_2(tp);
5612                 break;
5613
5614         case RTL_GIGA_MAC_VER_37:
5615                 rtl_hw_start_8402(tp);
5616                 break;
5617
5618         case RTL_GIGA_MAC_VER_39:
5619                 rtl_hw_start_8106(tp);
5620                 break;
5621         case RTL_GIGA_MAC_VER_43:
5622                 rtl_hw_start_8168g_2(tp);
5623                 break;
5624         }
5625
5626         RTL_W8(Cfg9346, Cfg9346_Lock);
5627
5628         RTL_W16(IntrMitigate, 0x0000);
5629
5630         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5631
5632         rtl_set_rx_mode(dev);
5633
5634         RTL_R8(IntrMask);
5635
5636         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5637 }
5638
5639 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5640 {
5641         struct rtl8169_private *tp = netdev_priv(dev);
5642
5643         if (new_mtu < ETH_ZLEN ||
5644             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5645                 return -EINVAL;
5646
5647         if (new_mtu > ETH_DATA_LEN)
5648                 rtl_hw_jumbo_enable(tp);
5649         else
5650                 rtl_hw_jumbo_disable(tp);
5651
5652         dev->mtu = new_mtu;
5653         netdev_update_features(dev);
5654
5655         return 0;
5656 }
5657
5658 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5659 {
5660         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5661         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5662 }
5663
5664 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5665                                      void **data_buff, struct RxDesc *desc)
5666 {
5667         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5668                          DMA_FROM_DEVICE);
5669
5670         kfree(*data_buff);
5671         *data_buff = NULL;
5672         rtl8169_make_unusable_by_asic(desc);
5673 }
5674
5675 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5676 {
5677         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5678
5679         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5680 }
5681
5682 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5683                                        u32 rx_buf_sz)
5684 {
5685         desc->addr = cpu_to_le64(mapping);
5686         wmb();
5687         rtl8169_mark_to_asic(desc, rx_buf_sz);
5688 }
5689
5690 static inline void *rtl8169_align(void *data)
5691 {
5692         return (void *)ALIGN((long)data, 16);
5693 }
5694
5695 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5696                                              struct RxDesc *desc)
5697 {
5698         void *data;
5699         dma_addr_t mapping;
5700         struct device *d = &tp->pci_dev->dev;
5701         struct net_device *dev = tp->dev;
5702         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5703
5704         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5705         if (!data)
5706                 return NULL;
5707
5708         if (rtl8169_align(data) != data) {
5709                 kfree(data);
5710                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5711                 if (!data)
5712                         return NULL;
5713         }
5714
5715         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5716                                  DMA_FROM_DEVICE);
5717         if (unlikely(dma_mapping_error(d, mapping))) {
5718                 if (net_ratelimit())
5719                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5720                 goto err_out;
5721         }
5722
5723         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5724         return data;
5725
5726 err_out:
5727         kfree(data);
5728         return NULL;
5729 }
5730
5731 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5732 {
5733         unsigned int i;
5734
5735         for (i = 0; i < NUM_RX_DESC; i++) {
5736                 if (tp->Rx_databuff[i]) {
5737                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5738                                             tp->RxDescArray + i);
5739                 }
5740         }
5741 }
5742
5743 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5744 {
5745         desc->opts1 |= cpu_to_le32(RingEnd);
5746 }
5747
5748 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5749 {
5750         unsigned int i;
5751
5752         for (i = 0; i < NUM_RX_DESC; i++) {
5753                 void *data;
5754
5755                 if (tp->Rx_databuff[i])
5756                         continue;
5757
5758                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5759                 if (!data) {
5760                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5761                         goto err_out;
5762                 }
5763                 tp->Rx_databuff[i] = data;
5764         }
5765
5766         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5767         return 0;
5768
5769 err_out:
5770         rtl8169_rx_clear(tp);
5771         return -ENOMEM;
5772 }
5773
5774 static int rtl8169_init_ring(struct net_device *dev)
5775 {
5776         struct rtl8169_private *tp = netdev_priv(dev);
5777
5778         rtl8169_init_ring_indexes(tp);
5779
5780         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5781         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5782
5783         return rtl8169_rx_fill(tp);
5784 }
5785
5786 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5787                                  struct TxDesc *desc)
5788 {
5789         unsigned int len = tx_skb->len;
5790
5791         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5792
5793         desc->opts1 = 0x00;
5794         desc->opts2 = 0x00;
5795         desc->addr = 0x00;
5796         tx_skb->len = 0;
5797 }
5798
5799 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5800                                    unsigned int n)
5801 {
5802         unsigned int i;
5803
5804         for (i = 0; i < n; i++) {
5805                 unsigned int entry = (start + i) % NUM_TX_DESC;
5806                 struct ring_info *tx_skb = tp->tx_skb + entry;
5807                 unsigned int len = tx_skb->len;
5808
5809                 if (len) {
5810                         struct sk_buff *skb = tx_skb->skb;
5811
5812                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5813                                              tp->TxDescArray + entry);
5814                         if (skb) {
5815                                 tp->dev->stats.tx_dropped++;
5816                                 dev_kfree_skb_any(skb);
5817                                 tx_skb->skb = NULL;
5818                         }
5819                 }
5820         }
5821 }
5822
5823 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5824 {
5825         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5826         tp->cur_tx = tp->dirty_tx = 0;
5827 }
5828
5829 static void rtl_reset_work(struct rtl8169_private *tp)
5830 {
5831         struct net_device *dev = tp->dev;
5832         int i;
5833
5834         napi_disable(&tp->napi);
5835         netif_stop_queue(dev);
5836         synchronize_sched();
5837
5838         rtl8169_hw_reset(tp);
5839
5840         for (i = 0; i < NUM_RX_DESC; i++)
5841                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5842
5843         rtl8169_tx_clear(tp);
5844         rtl8169_init_ring_indexes(tp);
5845
5846         napi_enable(&tp->napi);
5847         rtl_hw_start(dev);
5848         netif_wake_queue(dev);
5849         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5850 }
5851
5852 static void rtl8169_tx_timeout(struct net_device *dev)
5853 {
5854         struct rtl8169_private *tp = netdev_priv(dev);
5855
5856         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5857 }
5858
5859 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5860                               u32 *opts)
5861 {
5862         struct skb_shared_info *info = skb_shinfo(skb);
5863         unsigned int cur_frag, entry;
5864         struct TxDesc * uninitialized_var(txd);
5865         struct device *d = &tp->pci_dev->dev;
5866
5867         entry = tp->cur_tx;
5868         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5869                 const skb_frag_t *frag = info->frags + cur_frag;
5870                 dma_addr_t mapping;
5871                 u32 status, len;
5872                 void *addr;
5873
5874                 entry = (entry + 1) % NUM_TX_DESC;
5875
5876                 txd = tp->TxDescArray + entry;
5877                 len = skb_frag_size(frag);
5878                 addr = skb_frag_address(frag);
5879                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5880                 if (unlikely(dma_mapping_error(d, mapping))) {
5881                         if (net_ratelimit())
5882                                 netif_err(tp, drv, tp->dev,
5883                                           "Failed to map TX fragments DMA!\n");
5884                         goto err_out;
5885                 }
5886
5887                 /* Anti gcc 2.95.3 bugware (sic) */
5888                 status = opts[0] | len |
5889                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5890
5891                 txd->opts1 = cpu_to_le32(status);
5892                 txd->opts2 = cpu_to_le32(opts[1]);
5893                 txd->addr = cpu_to_le64(mapping);
5894
5895                 tp->tx_skb[entry].len = len;
5896         }
5897
5898         if (cur_frag) {
5899                 tp->tx_skb[entry].skb = skb;
5900                 txd->opts1 |= cpu_to_le32(LastFrag);
5901         }
5902
5903         return cur_frag;
5904
5905 err_out:
5906         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5907         return -EIO;
5908 }
5909
5910 static bool rtl_skb_pad(struct sk_buff *skb)
5911 {
5912         if (skb_padto(skb, ETH_ZLEN))
5913                 return false;
5914         skb_put(skb, ETH_ZLEN - skb->len);
5915         return true;
5916 }
5917
5918 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5919 {
5920         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5921 }
5922
5923 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5924                                 struct sk_buff *skb, u32 *opts)
5925 {
5926         u32 mss = skb_shinfo(skb)->gso_size;
5927
5928         if (mss) {
5929                 opts[0] |= TD_LSO;
5930                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5931         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5932                 const struct iphdr *ip = ip_hdr(skb);
5933
5934                 if (ip->protocol == IPPROTO_TCP)
5935                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5936                 else if (ip->protocol == IPPROTO_UDP)
5937                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5938                 else
5939                         WARN_ON_ONCE(1);
5940         }
5941
5942         return true;
5943 }
5944
5945 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5946                                 struct sk_buff *skb, u32 *opts)
5947 {
5948         u32 transport_offset = (u32)skb_transport_offset(skb);
5949         u32 mss = skb_shinfo(skb)->gso_size;
5950
5951         if (mss) {
5952                 opts[0] |= TD1_GTSENV4;
5953                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5954                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5955         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5956                 const struct iphdr *ip = ip_hdr(skb);
5957
5958                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5959                         return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5960
5961                 if (ip->protocol == IPPROTO_TCP)
5962                         opts[1] |= TD1_IP_CS | TD1_TCP_CS;
5963                 else if (ip->protocol == IPPROTO_UDP)
5964                         opts[1] |= TD1_IP_CS | TD1_UDP_CS;
5965                 else
5966                         WARN_ON_ONCE(1);
5967         } else {
5968                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5969                         return rtl_skb_pad(skb);
5970         }
5971
5972         return true;
5973 }
5974
5975 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5976                                       struct net_device *dev)
5977 {
5978         struct rtl8169_private *tp = netdev_priv(dev);
5979         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5980         struct TxDesc *txd = tp->TxDescArray + entry;
5981         void __iomem *ioaddr = tp->mmio_addr;
5982         struct device *d = &tp->pci_dev->dev;
5983         dma_addr_t mapping;
5984         u32 status, len;
5985         u32 opts[2];
5986         int frags;
5987
5988         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5989                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5990                 goto err_stop_0;
5991         }
5992
5993         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5994                 goto err_stop_0;
5995
5996         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5997         opts[0] = DescOwn;
5998
5999         if (!tp->tso_csum(tp, skb, opts))
6000                 goto err_update_stats;
6001
6002         len = skb_headlen(skb);
6003         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6004         if (unlikely(dma_mapping_error(d, mapping))) {
6005                 if (net_ratelimit())
6006                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6007                 goto err_dma_0;
6008         }
6009
6010         tp->tx_skb[entry].len = len;
6011         txd->addr = cpu_to_le64(mapping);
6012
6013         frags = rtl8169_xmit_frags(tp, skb, opts);
6014         if (frags < 0)
6015                 goto err_dma_1;
6016         else if (frags)
6017                 opts[0] |= FirstFrag;
6018         else {
6019                 opts[0] |= FirstFrag | LastFrag;
6020                 tp->tx_skb[entry].skb = skb;
6021         }
6022
6023         txd->opts2 = cpu_to_le32(opts[1]);
6024
6025         skb_tx_timestamp(skb);
6026
6027         wmb();
6028
6029         /* Anti gcc 2.95.3 bugware (sic) */
6030         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6031         txd->opts1 = cpu_to_le32(status);
6032
6033         tp->cur_tx += frags + 1;
6034
6035         wmb();
6036
6037         RTL_W8(TxPoll, NPQ);
6038
6039         mmiowb();
6040
6041         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6042                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6043                  * not miss a ring update when it notices a stopped queue.
6044                  */
6045                 smp_wmb();
6046                 netif_stop_queue(dev);
6047                 /* Sync with rtl_tx:
6048                  * - publish queue status and cur_tx ring index (write barrier)
6049                  * - refresh dirty_tx ring index (read barrier).
6050                  * May the current thread have a pessimistic view of the ring
6051                  * status and forget to wake up queue, a racing rtl_tx thread
6052                  * can't.
6053                  */
6054                 smp_mb();
6055                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6056                         netif_wake_queue(dev);
6057         }
6058
6059         return NETDEV_TX_OK;
6060
6061 err_dma_1:
6062         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6063 err_dma_0:
6064         dev_kfree_skb_any(skb);
6065 err_update_stats:
6066         dev->stats.tx_dropped++;
6067         return NETDEV_TX_OK;
6068
6069 err_stop_0:
6070         netif_stop_queue(dev);
6071         dev->stats.tx_dropped++;
6072         return NETDEV_TX_BUSY;
6073 }
6074
6075 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6076 {
6077         struct rtl8169_private *tp = netdev_priv(dev);
6078         struct pci_dev *pdev = tp->pci_dev;
6079         u16 pci_status, pci_cmd;
6080
6081         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6082         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6083
6084         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6085                   pci_cmd, pci_status);
6086
6087         /*
6088          * The recovery sequence below admits a very elaborated explanation:
6089          * - it seems to work;
6090          * - I did not see what else could be done;
6091          * - it makes iop3xx happy.
6092          *
6093          * Feel free to adjust to your needs.
6094          */
6095         if (pdev->broken_parity_status)
6096                 pci_cmd &= ~PCI_COMMAND_PARITY;
6097         else
6098                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6099
6100         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6101
6102         pci_write_config_word(pdev, PCI_STATUS,
6103                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6104                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6105                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6106
6107         /* The infamous DAC f*ckup only happens at boot time */
6108         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6109                 void __iomem *ioaddr = tp->mmio_addr;
6110
6111                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6112                 tp->cp_cmd &= ~PCIDAC;
6113                 RTL_W16(CPlusCmd, tp->cp_cmd);
6114                 dev->features &= ~NETIF_F_HIGHDMA;
6115         }
6116
6117         rtl8169_hw_reset(tp);
6118
6119         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6120 }
6121
6122 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6123 {
6124         unsigned int dirty_tx, tx_left;
6125
6126         dirty_tx = tp->dirty_tx;
6127         smp_rmb();
6128         tx_left = tp->cur_tx - dirty_tx;
6129
6130         while (tx_left > 0) {
6131                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6132                 struct ring_info *tx_skb = tp->tx_skb + entry;
6133                 u32 status;
6134
6135                 rmb();
6136                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6137                 if (status & DescOwn)
6138                         break;
6139
6140                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6141                                      tp->TxDescArray + entry);
6142                 if (status & LastFrag) {
6143                         u64_stats_update_begin(&tp->tx_stats.syncp);
6144                         tp->tx_stats.packets++;
6145                         tp->tx_stats.bytes += tx_skb->skb->len;
6146                         u64_stats_update_end(&tp->tx_stats.syncp);
6147                         dev_kfree_skb_any(tx_skb->skb);
6148                         tx_skb->skb = NULL;
6149                 }
6150                 dirty_tx++;
6151                 tx_left--;
6152         }
6153
6154         if (tp->dirty_tx != dirty_tx) {
6155                 tp->dirty_tx = dirty_tx;
6156                 /* Sync with rtl8169_start_xmit:
6157                  * - publish dirty_tx ring index (write barrier)
6158                  * - refresh cur_tx ring index and queue status (read barrier)
6159                  * May the current thread miss the stopped queue condition,
6160                  * a racing xmit thread can only have a right view of the
6161                  * ring status.
6162                  */
6163                 smp_mb();
6164                 if (netif_queue_stopped(dev) &&
6165                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6166                         netif_wake_queue(dev);
6167                 }
6168                 /*
6169                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6170                  * too close. Let's kick an extra TxPoll request when a burst
6171                  * of start_xmit activity is detected (if it is not detected,
6172                  * it is slow enough). -- FR
6173                  */
6174                 if (tp->cur_tx != dirty_tx) {
6175                         void __iomem *ioaddr = tp->mmio_addr;
6176
6177                         RTL_W8(TxPoll, NPQ);
6178                 }
6179         }
6180 }
6181
6182 static inline int rtl8169_fragmented_frame(u32 status)
6183 {
6184         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6185 }
6186
6187 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6188 {
6189         u32 status = opts1 & RxProtoMask;
6190
6191         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6192             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6193                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6194         else
6195                 skb_checksum_none_assert(skb);
6196 }
6197
6198 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6199                                            struct rtl8169_private *tp,
6200                                            int pkt_size,
6201                                            dma_addr_t addr)
6202 {
6203         struct sk_buff *skb;
6204         struct device *d = &tp->pci_dev->dev;
6205
6206         data = rtl8169_align(data);
6207         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6208         prefetch(data);
6209         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6210         if (skb)
6211                 memcpy(skb->data, data, pkt_size);
6212         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6213
6214         return skb;
6215 }
6216
6217 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6218 {
6219         unsigned int cur_rx, rx_left;
6220         unsigned int count;
6221
6222         cur_rx = tp->cur_rx;
6223
6224         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6225                 unsigned int entry = cur_rx % NUM_RX_DESC;
6226                 struct RxDesc *desc = tp->RxDescArray + entry;
6227                 u32 status;
6228
6229                 rmb();
6230                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6231
6232                 if (status & DescOwn)
6233                         break;
6234                 if (unlikely(status & RxRES)) {
6235                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6236                                    status);
6237                         dev->stats.rx_errors++;
6238                         if (status & (RxRWT | RxRUNT))
6239                                 dev->stats.rx_length_errors++;
6240                         if (status & RxCRC)
6241                                 dev->stats.rx_crc_errors++;
6242                         if (status & RxFOVF) {
6243                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6244                                 dev->stats.rx_fifo_errors++;
6245                         }
6246                         if ((status & (RxRUNT | RxCRC)) &&
6247                             !(status & (RxRWT | RxFOVF)) &&
6248                             (dev->features & NETIF_F_RXALL))
6249                                 goto process_pkt;
6250                 } else {
6251                         struct sk_buff *skb;
6252                         dma_addr_t addr;
6253                         int pkt_size;
6254
6255 process_pkt:
6256                         addr = le64_to_cpu(desc->addr);
6257                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6258                                 pkt_size = (status & 0x00003fff) - 4;
6259                         else
6260                                 pkt_size = status & 0x00003fff;
6261
6262                         /*
6263                          * The driver does not support incoming fragmented
6264                          * frames. They are seen as a symptom of over-mtu
6265                          * sized frames.
6266                          */
6267                         if (unlikely(rtl8169_fragmented_frame(status))) {
6268                                 dev->stats.rx_dropped++;
6269                                 dev->stats.rx_length_errors++;
6270                                 goto release_descriptor;
6271                         }
6272
6273                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6274                                                   tp, pkt_size, addr);
6275                         if (!skb) {
6276                                 dev->stats.rx_dropped++;
6277                                 goto release_descriptor;
6278                         }
6279
6280                         rtl8169_rx_csum(skb, status);
6281                         skb_put(skb, pkt_size);
6282                         skb->protocol = eth_type_trans(skb, dev);
6283
6284                         rtl8169_rx_vlan_tag(desc, skb);
6285
6286                         napi_gro_receive(&tp->napi, skb);
6287
6288                         u64_stats_update_begin(&tp->rx_stats.syncp);
6289                         tp->rx_stats.packets++;
6290                         tp->rx_stats.bytes += pkt_size;
6291                         u64_stats_update_end(&tp->rx_stats.syncp);
6292                 }
6293 release_descriptor:
6294                 desc->opts2 = 0;
6295                 wmb();
6296                 rtl8169_mark_to_asic(desc, rx_buf_sz);
6297         }
6298
6299         count = cur_rx - tp->cur_rx;
6300         tp->cur_rx = cur_rx;
6301
6302         return count;
6303 }
6304
6305 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6306 {
6307         struct net_device *dev = dev_instance;
6308         struct rtl8169_private *tp = netdev_priv(dev);
6309         int handled = 0;
6310         u16 status;
6311
6312         status = rtl_get_events(tp);
6313         if (status && status != 0xffff) {
6314                 status &= RTL_EVENT_NAPI | tp->event_slow;
6315                 if (status) {
6316                         handled = 1;
6317
6318                         rtl_irq_disable(tp);
6319                         napi_schedule(&tp->napi);
6320                 }
6321         }
6322         return IRQ_RETVAL(handled);
6323 }
6324
6325 /*
6326  * Workqueue context.
6327  */
6328 static void rtl_slow_event_work(struct rtl8169_private *tp)
6329 {
6330         struct net_device *dev = tp->dev;
6331         u16 status;
6332
6333         status = rtl_get_events(tp) & tp->event_slow;
6334         rtl_ack_events(tp, status);
6335
6336         if (unlikely(status & RxFIFOOver)) {
6337                 switch (tp->mac_version) {
6338                 /* Work around for rx fifo overflow */
6339                 case RTL_GIGA_MAC_VER_11:
6340                         netif_stop_queue(dev);
6341                         /* XXX - Hack alert. See rtl_task(). */
6342                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6343                 default:
6344                         break;
6345                 }
6346         }
6347
6348         if (unlikely(status & SYSErr))
6349                 rtl8169_pcierr_interrupt(dev);
6350
6351         if (status & LinkChg)
6352                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6353
6354         rtl_irq_enable_all(tp);
6355 }
6356
6357 static void rtl_task(struct work_struct *work)
6358 {
6359         static const struct {
6360                 int bitnr;
6361                 void (*action)(struct rtl8169_private *);
6362         } rtl_work[] = {
6363                 /* XXX - keep rtl_slow_event_work() as first element. */
6364                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6365                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6366                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
6367         };
6368         struct rtl8169_private *tp =
6369                 container_of(work, struct rtl8169_private, wk.work);
6370         struct net_device *dev = tp->dev;
6371         int i;
6372
6373         rtl_lock_work(tp);
6374
6375         if (!netif_running(dev) ||
6376             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6377                 goto out_unlock;
6378
6379         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6380                 bool pending;
6381
6382                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6383                 if (pending)
6384                         rtl_work[i].action(tp);
6385         }
6386
6387 out_unlock:
6388         rtl_unlock_work(tp);
6389 }
6390
6391 static int rtl8169_poll(struct napi_struct *napi, int budget)
6392 {
6393         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6394         struct net_device *dev = tp->dev;
6395         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6396         int work_done= 0;
6397         u16 status;
6398
6399         status = rtl_get_events(tp);
6400         rtl_ack_events(tp, status & ~tp->event_slow);
6401
6402         if (status & RTL_EVENT_NAPI_RX)
6403                 work_done = rtl_rx(dev, tp, (u32) budget);
6404
6405         if (status & RTL_EVENT_NAPI_TX)
6406                 rtl_tx(dev, tp);
6407
6408         if (status & tp->event_slow) {
6409                 enable_mask &= ~tp->event_slow;
6410
6411                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6412         }
6413
6414         if (work_done < budget) {
6415                 napi_complete(napi);
6416
6417                 rtl_irq_enable(tp, enable_mask);
6418                 mmiowb();
6419         }
6420
6421         return work_done;
6422 }
6423
6424 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6425 {
6426         struct rtl8169_private *tp = netdev_priv(dev);
6427
6428         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6429                 return;
6430
6431         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6432         RTL_W32(RxMissed, 0);
6433 }
6434
6435 static void rtl8169_down(struct net_device *dev)
6436 {
6437         struct rtl8169_private *tp = netdev_priv(dev);
6438         void __iomem *ioaddr = tp->mmio_addr;
6439
6440         del_timer_sync(&tp->timer);
6441
6442         napi_disable(&tp->napi);
6443         netif_stop_queue(dev);
6444
6445         rtl8169_hw_reset(tp);
6446         /*
6447          * At this point device interrupts can not be enabled in any function,
6448          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6449          * and napi is disabled (rtl8169_poll).
6450          */
6451         rtl8169_rx_missed(dev, ioaddr);
6452
6453         /* Give a racing hard_start_xmit a few cycles to complete. */
6454         synchronize_sched();
6455
6456         rtl8169_tx_clear(tp);
6457
6458         rtl8169_rx_clear(tp);
6459
6460         rtl_pll_power_down(tp);
6461 }
6462
6463 static int rtl8169_close(struct net_device *dev)
6464 {
6465         struct rtl8169_private *tp = netdev_priv(dev);
6466         struct pci_dev *pdev = tp->pci_dev;
6467
6468         pm_runtime_get_sync(&pdev->dev);
6469
6470         /* Update counters before going down */
6471         rtl8169_update_counters(dev);
6472
6473         rtl_lock_work(tp);
6474         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6475
6476         rtl8169_down(dev);
6477         rtl_unlock_work(tp);
6478
6479         cancel_work_sync(&tp->wk.work);
6480
6481         free_irq(pdev->irq, dev);
6482
6483         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6484                           tp->RxPhyAddr);
6485         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6486                           tp->TxPhyAddr);
6487         tp->TxDescArray = NULL;
6488         tp->RxDescArray = NULL;
6489
6490         pm_runtime_put_sync(&pdev->dev);
6491
6492         return 0;
6493 }
6494
6495 #ifdef CONFIG_NET_POLL_CONTROLLER
6496 static void rtl8169_netpoll(struct net_device *dev)
6497 {
6498         struct rtl8169_private *tp = netdev_priv(dev);
6499
6500         rtl8169_interrupt(tp->pci_dev->irq, dev);
6501 }
6502 #endif
6503
6504 static int rtl_open(struct net_device *dev)
6505 {
6506         struct rtl8169_private *tp = netdev_priv(dev);
6507         void __iomem *ioaddr = tp->mmio_addr;
6508         struct pci_dev *pdev = tp->pci_dev;
6509         int retval = -ENOMEM;
6510
6511         pm_runtime_get_sync(&pdev->dev);
6512
6513         /*
6514          * Rx and Tx descriptors needs 256 bytes alignment.
6515          * dma_alloc_coherent provides more.
6516          */
6517         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6518                                              &tp->TxPhyAddr, GFP_KERNEL);
6519         if (!tp->TxDescArray)
6520                 goto err_pm_runtime_put;
6521
6522         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6523                                              &tp->RxPhyAddr, GFP_KERNEL);
6524         if (!tp->RxDescArray)
6525                 goto err_free_tx_0;
6526
6527         retval = rtl8169_init_ring(dev);
6528         if (retval < 0)
6529                 goto err_free_rx_1;
6530
6531         INIT_WORK(&tp->wk.work, rtl_task);
6532
6533         smp_mb();
6534
6535         rtl_request_firmware(tp);
6536
6537         retval = request_irq(pdev->irq, rtl8169_interrupt,
6538                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6539                              dev->name, dev);
6540         if (retval < 0)
6541                 goto err_release_fw_2;
6542
6543         rtl_lock_work(tp);
6544
6545         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6546
6547         napi_enable(&tp->napi);
6548
6549         rtl8169_init_phy(dev, tp);
6550
6551         __rtl8169_set_features(dev, dev->features);
6552
6553         rtl_pll_power_up(tp);
6554
6555         rtl_hw_start(dev);
6556
6557         netif_start_queue(dev);
6558
6559         rtl_unlock_work(tp);
6560
6561         tp->saved_wolopts = 0;
6562         pm_runtime_put_noidle(&pdev->dev);
6563
6564         rtl8169_check_link_status(dev, tp, ioaddr);
6565 out:
6566         return retval;
6567
6568 err_release_fw_2:
6569         rtl_release_firmware(tp);
6570         rtl8169_rx_clear(tp);
6571 err_free_rx_1:
6572         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6573                           tp->RxPhyAddr);
6574         tp->RxDescArray = NULL;
6575 err_free_tx_0:
6576         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6577                           tp->TxPhyAddr);
6578         tp->TxDescArray = NULL;
6579 err_pm_runtime_put:
6580         pm_runtime_put_noidle(&pdev->dev);
6581         goto out;
6582 }
6583
6584 static struct rtnl_link_stats64 *
6585 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6586 {
6587         struct rtl8169_private *tp = netdev_priv(dev);
6588         void __iomem *ioaddr = tp->mmio_addr;
6589         unsigned int start;
6590
6591         if (netif_running(dev))
6592                 rtl8169_rx_missed(dev, ioaddr);
6593
6594         do {
6595                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6596                 stats->rx_packets = tp->rx_stats.packets;
6597                 stats->rx_bytes = tp->rx_stats.bytes;
6598         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6599
6600
6601         do {
6602                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6603                 stats->tx_packets = tp->tx_stats.packets;
6604                 stats->tx_bytes = tp->tx_stats.bytes;
6605         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6606
6607         stats->rx_dropped       = dev->stats.rx_dropped;
6608         stats->tx_dropped       = dev->stats.tx_dropped;
6609         stats->rx_length_errors = dev->stats.rx_length_errors;
6610         stats->rx_errors        = dev->stats.rx_errors;
6611         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6612         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6613         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6614
6615         return stats;
6616 }
6617
6618 static void rtl8169_net_suspend(struct net_device *dev)
6619 {
6620         struct rtl8169_private *tp = netdev_priv(dev);
6621
6622         if (!netif_running(dev))
6623                 return;
6624
6625         netif_device_detach(dev);
6626         netif_stop_queue(dev);
6627
6628         rtl_lock_work(tp);
6629         napi_disable(&tp->napi);
6630         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6631         rtl_unlock_work(tp);
6632
6633         rtl_pll_power_down(tp);
6634 }
6635
6636 #ifdef CONFIG_PM
6637
6638 static int rtl8169_suspend(struct device *device)
6639 {
6640         struct pci_dev *pdev = to_pci_dev(device);
6641         struct net_device *dev = pci_get_drvdata(pdev);
6642
6643         rtl8169_net_suspend(dev);
6644
6645         return 0;
6646 }
6647
6648 static void __rtl8169_resume(struct net_device *dev)
6649 {
6650         struct rtl8169_private *tp = netdev_priv(dev);
6651
6652         netif_device_attach(dev);
6653
6654         rtl_pll_power_up(tp);
6655
6656         rtl_lock_work(tp);
6657         napi_enable(&tp->napi);
6658         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6659         rtl_unlock_work(tp);
6660
6661         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6662 }
6663
6664 static int rtl8169_resume(struct device *device)
6665 {
6666         struct pci_dev *pdev = to_pci_dev(device);
6667         struct net_device *dev = pci_get_drvdata(pdev);
6668         struct rtl8169_private *tp = netdev_priv(dev);
6669
6670         rtl8169_init_phy(dev, tp);
6671
6672         if (netif_running(dev))
6673                 __rtl8169_resume(dev);
6674
6675         return 0;
6676 }
6677
6678 static int rtl8169_runtime_suspend(struct device *device)
6679 {
6680         struct pci_dev *pdev = to_pci_dev(device);
6681         struct net_device *dev = pci_get_drvdata(pdev);
6682         struct rtl8169_private *tp = netdev_priv(dev);
6683
6684         if (!tp->TxDescArray)
6685                 return 0;
6686
6687         rtl_lock_work(tp);
6688         tp->saved_wolopts = __rtl8169_get_wol(tp);
6689         __rtl8169_set_wol(tp, WAKE_ANY);
6690         rtl_unlock_work(tp);
6691
6692         rtl8169_net_suspend(dev);
6693
6694         return 0;
6695 }
6696
6697 static int rtl8169_runtime_resume(struct device *device)
6698 {
6699         struct pci_dev *pdev = to_pci_dev(device);
6700         struct net_device *dev = pci_get_drvdata(pdev);
6701         struct rtl8169_private *tp = netdev_priv(dev);
6702
6703         if (!tp->TxDescArray)
6704                 return 0;
6705
6706         rtl_lock_work(tp);
6707         __rtl8169_set_wol(tp, tp->saved_wolopts);
6708         tp->saved_wolopts = 0;
6709         rtl_unlock_work(tp);
6710
6711         rtl8169_init_phy(dev, tp);
6712
6713         __rtl8169_resume(dev);
6714
6715         return 0;
6716 }
6717
6718 static int rtl8169_runtime_idle(struct device *device)
6719 {
6720         struct pci_dev *pdev = to_pci_dev(device);
6721         struct net_device *dev = pci_get_drvdata(pdev);
6722         struct rtl8169_private *tp = netdev_priv(dev);
6723
6724         return tp->TxDescArray ? -EBUSY : 0;
6725 }
6726
6727 static const struct dev_pm_ops rtl8169_pm_ops = {
6728         .suspend                = rtl8169_suspend,
6729         .resume                 = rtl8169_resume,
6730         .freeze                 = rtl8169_suspend,
6731         .thaw                   = rtl8169_resume,
6732         .poweroff               = rtl8169_suspend,
6733         .restore                = rtl8169_resume,
6734         .runtime_suspend        = rtl8169_runtime_suspend,
6735         .runtime_resume         = rtl8169_runtime_resume,
6736         .runtime_idle           = rtl8169_runtime_idle,
6737 };
6738
6739 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6740
6741 #else /* !CONFIG_PM */
6742
6743 #define RTL8169_PM_OPS  NULL
6744
6745 #endif /* !CONFIG_PM */
6746
6747 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6748 {
6749         void __iomem *ioaddr = tp->mmio_addr;
6750
6751         /* WoL fails with 8168b when the receiver is disabled. */
6752         switch (tp->mac_version) {
6753         case RTL_GIGA_MAC_VER_11:
6754         case RTL_GIGA_MAC_VER_12:
6755         case RTL_GIGA_MAC_VER_17:
6756                 pci_clear_master(tp->pci_dev);
6757
6758                 RTL_W8(ChipCmd, CmdRxEnb);
6759                 /* PCI commit */
6760                 RTL_R8(ChipCmd);
6761                 break;
6762         default:
6763                 break;
6764         }
6765 }
6766
6767 static void rtl_shutdown(struct pci_dev *pdev)
6768 {
6769         struct net_device *dev = pci_get_drvdata(pdev);
6770         struct rtl8169_private *tp = netdev_priv(dev);
6771         struct device *d = &pdev->dev;
6772
6773         pm_runtime_get_sync(d);
6774
6775         rtl8169_net_suspend(dev);
6776
6777         /* Restore original MAC address */
6778         rtl_rar_set(tp, dev->perm_addr);
6779
6780         rtl8169_hw_reset(tp);
6781
6782         if (system_state == SYSTEM_POWER_OFF) {
6783                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6784                         rtl_wol_suspend_quirk(tp);
6785                         rtl_wol_shutdown_quirk(tp);
6786                 }
6787
6788                 pci_wake_from_d3(pdev, true);
6789                 pci_set_power_state(pdev, PCI_D3hot);
6790         }
6791
6792         pm_runtime_put_noidle(d);
6793 }
6794
6795 static void rtl_remove_one(struct pci_dev *pdev)
6796 {
6797         struct net_device *dev = pci_get_drvdata(pdev);
6798         struct rtl8169_private *tp = netdev_priv(dev);
6799
6800         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6801             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6802             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6803                 rtl8168_driver_stop(tp);
6804         }
6805
6806         netif_napi_del(&tp->napi);
6807
6808         unregister_netdev(dev);
6809
6810         rtl_release_firmware(tp);
6811
6812         if (pci_dev_run_wake(pdev))
6813                 pm_runtime_get_noresume(&pdev->dev);
6814
6815         /* restore original MAC address */
6816         rtl_rar_set(tp, dev->perm_addr);
6817
6818         rtl_disable_msi(pdev, tp);
6819         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6820 }
6821
6822 static const struct net_device_ops rtl_netdev_ops = {
6823         .ndo_open               = rtl_open,
6824         .ndo_stop               = rtl8169_close,
6825         .ndo_get_stats64        = rtl8169_get_stats64,
6826         .ndo_start_xmit         = rtl8169_start_xmit,
6827         .ndo_tx_timeout         = rtl8169_tx_timeout,
6828         .ndo_validate_addr      = eth_validate_addr,
6829         .ndo_change_mtu         = rtl8169_change_mtu,
6830         .ndo_fix_features       = rtl8169_fix_features,
6831         .ndo_set_features       = rtl8169_set_features,
6832         .ndo_set_mac_address    = rtl_set_mac_address,
6833         .ndo_do_ioctl           = rtl8169_ioctl,
6834         .ndo_set_rx_mode        = rtl_set_rx_mode,
6835 #ifdef CONFIG_NET_POLL_CONTROLLER
6836         .ndo_poll_controller    = rtl8169_netpoll,
6837 #endif
6838
6839 };
6840
6841 static const struct rtl_cfg_info {
6842         void (*hw_start)(struct net_device *);
6843         unsigned int region;
6844         unsigned int align;
6845         u16 event_slow;
6846         unsigned features;
6847         u8 default_ver;
6848 } rtl_cfg_infos [] = {
6849         [RTL_CFG_0] = {
6850                 .hw_start       = rtl_hw_start_8169,
6851                 .region         = 1,
6852                 .align          = 0,
6853                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6854                 .features       = RTL_FEATURE_GMII,
6855                 .default_ver    = RTL_GIGA_MAC_VER_01,
6856         },
6857         [RTL_CFG_1] = {
6858                 .hw_start       = rtl_hw_start_8168,
6859                 .region         = 2,
6860                 .align          = 8,
6861                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6862                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6863                 .default_ver    = RTL_GIGA_MAC_VER_11,
6864         },
6865         [RTL_CFG_2] = {
6866                 .hw_start       = rtl_hw_start_8101,
6867                 .region         = 2,
6868                 .align          = 8,
6869                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6870                                   PCSTimeout,
6871                 .features       = RTL_FEATURE_MSI,
6872                 .default_ver    = RTL_GIGA_MAC_VER_13,
6873         }
6874 };
6875
6876 /* Cfg9346_Unlock assumed. */
6877 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6878                             const struct rtl_cfg_info *cfg)
6879 {
6880         void __iomem *ioaddr = tp->mmio_addr;
6881         unsigned msi = 0;
6882         u8 cfg2;
6883
6884         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6885         if (cfg->features & RTL_FEATURE_MSI) {
6886                 if (pci_enable_msi(tp->pci_dev)) {
6887                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6888                 } else {
6889                         cfg2 |= MSIEnable;
6890                         msi = RTL_FEATURE_MSI;
6891                 }
6892         }
6893         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6894                 RTL_W8(Config2, cfg2);
6895         return msi;
6896 }
6897
6898 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6899 {
6900         void __iomem *ioaddr = tp->mmio_addr;
6901
6902         return RTL_R8(MCU) & LINK_LIST_RDY;
6903 }
6904
6905 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6906 {
6907         void __iomem *ioaddr = tp->mmio_addr;
6908
6909         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6910 }
6911
6912 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6913 {
6914         void __iomem *ioaddr = tp->mmio_addr;
6915         u32 data;
6916
6917         tp->ocp_base = OCP_STD_PHY_BASE;
6918
6919         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6920
6921         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6922                 return;
6923
6924         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6925                 return;
6926
6927         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6928         msleep(1);
6929         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6930
6931         data = r8168_mac_ocp_read(tp, 0xe8de);
6932         data &= ~(1 << 14);
6933         r8168_mac_ocp_write(tp, 0xe8de, data);
6934
6935         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6936                 return;
6937
6938         data = r8168_mac_ocp_read(tp, 0xe8de);
6939         data |= (1 << 15);
6940         r8168_mac_ocp_write(tp, 0xe8de, data);
6941
6942         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6943                 return;
6944 }
6945
6946 static void rtl_hw_initialize(struct rtl8169_private *tp)
6947 {
6948         switch (tp->mac_version) {
6949         case RTL_GIGA_MAC_VER_40:
6950         case RTL_GIGA_MAC_VER_41:
6951         case RTL_GIGA_MAC_VER_42:
6952         case RTL_GIGA_MAC_VER_43:
6953         case RTL_GIGA_MAC_VER_44:
6954                 rtl_hw_init_8168g(tp);
6955                 break;
6956
6957         default:
6958                 break;
6959         }
6960 }
6961
6962 static int
6963 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6964 {
6965         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6966         const unsigned int region = cfg->region;
6967         struct rtl8169_private *tp;
6968         struct mii_if_info *mii;
6969         struct net_device *dev;
6970         void __iomem *ioaddr;
6971         int chipset, i;
6972         int rc;
6973
6974         if (netif_msg_drv(&debug)) {
6975                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6976                        MODULENAME, RTL8169_VERSION);
6977         }
6978
6979         dev = alloc_etherdev(sizeof (*tp));
6980         if (!dev) {
6981                 rc = -ENOMEM;
6982                 goto out;
6983         }
6984
6985         SET_NETDEV_DEV(dev, &pdev->dev);
6986         dev->netdev_ops = &rtl_netdev_ops;
6987         tp = netdev_priv(dev);
6988         tp->dev = dev;
6989         tp->pci_dev = pdev;
6990         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6991
6992         mii = &tp->mii;
6993         mii->dev = dev;
6994         mii->mdio_read = rtl_mdio_read;
6995         mii->mdio_write = rtl_mdio_write;
6996         mii->phy_id_mask = 0x1f;
6997         mii->reg_num_mask = 0x1f;
6998         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6999
7000         /* disable ASPM completely as that cause random device stop working
7001          * problems as well as full system hangs for some PCIe devices users */
7002         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7003                                      PCIE_LINK_STATE_CLKPM);
7004
7005         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7006         rc = pci_enable_device(pdev);
7007         if (rc < 0) {
7008                 netif_err(tp, probe, dev, "enable failure\n");
7009                 goto err_out_free_dev_1;
7010         }
7011
7012         if (pci_set_mwi(pdev) < 0)
7013                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7014
7015         /* make sure PCI base addr 1 is MMIO */
7016         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7017                 netif_err(tp, probe, dev,
7018                           "region #%d not an MMIO resource, aborting\n",
7019                           region);
7020                 rc = -ENODEV;
7021                 goto err_out_mwi_2;
7022         }
7023
7024         /* check for weird/broken PCI region reporting */
7025         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7026                 netif_err(tp, probe, dev,
7027                           "Invalid PCI region size(s), aborting\n");
7028                 rc = -ENODEV;
7029                 goto err_out_mwi_2;
7030         }
7031
7032         rc = pci_request_regions(pdev, MODULENAME);
7033         if (rc < 0) {
7034                 netif_err(tp, probe, dev, "could not request regions\n");
7035                 goto err_out_mwi_2;
7036         }
7037
7038         tp->cp_cmd = RxChkSum;
7039
7040         if ((sizeof(dma_addr_t) > 4) &&
7041             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7042                 tp->cp_cmd |= PCIDAC;
7043                 dev->features |= NETIF_F_HIGHDMA;
7044         } else {
7045                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7046                 if (rc < 0) {
7047                         netif_err(tp, probe, dev, "DMA configuration failed\n");
7048                         goto err_out_free_res_3;
7049                 }
7050         }
7051
7052         /* ioremap MMIO region */
7053         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7054         if (!ioaddr) {
7055                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7056                 rc = -EIO;
7057                 goto err_out_free_res_3;
7058         }
7059         tp->mmio_addr = ioaddr;
7060
7061         if (!pci_is_pcie(pdev))
7062                 netif_info(tp, probe, dev, "not PCI Express\n");
7063
7064         /* Identify chip attached to board */
7065         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7066
7067         rtl_init_rxcfg(tp);
7068
7069         rtl_irq_disable(tp);
7070
7071         rtl_hw_initialize(tp);
7072
7073         rtl_hw_reset(tp);
7074
7075         rtl_ack_events(tp, 0xffff);
7076
7077         pci_set_master(pdev);
7078
7079         /*
7080          * Pretend we are using VLANs; This bypasses a nasty bug where
7081          * Interrupts stop flowing on high load on 8110SCd controllers.
7082          */
7083         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7084                 tp->cp_cmd |= RxVlan;
7085
7086         rtl_init_mdio_ops(tp);
7087         rtl_init_pll_power_ops(tp);
7088         rtl_init_jumbo_ops(tp);
7089         rtl_init_csi_ops(tp);
7090
7091         rtl8169_print_mac_version(tp);
7092
7093         chipset = tp->mac_version;
7094         tp->txd_version = rtl_chip_infos[chipset].txd_version;
7095
7096         RTL_W8(Cfg9346, Cfg9346_Unlock);
7097         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7098         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
7099         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7100                 tp->features |= RTL_FEATURE_WOL;
7101         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7102                 tp->features |= RTL_FEATURE_WOL;
7103         tp->features |= rtl_try_msi(tp, cfg);
7104         RTL_W8(Cfg9346, Cfg9346_Lock);
7105
7106         if (rtl_tbi_enabled(tp)) {
7107                 tp->set_speed = rtl8169_set_speed_tbi;
7108                 tp->get_settings = rtl8169_gset_tbi;
7109                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7110                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7111                 tp->link_ok = rtl8169_tbi_link_ok;
7112                 tp->do_ioctl = rtl_tbi_ioctl;
7113         } else {
7114                 tp->set_speed = rtl8169_set_speed_xmii;
7115                 tp->get_settings = rtl8169_gset_xmii;
7116                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7117                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7118                 tp->link_ok = rtl8169_xmii_link_ok;
7119                 tp->do_ioctl = rtl_xmii_ioctl;
7120         }
7121
7122         mutex_init(&tp->wk.mutex);
7123         u64_stats_init(&tp->rx_stats.syncp);
7124         u64_stats_init(&tp->tx_stats.syncp);
7125
7126         /* Get MAC address */
7127         for (i = 0; i < ETH_ALEN; i++)
7128                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7129
7130         dev->ethtool_ops = &rtl8169_ethtool_ops;
7131         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7132
7133         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7134
7135         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7136          * properly for all devices */
7137         dev->features |= NETIF_F_RXCSUM |
7138                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7139
7140         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7141                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7142                 NETIF_F_HW_VLAN_CTAG_RX;
7143         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7144                 NETIF_F_HIGHDMA;
7145
7146         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7147                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7148                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7149
7150         if (tp->txd_version == RTL_TD_0)
7151                 tp->tso_csum = rtl8169_tso_csum_v1;
7152         else if (tp->txd_version == RTL_TD_1)
7153                 tp->tso_csum = rtl8169_tso_csum_v2;
7154         else
7155                 WARN_ON_ONCE(1);
7156
7157         dev->hw_features |= NETIF_F_RXALL;
7158         dev->hw_features |= NETIF_F_RXFCS;
7159
7160         tp->hw_start = cfg->hw_start;
7161         tp->event_slow = cfg->event_slow;
7162
7163         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7164                 ~(RxBOVF | RxFOVF) : ~0;
7165
7166         init_timer(&tp->timer);
7167         tp->timer.data = (unsigned long) dev;
7168         tp->timer.function = rtl8169_phy_timer;
7169
7170         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7171
7172         rc = register_netdev(dev);
7173         if (rc < 0)
7174                 goto err_out_msi_4;
7175
7176         pci_set_drvdata(pdev, dev);
7177
7178         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7179                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7180                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7181         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7182                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7183                            "tx checksumming: %s]\n",
7184                            rtl_chip_infos[chipset].jumbo_max,
7185                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7186         }
7187
7188         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7189             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7190             tp->mac_version == RTL_GIGA_MAC_VER_31) {
7191                 rtl8168_driver_start(tp);
7192         }
7193
7194         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7195
7196         if (pci_dev_run_wake(pdev))
7197                 pm_runtime_put_noidle(&pdev->dev);
7198
7199         netif_carrier_off(dev);
7200
7201 out:
7202         return rc;
7203
7204 err_out_msi_4:
7205         netif_napi_del(&tp->napi);
7206         rtl_disable_msi(pdev, tp);
7207         iounmap(ioaddr);
7208 err_out_free_res_3:
7209         pci_release_regions(pdev);
7210 err_out_mwi_2:
7211         pci_clear_mwi(pdev);
7212         pci_disable_device(pdev);
7213 err_out_free_dev_1:
7214         free_netdev(dev);
7215         goto out;
7216 }
7217
7218 static struct pci_driver rtl8169_pci_driver = {
7219         .name           = MODULENAME,
7220         .id_table       = rtl8169_pci_tbl,
7221         .probe          = rtl_init_one,
7222         .remove         = rtl_remove_one,
7223         .shutdown       = rtl_shutdown,
7224         .driver.pm      = RTL8169_PM_OPS,
7225 };
7226
7227 module_pci_driver(rtl8169_pci_driver);