drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55
  56 #ifdef RTL8169_DEBUG
  57 #define assert(expr) \
  58         if (!(expr)) {                                  \
  59                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  60                 #expr,__FILE__,__func__,__LINE__);              \
  61         }
  62 #define dprintk(fmt, args...) \
  63         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  64 #else
  65 #define assert(expr) do {} while (0)
  66 #define dprintk(fmt, args...)   do {} while (0)
  67 #endif /* RTL8169_DEBUG */
  68
  69 #define R8169_MSG_DEFAULT \
  70         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  71
  72 #define TX_SLOTS_AVAIL(tp) \
  73         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  74
  75 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  76 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  77         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  78
  79 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  80    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  81 static const int multicast_filter_limit = 32;
  82
  83 #define MAX_READ_REQUEST_SHIFT  12
  84 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  85 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  86
  87 #define R8169_REGS_SIZE         256
  88 #define R8169_NAPI_WEIGHT       64
  89 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  90 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  91 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  92 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  93
  94 #define RTL8169_TX_TIMEOUT      (6*HZ)
  95 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  96
  97 /* write/read MMIO register */
  98 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  99 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 100 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 101 #define RTL_R8(reg)             readb (ioaddr + (reg))
 102 #define RTL_R16(reg)            readw (ioaddr + (reg))
 103 #define RTL_R32(reg)            readl (ioaddr + (reg))
 104
 105 enum mac_version {
 106         RTL_GIGA_MAC_VER_01 = 0,
 107         RTL_GIGA_MAC_VER_02,
 108         RTL_GIGA_MAC_VER_03,
 109         RTL_GIGA_MAC_VER_04,
 110         RTL_GIGA_MAC_VER_05,
 111         RTL_GIGA_MAC_VER_06,
 112         RTL_GIGA_MAC_VER_07,
 113         RTL_GIGA_MAC_VER_08,
 114         RTL_GIGA_MAC_VER_09,
 115         RTL_GIGA_MAC_VER_10,
 116         RTL_GIGA_MAC_VER_11,
 117         RTL_GIGA_MAC_VER_12,
 118         RTL_GIGA_MAC_VER_13,
 119         RTL_GIGA_MAC_VER_14,
 120         RTL_GIGA_MAC_VER_15,
 121         RTL_GIGA_MAC_VER_16,
 122         RTL_GIGA_MAC_VER_17,
 123         RTL_GIGA_MAC_VER_18,
 124         RTL_GIGA_MAC_VER_19,
 125         RTL_GIGA_MAC_VER_20,
 126         RTL_GIGA_MAC_VER_21,
 127         RTL_GIGA_MAC_VER_22,
 128         RTL_GIGA_MAC_VER_23,
 129         RTL_GIGA_MAC_VER_24,
 130         RTL_GIGA_MAC_VER_25,
 131         RTL_GIGA_MAC_VER_26,
 132         RTL_GIGA_MAC_VER_27,
 133         RTL_GIGA_MAC_VER_28,
 134         RTL_GIGA_MAC_VER_29,
 135         RTL_GIGA_MAC_VER_30,
 136         RTL_GIGA_MAC_VER_31,
 137         RTL_GIGA_MAC_VER_32,
 138         RTL_GIGA_MAC_VER_33,
 139         RTL_GIGA_MAC_VER_34,
 140         RTL_GIGA_MAC_VER_35,
 141         RTL_GIGA_MAC_VER_36,
 142         RTL_GIGA_MAC_VER_37,
 143         RTL_GIGA_MAC_VER_38,
 144         RTL_GIGA_MAC_VER_39,
 145         RTL_GIGA_MAC_VER_40,
 146         RTL_GIGA_MAC_VER_41,
 147         RTL_GIGA_MAC_VER_42,
 148         RTL_GIGA_MAC_VER_43,
 149         RTL_GIGA_MAC_VER_44,
 150         RTL_GIGA_MAC_NONE   = 0xff,
 151 };
 152
 153 enum rtl_tx_desc_version {
 154         RTL_TD_0        = 0,
 155         RTL_TD_1        = 1,
 156 };
 157
 158 #define JUMBO_1K        ETH_DATA_LEN
 159 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 160 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 161 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 162 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 163
 164 #define _R(NAME,TD,FW,SZ,B) {   \
 165         .name = NAME,           \
 166         .txd_version = TD,      \
 167         .fw_name = FW,          \
 168         .jumbo_max = SZ,        \
 169         .jumbo_tx_csum = B      \
 170 }
 171
 172 static const struct {
 173         const char *name;
 174         enum rtl_tx_desc_version txd_version;
 175         const char *fw_name;
 176         u16 jumbo_max;
 177         bool jumbo_tx_csum;
 178 } rtl_chip_infos[] = {
 179         /* PCI devices. */
 180         [RTL_GIGA_MAC_VER_01] =
 181                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 182         [RTL_GIGA_MAC_VER_02] =
 183                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 184         [RTL_GIGA_MAC_VER_03] =
 185                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 186         [RTL_GIGA_MAC_VER_04] =
 187                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 188         [RTL_GIGA_MAC_VER_05] =
 189                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 190         [RTL_GIGA_MAC_VER_06] =
 191                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 192         /* PCI-E devices. */
 193         [RTL_GIGA_MAC_VER_07] =
 194                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 195         [RTL_GIGA_MAC_VER_08] =
 196                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_09] =
 198                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 199         [RTL_GIGA_MAC_VER_10] =
 200                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_11] =
 202                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 203         [RTL_GIGA_MAC_VER_12] =
 204                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 205         [RTL_GIGA_MAC_VER_13] =
 206                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_14] =
 208                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 209         [RTL_GIGA_MAC_VER_15] =
 210                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 211         [RTL_GIGA_MAC_VER_16] =
 212                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 213         [RTL_GIGA_MAC_VER_17] =
 214                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 215         [RTL_GIGA_MAC_VER_18] =
 216                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_19] =
 218                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_20] =
 220                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 221         [RTL_GIGA_MAC_VER_21] =
 222                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 223         [RTL_GIGA_MAC_VER_22] =
 224                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 225         [RTL_GIGA_MAC_VER_23] =
 226                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 227         [RTL_GIGA_MAC_VER_24] =
 228                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 229         [RTL_GIGA_MAC_VER_25] =
 230                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 231                                                         JUMBO_9K, false),
 232         [RTL_GIGA_MAC_VER_26] =
 233                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 234                                                         JUMBO_9K, false),
 235         [RTL_GIGA_MAC_VER_27] =
 236                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_28] =
 238                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 239         [RTL_GIGA_MAC_VER_29] =
 240                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 241                                                         JUMBO_1K, true),
 242         [RTL_GIGA_MAC_VER_30] =
 243                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 244                                                         JUMBO_1K, true),
 245         [RTL_GIGA_MAC_VER_31] =
 246                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_32] =
 248                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 249                                                         JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_33] =
 251                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 252                                                         JUMBO_9K, false),
 253         [RTL_GIGA_MAC_VER_34] =
 254                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 255                                                         JUMBO_9K, false),
 256         [RTL_GIGA_MAC_VER_35] =
 257                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 258                                                         JUMBO_9K, false),
 259         [RTL_GIGA_MAC_VER_36] =
 260                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 261                                                         JUMBO_9K, false),
 262         [RTL_GIGA_MAC_VER_37] =
 263                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 264                                                         JUMBO_1K, true),
 265         [RTL_GIGA_MAC_VER_38] =
 266                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 267                                                         JUMBO_9K, false),
 268         [RTL_GIGA_MAC_VER_39] =
 269                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 270                                                         JUMBO_1K, true),
 271         [RTL_GIGA_MAC_VER_40] =
 272                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 273                                                         JUMBO_9K, false),
 274         [RTL_GIGA_MAC_VER_41] =
 275                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 276         [RTL_GIGA_MAC_VER_42] =
 277                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_43] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_44] =
 283                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 284                                                         JUMBO_9K, false),
 285 };
 286 #undef _R
 287
 288 enum cfg_version {
 289         RTL_CFG_0 = 0x00,
 290         RTL_CFG_1,
 291         RTL_CFG_2
 292 };
 293
 294 static const struct pci_device_id rtl8169_pci_tbl[] = {
 295         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 296         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 297         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 298         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 299         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 300         { PCI_VENDOR_ID_DLINK,                  0x4300,
 301                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 302         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 303         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 304         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 305         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 306         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 307                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 308         { 0x0001,                               0x8168,
 309                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 310         {0,},
 311 };
 312
 313 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 314
 315 static int rx_buf_sz = 16383;
 316 static int use_dac;
 317 static struct {
 318         u32 msg_enable;
 319 } debug = { -1 };
 320
 321 enum rtl_registers {
 322         MAC0            = 0,    /* Ethernet hardware address. */
 323         MAC4            = 4,
 324         MAR0            = 8,    /* Multicast filter. */
 325         CounterAddrLow          = 0x10,
 326         CounterAddrHigh         = 0x14,
 327         TxDescStartAddrLow      = 0x20,
 328         TxDescStartAddrHigh     = 0x24,
 329         TxHDescStartAddrLow     = 0x28,
 330         TxHDescStartAddrHigh    = 0x2c,
 331         FLASH           = 0x30,
 332         ERSR            = 0x36,
 333         ChipCmd         = 0x37,
 334         TxPoll          = 0x38,
 335         IntrMask        = 0x3c,
 336         IntrStatus      = 0x3e,
 337
 338         TxConfig        = 0x40,
 339 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 340 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 341
 342         RxConfig        = 0x44,
 343 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 344 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 345 #define RXCFG_FIFO_SHIFT                13
 346                                         /* No threshold before first PCI xfer */
 347 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 348 #define RX_EARLY_OFF                    (1 << 11)
 349 #define RXCFG_DMA_SHIFT                 8
 350                                         /* Unlimited maximum PCI burst. */
 351 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 352
 353         RxMissed        = 0x4c,
 354         Cfg9346         = 0x50,
 355         Config0         = 0x51,
 356         Config1         = 0x52,
 357         Config2         = 0x53,
 358 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 359
 360         Config3         = 0x54,
 361         Config4         = 0x55,
 362         Config5         = 0x56,
 363         MultiIntr       = 0x5c,
 364         PHYAR           = 0x60,
 365         PHYstatus       = 0x6c,
 366         RxMaxSize       = 0xda,
 367         CPlusCmd        = 0xe0,
 368         IntrMitigate    = 0xe2,
 369         RxDescAddrLow   = 0xe4,
 370         RxDescAddrHigh  = 0xe8,
 371         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 372
 373 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 374
 375         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 376
 377 #define TxPacketMax     (8064 >> 7)
 378 #define EarlySize       0x27
 379
 380         FuncEvent       = 0xf0,
 381         FuncEventMask   = 0xf4,
 382         FuncPresetState = 0xf8,
 383         FuncForceEvent  = 0xfc,
 384 };
 385
 386 enum rtl8110_registers {
 387         TBICSR                  = 0x64,
 388         TBI_ANAR                = 0x68,
 389         TBI_LPAR                = 0x6a,
 390 };
 391
 392 enum rtl8168_8101_registers {
 393         CSIDR                   = 0x64,
 394         CSIAR                   = 0x68,
 395 #define CSIAR_FLAG                      0x80000000
 396 #define CSIAR_WRITE_CMD                 0x80000000
 397 #define CSIAR_BYTE_ENABLE               0x0f
 398 #define CSIAR_BYTE_ENABLE_SHIFT         12
 399 #define CSIAR_ADDR_MASK                 0x0fff
 400 #define CSIAR_FUNC_CARD                 0x00000000
 401 #define CSIAR_FUNC_SDIO                 0x00010000
 402 #define CSIAR_FUNC_NIC                  0x00020000
 403 #define CSIAR_FUNC_NIC2                 0x00010000
 404         PMCH                    = 0x6f,
 405         EPHYAR                  = 0x80,
 406 #define EPHYAR_FLAG                     0x80000000
 407 #define EPHYAR_WRITE_CMD                0x80000000
 408 #define EPHYAR_REG_MASK                 0x1f
 409 #define EPHYAR_REG_SHIFT                16
 410 #define EPHYAR_DATA_MASK                0xffff
 411         DLLPR                   = 0xd0,
 412 #define PFM_EN                          (1 << 6)
 413         DBG_REG                 = 0xd1,
 414 #define FIX_NAK_1                       (1 << 4)
 415 #define FIX_NAK_2                       (1 << 3)
 416         TWSI                    = 0xd2,
 417         MCU                     = 0xd3,
 418 #define NOW_IS_OOB                      (1 << 7)
 419 #define TX_EMPTY                        (1 << 5)
 420 #define RX_EMPTY                        (1 << 4)
 421 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 422 #define EN_NDP                          (1 << 3)
 423 #define EN_OOB_RESET                    (1 << 2)
 424 #define LINK_LIST_RDY                   (1 << 1)
 425         EFUSEAR                 = 0xdc,
 426 #define EFUSEAR_FLAG                    0x80000000
 427 #define EFUSEAR_WRITE_CMD               0x80000000
 428 #define EFUSEAR_READ_CMD                0x00000000
 429 #define EFUSEAR_REG_MASK                0x03ff
 430 #define EFUSEAR_REG_SHIFT               8
 431 #define EFUSEAR_DATA_MASK               0xff
 432 };
 433
 434 enum rtl8168_registers {
 435         LED_FREQ                = 0x1a,
 436         EEE_LED                 = 0x1b,
 437         ERIDR                   = 0x70,
 438         ERIAR                   = 0x74,
 439 #define ERIAR_FLAG                      0x80000000
 440 #define ERIAR_WRITE_CMD                 0x80000000
 441 #define ERIAR_READ_CMD                  0x00000000
 442 #define ERIAR_ADDR_BYTE_ALIGN           4
 443 #define ERIAR_TYPE_SHIFT                16
 444 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 445 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 446 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 447 #define ERIAR_MASK_SHIFT                12
 448 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 449 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 450 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 451 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 452         EPHY_RXER_NUM           = 0x7c,
 453         OCPDR                   = 0xb0, /* OCP GPHY access */
 454 #define OCPDR_WRITE_CMD                 0x80000000
 455 #define OCPDR_READ_CMD                  0x00000000
 456 #define OCPDR_REG_MASK                  0x7f
 457 #define OCPDR_GPHY_REG_SHIFT            16
 458 #define OCPDR_DATA_MASK                 0xffff
 459         OCPAR                   = 0xb4,
 460 #define OCPAR_FLAG                      0x80000000
 461 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 462 #define OCPAR_GPHY_READ_CMD             0x0000f060
 463         GPHY_OCP                = 0xb8,
 464         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 465         MISC                    = 0xf0, /* 8168e only. */
 466 #define TXPLA_RST                       (1 << 29)
 467 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 468 #define PWM_EN                          (1 << 22)
 469 #define RXDV_GATED_EN                   (1 << 19)
 470 #define EARLY_TALLY_EN                  (1 << 16)
 471 };
 472
 473 enum rtl_register_content {
 474         /* InterruptStatusBits */
 475         SYSErr          = 0x8000,
 476         PCSTimeout      = 0x4000,
 477         SWInt           = 0x0100,
 478         TxDescUnavail   = 0x0080,
 479         RxFIFOOver      = 0x0040,
 480         LinkChg         = 0x0020,
 481         RxOverflow      = 0x0010,
 482         TxErr           = 0x0008,
 483         TxOK            = 0x0004,
 484         RxErr           = 0x0002,
 485         RxOK            = 0x0001,
 486
 487         /* RxStatusDesc */
 488         RxBOVF  = (1 << 24),
 489         RxFOVF  = (1 << 23),
 490         RxRWT   = (1 << 22),
 491         RxRES   = (1 << 21),
 492         RxRUNT  = (1 << 20),
 493         RxCRC   = (1 << 19),
 494
 495         /* ChipCmdBits */
 496         StopReq         = 0x80,
 497         CmdReset        = 0x10,
 498         CmdRxEnb        = 0x08,
 499         CmdTxEnb        = 0x04,
 500         RxBufEmpty      = 0x01,
 501
 502         /* TXPoll register p.5 */
 503         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 504         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 505         FSWInt          = 0x01,         /* Forced software interrupt */
 506
 507         /* Cfg9346Bits */
 508         Cfg9346_Lock    = 0x00,
 509         Cfg9346_Unlock  = 0xc0,
 510
 511         /* rx_mode_bits */
 512         AcceptErr       = 0x20,
 513         AcceptRunt      = 0x10,
 514         AcceptBroadcast = 0x08,
 515         AcceptMulticast = 0x04,
 516         AcceptMyPhys    = 0x02,
 517         AcceptAllPhys   = 0x01,
 518 #define RX_CONFIG_ACCEPT_MASK           0x3f
 519
 520         /* TxConfigBits */
 521         TxInterFrameGapShift = 24,
 522         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 523
 524         /* Config1 register p.24 */
 525         LEDS1           = (1 << 7),
 526         LEDS0           = (1 << 6),
 527         Speed_down      = (1 << 4),
 528         MEMMAP          = (1 << 3),
 529         IOMAP           = (1 << 2),
 530         VPD             = (1 << 1),
 531         PMEnable        = (1 << 0),     /* Power Management Enable */
 532
 533         /* Config2 register p. 25 */
 534         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 535         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 536         PCI_Clock_66MHz = 0x01,
 537         PCI_Clock_33MHz = 0x00,
 538
 539         /* Config3 register p.25 */
 540         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 541         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 542         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 543         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 544         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 545
 546         /* Config4 register */
 547         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 548
 549         /* Config5 register p.27 */
 550         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 551         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 552         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 553         Spi_en          = (1 << 3),
 554         LanWake         = (1 << 1),     /* LanWake enable/disable */
 555         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 556         ASPM_en         = (1 << 0),     /* ASPM enable */
 557
 558         /* TBICSR p.28 */
 559         TBIReset        = 0x80000000,
 560         TBILoopback     = 0x40000000,
 561         TBINwEnable     = 0x20000000,
 562         TBINwRestart    = 0x10000000,
 563         TBILinkOk       = 0x02000000,
 564         TBINwComplete   = 0x01000000,
 565
 566         /* CPlusCmd p.31 */
 567         EnableBist      = (1 << 15),    // 8168 8101
 568         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 569         Normal_mode     = (1 << 13),    // unused
 570         Force_half_dup  = (1 << 12),    // 8168 8101
 571         Force_rxflow_en = (1 << 11),    // 8168 8101
 572         Force_txflow_en = (1 << 10),    // 8168 8101
 573         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 574         ASF             = (1 << 8),     // 8168 8101
 575         PktCntrDisable  = (1 << 7),     // 8168 8101
 576         Mac_dbgo_sel    = 0x001c,       // 8168
 577         RxVlan          = (1 << 6),
 578         RxChkSum        = (1 << 5),
 579         PCIDAC          = (1 << 4),
 580         PCIMulRW        = (1 << 3),
 581         INTT_0          = 0x0000,       // 8168
 582         INTT_1          = 0x0001,       // 8168
 583         INTT_2          = 0x0002,       // 8168
 584         INTT_3          = 0x0003,       // 8168
 585
 586         /* rtl8169_PHYstatus */
 587         TBI_Enable      = 0x80,
 588         TxFlowCtrl      = 0x40,
 589         RxFlowCtrl      = 0x20,
 590         _1000bpsF       = 0x10,
 591         _100bps         = 0x08,
 592         _10bps          = 0x04,
 593         LinkStatus      = 0x02,
 594         FullDup         = 0x01,
 595
 596         /* _TBICSRBit */
 597         TBILinkOK       = 0x02000000,
 598
 599         /* DumpCounterCommand */
 600         CounterDump     = 0x8,
 601 };
 602
 603 enum rtl_desc_bit {
 604         /* First doubleword. */
 605         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 606         RingEnd         = (1 << 30), /* End of descriptor ring */
 607         FirstFrag       = (1 << 29), /* First segment of a packet */
 608         LastFrag        = (1 << 28), /* Final segment of a packet */
 609 };
 610
 611 /* Generic case. */
 612 enum rtl_tx_desc_bit {
 613         /* First doubleword. */
 614         TD_LSO          = (1 << 27),            /* Large Send Offload */
 615 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 616
 617         /* Second doubleword. */
 618         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 619 };
 620
 621 /* 8169, 8168b and 810x except 8102e. */
 622 enum rtl_tx_desc_bit_0 {
 623         /* First doubleword. */
 624 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 625         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 626         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 627         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 628 };
 629
 630 /* 8102e, 8168c and beyond. */
 631 enum rtl_tx_desc_bit_1 {
 632         /* First doubleword. */
 633         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 634         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 635 #define GTTCPHO_SHIFT                   18
 636 #define GTTCPHO_MAX                     0x7fU
 637
 638         /* Second doubleword. */
 639 #define TCPHO_SHIFT                     18
 640 #define TCPHO_MAX                       0x3ffU
 641 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 642         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 643         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 644         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 645         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 646 };
 647
 648 enum rtl_rx_desc_bit {
 649         /* Rx private */
 650         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 651         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 652
 653 #define RxProtoUDP      (PID1)
 654 #define RxProtoTCP      (PID0)
 655 #define RxProtoIP       (PID1 | PID0)
 656 #define RxProtoMask     RxProtoIP
 657
 658         IPFail          = (1 << 16), /* IP checksum failed */
 659         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 660         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 661         RxVlanTag       = (1 << 16), /* VLAN tag available */
 662 };
 663
 664 #define RsvdMask        0x3fffc000
 665
 666 struct TxDesc {
 667         __le32 opts1;
 668         __le32 opts2;
 669         __le64 addr;
 670 };
 671
 672 struct RxDesc {
 673         __le32 opts1;
 674         __le32 opts2;
 675         __le64 addr;
 676 };
 677
 678 struct ring_info {
 679         struct sk_buff  *skb;
 680         u32             len;
 681         u8              __pad[sizeof(void *) - sizeof(u32)];
 682 };
 683
 684 enum features {
 685         RTL_FEATURE_WOL         = (1 << 0),
 686         RTL_FEATURE_MSI         = (1 << 1),
 687         RTL_FEATURE_GMII        = (1 << 2),
 688 };
 689
 690 struct rtl8169_counters {
 691         __le64  tx_packets;
 692         __le64  rx_packets;
 693         __le64  tx_errors;
 694         __le32  rx_errors;
 695         __le16  rx_missed;
 696         __le16  align_errors;
 697         __le32  tx_one_collision;
 698         __le32  tx_multi_collision;
 699         __le64  rx_unicast;
 700         __le64  rx_broadcast;
 701         __le32  rx_multicast;
 702         __le16  tx_aborted;
 703         __le16  tx_underun;
 704 };
 705
 706 enum rtl_flag {
 707         RTL_FLAG_TASK_ENABLED,
 708         RTL_FLAG_TASK_SLOW_PENDING,
 709         RTL_FLAG_TASK_RESET_PENDING,
 710         RTL_FLAG_TASK_PHY_PENDING,
 711         RTL_FLAG_MAX
 712 };
 713
 714 struct rtl8169_stats {
 715         u64                     packets;
 716         u64                     bytes;
 717         struct u64_stats_sync   syncp;
 718 };
 719
 720 struct rtl8169_private {
 721         void __iomem *mmio_addr;        /* memory map physical address */
 722         struct pci_dev *pci_dev;
 723         struct net_device *dev;
 724         struct napi_struct napi;
 725         u32 msg_enable;
 726         u16 txd_version;
 727         u16 mac_version;
 728         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 729         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 730         u32 dirty_tx;
 731         struct rtl8169_stats rx_stats;
 732         struct rtl8169_stats tx_stats;
 733         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 734         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 735         dma_addr_t TxPhyAddr;
 736         dma_addr_t RxPhyAddr;
 737         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 738         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 739         struct timer_list timer;
 740         u16 cp_cmd;
 741
 742         u16 event_slow;
 743
 744         struct mdio_ops {
 745                 void (*write)(struct rtl8169_private *, int, int);
 746                 int (*read)(struct rtl8169_private *, int);
 747         } mdio_ops;
 748
 749         struct pll_power_ops {
 750                 void (*down)(struct rtl8169_private *);
 751                 void (*up)(struct rtl8169_private *);
 752         } pll_power_ops;
 753
 754         struct jumbo_ops {
 755                 void (*enable)(struct rtl8169_private *);
 756                 void (*disable)(struct rtl8169_private *);
 757         } jumbo_ops;
 758
 759         struct csi_ops {
 760                 void (*write)(struct rtl8169_private *, int, int);
 761                 u32 (*read)(struct rtl8169_private *, int);
 762         } csi_ops;
 763
 764         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 765         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 766         void (*phy_reset_enable)(struct rtl8169_private *tp);
 767         void (*hw_start)(struct net_device *);
 768         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 769         unsigned int (*link_ok)(void __iomem *);
 770         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 771         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 772
 773         struct {
 774                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 775                 struct mutex mutex;
 776                 struct work_struct work;
 777         } wk;
 778
 779         unsigned features;
 780
 781         struct mii_if_info mii;
 782         struct rtl8169_counters counters;
 783         u32 saved_wolopts;
 784         u32 opts1_mask;
 785
 786         struct rtl_fw {
 787                 const struct firmware *fw;
 788
 789 #define RTL_VER_SIZE            32
 790
 791                 char version[RTL_VER_SIZE];
 792
 793                 struct rtl_fw_phy_action {
 794                         __le32 *code;
 795                         size_t size;
 796                 } phy_action;
 797         } *rtl_fw;
 798 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 799
 800         u32 ocp_base;
 801 };
 802
 803 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 804 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 805 module_param(use_dac, int, 0);
 806 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 807 module_param_named(debug, debug.msg_enable, int, 0);
 808 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 809 MODULE_LICENSE("GPL");
 810 MODULE_VERSION(RTL8169_VERSION);
 811 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 812 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 813 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 814 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 815 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 816 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 817 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 818 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 819 MODULE_FIRMWARE(FIRMWARE_8402_1);
 820 MODULE_FIRMWARE(FIRMWARE_8411_1);
 821 MODULE_FIRMWARE(FIRMWARE_8411_2);
 822 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 823 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 824 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 825 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 826
 827 static void rtl_lock_work(struct rtl8169_private *tp)
 828 {
 829         mutex_lock(&tp->wk.mutex);
 830 }
 831
 832 static void rtl_unlock_work(struct rtl8169_private *tp)
 833 {
 834         mutex_unlock(&tp->wk.mutex);
 835 }
 836
 837 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 838 {
 839         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 840                                            PCI_EXP_DEVCTL_READRQ, force);
 841 }
 842
 843 struct rtl_cond {
 844         bool (*check)(struct rtl8169_private *);
 845         const char *msg;
 846 };
 847
 848 static void rtl_udelay(unsigned int d)
 849 {
 850         udelay(d);
 851 }
 852
 853 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 854                           void (*delay)(unsigned int), unsigned int d, int n,
 855                           bool high)
 856 {
 857         int i;
 858
 859         for (i = 0; i < n; i++) {
 860                 delay(d);
 861                 if (c->check(tp) == high)
 862                         return true;
 863         }
 864         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 865                   c->msg, !high, n, d);
 866         return false;
 867 }
 868
 869 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 870                                       const struct rtl_cond *c,
 871                                       unsigned int d, int n)
 872 {
 873         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 874 }
 875
 876 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 877                                      const struct rtl_cond *c,
 878                                      unsigned int d, int n)
 879 {
 880         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 881 }
 882
 883 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 884                                       const struct rtl_cond *c,
 885                                       unsigned int d, int n)
 886 {
 887         return rtl_loop_wait(tp, c, msleep, d, n, true);
 888 }
 889
 890 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 891                                      const struct rtl_cond *c,
 892                                      unsigned int d, int n)
 893 {
 894         return rtl_loop_wait(tp, c, msleep, d, n, false);
 895 }
 896
 897 #define DECLARE_RTL_COND(name)                          \
 898 static bool name ## _check(struct rtl8169_private *);   \
 899                                                         \
 900 static const struct rtl_cond name = {                   \
 901         .check  = name ## _check,                       \
 902         .msg    = #name                                 \
 903 };                                                      \
 904                                                         \
 905 static bool name ## _check(struct rtl8169_private *tp)
 906
 907 DECLARE_RTL_COND(rtl_ocpar_cond)
 908 {
 909         void __iomem *ioaddr = tp->mmio_addr;
 910
 911         return RTL_R32(OCPAR) & OCPAR_FLAG;
 912 }
 913
 914 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 915 {
 916         void __iomem *ioaddr = tp->mmio_addr;
 917
 918         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 919
 920         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
 921                 RTL_R32(OCPDR) : ~0;
 922 }
 923
 924 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 925 {
 926         void __iomem *ioaddr = tp->mmio_addr;
 927
 928         RTL_W32(OCPDR, data);
 929         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 930
 931         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
 932 }
 933
 934 DECLARE_RTL_COND(rtl_eriar_cond)
 935 {
 936         void __iomem *ioaddr = tp->mmio_addr;
 937
 938         return RTL_R32(ERIAR) & ERIAR_FLAG;
 939 }
 940
 941 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 942 {
 943         void __iomem *ioaddr = tp->mmio_addr;
 944
 945         RTL_W8(ERIDR, cmd);
 946         RTL_W32(ERIAR, 0x800010e8);
 947         msleep(2);
 948
 949         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
 950                 return;
 951
 952         ocp_write(tp, 0x1, 0x30, 0x00000001);
 953 }
 954
 955 #define OOB_CMD_RESET           0x00
 956 #define OOB_CMD_DRIVER_START    0x05
 957 #define OOB_CMD_DRIVER_STOP     0x06
 958
 959 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 960 {
 961         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 962 }
 963
 964 DECLARE_RTL_COND(rtl_ocp_read_cond)
 965 {
 966         u16 reg;
 967
 968         reg = rtl8168_get_ocp_reg(tp);
 969
 970         return ocp_read(tp, 0x0f, reg) & 0x00000800;
 971 }
 972
 973 static void rtl8168_driver_start(struct rtl8169_private *tp)
 974 {
 975         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 976
 977         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
 978 }
 979
 980 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 981 {
 982         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 983
 984         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
 985 }
 986
 987 static int r8168dp_check_dash(struct rtl8169_private *tp)
 988 {
 989         u16 reg = rtl8168_get_ocp_reg(tp);
 990
 991         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 992 }
 993
 994 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 995 {
 996         if (reg & 0xffff0001) {
 997                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 998                 return true;
 999         }
1000         return false;
1001 }
1002
1003 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1004 {
1005         void __iomem *ioaddr = tp->mmio_addr;
1006
1007         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1008 }
1009
1010 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1011 {
1012         void __iomem *ioaddr = tp->mmio_addr;
1013
1014         if (rtl_ocp_reg_failure(tp, reg))
1015                 return;
1016
1017         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1018
1019         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1020 }
1021
1022 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1023 {
1024         void __iomem *ioaddr = tp->mmio_addr;
1025
1026         if (rtl_ocp_reg_failure(tp, reg))
1027                 return 0;
1028
1029         RTL_W32(GPHY_OCP, reg << 15);
1030
1031         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1032                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1033 }
1034
1035 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1036 {
1037         void __iomem *ioaddr = tp->mmio_addr;
1038
1039         if (rtl_ocp_reg_failure(tp, reg))
1040                 return;
1041
1042         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1043 }
1044
1045 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1046 {
1047         void __iomem *ioaddr = tp->mmio_addr;
1048
1049         if (rtl_ocp_reg_failure(tp, reg))
1050                 return 0;
1051
1052         RTL_W32(OCPDR, reg << 15);
1053
1054         return RTL_R32(OCPDR);
1055 }
1056
1057 #define OCP_STD_PHY_BASE        0xa400
1058
1059 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1060 {
1061         if (reg == 0x1f) {
1062                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1063                 return;
1064         }
1065
1066         if (tp->ocp_base != OCP_STD_PHY_BASE)
1067                 reg -= 0x10;
1068
1069         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1070 }
1071
1072 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1073 {
1074         if (tp->ocp_base != OCP_STD_PHY_BASE)
1075                 reg -= 0x10;
1076
1077         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1078 }
1079
1080 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1081 {
1082         if (reg == 0x1f) {
1083                 tp->ocp_base = value << 4;
1084                 return;
1085         }
1086
1087         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1088 }
1089
1090 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1091 {
1092         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1093 }
1094
1095 DECLARE_RTL_COND(rtl_phyar_cond)
1096 {
1097         void __iomem *ioaddr = tp->mmio_addr;
1098
1099         return RTL_R32(PHYAR) & 0x80000000;
1100 }
1101
1102 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1103 {
1104         void __iomem *ioaddr = tp->mmio_addr;
1105
1106         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1107
1108         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1109         /*
1110          * According to hardware specs a 20us delay is required after write
1111          * complete indication, but before sending next command.
1112          */
1113         udelay(20);
1114 }
1115
1116 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1117 {
1118         void __iomem *ioaddr = tp->mmio_addr;
1119         int value;
1120
1121         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1122
1123         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1124                 RTL_R32(PHYAR) & 0xffff : ~0;
1125
1126         /*
1127          * According to hardware specs a 20us delay is required after read
1128          * complete indication, but before sending next command.
1129          */
1130         udelay(20);
1131
1132         return value;
1133 }
1134
1135 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1136 {
1137         void __iomem *ioaddr = tp->mmio_addr;
1138
1139         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1140         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1141         RTL_W32(EPHY_RXER_NUM, 0);
1142
1143         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1144 }
1145
1146 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1147 {
1148         r8168dp_1_mdio_access(tp, reg,
1149                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1150 }
1151
1152 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1153 {
1154         void __iomem *ioaddr = tp->mmio_addr;
1155
1156         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1157
1158         mdelay(1);
1159         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1160         RTL_W32(EPHY_RXER_NUM, 0);
1161
1162         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1163                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1164 }
1165
1166 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1167
1168 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1169 {
1170         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1171 }
1172
1173 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1174 {
1175         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1176 }
1177
1178 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1179 {
1180         void __iomem *ioaddr = tp->mmio_addr;
1181
1182         r8168dp_2_mdio_start(ioaddr);
1183
1184         r8169_mdio_write(tp, reg, value);
1185
1186         r8168dp_2_mdio_stop(ioaddr);
1187 }
1188
1189 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1190 {
1191         void __iomem *ioaddr = tp->mmio_addr;
1192         int value;
1193
1194         r8168dp_2_mdio_start(ioaddr);
1195
1196         value = r8169_mdio_read(tp, reg);
1197
1198         r8168dp_2_mdio_stop(ioaddr);
1199
1200         return value;
1201 }
1202
1203 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1204 {
1205         tp->mdio_ops.write(tp, location, val);
1206 }
1207
1208 static int rtl_readphy(struct rtl8169_private *tp, int location)
1209 {
1210         return tp->mdio_ops.read(tp, location);
1211 }
1212
1213 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1214 {
1215         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1216 }
1217
1218 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1219 {
1220         int val;
1221
1222         val = rtl_readphy(tp, reg_addr);
1223         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1224 }
1225
1226 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1227                            int val)
1228 {
1229         struct rtl8169_private *tp = netdev_priv(dev);
1230
1231         rtl_writephy(tp, location, val);
1232 }
1233
1234 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1235 {
1236         struct rtl8169_private *tp = netdev_priv(dev);
1237
1238         return rtl_readphy(tp, location);
1239 }
1240
1241 DECLARE_RTL_COND(rtl_ephyar_cond)
1242 {
1243         void __iomem *ioaddr = tp->mmio_addr;
1244
1245         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1246 }
1247
1248 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1249 {
1250         void __iomem *ioaddr = tp->mmio_addr;
1251
1252         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1253                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1254
1255         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1256
1257         udelay(10);
1258 }
1259
1260 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1261 {
1262         void __iomem *ioaddr = tp->mmio_addr;
1263
1264         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1265
1266         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1267                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1268 }
1269
1270 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1271                           u32 val, int type)
1272 {
1273         void __iomem *ioaddr = tp->mmio_addr;
1274
1275         BUG_ON((addr & 3) || (mask == 0));
1276         RTL_W32(ERIDR, val);
1277         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1278
1279         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1280 }
1281
1282 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1283 {
1284         void __iomem *ioaddr = tp->mmio_addr;
1285
1286         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1287
1288         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1289                 RTL_R32(ERIDR) : ~0;
1290 }
1291
1292 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1293                          u32 m, int type)
1294 {
1295         u32 val;
1296
1297         val = rtl_eri_read(tp, addr, type);
1298         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1299 }
1300
1301 struct exgmac_reg {
1302         u16 addr;
1303         u16 mask;
1304         u32 val;
1305 };
1306
1307 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1308                                    const struct exgmac_reg *r, int len)
1309 {
1310         while (len-- > 0) {
1311                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1312                 r++;
1313         }
1314 }
1315
1316 DECLARE_RTL_COND(rtl_efusear_cond)
1317 {
1318         void __iomem *ioaddr = tp->mmio_addr;
1319
1320         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1321 }
1322
1323 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1324 {
1325         void __iomem *ioaddr = tp->mmio_addr;
1326
1327         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1328
1329         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1330                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1331 }
1332
1333 static u16 rtl_get_events(struct rtl8169_private *tp)
1334 {
1335         void __iomem *ioaddr = tp->mmio_addr;
1336
1337         return RTL_R16(IntrStatus);
1338 }
1339
1340 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1341 {
1342         void __iomem *ioaddr = tp->mmio_addr;
1343
1344         RTL_W16(IntrStatus, bits);
1345         mmiowb();
1346 }
1347
1348 static void rtl_irq_disable(struct rtl8169_private *tp)
1349 {
1350         void __iomem *ioaddr = tp->mmio_addr;
1351
1352         RTL_W16(IntrMask, 0);
1353         mmiowb();
1354 }
1355
1356 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1357 {
1358         void __iomem *ioaddr = tp->mmio_addr;
1359
1360         RTL_W16(IntrMask, bits);
1361 }
1362
1363 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1364 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1365 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1366
1367 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1368 {
1369         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1370 }
1371
1372 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1373 {
1374         void __iomem *ioaddr = tp->mmio_addr;
1375
1376         rtl_irq_disable(tp);
1377         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1378         RTL_R8(ChipCmd);
1379 }
1380
1381 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1382 {
1383         void __iomem *ioaddr = tp->mmio_addr;
1384
1385         return RTL_R32(TBICSR) & TBIReset;
1386 }
1387
1388 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1389 {
1390         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1391 }
1392
1393 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1394 {
1395         return RTL_R32(TBICSR) & TBILinkOk;
1396 }
1397
1398 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1399 {
1400         return RTL_R8(PHYstatus) & LinkStatus;
1401 }
1402
1403 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1404 {
1405         void __iomem *ioaddr = tp->mmio_addr;
1406
1407         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1408 }
1409
1410 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1411 {
1412         unsigned int val;
1413
1414         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1415         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1416 }
1417
1418 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1419 {
1420         void __iomem *ioaddr = tp->mmio_addr;
1421         struct net_device *dev = tp->dev;
1422
1423         if (!netif_running(dev))
1424                 return;
1425
1426         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1427             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1428                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1429                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1430                                       ERIAR_EXGMAC);
1431                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1432                                       ERIAR_EXGMAC);
1433                 } else if (RTL_R8(PHYstatus) & _100bps) {
1434                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1435                                       ERIAR_EXGMAC);
1436                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1437                                       ERIAR_EXGMAC);
1438                 } else {
1439                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1440                                       ERIAR_EXGMAC);
1441                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1442                                       ERIAR_EXGMAC);
1443                 }
1444                 /* Reset packet filter */
1445                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1446                              ERIAR_EXGMAC);
1447                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1448                              ERIAR_EXGMAC);
1449         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1450                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1451                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1452                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1453                                       ERIAR_EXGMAC);
1454                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1455                                       ERIAR_EXGMAC);
1456                 } else {
1457                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1458                                       ERIAR_EXGMAC);
1459                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1460                                       ERIAR_EXGMAC);
1461                 }
1462         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1463                 if (RTL_R8(PHYstatus) & _10bps) {
1464                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1465                                       ERIAR_EXGMAC);
1466                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1467                                       ERIAR_EXGMAC);
1468                 } else {
1469                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1470                                       ERIAR_EXGMAC);
1471                 }
1472         }
1473 }
1474
1475 static void __rtl8169_check_link_status(struct net_device *dev,
1476                                         struct rtl8169_private *tp,
1477                                         void __iomem *ioaddr, bool pm)
1478 {
1479         if (tp->link_ok(ioaddr)) {
1480                 rtl_link_chg_patch(tp);
1481                 /* This is to cancel a scheduled suspend if there's one. */
1482                 if (pm)
1483                         pm_request_resume(&tp->pci_dev->dev);
1484                 netif_carrier_on(dev);
1485                 if (net_ratelimit())
1486                         netif_info(tp, ifup, dev, "link up\n");
1487         } else {
1488                 netif_carrier_off(dev);
1489                 netif_info(tp, ifdown, dev, "link down\n");
1490                 if (pm)
1491                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1492         }
1493 }
1494
1495 static void rtl8169_check_link_status(struct net_device *dev,
1496                                       struct rtl8169_private *tp,
1497                                       void __iomem *ioaddr)
1498 {
1499         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1500 }
1501
1502 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1503
1504 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1505 {
1506         void __iomem *ioaddr = tp->mmio_addr;
1507         u8 options;
1508         u32 wolopts = 0;
1509
1510         options = RTL_R8(Config1);
1511         if (!(options & PMEnable))
1512                 return 0;
1513
1514         options = RTL_R8(Config3);
1515         if (options & LinkUp)
1516                 wolopts |= WAKE_PHY;
1517         if (options & MagicPacket)
1518                 wolopts |= WAKE_MAGIC;
1519
1520         options = RTL_R8(Config5);
1521         if (options & UWF)
1522                 wolopts |= WAKE_UCAST;
1523         if (options & BWF)
1524                 wolopts |= WAKE_BCAST;
1525         if (options & MWF)
1526                 wolopts |= WAKE_MCAST;
1527
1528         return wolopts;
1529 }
1530
1531 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1532 {
1533         struct rtl8169_private *tp = netdev_priv(dev);
1534
1535         rtl_lock_work(tp);
1536
1537         wol->supported = WAKE_ANY;
1538         wol->wolopts = __rtl8169_get_wol(tp);
1539
1540         rtl_unlock_work(tp);
1541 }
1542
1543 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1544 {
1545         void __iomem *ioaddr = tp->mmio_addr;
1546         unsigned int i;
1547         static const struct {
1548                 u32 opt;
1549                 u16 reg;
1550                 u8  mask;
1551         } cfg[] = {
1552                 { WAKE_PHY,   Config3, LinkUp },
1553                 { WAKE_MAGIC, Config3, MagicPacket },
1554                 { WAKE_UCAST, Config5, UWF },
1555                 { WAKE_BCAST, Config5, BWF },
1556                 { WAKE_MCAST, Config5, MWF },
1557                 { WAKE_ANY,   Config5, LanWake }
1558         };
1559         u8 options;
1560
1561         RTL_W8(Cfg9346, Cfg9346_Unlock);
1562
1563         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1564                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1565                 if (wolopts & cfg[i].opt)
1566                         options |= cfg[i].mask;
1567                 RTL_W8(cfg[i].reg, options);
1568         }
1569
1570         switch (tp->mac_version) {
1571         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1572                 options = RTL_R8(Config1) & ~PMEnable;
1573                 if (wolopts)
1574                         options |= PMEnable;
1575                 RTL_W8(Config1, options);
1576                 break;
1577         default:
1578                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1579                 if (wolopts)
1580                         options |= PME_SIGNAL;
1581                 RTL_W8(Config2, options);
1582                 break;
1583         }
1584
1585         RTL_W8(Cfg9346, Cfg9346_Lock);
1586 }
1587
1588 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1589 {
1590         struct rtl8169_private *tp = netdev_priv(dev);
1591
1592         rtl_lock_work(tp);
1593
1594         if (wol->wolopts)
1595                 tp->features |= RTL_FEATURE_WOL;
1596         else
1597                 tp->features &= ~RTL_FEATURE_WOL;
1598         __rtl8169_set_wol(tp, wol->wolopts);
1599
1600         rtl_unlock_work(tp);
1601
1602         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1603
1604         return 0;
1605 }
1606
1607 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1608 {
1609         return rtl_chip_infos[tp->mac_version].fw_name;
1610 }
1611
1612 static void rtl8169_get_drvinfo(struct net_device *dev,
1613                                 struct ethtool_drvinfo *info)
1614 {
1615         struct rtl8169_private *tp = netdev_priv(dev);
1616         struct rtl_fw *rtl_fw = tp->rtl_fw;
1617
1618         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1619         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1620         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1621         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1622         if (!IS_ERR_OR_NULL(rtl_fw))
1623                 strlcpy(info->fw_version, rtl_fw->version,
1624                         sizeof(info->fw_version));
1625 }
1626
1627 static int rtl8169_get_regs_len(struct net_device *dev)
1628 {
1629         return R8169_REGS_SIZE;
1630 }
1631
1632 static int rtl8169_set_speed_tbi(struct net_device *dev,
1633                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1634 {
1635         struct rtl8169_private *tp = netdev_priv(dev);
1636         void __iomem *ioaddr = tp->mmio_addr;
1637         int ret = 0;
1638         u32 reg;
1639
1640         reg = RTL_R32(TBICSR);
1641         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1642             (duplex == DUPLEX_FULL)) {
1643                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1644         } else if (autoneg == AUTONEG_ENABLE)
1645                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1646         else {
1647                 netif_warn(tp, link, dev,
1648                            "incorrect speed setting refused in TBI mode\n");
1649                 ret = -EOPNOTSUPP;
1650         }
1651
1652         return ret;
1653 }
1654
1655 static int rtl8169_set_speed_xmii(struct net_device *dev,
1656                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1657 {
1658         struct rtl8169_private *tp = netdev_priv(dev);
1659         int giga_ctrl, bmcr;
1660         int rc = -EINVAL;
1661
1662         rtl_writephy(tp, 0x1f, 0x0000);
1663
1664         if (autoneg == AUTONEG_ENABLE) {
1665                 int auto_nego;
1666
1667                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1668                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1669                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1670
1671                 if (adv & ADVERTISED_10baseT_Half)
1672                         auto_nego |= ADVERTISE_10HALF;
1673                 if (adv & ADVERTISED_10baseT_Full)
1674                         auto_nego |= ADVERTISE_10FULL;
1675                 if (adv & ADVERTISED_100baseT_Half)
1676                         auto_nego |= ADVERTISE_100HALF;
1677                 if (adv & ADVERTISED_100baseT_Full)
1678                         auto_nego |= ADVERTISE_100FULL;
1679
1680                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1681
1682                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1683                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1684
1685                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1686                 if (tp->mii.supports_gmii) {
1687                         if (adv & ADVERTISED_1000baseT_Half)
1688                                 giga_ctrl |= ADVERTISE_1000HALF;
1689                         if (adv & ADVERTISED_1000baseT_Full)
1690                                 giga_ctrl |= ADVERTISE_1000FULL;
1691                 } else if (adv & (ADVERTISED_1000baseT_Half |
1692                                   ADVERTISED_1000baseT_Full)) {
1693                         netif_info(tp, link, dev,
1694                                    "PHY does not support 1000Mbps\n");
1695                         goto out;
1696                 }
1697
1698                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1699
1700                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1701                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1702         } else {
1703                 giga_ctrl = 0;
1704
1705                 if (speed == SPEED_10)
1706                         bmcr = 0;
1707                 else if (speed == SPEED_100)
1708                         bmcr = BMCR_SPEED100;
1709                 else
1710                         goto out;
1711
1712                 if (duplex == DUPLEX_FULL)
1713                         bmcr |= BMCR_FULLDPLX;
1714         }
1715
1716         rtl_writephy(tp, MII_BMCR, bmcr);
1717
1718         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1719             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1720                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1721                         rtl_writephy(tp, 0x17, 0x2138);
1722                         rtl_writephy(tp, 0x0e, 0x0260);
1723                 } else {
1724                         rtl_writephy(tp, 0x17, 0x2108);
1725                         rtl_writephy(tp, 0x0e, 0x0000);
1726                 }
1727         }
1728
1729         rc = 0;
1730 out:
1731         return rc;
1732 }
1733
1734 static int rtl8169_set_speed(struct net_device *dev,
1735                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1736 {
1737         struct rtl8169_private *tp = netdev_priv(dev);
1738         int ret;
1739
1740         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1741         if (ret < 0)
1742                 goto out;
1743
1744         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1745             (advertising & ADVERTISED_1000baseT_Full)) {
1746                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1747         }
1748 out:
1749         return ret;
1750 }
1751
1752 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1753 {
1754         struct rtl8169_private *tp = netdev_priv(dev);
1755         int ret;
1756
1757         del_timer_sync(&tp->timer);
1758
1759         rtl_lock_work(tp);
1760         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1761                                 cmd->duplex, cmd->advertising);
1762         rtl_unlock_work(tp);
1763
1764         return ret;
1765 }
1766
1767 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1768         netdev_features_t features)
1769 {
1770         struct rtl8169_private *tp = netdev_priv(dev);
1771
1772         if (dev->mtu > TD_MSS_MAX)
1773                 features &= ~NETIF_F_ALL_TSO;
1774
1775         if (dev->mtu > JUMBO_1K &&
1776             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1777                 features &= ~NETIF_F_IP_CSUM;
1778
1779         return features;
1780 }
1781
1782 static void __rtl8169_set_features(struct net_device *dev,
1783                                    netdev_features_t features)
1784 {
1785         struct rtl8169_private *tp = netdev_priv(dev);
1786         void __iomem *ioaddr = tp->mmio_addr;
1787         u32 rx_config;
1788
1789         rx_config = RTL_R32(RxConfig);
1790         if (features & NETIF_F_RXALL)
1791                 rx_config |= (AcceptErr | AcceptRunt);
1792         else
1793                 rx_config &= ~(AcceptErr | AcceptRunt);
1794
1795         RTL_W32(RxConfig, rx_config);
1796
1797         if (features & NETIF_F_RXCSUM)
1798                 tp->cp_cmd |= RxChkSum;
1799         else
1800                 tp->cp_cmd &= ~RxChkSum;
1801
1802         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1803                 tp->cp_cmd |= RxVlan;
1804         else
1805                 tp->cp_cmd &= ~RxVlan;
1806
1807         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
1808
1809         RTL_W16(CPlusCmd, tp->cp_cmd);
1810         RTL_R16(CPlusCmd);
1811 }
1812
1813 static int rtl8169_set_features(struct net_device *dev,
1814                                 netdev_features_t features)
1815 {
1816         struct rtl8169_private *tp = netdev_priv(dev);
1817
1818         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
1819
1820         rtl_lock_work(tp);
1821         if (features ^ dev->features);
1822                 __rtl8169_set_features(dev, features);
1823         rtl_unlock_work(tp);
1824
1825         return 0;
1826 }
1827
1828
1829 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1830 {
1831         return (vlan_tx_tag_present(skb)) ?
1832                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1833 }
1834
1835 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1836 {
1837         u32 opts2 = le32_to_cpu(desc->opts2);
1838
1839         if (opts2 & RxVlanTag)
1840                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1841 }
1842
1843 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1844 {
1845         struct rtl8169_private *tp = netdev_priv(dev);
1846         void __iomem *ioaddr = tp->mmio_addr;
1847         u32 status;
1848
1849         cmd->supported =
1850                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1851         cmd->port = PORT_FIBRE;
1852         cmd->transceiver = XCVR_INTERNAL;
1853
1854         status = RTL_R32(TBICSR);
1855         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1856         cmd->autoneg = !!(status & TBINwEnable);
1857
1858         ethtool_cmd_speed_set(cmd, SPEED_1000);
1859         cmd->duplex = DUPLEX_FULL; /* Always set */
1860
1861         return 0;
1862 }
1863
1864 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1865 {
1866         struct rtl8169_private *tp = netdev_priv(dev);
1867
1868         return mii_ethtool_gset(&tp->mii, cmd);
1869 }
1870
1871 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1872 {
1873         struct rtl8169_private *tp = netdev_priv(dev);
1874         int rc;
1875
1876         rtl_lock_work(tp);
1877         rc = tp->get_settings(dev, cmd);
1878         rtl_unlock_work(tp);
1879
1880         return rc;
1881 }
1882
1883 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1884                              void *p)
1885 {
1886         struct rtl8169_private *tp = netdev_priv(dev);
1887         u32 __iomem *data = tp->mmio_addr;
1888         u32 *dw = p;
1889         int i;
1890
1891         rtl_lock_work(tp);
1892         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1893                 memcpy_fromio(dw++, data++, 4);
1894         rtl_unlock_work(tp);
1895 }
1896
1897 static u32 rtl8169_get_msglevel(struct net_device *dev)
1898 {
1899         struct rtl8169_private *tp = netdev_priv(dev);
1900
1901         return tp->msg_enable;
1902 }
1903
1904 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1905 {
1906         struct rtl8169_private *tp = netdev_priv(dev);
1907
1908         tp->msg_enable = value;
1909 }
1910
1911 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1912         "tx_packets",
1913         "rx_packets",
1914         "tx_errors",
1915         "rx_errors",
1916         "rx_missed",
1917         "align_errors",
1918         "tx_single_collisions",
1919         "tx_multi_collisions",
1920         "unicast",
1921         "broadcast",
1922         "multicast",
1923         "tx_aborted",
1924         "tx_underrun",
1925 };
1926
1927 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1928 {
1929         switch (sset) {
1930         case ETH_SS_STATS:
1931                 return ARRAY_SIZE(rtl8169_gstrings);
1932         default:
1933                 return -EOPNOTSUPP;
1934         }
1935 }
1936
1937 DECLARE_RTL_COND(rtl_counters_cond)
1938 {
1939         void __iomem *ioaddr = tp->mmio_addr;
1940
1941         return RTL_R32(CounterAddrLow) & CounterDump;
1942 }
1943
1944 static void rtl8169_update_counters(struct net_device *dev)
1945 {
1946         struct rtl8169_private *tp = netdev_priv(dev);
1947         void __iomem *ioaddr = tp->mmio_addr;
1948         struct device *d = &tp->pci_dev->dev;
1949         struct rtl8169_counters *counters;
1950         dma_addr_t paddr;
1951         u32 cmd;
1952
1953         /*
1954          * Some chips are unable to dump tally counters when the receiver
1955          * is disabled.
1956          */
1957         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1958                 return;
1959
1960         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1961         if (!counters)
1962                 return;
1963
1964         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1965         cmd = (u64)paddr & DMA_BIT_MASK(32);
1966         RTL_W32(CounterAddrLow, cmd);
1967         RTL_W32(CounterAddrLow, cmd | CounterDump);
1968
1969         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1970                 memcpy(&tp->counters, counters, sizeof(*counters));
1971
1972         RTL_W32(CounterAddrLow, 0);
1973         RTL_W32(CounterAddrHigh, 0);
1974
1975         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1976 }
1977
1978 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1979                                       struct ethtool_stats *stats, u64 *data)
1980 {
1981         struct rtl8169_private *tp = netdev_priv(dev);
1982
1983         ASSERT_RTNL();
1984
1985         rtl8169_update_counters(dev);
1986
1987         data[0] = le64_to_cpu(tp->counters.tx_packets);
1988         data[1] = le64_to_cpu(tp->counters.rx_packets);
1989         data[2] = le64_to_cpu(tp->counters.tx_errors);
1990         data[3] = le32_to_cpu(tp->counters.rx_errors);
1991         data[4] = le16_to_cpu(tp->counters.rx_missed);
1992         data[5] = le16_to_cpu(tp->counters.align_errors);
1993         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1994         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1995         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1996         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1997         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1998         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1999         data[12] = le16_to_cpu(tp->counters.tx_underun);
2000 }
2001
2002 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2003 {
2004         switch(stringset) {
2005         case ETH_SS_STATS:
2006                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2007                 break;
2008         }
2009 }
2010
2011 static const struct ethtool_ops rtl8169_ethtool_ops = {
2012         .get_drvinfo            = rtl8169_get_drvinfo,
2013         .get_regs_len           = rtl8169_get_regs_len,
2014         .get_link               = ethtool_op_get_link,
2015         .get_settings           = rtl8169_get_settings,
2016         .set_settings           = rtl8169_set_settings,
2017         .get_msglevel           = rtl8169_get_msglevel,
2018         .set_msglevel           = rtl8169_set_msglevel,
2019         .get_regs               = rtl8169_get_regs,
2020         .get_wol                = rtl8169_get_wol,
2021         .set_wol                = rtl8169_set_wol,
2022         .get_strings            = rtl8169_get_strings,
2023         .get_sset_count         = rtl8169_get_sset_count,
2024         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2025         .get_ts_info            = ethtool_op_get_ts_info,
2026 };
2027
2028 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2029                                     struct net_device *dev, u8 default_version)
2030 {
2031         void __iomem *ioaddr = tp->mmio_addr;
2032         /*
2033          * The driver currently handles the 8168Bf and the 8168Be identically
2034          * but they can be identified more specifically through the test below
2035          * if needed:
2036          *
2037          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2038          *
2039          * Same thing for the 8101Eb and the 8101Ec:
2040          *
2041          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2042          */
2043         static const struct rtl_mac_info {
2044                 u32 mask;
2045                 u32 val;
2046                 int mac_version;
2047         } mac_info[] = {
2048                 /* 8168G family. */
2049                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2050                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2051                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2052                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2053
2054                 /* 8168F family. */
2055                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2056                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2057                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2058
2059                 /* 8168E family. */
2060                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2061                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2062                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2063                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2064
2065                 /* 8168D family. */
2066                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2067                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2068                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2069
2070                 /* 8168DP family. */
2071                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2072                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2073                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2074
2075                 /* 8168C family. */
2076                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2077                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2078                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2079                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2080                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2081                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2082                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2083                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2084                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2085
2086                 /* 8168B family. */
2087                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2088                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2089                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2090                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2091
2092                 /* 8101 family. */
2093                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2094                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2095                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2096                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2097                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2098                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2099                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2100                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2101                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2102                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2103                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2104                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2105                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2106                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2107                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2108                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2109                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2110                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2111                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2112                 /* FIXME: where did these entries come from ? -- FR */
2113                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2114                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2115
2116                 /* 8110 family. */
2117                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2118                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2119                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2120                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2121                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2122                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2123
2124                 /* Catch-all */
2125                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2126         };
2127         const struct rtl_mac_info *p = mac_info;
2128         u32 reg;
2129
2130         reg = RTL_R32(TxConfig);
2131         while ((reg & p->mask) != p->val)
2132                 p++;
2133         tp->mac_version = p->mac_version;
2134
2135         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2136                 netif_notice(tp, probe, dev,
2137                              "unknown MAC, using family default\n");
2138                 tp->mac_version = default_version;
2139         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2140                 tp->mac_version = tp->mii.supports_gmii ?
2141                                   RTL_GIGA_MAC_VER_42 :
2142                                   RTL_GIGA_MAC_VER_43;
2143         }
2144 }
2145
2146 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2147 {
2148         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2149 }
2150
2151 struct phy_reg {
2152         u16 reg;
2153         u16 val;
2154 };
2155
2156 static void rtl_writephy_batch(struct rtl8169_private *tp,
2157                                const struct phy_reg *regs, int len)
2158 {
2159         while (len-- > 0) {
2160                 rtl_writephy(tp, regs->reg, regs->val);
2161                 regs++;
2162         }
2163 }
2164
2165 #define PHY_READ                0x00000000
2166 #define PHY_DATA_OR             0x10000000
2167 #define PHY_DATA_AND            0x20000000
2168 #define PHY_BJMPN               0x30000000
2169 #define PHY_MDIO_CHG            0x40000000
2170 #define PHY_CLEAR_READCOUNT     0x70000000
2171 #define PHY_WRITE               0x80000000
2172 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2173 #define PHY_COMP_EQ_SKIPN       0xa0000000
2174 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2175 #define PHY_WRITE_PREVIOUS      0xc0000000
2176 #define PHY_SKIPN               0xd0000000
2177 #define PHY_DELAY_MS            0xe0000000
2178
2179 struct fw_info {
2180         u32     magic;
2181         char    version[RTL_VER_SIZE];
2182         __le32  fw_start;
2183         __le32  fw_len;
2184         u8      chksum;
2185 } __packed;
2186
2187 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2188
2189 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2190 {
2191         const struct firmware *fw = rtl_fw->fw;
2192         struct fw_info *fw_info = (struct fw_info *)fw->data;
2193         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2194         char *version = rtl_fw->version;
2195         bool rc = false;
2196
2197         if (fw->size < FW_OPCODE_SIZE)
2198                 goto out;
2199
2200         if (!fw_info->magic) {
2201                 size_t i, size, start;
2202                 u8 checksum = 0;
2203
2204                 if (fw->size < sizeof(*fw_info))
2205                         goto out;
2206
2207                 for (i = 0; i < fw->size; i++)
2208                         checksum += fw->data[i];
2209                 if (checksum != 0)
2210                         goto out;
2211
2212                 start = le32_to_cpu(fw_info->fw_start);
2213                 if (start > fw->size)
2214                         goto out;
2215
2216                 size = le32_to_cpu(fw_info->fw_len);
2217                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2218                         goto out;
2219
2220                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2221
2222                 pa->code = (__le32 *)(fw->data + start);
2223                 pa->size = size;
2224         } else {
2225                 if (fw->size % FW_OPCODE_SIZE)
2226                         goto out;
2227
2228                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2229
2230                 pa->code = (__le32 *)fw->data;
2231                 pa->size = fw->size / FW_OPCODE_SIZE;
2232         }
2233         version[RTL_VER_SIZE - 1] = 0;
2234
2235         rc = true;
2236 out:
2237         return rc;
2238 }
2239
2240 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2241                            struct rtl_fw_phy_action *pa)
2242 {
2243         bool rc = false;
2244         size_t index;
2245
2246         for (index = 0; index < pa->size; index++) {
2247                 u32 action = le32_to_cpu(pa->code[index]);
2248                 u32 regno = (action & 0x0fff0000) >> 16;
2249
2250                 switch(action & 0xf0000000) {
2251                 case PHY_READ:
2252                 case PHY_DATA_OR:
2253                 case PHY_DATA_AND:
2254                 case PHY_MDIO_CHG:
2255                 case PHY_CLEAR_READCOUNT:
2256                 case PHY_WRITE:
2257                 case PHY_WRITE_PREVIOUS:
2258                 case PHY_DELAY_MS:
2259                         break;
2260
2261                 case PHY_BJMPN:
2262                         if (regno > index) {
2263                                 netif_err(tp, ifup, tp->dev,
2264                                           "Out of range of firmware\n");
2265                                 goto out;
2266                         }
2267                         break;
2268                 case PHY_READCOUNT_EQ_SKIP:
2269                         if (index + 2 >= pa->size) {
2270                                 netif_err(tp, ifup, tp->dev,
2271                                           "Out of range of firmware\n");
2272                                 goto out;
2273                         }
2274                         break;
2275                 case PHY_COMP_EQ_SKIPN:
2276                 case PHY_COMP_NEQ_SKIPN:
2277                 case PHY_SKIPN:
2278                         if (index + 1 + regno >= pa->size) {
2279                                 netif_err(tp, ifup, tp->dev,
2280                                           "Out of range of firmware\n");
2281                                 goto out;
2282                         }
2283                         break;
2284
2285                 default:
2286                         netif_err(tp, ifup, tp->dev,
2287                                   "Invalid action 0x%08x\n", action);
2288                         goto out;
2289                 }
2290         }
2291         rc = true;
2292 out:
2293         return rc;
2294 }
2295
2296 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2297 {
2298         struct net_device *dev = tp->dev;
2299         int rc = -EINVAL;
2300
2301         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2302                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2303                 goto out;
2304         }
2305
2306         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2307                 rc = 0;
2308 out:
2309         return rc;
2310 }
2311
2312 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2313 {
2314         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2315         struct mdio_ops org, *ops = &tp->mdio_ops;
2316         u32 predata, count;
2317         size_t index;
2318
2319         predata = count = 0;
2320         org.write = ops->write;
2321         org.read = ops->read;
2322
2323         for (index = 0; index < pa->size; ) {
2324                 u32 action = le32_to_cpu(pa->code[index]);
2325                 u32 data = action & 0x0000ffff;
2326                 u32 regno = (action & 0x0fff0000) >> 16;
2327
2328                 if (!action)
2329                         break;
2330
2331                 switch(action & 0xf0000000) {
2332                 case PHY_READ:
2333                         predata = rtl_readphy(tp, regno);
2334                         count++;
2335                         index++;
2336                         break;
2337                 case PHY_DATA_OR:
2338                         predata |= data;
2339                         index++;
2340                         break;
2341                 case PHY_DATA_AND:
2342                         predata &= data;
2343                         index++;
2344                         break;
2345                 case PHY_BJMPN:
2346                         index -= regno;
2347                         break;
2348                 case PHY_MDIO_CHG:
2349                         if (data == 0) {
2350                                 ops->write = org.write;
2351                                 ops->read = org.read;
2352                         } else if (data == 1) {
2353                                 ops->write = mac_mcu_write;
2354                                 ops->read = mac_mcu_read;
2355                         }
2356
2357                         index++;
2358                         break;
2359                 case PHY_CLEAR_READCOUNT:
2360                         count = 0;
2361                         index++;
2362                         break;
2363                 case PHY_WRITE:
2364                         rtl_writephy(tp, regno, data);
2365                         index++;
2366                         break;
2367                 case PHY_READCOUNT_EQ_SKIP:
2368                         index += (count == data) ? 2 : 1;
2369                         break;
2370                 case PHY_COMP_EQ_SKIPN:
2371                         if (predata == data)
2372                                 index += regno;
2373                         index++;
2374                         break;
2375                 case PHY_COMP_NEQ_SKIPN:
2376                         if (predata != data)
2377                                 index += regno;
2378                         index++;
2379                         break;
2380                 case PHY_WRITE_PREVIOUS:
2381                         rtl_writephy(tp, regno, predata);
2382                         index++;
2383                         break;
2384                 case PHY_SKIPN:
2385                         index += regno + 1;
2386                         break;
2387                 case PHY_DELAY_MS:
2388                         mdelay(data);
2389                         index++;
2390                         break;
2391
2392                 default:
2393                         BUG();
2394                 }
2395         }
2396
2397         ops->write = org.write;
2398         ops->read = org.read;
2399 }
2400
2401 static void rtl_release_firmware(struct rtl8169_private *tp)
2402 {
2403         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2404                 release_firmware(tp->rtl_fw->fw);
2405                 kfree(tp->rtl_fw);
2406         }
2407         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2408 }
2409
2410 static void rtl_apply_firmware(struct rtl8169_private *tp)
2411 {
2412         struct rtl_fw *rtl_fw = tp->rtl_fw;
2413
2414         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2415         if (!IS_ERR_OR_NULL(rtl_fw))
2416                 rtl_phy_write_fw(tp, rtl_fw);
2417 }
2418
2419 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2420 {
2421         if (rtl_readphy(tp, reg) != val)
2422                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2423         else
2424                 rtl_apply_firmware(tp);
2425 }
2426
2427 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2428 {
2429         static const struct phy_reg phy_reg_init[] = {
2430                 { 0x1f, 0x0001 },
2431                 { 0x06, 0x006e },
2432                 { 0x08, 0x0708 },
2433                 { 0x15, 0x4000 },
2434                 { 0x18, 0x65c7 },
2435
2436                 { 0x1f, 0x0001 },
2437                 { 0x03, 0x00a1 },
2438                 { 0x02, 0x0008 },
2439                 { 0x01, 0x0120 },
2440                 { 0x00, 0x1000 },
2441                 { 0x04, 0x0800 },
2442                 { 0x04, 0x0000 },
2443
2444                 { 0x03, 0xff41 },
2445                 { 0x02, 0xdf60 },
2446                 { 0x01, 0x0140 },
2447                 { 0x00, 0x0077 },
2448                 { 0x04, 0x7800 },
2449                 { 0x04, 0x7000 },
2450
2451                 { 0x03, 0x802f },
2452                 { 0x02, 0x4f02 },
2453                 { 0x01, 0x0409 },
2454                 { 0x00, 0xf0f9 },
2455                 { 0x04, 0x9800 },
2456                 { 0x04, 0x9000 },
2457
2458                 { 0x03, 0xdf01 },
2459                 { 0x02, 0xdf20 },
2460                 { 0x01, 0xff95 },
2461                 { 0x00, 0xba00 },
2462                 { 0x04, 0xa800 },
2463                 { 0x04, 0xa000 },
2464
2465                 { 0x03, 0xff41 },
2466                 { 0x02, 0xdf20 },
2467                 { 0x01, 0x0140 },
2468                 { 0x00, 0x00bb },
2469                 { 0x04, 0xb800 },
2470                 { 0x04, 0xb000 },
2471
2472                 { 0x03, 0xdf41 },
2473                 { 0x02, 0xdc60 },
2474                 { 0x01, 0x6340 },
2475                 { 0x00, 0x007d },
2476                 { 0x04, 0xd800 },
2477                 { 0x04, 0xd000 },
2478
2479                 { 0x03, 0xdf01 },
2480                 { 0x02, 0xdf20 },
2481                 { 0x01, 0x100a },
2482                 { 0x00, 0xa0ff },
2483                 { 0x04, 0xf800 },
2484                 { 0x04, 0xf000 },
2485
2486                 { 0x1f, 0x0000 },
2487                 { 0x0b, 0x0000 },
2488                 { 0x00, 0x9200 }
2489         };
2490
2491         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2492 }
2493
2494 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2495 {
2496         static const struct phy_reg phy_reg_init[] = {
2497                 { 0x1f, 0x0002 },
2498                 { 0x01, 0x90d0 },
2499                 { 0x1f, 0x0000 }
2500         };
2501
2502         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2503 }
2504
2505 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2506 {
2507         struct pci_dev *pdev = tp->pci_dev;
2508
2509         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2510             (pdev->subsystem_device != 0xe000))
2511                 return;
2512
2513         rtl_writephy(tp, 0x1f, 0x0001);
2514         rtl_writephy(tp, 0x10, 0xf01b);
2515         rtl_writephy(tp, 0x1f, 0x0000);
2516 }
2517
2518 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2519 {
2520         static const struct phy_reg phy_reg_init[] = {
2521                 { 0x1f, 0x0001 },
2522                 { 0x04, 0x0000 },
2523                 { 0x03, 0x00a1 },
2524                 { 0x02, 0x0008 },
2525                 { 0x01, 0x0120 },
2526                 { 0x00, 0x1000 },
2527                 { 0x04, 0x0800 },
2528                 { 0x04, 0x9000 },
2529                 { 0x03, 0x802f },
2530                 { 0x02, 0x4f02 },
2531                 { 0x01, 0x0409 },
2532                 { 0x00, 0xf099 },
2533                 { 0x04, 0x9800 },
2534                 { 0x04, 0xa000 },
2535                 { 0x03, 0xdf01 },
2536                 { 0x02, 0xdf20 },
2537                 { 0x01, 0xff95 },
2538                 { 0x00, 0xba00 },
2539                 { 0x04, 0xa800 },
2540                 { 0x04, 0xf000 },
2541                 { 0x03, 0xdf01 },
2542                 { 0x02, 0xdf20 },
2543                 { 0x01, 0x101a },
2544                 { 0x00, 0xa0ff },
2545                 { 0x04, 0xf800 },
2546                 { 0x04, 0x0000 },
2547                 { 0x1f, 0x0000 },
2548
2549                 { 0x1f, 0x0001 },
2550                 { 0x10, 0xf41b },
2551                 { 0x14, 0xfb54 },
2552                 { 0x18, 0xf5c7 },
2553                 { 0x1f, 0x0000 },
2554
2555                 { 0x1f, 0x0001 },
2556                 { 0x17, 0x0cc0 },
2557                 { 0x1f, 0x0000 }
2558         };
2559
2560         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2561
2562         rtl8169scd_hw_phy_config_quirk(tp);
2563 }
2564
2565 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2566 {
2567         static const struct phy_reg phy_reg_init[] = {
2568                 { 0x1f, 0x0001 },
2569                 { 0x04, 0x0000 },
2570                 { 0x03, 0x00a1 },
2571                 { 0x02, 0x0008 },
2572                 { 0x01, 0x0120 },
2573                 { 0x00, 0x1000 },
2574                 { 0x04, 0x0800 },
2575                 { 0x04, 0x9000 },
2576                 { 0x03, 0x802f },
2577                 { 0x02, 0x4f02 },
2578                 { 0x01, 0x0409 },
2579                 { 0x00, 0xf099 },
2580                 { 0x04, 0x9800 },
2581                 { 0x04, 0xa000 },
2582                 { 0x03, 0xdf01 },
2583                 { 0x02, 0xdf20 },
2584                 { 0x01, 0xff95 },
2585                 { 0x00, 0xba00 },
2586                 { 0x04, 0xa800 },
2587                 { 0x04, 0xf000 },
2588                 { 0x03, 0xdf01 },
2589                 { 0x02, 0xdf20 },
2590                 { 0x01, 0x101a },
2591                 { 0x00, 0xa0ff },
2592                 { 0x04, 0xf800 },
2593                 { 0x04, 0x0000 },
2594                 { 0x1f, 0x0000 },
2595
2596                 { 0x1f, 0x0001 },
2597                 { 0x0b, 0x8480 },
2598                 { 0x1f, 0x0000 },
2599
2600                 { 0x1f, 0x0001 },
2601                 { 0x18, 0x67c7 },
2602                 { 0x04, 0x2000 },
2603                 { 0x03, 0x002f },
2604                 { 0x02, 0x4360 },
2605                 { 0x01, 0x0109 },
2606                 { 0x00, 0x3022 },
2607                 { 0x04, 0x2800 },
2608                 { 0x1f, 0x0000 },
2609
2610                 { 0x1f, 0x0001 },
2611                 { 0x17, 0x0cc0 },
2612                 { 0x1f, 0x0000 }
2613         };
2614
2615         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2616 }
2617
2618 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2619 {
2620         static const struct phy_reg phy_reg_init[] = {
2621                 { 0x10, 0xf41b },
2622                 { 0x1f, 0x0000 }
2623         };
2624
2625         rtl_writephy(tp, 0x1f, 0x0001);
2626         rtl_patchphy(tp, 0x16, 1 << 0);
2627
2628         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2629 }
2630
2631 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2632 {
2633         static const struct phy_reg phy_reg_init[] = {
2634                 { 0x1f, 0x0001 },
2635                 { 0x10, 0xf41b },
2636                 { 0x1f, 0x0000 }
2637         };
2638
2639         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2640 }
2641
2642 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2643 {
2644         static const struct phy_reg phy_reg_init[] = {
2645                 { 0x1f, 0x0000 },
2646                 { 0x1d, 0x0f00 },
2647                 { 0x1f, 0x0002 },
2648                 { 0x0c, 0x1ec8 },
2649                 { 0x1f, 0x0000 }
2650         };
2651
2652         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2653 }
2654
2655 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2656 {
2657         static const struct phy_reg phy_reg_init[] = {
2658                 { 0x1f, 0x0001 },
2659                 { 0x1d, 0x3d98 },
2660                 { 0x1f, 0x0000 }
2661         };
2662
2663         rtl_writephy(tp, 0x1f, 0x0000);
2664         rtl_patchphy(tp, 0x14, 1 << 5);
2665         rtl_patchphy(tp, 0x0d, 1 << 5);
2666
2667         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2668 }
2669
2670 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2671 {
2672         static const struct phy_reg phy_reg_init[] = {
2673                 { 0x1f, 0x0001 },
2674                 { 0x12, 0x2300 },
2675                 { 0x1f, 0x0002 },
2676                 { 0x00, 0x88d4 },
2677                 { 0x01, 0x82b1 },
2678                 { 0x03, 0x7002 },
2679                 { 0x08, 0x9e30 },
2680                 { 0x09, 0x01f0 },
2681                 { 0x0a, 0x5500 },
2682                 { 0x0c, 0x00c8 },
2683                 { 0x1f, 0x0003 },
2684                 { 0x12, 0xc096 },
2685                 { 0x16, 0x000a },
2686                 { 0x1f, 0x0000 },
2687                 { 0x1f, 0x0000 },
2688                 { 0x09, 0x2000 },
2689                 { 0x09, 0x0000 }
2690         };
2691
2692         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2693
2694         rtl_patchphy(tp, 0x14, 1 << 5);
2695         rtl_patchphy(tp, 0x0d, 1 << 5);
2696         rtl_writephy(tp, 0x1f, 0x0000);
2697 }
2698
2699 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2700 {
2701         static const struct phy_reg phy_reg_init[] = {
2702                 { 0x1f, 0x0001 },
2703                 { 0x12, 0x2300 },
2704                 { 0x03, 0x802f },
2705                 { 0x02, 0x4f02 },
2706                 { 0x01, 0x0409 },
2707                 { 0x00, 0xf099 },
2708                 { 0x04, 0x9800 },
2709                 { 0x04, 0x9000 },
2710                 { 0x1d, 0x3d98 },
2711                 { 0x1f, 0x0002 },
2712                 { 0x0c, 0x7eb8 },
2713                 { 0x06, 0x0761 },
2714                 { 0x1f, 0x0003 },
2715                 { 0x16, 0x0f0a },
2716                 { 0x1f, 0x0000 }
2717         };
2718
2719         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2720
2721         rtl_patchphy(tp, 0x16, 1 << 0);
2722         rtl_patchphy(tp, 0x14, 1 << 5);
2723         rtl_patchphy(tp, 0x0d, 1 << 5);
2724         rtl_writephy(tp, 0x1f, 0x0000);
2725 }
2726
2727 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2728 {
2729         static const struct phy_reg phy_reg_init[] = {
2730                 { 0x1f, 0x0001 },
2731                 { 0x12, 0x2300 },
2732                 { 0x1d, 0x3d98 },
2733                 { 0x1f, 0x0002 },
2734                 { 0x0c, 0x7eb8 },
2735                 { 0x06, 0x5461 },
2736                 { 0x1f, 0x0003 },
2737                 { 0x16, 0x0f0a },
2738                 { 0x1f, 0x0000 }
2739         };
2740
2741         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2742
2743         rtl_patchphy(tp, 0x16, 1 << 0);
2744         rtl_patchphy(tp, 0x14, 1 << 5);
2745         rtl_patchphy(tp, 0x0d, 1 << 5);
2746         rtl_writephy(tp, 0x1f, 0x0000);
2747 }
2748
2749 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2750 {
2751         rtl8168c_3_hw_phy_config(tp);
2752 }
2753
2754 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2755 {
2756         static const struct phy_reg phy_reg_init_0[] = {
2757                 /* Channel Estimation */
2758                 { 0x1f, 0x0001 },
2759                 { 0x06, 0x4064 },
2760                 { 0x07, 0x2863 },
2761                 { 0x08, 0x059c },
2762                 { 0x09, 0x26b4 },
2763                 { 0x0a, 0x6a19 },
2764                 { 0x0b, 0xdcc8 },
2765                 { 0x10, 0xf06d },
2766                 { 0x14, 0x7f68 },
2767                 { 0x18, 0x7fd9 },
2768                 { 0x1c, 0xf0ff },
2769                 { 0x1d, 0x3d9c },
2770                 { 0x1f, 0x0003 },
2771                 { 0x12, 0xf49f },
2772                 { 0x13, 0x070b },
2773                 { 0x1a, 0x05ad },
2774                 { 0x14, 0x94c0 },
2775
2776                 /*
2777                  * Tx Error Issue
2778                  * Enhance line driver power
2779                  */
2780                 { 0x1f, 0x0002 },
2781                 { 0x06, 0x5561 },
2782                 { 0x1f, 0x0005 },
2783                 { 0x05, 0x8332 },
2784                 { 0x06, 0x5561 },
2785
2786                 /*
2787                  * Can not link to 1Gbps with bad cable
2788                  * Decrease SNR threshold form 21.07dB to 19.04dB
2789                  */
2790                 { 0x1f, 0x0001 },
2791                 { 0x17, 0x0cc0 },
2792
2793                 { 0x1f, 0x0000 },
2794                 { 0x0d, 0xf880 }
2795         };
2796
2797         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2798
2799         /*
2800          * Rx Error Issue
2801          * Fine Tune Switching regulator parameter
2802          */
2803         rtl_writephy(tp, 0x1f, 0x0002);
2804         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2805         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2806
2807         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2808                 static const struct phy_reg phy_reg_init[] = {
2809                         { 0x1f, 0x0002 },
2810                         { 0x05, 0x669a },
2811                         { 0x1f, 0x0005 },
2812                         { 0x05, 0x8330 },
2813                         { 0x06, 0x669a },
2814                         { 0x1f, 0x0002 }
2815                 };
2816                 int val;
2817
2818                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2819
2820                 val = rtl_readphy(tp, 0x0d);
2821
2822                 if ((val & 0x00ff) != 0x006c) {
2823                         static const u32 set[] = {
2824                                 0x0065, 0x0066, 0x0067, 0x0068,
2825                                 0x0069, 0x006a, 0x006b, 0x006c
2826                         };
2827                         int i;
2828
2829                         rtl_writephy(tp, 0x1f, 0x0002);
2830
2831                         val &= 0xff00;
2832                         for (i = 0; i < ARRAY_SIZE(set); i++)
2833                                 rtl_writephy(tp, 0x0d, val | set[i]);
2834                 }
2835         } else {
2836                 static const struct phy_reg phy_reg_init[] = {
2837                         { 0x1f, 0x0002 },
2838                         { 0x05, 0x6662 },
2839                         { 0x1f, 0x0005 },
2840                         { 0x05, 0x8330 },
2841                         { 0x06, 0x6662 }
2842                 };
2843
2844                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2845         }
2846
2847         /* RSET couple improve */
2848         rtl_writephy(tp, 0x1f, 0x0002);
2849         rtl_patchphy(tp, 0x0d, 0x0300);
2850         rtl_patchphy(tp, 0x0f, 0x0010);
2851
2852         /* Fine tune PLL performance */
2853         rtl_writephy(tp, 0x1f, 0x0002);
2854         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2855         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2856
2857         rtl_writephy(tp, 0x1f, 0x0005);
2858         rtl_writephy(tp, 0x05, 0x001b);
2859
2860         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2861
2862         rtl_writephy(tp, 0x1f, 0x0000);
2863 }
2864
2865 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2866 {
2867         static const struct phy_reg phy_reg_init_0[] = {
2868                 /* Channel Estimation */
2869                 { 0x1f, 0x0001 },
2870                 { 0x06, 0x4064 },
2871                 { 0x07, 0x2863 },
2872                 { 0x08, 0x059c },
2873                 { 0x09, 0x26b4 },
2874                 { 0x0a, 0x6a19 },
2875                 { 0x0b, 0xdcc8 },
2876                 { 0x10, 0xf06d },
2877                 { 0x14, 0x7f68 },
2878                 { 0x18, 0x7fd9 },
2879                 { 0x1c, 0xf0ff },
2880                 { 0x1d, 0x3d9c },
2881                 { 0x1f, 0x0003 },
2882                 { 0x12, 0xf49f },
2883                 { 0x13, 0x070b },
2884                 { 0x1a, 0x05ad },
2885                 { 0x14, 0x94c0 },
2886
2887                 /*
2888                  * Tx Error Issue
2889                  * Enhance line driver power
2890                  */
2891                 { 0x1f, 0x0002 },
2892                 { 0x06, 0x5561 },
2893                 { 0x1f, 0x0005 },
2894                 { 0x05, 0x8332 },
2895                 { 0x06, 0x5561 },
2896
2897                 /*
2898                  * Can not link to 1Gbps with bad cable
2899                  * Decrease SNR threshold form 21.07dB to 19.04dB
2900                  */
2901                 { 0x1f, 0x0001 },
2902                 { 0x17, 0x0cc0 },
2903
2904                 { 0x1f, 0x0000 },
2905                 { 0x0d, 0xf880 }
2906         };
2907
2908         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2909
2910         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2911                 static const struct phy_reg phy_reg_init[] = {
2912                         { 0x1f, 0x0002 },
2913                         { 0x05, 0x669a },
2914                         { 0x1f, 0x0005 },
2915                         { 0x05, 0x8330 },
2916                         { 0x06, 0x669a },
2917
2918                         { 0x1f, 0x0002 }
2919                 };
2920                 int val;
2921
2922                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2923
2924                 val = rtl_readphy(tp, 0x0d);
2925                 if ((val & 0x00ff) != 0x006c) {
2926                         static const u32 set[] = {
2927                                 0x0065, 0x0066, 0x0067, 0x0068,
2928                                 0x0069, 0x006a, 0x006b, 0x006c
2929                         };
2930                         int i;
2931
2932                         rtl_writephy(tp, 0x1f, 0x0002);
2933
2934                         val &= 0xff00;
2935                         for (i = 0; i < ARRAY_SIZE(set); i++)
2936                                 rtl_writephy(tp, 0x0d, val | set[i]);
2937                 }
2938         } else {
2939                 static const struct phy_reg phy_reg_init[] = {
2940                         { 0x1f, 0x0002 },
2941                         { 0x05, 0x2642 },
2942                         { 0x1f, 0x0005 },
2943                         { 0x05, 0x8330 },
2944                         { 0x06, 0x2642 }
2945                 };
2946
2947                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2948         }
2949
2950         /* Fine tune PLL performance */
2951         rtl_writephy(tp, 0x1f, 0x0002);
2952         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2953         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2954
2955         /* Switching regulator Slew rate */
2956         rtl_writephy(tp, 0x1f, 0x0002);
2957         rtl_patchphy(tp, 0x0f, 0x0017);
2958
2959         rtl_writephy(tp, 0x1f, 0x0005);
2960         rtl_writephy(tp, 0x05, 0x001b);
2961
2962         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2963
2964         rtl_writephy(tp, 0x1f, 0x0000);
2965 }
2966
2967 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2968 {
2969         static const struct phy_reg phy_reg_init[] = {
2970                 { 0x1f, 0x0002 },
2971                 { 0x10, 0x0008 },
2972                 { 0x0d, 0x006c },
2973
2974                 { 0x1f, 0x0000 },
2975                 { 0x0d, 0xf880 },
2976
2977                 { 0x1f, 0x0001 },
2978                 { 0x17, 0x0cc0 },
2979
2980                 { 0x1f, 0x0001 },
2981                 { 0x0b, 0xa4d8 },
2982                 { 0x09, 0x281c },
2983                 { 0x07, 0x2883 },
2984                 { 0x0a, 0x6b35 },
2985                 { 0x1d, 0x3da4 },
2986                 { 0x1c, 0xeffd },
2987                 { 0x14, 0x7f52 },
2988                 { 0x18, 0x7fc6 },
2989                 { 0x08, 0x0601 },
2990                 { 0x06, 0x4063 },
2991                 { 0x10, 0xf074 },
2992                 { 0x1f, 0x0003 },
2993                 { 0x13, 0x0789 },
2994                 { 0x12, 0xf4bd },
2995                 { 0x1a, 0x04fd },
2996                 { 0x14, 0x84b0 },
2997                 { 0x1f, 0x0000 },
2998                 { 0x00, 0x9200 },
2999
3000                 { 0x1f, 0x0005 },
3001                 { 0x01, 0x0340 },
3002                 { 0x1f, 0x0001 },
3003                 { 0x04, 0x4000 },
3004                 { 0x03, 0x1d21 },
3005                 { 0x02, 0x0c32 },
3006                 { 0x01, 0x0200 },
3007                 { 0x00, 0x5554 },
3008                 { 0x04, 0x4800 },
3009                 { 0x04, 0x4000 },
3010                 { 0x04, 0xf000 },
3011                 { 0x03, 0xdf01 },
3012                 { 0x02, 0xdf20 },
3013                 { 0x01, 0x101a },
3014                 { 0x00, 0xa0ff },
3015                 { 0x04, 0xf800 },
3016                 { 0x04, 0xf000 },
3017                 { 0x1f, 0x0000 },
3018
3019                 { 0x1f, 0x0007 },
3020                 { 0x1e, 0x0023 },
3021                 { 0x16, 0x0000 },
3022                 { 0x1f, 0x0000 }
3023         };
3024
3025         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3026 }
3027
3028 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3029 {
3030         static const struct phy_reg phy_reg_init[] = {
3031                 { 0x1f, 0x0001 },
3032                 { 0x17, 0x0cc0 },
3033
3034                 { 0x1f, 0x0007 },
3035                 { 0x1e, 0x002d },
3036                 { 0x18, 0x0040 },
3037                 { 0x1f, 0x0000 }
3038         };
3039
3040         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3041         rtl_patchphy(tp, 0x0d, 1 << 5);
3042 }
3043
3044 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3045 {
3046         static const struct phy_reg phy_reg_init[] = {
3047                 /* Enable Delay cap */
3048                 { 0x1f, 0x0005 },
3049                 { 0x05, 0x8b80 },
3050                 { 0x06, 0xc896 },
3051                 { 0x1f, 0x0000 },
3052
3053                 /* Channel estimation fine tune */
3054                 { 0x1f, 0x0001 },
3055                 { 0x0b, 0x6c20 },
3056                 { 0x07, 0x2872 },
3057                 { 0x1c, 0xefff },
3058                 { 0x1f, 0x0003 },
3059                 { 0x14, 0x6420 },
3060                 { 0x1f, 0x0000 },
3061
3062                 /* Update PFM & 10M TX idle timer */
3063                 { 0x1f, 0x0007 },
3064                 { 0x1e, 0x002f },
3065                 { 0x15, 0x1919 },
3066                 { 0x1f, 0x0000 },
3067
3068                 { 0x1f, 0x0007 },
3069                 { 0x1e, 0x00ac },
3070                 { 0x18, 0x0006 },
3071                 { 0x1f, 0x0000 }
3072         };
3073
3074         rtl_apply_firmware(tp);
3075
3076         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3077
3078         /* DCO enable for 10M IDLE Power */
3079         rtl_writephy(tp, 0x1f, 0x0007);
3080         rtl_writephy(tp, 0x1e, 0x0023);
3081         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3082         rtl_writephy(tp, 0x1f, 0x0000);
3083
3084         /* For impedance matching */
3085         rtl_writephy(tp, 0x1f, 0x0002);
3086         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3087         rtl_writephy(tp, 0x1f, 0x0000);
3088
3089         /* PHY auto speed down */
3090         rtl_writephy(tp, 0x1f, 0x0007);
3091         rtl_writephy(tp, 0x1e, 0x002d);
3092         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3093         rtl_writephy(tp, 0x1f, 0x0000);
3094         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3095
3096         rtl_writephy(tp, 0x1f, 0x0005);
3097         rtl_writephy(tp, 0x05, 0x8b86);
3098         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3099         rtl_writephy(tp, 0x1f, 0x0000);
3100
3101         rtl_writephy(tp, 0x1f, 0x0005);
3102         rtl_writephy(tp, 0x05, 0x8b85);
3103         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3104         rtl_writephy(tp, 0x1f, 0x0007);
3105         rtl_writephy(tp, 0x1e, 0x0020);
3106         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3107         rtl_writephy(tp, 0x1f, 0x0006);
3108         rtl_writephy(tp, 0x00, 0x5a00);
3109         rtl_writephy(tp, 0x1f, 0x0000);
3110         rtl_writephy(tp, 0x0d, 0x0007);
3111         rtl_writephy(tp, 0x0e, 0x003c);
3112         rtl_writephy(tp, 0x0d, 0x4007);
3113         rtl_writephy(tp, 0x0e, 0x0000);
3114         rtl_writephy(tp, 0x0d, 0x0000);
3115 }
3116
3117 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3118 {
3119         const u16 w[] = {
3120                 addr[0] | (addr[1] << 8),
3121                 addr[2] | (addr[3] << 8),
3122                 addr[4] | (addr[5] << 8)
3123         };
3124         const struct exgmac_reg e[] = {
3125                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3126                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3127                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3128                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3129         };
3130
3131         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3132 }
3133
3134 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3135 {
3136         static const struct phy_reg phy_reg_init[] = {
3137                 /* Enable Delay cap */
3138                 { 0x1f, 0x0004 },
3139                 { 0x1f, 0x0007 },
3140                 { 0x1e, 0x00ac },
3141                 { 0x18, 0x0006 },
3142                 { 0x1f, 0x0002 },
3143                 { 0x1f, 0x0000 },
3144                 { 0x1f, 0x0000 },
3145
3146                 /* Channel estimation fine tune */
3147                 { 0x1f, 0x0003 },
3148                 { 0x09, 0xa20f },
3149                 { 0x1f, 0x0000 },
3150                 { 0x1f, 0x0000 },
3151
3152                 /* Green Setting */
3153                 { 0x1f, 0x0005 },
3154                 { 0x05, 0x8b5b },
3155                 { 0x06, 0x9222 },
3156                 { 0x05, 0x8b6d },
3157                 { 0x06, 0x8000 },
3158                 { 0x05, 0x8b76 },
3159                 { 0x06, 0x8000 },
3160                 { 0x1f, 0x0000 }
3161         };
3162
3163         rtl_apply_firmware(tp);
3164
3165         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3166
3167         /* For 4-corner performance improve */
3168         rtl_writephy(tp, 0x1f, 0x0005);
3169         rtl_writephy(tp, 0x05, 0x8b80);
3170         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3171         rtl_writephy(tp, 0x1f, 0x0000);
3172
3173         /* PHY auto speed down */
3174         rtl_writephy(tp, 0x1f, 0x0004);
3175         rtl_writephy(tp, 0x1f, 0x0007);
3176         rtl_writephy(tp, 0x1e, 0x002d);
3177         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3178         rtl_writephy(tp, 0x1f, 0x0002);
3179         rtl_writephy(tp, 0x1f, 0x0000);
3180         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3181
3182         /* improve 10M EEE waveform */
3183         rtl_writephy(tp, 0x1f, 0x0005);
3184         rtl_writephy(tp, 0x05, 0x8b86);
3185         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3186         rtl_writephy(tp, 0x1f, 0x0000);
3187
3188         /* Improve 2-pair detection performance */
3189         rtl_writephy(tp, 0x1f, 0x0005);
3190         rtl_writephy(tp, 0x05, 0x8b85);
3191         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3192         rtl_writephy(tp, 0x1f, 0x0000);
3193
3194         /* EEE setting */
3195         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3196         rtl_writephy(tp, 0x1f, 0x0005);
3197         rtl_writephy(tp, 0x05, 0x8b85);
3198         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3199         rtl_writephy(tp, 0x1f, 0x0004);
3200         rtl_writephy(tp, 0x1f, 0x0007);
3201         rtl_writephy(tp, 0x1e, 0x0020);
3202         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3203         rtl_writephy(tp, 0x1f, 0x0002);
3204         rtl_writephy(tp, 0x1f, 0x0000);
3205         rtl_writephy(tp, 0x0d, 0x0007);
3206         rtl_writephy(tp, 0x0e, 0x003c);
3207         rtl_writephy(tp, 0x0d, 0x4007);
3208         rtl_writephy(tp, 0x0e, 0x0000);
3209         rtl_writephy(tp, 0x0d, 0x0000);
3210
3211         /* Green feature */
3212         rtl_writephy(tp, 0x1f, 0x0003);
3213         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3214         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3215         rtl_writephy(tp, 0x1f, 0x0000);
3216
3217         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3218         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3219 }
3220
3221 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3222 {
3223         /* For 4-corner performance improve */
3224         rtl_writephy(tp, 0x1f, 0x0005);
3225         rtl_writephy(tp, 0x05, 0x8b80);
3226         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3227         rtl_writephy(tp, 0x1f, 0x0000);
3228
3229         /* PHY auto speed down */
3230         rtl_writephy(tp, 0x1f, 0x0007);
3231         rtl_writephy(tp, 0x1e, 0x002d);
3232         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3233         rtl_writephy(tp, 0x1f, 0x0000);
3234         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3235
3236         /* Improve 10M EEE waveform */
3237         rtl_writephy(tp, 0x1f, 0x0005);
3238         rtl_writephy(tp, 0x05, 0x8b86);
3239         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3240         rtl_writephy(tp, 0x1f, 0x0000);
3241 }
3242
3243 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3244 {
3245         static const struct phy_reg phy_reg_init[] = {
3246                 /* Channel estimation fine tune */
3247                 { 0x1f, 0x0003 },
3248                 { 0x09, 0xa20f },
3249                 { 0x1f, 0x0000 },
3250
3251                 /* Modify green table for giga & fnet */
3252                 { 0x1f, 0x0005 },
3253                 { 0x05, 0x8b55 },
3254                 { 0x06, 0x0000 },
3255                 { 0x05, 0x8b5e },
3256                 { 0x06, 0x0000 },
3257                 { 0x05, 0x8b67 },
3258                 { 0x06, 0x0000 },
3259                 { 0x05, 0x8b70 },
3260                 { 0x06, 0x0000 },
3261                 { 0x1f, 0x0000 },
3262                 { 0x1f, 0x0007 },
3263                 { 0x1e, 0x0078 },
3264                 { 0x17, 0x0000 },
3265                 { 0x19, 0x00fb },
3266                 { 0x1f, 0x0000 },
3267
3268                 /* Modify green table for 10M */
3269                 { 0x1f, 0x0005 },
3270                 { 0x05, 0x8b79 },
3271                 { 0x06, 0xaa00 },
3272                 { 0x1f, 0x0000 },
3273
3274                 /* Disable hiimpedance detection (RTCT) */
3275                 { 0x1f, 0x0003 },
3276                 { 0x01, 0x328a },
3277                 { 0x1f, 0x0000 }
3278         };
3279
3280         rtl_apply_firmware(tp);
3281
3282         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3283
3284         rtl8168f_hw_phy_config(tp);
3285
3286         /* Improve 2-pair detection performance */
3287         rtl_writephy(tp, 0x1f, 0x0005);
3288         rtl_writephy(tp, 0x05, 0x8b85);
3289         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3290         rtl_writephy(tp, 0x1f, 0x0000);
3291 }
3292
3293 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3294 {
3295         rtl_apply_firmware(tp);
3296
3297         rtl8168f_hw_phy_config(tp);
3298 }
3299
3300 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3301 {
3302         static const struct phy_reg phy_reg_init[] = {
3303                 /* Channel estimation fine tune */
3304                 { 0x1f, 0x0003 },
3305                 { 0x09, 0xa20f },
3306                 { 0x1f, 0x0000 },
3307
3308                 /* Modify green table for giga & fnet */
3309                 { 0x1f, 0x0005 },
3310                 { 0x05, 0x8b55 },
3311                 { 0x06, 0x0000 },
3312                 { 0x05, 0x8b5e },
3313                 { 0x06, 0x0000 },
3314                 { 0x05, 0x8b67 },
3315                 { 0x06, 0x0000 },
3316                 { 0x05, 0x8b70 },
3317                 { 0x06, 0x0000 },
3318                 { 0x1f, 0x0000 },
3319                 { 0x1f, 0x0007 },
3320                 { 0x1e, 0x0078 },
3321                 { 0x17, 0x0000 },
3322                 { 0x19, 0x00aa },
3323                 { 0x1f, 0x0000 },
3324
3325                 /* Modify green table for 10M */
3326                 { 0x1f, 0x0005 },
3327                 { 0x05, 0x8b79 },
3328                 { 0x06, 0xaa00 },
3329                 { 0x1f, 0x0000 },
3330
3331                 /* Disable hiimpedance detection (RTCT) */
3332                 { 0x1f, 0x0003 },
3333                 { 0x01, 0x328a },
3334                 { 0x1f, 0x0000 }
3335         };
3336
3337
3338         rtl_apply_firmware(tp);
3339
3340         rtl8168f_hw_phy_config(tp);
3341
3342         /* Improve 2-pair detection performance */
3343         rtl_writephy(tp, 0x1f, 0x0005);
3344         rtl_writephy(tp, 0x05, 0x8b85);
3345         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3346         rtl_writephy(tp, 0x1f, 0x0000);
3347
3348         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3349
3350         /* Modify green table for giga */
3351         rtl_writephy(tp, 0x1f, 0x0005);
3352         rtl_writephy(tp, 0x05, 0x8b54);
3353         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3354         rtl_writephy(tp, 0x05, 0x8b5d);
3355         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3356         rtl_writephy(tp, 0x05, 0x8a7c);
3357         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3358         rtl_writephy(tp, 0x05, 0x8a7f);
3359         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3360         rtl_writephy(tp, 0x05, 0x8a82);
3361         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3362         rtl_writephy(tp, 0x05, 0x8a85);
3363         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3364         rtl_writephy(tp, 0x05, 0x8a88);
3365         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3366         rtl_writephy(tp, 0x1f, 0x0000);
3367
3368         /* uc same-seed solution */
3369         rtl_writephy(tp, 0x1f, 0x0005);
3370         rtl_writephy(tp, 0x05, 0x8b85);
3371         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3372         rtl_writephy(tp, 0x1f, 0x0000);
3373
3374         /* eee setting */
3375         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3376         rtl_writephy(tp, 0x1f, 0x0005);
3377         rtl_writephy(tp, 0x05, 0x8b85);
3378         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3379         rtl_writephy(tp, 0x1f, 0x0004);
3380         rtl_writephy(tp, 0x1f, 0x0007);
3381         rtl_writephy(tp, 0x1e, 0x0020);
3382         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3383         rtl_writephy(tp, 0x1f, 0x0000);
3384         rtl_writephy(tp, 0x0d, 0x0007);
3385         rtl_writephy(tp, 0x0e, 0x003c);
3386         rtl_writephy(tp, 0x0d, 0x4007);
3387         rtl_writephy(tp, 0x0e, 0x0000);
3388         rtl_writephy(tp, 0x0d, 0x0000);
3389
3390         /* Green feature */
3391         rtl_writephy(tp, 0x1f, 0x0003);
3392         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3393         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3394         rtl_writephy(tp, 0x1f, 0x0000);
3395 }
3396
3397 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3398 {
3399         rtl_apply_firmware(tp);
3400
3401         rtl_writephy(tp, 0x1f, 0x0a46);
3402         if (rtl_readphy(tp, 0x10) & 0x0100) {
3403                 rtl_writephy(tp, 0x1f, 0x0bcc);
3404                 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3405         } else {
3406                 rtl_writephy(tp, 0x1f, 0x0bcc);
3407                 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3408         }
3409
3410         rtl_writephy(tp, 0x1f, 0x0a46);
3411         if (rtl_readphy(tp, 0x13) & 0x0100) {
3412                 rtl_writephy(tp, 0x1f, 0x0c41);
3413                 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3414         } else {
3415                 rtl_writephy(tp, 0x1f, 0x0c41);
3416                 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3417         }
3418
3419         /* Enable PHY auto speed down */
3420         rtl_writephy(tp, 0x1f, 0x0a44);
3421         rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3422
3423         rtl_writephy(tp, 0x1f, 0x0bcc);
3424         rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3425         rtl_writephy(tp, 0x1f, 0x0a44);
3426         rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3427         rtl_writephy(tp, 0x1f, 0x0a43);
3428         rtl_writephy(tp, 0x13, 0x8084);
3429         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3430         rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3431
3432         /* EEE auto-fallback function */
3433         rtl_writephy(tp, 0x1f, 0x0a4b);
3434         rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3435
3436         /* Enable UC LPF tune function */
3437         rtl_writephy(tp, 0x1f, 0x0a43);
3438         rtl_writephy(tp, 0x13, 0x8012);
3439         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3440
3441         rtl_writephy(tp, 0x1f, 0x0c42);
3442         rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3443
3444         /* Improve SWR Efficiency */
3445         rtl_writephy(tp, 0x1f, 0x0bcd);
3446         rtl_writephy(tp, 0x14, 0x5065);
3447         rtl_writephy(tp, 0x14, 0xd065);
3448         rtl_writephy(tp, 0x1f, 0x0bc8);
3449         rtl_writephy(tp, 0x11, 0x5655);
3450         rtl_writephy(tp, 0x1f, 0x0bcd);
3451         rtl_writephy(tp, 0x14, 0x1065);
3452         rtl_writephy(tp, 0x14, 0x9065);
3453         rtl_writephy(tp, 0x14, 0x1065);
3454
3455         /* Check ALDPS bit, disable it if enabled */
3456         rtl_writephy(tp, 0x1f, 0x0a43);
3457         if (rtl_readphy(tp, 0x10) & 0x0004)
3458                 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3459
3460         rtl_writephy(tp, 0x1f, 0x0000);
3461 }
3462
3463 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3464 {
3465         rtl_apply_firmware(tp);
3466 }
3467
3468 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3469 {
3470         static const struct phy_reg phy_reg_init[] = {
3471                 { 0x1f, 0x0003 },
3472                 { 0x08, 0x441d },
3473                 { 0x01, 0x9100 },
3474                 { 0x1f, 0x0000 }
3475         };
3476
3477         rtl_writephy(tp, 0x1f, 0x0000);
3478         rtl_patchphy(tp, 0x11, 1 << 12);
3479         rtl_patchphy(tp, 0x19, 1 << 13);
3480         rtl_patchphy(tp, 0x10, 1 << 15);
3481
3482         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3483 }
3484
3485 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3486 {
3487         static const struct phy_reg phy_reg_init[] = {
3488                 { 0x1f, 0x0005 },
3489                 { 0x1a, 0x0000 },
3490                 { 0x1f, 0x0000 },
3491
3492                 { 0x1f, 0x0004 },
3493                 { 0x1c, 0x0000 },
3494                 { 0x1f, 0x0000 },
3495
3496                 { 0x1f, 0x0001 },
3497                 { 0x15, 0x7701 },
3498                 { 0x1f, 0x0000 }
3499         };
3500
3501         /* Disable ALDPS before ram code */
3502         rtl_writephy(tp, 0x1f, 0x0000);
3503         rtl_writephy(tp, 0x18, 0x0310);
3504         msleep(100);
3505
3506         rtl_apply_firmware(tp);
3507
3508         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3509 }
3510
3511 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3512 {
3513         /* Disable ALDPS before setting firmware */
3514         rtl_writephy(tp, 0x1f, 0x0000);
3515         rtl_writephy(tp, 0x18, 0x0310);
3516         msleep(20);
3517
3518         rtl_apply_firmware(tp);
3519
3520         /* EEE setting */
3521         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3522         rtl_writephy(tp, 0x1f, 0x0004);
3523         rtl_writephy(tp, 0x10, 0x401f);
3524         rtl_writephy(tp, 0x19, 0x7030);
3525         rtl_writephy(tp, 0x1f, 0x0000);
3526 }
3527
3528 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3529 {
3530         static const struct phy_reg phy_reg_init[] = {
3531                 { 0x1f, 0x0004 },
3532                 { 0x10, 0xc07f },
3533                 { 0x19, 0x7030 },
3534                 { 0x1f, 0x0000 }
3535         };
3536
3537         /* Disable ALDPS before ram code */
3538         rtl_writephy(tp, 0x1f, 0x0000);
3539         rtl_writephy(tp, 0x18, 0x0310);
3540         msleep(100);
3541
3542         rtl_apply_firmware(tp);
3543
3544         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3545         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3546
3547         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3548 }
3549
3550 static void rtl_hw_phy_config(struct net_device *dev)
3551 {
3552         struct rtl8169_private *tp = netdev_priv(dev);
3553
3554         rtl8169_print_mac_version(tp);
3555
3556         switch (tp->mac_version) {
3557         case RTL_GIGA_MAC_VER_01:
3558                 break;
3559         case RTL_GIGA_MAC_VER_02:
3560         case RTL_GIGA_MAC_VER_03:
3561                 rtl8169s_hw_phy_config(tp);
3562                 break;
3563         case RTL_GIGA_MAC_VER_04:
3564                 rtl8169sb_hw_phy_config(tp);
3565                 break;
3566         case RTL_GIGA_MAC_VER_05:
3567                 rtl8169scd_hw_phy_config(tp);
3568                 break;
3569         case RTL_GIGA_MAC_VER_06:
3570                 rtl8169sce_hw_phy_config(tp);
3571                 break;
3572         case RTL_GIGA_MAC_VER_07:
3573         case RTL_GIGA_MAC_VER_08:
3574         case RTL_GIGA_MAC_VER_09:
3575                 rtl8102e_hw_phy_config(tp);
3576                 break;
3577         case RTL_GIGA_MAC_VER_11:
3578                 rtl8168bb_hw_phy_config(tp);
3579                 break;
3580         case RTL_GIGA_MAC_VER_12:
3581                 rtl8168bef_hw_phy_config(tp);
3582                 break;
3583         case RTL_GIGA_MAC_VER_17:
3584                 rtl8168bef_hw_phy_config(tp);
3585                 break;
3586         case RTL_GIGA_MAC_VER_18:
3587                 rtl8168cp_1_hw_phy_config(tp);
3588                 break;
3589         case RTL_GIGA_MAC_VER_19:
3590                 rtl8168c_1_hw_phy_config(tp);
3591                 break;
3592         case RTL_GIGA_MAC_VER_20:
3593                 rtl8168c_2_hw_phy_config(tp);
3594                 break;
3595         case RTL_GIGA_MAC_VER_21:
3596                 rtl8168c_3_hw_phy_config(tp);
3597                 break;
3598         case RTL_GIGA_MAC_VER_22:
3599                 rtl8168c_4_hw_phy_config(tp);
3600                 break;
3601         case RTL_GIGA_MAC_VER_23:
3602         case RTL_GIGA_MAC_VER_24:
3603                 rtl8168cp_2_hw_phy_config(tp);
3604                 break;
3605         case RTL_GIGA_MAC_VER_25:
3606                 rtl8168d_1_hw_phy_config(tp);
3607                 break;
3608         case RTL_GIGA_MAC_VER_26:
3609                 rtl8168d_2_hw_phy_config(tp);
3610                 break;
3611         case RTL_GIGA_MAC_VER_27:
3612                 rtl8168d_3_hw_phy_config(tp);
3613                 break;
3614         case RTL_GIGA_MAC_VER_28:
3615                 rtl8168d_4_hw_phy_config(tp);
3616                 break;
3617         case RTL_GIGA_MAC_VER_29:
3618         case RTL_GIGA_MAC_VER_30:
3619                 rtl8105e_hw_phy_config(tp);
3620                 break;
3621         case RTL_GIGA_MAC_VER_31:
3622                 /* None. */
3623                 break;
3624         case RTL_GIGA_MAC_VER_32:
3625         case RTL_GIGA_MAC_VER_33:
3626                 rtl8168e_1_hw_phy_config(tp);
3627                 break;
3628         case RTL_GIGA_MAC_VER_34:
3629                 rtl8168e_2_hw_phy_config(tp);
3630                 break;
3631         case RTL_GIGA_MAC_VER_35:
3632                 rtl8168f_1_hw_phy_config(tp);
3633                 break;
3634         case RTL_GIGA_MAC_VER_36:
3635                 rtl8168f_2_hw_phy_config(tp);
3636                 break;
3637
3638         case RTL_GIGA_MAC_VER_37:
3639                 rtl8402_hw_phy_config(tp);
3640                 break;
3641
3642         case RTL_GIGA_MAC_VER_38:
3643                 rtl8411_hw_phy_config(tp);
3644                 break;
3645
3646         case RTL_GIGA_MAC_VER_39:
3647                 rtl8106e_hw_phy_config(tp);
3648                 break;
3649
3650         case RTL_GIGA_MAC_VER_40:
3651                 rtl8168g_1_hw_phy_config(tp);
3652                 break;
3653         case RTL_GIGA_MAC_VER_42:
3654         case RTL_GIGA_MAC_VER_43:
3655         case RTL_GIGA_MAC_VER_44:
3656                 rtl8168g_2_hw_phy_config(tp);
3657                 break;
3658
3659         case RTL_GIGA_MAC_VER_41:
3660         default:
3661                 break;
3662         }
3663 }
3664
3665 static void rtl_phy_work(struct rtl8169_private *tp)
3666 {
3667         struct timer_list *timer = &tp->timer;
3668         void __iomem *ioaddr = tp->mmio_addr;
3669         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3670
3671         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3672
3673         if (tp->phy_reset_pending(tp)) {
3674                 /*
3675                  * A busy loop could burn quite a few cycles on nowadays CPU.
3676                  * Let's delay the execution of the timer for a few ticks.
3677                  */
3678                 timeout = HZ/10;
3679                 goto out_mod_timer;
3680         }
3681
3682         if (tp->link_ok(ioaddr))
3683                 return;
3684
3685         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
3686
3687         tp->phy_reset_enable(tp);
3688
3689 out_mod_timer:
3690         mod_timer(timer, jiffies + timeout);
3691 }
3692
3693 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3694 {
3695         if (!test_and_set_bit(flag, tp->wk.flags))
3696                 schedule_work(&tp->wk.work);
3697 }
3698
3699 static void rtl8169_phy_timer(unsigned long __opaque)
3700 {
3701         struct net_device *dev = (struct net_device *)__opaque;
3702         struct rtl8169_private *tp = netdev_priv(dev);
3703
3704         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3705 }
3706
3707 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3708                                   void __iomem *ioaddr)
3709 {
3710         iounmap(ioaddr);
3711         pci_release_regions(pdev);
3712         pci_clear_mwi(pdev);
3713         pci_disable_device(pdev);
3714         free_netdev(dev);
3715 }
3716
3717 DECLARE_RTL_COND(rtl_phy_reset_cond)
3718 {
3719         return tp->phy_reset_pending(tp);
3720 }
3721
3722 static void rtl8169_phy_reset(struct net_device *dev,
3723                               struct rtl8169_private *tp)
3724 {
3725         tp->phy_reset_enable(tp);
3726         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3727 }
3728
3729 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3730 {
3731         void __iomem *ioaddr = tp->mmio_addr;
3732
3733         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3734             (RTL_R8(PHYstatus) & TBI_Enable);
3735 }
3736
3737 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3738 {
3739         void __iomem *ioaddr = tp->mmio_addr;
3740
3741         rtl_hw_phy_config(dev);
3742
3743         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3744                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3745                 RTL_W8(0x82, 0x01);
3746         }
3747
3748         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3749
3750         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3751                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3752
3753         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3754                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3755                 RTL_W8(0x82, 0x01);
3756                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3757                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3758         }
3759
3760         rtl8169_phy_reset(dev, tp);
3761
3762         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3763                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3764                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3765                           (tp->mii.supports_gmii ?
3766                            ADVERTISED_1000baseT_Half |
3767                            ADVERTISED_1000baseT_Full : 0));
3768
3769         if (rtl_tbi_enabled(tp))
3770                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3771 }
3772
3773 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3774 {
3775         void __iomem *ioaddr = tp->mmio_addr;
3776
3777         rtl_lock_work(tp);
3778
3779         RTL_W8(Cfg9346, Cfg9346_Unlock);
3780
3781         RTL_W32(MAC4, addr[4] | addr[5] << 8);
3782         RTL_R32(MAC4);
3783
3784         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3785         RTL_R32(MAC0);
3786
3787         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3788                 rtl_rar_exgmac_set(tp, addr);
3789
3790         RTL_W8(Cfg9346, Cfg9346_Lock);
3791
3792         rtl_unlock_work(tp);
3793 }
3794
3795 static int rtl_set_mac_address(struct net_device *dev, void *p)
3796 {
3797         struct rtl8169_private *tp = netdev_priv(dev);
3798         struct sockaddr *addr = p;
3799
3800         if (!is_valid_ether_addr(addr->sa_data))
3801                 return -EADDRNOTAVAIL;
3802
3803         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3804
3805         rtl_rar_set(tp, dev->dev_addr);
3806
3807         return 0;
3808 }
3809
3810 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3811 {
3812         struct rtl8169_private *tp = netdev_priv(dev);
3813         struct mii_ioctl_data *data = if_mii(ifr);
3814
3815         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3816 }
3817
3818 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3819                           struct mii_ioctl_data *data, int cmd)
3820 {
3821         switch (cmd) {
3822         case SIOCGMIIPHY:
3823                 data->phy_id = 32; /* Internal PHY */
3824                 return 0;
3825
3826         case SIOCGMIIREG:
3827                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3828                 return 0;
3829
3830         case SIOCSMIIREG:
3831                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3832                 return 0;
3833         }
3834         return -EOPNOTSUPP;
3835 }
3836
3837 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3838 {
3839         return -EOPNOTSUPP;
3840 }
3841
3842 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3843 {
3844         if (tp->features & RTL_FEATURE_MSI) {
3845                 pci_disable_msi(pdev);
3846                 tp->features &= ~RTL_FEATURE_MSI;
3847         }
3848 }
3849
3850 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3851 {
3852         struct mdio_ops *ops = &tp->mdio_ops;
3853
3854         switch (tp->mac_version) {
3855         case RTL_GIGA_MAC_VER_27:
3856                 ops->write      = r8168dp_1_mdio_write;
3857                 ops->read       = r8168dp_1_mdio_read;
3858                 break;
3859         case RTL_GIGA_MAC_VER_28:
3860         case RTL_GIGA_MAC_VER_31:
3861                 ops->write      = r8168dp_2_mdio_write;
3862                 ops->read       = r8168dp_2_mdio_read;
3863                 break;
3864         case RTL_GIGA_MAC_VER_40:
3865         case RTL_GIGA_MAC_VER_41:
3866         case RTL_GIGA_MAC_VER_42:
3867         case RTL_GIGA_MAC_VER_43:
3868         case RTL_GIGA_MAC_VER_44:
3869                 ops->write      = r8168g_mdio_write;
3870                 ops->read       = r8168g_mdio_read;
3871                 break;
3872         default:
3873                 ops->write      = r8169_mdio_write;
3874                 ops->read       = r8169_mdio_read;
3875                 break;
3876         }
3877 }
3878
3879 static void rtl_speed_down(struct rtl8169_private *tp)
3880 {
3881         u32 adv;
3882         int lpa;
3883
3884         rtl_writephy(tp, 0x1f, 0x0000);
3885         lpa = rtl_readphy(tp, MII_LPA);
3886
3887         if (lpa & (LPA_10HALF | LPA_10FULL))
3888                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3889         else if (lpa & (LPA_100HALF | LPA_100FULL))
3890                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3891                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3892         else
3893                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3894                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3895                       (tp->mii.supports_gmii ?
3896                        ADVERTISED_1000baseT_Half |
3897                        ADVERTISED_1000baseT_Full : 0);
3898
3899         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3900                           adv);
3901 }
3902
3903 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3904 {
3905         void __iomem *ioaddr = tp->mmio_addr;
3906
3907         switch (tp->mac_version) {
3908         case RTL_GIGA_MAC_VER_25:
3909         case RTL_GIGA_MAC_VER_26:
3910         case RTL_GIGA_MAC_VER_29:
3911         case RTL_GIGA_MAC_VER_30:
3912         case RTL_GIGA_MAC_VER_32:
3913         case RTL_GIGA_MAC_VER_33:
3914         case RTL_GIGA_MAC_VER_34:
3915         case RTL_GIGA_MAC_VER_37:
3916         case RTL_GIGA_MAC_VER_38:
3917         case RTL_GIGA_MAC_VER_39:
3918         case RTL_GIGA_MAC_VER_40:
3919         case RTL_GIGA_MAC_VER_41:
3920         case RTL_GIGA_MAC_VER_42:
3921         case RTL_GIGA_MAC_VER_43:
3922         case RTL_GIGA_MAC_VER_44:
3923                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3924                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3925                 break;
3926         default:
3927                 break;
3928         }
3929 }
3930
3931 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3932 {
3933         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3934                 return false;
3935
3936         rtl_speed_down(tp);
3937         rtl_wol_suspend_quirk(tp);
3938
3939         return true;
3940 }
3941
3942 static void r810x_phy_power_down(struct rtl8169_private *tp)
3943 {
3944         rtl_writephy(tp, 0x1f, 0x0000);
3945         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3946 }
3947
3948 static void r810x_phy_power_up(struct rtl8169_private *tp)
3949 {
3950         rtl_writephy(tp, 0x1f, 0x0000);
3951         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3952 }
3953
3954 static void r810x_pll_power_down(struct rtl8169_private *tp)
3955 {
3956         void __iomem *ioaddr = tp->mmio_addr;
3957
3958         if (rtl_wol_pll_power_down(tp))
3959                 return;
3960
3961         r810x_phy_power_down(tp);
3962
3963         switch (tp->mac_version) {
3964         case RTL_GIGA_MAC_VER_07:
3965         case RTL_GIGA_MAC_VER_08:
3966         case RTL_GIGA_MAC_VER_09:
3967         case RTL_GIGA_MAC_VER_10:
3968         case RTL_GIGA_MAC_VER_13:
3969         case RTL_GIGA_MAC_VER_16:
3970                 break;
3971         default:
3972                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3973                 break;
3974         }
3975 }
3976
3977 static void r810x_pll_power_up(struct rtl8169_private *tp)
3978 {
3979         void __iomem *ioaddr = tp->mmio_addr;
3980
3981         r810x_phy_power_up(tp);
3982
3983         switch (tp->mac_version) {
3984         case RTL_GIGA_MAC_VER_07:
3985         case RTL_GIGA_MAC_VER_08:
3986         case RTL_GIGA_MAC_VER_09:
3987         case RTL_GIGA_MAC_VER_10:
3988         case RTL_GIGA_MAC_VER_13:
3989         case RTL_GIGA_MAC_VER_16:
3990                 break;
3991         default:
3992                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3993                 break;
3994         }
3995 }
3996
3997 static void r8168_phy_power_up(struct rtl8169_private *tp)
3998 {
3999         rtl_writephy(tp, 0x1f, 0x0000);
4000         switch (tp->mac_version) {
4001         case RTL_GIGA_MAC_VER_11:
4002         case RTL_GIGA_MAC_VER_12:
4003         case RTL_GIGA_MAC_VER_17:
4004         case RTL_GIGA_MAC_VER_18:
4005         case RTL_GIGA_MAC_VER_19:
4006         case RTL_GIGA_MAC_VER_20:
4007         case RTL_GIGA_MAC_VER_21:
4008         case RTL_GIGA_MAC_VER_22:
4009         case RTL_GIGA_MAC_VER_23:
4010         case RTL_GIGA_MAC_VER_24:
4011         case RTL_GIGA_MAC_VER_25:
4012         case RTL_GIGA_MAC_VER_26:
4013         case RTL_GIGA_MAC_VER_27:
4014         case RTL_GIGA_MAC_VER_28:
4015         case RTL_GIGA_MAC_VER_31:
4016                 rtl_writephy(tp, 0x0e, 0x0000);
4017                 break;
4018         default:
4019                 break;
4020         }
4021         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4022 }
4023
4024 static void r8168_phy_power_down(struct rtl8169_private *tp)
4025 {
4026         rtl_writephy(tp, 0x1f, 0x0000);
4027         switch (tp->mac_version) {
4028         case RTL_GIGA_MAC_VER_32:
4029         case RTL_GIGA_MAC_VER_33:
4030         case RTL_GIGA_MAC_VER_40:
4031         case RTL_GIGA_MAC_VER_41:
4032                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4033                 break;
4034
4035         case RTL_GIGA_MAC_VER_11:
4036         case RTL_GIGA_MAC_VER_12:
4037         case RTL_GIGA_MAC_VER_17:
4038         case RTL_GIGA_MAC_VER_18:
4039         case RTL_GIGA_MAC_VER_19:
4040         case RTL_GIGA_MAC_VER_20:
4041         case RTL_GIGA_MAC_VER_21:
4042         case RTL_GIGA_MAC_VER_22:
4043         case RTL_GIGA_MAC_VER_23:
4044         case RTL_GIGA_MAC_VER_24:
4045         case RTL_GIGA_MAC_VER_25:
4046         case RTL_GIGA_MAC_VER_26:
4047         case RTL_GIGA_MAC_VER_27:
4048         case RTL_GIGA_MAC_VER_28:
4049         case RTL_GIGA_MAC_VER_31:
4050                 rtl_writephy(tp, 0x0e, 0x0200);
4051         default:
4052                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4053                 break;
4054         }
4055 }
4056
4057 static void r8168_pll_power_down(struct rtl8169_private *tp)
4058 {
4059         void __iomem *ioaddr = tp->mmio_addr;
4060
4061         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4062              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4063              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4064             r8168dp_check_dash(tp)) {
4065                 return;
4066         }
4067
4068         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4069              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4070             (RTL_R16(CPlusCmd) & ASF)) {
4071                 return;
4072         }
4073
4074         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4075             tp->mac_version == RTL_GIGA_MAC_VER_33)
4076                 rtl_ephy_write(tp, 0x19, 0xff64);
4077
4078         if (rtl_wol_pll_power_down(tp))
4079                 return;
4080
4081         r8168_phy_power_down(tp);
4082
4083         switch (tp->mac_version) {
4084         case RTL_GIGA_MAC_VER_25:
4085         case RTL_GIGA_MAC_VER_26:
4086         case RTL_GIGA_MAC_VER_27:
4087         case RTL_GIGA_MAC_VER_28:
4088         case RTL_GIGA_MAC_VER_31:
4089         case RTL_GIGA_MAC_VER_32:
4090         case RTL_GIGA_MAC_VER_33:
4091                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4092                 break;
4093         case RTL_GIGA_MAC_VER_40:
4094         case RTL_GIGA_MAC_VER_41:
4095                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4096                              0xfc000000, ERIAR_EXGMAC);
4097                 break;
4098         }
4099 }
4100
4101 static void r8168_pll_power_up(struct rtl8169_private *tp)
4102 {
4103         void __iomem *ioaddr = tp->mmio_addr;
4104
4105         switch (tp->mac_version) {
4106         case RTL_GIGA_MAC_VER_25:
4107         case RTL_GIGA_MAC_VER_26:
4108         case RTL_GIGA_MAC_VER_27:
4109         case RTL_GIGA_MAC_VER_28:
4110         case RTL_GIGA_MAC_VER_31:
4111         case RTL_GIGA_MAC_VER_32:
4112         case RTL_GIGA_MAC_VER_33:
4113                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4114                 break;
4115         case RTL_GIGA_MAC_VER_40:
4116         case RTL_GIGA_MAC_VER_41:
4117                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4118                              0x00000000, ERIAR_EXGMAC);
4119                 break;
4120         }
4121
4122         r8168_phy_power_up(tp);
4123 }
4124
4125 static void rtl_generic_op(struct rtl8169_private *tp,
4126                            void (*op)(struct rtl8169_private *))
4127 {
4128         if (op)
4129                 op(tp);
4130 }
4131
4132 static void rtl_pll_power_down(struct rtl8169_private *tp)
4133 {
4134         rtl_generic_op(tp, tp->pll_power_ops.down);
4135 }
4136
4137 static void rtl_pll_power_up(struct rtl8169_private *tp)
4138 {
4139         rtl_generic_op(tp, tp->pll_power_ops.up);
4140 }
4141
4142 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4143 {
4144         struct pll_power_ops *ops = &tp->pll_power_ops;
4145
4146         switch (tp->mac_version) {
4147         case RTL_GIGA_MAC_VER_07:
4148         case RTL_GIGA_MAC_VER_08:
4149         case RTL_GIGA_MAC_VER_09:
4150         case RTL_GIGA_MAC_VER_10:
4151         case RTL_GIGA_MAC_VER_16:
4152         case RTL_GIGA_MAC_VER_29:
4153         case RTL_GIGA_MAC_VER_30:
4154         case RTL_GIGA_MAC_VER_37:
4155         case RTL_GIGA_MAC_VER_39:
4156         case RTL_GIGA_MAC_VER_43:
4157                 ops->down       = r810x_pll_power_down;
4158                 ops->up         = r810x_pll_power_up;
4159                 break;
4160
4161         case RTL_GIGA_MAC_VER_11:
4162         case RTL_GIGA_MAC_VER_12:
4163         case RTL_GIGA_MAC_VER_17:
4164         case RTL_GIGA_MAC_VER_18:
4165         case RTL_GIGA_MAC_VER_19:
4166         case RTL_GIGA_MAC_VER_20:
4167         case RTL_GIGA_MAC_VER_21:
4168         case RTL_GIGA_MAC_VER_22:
4169         case RTL_GIGA_MAC_VER_23:
4170         case RTL_GIGA_MAC_VER_24:
4171         case RTL_GIGA_MAC_VER_25:
4172         case RTL_GIGA_MAC_VER_26:
4173         case RTL_GIGA_MAC_VER_27:
4174         case RTL_GIGA_MAC_VER_28:
4175         case RTL_GIGA_MAC_VER_31:
4176         case RTL_GIGA_MAC_VER_32:
4177         case RTL_GIGA_MAC_VER_33:
4178         case RTL_GIGA_MAC_VER_34:
4179         case RTL_GIGA_MAC_VER_35:
4180         case RTL_GIGA_MAC_VER_36:
4181         case RTL_GIGA_MAC_VER_38:
4182         case RTL_GIGA_MAC_VER_40:
4183         case RTL_GIGA_MAC_VER_41:
4184         case RTL_GIGA_MAC_VER_42:
4185         case RTL_GIGA_MAC_VER_44:
4186                 ops->down       = r8168_pll_power_down;
4187                 ops->up         = r8168_pll_power_up;
4188                 break;
4189
4190         default:
4191                 ops->down       = NULL;
4192                 ops->up         = NULL;
4193                 break;
4194         }
4195 }
4196
4197 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4198 {
4199         void __iomem *ioaddr = tp->mmio_addr;
4200
4201         switch (tp->mac_version) {
4202         case RTL_GIGA_MAC_VER_01:
4203         case RTL_GIGA_MAC_VER_02:
4204         case RTL_GIGA_MAC_VER_03:
4205         case RTL_GIGA_MAC_VER_04:
4206         case RTL_GIGA_MAC_VER_05:
4207         case RTL_GIGA_MAC_VER_06:
4208         case RTL_GIGA_MAC_VER_10:
4209         case RTL_GIGA_MAC_VER_11:
4210         case RTL_GIGA_MAC_VER_12:
4211         case RTL_GIGA_MAC_VER_13:
4212         case RTL_GIGA_MAC_VER_14:
4213         case RTL_GIGA_MAC_VER_15:
4214         case RTL_GIGA_MAC_VER_16:
4215         case RTL_GIGA_MAC_VER_17:
4216                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4217                 break;
4218         case RTL_GIGA_MAC_VER_18:
4219         case RTL_GIGA_MAC_VER_19:
4220         case RTL_GIGA_MAC_VER_20:
4221         case RTL_GIGA_MAC_VER_21:
4222         case RTL_GIGA_MAC_VER_22:
4223         case RTL_GIGA_MAC_VER_23:
4224         case RTL_GIGA_MAC_VER_24:
4225         case RTL_GIGA_MAC_VER_34:
4226         case RTL_GIGA_MAC_VER_35:
4227                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4228                 break;
4229         case RTL_GIGA_MAC_VER_40:
4230                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4231                 break;
4232         case RTL_GIGA_MAC_VER_41:
4233         case RTL_GIGA_MAC_VER_42:
4234         case RTL_GIGA_MAC_VER_43:
4235         case RTL_GIGA_MAC_VER_44:
4236                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4237                 break;
4238         default:
4239                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4240                 break;
4241         }
4242 }
4243
4244 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4245 {
4246         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4247 }
4248
4249 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4250 {
4251         void __iomem *ioaddr = tp->mmio_addr;
4252
4253         RTL_W8(Cfg9346, Cfg9346_Unlock);
4254         rtl_generic_op(tp, tp->jumbo_ops.enable);
4255         RTL_W8(Cfg9346, Cfg9346_Lock);
4256 }
4257
4258 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4259 {
4260         void __iomem *ioaddr = tp->mmio_addr;
4261
4262         RTL_W8(Cfg9346, Cfg9346_Unlock);
4263         rtl_generic_op(tp, tp->jumbo_ops.disable);
4264         RTL_W8(Cfg9346, Cfg9346_Lock);
4265 }
4266
4267 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4268 {
4269         void __iomem *ioaddr = tp->mmio_addr;
4270
4271         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4272         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4273         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4274 }
4275
4276 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4277 {
4278         void __iomem *ioaddr = tp->mmio_addr;
4279
4280         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4281         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4282         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4283 }
4284
4285 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4286 {
4287         void __iomem *ioaddr = tp->mmio_addr;
4288
4289         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4290 }
4291
4292 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4293 {
4294         void __iomem *ioaddr = tp->mmio_addr;
4295
4296         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4297 }
4298
4299 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4300 {
4301         void __iomem *ioaddr = tp->mmio_addr;
4302
4303         RTL_W8(MaxTxPacketSize, 0x3f);
4304         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4305         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4306         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4307 }
4308
4309 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4310 {
4311         void __iomem *ioaddr = tp->mmio_addr;
4312
4313         RTL_W8(MaxTxPacketSize, 0x0c);
4314         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4315         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4316         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4317 }
4318
4319 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4320 {
4321         rtl_tx_performance_tweak(tp->pci_dev,
4322                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4323 }
4324
4325 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4326 {
4327         rtl_tx_performance_tweak(tp->pci_dev,
4328                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4329 }
4330
4331 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4332 {
4333         void __iomem *ioaddr = tp->mmio_addr;
4334
4335         r8168b_0_hw_jumbo_enable(tp);
4336
4337         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4338 }
4339
4340 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4341 {
4342         void __iomem *ioaddr = tp->mmio_addr;
4343
4344         r8168b_0_hw_jumbo_disable(tp);
4345
4346         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4347 }
4348
4349 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4350 {
4351         struct jumbo_ops *ops = &tp->jumbo_ops;
4352
4353         switch (tp->mac_version) {
4354         case RTL_GIGA_MAC_VER_11:
4355                 ops->disable    = r8168b_0_hw_jumbo_disable;
4356                 ops->enable     = r8168b_0_hw_jumbo_enable;
4357                 break;
4358         case RTL_GIGA_MAC_VER_12:
4359         case RTL_GIGA_MAC_VER_17:
4360                 ops->disable    = r8168b_1_hw_jumbo_disable;
4361                 ops->enable     = r8168b_1_hw_jumbo_enable;
4362                 break;
4363         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4364         case RTL_GIGA_MAC_VER_19:
4365         case RTL_GIGA_MAC_VER_20:
4366         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4367         case RTL_GIGA_MAC_VER_22:
4368         case RTL_GIGA_MAC_VER_23:
4369         case RTL_GIGA_MAC_VER_24:
4370         case RTL_GIGA_MAC_VER_25:
4371         case RTL_GIGA_MAC_VER_26:
4372                 ops->disable    = r8168c_hw_jumbo_disable;
4373                 ops->enable     = r8168c_hw_jumbo_enable;
4374                 break;
4375         case RTL_GIGA_MAC_VER_27:
4376         case RTL_GIGA_MAC_VER_28:
4377                 ops->disable    = r8168dp_hw_jumbo_disable;
4378                 ops->enable     = r8168dp_hw_jumbo_enable;
4379                 break;
4380         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4381         case RTL_GIGA_MAC_VER_32:
4382         case RTL_GIGA_MAC_VER_33:
4383         case RTL_GIGA_MAC_VER_34:
4384                 ops->disable    = r8168e_hw_jumbo_disable;
4385                 ops->enable     = r8168e_hw_jumbo_enable;
4386                 break;
4387
4388         /*
4389          * No action needed for jumbo frames with 8169.
4390          * No jumbo for 810x at all.
4391          */
4392         case RTL_GIGA_MAC_VER_40:
4393         case RTL_GIGA_MAC_VER_41:
4394         case RTL_GIGA_MAC_VER_42:
4395         case RTL_GIGA_MAC_VER_43:
4396         case RTL_GIGA_MAC_VER_44:
4397         default:
4398                 ops->disable    = NULL;
4399                 ops->enable     = NULL;
4400                 break;
4401         }
4402 }
4403
4404 DECLARE_RTL_COND(rtl_chipcmd_cond)
4405 {
4406         void __iomem *ioaddr = tp->mmio_addr;
4407
4408         return RTL_R8(ChipCmd) & CmdReset;
4409 }
4410
4411 static void rtl_hw_reset(struct rtl8169_private *tp)
4412 {
4413         void __iomem *ioaddr = tp->mmio_addr;
4414
4415         RTL_W8(ChipCmd, CmdReset);
4416
4417         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4418 }
4419
4420 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4421 {
4422         struct rtl_fw *rtl_fw;
4423         const char *name;
4424         int rc = -ENOMEM;
4425
4426         name = rtl_lookup_firmware_name(tp);
4427         if (!name)
4428                 goto out_no_firmware;
4429
4430         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4431         if (!rtl_fw)
4432                 goto err_warn;
4433
4434         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4435         if (rc < 0)
4436                 goto err_free;
4437
4438         rc = rtl_check_firmware(tp, rtl_fw);
4439         if (rc < 0)
4440                 goto err_release_firmware;
4441
4442         tp->rtl_fw = rtl_fw;
4443 out:
4444         return;
4445
4446 err_release_firmware:
4447         release_firmware(rtl_fw->fw);
4448 err_free:
4449         kfree(rtl_fw);
4450 err_warn:
4451         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4452                    name, rc);
4453 out_no_firmware:
4454         tp->rtl_fw = NULL;
4455         goto out;
4456 }
4457
4458 static void rtl_request_firmware(struct rtl8169_private *tp)
4459 {
4460         if (IS_ERR(tp->rtl_fw))
4461                 rtl_request_uncached_firmware(tp);
4462 }
4463
4464 static void rtl_rx_close(struct rtl8169_private *tp)
4465 {
4466         void __iomem *ioaddr = tp->mmio_addr;
4467
4468         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4469 }
4470
4471 DECLARE_RTL_COND(rtl_npq_cond)
4472 {
4473         void __iomem *ioaddr = tp->mmio_addr;
4474
4475         return RTL_R8(TxPoll) & NPQ;
4476 }
4477
4478 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4479 {
4480         void __iomem *ioaddr = tp->mmio_addr;
4481
4482         return RTL_R32(TxConfig) & TXCFG_EMPTY;
4483 }
4484
4485 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4486 {
4487         void __iomem *ioaddr = tp->mmio_addr;
4488
4489         /* Disable interrupts */
4490         rtl8169_irq_mask_and_ack(tp);
4491
4492         rtl_rx_close(tp);
4493
4494         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4495             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4496             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4497                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4498         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4499                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4500                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4501                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4502                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4503                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4504                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4505                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4506                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4507                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4508                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4509                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4510         } else {
4511                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4512                 udelay(100);
4513         }
4514
4515         rtl_hw_reset(tp);
4516 }
4517
4518 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4519 {
4520         void __iomem *ioaddr = tp->mmio_addr;
4521
4522         /* Set DMA burst size and Interframe Gap Time */
4523         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4524                 (InterFrameGap << TxInterFrameGapShift));
4525 }
4526
4527 static void rtl_hw_start(struct net_device *dev)
4528 {
4529         struct rtl8169_private *tp = netdev_priv(dev);
4530
4531         tp->hw_start(dev);
4532
4533         rtl_irq_enable_all(tp);
4534 }
4535
4536 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4537                                          void __iomem *ioaddr)
4538 {
4539         /*
4540          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4541          * register to be written before TxDescAddrLow to work.
4542          * Switching from MMIO to I/O access fixes the issue as well.
4543          */
4544         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4545         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4546         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4547         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4548 }
4549
4550 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4551 {
4552         u16 cmd;
4553
4554         cmd = RTL_R16(CPlusCmd);
4555         RTL_W16(CPlusCmd, cmd);
4556         return cmd;
4557 }
4558
4559 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4560 {
4561         /* Low hurts. Let's disable the filtering. */
4562         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4563 }
4564
4565 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4566 {
4567         static const struct rtl_cfg2_info {
4568                 u32 mac_version;
4569                 u32 clk;
4570                 u32 val;
4571         } cfg2_info [] = {
4572                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4573                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4574                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4575                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4576         };
4577         const struct rtl_cfg2_info *p = cfg2_info;
4578         unsigned int i;
4579         u32 clk;
4580
4581         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4582         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4583                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4584                         RTL_W32(0x7c, p->val);
4585                         break;
4586                 }
4587         }
4588 }
4589
4590 static void rtl_set_rx_mode(struct net_device *dev)
4591 {
4592         struct rtl8169_private *tp = netdev_priv(dev);
4593         void __iomem *ioaddr = tp->mmio_addr;
4594         u32 mc_filter[2];       /* Multicast hash filter */
4595         int rx_mode;
4596         u32 tmp = 0;
4597
4598         if (dev->flags & IFF_PROMISC) {
4599                 /* Unconditionally log net taps. */
4600                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4601                 rx_mode =
4602                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4603                     AcceptAllPhys;
4604                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4605         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4606                    (dev->flags & IFF_ALLMULTI)) {
4607                 /* Too many to filter perfectly -- accept all multicasts. */
4608                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4609                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4610         } else {
4611                 struct netdev_hw_addr *ha;
4612
4613                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4614                 mc_filter[1] = mc_filter[0] = 0;
4615                 netdev_for_each_mc_addr(ha, dev) {
4616                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4617                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4618                         rx_mode |= AcceptMulticast;
4619                 }
4620         }
4621
4622         if (dev->features & NETIF_F_RXALL)
4623                 rx_mode |= (AcceptErr | AcceptRunt);
4624
4625         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4626
4627         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4628                 u32 data = mc_filter[0];
4629
4630                 mc_filter[0] = swab32(mc_filter[1]);
4631                 mc_filter[1] = swab32(data);
4632         }
4633
4634         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4635                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4636
4637         RTL_W32(MAR0 + 4, mc_filter[1]);
4638         RTL_W32(MAR0 + 0, mc_filter[0]);
4639
4640         RTL_W32(RxConfig, tmp);
4641 }
4642
4643 static void rtl_hw_start_8169(struct net_device *dev)
4644 {
4645         struct rtl8169_private *tp = netdev_priv(dev);
4646         void __iomem *ioaddr = tp->mmio_addr;
4647         struct pci_dev *pdev = tp->pci_dev;
4648
4649         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4650                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4651                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4652         }
4653
4654         RTL_W8(Cfg9346, Cfg9346_Unlock);
4655         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4656             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4657             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4658             tp->mac_version == RTL_GIGA_MAC_VER_04)
4659                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4660
4661         rtl_init_rxcfg(tp);
4662
4663         RTL_W8(EarlyTxThres, NoEarlyTx);
4664
4665         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4666
4667         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4668             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4669             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4670             tp->mac_version == RTL_GIGA_MAC_VER_04)
4671                 rtl_set_rx_tx_config_registers(tp);
4672
4673         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4674
4675         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4676             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4677                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4678                         "Bit-3 and bit-14 MUST be 1\n");
4679                 tp->cp_cmd |= (1 << 14);
4680         }
4681
4682         RTL_W16(CPlusCmd, tp->cp_cmd);
4683
4684         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4685
4686         /*
4687          * Undocumented corner. Supposedly:
4688          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4689          */
4690         RTL_W16(IntrMitigate, 0x0000);
4691
4692         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4693
4694         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4695             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4696             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4697             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4698                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4699                 rtl_set_rx_tx_config_registers(tp);
4700         }
4701
4702         RTL_W8(Cfg9346, Cfg9346_Lock);
4703
4704         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4705         RTL_R8(IntrMask);
4706
4707         RTL_W32(RxMissed, 0);
4708
4709         rtl_set_rx_mode(dev);
4710
4711         /* no early-rx interrupts */
4712         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4713 }
4714
4715 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4716 {
4717         if (tp->csi_ops.write)
4718                 tp->csi_ops.write(tp, addr, value);
4719 }
4720
4721 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4722 {
4723         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4724 }
4725
4726 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4727 {
4728         u32 csi;
4729
4730         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4731         rtl_csi_write(tp, 0x070c, csi | bits);
4732 }
4733
4734 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4735 {
4736         rtl_csi_access_enable(tp, 0x17000000);
4737 }
4738
4739 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4740 {
4741         rtl_csi_access_enable(tp, 0x27000000);
4742 }
4743
4744 DECLARE_RTL_COND(rtl_csiar_cond)
4745 {
4746         void __iomem *ioaddr = tp->mmio_addr;
4747
4748         return RTL_R32(CSIAR) & CSIAR_FLAG;
4749 }
4750
4751 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4752 {
4753         void __iomem *ioaddr = tp->mmio_addr;
4754
4755         RTL_W32(CSIDR, value);
4756         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4757                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4758
4759         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4760 }
4761
4762 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4763 {
4764         void __iomem *ioaddr = tp->mmio_addr;
4765
4766         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4767                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4768
4769         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4770                 RTL_R32(CSIDR) : ~0;
4771 }
4772
4773 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4774 {
4775         void __iomem *ioaddr = tp->mmio_addr;
4776
4777         RTL_W32(CSIDR, value);
4778         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4779                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4780                 CSIAR_FUNC_NIC);
4781
4782         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4783 }
4784
4785 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4786 {
4787         void __iomem *ioaddr = tp->mmio_addr;
4788
4789         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4790                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4791
4792         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4793                 RTL_R32(CSIDR) : ~0;
4794 }
4795
4796 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
4797 {
4798         void __iomem *ioaddr = tp->mmio_addr;
4799
4800         RTL_W32(CSIDR, value);
4801         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4802                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4803                 CSIAR_FUNC_NIC2);
4804
4805         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4806 }
4807
4808 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
4809 {
4810         void __iomem *ioaddr = tp->mmio_addr;
4811
4812         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
4813                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4814
4815         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4816                 RTL_R32(CSIDR) : ~0;
4817 }
4818
4819 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4820 {
4821         struct csi_ops *ops = &tp->csi_ops;
4822
4823         switch (tp->mac_version) {
4824         case RTL_GIGA_MAC_VER_01:
4825         case RTL_GIGA_MAC_VER_02:
4826         case RTL_GIGA_MAC_VER_03:
4827         case RTL_GIGA_MAC_VER_04:
4828         case RTL_GIGA_MAC_VER_05:
4829         case RTL_GIGA_MAC_VER_06:
4830         case RTL_GIGA_MAC_VER_10:
4831         case RTL_GIGA_MAC_VER_11:
4832         case RTL_GIGA_MAC_VER_12:
4833         case RTL_GIGA_MAC_VER_13:
4834         case RTL_GIGA_MAC_VER_14:
4835         case RTL_GIGA_MAC_VER_15:
4836         case RTL_GIGA_MAC_VER_16:
4837         case RTL_GIGA_MAC_VER_17:
4838                 ops->write      = NULL;
4839                 ops->read       = NULL;
4840                 break;
4841
4842         case RTL_GIGA_MAC_VER_37:
4843         case RTL_GIGA_MAC_VER_38:
4844                 ops->write      = r8402_csi_write;
4845                 ops->read       = r8402_csi_read;
4846                 break;
4847
4848         case RTL_GIGA_MAC_VER_44:
4849                 ops->write      = r8411_csi_write;
4850                 ops->read       = r8411_csi_read;
4851                 break;
4852
4853         default:
4854                 ops->write      = r8169_csi_write;
4855                 ops->read       = r8169_csi_read;
4856                 break;
4857         }
4858 }
4859
4860 struct ephy_info {
4861         unsigned int offset;
4862         u16 mask;
4863         u16 bits;
4864 };
4865
4866 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4867                           int len)
4868 {
4869         u16 w;
4870
4871         while (len-- > 0) {
4872                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4873                 rtl_ephy_write(tp, e->offset, w);
4874                 e++;
4875         }
4876 }
4877
4878 static void rtl_disable_clock_request(struct pci_dev *pdev)
4879 {
4880         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4881                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4882 }
4883
4884 static void rtl_enable_clock_request(struct pci_dev *pdev)
4885 {
4886         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4887                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4888 }
4889
4890 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4891 {
4892         void __iomem *ioaddr = tp->mmio_addr;
4893         u8 data;
4894
4895         data = RTL_R8(Config3);
4896
4897         if (enable)
4898                 data |= Rdy_to_L23;
4899         else
4900                 data &= ~Rdy_to_L23;
4901
4902         RTL_W8(Config3, data);
4903 }
4904
4905 #define R8168_CPCMD_QUIRK_MASK (\
4906         EnableBist | \
4907         Mac_dbgo_oe | \
4908         Force_half_dup | \
4909         Force_rxflow_en | \
4910         Force_txflow_en | \
4911         Cxpl_dbg_sel | \
4912         ASF | \
4913         PktCntrDisable | \
4914         Mac_dbgo_sel)
4915
4916 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4917 {
4918         void __iomem *ioaddr = tp->mmio_addr;
4919         struct pci_dev *pdev = tp->pci_dev;
4920
4921         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4922
4923         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4924
4925         if (tp->dev->mtu <= ETH_DATA_LEN) {
4926                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4927                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4928         }
4929 }
4930
4931 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4932 {
4933         void __iomem *ioaddr = tp->mmio_addr;
4934
4935         rtl_hw_start_8168bb(tp);
4936
4937         RTL_W8(MaxTxPacketSize, TxPacketMax);
4938
4939         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4940 }
4941
4942 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4943 {
4944         void __iomem *ioaddr = tp->mmio_addr;
4945         struct pci_dev *pdev = tp->pci_dev;
4946
4947         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4948
4949         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4950
4951         if (tp->dev->mtu <= ETH_DATA_LEN)
4952                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4953
4954         rtl_disable_clock_request(pdev);
4955
4956         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4957 }
4958
4959 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4960 {
4961         static const struct ephy_info e_info_8168cp[] = {
4962                 { 0x01, 0,      0x0001 },
4963                 { 0x02, 0x0800, 0x1000 },
4964                 { 0x03, 0,      0x0042 },
4965                 { 0x06, 0x0080, 0x0000 },
4966                 { 0x07, 0,      0x2000 }
4967         };
4968
4969         rtl_csi_access_enable_2(tp);
4970
4971         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4972
4973         __rtl_hw_start_8168cp(tp);
4974 }
4975
4976 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4977 {
4978         void __iomem *ioaddr = tp->mmio_addr;
4979         struct pci_dev *pdev = tp->pci_dev;
4980
4981         rtl_csi_access_enable_2(tp);
4982
4983         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4984
4985         if (tp->dev->mtu <= ETH_DATA_LEN)
4986                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4987
4988         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4989 }
4990
4991 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4992 {
4993         void __iomem *ioaddr = tp->mmio_addr;
4994         struct pci_dev *pdev = tp->pci_dev;
4995
4996         rtl_csi_access_enable_2(tp);
4997
4998         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4999
5000         /* Magic. */
5001         RTL_W8(DBG_REG, 0x20);
5002
5003         RTL_W8(MaxTxPacketSize, TxPacketMax);
5004
5005         if (tp->dev->mtu <= ETH_DATA_LEN)
5006                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5007
5008         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5009 }
5010
5011 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5012 {
5013         void __iomem *ioaddr = tp->mmio_addr;
5014         static const struct ephy_info e_info_8168c_1[] = {
5015                 { 0x02, 0x0800, 0x1000 },
5016                 { 0x03, 0,      0x0002 },
5017                 { 0x06, 0x0080, 0x0000 }
5018         };
5019
5020         rtl_csi_access_enable_2(tp);
5021
5022         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5023
5024         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5025
5026         __rtl_hw_start_8168cp(tp);
5027 }
5028
5029 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5030 {
5031         static const struct ephy_info e_info_8168c_2[] = {
5032                 { 0x01, 0,      0x0001 },
5033                 { 0x03, 0x0400, 0x0220 }
5034         };
5035
5036         rtl_csi_access_enable_2(tp);
5037
5038         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5039
5040         __rtl_hw_start_8168cp(tp);
5041 }
5042
5043 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5044 {
5045         rtl_hw_start_8168c_2(tp);
5046 }
5047
5048 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5049 {
5050         rtl_csi_access_enable_2(tp);
5051
5052         __rtl_hw_start_8168cp(tp);
5053 }
5054
5055 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5056 {
5057         void __iomem *ioaddr = tp->mmio_addr;
5058         struct pci_dev *pdev = tp->pci_dev;
5059
5060         rtl_csi_access_enable_2(tp);
5061
5062         rtl_disable_clock_request(pdev);
5063
5064         RTL_W8(MaxTxPacketSize, TxPacketMax);
5065
5066         if (tp->dev->mtu <= ETH_DATA_LEN)
5067                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5068
5069         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5070 }
5071
5072 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5073 {
5074         void __iomem *ioaddr = tp->mmio_addr;
5075         struct pci_dev *pdev = tp->pci_dev;
5076
5077         rtl_csi_access_enable_1(tp);
5078
5079         if (tp->dev->mtu <= ETH_DATA_LEN)
5080                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5081
5082         RTL_W8(MaxTxPacketSize, TxPacketMax);
5083
5084         rtl_disable_clock_request(pdev);
5085 }
5086
5087 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5088 {
5089         void __iomem *ioaddr = tp->mmio_addr;
5090         struct pci_dev *pdev = tp->pci_dev;
5091         static const struct ephy_info e_info_8168d_4[] = {
5092                 { 0x0b, ~0,     0x48 },
5093                 { 0x19, 0x20,   0x50 },
5094                 { 0x0c, ~0,     0x20 }
5095         };
5096         int i;
5097
5098         rtl_csi_access_enable_1(tp);
5099
5100         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5101
5102         RTL_W8(MaxTxPacketSize, TxPacketMax);
5103
5104         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5105                 const struct ephy_info *e = e_info_8168d_4 + i;
5106                 u16 w;
5107
5108                 w = rtl_ephy_read(tp, e->offset);
5109                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5110         }
5111
5112         rtl_enable_clock_request(pdev);
5113 }
5114
5115 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5116 {
5117         void __iomem *ioaddr = tp->mmio_addr;
5118         struct pci_dev *pdev = tp->pci_dev;
5119         static const struct ephy_info e_info_8168e_1[] = {
5120                 { 0x00, 0x0200, 0x0100 },
5121                 { 0x00, 0x0000, 0x0004 },
5122                 { 0x06, 0x0002, 0x0001 },
5123                 { 0x06, 0x0000, 0x0030 },
5124                 { 0x07, 0x0000, 0x2000 },
5125                 { 0x00, 0x0000, 0x0020 },
5126                 { 0x03, 0x5800, 0x2000 },
5127                 { 0x03, 0x0000, 0x0001 },
5128                 { 0x01, 0x0800, 0x1000 },
5129                 { 0x07, 0x0000, 0x4000 },
5130                 { 0x1e, 0x0000, 0x2000 },
5131                 { 0x19, 0xffff, 0xfe6c },
5132                 { 0x0a, 0x0000, 0x0040 }
5133         };
5134
5135         rtl_csi_access_enable_2(tp);
5136
5137         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5138
5139         if (tp->dev->mtu <= ETH_DATA_LEN)
5140                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5141
5142         RTL_W8(MaxTxPacketSize, TxPacketMax);
5143
5144         rtl_disable_clock_request(pdev);
5145
5146         /* Reset tx FIFO pointer */
5147         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5148         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5149
5150         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5151 }
5152
5153 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5154 {
5155         void __iomem *ioaddr = tp->mmio_addr;
5156         struct pci_dev *pdev = tp->pci_dev;
5157         static const struct ephy_info e_info_8168e_2[] = {
5158                 { 0x09, 0x0000, 0x0080 },
5159                 { 0x19, 0x0000, 0x0224 }
5160         };
5161
5162         rtl_csi_access_enable_1(tp);
5163
5164         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5165
5166         if (tp->dev->mtu <= ETH_DATA_LEN)
5167                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5168
5169         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5170         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5171         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5172         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5173         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5174         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5175         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5176         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5177
5178         RTL_W8(MaxTxPacketSize, EarlySize);
5179
5180         rtl_disable_clock_request(pdev);
5181
5182         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5183         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5184
5185         /* Adjust EEE LED frequency */
5186         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5187
5188         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5189         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5190         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5191 }
5192
5193 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5194 {
5195         void __iomem *ioaddr = tp->mmio_addr;
5196         struct pci_dev *pdev = tp->pci_dev;
5197
5198         rtl_csi_access_enable_2(tp);
5199
5200         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5201
5202         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5203         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5204         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5205         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5206         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5207         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5208         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5209         rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5210         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5211         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5212
5213         RTL_W8(MaxTxPacketSize, EarlySize);
5214
5215         rtl_disable_clock_request(pdev);
5216
5217         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5218         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5219         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5220         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5221         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5222 }
5223
5224 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5225 {
5226         void __iomem *ioaddr = tp->mmio_addr;
5227         static const struct ephy_info e_info_8168f_1[] = {
5228                 { 0x06, 0x00c0, 0x0020 },
5229                 { 0x08, 0x0001, 0x0002 },
5230                 { 0x09, 0x0000, 0x0080 },
5231                 { 0x19, 0x0000, 0x0224 }
5232         };
5233
5234         rtl_hw_start_8168f(tp);
5235
5236         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5237
5238         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5239
5240         /* Adjust EEE LED frequency */
5241         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5242 }
5243
5244 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5245 {
5246         static const struct ephy_info e_info_8168f_1[] = {
5247                 { 0x06, 0x00c0, 0x0020 },
5248                 { 0x0f, 0xffff, 0x5200 },
5249                 { 0x1e, 0x0000, 0x4000 },
5250                 { 0x19, 0x0000, 0x0224 }
5251         };
5252
5253         rtl_hw_start_8168f(tp);
5254         rtl_pcie_state_l2l3_enable(tp, false);
5255
5256         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5257
5258         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5259 }
5260
5261 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5262 {
5263         void __iomem *ioaddr = tp->mmio_addr;
5264         struct pci_dev *pdev = tp->pci_dev;
5265
5266         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5267
5268         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5269         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5270         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5271         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5272
5273         rtl_csi_access_enable_1(tp);
5274
5275         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5276
5277         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5278         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5279         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5280
5281         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5282         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5283         RTL_W8(MaxTxPacketSize, EarlySize);
5284
5285         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5286         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5287
5288         /* Adjust EEE LED frequency */
5289         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5290
5291         rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5292         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5293
5294         rtl_pcie_state_l2l3_enable(tp, false);
5295 }
5296
5297 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5298 {
5299         void __iomem *ioaddr = tp->mmio_addr;
5300         static const struct ephy_info e_info_8168g_2[] = {
5301                 { 0x00, 0x0000, 0x0008 },
5302                 { 0x0c, 0x3df0, 0x0200 },
5303                 { 0x19, 0xffff, 0xfc00 },
5304                 { 0x1e, 0xffff, 0x20eb }
5305         };
5306
5307         rtl_hw_start_8168g_1(tp);
5308
5309         /* disable aspm and clock request before access ephy */
5310         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5311         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5312         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5313 }
5314
5315 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5316 {
5317         void __iomem *ioaddr = tp->mmio_addr;
5318         static const struct ephy_info e_info_8411_2[] = {
5319                 { 0x00, 0x0000, 0x0008 },
5320                 { 0x0c, 0x3df0, 0x0200 },
5321                 { 0x0f, 0xffff, 0x5200 },
5322                 { 0x19, 0x0020, 0x0000 },
5323                 { 0x1e, 0x0000, 0x2000 }
5324         };
5325
5326         rtl_hw_start_8168g_1(tp);
5327
5328         /* disable aspm and clock request before access ephy */
5329         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5330         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5331         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5332 }
5333
5334 static void rtl_hw_start_8168(struct net_device *dev)
5335 {
5336         struct rtl8169_private *tp = netdev_priv(dev);
5337         void __iomem *ioaddr = tp->mmio_addr;
5338
5339         RTL_W8(Cfg9346, Cfg9346_Unlock);
5340
5341         RTL_W8(MaxTxPacketSize, TxPacketMax);
5342
5343         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5344
5345         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5346
5347         RTL_W16(CPlusCmd, tp->cp_cmd);
5348
5349         RTL_W16(IntrMitigate, 0x5151);
5350
5351         /* Work around for RxFIFO overflow. */
5352         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5353                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5354                 tp->event_slow &= ~RxOverflow;
5355         }
5356
5357         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5358
5359         rtl_set_rx_tx_config_registers(tp);
5360
5361         RTL_R8(IntrMask);
5362
5363         switch (tp->mac_version) {
5364         case RTL_GIGA_MAC_VER_11:
5365                 rtl_hw_start_8168bb(tp);
5366                 break;
5367
5368         case RTL_GIGA_MAC_VER_12:
5369         case RTL_GIGA_MAC_VER_17:
5370                 rtl_hw_start_8168bef(tp);
5371                 break;
5372
5373         case RTL_GIGA_MAC_VER_18:
5374                 rtl_hw_start_8168cp_1(tp);
5375                 break;
5376
5377         case RTL_GIGA_MAC_VER_19:
5378                 rtl_hw_start_8168c_1(tp);
5379                 break;
5380
5381         case RTL_GIGA_MAC_VER_20:
5382                 rtl_hw_start_8168c_2(tp);
5383                 break;
5384
5385         case RTL_GIGA_MAC_VER_21:
5386                 rtl_hw_start_8168c_3(tp);
5387                 break;
5388
5389         case RTL_GIGA_MAC_VER_22:
5390                 rtl_hw_start_8168c_4(tp);
5391                 break;
5392
5393         case RTL_GIGA_MAC_VER_23:
5394                 rtl_hw_start_8168cp_2(tp);
5395                 break;
5396
5397         case RTL_GIGA_MAC_VER_24:
5398                 rtl_hw_start_8168cp_3(tp);
5399                 break;
5400
5401         case RTL_GIGA_MAC_VER_25:
5402         case RTL_GIGA_MAC_VER_26:
5403         case RTL_GIGA_MAC_VER_27:
5404                 rtl_hw_start_8168d(tp);
5405                 break;
5406
5407         case RTL_GIGA_MAC_VER_28:
5408                 rtl_hw_start_8168d_4(tp);
5409                 break;
5410
5411         case RTL_GIGA_MAC_VER_31:
5412                 rtl_hw_start_8168dp(tp);
5413                 break;
5414
5415         case RTL_GIGA_MAC_VER_32:
5416         case RTL_GIGA_MAC_VER_33:
5417                 rtl_hw_start_8168e_1(tp);
5418                 break;
5419         case RTL_GIGA_MAC_VER_34:
5420                 rtl_hw_start_8168e_2(tp);
5421                 break;
5422
5423         case RTL_GIGA_MAC_VER_35:
5424         case RTL_GIGA_MAC_VER_36:
5425                 rtl_hw_start_8168f_1(tp);
5426                 break;
5427
5428         case RTL_GIGA_MAC_VER_38:
5429                 rtl_hw_start_8411(tp);
5430                 break;
5431
5432         case RTL_GIGA_MAC_VER_40:
5433         case RTL_GIGA_MAC_VER_41:
5434                 rtl_hw_start_8168g_1(tp);
5435                 break;
5436         case RTL_GIGA_MAC_VER_42:
5437                 rtl_hw_start_8168g_2(tp);
5438                 break;
5439
5440         case RTL_GIGA_MAC_VER_44:
5441                 rtl_hw_start_8411_2(tp);
5442                 break;
5443
5444         default:
5445                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5446                         dev->name, tp->mac_version);
5447                 break;
5448         }
5449
5450         RTL_W8(Cfg9346, Cfg9346_Lock);
5451
5452         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5453
5454         rtl_set_rx_mode(dev);
5455
5456         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5457 }
5458
5459 #define R810X_CPCMD_QUIRK_MASK (\
5460         EnableBist | \
5461         Mac_dbgo_oe | \
5462         Force_half_dup | \
5463         Force_rxflow_en | \
5464         Force_txflow_en | \
5465         Cxpl_dbg_sel | \
5466         ASF | \
5467         PktCntrDisable | \
5468         Mac_dbgo_sel)
5469
5470 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5471 {
5472         void __iomem *ioaddr = tp->mmio_addr;
5473         struct pci_dev *pdev = tp->pci_dev;
5474         static const struct ephy_info e_info_8102e_1[] = {
5475                 { 0x01, 0, 0x6e65 },
5476                 { 0x02, 0, 0x091f },
5477                 { 0x03, 0, 0xc2f9 },
5478                 { 0x06, 0, 0xafb5 },
5479                 { 0x07, 0, 0x0e00 },
5480                 { 0x19, 0, 0xec80 },
5481                 { 0x01, 0, 0x2e65 },
5482                 { 0x01, 0, 0x6e65 }
5483         };
5484         u8 cfg1;
5485
5486         rtl_csi_access_enable_2(tp);
5487
5488         RTL_W8(DBG_REG, FIX_NAK_1);
5489
5490         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5491
5492         RTL_W8(Config1,
5493                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5494         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5495
5496         cfg1 = RTL_R8(Config1);
5497         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5498                 RTL_W8(Config1, cfg1 & ~LEDS0);
5499
5500         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5501 }
5502
5503 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5504 {
5505         void __iomem *ioaddr = tp->mmio_addr;
5506         struct pci_dev *pdev = tp->pci_dev;
5507
5508         rtl_csi_access_enable_2(tp);
5509
5510         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5511
5512         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5513         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5514 }
5515
5516 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5517 {
5518         rtl_hw_start_8102e_2(tp);
5519
5520         rtl_ephy_write(tp, 0x03, 0xc2f9);
5521 }
5522
5523 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5524 {
5525         void __iomem *ioaddr = tp->mmio_addr;
5526         static const struct ephy_info e_info_8105e_1[] = {
5527                 { 0x07, 0, 0x4000 },
5528                 { 0x19, 0, 0x0200 },
5529                 { 0x19, 0, 0x0020 },
5530                 { 0x1e, 0, 0x2000 },
5531                 { 0x03, 0, 0x0001 },
5532                 { 0x19, 0, 0x0100 },
5533                 { 0x19, 0, 0x0004 },
5534                 { 0x0a, 0, 0x0020 }
5535         };
5536
5537         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5538         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5539
5540         /* Disable Early Tally Counter */
5541         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5542
5543         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5544         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5545
5546         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5547
5548         rtl_pcie_state_l2l3_enable(tp, false);
5549 }
5550
5551 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5552 {
5553         rtl_hw_start_8105e_1(tp);
5554         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5555 }
5556
5557 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5558 {
5559         void __iomem *ioaddr = tp->mmio_addr;
5560         static const struct ephy_info e_info_8402[] = {
5561                 { 0x19, 0xffff, 0xff64 },
5562                 { 0x1e, 0, 0x4000 }
5563         };
5564
5565         rtl_csi_access_enable_2(tp);
5566
5567         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5568         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5569
5570         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5571         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5572
5573         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5574
5575         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5576
5577         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5578         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5579         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5580         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5581         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5582         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5583         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5584
5585         rtl_pcie_state_l2l3_enable(tp, false);
5586 }
5587
5588 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5589 {
5590         void __iomem *ioaddr = tp->mmio_addr;
5591
5592         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5593         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5594
5595         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5596         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5597         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5598
5599         rtl_pcie_state_l2l3_enable(tp, false);
5600 }
5601
5602 static void rtl_hw_start_8101(struct net_device *dev)
5603 {
5604         struct rtl8169_private *tp = netdev_priv(dev);
5605         void __iomem *ioaddr = tp->mmio_addr;
5606         struct pci_dev *pdev = tp->pci_dev;
5607
5608         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5609                 tp->event_slow &= ~RxFIFOOver;
5610
5611         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5612             tp->mac_version == RTL_GIGA_MAC_VER_16)
5613                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5614                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5615
5616         RTL_W8(Cfg9346, Cfg9346_Unlock);
5617
5618         RTL_W8(MaxTxPacketSize, TxPacketMax);
5619
5620         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5621
5622         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5623         RTL_W16(CPlusCmd, tp->cp_cmd);
5624
5625         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5626
5627         rtl_set_rx_tx_config_registers(tp);
5628
5629         switch (tp->mac_version) {
5630         case RTL_GIGA_MAC_VER_07:
5631                 rtl_hw_start_8102e_1(tp);
5632                 break;
5633
5634         case RTL_GIGA_MAC_VER_08:
5635                 rtl_hw_start_8102e_3(tp);
5636                 break;
5637
5638         case RTL_GIGA_MAC_VER_09:
5639                 rtl_hw_start_8102e_2(tp);
5640                 break;
5641
5642         case RTL_GIGA_MAC_VER_29:
5643                 rtl_hw_start_8105e_1(tp);
5644                 break;
5645         case RTL_GIGA_MAC_VER_30:
5646                 rtl_hw_start_8105e_2(tp);
5647                 break;
5648
5649         case RTL_GIGA_MAC_VER_37:
5650                 rtl_hw_start_8402(tp);
5651                 break;
5652
5653         case RTL_GIGA_MAC_VER_39:
5654                 rtl_hw_start_8106(tp);
5655                 break;
5656         case RTL_GIGA_MAC_VER_43:
5657                 rtl_hw_start_8168g_2(tp);
5658                 break;
5659         }
5660
5661         RTL_W8(Cfg9346, Cfg9346_Lock);
5662
5663         RTL_W16(IntrMitigate, 0x0000);
5664
5665         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5666
5667         rtl_set_rx_mode(dev);
5668
5669         RTL_R8(IntrMask);
5670
5671         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5672 }
5673
5674 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5675 {
5676         struct rtl8169_private *tp = netdev_priv(dev);
5677
5678         if (new_mtu < ETH_ZLEN ||
5679             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5680                 return -EINVAL;
5681
5682         if (new_mtu > ETH_DATA_LEN)
5683                 rtl_hw_jumbo_enable(tp);
5684         else
5685                 rtl_hw_jumbo_disable(tp);
5686
5687         dev->mtu = new_mtu;
5688         netdev_update_features(dev);
5689
5690         return 0;
5691 }
5692
5693 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5694 {
5695         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5696         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5697 }
5698
5699 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5700                                      void **data_buff, struct RxDesc *desc)
5701 {
5702         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5703                          DMA_FROM_DEVICE);
5704
5705         kfree(*data_buff);
5706         *data_buff = NULL;
5707         rtl8169_make_unusable_by_asic(desc);
5708 }
5709
5710 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5711 {
5712         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5713
5714         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5715 }
5716
5717 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5718                                        u32 rx_buf_sz)
5719 {
5720         desc->addr = cpu_to_le64(mapping);
5721         wmb();
5722         rtl8169_mark_to_asic(desc, rx_buf_sz);
5723 }
5724
5725 static inline void *rtl8169_align(void *data)
5726 {
5727         return (void *)ALIGN((long)data, 16);
5728 }
5729
5730 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5731                                              struct RxDesc *desc)
5732 {
5733         void *data;
5734         dma_addr_t mapping;
5735         struct device *d = &tp->pci_dev->dev;
5736         struct net_device *dev = tp->dev;
5737         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5738
5739         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5740         if (!data)
5741                 return NULL;
5742
5743         if (rtl8169_align(data) != data) {
5744                 kfree(data);
5745                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5746                 if (!data)
5747                         return NULL;
5748         }
5749
5750         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5751                                  DMA_FROM_DEVICE);
5752         if (unlikely(dma_mapping_error(d, mapping))) {
5753                 if (net_ratelimit())
5754                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5755                 goto err_out;
5756         }
5757
5758         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5759         return data;
5760
5761 err_out:
5762         kfree(data);
5763         return NULL;
5764 }
5765
5766 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5767 {
5768         unsigned int i;
5769
5770         for (i = 0; i < NUM_RX_DESC; i++) {
5771                 if (tp->Rx_databuff[i]) {
5772                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5773                                             tp->RxDescArray + i);
5774                 }
5775         }
5776 }
5777
5778 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5779 {
5780         desc->opts1 |= cpu_to_le32(RingEnd);
5781 }
5782
5783 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5784 {
5785         unsigned int i;
5786
5787         for (i = 0; i < NUM_RX_DESC; i++) {
5788                 void *data;
5789
5790                 if (tp->Rx_databuff[i])
5791                         continue;
5792
5793                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5794                 if (!data) {
5795                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5796                         goto err_out;
5797                 }
5798                 tp->Rx_databuff[i] = data;
5799         }
5800
5801         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5802         return 0;
5803
5804 err_out:
5805         rtl8169_rx_clear(tp);
5806         return -ENOMEM;
5807 }
5808
5809 static int rtl8169_init_ring(struct net_device *dev)
5810 {
5811         struct rtl8169_private *tp = netdev_priv(dev);
5812
5813         rtl8169_init_ring_indexes(tp);
5814
5815         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5816         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5817
5818         return rtl8169_rx_fill(tp);
5819 }
5820
5821 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5822                                  struct TxDesc *desc)
5823 {
5824         unsigned int len = tx_skb->len;
5825
5826         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5827
5828         desc->opts1 = 0x00;
5829         desc->opts2 = 0x00;
5830         desc->addr = 0x00;
5831         tx_skb->len = 0;
5832 }
5833
5834 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5835                                    unsigned int n)
5836 {
5837         unsigned int i;
5838
5839         for (i = 0; i < n; i++) {
5840                 unsigned int entry = (start + i) % NUM_TX_DESC;
5841                 struct ring_info *tx_skb = tp->tx_skb + entry;
5842                 unsigned int len = tx_skb->len;
5843
5844                 if (len) {
5845                         struct sk_buff *skb = tx_skb->skb;
5846
5847                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5848                                              tp->TxDescArray + entry);
5849                         if (skb) {
5850                                 tp->dev->stats.tx_dropped++;
5851                                 dev_kfree_skb_any(skb);
5852                                 tx_skb->skb = NULL;
5853                         }
5854                 }
5855         }
5856 }
5857
5858 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5859 {
5860         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5861         tp->cur_tx = tp->dirty_tx = 0;
5862 }
5863
5864 static void rtl_reset_work(struct rtl8169_private *tp)
5865 {
5866         struct net_device *dev = tp->dev;
5867         int i;
5868
5869         napi_disable(&tp->napi);
5870         netif_stop_queue(dev);
5871         synchronize_sched();
5872
5873         rtl8169_hw_reset(tp);
5874
5875         for (i = 0; i < NUM_RX_DESC; i++)
5876                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5877
5878         rtl8169_tx_clear(tp);
5879         rtl8169_init_ring_indexes(tp);
5880
5881         napi_enable(&tp->napi);
5882         rtl_hw_start(dev);
5883         netif_wake_queue(dev);
5884         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5885 }
5886
5887 static void rtl8169_tx_timeout(struct net_device *dev)
5888 {
5889         struct rtl8169_private *tp = netdev_priv(dev);
5890
5891         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5892 }
5893
5894 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5895                               u32 *opts)
5896 {
5897         struct skb_shared_info *info = skb_shinfo(skb);
5898         unsigned int cur_frag, entry;
5899         struct TxDesc * uninitialized_var(txd);
5900         struct device *d = &tp->pci_dev->dev;
5901
5902         entry = tp->cur_tx;
5903         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5904                 const skb_frag_t *frag = info->frags + cur_frag;
5905                 dma_addr_t mapping;
5906                 u32 status, len;
5907                 void *addr;
5908
5909                 entry = (entry + 1) % NUM_TX_DESC;
5910
5911                 txd = tp->TxDescArray + entry;
5912                 len = skb_frag_size(frag);
5913                 addr = skb_frag_address(frag);
5914                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5915                 if (unlikely(dma_mapping_error(d, mapping))) {
5916                         if (net_ratelimit())
5917                                 netif_err(tp, drv, tp->dev,
5918                                           "Failed to map TX fragments DMA!\n");
5919                         goto err_out;
5920                 }
5921
5922                 /* Anti gcc 2.95.3 bugware (sic) */
5923                 status = opts[0] | len |
5924                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5925
5926                 txd->opts1 = cpu_to_le32(status);
5927                 txd->opts2 = cpu_to_le32(opts[1]);
5928                 txd->addr = cpu_to_le64(mapping);
5929
5930                 tp->tx_skb[entry].len = len;
5931         }
5932
5933         if (cur_frag) {
5934                 tp->tx_skb[entry].skb = skb;
5935                 txd->opts1 |= cpu_to_le32(LastFrag);
5936         }
5937
5938         return cur_frag;
5939
5940 err_out:
5941         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5942         return -EIO;
5943 }
5944
5945 static bool rtl_skb_pad(struct sk_buff *skb)
5946 {
5947         if (skb_padto(skb, ETH_ZLEN))
5948                 return false;
5949         skb_put(skb, ETH_ZLEN - skb->len);
5950         return true;
5951 }
5952
5953 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5954 {
5955         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5956 }
5957
5958 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5959                                       struct net_device *dev);
5960 /* r8169_csum_workaround()
5961  * The hw limites the value the transport offset. When the offset is out of the
5962  * range, calculate the checksum by sw.
5963  */
5964 static void r8169_csum_workaround(struct rtl8169_private *tp,
5965                                   struct sk_buff *skb)
5966 {
5967         if (skb_shinfo(skb)->gso_size) {
5968                 netdev_features_t features = tp->dev->features;
5969                 struct sk_buff *segs, *nskb;
5970
5971                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5972                 segs = skb_gso_segment(skb, features);
5973                 if (IS_ERR(segs) || !segs)
5974                         goto drop;
5975
5976                 do {
5977                         nskb = segs;
5978                         segs = segs->next;
5979                         nskb->next = NULL;
5980                         rtl8169_start_xmit(nskb, tp->dev);
5981                 } while (segs);
5982
5983                 dev_kfree_skb(skb);
5984         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5985                 if (skb_checksum_help(skb) < 0)
5986                         goto drop;
5987
5988                 rtl8169_start_xmit(skb, tp->dev);
5989         } else {
5990                 struct net_device_stats *stats;
5991
5992 drop:
5993                 stats = &tp->dev->stats;
5994                 stats->tx_dropped++;
5995                 dev_kfree_skb(skb);
5996         }
5997 }
5998
5999 /* msdn_giant_send_check()
6000  * According to the document of microsoft, the TCP Pseudo Header excludes the
6001  * packet length for IPv6 TCP large packets.
6002  */
6003 static int msdn_giant_send_check(struct sk_buff *skb)
6004 {
6005         const struct ipv6hdr *ipv6h;
6006         struct tcphdr *th;
6007         int ret;
6008
6009         ret = skb_cow_head(skb, 0);
6010         if (ret)
6011                 return ret;
6012
6013         ipv6h = ipv6_hdr(skb);
6014         th = tcp_hdr(skb);
6015
6016         th->check = 0;
6017         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6018
6019         return ret;
6020 }
6021
6022 static inline __be16 get_protocol(struct sk_buff *skb)
6023 {
6024         __be16 protocol;
6025
6026         if (skb->protocol == htons(ETH_P_8021Q))
6027                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6028         else
6029                 protocol = skb->protocol;
6030
6031         return protocol;
6032 }
6033
6034 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6035                                 struct sk_buff *skb, u32 *opts)
6036 {
6037         u32 mss = skb_shinfo(skb)->gso_size;
6038
6039         if (mss) {
6040                 opts[0] |= TD_LSO;
6041                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6042         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6043                 const struct iphdr *ip = ip_hdr(skb);
6044
6045                 if (ip->protocol == IPPROTO_TCP)
6046                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6047                 else if (ip->protocol == IPPROTO_UDP)
6048                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6049                 else
6050                         WARN_ON_ONCE(1);
6051         }
6052
6053         return true;
6054 }
6055
6056 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6057                                 struct sk_buff *skb, u32 *opts)
6058 {
6059         u32 transport_offset = (u32)skb_transport_offset(skb);
6060         u32 mss = skb_shinfo(skb)->gso_size;
6061
6062         if (mss) {
6063                 if (transport_offset > GTTCPHO_MAX) {
6064                         netif_warn(tp, tx_err, tp->dev,
6065                                    "Invalid transport offset 0x%x for TSO\n",
6066                                    transport_offset);
6067                         return false;
6068                 }
6069
6070                 switch (get_protocol(skb)) {
6071                 case htons(ETH_P_IP):
6072                         opts[0] |= TD1_GTSENV4;
6073                         break;
6074
6075                 case htons(ETH_P_IPV6):
6076                         if (msdn_giant_send_check(skb))
6077                                 return false;
6078
6079                         opts[0] |= TD1_GTSENV6;
6080                         break;
6081
6082                 default:
6083                         WARN_ON_ONCE(1);
6084                         break;
6085                 }
6086
6087                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6088                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6089         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6090                 u8 ip_protocol;
6091
6092                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6093                         return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6094
6095                 if (transport_offset > TCPHO_MAX) {
6096                         netif_warn(tp, tx_err, tp->dev,
6097                                    "Invalid transport offset 0x%x\n",
6098                                    transport_offset);
6099                         return false;
6100                 }
6101
6102                 switch (get_protocol(skb)) {
6103                 case htons(ETH_P_IP):
6104                         opts[1] |= TD1_IPv4_CS;
6105                         ip_protocol = ip_hdr(skb)->protocol;
6106                         break;
6107
6108                 case htons(ETH_P_IPV6):
6109                         opts[1] |= TD1_IPv6_CS;
6110                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6111                         break;
6112
6113                 default:
6114                         ip_protocol = IPPROTO_RAW;
6115                         break;
6116                 }
6117
6118                 if (ip_protocol == IPPROTO_TCP)
6119                         opts[1] |= TD1_TCP_CS;
6120                 else if (ip_protocol == IPPROTO_UDP)
6121                         opts[1] |= TD1_UDP_CS;
6122                 else
6123                         WARN_ON_ONCE(1);
6124
6125                 opts[1] |= transport_offset << TCPHO_SHIFT;
6126         } else {
6127                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6128                         return rtl_skb_pad(skb);
6129         }
6130
6131         return true;
6132 }
6133
6134 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6135                                       struct net_device *dev)
6136 {
6137         struct rtl8169_private *tp = netdev_priv(dev);
6138         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6139         struct TxDesc *txd = tp->TxDescArray + entry;
6140         void __iomem *ioaddr = tp->mmio_addr;
6141         struct device *d = &tp->pci_dev->dev;
6142         dma_addr_t mapping;
6143         u32 status, len;
6144         u32 opts[2];
6145         int frags;
6146
6147         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6148                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6149                 goto err_stop_0;
6150         }
6151
6152         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6153                 goto err_stop_0;
6154
6155         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6156         opts[0] = DescOwn;
6157
6158         if (!tp->tso_csum(tp, skb, opts)) {
6159                 r8169_csum_workaround(tp, skb);
6160                 return NETDEV_TX_OK;
6161         }
6162
6163         len = skb_headlen(skb);
6164         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6165         if (unlikely(dma_mapping_error(d, mapping))) {
6166                 if (net_ratelimit())
6167                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6168                 goto err_dma_0;
6169         }
6170
6171         tp->tx_skb[entry].len = len;
6172         txd->addr = cpu_to_le64(mapping);
6173
6174         frags = rtl8169_xmit_frags(tp, skb, opts);
6175         if (frags < 0)
6176                 goto err_dma_1;
6177         else if (frags)
6178                 opts[0] |= FirstFrag;
6179         else {
6180                 opts[0] |= FirstFrag | LastFrag;
6181                 tp->tx_skb[entry].skb = skb;
6182         }
6183
6184         txd->opts2 = cpu_to_le32(opts[1]);
6185
6186         skb_tx_timestamp(skb);
6187
6188         wmb();
6189
6190         /* Anti gcc 2.95.3 bugware (sic) */
6191         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6192         txd->opts1 = cpu_to_le32(status);
6193
6194         tp->cur_tx += frags + 1;
6195
6196         wmb();
6197
6198         RTL_W8(TxPoll, NPQ);
6199
6200         mmiowb();
6201
6202         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6203                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6204                  * not miss a ring update when it notices a stopped queue.
6205                  */
6206                 smp_wmb();
6207                 netif_stop_queue(dev);
6208                 /* Sync with rtl_tx:
6209                  * - publish queue status and cur_tx ring index (write barrier)
6210                  * - refresh dirty_tx ring index (read barrier).
6211                  * May the current thread have a pessimistic view of the ring
6212                  * status and forget to wake up queue, a racing rtl_tx thread
6213                  * can't.
6214                  */
6215                 smp_mb();
6216                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6217                         netif_wake_queue(dev);
6218         }
6219
6220         return NETDEV_TX_OK;
6221
6222 err_dma_1:
6223         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6224 err_dma_0:
6225         dev_kfree_skb_any(skb);
6226         dev->stats.tx_dropped++;
6227         return NETDEV_TX_OK;
6228
6229 err_stop_0:
6230         netif_stop_queue(dev);
6231         dev->stats.tx_dropped++;
6232         return NETDEV_TX_BUSY;
6233 }
6234
6235 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6236 {
6237         struct rtl8169_private *tp = netdev_priv(dev);
6238         struct pci_dev *pdev = tp->pci_dev;
6239         u16 pci_status, pci_cmd;
6240
6241         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6242         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6243
6244         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6245                   pci_cmd, pci_status);
6246
6247         /*
6248          * The recovery sequence below admits a very elaborated explanation:
6249          * - it seems to work;
6250          * - I did not see what else could be done;
6251          * - it makes iop3xx happy.
6252          *
6253          * Feel free to adjust to your needs.
6254          */
6255         if (pdev->broken_parity_status)
6256                 pci_cmd &= ~PCI_COMMAND_PARITY;
6257         else
6258                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6259
6260         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6261
6262         pci_write_config_word(pdev, PCI_STATUS,
6263                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6264                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6265                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6266
6267         /* The infamous DAC f*ckup only happens at boot time */
6268         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6269                 void __iomem *ioaddr = tp->mmio_addr;
6270
6271                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6272                 tp->cp_cmd &= ~PCIDAC;
6273                 RTL_W16(CPlusCmd, tp->cp_cmd);
6274                 dev->features &= ~NETIF_F_HIGHDMA;
6275         }
6276
6277         rtl8169_hw_reset(tp);
6278
6279         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6280 }
6281
6282 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6283 {
6284         unsigned int dirty_tx, tx_left;
6285
6286         dirty_tx = tp->dirty_tx;
6287         smp_rmb();
6288         tx_left = tp->cur_tx - dirty_tx;
6289
6290         while (tx_left > 0) {
6291                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6292                 struct ring_info *tx_skb = tp->tx_skb + entry;
6293                 u32 status;
6294
6295                 rmb();
6296                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6297                 if (status & DescOwn)
6298                         break;
6299
6300                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6301                                      tp->TxDescArray + entry);
6302                 if (status & LastFrag) {
6303                         u64_stats_update_begin(&tp->tx_stats.syncp);
6304                         tp->tx_stats.packets++;
6305                         tp->tx_stats.bytes += tx_skb->skb->len;
6306                         u64_stats_update_end(&tp->tx_stats.syncp);
6307                         dev_kfree_skb_any(tx_skb->skb);
6308                         tx_skb->skb = NULL;
6309                 }
6310                 dirty_tx++;
6311                 tx_left--;
6312         }
6313
6314         if (tp->dirty_tx != dirty_tx) {
6315                 tp->dirty_tx = dirty_tx;
6316                 /* Sync with rtl8169_start_xmit:
6317                  * - publish dirty_tx ring index (write barrier)
6318                  * - refresh cur_tx ring index and queue status (read barrier)
6319                  * May the current thread miss the stopped queue condition,
6320                  * a racing xmit thread can only have a right view of the
6321                  * ring status.
6322                  */
6323                 smp_mb();
6324                 if (netif_queue_stopped(dev) &&
6325                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6326                         netif_wake_queue(dev);
6327                 }
6328                 /*
6329                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6330                  * too close. Let's kick an extra TxPoll request when a burst
6331                  * of start_xmit activity is detected (if it is not detected,
6332                  * it is slow enough). -- FR
6333                  */
6334                 if (tp->cur_tx != dirty_tx) {
6335                         void __iomem *ioaddr = tp->mmio_addr;
6336
6337                         RTL_W8(TxPoll, NPQ);
6338                 }
6339         }
6340 }
6341
6342 static inline int rtl8169_fragmented_frame(u32 status)
6343 {
6344         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6345 }
6346
6347 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6348 {
6349         u32 status = opts1 & RxProtoMask;
6350
6351         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6352             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6353                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6354         else
6355                 skb_checksum_none_assert(skb);
6356 }
6357
6358 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6359                                            struct rtl8169_private *tp,
6360                                            int pkt_size,
6361                                            dma_addr_t addr)
6362 {
6363         struct sk_buff *skb;
6364         struct device *d = &tp->pci_dev->dev;
6365
6366         data = rtl8169_align(data);
6367         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6368         prefetch(data);
6369         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6370         if (skb)
6371                 memcpy(skb->data, data, pkt_size);
6372         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6373
6374         return skb;
6375 }
6376
6377 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6378 {
6379         unsigned int cur_rx, rx_left;
6380         unsigned int count;
6381
6382         cur_rx = tp->cur_rx;
6383
6384         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6385                 unsigned int entry = cur_rx % NUM_RX_DESC;
6386                 struct RxDesc *desc = tp->RxDescArray + entry;
6387                 u32 status;
6388
6389                 rmb();
6390                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6391
6392                 if (status & DescOwn)
6393                         break;
6394                 if (unlikely(status & RxRES)) {
6395                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6396                                    status);
6397                         dev->stats.rx_errors++;
6398                         if (status & (RxRWT | RxRUNT))
6399                                 dev->stats.rx_length_errors++;
6400                         if (status & RxCRC)
6401                                 dev->stats.rx_crc_errors++;
6402                         if (status & RxFOVF) {
6403                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6404                                 dev->stats.rx_fifo_errors++;
6405                         }
6406                         if ((status & (RxRUNT | RxCRC)) &&
6407                             !(status & (RxRWT | RxFOVF)) &&
6408                             (dev->features & NETIF_F_RXALL))
6409                                 goto process_pkt;
6410                 } else {
6411                         struct sk_buff *skb;
6412                         dma_addr_t addr;
6413                         int pkt_size;
6414
6415 process_pkt:
6416                         addr = le64_to_cpu(desc->addr);
6417                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6418                                 pkt_size = (status & 0x00003fff) - 4;
6419                         else
6420                                 pkt_size = status & 0x00003fff;
6421
6422                         /*
6423                          * The driver does not support incoming fragmented
6424                          * frames. They are seen as a symptom of over-mtu
6425                          * sized frames.
6426                          */
6427                         if (unlikely(rtl8169_fragmented_frame(status))) {
6428                                 dev->stats.rx_dropped++;
6429                                 dev->stats.rx_length_errors++;
6430                                 goto release_descriptor;
6431                         }
6432
6433                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6434                                                   tp, pkt_size, addr);
6435                         if (!skb) {
6436                                 dev->stats.rx_dropped++;
6437                                 goto release_descriptor;
6438                         }
6439
6440                         rtl8169_rx_csum(skb, status);
6441                         skb_put(skb, pkt_size);
6442                         skb->protocol = eth_type_trans(skb, dev);
6443
6444                         rtl8169_rx_vlan_tag(desc, skb);
6445
6446                         napi_gro_receive(&tp->napi, skb);
6447
6448                         u64_stats_update_begin(&tp->rx_stats.syncp);
6449                         tp->rx_stats.packets++;
6450                         tp->rx_stats.bytes += pkt_size;
6451                         u64_stats_update_end(&tp->rx_stats.syncp);
6452                 }
6453 release_descriptor:
6454                 desc->opts2 = 0;
6455                 wmb();
6456                 rtl8169_mark_to_asic(desc, rx_buf_sz);
6457         }
6458
6459         count = cur_rx - tp->cur_rx;
6460         tp->cur_rx = cur_rx;
6461
6462         return count;
6463 }
6464
6465 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6466 {
6467         struct net_device *dev = dev_instance;
6468         struct rtl8169_private *tp = netdev_priv(dev);
6469         int handled = 0;
6470         u16 status;
6471
6472         status = rtl_get_events(tp);
6473         if (status && status != 0xffff) {
6474                 status &= RTL_EVENT_NAPI | tp->event_slow;
6475                 if (status) {
6476                         handled = 1;
6477
6478                         rtl_irq_disable(tp);
6479                         napi_schedule(&tp->napi);
6480                 }
6481         }
6482         return IRQ_RETVAL(handled);
6483 }
6484
6485 /*
6486  * Workqueue context.
6487  */
6488 static void rtl_slow_event_work(struct rtl8169_private *tp)
6489 {
6490         struct net_device *dev = tp->dev;
6491         u16 status;
6492
6493         status = rtl_get_events(tp) & tp->event_slow;
6494         rtl_ack_events(tp, status);
6495
6496         if (unlikely(status & RxFIFOOver)) {
6497                 switch (tp->mac_version) {
6498                 /* Work around for rx fifo overflow */
6499                 case RTL_GIGA_MAC_VER_11:
6500                         netif_stop_queue(dev);
6501                         /* XXX - Hack alert. See rtl_task(). */
6502                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6503                 default:
6504                         break;
6505                 }
6506         }
6507
6508         if (unlikely(status & SYSErr))
6509                 rtl8169_pcierr_interrupt(dev);
6510
6511         if (status & LinkChg)
6512                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6513
6514         rtl_irq_enable_all(tp);
6515 }
6516
6517 static void rtl_task(struct work_struct *work)
6518 {
6519         static const struct {
6520                 int bitnr;
6521                 void (*action)(struct rtl8169_private *);
6522         } rtl_work[] = {
6523                 /* XXX - keep rtl_slow_event_work() as first element. */
6524                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6525                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6526                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
6527         };
6528         struct rtl8169_private *tp =
6529                 container_of(work, struct rtl8169_private, wk.work);
6530         struct net_device *dev = tp->dev;
6531         int i;
6532
6533         rtl_lock_work(tp);
6534
6535         if (!netif_running(dev) ||
6536             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6537                 goto out_unlock;
6538
6539         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6540                 bool pending;
6541
6542                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6543                 if (pending)
6544                         rtl_work[i].action(tp);
6545         }
6546
6547 out_unlock:
6548         rtl_unlock_work(tp);
6549 }
6550
6551 static int rtl8169_poll(struct napi_struct *napi, int budget)
6552 {
6553         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6554         struct net_device *dev = tp->dev;
6555         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6556         int work_done= 0;
6557         u16 status;
6558
6559         status = rtl_get_events(tp);
6560         rtl_ack_events(tp, status & ~tp->event_slow);
6561
6562         if (status & RTL_EVENT_NAPI_RX)
6563                 work_done = rtl_rx(dev, tp, (u32) budget);
6564
6565         if (status & RTL_EVENT_NAPI_TX)
6566                 rtl_tx(dev, tp);
6567
6568         if (status & tp->event_slow) {
6569                 enable_mask &= ~tp->event_slow;
6570
6571                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6572         }
6573
6574         if (work_done < budget) {
6575                 napi_complete(napi);
6576
6577                 rtl_irq_enable(tp, enable_mask);
6578                 mmiowb();
6579         }
6580
6581         return work_done;
6582 }
6583
6584 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6585 {
6586         struct rtl8169_private *tp = netdev_priv(dev);
6587
6588         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6589                 return;
6590
6591         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6592         RTL_W32(RxMissed, 0);
6593 }
6594
6595 static void rtl8169_down(struct net_device *dev)
6596 {
6597         struct rtl8169_private *tp = netdev_priv(dev);
6598         void __iomem *ioaddr = tp->mmio_addr;
6599
6600         del_timer_sync(&tp->timer);
6601
6602         napi_disable(&tp->napi);
6603         netif_stop_queue(dev);
6604
6605         rtl8169_hw_reset(tp);
6606         /*
6607          * At this point device interrupts can not be enabled in any function,
6608          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6609          * and napi is disabled (rtl8169_poll).
6610          */
6611         rtl8169_rx_missed(dev, ioaddr);
6612
6613         /* Give a racing hard_start_xmit a few cycles to complete. */
6614         synchronize_sched();
6615
6616         rtl8169_tx_clear(tp);
6617
6618         rtl8169_rx_clear(tp);
6619
6620         rtl_pll_power_down(tp);
6621 }
6622
6623 static int rtl8169_close(struct net_device *dev)
6624 {
6625         struct rtl8169_private *tp = netdev_priv(dev);
6626         struct pci_dev *pdev = tp->pci_dev;
6627
6628         pm_runtime_get_sync(&pdev->dev);
6629
6630         /* Update counters before going down */
6631         rtl8169_update_counters(dev);
6632
6633         rtl_lock_work(tp);
6634         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6635
6636         rtl8169_down(dev);
6637         rtl_unlock_work(tp);
6638
6639         cancel_work_sync(&tp->wk.work);
6640
6641         free_irq(pdev->irq, dev);
6642
6643         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6644                           tp->RxPhyAddr);
6645         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6646                           tp->TxPhyAddr);
6647         tp->TxDescArray = NULL;
6648         tp->RxDescArray = NULL;
6649
6650         pm_runtime_put_sync(&pdev->dev);
6651
6652         return 0;
6653 }
6654
6655 #ifdef CONFIG_NET_POLL_CONTROLLER
6656 static void rtl8169_netpoll(struct net_device *dev)
6657 {
6658         struct rtl8169_private *tp = netdev_priv(dev);
6659
6660         rtl8169_interrupt(tp->pci_dev->irq, dev);
6661 }
6662 #endif
6663
6664 static int rtl_open(struct net_device *dev)
6665 {
6666         struct rtl8169_private *tp = netdev_priv(dev);
6667         void __iomem *ioaddr = tp->mmio_addr;
6668         struct pci_dev *pdev = tp->pci_dev;
6669         int retval = -ENOMEM;
6670
6671         pm_runtime_get_sync(&pdev->dev);
6672
6673         /*
6674          * Rx and Tx descriptors needs 256 bytes alignment.
6675          * dma_alloc_coherent provides more.
6676          */
6677         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6678                                              &tp->TxPhyAddr, GFP_KERNEL);
6679         if (!tp->TxDescArray)
6680                 goto err_pm_runtime_put;
6681
6682         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6683                                              &tp->RxPhyAddr, GFP_KERNEL);
6684         if (!tp->RxDescArray)
6685                 goto err_free_tx_0;
6686
6687         retval = rtl8169_init_ring(dev);
6688         if (retval < 0)
6689                 goto err_free_rx_1;
6690
6691         INIT_WORK(&tp->wk.work, rtl_task);
6692
6693         smp_mb();
6694
6695         rtl_request_firmware(tp);
6696
6697         retval = request_irq(pdev->irq, rtl8169_interrupt,
6698                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6699                              dev->name, dev);
6700         if (retval < 0)
6701                 goto err_release_fw_2;
6702
6703         rtl_lock_work(tp);
6704
6705         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6706
6707         napi_enable(&tp->napi);
6708
6709         rtl8169_init_phy(dev, tp);
6710
6711         __rtl8169_set_features(dev, dev->features);
6712
6713         rtl_pll_power_up(tp);
6714
6715         rtl_hw_start(dev);
6716
6717         netif_start_queue(dev);
6718
6719         rtl_unlock_work(tp);
6720
6721         tp->saved_wolopts = 0;
6722         pm_runtime_put_noidle(&pdev->dev);
6723
6724         rtl8169_check_link_status(dev, tp, ioaddr);
6725 out:
6726         return retval;
6727
6728 err_release_fw_2:
6729         rtl_release_firmware(tp);
6730         rtl8169_rx_clear(tp);
6731 err_free_rx_1:
6732         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6733                           tp->RxPhyAddr);
6734         tp->RxDescArray = NULL;
6735 err_free_tx_0:
6736         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6737                           tp->TxPhyAddr);
6738         tp->TxDescArray = NULL;
6739 err_pm_runtime_put:
6740         pm_runtime_put_noidle(&pdev->dev);
6741         goto out;
6742 }
6743
6744 static struct rtnl_link_stats64 *
6745 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6746 {
6747         struct rtl8169_private *tp = netdev_priv(dev);
6748         void __iomem *ioaddr = tp->mmio_addr;
6749         unsigned int start;
6750
6751         if (netif_running(dev))
6752                 rtl8169_rx_missed(dev, ioaddr);
6753
6754         do {
6755                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6756                 stats->rx_packets = tp->rx_stats.packets;
6757                 stats->rx_bytes = tp->rx_stats.bytes;
6758         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6759
6760
6761         do {
6762                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6763                 stats->tx_packets = tp->tx_stats.packets;
6764                 stats->tx_bytes = tp->tx_stats.bytes;
6765         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6766
6767         stats->rx_dropped       = dev->stats.rx_dropped;
6768         stats->tx_dropped       = dev->stats.tx_dropped;
6769         stats->rx_length_errors = dev->stats.rx_length_errors;
6770         stats->rx_errors        = dev->stats.rx_errors;
6771         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6772         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6773         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6774
6775         return stats;
6776 }
6777
6778 static void rtl8169_net_suspend(struct net_device *dev)
6779 {
6780         struct rtl8169_private *tp = netdev_priv(dev);
6781
6782         if (!netif_running(dev))
6783                 return;
6784
6785         netif_device_detach(dev);
6786         netif_stop_queue(dev);
6787
6788         rtl_lock_work(tp);
6789         napi_disable(&tp->napi);
6790         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6791         rtl_unlock_work(tp);
6792
6793         rtl_pll_power_down(tp);
6794 }
6795
6796 #ifdef CONFIG_PM
6797
6798 static int rtl8169_suspend(struct device *device)
6799 {
6800         struct pci_dev *pdev = to_pci_dev(device);
6801         struct net_device *dev = pci_get_drvdata(pdev);
6802
6803         rtl8169_net_suspend(dev);
6804
6805         return 0;
6806 }
6807
6808 static void __rtl8169_resume(struct net_device *dev)
6809 {
6810         struct rtl8169_private *tp = netdev_priv(dev);
6811
6812         netif_device_attach(dev);
6813
6814         rtl_pll_power_up(tp);
6815
6816         rtl_lock_work(tp);
6817         napi_enable(&tp->napi);
6818         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6819         rtl_unlock_work(tp);
6820
6821         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6822 }
6823
6824 static int rtl8169_resume(struct device *device)
6825 {
6826         struct pci_dev *pdev = to_pci_dev(device);
6827         struct net_device *dev = pci_get_drvdata(pdev);
6828         struct rtl8169_private *tp = netdev_priv(dev);
6829
6830         rtl8169_init_phy(dev, tp);
6831
6832         if (netif_running(dev))
6833                 __rtl8169_resume(dev);
6834
6835         return 0;
6836 }
6837
6838 static int rtl8169_runtime_suspend(struct device *device)
6839 {
6840         struct pci_dev *pdev = to_pci_dev(device);
6841         struct net_device *dev = pci_get_drvdata(pdev);
6842         struct rtl8169_private *tp = netdev_priv(dev);
6843
6844         if (!tp->TxDescArray)
6845                 return 0;
6846
6847         rtl_lock_work(tp);
6848         tp->saved_wolopts = __rtl8169_get_wol(tp);
6849         __rtl8169_set_wol(tp, WAKE_ANY);
6850         rtl_unlock_work(tp);
6851
6852         rtl8169_net_suspend(dev);
6853
6854         return 0;
6855 }
6856
6857 static int rtl8169_runtime_resume(struct device *device)
6858 {
6859         struct pci_dev *pdev = to_pci_dev(device);
6860         struct net_device *dev = pci_get_drvdata(pdev);
6861         struct rtl8169_private *tp = netdev_priv(dev);
6862
6863         if (!tp->TxDescArray)
6864                 return 0;
6865
6866         rtl_lock_work(tp);
6867         __rtl8169_set_wol(tp, tp->saved_wolopts);
6868         tp->saved_wolopts = 0;
6869         rtl_unlock_work(tp);
6870
6871         rtl8169_init_phy(dev, tp);
6872
6873         __rtl8169_resume(dev);
6874
6875         return 0;
6876 }
6877
6878 static int rtl8169_runtime_idle(struct device *device)
6879 {
6880         struct pci_dev *pdev = to_pci_dev(device);
6881         struct net_device *dev = pci_get_drvdata(pdev);
6882         struct rtl8169_private *tp = netdev_priv(dev);
6883
6884         return tp->TxDescArray ? -EBUSY : 0;
6885 }
6886
6887 static const struct dev_pm_ops rtl8169_pm_ops = {
6888         .suspend                = rtl8169_suspend,
6889         .resume                 = rtl8169_resume,
6890         .freeze                 = rtl8169_suspend,
6891         .thaw                   = rtl8169_resume,
6892         .poweroff               = rtl8169_suspend,
6893         .restore                = rtl8169_resume,
6894         .runtime_suspend        = rtl8169_runtime_suspend,
6895         .runtime_resume         = rtl8169_runtime_resume,
6896         .runtime_idle           = rtl8169_runtime_idle,
6897 };
6898
6899 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6900
6901 #else /* !CONFIG_PM */
6902
6903 #define RTL8169_PM_OPS  NULL
6904
6905 #endif /* !CONFIG_PM */
6906
6907 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6908 {
6909         void __iomem *ioaddr = tp->mmio_addr;
6910
6911         /* WoL fails with 8168b when the receiver is disabled. */
6912         switch (tp->mac_version) {
6913         case RTL_GIGA_MAC_VER_11:
6914         case RTL_GIGA_MAC_VER_12:
6915         case RTL_GIGA_MAC_VER_17:
6916                 pci_clear_master(tp->pci_dev);
6917
6918                 RTL_W8(ChipCmd, CmdRxEnb);
6919                 /* PCI commit */
6920                 RTL_R8(ChipCmd);
6921                 break;
6922         default:
6923                 break;
6924         }
6925 }
6926
6927 static void rtl_shutdown(struct pci_dev *pdev)
6928 {
6929         struct net_device *dev = pci_get_drvdata(pdev);
6930         struct rtl8169_private *tp = netdev_priv(dev);
6931         struct device *d = &pdev->dev;
6932
6933         pm_runtime_get_sync(d);
6934
6935         rtl8169_net_suspend(dev);
6936
6937         /* Restore original MAC address */
6938         rtl_rar_set(tp, dev->perm_addr);
6939
6940         rtl8169_hw_reset(tp);
6941
6942         if (system_state == SYSTEM_POWER_OFF) {
6943                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6944                         rtl_wol_suspend_quirk(tp);
6945                         rtl_wol_shutdown_quirk(tp);
6946                 }
6947
6948                 pci_wake_from_d3(pdev, true);
6949                 pci_set_power_state(pdev, PCI_D3hot);
6950         }
6951
6952         pm_runtime_put_noidle(d);
6953 }
6954
6955 static void rtl_remove_one(struct pci_dev *pdev)
6956 {
6957         struct net_device *dev = pci_get_drvdata(pdev);
6958         struct rtl8169_private *tp = netdev_priv(dev);
6959
6960         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6961             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6962             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6963                 rtl8168_driver_stop(tp);
6964         }
6965
6966         netif_napi_del(&tp->napi);
6967
6968         unregister_netdev(dev);
6969
6970         rtl_release_firmware(tp);
6971
6972         if (pci_dev_run_wake(pdev))
6973                 pm_runtime_get_noresume(&pdev->dev);
6974
6975         /* restore original MAC address */
6976         rtl_rar_set(tp, dev->perm_addr);
6977
6978         rtl_disable_msi(pdev, tp);
6979         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6980 }
6981
6982 static const struct net_device_ops rtl_netdev_ops = {
6983         .ndo_open               = rtl_open,
6984         .ndo_stop               = rtl8169_close,
6985         .ndo_get_stats64        = rtl8169_get_stats64,
6986         .ndo_start_xmit         = rtl8169_start_xmit,
6987         .ndo_tx_timeout         = rtl8169_tx_timeout,
6988         .ndo_validate_addr      = eth_validate_addr,
6989         .ndo_change_mtu         = rtl8169_change_mtu,
6990         .ndo_fix_features       = rtl8169_fix_features,
6991         .ndo_set_features       = rtl8169_set_features,
6992         .ndo_set_mac_address    = rtl_set_mac_address,
6993         .ndo_do_ioctl           = rtl8169_ioctl,
6994         .ndo_set_rx_mode        = rtl_set_rx_mode,
6995 #ifdef CONFIG_NET_POLL_CONTROLLER
6996         .ndo_poll_controller    = rtl8169_netpoll,
6997 #endif
6998
6999 };
7000
7001 static const struct rtl_cfg_info {
7002         void (*hw_start)(struct net_device *);
7003         unsigned int region;
7004         unsigned int align;
7005         u16 event_slow;
7006         unsigned features;
7007         u8 default_ver;
7008 } rtl_cfg_infos [] = {
7009         [RTL_CFG_0] = {
7010                 .hw_start       = rtl_hw_start_8169,
7011                 .region         = 1,
7012                 .align          = 0,
7013                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7014                 .features       = RTL_FEATURE_GMII,
7015                 .default_ver    = RTL_GIGA_MAC_VER_01,
7016         },
7017         [RTL_CFG_1] = {
7018                 .hw_start       = rtl_hw_start_8168,
7019                 .region         = 2,
7020                 .align          = 8,
7021                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7022                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7023                 .default_ver    = RTL_GIGA_MAC_VER_11,
7024         },
7025         [RTL_CFG_2] = {
7026                 .hw_start       = rtl_hw_start_8101,
7027                 .region         = 2,
7028                 .align          = 8,
7029                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7030                                   PCSTimeout,
7031                 .features       = RTL_FEATURE_MSI,
7032                 .default_ver    = RTL_GIGA_MAC_VER_13,
7033         }
7034 };
7035
7036 /* Cfg9346_Unlock assumed. */
7037 static unsigned rtl_try_msi(struct rtl8169_private *tp,
7038                             const struct rtl_cfg_info *cfg)
7039 {
7040         void __iomem *ioaddr = tp->mmio_addr;
7041         unsigned msi = 0;
7042         u8 cfg2;
7043
7044         cfg2 = RTL_R8(Config2) & ~MSIEnable;
7045         if (cfg->features & RTL_FEATURE_MSI) {
7046                 if (pci_enable_msi(tp->pci_dev)) {
7047                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7048                 } else {
7049                         cfg2 |= MSIEnable;
7050                         msi = RTL_FEATURE_MSI;
7051                 }
7052         }
7053         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7054                 RTL_W8(Config2, cfg2);
7055         return msi;
7056 }
7057
7058 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7059 {
7060         void __iomem *ioaddr = tp->mmio_addr;
7061
7062         return RTL_R8(MCU) & LINK_LIST_RDY;
7063 }
7064
7065 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7066 {
7067         void __iomem *ioaddr = tp->mmio_addr;
7068
7069         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7070 }
7071
7072 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7073 {
7074         void __iomem *ioaddr = tp->mmio_addr;
7075         u32 data;
7076
7077         tp->ocp_base = OCP_STD_PHY_BASE;
7078
7079         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7080
7081         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7082                 return;
7083
7084         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7085                 return;
7086
7087         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7088         msleep(1);
7089         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7090
7091         data = r8168_mac_ocp_read(tp, 0xe8de);
7092         data &= ~(1 << 14);
7093         r8168_mac_ocp_write(tp, 0xe8de, data);
7094
7095         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7096                 return;
7097
7098         data = r8168_mac_ocp_read(tp, 0xe8de);
7099         data |= (1 << 15);
7100         r8168_mac_ocp_write(tp, 0xe8de, data);
7101
7102         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7103                 return;
7104 }
7105
7106 static void rtl_hw_initialize(struct rtl8169_private *tp)
7107 {
7108         switch (tp->mac_version) {
7109         case RTL_GIGA_MAC_VER_40:
7110         case RTL_GIGA_MAC_VER_41:
7111         case RTL_GIGA_MAC_VER_42:
7112         case RTL_GIGA_MAC_VER_43:
7113         case RTL_GIGA_MAC_VER_44:
7114                 rtl_hw_init_8168g(tp);
7115                 break;
7116
7117         default:
7118                 break;
7119         }
7120 }
7121
7122 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7123 {
7124         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7125         const unsigned int region = cfg->region;
7126         struct rtl8169_private *tp;
7127         struct mii_if_info *mii;
7128         struct net_device *dev;
7129         void __iomem *ioaddr;
7130         int chipset, i;
7131         int rc;
7132
7133         if (netif_msg_drv(&debug)) {
7134                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7135                        MODULENAME, RTL8169_VERSION);
7136         }
7137
7138         dev = alloc_etherdev(sizeof (*tp));
7139         if (!dev) {
7140                 rc = -ENOMEM;
7141                 goto out;
7142         }
7143
7144         SET_NETDEV_DEV(dev, &pdev->dev);
7145         dev->netdev_ops = &rtl_netdev_ops;
7146         tp = netdev_priv(dev);
7147         tp->dev = dev;
7148         tp->pci_dev = pdev;
7149         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7150
7151         mii = &tp->mii;
7152         mii->dev = dev;
7153         mii->mdio_read = rtl_mdio_read;
7154         mii->mdio_write = rtl_mdio_write;
7155         mii->phy_id_mask = 0x1f;
7156         mii->reg_num_mask = 0x1f;
7157         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
7158
7159         /* disable ASPM completely as that cause random device stop working
7160          * problems as well as full system hangs for some PCIe devices users */
7161         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
7162                                      PCIE_LINK_STATE_CLKPM);
7163
7164         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7165         rc = pci_enable_device(pdev);
7166         if (rc < 0) {
7167                 netif_err(tp, probe, dev, "enable failure\n");
7168                 goto err_out_free_dev_1;
7169         }
7170
7171         if (pci_set_mwi(pdev) < 0)
7172                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7173
7174         /* make sure PCI base addr 1 is MMIO */
7175         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7176                 netif_err(tp, probe, dev,
7177                           "region #%d not an MMIO resource, aborting\n",
7178                           region);
7179                 rc = -ENODEV;
7180                 goto err_out_mwi_2;
7181         }
7182
7183         /* check for weird/broken PCI region reporting */
7184         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7185                 netif_err(tp, probe, dev,
7186                           "Invalid PCI region size(s), aborting\n");
7187                 rc = -ENODEV;
7188                 goto err_out_mwi_2;
7189         }
7190
7191         rc = pci_request_regions(pdev, MODULENAME);
7192         if (rc < 0) {
7193                 netif_err(tp, probe, dev, "could not request regions\n");
7194                 goto err_out_mwi_2;
7195         }
7196
7197         tp->cp_cmd = 0;
7198
7199         if ((sizeof(dma_addr_t) > 4) &&
7200             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7201                 tp->cp_cmd |= PCIDAC;
7202                 dev->features |= NETIF_F_HIGHDMA;
7203         } else {
7204                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7205                 if (rc < 0) {
7206                         netif_err(tp, probe, dev, "DMA configuration failed\n");
7207                         goto err_out_free_res_3;
7208                 }
7209         }
7210
7211         /* ioremap MMIO region */
7212         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7213         if (!ioaddr) {
7214                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7215                 rc = -EIO;
7216                 goto err_out_free_res_3;
7217         }
7218         tp->mmio_addr = ioaddr;
7219
7220         if (!pci_is_pcie(pdev))
7221                 netif_info(tp, probe, dev, "not PCI Express\n");
7222
7223         /* Identify chip attached to board */
7224         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7225
7226         rtl_init_rxcfg(tp);
7227
7228         rtl_irq_disable(tp);
7229
7230         rtl_hw_initialize(tp);
7231
7232         rtl_hw_reset(tp);
7233
7234         rtl_ack_events(tp, 0xffff);
7235
7236         pci_set_master(pdev);
7237
7238         rtl_init_mdio_ops(tp);
7239         rtl_init_pll_power_ops(tp);
7240         rtl_init_jumbo_ops(tp);
7241         rtl_init_csi_ops(tp);
7242
7243         rtl8169_print_mac_version(tp);
7244
7245         chipset = tp->mac_version;
7246         tp->txd_version = rtl_chip_infos[chipset].txd_version;
7247
7248         RTL_W8(Cfg9346, Cfg9346_Unlock);
7249         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7250         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
7251         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7252                 tp->features |= RTL_FEATURE_WOL;
7253         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7254                 tp->features |= RTL_FEATURE_WOL;
7255         tp->features |= rtl_try_msi(tp, cfg);
7256         RTL_W8(Cfg9346, Cfg9346_Lock);
7257
7258         if (rtl_tbi_enabled(tp)) {
7259                 tp->set_speed = rtl8169_set_speed_tbi;
7260                 tp->get_settings = rtl8169_gset_tbi;
7261                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7262                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7263                 tp->link_ok = rtl8169_tbi_link_ok;
7264                 tp->do_ioctl = rtl_tbi_ioctl;
7265         } else {
7266                 tp->set_speed = rtl8169_set_speed_xmii;
7267                 tp->get_settings = rtl8169_gset_xmii;
7268                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7269                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7270                 tp->link_ok = rtl8169_xmii_link_ok;
7271                 tp->do_ioctl = rtl_xmii_ioctl;
7272         }
7273
7274         mutex_init(&tp->wk.mutex);
7275         u64_stats_init(&tp->rx_stats.syncp);
7276         u64_stats_init(&tp->tx_stats.syncp);
7277
7278         /* Get MAC address */
7279         for (i = 0; i < ETH_ALEN; i++)
7280                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7281
7282         dev->ethtool_ops = &rtl8169_ethtool_ops;
7283         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7284
7285         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7286
7287         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7288          * properly for all devices */
7289         dev->features |= NETIF_F_RXCSUM |
7290                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7291
7292         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7293                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7294                 NETIF_F_HW_VLAN_CTAG_RX;
7295         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7296                 NETIF_F_HIGHDMA;
7297
7298         tp->cp_cmd |= RxChkSum | RxVlan;
7299
7300         /*
7301          * Pretend we are using VLANs; This bypasses a nasty bug where
7302          * Interrupts stop flowing on high load on 8110SCd controllers.
7303          */
7304         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7305                 /* Disallow toggling */
7306                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7307
7308         if (tp->txd_version == RTL_TD_0)
7309                 tp->tso_csum = rtl8169_tso_csum_v1;
7310         else if (tp->txd_version == RTL_TD_1) {
7311                 tp->tso_csum = rtl8169_tso_csum_v2;
7312                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7313         } else
7314                 WARN_ON_ONCE(1);
7315
7316         dev->hw_features |= NETIF_F_RXALL;
7317         dev->hw_features |= NETIF_F_RXFCS;
7318
7319         tp->hw_start = cfg->hw_start;
7320         tp->event_slow = cfg->event_slow;
7321
7322         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7323                 ~(RxBOVF | RxFOVF) : ~0;
7324
7325         init_timer(&tp->timer);
7326         tp->timer.data = (unsigned long) dev;
7327         tp->timer.function = rtl8169_phy_timer;
7328
7329         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7330
7331         rc = register_netdev(dev);
7332         if (rc < 0)
7333                 goto err_out_msi_4;
7334
7335         pci_set_drvdata(pdev, dev);
7336
7337         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7338                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7339                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7340         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7341                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7342                            "tx checksumming: %s]\n",
7343                            rtl_chip_infos[chipset].jumbo_max,
7344                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7345         }
7346
7347         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7348             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7349             tp->mac_version == RTL_GIGA_MAC_VER_31) {
7350                 rtl8168_driver_start(tp);
7351         }
7352
7353         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7354
7355         if (pci_dev_run_wake(pdev))
7356                 pm_runtime_put_noidle(&pdev->dev);
7357
7358         netif_carrier_off(dev);
7359
7360 out:
7361         return rc;
7362
7363 err_out_msi_4:
7364         netif_napi_del(&tp->napi);
7365         rtl_disable_msi(pdev, tp);
7366         iounmap(ioaddr);
7367 err_out_free_res_3:
7368         pci_release_regions(pdev);
7369 err_out_mwi_2:
7370         pci_clear_mwi(pdev);
7371         pci_disable_device(pdev);
7372 err_out_free_dev_1:
7373         free_netdev(dev);
7374         goto out;
7375 }
7376
7377 static struct pci_driver rtl8169_pci_driver = {
7378         .name           = MODULENAME,
7379         .id_table       = rtl8169_pci_tbl,
7380         .probe          = rtl_init_one,
7381         .remove         = rtl_remove_one,
7382         .shutdown       = rtl_shutdown,
7383         .driver.pm      = RTL8169_PM_OPS,
7384 };
7385
7386 module_pci_driver(rtl8169_pci_driver);