1 /* Renesas Ethernet AVB device driver
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 * Based on the SuperH Ethernet driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
35 #include <asm/div64.h>
39 #define RAVB_DEF_MSG_ENABLE \
45 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
50 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
55 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
58 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
61 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
65 for (i = 0; i < 10000; i++) {
66 if ((ravb_read(ndev, reg) & mask) == value)
73 static int ravb_config(struct net_device *ndev)
78 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
79 /* Check if the operating mode is changed to the config mode */
80 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
82 netdev_err(ndev, "failed to switch device to config mode\n");
87 static void ravb_set_duplex(struct net_device *ndev)
89 struct ravb_private *priv = netdev_priv(ndev);
91 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
94 static void ravb_set_rate(struct net_device *ndev)
96 struct ravb_private *priv = netdev_priv(ndev);
98 switch (priv->speed) {
99 case 100: /* 100BASE */
100 ravb_write(ndev, GECMR_SPEED_100, GECMR);
102 case 1000: /* 1000BASE */
103 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
108 static void ravb_set_buffer_align(struct sk_buff *skb)
110 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
113 skb_reserve(skb, RAVB_ALIGN - reserve);
116 /* Get MAC address from the MAC address registers
118 * Ethernet AVB device doesn't have ROM for MAC address.
119 * This function gets the MAC address that was used by a bootloader.
121 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
124 ether_addr_copy(ndev->dev_addr, mac);
126 u32 mahr = ravb_read(ndev, MAHR);
127 u32 malr = ravb_read(ndev, MALR);
129 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
130 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
131 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
132 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
133 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
134 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
138 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
140 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
143 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
146 /* MDC pin control */
147 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
149 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
152 /* Data I/O pin control */
153 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
155 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
159 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
161 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
165 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
167 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
170 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
173 /* MDIO bus control struct */
174 static struct mdiobb_ops bb_ops = {
175 .owner = THIS_MODULE,
176 .set_mdc = ravb_set_mdc,
177 .set_mdio_dir = ravb_set_mdio_dir,
178 .set_mdio_data = ravb_set_mdio_data,
179 .get_mdio_data = ravb_get_mdio_data,
182 /* Free skb's and DMA buffers for Ethernet AVB */
183 static void ravb_ring_free(struct net_device *ndev, int q)
185 struct ravb_private *priv = netdev_priv(ndev);
189 /* Free RX skb ringbuffer */
190 if (priv->rx_skb[q]) {
191 for (i = 0; i < priv->num_rx_ring[q]; i++)
192 dev_kfree_skb(priv->rx_skb[q][i]);
194 kfree(priv->rx_skb[q]);
195 priv->rx_skb[q] = NULL;
197 /* Free TX skb ringbuffer */
198 if (priv->tx_skb[q]) {
199 for (i = 0; i < priv->num_tx_ring[q]; i++)
200 dev_kfree_skb(priv->tx_skb[q][i]);
202 kfree(priv->tx_skb[q]);
203 priv->tx_skb[q] = NULL;
205 /* Free aligned TX buffers */
206 kfree(priv->tx_align[q]);
207 priv->tx_align[q] = NULL;
209 if (priv->rx_ring[q]) {
210 ring_size = sizeof(struct ravb_ex_rx_desc) *
211 (priv->num_rx_ring[q] + 1);
212 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
213 priv->rx_desc_dma[q]);
214 priv->rx_ring[q] = NULL;
217 if (priv->tx_ring[q]) {
218 ring_size = sizeof(struct ravb_tx_desc) *
219 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
220 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
221 priv->tx_desc_dma[q]);
222 priv->tx_ring[q] = NULL;
226 /* Format skb and descriptor buffer for Ethernet AVB */
227 static void ravb_ring_format(struct net_device *ndev, int q)
229 struct ravb_private *priv = netdev_priv(ndev);
230 struct ravb_ex_rx_desc *rx_desc;
231 struct ravb_tx_desc *tx_desc;
232 struct ravb_desc *desc;
233 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
234 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
241 priv->dirty_rx[q] = 0;
242 priv->dirty_tx[q] = 0;
244 memset(priv->rx_ring[q], 0, rx_ring_size);
245 /* Build RX ring buffer */
246 for (i = 0; i < priv->num_rx_ring[q]; i++) {
248 rx_desc = &priv->rx_ring[q][i];
249 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
250 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
253 /* We just set the data size to 0 for a failed mapping which
254 * should prevent DMA from happening...
256 if (dma_mapping_error(ndev->dev.parent, dma_addr))
257 rx_desc->ds_cc = cpu_to_le16(0);
258 rx_desc->dptr = cpu_to_le32(dma_addr);
259 rx_desc->die_dt = DT_FEMPTY;
261 rx_desc = &priv->rx_ring[q][i];
262 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
263 rx_desc->die_dt = DT_LINKFIX; /* type */
265 memset(priv->tx_ring[q], 0, tx_ring_size);
266 /* Build TX ring buffer */
267 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
269 tx_desc->die_dt = DT_EEMPTY;
271 tx_desc->die_dt = DT_EEMPTY;
273 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
274 tx_desc->die_dt = DT_LINKFIX; /* type */
276 /* RX descriptor base address for best effort */
277 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
278 desc->die_dt = DT_LINKFIX; /* type */
279 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
281 /* TX descriptor base address for best effort */
282 desc = &priv->desc_bat[q];
283 desc->die_dt = DT_LINKFIX; /* type */
284 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
287 /* Init skb and descriptor buffer for Ethernet AVB */
288 static int ravb_ring_init(struct net_device *ndev, int q)
290 struct ravb_private *priv = netdev_priv(ndev);
295 /* Allocate RX and TX skb rings */
296 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
297 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
298 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
299 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
300 if (!priv->rx_skb[q] || !priv->tx_skb[q])
303 for (i = 0; i < priv->num_rx_ring[q]; i++) {
304 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
307 ravb_set_buffer_align(skb);
308 priv->rx_skb[q][i] = skb;
311 /* Allocate rings for the aligned buffers */
312 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
313 DPTR_ALIGN - 1, GFP_KERNEL);
314 if (!priv->tx_align[q])
317 /* Allocate all RX descriptors. */
318 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
319 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
320 &priv->rx_desc_dma[q],
322 if (!priv->rx_ring[q])
325 priv->dirty_rx[q] = 0;
327 /* Allocate all TX descriptors. */
328 ring_size = sizeof(struct ravb_tx_desc) *
329 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
330 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
331 &priv->tx_desc_dma[q],
333 if (!priv->tx_ring[q])
339 ravb_ring_free(ndev, q);
344 /* E-MAC init function */
345 static void ravb_emac_init(struct net_device *ndev)
347 struct ravb_private *priv = netdev_priv(ndev);
349 /* Receive frame limit set register */
350 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
352 /* PAUSE prohibition */
353 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
354 ECMR_TE | ECMR_RE, ECMR);
358 /* Set MAC address */
360 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
361 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
363 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
365 ravb_write(ndev, 1, MPR);
367 /* E-MAC status register clear */
368 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
370 /* E-MAC interrupt enable register */
371 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
374 /* Device init function for Ethernet AVB */
375 static int ravb_dmac_init(struct net_device *ndev)
377 struct ravb_private *priv = netdev_priv(ndev);
380 /* Set CONFIG mode */
381 error = ravb_config(ndev);
385 error = ravb_ring_init(ndev, RAVB_BE);
388 error = ravb_ring_init(ndev, RAVB_NC);
390 ravb_ring_free(ndev, RAVB_BE);
394 /* Descriptor format */
395 ravb_ring_format(ndev, RAVB_BE);
396 ravb_ring_format(ndev, RAVB_NC);
398 #if defined(__LITTLE_ENDIAN)
399 ravb_modify(ndev, CCC, CCC_BOC, 0);
401 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
405 ravb_write(ndev, RCR_EFFS | RCR_ENCF | RCR_ETS0 | 0x18000000, RCR);
408 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
410 /* Timestamp enable */
411 ravb_write(ndev, TCCR_TFEN, TCCR);
413 /* Interrupt init: */
414 if (priv->chip_id == RCAR_GEN3) {
416 ravb_write(ndev, 0, DIL);
417 /* Set queue specific interrupt */
418 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
421 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
422 /* Disable FIFO full warning */
423 ravb_write(ndev, 0, RIC1);
424 /* Receive FIFO full error, descriptor empty */
425 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
426 /* Frame transmitted, timestamp FIFO updated */
427 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
429 /* Setting the control will start the AVB-DMAC process. */
430 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
435 /* Free TX skb function for AVB-IP */
436 static int ravb_tx_free(struct net_device *ndev, int q)
438 struct ravb_private *priv = netdev_priv(ndev);
439 struct net_device_stats *stats = &priv->stats[q];
440 struct ravb_tx_desc *desc;
445 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
446 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
448 desc = &priv->tx_ring[q][entry];
449 if (desc->die_dt != DT_FEMPTY)
451 /* Descriptor type must be checked before all other reads */
453 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
454 /* Free the original skb. */
455 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
456 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
457 size, DMA_TO_DEVICE);
458 /* Last packet descriptor? */
459 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
460 entry /= NUM_TX_DESC;
461 dev_kfree_skb_any(priv->tx_skb[q][entry]);
462 priv->tx_skb[q][entry] = NULL;
467 stats->tx_bytes += size;
468 desc->die_dt = DT_EEMPTY;
473 static void ravb_get_tx_tstamp(struct net_device *ndev)
475 struct ravb_private *priv = netdev_priv(ndev);
476 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
477 struct skb_shared_hwtstamps shhwtstamps;
479 struct timespec64 ts;
484 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
486 tfa2 = ravb_read(ndev, TFA2);
487 tfa_tag = (tfa2 & TFA2_TST) >> 16;
488 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
489 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
490 ravb_read(ndev, TFA1);
491 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
492 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
493 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
497 list_del(&ts_skb->list);
499 if (tag == tfa_tag) {
500 skb_tstamp_tx(skb, &shhwtstamps);
504 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
508 /* Packet receive function for Ethernet AVB */
509 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
511 struct ravb_private *priv = netdev_priv(ndev);
512 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
513 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
515 struct net_device_stats *stats = &priv->stats[q];
516 struct ravb_ex_rx_desc *desc;
519 struct timespec64 ts;
524 boguscnt = min(boguscnt, *quota);
526 desc = &priv->rx_ring[q][entry];
527 while (desc->die_dt != DT_FEMPTY) {
528 /* Descriptor type must be checked before all other reads */
530 desc_status = desc->msc;
531 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
536 /* We use 0-byte descriptors to mark the DMA mapping errors */
540 if (desc_status & MSC_MC)
543 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
546 if (desc_status & MSC_CRC)
547 stats->rx_crc_errors++;
548 if (desc_status & MSC_RFE)
549 stats->rx_frame_errors++;
550 if (desc_status & (MSC_RTLF | MSC_RTSF))
551 stats->rx_length_errors++;
552 if (desc_status & MSC_CEEF)
553 stats->rx_missed_errors++;
555 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
557 skb = priv->rx_skb[q][entry];
558 priv->rx_skb[q][entry] = NULL;
559 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
562 get_ts &= (q == RAVB_NC) ?
563 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
564 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
566 struct skb_shared_hwtstamps *shhwtstamps;
568 shhwtstamps = skb_hwtstamps(skb);
569 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
570 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
571 32) | le32_to_cpu(desc->ts_sl);
572 ts.tv_nsec = le32_to_cpu(desc->ts_n);
573 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
575 skb_put(skb, pkt_len);
576 skb->protocol = eth_type_trans(skb, ndev);
577 napi_gro_receive(&priv->napi[q], skb);
579 stats->rx_bytes += pkt_len;
582 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
583 desc = &priv->rx_ring[q][entry];
586 /* Refill the RX ring buffers. */
587 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
588 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
589 desc = &priv->rx_ring[q][entry];
590 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
592 if (!priv->rx_skb[q][entry]) {
593 skb = netdev_alloc_skb(ndev,
594 PKT_BUF_SZ + RAVB_ALIGN - 1);
596 break; /* Better luck next round. */
597 ravb_set_buffer_align(skb);
598 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
599 le16_to_cpu(desc->ds_cc),
601 skb_checksum_none_assert(skb);
602 /* We just set the data size to 0 for a failed mapping
603 * which should prevent DMA from happening...
605 if (dma_mapping_error(ndev->dev.parent, dma_addr))
606 desc->ds_cc = cpu_to_le16(0);
607 desc->dptr = cpu_to_le32(dma_addr);
608 priv->rx_skb[q][entry] = skb;
610 /* Descriptor type must be set after all the above writes */
612 desc->die_dt = DT_FEMPTY;
615 *quota -= limit - (++boguscnt);
617 return boguscnt <= 0;
620 static void ravb_rcv_snd_disable(struct net_device *ndev)
622 /* Disable TX and RX */
623 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
626 static void ravb_rcv_snd_enable(struct net_device *ndev)
628 /* Enable TX and RX */
629 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
632 /* function for waiting dma process finished */
633 static int ravb_stop_dma(struct net_device *ndev)
637 /* Wait for stopping the hardware TX process */
638 error = ravb_wait(ndev, TCCR,
639 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
643 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
648 /* Stop the E-MAC's RX/TX processes. */
649 ravb_rcv_snd_disable(ndev);
651 /* Wait for stopping the RX DMA process */
652 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
656 /* Stop AVB-DMAC process */
657 return ravb_config(ndev);
660 /* E-MAC interrupt handler */
661 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
663 struct ravb_private *priv = netdev_priv(ndev);
666 ecsr = ravb_read(ndev, ECSR);
667 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
669 ndev->stats.tx_carrier_errors++;
670 if (ecsr & ECSR_LCHNG) {
672 if (priv->no_avb_link)
674 psr = ravb_read(ndev, PSR);
675 if (priv->avb_link_active_low)
677 if (!(psr & PSR_LMON)) {
678 /* DIsable RX and TX */
679 ravb_rcv_snd_disable(ndev);
681 /* Enable RX and TX */
682 ravb_rcv_snd_enable(ndev);
687 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
689 struct net_device *ndev = dev_id;
690 struct ravb_private *priv = netdev_priv(ndev);
692 spin_lock(&priv->lock);
693 ravb_emac_interrupt_unlocked(ndev);
695 spin_unlock(&priv->lock);
699 /* Error interrupt handler */
700 static void ravb_error_interrupt(struct net_device *ndev)
702 struct ravb_private *priv = netdev_priv(ndev);
705 eis = ravb_read(ndev, EIS);
706 ravb_write(ndev, ~EIS_QFS, EIS);
708 ris2 = ravb_read(ndev, RIS2);
709 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
711 /* Receive Descriptor Empty int */
712 if (ris2 & RIS2_QFF0)
713 priv->stats[RAVB_BE].rx_over_errors++;
715 /* Receive Descriptor Empty int */
716 if (ris2 & RIS2_QFF1)
717 priv->stats[RAVB_NC].rx_over_errors++;
719 /* Receive FIFO Overflow int */
720 if (ris2 & RIS2_RFFF)
721 priv->rx_fifo_errors++;
725 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
727 struct ravb_private *priv = netdev_priv(ndev);
728 u32 ris0 = ravb_read(ndev, RIS0);
729 u32 ric0 = ravb_read(ndev, RIC0);
730 u32 tis = ravb_read(ndev, TIS);
731 u32 tic = ravb_read(ndev, TIC);
733 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
734 if (napi_schedule_prep(&priv->napi[q])) {
735 /* Mask RX and TX interrupts */
736 if (priv->chip_id == RCAR_GEN2) {
737 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
738 ravb_write(ndev, tic & ~BIT(q), TIC);
740 ravb_write(ndev, BIT(q), RID0);
741 ravb_write(ndev, BIT(q), TID);
743 __napi_schedule(&priv->napi[q]);
746 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
749 " tx status 0x%08x, tx mask 0x%08x.\n",
757 static bool ravb_timestamp_interrupt(struct net_device *ndev)
759 u32 tis = ravb_read(ndev, TIS);
761 if (tis & TIS_TFUF) {
762 ravb_write(ndev, ~TIS_TFUF, TIS);
763 ravb_get_tx_tstamp(ndev);
769 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
771 struct net_device *ndev = dev_id;
772 struct ravb_private *priv = netdev_priv(ndev);
773 irqreturn_t result = IRQ_NONE;
776 spin_lock(&priv->lock);
777 /* Get interrupt status */
778 iss = ravb_read(ndev, ISS);
780 /* Received and transmitted interrupts */
781 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
784 /* Timestamp updated */
785 if (ravb_timestamp_interrupt(ndev))
786 result = IRQ_HANDLED;
788 /* Network control and best effort queue RX/TX */
789 for (q = RAVB_NC; q >= RAVB_BE; q--) {
790 if (ravb_queue_interrupt(ndev, q))
791 result = IRQ_HANDLED;
795 /* E-MAC status summary */
797 ravb_emac_interrupt_unlocked(ndev);
798 result = IRQ_HANDLED;
801 /* Error status summary */
803 ravb_error_interrupt(ndev);
804 result = IRQ_HANDLED;
807 /* gPTP interrupt status summary */
808 if (iss & ISS_CGIS) {
809 ravb_ptp_interrupt(ndev);
810 result = IRQ_HANDLED;
814 spin_unlock(&priv->lock);
818 /* Timestamp/Error/gPTP interrupt handler */
819 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
821 struct net_device *ndev = dev_id;
822 struct ravb_private *priv = netdev_priv(ndev);
823 irqreturn_t result = IRQ_NONE;
826 spin_lock(&priv->lock);
827 /* Get interrupt status */
828 iss = ravb_read(ndev, ISS);
830 /* Timestamp updated */
831 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
832 result = IRQ_HANDLED;
834 /* Error status summary */
836 ravb_error_interrupt(ndev);
837 result = IRQ_HANDLED;
840 /* gPTP interrupt status summary */
841 if (iss & ISS_CGIS) {
842 ravb_ptp_interrupt(ndev);
843 result = IRQ_HANDLED;
847 spin_unlock(&priv->lock);
851 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
853 struct net_device *ndev = dev_id;
854 struct ravb_private *priv = netdev_priv(ndev);
855 irqreturn_t result = IRQ_NONE;
857 spin_lock(&priv->lock);
859 /* Network control/Best effort queue RX/TX */
860 if (ravb_queue_interrupt(ndev, q))
861 result = IRQ_HANDLED;
864 spin_unlock(&priv->lock);
868 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
870 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
873 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
875 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
878 static int ravb_poll(struct napi_struct *napi, int budget)
880 struct net_device *ndev = napi->dev;
881 struct ravb_private *priv = netdev_priv(ndev);
883 int q = napi - priv->napi;
889 tis = ravb_read(ndev, TIS);
890 ris0 = ravb_read(ndev, RIS0);
891 if (!((ris0 & mask) || (tis & mask)))
894 /* Processing RX Descriptor Ring */
896 /* Clear RX interrupt */
897 ravb_write(ndev, ~mask, RIS0);
898 if (ravb_rx(ndev, "a, q))
901 /* Processing TX Descriptor Ring */
903 spin_lock_irqsave(&priv->lock, flags);
904 /* Clear TX interrupt */
905 ravb_write(ndev, ~mask, TIS);
906 ravb_tx_free(ndev, q);
907 netif_wake_subqueue(ndev, q);
909 spin_unlock_irqrestore(&priv->lock, flags);
915 /* Re-enable RX/TX interrupts */
916 spin_lock_irqsave(&priv->lock, flags);
917 if (priv->chip_id == RCAR_GEN2) {
918 ravb_modify(ndev, RIC0, mask, mask);
919 ravb_modify(ndev, TIC, mask, mask);
921 ravb_write(ndev, mask, RIE0);
922 ravb_write(ndev, mask, TIE);
925 spin_unlock_irqrestore(&priv->lock, flags);
927 /* Receive error message handling */
928 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
929 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
930 if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
931 ndev->stats.rx_over_errors = priv->rx_over_errors;
932 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
934 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
935 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
936 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
939 return budget - quota;
942 /* PHY state control function */
943 static void ravb_adjust_link(struct net_device *ndev)
945 struct ravb_private *priv = netdev_priv(ndev);
946 struct phy_device *phydev = priv->phydev;
947 bool new_state = false;
950 if (phydev->duplex != priv->duplex) {
952 priv->duplex = phydev->duplex;
953 ravb_set_duplex(ndev);
956 if (phydev->speed != priv->speed) {
958 priv->speed = phydev->speed;
962 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
964 priv->link = phydev->link;
965 if (priv->no_avb_link)
966 ravb_rcv_snd_enable(ndev);
968 } else if (priv->link) {
973 if (priv->no_avb_link)
974 ravb_rcv_snd_disable(ndev);
977 if (new_state && netif_msg_link(priv))
978 phy_print_status(phydev);
981 /* PHY init function */
982 static int ravb_phy_init(struct net_device *ndev)
984 struct device_node *np = ndev->dev.parent->of_node;
985 struct ravb_private *priv = netdev_priv(ndev);
986 struct phy_device *phydev;
987 struct device_node *pn;
994 /* Try connecting to PHY */
995 pn = of_parse_phandle(np, "phy-handle", 0);
997 /* In the case of a fixed PHY, the DT node associated
998 * to the PHY is the Ethernet MAC DT node.
1000 if (of_phy_is_fixed_link(np)) {
1001 err = of_phy_register_fixed_link(np);
1005 pn = of_node_get(np);
1007 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1008 priv->phy_interface);
1010 netdev_err(ndev, "failed to connect PHY\n");
1014 /* This driver only support 10/100Mbit speeds on Gen3
1017 if (priv->chip_id == RCAR_GEN3) {
1020 err = phy_set_max_speed(phydev, SPEED_100);
1022 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1023 phy_disconnect(phydev);
1027 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1030 /* 10BASE is not supported */
1031 phydev->supported &= ~PHY_10BT_FEATURES;
1033 phy_attached_info(phydev);
1035 priv->phydev = phydev;
1040 /* PHY control start function */
1041 static int ravb_phy_start(struct net_device *ndev)
1043 struct ravb_private *priv = netdev_priv(ndev);
1046 error = ravb_phy_init(ndev);
1050 phy_start(priv->phydev);
1055 static int ravb_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1057 struct ravb_private *priv = netdev_priv(ndev);
1058 int error = -ENODEV;
1059 unsigned long flags;
1062 spin_lock_irqsave(&priv->lock, flags);
1063 error = phy_ethtool_gset(priv->phydev, ecmd);
1064 spin_unlock_irqrestore(&priv->lock, flags);
1070 static int ravb_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1072 struct ravb_private *priv = netdev_priv(ndev);
1073 unsigned long flags;
1079 spin_lock_irqsave(&priv->lock, flags);
1081 /* Disable TX and RX */
1082 ravb_rcv_snd_disable(ndev);
1084 error = phy_ethtool_sset(priv->phydev, ecmd);
1088 if (ecmd->duplex == DUPLEX_FULL)
1093 ravb_set_duplex(ndev);
1098 /* Enable TX and RX */
1099 ravb_rcv_snd_enable(ndev);
1102 spin_unlock_irqrestore(&priv->lock, flags);
1107 static int ravb_nway_reset(struct net_device *ndev)
1109 struct ravb_private *priv = netdev_priv(ndev);
1110 int error = -ENODEV;
1111 unsigned long flags;
1114 spin_lock_irqsave(&priv->lock, flags);
1115 error = phy_start_aneg(priv->phydev);
1116 spin_unlock_irqrestore(&priv->lock, flags);
1122 static u32 ravb_get_msglevel(struct net_device *ndev)
1124 struct ravb_private *priv = netdev_priv(ndev);
1126 return priv->msg_enable;
1129 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1131 struct ravb_private *priv = netdev_priv(ndev);
1133 priv->msg_enable = value;
1136 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1137 "rx_queue_0_current",
1138 "tx_queue_0_current",
1141 "rx_queue_0_packets",
1142 "tx_queue_0_packets",
1145 "rx_queue_0_mcast_packets",
1146 "rx_queue_0_errors",
1147 "rx_queue_0_crc_errors",
1148 "rx_queue_0_frame_errors",
1149 "rx_queue_0_length_errors",
1150 "rx_queue_0_missed_errors",
1151 "rx_queue_0_over_errors",
1153 "rx_queue_1_current",
1154 "tx_queue_1_current",
1157 "rx_queue_1_packets",
1158 "tx_queue_1_packets",
1161 "rx_queue_1_mcast_packets",
1162 "rx_queue_1_errors",
1163 "rx_queue_1_crc_errors",
1164 "rx_queue_1_frame_errors",
1165 "rx_queue_1_length_errors",
1166 "rx_queue_1_missed_errors",
1167 "rx_queue_1_over_errors",
1170 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1172 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1176 return RAVB_STATS_LEN;
1182 static void ravb_get_ethtool_stats(struct net_device *ndev,
1183 struct ethtool_stats *stats, u64 *data)
1185 struct ravb_private *priv = netdev_priv(ndev);
1189 /* Device-specific stats */
1190 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1191 struct net_device_stats *stats = &priv->stats[q];
1193 data[i++] = priv->cur_rx[q];
1194 data[i++] = priv->cur_tx[q];
1195 data[i++] = priv->dirty_rx[q];
1196 data[i++] = priv->dirty_tx[q];
1197 data[i++] = stats->rx_packets;
1198 data[i++] = stats->tx_packets;
1199 data[i++] = stats->rx_bytes;
1200 data[i++] = stats->tx_bytes;
1201 data[i++] = stats->multicast;
1202 data[i++] = stats->rx_errors;
1203 data[i++] = stats->rx_crc_errors;
1204 data[i++] = stats->rx_frame_errors;
1205 data[i++] = stats->rx_length_errors;
1206 data[i++] = stats->rx_missed_errors;
1207 data[i++] = stats->rx_over_errors;
1211 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1213 switch (stringset) {
1215 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1220 static void ravb_get_ringparam(struct net_device *ndev,
1221 struct ethtool_ringparam *ring)
1223 struct ravb_private *priv = netdev_priv(ndev);
1225 ring->rx_max_pending = BE_RX_RING_MAX;
1226 ring->tx_max_pending = BE_TX_RING_MAX;
1227 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1228 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1231 static int ravb_set_ringparam(struct net_device *ndev,
1232 struct ethtool_ringparam *ring)
1234 struct ravb_private *priv = netdev_priv(ndev);
1237 if (ring->tx_pending > BE_TX_RING_MAX ||
1238 ring->rx_pending > BE_RX_RING_MAX ||
1239 ring->tx_pending < BE_TX_RING_MIN ||
1240 ring->rx_pending < BE_RX_RING_MIN)
1242 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1245 if (netif_running(ndev)) {
1246 netif_device_detach(ndev);
1247 /* Stop PTP Clock driver */
1248 if (priv->chip_id == RCAR_GEN2)
1249 ravb_ptp_stop(ndev);
1250 /* Wait for DMA stopping */
1251 error = ravb_stop_dma(ndev);
1254 "cannot set ringparam! Any AVB processes are still running?\n");
1257 synchronize_irq(ndev->irq);
1259 /* Free all the skb's in the RX queue and the DMA buffers. */
1260 ravb_ring_free(ndev, RAVB_BE);
1261 ravb_ring_free(ndev, RAVB_NC);
1264 /* Set new parameters */
1265 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1266 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1268 if (netif_running(ndev)) {
1269 error = ravb_dmac_init(ndev);
1272 "%s: ravb_dmac_init() failed, error %d\n",
1277 ravb_emac_init(ndev);
1279 /* Initialise PTP Clock driver */
1280 if (priv->chip_id == RCAR_GEN2)
1281 ravb_ptp_init(ndev, priv->pdev);
1283 netif_device_attach(ndev);
1289 static int ravb_get_ts_info(struct net_device *ndev,
1290 struct ethtool_ts_info *info)
1292 struct ravb_private *priv = netdev_priv(ndev);
1294 info->so_timestamping =
1295 SOF_TIMESTAMPING_TX_SOFTWARE |
1296 SOF_TIMESTAMPING_RX_SOFTWARE |
1297 SOF_TIMESTAMPING_SOFTWARE |
1298 SOF_TIMESTAMPING_TX_HARDWARE |
1299 SOF_TIMESTAMPING_RX_HARDWARE |
1300 SOF_TIMESTAMPING_RAW_HARDWARE;
1301 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1303 (1 << HWTSTAMP_FILTER_NONE) |
1304 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1305 (1 << HWTSTAMP_FILTER_ALL);
1306 info->phc_index = ptp_clock_index(priv->ptp.clock);
1311 static const struct ethtool_ops ravb_ethtool_ops = {
1312 .get_settings = ravb_get_settings,
1313 .set_settings = ravb_set_settings,
1314 .nway_reset = ravb_nway_reset,
1315 .get_msglevel = ravb_get_msglevel,
1316 .set_msglevel = ravb_set_msglevel,
1317 .get_link = ethtool_op_get_link,
1318 .get_strings = ravb_get_strings,
1319 .get_ethtool_stats = ravb_get_ethtool_stats,
1320 .get_sset_count = ravb_get_sset_count,
1321 .get_ringparam = ravb_get_ringparam,
1322 .set_ringparam = ravb_set_ringparam,
1323 .get_ts_info = ravb_get_ts_info,
1326 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1327 struct net_device *ndev, struct device *dev,
1333 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1336 error = request_irq(irq, handler, 0, name, ndev);
1338 netdev_err(ndev, "cannot request IRQ %s\n", name);
1343 /* Network device open function for Ethernet AVB */
1344 static int ravb_open(struct net_device *ndev)
1346 struct ravb_private *priv = netdev_priv(ndev);
1347 struct platform_device *pdev = priv->pdev;
1348 struct device *dev = &pdev->dev;
1351 napi_enable(&priv->napi[RAVB_BE]);
1352 napi_enable(&priv->napi[RAVB_NC]);
1354 if (priv->chip_id == RCAR_GEN2) {
1355 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1358 netdev_err(ndev, "cannot request IRQ\n");
1362 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1366 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1370 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1371 ndev, dev, "ch0:rx_be");
1373 goto out_free_irq_emac;
1374 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1375 ndev, dev, "ch18:tx_be");
1377 goto out_free_irq_be_rx;
1378 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1379 ndev, dev, "ch1:rx_nc");
1381 goto out_free_irq_be_tx;
1382 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1383 ndev, dev, "ch19:tx_nc");
1385 goto out_free_irq_nc_rx;
1389 error = ravb_dmac_init(ndev);
1391 goto out_free_irq_nc_tx;
1392 ravb_emac_init(ndev);
1394 /* Initialise PTP Clock driver */
1395 if (priv->chip_id == RCAR_GEN2)
1396 ravb_ptp_init(ndev, priv->pdev);
1398 netif_tx_start_all_queues(ndev);
1400 /* PHY control start */
1401 error = ravb_phy_start(ndev);
1408 /* Stop PTP Clock driver */
1409 if (priv->chip_id == RCAR_GEN2)
1410 ravb_ptp_stop(ndev);
1412 if (priv->chip_id == RCAR_GEN2)
1414 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1416 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1418 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1420 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1422 free_irq(priv->emac_irq, ndev);
1424 free_irq(ndev->irq, ndev);
1426 napi_disable(&priv->napi[RAVB_NC]);
1427 napi_disable(&priv->napi[RAVB_BE]);
1431 /* Timeout function for Ethernet AVB */
1432 static void ravb_tx_timeout(struct net_device *ndev)
1434 struct ravb_private *priv = netdev_priv(ndev);
1436 netif_err(priv, tx_err, ndev,
1437 "transmit timed out, status %08x, resetting...\n",
1438 ravb_read(ndev, ISS));
1440 /* tx_errors count up */
1441 ndev->stats.tx_errors++;
1443 schedule_work(&priv->work);
1446 static void ravb_tx_timeout_work(struct work_struct *work)
1448 struct ravb_private *priv = container_of(work, struct ravb_private,
1450 struct net_device *ndev = priv->ndev;
1452 netif_tx_stop_all_queues(ndev);
1454 /* Stop PTP Clock driver */
1455 if (priv->chip_id == RCAR_GEN2)
1456 ravb_ptp_stop(ndev);
1458 /* Wait for DMA stopping */
1459 ravb_stop_dma(ndev);
1461 ravb_ring_free(ndev, RAVB_BE);
1462 ravb_ring_free(ndev, RAVB_NC);
1465 ravb_dmac_init(ndev);
1466 ravb_emac_init(ndev);
1468 /* Initialise PTP Clock driver */
1469 if (priv->chip_id == RCAR_GEN2)
1470 ravb_ptp_init(ndev, priv->pdev);
1472 netif_tx_start_all_queues(ndev);
1475 /* Packet transmit function for Ethernet AVB */
1476 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1478 struct ravb_private *priv = netdev_priv(ndev);
1479 u16 q = skb_get_queue_mapping(skb);
1480 struct ravb_tstamp_skb *ts_skb;
1481 struct ravb_tx_desc *desc;
1482 unsigned long flags;
1488 spin_lock_irqsave(&priv->lock, flags);
1489 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1491 netif_err(priv, tx_queued, ndev,
1492 "still transmitting with the full ring!\n");
1493 netif_stop_subqueue(ndev, q);
1494 spin_unlock_irqrestore(&priv->lock, flags);
1495 return NETDEV_TX_BUSY;
1497 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1498 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1500 if (skb_put_padto(skb, ETH_ZLEN))
1503 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1504 entry / NUM_TX_DESC * DPTR_ALIGN;
1505 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1506 memcpy(buffer, skb->data, len);
1507 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1508 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1511 desc = &priv->tx_ring[q][entry];
1512 desc->ds_tagl = cpu_to_le16(len);
1513 desc->dptr = cpu_to_le32(dma_addr);
1515 buffer = skb->data + len;
1516 len = skb->len - len;
1517 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1518 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1522 desc->ds_tagl = cpu_to_le16(len);
1523 desc->dptr = cpu_to_le32(dma_addr);
1525 /* TX timestamp required */
1527 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1530 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1535 ts_skb->tag = priv->ts_skb_tag++;
1536 priv->ts_skb_tag &= 0x3ff;
1537 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1539 /* TAG and timestamp required flag */
1540 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1541 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1542 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1545 skb_tx_timestamp(skb);
1546 /* Descriptor type must be set after all the above writes */
1548 desc->die_dt = DT_FEND;
1550 desc->die_dt = DT_FSTART;
1552 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1554 priv->cur_tx[q] += NUM_TX_DESC;
1555 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1556 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q))
1557 netif_stop_subqueue(ndev, q);
1561 spin_unlock_irqrestore(&priv->lock, flags);
1562 return NETDEV_TX_OK;
1565 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1566 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1568 dev_kfree_skb_any(skb);
1569 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1573 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1574 void *accel_priv, select_queue_fallback_t fallback)
1576 /* If skb needs TX timestamp, it is handled in network control queue */
1577 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1582 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1584 struct ravb_private *priv = netdev_priv(ndev);
1585 struct net_device_stats *nstats, *stats0, *stats1;
1587 nstats = &ndev->stats;
1588 stats0 = &priv->stats[RAVB_BE];
1589 stats1 = &priv->stats[RAVB_NC];
1591 nstats->tx_dropped += ravb_read(ndev, TROCR);
1592 ravb_write(ndev, 0, TROCR); /* (write clear) */
1593 nstats->collisions += ravb_read(ndev, CDCR);
1594 ravb_write(ndev, 0, CDCR); /* (write clear) */
1595 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1596 ravb_write(ndev, 0, LCCR); /* (write clear) */
1598 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1599 ravb_write(ndev, 0, CERCR); /* (write clear) */
1600 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1601 ravb_write(ndev, 0, CEECR); /* (write clear) */
1603 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1604 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1605 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1606 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1607 nstats->multicast = stats0->multicast + stats1->multicast;
1608 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1609 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1610 nstats->rx_frame_errors =
1611 stats0->rx_frame_errors + stats1->rx_frame_errors;
1612 nstats->rx_length_errors =
1613 stats0->rx_length_errors + stats1->rx_length_errors;
1614 nstats->rx_missed_errors =
1615 stats0->rx_missed_errors + stats1->rx_missed_errors;
1616 nstats->rx_over_errors =
1617 stats0->rx_over_errors + stats1->rx_over_errors;
1622 /* Update promiscuous bit */
1623 static void ravb_set_rx_mode(struct net_device *ndev)
1625 struct ravb_private *priv = netdev_priv(ndev);
1626 unsigned long flags;
1628 spin_lock_irqsave(&priv->lock, flags);
1629 ravb_modify(ndev, ECMR, ECMR_PRM,
1630 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1632 spin_unlock_irqrestore(&priv->lock, flags);
1635 /* Device close function for Ethernet AVB */
1636 static int ravb_close(struct net_device *ndev)
1638 struct ravb_private *priv = netdev_priv(ndev);
1639 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1641 netif_tx_stop_all_queues(ndev);
1643 /* Disable interrupts by clearing the interrupt masks. */
1644 ravb_write(ndev, 0, RIC0);
1645 ravb_write(ndev, 0, RIC2);
1646 ravb_write(ndev, 0, TIC);
1648 /* Stop PTP Clock driver */
1649 if (priv->chip_id == RCAR_GEN2)
1650 ravb_ptp_stop(ndev);
1652 /* Set the config mode to stop the AVB-DMAC's processes */
1653 if (ravb_stop_dma(ndev) < 0)
1655 "device will be stopped after h/w processes are done.\n");
1657 /* Clear the timestamp list */
1658 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1659 list_del(&ts_skb->list);
1663 /* PHY disconnect */
1665 phy_stop(priv->phydev);
1666 phy_disconnect(priv->phydev);
1667 priv->phydev = NULL;
1670 if (priv->chip_id != RCAR_GEN2) {
1671 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1672 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1673 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1674 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1675 free_irq(priv->emac_irq, ndev);
1677 free_irq(ndev->irq, ndev);
1679 napi_disable(&priv->napi[RAVB_NC]);
1680 napi_disable(&priv->napi[RAVB_BE]);
1682 /* Free all the skb's in the RX queue and the DMA buffers. */
1683 ravb_ring_free(ndev, RAVB_BE);
1684 ravb_ring_free(ndev, RAVB_NC);
1689 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1691 struct ravb_private *priv = netdev_priv(ndev);
1692 struct hwtstamp_config config;
1695 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1697 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1698 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1699 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1700 config.rx_filter = HWTSTAMP_FILTER_ALL;
1702 config.rx_filter = HWTSTAMP_FILTER_NONE;
1704 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1708 /* Control hardware time stamping */
1709 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1711 struct ravb_private *priv = netdev_priv(ndev);
1712 struct hwtstamp_config config;
1713 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1716 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1719 /* Reserved for future extensions */
1723 switch (config.tx_type) {
1724 case HWTSTAMP_TX_OFF:
1727 case HWTSTAMP_TX_ON:
1728 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1734 switch (config.rx_filter) {
1735 case HWTSTAMP_FILTER_NONE:
1738 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1739 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1742 config.rx_filter = HWTSTAMP_FILTER_ALL;
1743 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1746 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1747 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1749 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1753 /* ioctl to device function */
1754 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1756 struct ravb_private *priv = netdev_priv(ndev);
1757 struct phy_device *phydev = priv->phydev;
1759 if (!netif_running(ndev))
1767 return ravb_hwtstamp_get(ndev, req);
1769 return ravb_hwtstamp_set(ndev, req);
1772 return phy_mii_ioctl(phydev, req, cmd);
1775 static const struct net_device_ops ravb_netdev_ops = {
1776 .ndo_open = ravb_open,
1777 .ndo_stop = ravb_close,
1778 .ndo_start_xmit = ravb_start_xmit,
1779 .ndo_select_queue = ravb_select_queue,
1780 .ndo_get_stats = ravb_get_stats,
1781 .ndo_set_rx_mode = ravb_set_rx_mode,
1782 .ndo_tx_timeout = ravb_tx_timeout,
1783 .ndo_do_ioctl = ravb_do_ioctl,
1784 .ndo_validate_addr = eth_validate_addr,
1785 .ndo_set_mac_address = eth_mac_addr,
1786 .ndo_change_mtu = eth_change_mtu,
1789 /* MDIO bus init function */
1790 static int ravb_mdio_init(struct ravb_private *priv)
1792 struct platform_device *pdev = priv->pdev;
1793 struct device *dev = &pdev->dev;
1797 priv->mdiobb.ops = &bb_ops;
1799 /* MII controller setting */
1800 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1804 /* Hook up MII support for ethtool */
1805 priv->mii_bus->name = "ravb_mii";
1806 priv->mii_bus->parent = dev;
1807 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1808 pdev->name, pdev->id);
1810 /* Register MDIO bus */
1811 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1818 free_mdio_bitbang(priv->mii_bus);
1822 /* MDIO bus release function */
1823 static int ravb_mdio_release(struct ravb_private *priv)
1825 /* Unregister mdio bus */
1826 mdiobus_unregister(priv->mii_bus);
1828 /* Free bitbang info */
1829 free_mdio_bitbang(priv->mii_bus);
1834 static const struct of_device_id ravb_match_table[] = {
1835 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1836 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1837 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1838 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1839 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1842 MODULE_DEVICE_TABLE(of, ravb_match_table);
1844 static int ravb_set_gti(struct net_device *ndev)
1847 struct device *dev = ndev->dev.parent;
1848 struct device_node *np = dev->of_node;
1853 clk = of_clk_get(np, 0);
1855 dev_err(dev, "could not get clock\n");
1856 return PTR_ERR(clk);
1859 rate = clk_get_rate(clk);
1865 inc = 1000000000ULL << 20;
1868 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1869 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1870 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1874 ravb_write(ndev, inc, GTI);
1879 static int ravb_probe(struct platform_device *pdev)
1881 struct device_node *np = pdev->dev.of_node;
1882 struct ravb_private *priv;
1883 enum ravb_chip_id chip_id;
1884 struct net_device *ndev;
1886 struct resource *res;
1891 "this driver is required to be instantiated from device tree\n");
1895 /* Get base address */
1896 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1898 dev_err(&pdev->dev, "invalid resource\n");
1902 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1903 NUM_TX_QUEUE, NUM_RX_QUEUE);
1907 pm_runtime_enable(&pdev->dev);
1908 pm_runtime_get_sync(&pdev->dev);
1910 /* The Ether-specific entries in the device structure. */
1911 ndev->base_addr = res->start;
1914 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
1916 if (chip_id == RCAR_GEN3)
1917 irq = platform_get_irq_byname(pdev, "ch22");
1919 irq = platform_get_irq(pdev, 0);
1926 SET_NETDEV_DEV(ndev, &pdev->dev);
1928 priv = netdev_priv(ndev);
1931 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1932 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1933 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1934 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1935 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1936 if (IS_ERR(priv->addr)) {
1937 error = PTR_ERR(priv->addr);
1941 spin_lock_init(&priv->lock);
1942 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1944 priv->phy_interface = of_get_phy_mode(np);
1946 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1947 priv->avb_link_active_low =
1948 of_property_read_bool(np, "renesas,ether-link-active-low");
1950 if (chip_id == RCAR_GEN3) {
1951 irq = platform_get_irq_byname(pdev, "ch24");
1956 priv->emac_irq = irq;
1957 for (i = 0; i < NUM_RX_QUEUE; i++) {
1958 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
1963 priv->rx_irqs[i] = irq;
1965 for (i = 0; i < NUM_TX_QUEUE; i++) {
1966 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
1971 priv->tx_irqs[i] = irq;
1975 priv->chip_id = chip_id;
1978 ndev->netdev_ops = &ravb_netdev_ops;
1979 ndev->ethtool_ops = &ravb_ethtool_ops;
1981 /* Set AVB config mode */
1982 if (chip_id == RCAR_GEN2) {
1983 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1984 /* Set CSEL value */
1985 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1987 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1988 CCC_GAC | CCC_CSEL_HPB);
1992 error = ravb_set_gti(ndev);
1996 /* Request GTI loading */
1997 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
1999 /* Allocate descriptor base address table */
2000 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2001 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2002 &priv->desc_bat_dma, GFP_KERNEL);
2003 if (!priv->desc_bat) {
2005 "Cannot allocate desc base address table (size %d bytes)\n",
2006 priv->desc_bat_size);
2010 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2011 priv->desc_bat[q].die_dt = DT_EOS;
2012 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2014 /* Initialise HW timestamp list */
2015 INIT_LIST_HEAD(&priv->ts_skb_list);
2017 /* Initialise PTP Clock driver */
2018 if (chip_id != RCAR_GEN2)
2019 ravb_ptp_init(ndev, pdev);
2021 /* Debug message level */
2022 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2024 /* Read and set MAC address */
2025 ravb_read_mac_address(ndev, of_get_mac_address(np));
2026 if (!is_valid_ether_addr(ndev->dev_addr)) {
2027 dev_warn(&pdev->dev,
2028 "no valid MAC address supplied, using a random one\n");
2029 eth_hw_addr_random(ndev);
2033 error = ravb_mdio_init(priv);
2035 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2039 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2040 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2042 /* Network device register */
2043 error = register_netdev(ndev);
2047 /* Print device information */
2048 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2049 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2051 platform_set_drvdata(pdev, ndev);
2056 netif_napi_del(&priv->napi[RAVB_NC]);
2057 netif_napi_del(&priv->napi[RAVB_BE]);
2058 ravb_mdio_release(priv);
2060 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2061 priv->desc_bat_dma);
2063 /* Stop PTP Clock driver */
2064 if (chip_id != RCAR_GEN2)
2065 ravb_ptp_stop(ndev);
2070 pm_runtime_put(&pdev->dev);
2071 pm_runtime_disable(&pdev->dev);
2075 static int ravb_remove(struct platform_device *pdev)
2077 struct net_device *ndev = platform_get_drvdata(pdev);
2078 struct ravb_private *priv = netdev_priv(ndev);
2080 /* Stop PTP Clock driver */
2081 if (priv->chip_id != RCAR_GEN2)
2082 ravb_ptp_stop(ndev);
2084 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2085 priv->desc_bat_dma);
2086 /* Set reset mode */
2087 ravb_write(ndev, CCC_OPC_RESET, CCC);
2088 pm_runtime_put_sync(&pdev->dev);
2089 unregister_netdev(ndev);
2090 netif_napi_del(&priv->napi[RAVB_NC]);
2091 netif_napi_del(&priv->napi[RAVB_BE]);
2092 ravb_mdio_release(priv);
2093 pm_runtime_disable(&pdev->dev);
2095 platform_set_drvdata(pdev, NULL);
2101 static int ravb_runtime_nop(struct device *dev)
2103 /* Runtime PM callback shared between ->runtime_suspend()
2104 * and ->runtime_resume(). Simply returns success.
2106 * This driver re-initializes all registers after
2107 * pm_runtime_get_sync() anyway so there is no need
2108 * to save and restore registers here.
2113 static const struct dev_pm_ops ravb_dev_pm_ops = {
2114 .runtime_suspend = ravb_runtime_nop,
2115 .runtime_resume = ravb_runtime_nop,
2118 #define RAVB_PM_OPS (&ravb_dev_pm_ops)
2120 #define RAVB_PM_OPS NULL
2123 static struct platform_driver ravb_driver = {
2124 .probe = ravb_probe,
2125 .remove = ravb_remove,
2129 .of_match_table = ravb_match_table,
2133 module_platform_driver(ravb_driver);
2135 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2136 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2137 MODULE_LICENSE("GPL v2");