drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
  53
  54 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  55 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  56
  57 /* VLAN list entry */
  58 struct efx_ef10_vlan {
  59         struct list_head list;
  60         u16 vid;
  61 };
  62
  63 /* Per-VLAN filters information */
  64 struct efx_ef10_filter_vlan {
  65         struct list_head list;
  66         u16 vid;
  67         u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
  68         u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
  69         u16 ucdef;
  70         u16 bcast;
  71         u16 mcdef;
  72 };
  73
  74 struct efx_ef10_dev_addr {
  75         u8 addr[ETH_ALEN];
  76 };
  77
  78 struct efx_ef10_filter_table {
  79 /* The MCDI match masks supported by this fw & hw, in order of priority */
  80         u32 rx_match_mcdi_flags[
  81                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  82         unsigned int rx_match_count;
  83
  84         struct {
  85                 unsigned long spec;     /* pointer to spec plus flag bits */
  86 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  87  * used to mark and sweep MAC filters for the device address lists.
  88  */
  89 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  91 #define EFX_EF10_FILTER_FLAGS           3UL
  92                 u64 handle;             /* firmware handle */
  93         } *entry;
  94         wait_queue_head_t waitq;
  95 /* Shadow of net_device address lists, guarded by mac_lock */
  96         struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
  97         struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  98         int dev_uc_count;
  99         int dev_mc_count;
 100         bool uc_promisc;
 101         bool mc_promisc;
 102 /* Whether in multicast promiscuous mode when last changed */
 103         bool mc_promisc_last;
 104         bool vlan_filter;
 105         struct list_head vlan_list;
 106 };
 107
 108 /* An arbitrary search limit for the software hash table */
 109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
 110
 111 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
 112 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
 113 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
 114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
 115                                               struct efx_ef10_filter_vlan *vlan);
 116 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
 117
 118 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
 119 {
 120         efx_dword_t reg;
 121
 122         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
 123         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
 124                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
 125 }
 126
 127 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
 128 {
 129         int bar;
 130
 131         bar = efx->type->mem_bar;
 132         return resource_size(&efx->pci_dev->resource[bar]);
 133 }
 134
 135 static bool efx_ef10_is_vf(struct efx_nic *efx)
 136 {
 137         return efx->type->is_vf;
 138 }
 139
 140 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 141 {
 142         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 143         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 144         size_t outlen;
 145         int rc;
 146
 147         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 148                           sizeof(outbuf), &outlen);
 149         if (rc)
 150                 return rc;
 151         if (outlen < sizeof(outbuf))
 152                 return -EIO;
 153
 154         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 155         return 0;
 156 }
 157
 158 #ifdef CONFIG_SFC_SRIOV
 159 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 160 {
 161         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 162         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 163         size_t outlen;
 164         int rc;
 165
 166         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 167                           sizeof(outbuf), &outlen);
 168         if (rc)
 169                 return rc;
 170         if (outlen < sizeof(outbuf))
 171                 return -EIO;
 172
 173         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 174         return 0;
 175 }
 176 #endif
 177
 178 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 179 {
 180         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
 181         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 182         size_t outlen;
 183         int rc;
 184
 185         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 186
 187         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 188                           outbuf, sizeof(outbuf), &outlen);
 189         if (rc)
 190                 return rc;
 191         if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
 192                 netif_err(efx, drv, efx->net_dev,
 193                           "unable to read datapath firmware capabilities\n");
 194                 return -EIO;
 195         }
 196
 197         nic_data->datapath_caps =
 198                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 199
 200         if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
 201                 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
 202                                 GET_CAPABILITIES_V2_OUT_FLAGS2);
 203         else
 204                 nic_data->datapath_caps2 = 0;
 205
 206         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 207          */
 208         nic_data->rx_dpcpu_fw_id =
 209                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 210         nic_data->tx_dpcpu_fw_id =
 211                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 212
 213         if (!(nic_data->datapath_caps &
 214               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 215                 netif_err(efx, probe, efx->net_dev,
 216                           "current firmware does not support an RX prefix\n");
 217                 return -ENODEV;
 218         }
 219
 220         return 0;
 221 }
 222
 223 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 224 {
 225         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 226         int rc;
 227
 228         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 229                           outbuf, sizeof(outbuf), NULL);
 230         if (rc)
 231                 return rc;
 232         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 233         return rc > 0 ? rc : -ERANGE;
 234 }
 235
 236 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
 237 {
 238         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 239         unsigned int implemented;
 240         unsigned int enabled;
 241         int rc;
 242
 243         nic_data->workaround_35388 = false;
 244         nic_data->workaround_61265 = false;
 245
 246         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
 247
 248         if (rc == -ENOSYS) {
 249                 /* Firmware without GET_WORKAROUNDS - not a problem. */
 250                 rc = 0;
 251         } else if (rc == 0) {
 252                 /* Bug61265 workaround is always enabled if implemented. */
 253                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
 254                         nic_data->workaround_61265 = true;
 255
 256                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 257                         nic_data->workaround_35388 = true;
 258                 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 259                         /* Workaround is implemented but not enabled.
 260                          * Try to enable it.
 261                          */
 262                         rc = efx_mcdi_set_workaround(efx,
 263                                                      MC_CMD_WORKAROUND_BUG35388,
 264                                                      true, NULL);
 265                         if (rc == 0)
 266                                 nic_data->workaround_35388 = true;
 267                         /* If we failed to set the workaround just carry on. */
 268                         rc = 0;
 269                 }
 270         }
 271
 272         netif_dbg(efx, probe, efx->net_dev,
 273                   "workaround for bug 35388 is %sabled\n",
 274                   nic_data->workaround_35388 ? "en" : "dis");
 275         netif_dbg(efx, probe, efx->net_dev,
 276                   "workaround for bug 61265 is %sabled\n",
 277                   nic_data->workaround_61265 ? "en" : "dis");
 278
 279         return rc;
 280 }
 281
 282 static void efx_ef10_process_timer_config(struct efx_nic *efx,
 283                                           const efx_dword_t *data)
 284 {
 285         unsigned int max_count;
 286
 287         if (EFX_EF10_WORKAROUND_61265(efx)) {
 288                 efx->timer_quantum_ns = MCDI_DWORD(data,
 289                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
 290                 efx->timer_max_ns = MCDI_DWORD(data,
 291                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
 292         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
 293                 efx->timer_quantum_ns = MCDI_DWORD(data,
 294                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
 295                 max_count = MCDI_DWORD(data,
 296                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
 297                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 298         } else {
 299                 efx->timer_quantum_ns = MCDI_DWORD(data,
 300                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
 301                 max_count = MCDI_DWORD(data,
 302                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
 303                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 304         }
 305
 306         netif_dbg(efx, probe, efx->net_dev,
 307                   "got timer properties from MC: quantum %u ns; max %u ns\n",
 308                   efx->timer_quantum_ns, efx->timer_max_ns);
 309 }
 310
 311 static int efx_ef10_get_timer_config(struct efx_nic *efx)
 312 {
 313         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
 314         int rc;
 315
 316         rc = efx_ef10_get_timer_workarounds(efx);
 317         if (rc)
 318                 return rc;
 319
 320         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
 321                                 outbuf, sizeof(outbuf), NULL);
 322
 323         if (rc == 0) {
 324                 efx_ef10_process_timer_config(efx, outbuf);
 325         } else if (rc == -ENOSYS || rc == -EPERM) {
 326                 /* Not available - fall back to Huntington defaults. */
 327                 unsigned int quantum;
 328
 329                 rc = efx_ef10_get_sysclk_freq(efx);
 330                 if (rc < 0)
 331                         return rc;
 332
 333                 quantum = 1536000 / rc; /* 1536 cycles */
 334                 efx->timer_quantum_ns = quantum;
 335                 efx->timer_max_ns = efx->type->timer_period_max * quantum;
 336                 rc = 0;
 337         } else {
 338                 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
 339                                        MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
 340                                        NULL, 0, rc);
 341         }
 342
 343         return rc;
 344 }
 345
 346 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 347 {
 348         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 349         size_t outlen;
 350         int rc;
 351
 352         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 353
 354         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 355                           outbuf, sizeof(outbuf), &outlen);
 356         if (rc)
 357                 return rc;
 358         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 359                 return -EIO;
 360
 361         ether_addr_copy(mac_address,
 362                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 363         return 0;
 364 }
 365
 366 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 367 {
 368         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 369         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 370         size_t outlen;
 371         int num_addrs, rc;
 372
 373         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 374                        EVB_PORT_ID_ASSIGNED);
 375         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 376                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 377
 378         if (rc)
 379                 return rc;
 380         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 381                 return -EIO;
 382
 383         num_addrs = MCDI_DWORD(outbuf,
 384                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 385
 386         WARN_ON(num_addrs != 1);
 387
 388         ether_addr_copy(mac_address,
 389                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 390
 391         return 0;
 392 }
 393
 394 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 395                                                struct device_attribute *attr,
 396                                                char *buf)
 397 {
 398         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 399
 400         return sprintf(buf, "%d\n",
 401                        ((efx->mcdi->fn_flags) &
 402                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 403                        ? 1 : 0);
 404 }
 405
 406 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 407                                           struct device_attribute *attr,
 408                                           char *buf)
 409 {
 410         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 411
 412         return sprintf(buf, "%d\n",
 413                        ((efx->mcdi->fn_flags) &
 414                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 415                        ? 1 : 0);
 416 }
 417
 418 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
 419 {
 420         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 421         struct efx_ef10_vlan *vlan;
 422
 423         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 424
 425         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
 426                 if (vlan->vid == vid)
 427                         return vlan;
 428         }
 429
 430         return NULL;
 431 }
 432
 433 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
 434 {
 435         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 436         struct efx_ef10_vlan *vlan;
 437         int rc;
 438
 439         mutex_lock(&nic_data->vlan_lock);
 440
 441         vlan = efx_ef10_find_vlan(efx, vid);
 442         if (vlan) {
 443                 /* We add VID 0 on init. 8021q adds it on module init
 444                  * for all interfaces with VLAN filtring feature.
 445                  */
 446                 if (vid == 0)
 447                         goto done_unlock;
 448                 netif_warn(efx, drv, efx->net_dev,
 449                            "VLAN %u already added\n", vid);
 450                 rc = -EALREADY;
 451                 goto fail_exist;
 452         }
 453
 454         rc = -ENOMEM;
 455         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
 456         if (!vlan)
 457                 goto fail_alloc;
 458
 459         vlan->vid = vid;
 460
 461         list_add_tail(&vlan->list, &nic_data->vlan_list);
 462
 463         if (efx->filter_state) {
 464                 mutex_lock(&efx->mac_lock);
 465                 down_write(&efx->filter_sem);
 466                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
 467                 up_write(&efx->filter_sem);
 468                 mutex_unlock(&efx->mac_lock);
 469                 if (rc)
 470                         goto fail_filter_add_vlan;
 471         }
 472
 473 done_unlock:
 474         mutex_unlock(&nic_data->vlan_lock);
 475         return 0;
 476
 477 fail_filter_add_vlan:
 478         list_del(&vlan->list);
 479         kfree(vlan);
 480 fail_alloc:
 481 fail_exist:
 482         mutex_unlock(&nic_data->vlan_lock);
 483         return rc;
 484 }
 485
 486 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
 487                                        struct efx_ef10_vlan *vlan)
 488 {
 489         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 490
 491         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 492
 493         if (efx->filter_state) {
 494                 down_write(&efx->filter_sem);
 495                 efx_ef10_filter_del_vlan(efx, vlan->vid);
 496                 up_write(&efx->filter_sem);
 497         }
 498
 499         list_del(&vlan->list);
 500         kfree(vlan);
 501 }
 502
 503 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
 504 {
 505         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 506         struct efx_ef10_vlan *vlan;
 507         int rc = 0;
 508
 509         /* 8021q removes VID 0 on module unload for all interfaces
 510          * with VLAN filtering feature. We need to keep it to receive
 511          * untagged traffic.
 512          */
 513         if (vid == 0)
 514                 return 0;
 515
 516         mutex_lock(&nic_data->vlan_lock);
 517
 518         vlan = efx_ef10_find_vlan(efx, vid);
 519         if (!vlan) {
 520                 netif_err(efx, drv, efx->net_dev,
 521                           "VLAN %u to be deleted not found\n", vid);
 522                 rc = -ENOENT;
 523         } else {
 524                 efx_ef10_del_vlan_internal(efx, vlan);
 525         }
 526
 527         mutex_unlock(&nic_data->vlan_lock);
 528
 529         return rc;
 530 }
 531
 532 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
 533 {
 534         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 535         struct efx_ef10_vlan *vlan, *next_vlan;
 536
 537         mutex_lock(&nic_data->vlan_lock);
 538         list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
 539                 efx_ef10_del_vlan_internal(efx, vlan);
 540         mutex_unlock(&nic_data->vlan_lock);
 541 }
 542
 543 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 544                    NULL);
 545 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 546
 547 static int efx_ef10_probe(struct efx_nic *efx)
 548 {
 549         struct efx_ef10_nic_data *nic_data;
 550         struct net_device *net_dev = efx->net_dev;
 551         int i, rc;
 552
 553         /* We can have one VI for each 8K region.  However, until we
 554          * use TX option descriptors we need two TX queues per channel.
 555          */
 556         efx->max_channels = min_t(unsigned int,
 557                                   EFX_MAX_CHANNELS,
 558                                   efx_ef10_mem_map_size(efx) /
 559                                   (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 560         efx->max_tx_channels = efx->max_channels;
 561         if (WARN_ON(efx->max_channels == 0))
 562                 return -EIO;
 563
 564         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 565         if (!nic_data)
 566                 return -ENOMEM;
 567         efx->nic_data = nic_data;
 568
 569         /* we assume later that we can copy from this buffer in dwords */
 570         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 571
 572         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 573                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 574         if (rc)
 575                 goto fail1;
 576
 577         /* Get the MC's warm boot count.  In case it's rebooting right
 578          * now, be prepared to retry.
 579          */
 580         i = 0;
 581         for (;;) {
 582                 rc = efx_ef10_get_warm_boot_count(efx);
 583                 if (rc >= 0)
 584                         break;
 585                 if (++i == 5)
 586                         goto fail2;
 587                 ssleep(1);
 588         }
 589         nic_data->warm_boot_count = rc;
 590
 591         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 592
 593         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 594
 595         /* In case we're recovering from a crash (kexec), we want to
 596          * cancel any outstanding request by the previous user of this
 597          * function.  We send a special message using the least
 598          * significant bits of the 'high' (doorbell) register.
 599          */
 600         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 601
 602         rc = efx_mcdi_init(efx);
 603         if (rc)
 604                 goto fail2;
 605
 606         /* Reset (most) configuration for this function */
 607         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 608         if (rc)
 609                 goto fail3;
 610
 611         /* Enable event logging */
 612         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 613         if (rc)
 614                 goto fail3;
 615
 616         rc = device_create_file(&efx->pci_dev->dev,
 617                                 &dev_attr_link_control_flag);
 618         if (rc)
 619                 goto fail3;
 620
 621         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 622         if (rc)
 623                 goto fail4;
 624
 625         rc = efx_ef10_get_pf_index(efx);
 626         if (rc)
 627                 goto fail5;
 628
 629         rc = efx_ef10_init_datapath_caps(efx);
 630         if (rc < 0)
 631                 goto fail5;
 632
 633         efx->rx_packet_len_offset =
 634                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 635
 636         rc = efx_mcdi_port_get_number(efx);
 637         if (rc < 0)
 638                 goto fail5;
 639         efx->port_num = rc;
 640         net_dev->dev_port = rc;
 641
 642         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 643         if (rc)
 644                 goto fail5;
 645
 646         rc = efx_ef10_get_timer_config(efx);
 647         if (rc < 0)
 648                 goto fail5;
 649         efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
 650
 651         rc = efx_mcdi_mon_probe(efx);
 652         if (rc && rc != -EPERM)
 653                 goto fail5;
 654
 655         efx_ptp_probe(efx, NULL);
 656
 657 #ifdef CONFIG_SFC_SRIOV
 658         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 659                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 660                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 661
 662                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 663         } else
 664 #endif
 665                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 666
 667         INIT_LIST_HEAD(&nic_data->vlan_list);
 668         mutex_init(&nic_data->vlan_lock);
 669
 670         /* Add unspecified VID to support VLAN filtering being disabled */
 671         rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
 672         if (rc)
 673                 goto fail_add_vid_unspec;
 674
 675         /* If VLAN filtering is enabled, we need VID 0 to get untagged
 676          * traffic.  It is added automatically if 8021q module is loaded,
 677          * but we can't rely on it since module may be not loaded.
 678          */
 679         rc = efx_ef10_add_vlan(efx, 0);
 680         if (rc)
 681                 goto fail_add_vid_0;
 682
 683         return 0;
 684
 685 fail_add_vid_0:
 686         efx_ef10_cleanup_vlans(efx);
 687 fail_add_vid_unspec:
 688         mutex_destroy(&nic_data->vlan_lock);
 689         efx_ptp_remove(efx);
 690         efx_mcdi_mon_remove(efx);
 691 fail5:
 692         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 693 fail4:
 694         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 695 fail3:
 696         efx_mcdi_fini(efx);
 697 fail2:
 698         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 699 fail1:
 700         kfree(nic_data);
 701         efx->nic_data = NULL;
 702         return rc;
 703 }
 704
 705 static int efx_ef10_free_vis(struct efx_nic *efx)
 706 {
 707         MCDI_DECLARE_BUF_ERR(outbuf);
 708         size_t outlen;
 709         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 710                                     outbuf, sizeof(outbuf), &outlen);
 711
 712         /* -EALREADY means nothing to free, so ignore */
 713         if (rc == -EALREADY)
 714                 rc = 0;
 715         if (rc)
 716                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 717                                        rc);
 718         return rc;
 719 }
 720
 721 #ifdef EFX_USE_PIO
 722
 723 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 724 {
 725         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 726         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 727         unsigned int i;
 728         int rc;
 729
 730         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 731
 732         for (i = 0; i < nic_data->n_piobufs; i++) {
 733                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 734                                nic_data->piobuf_handle[i]);
 735                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 736                                   NULL, 0, NULL);
 737                 WARN_ON(rc);
 738         }
 739
 740         nic_data->n_piobufs = 0;
 741 }
 742
 743 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 744 {
 745         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 746         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 747         unsigned int i;
 748         size_t outlen;
 749         int rc = 0;
 750
 751         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 752
 753         for (i = 0; i < n; i++) {
 754                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 755                                         outbuf, sizeof(outbuf), &outlen);
 756                 if (rc) {
 757                         /* Don't display the MC error if we didn't have space
 758                          * for a VF.
 759                          */
 760                         if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
 761                                 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
 762                                                        0, outbuf, outlen, rc);
 763                         break;
 764                 }
 765                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 766                         rc = -EIO;
 767                         break;
 768                 }
 769                 nic_data->piobuf_handle[i] =
 770                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 771                 netif_dbg(efx, probe, efx->net_dev,
 772                           "allocated PIO buffer %u handle %x\n", i,
 773                           nic_data->piobuf_handle[i]);
 774         }
 775
 776         nic_data->n_piobufs = i;
 777         if (rc)
 778                 efx_ef10_free_piobufs(efx);
 779         return rc;
 780 }
 781
 782 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 783 {
 784         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 785         _MCDI_DECLARE_BUF(inbuf,
 786                           max(MC_CMD_LINK_PIOBUF_IN_LEN,
 787                               MC_CMD_UNLINK_PIOBUF_IN_LEN));
 788         struct efx_channel *channel;
 789         struct efx_tx_queue *tx_queue;
 790         unsigned int offset, index;
 791         int rc;
 792
 793         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 794         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 795
 796         memset(inbuf, 0, sizeof(inbuf));
 797
 798         /* Link a buffer to each VI in the write-combining mapping */
 799         for (index = 0; index < nic_data->n_piobufs; ++index) {
 800                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 801                                nic_data->piobuf_handle[index]);
 802                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 803                                nic_data->pio_write_vi_base + index);
 804                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 805                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 806                                   NULL, 0, NULL);
 807                 if (rc) {
 808                         netif_err(efx, drv, efx->net_dev,
 809                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 810                                   nic_data->pio_write_vi_base + index, index,
 811                                   rc);
 812                         goto fail;
 813                 }
 814                 netif_dbg(efx, probe, efx->net_dev,
 815                           "linked VI %u to PIO buffer %u\n",
 816                           nic_data->pio_write_vi_base + index, index);
 817         }
 818
 819         /* Link a buffer to each TX queue */
 820         efx_for_each_channel(channel, efx) {
 821                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 822                         /* We assign the PIO buffers to queues in
 823                          * reverse order to allow for the following
 824                          * special case.
 825                          */
 826                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 827                                    tx_queue->channel->channel - 1) *
 828                                   efx_piobuf_size);
 829                         index = offset / ER_DZ_TX_PIOBUF_SIZE;
 830                         offset = offset % ER_DZ_TX_PIOBUF_SIZE;
 831
 832                         /* When the host page size is 4K, the first
 833                          * host page in the WC mapping may be within
 834                          * the same VI page as the last TX queue.  We
 835                          * can only link one buffer to each VI.
 836                          */
 837                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 838                                 BUG_ON(index != 0);
 839                                 rc = 0;
 840                         } else {
 841                                 MCDI_SET_DWORD(inbuf,
 842                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 843                                                nic_data->piobuf_handle[index]);
 844                                 MCDI_SET_DWORD(inbuf,
 845                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 846                                                tx_queue->queue);
 847                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 848                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 849                                                   NULL, 0, NULL);
 850                         }
 851
 852                         if (rc) {
 853                                 /* This is non-fatal; the TX path just
 854                                  * won't use PIO for this queue
 855                                  */
 856                                 netif_err(efx, drv, efx->net_dev,
 857                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 858                                           tx_queue->queue, index, rc);
 859                                 tx_queue->piobuf = NULL;
 860                         } else {
 861                                 tx_queue->piobuf =
 862                                         nic_data->pio_write_base +
 863                                         index * EFX_VI_PAGE_SIZE + offset;
 864                                 tx_queue->piobuf_offset = offset;
 865                                 netif_dbg(efx, probe, efx->net_dev,
 866                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 867                                           tx_queue->queue, index,
 868                                           tx_queue->piobuf_offset,
 869                                           tx_queue->piobuf);
 870                         }
 871                 }
 872         }
 873
 874         return 0;
 875
 876 fail:
 877         while (index--) {
 878                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 879                                nic_data->pio_write_vi_base + index);
 880                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 881                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 882                              NULL, 0, NULL);
 883         }
 884         return rc;
 885 }
 886
 887 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
 888 {
 889         struct efx_channel *channel;
 890         struct efx_tx_queue *tx_queue;
 891
 892         /* All our existing PIO buffers went away */
 893         efx_for_each_channel(channel, efx)
 894                 efx_for_each_channel_tx_queue(tx_queue, channel)
 895                         tx_queue->piobuf = NULL;
 896 }
 897
 898 #else /* !EFX_USE_PIO */
 899
 900 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 901 {
 902         return n == 0 ? 0 : -ENOBUFS;
 903 }
 904
 905 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 906 {
 907         return 0;
 908 }
 909
 910 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 911 {
 912 }
 913
 914 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
 915 {
 916 }
 917
 918 #endif /* EFX_USE_PIO */
 919
 920 static void efx_ef10_remove(struct efx_nic *efx)
 921 {
 922         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 923         int rc;
 924
 925 #ifdef CONFIG_SFC_SRIOV
 926         struct efx_ef10_nic_data *nic_data_pf;
 927         struct pci_dev *pci_dev_pf;
 928         struct efx_nic *efx_pf;
 929         struct ef10_vf *vf;
 930
 931         if (efx->pci_dev->is_virtfn) {
 932                 pci_dev_pf = efx->pci_dev->physfn;
 933                 if (pci_dev_pf) {
 934                         efx_pf = pci_get_drvdata(pci_dev_pf);
 935                         nic_data_pf = efx_pf->nic_data;
 936                         vf = nic_data_pf->vf + nic_data->vf_index;
 937                         vf->efx = NULL;
 938                 } else
 939                         netif_info(efx, drv, efx->net_dev,
 940                                    "Could not get the PF id from VF\n");
 941         }
 942 #endif
 943
 944         efx_ef10_cleanup_vlans(efx);
 945         mutex_destroy(&nic_data->vlan_lock);
 946
 947         efx_ptp_remove(efx);
 948
 949         efx_mcdi_mon_remove(efx);
 950
 951         efx_ef10_rx_free_indir_table(efx);
 952
 953         if (nic_data->wc_membase)
 954                 iounmap(nic_data->wc_membase);
 955
 956         rc = efx_ef10_free_vis(efx);
 957         WARN_ON(rc != 0);
 958
 959         if (!nic_data->must_restore_piobufs)
 960                 efx_ef10_free_piobufs(efx);
 961
 962         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 963         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 964
 965         efx_mcdi_fini(efx);
 966         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 967         kfree(nic_data);
 968 }
 969
 970 static int efx_ef10_probe_pf(struct efx_nic *efx)
 971 {
 972         return efx_ef10_probe(efx);
 973 }
 974
 975 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
 976                             u32 *port_flags, u32 *vadaptor_flags,
 977                             unsigned int *vlan_tags)
 978 {
 979         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 980         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
 981         MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
 982         size_t outlen;
 983         int rc;
 984
 985         if (nic_data->datapath_caps &
 986             (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
 987                 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
 988                                port_id);
 989
 990                 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
 991                                   outbuf, sizeof(outbuf), &outlen);
 992                 if (rc)
 993                         return rc;
 994
 995                 if (outlen < sizeof(outbuf)) {
 996                         rc = -EIO;
 997                         return rc;
 998                 }
 999         }
1000
1001         if (port_flags)
1002                 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1003         if (vadaptor_flags)
1004                 *vadaptor_flags =
1005                         MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1006         if (vlan_tags)
1007                 *vlan_tags =
1008                         MCDI_DWORD(outbuf,
1009                                    VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1010
1011         return 0;
1012 }
1013
1014 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1015 {
1016         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1017
1018         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1019         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1020                             NULL, 0, NULL);
1021 }
1022
1023 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1024 {
1025         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1026
1027         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1028         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1029                             NULL, 0, NULL);
1030 }
1031
1032 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1033                            unsigned int port_id, u8 *mac)
1034 {
1035         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1036
1037         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1038         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1039
1040         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1041                             sizeof(inbuf), NULL, 0, NULL);
1042 }
1043
1044 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1045                            unsigned int port_id, u8 *mac)
1046 {
1047         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1048
1049         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1050         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1051
1052         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1053                             sizeof(inbuf), NULL, 0, NULL);
1054 }
1055
1056 #ifdef CONFIG_SFC_SRIOV
1057 static int efx_ef10_probe_vf(struct efx_nic *efx)
1058 {
1059         int rc;
1060         struct pci_dev *pci_dev_pf;
1061
1062         /* If the parent PF has no VF data structure, it doesn't know about this
1063          * VF so fail probe.  The VF needs to be re-created.  This can happen
1064          * if the PF driver is unloaded while the VF is assigned to a guest.
1065          */
1066         pci_dev_pf = efx->pci_dev->physfn;
1067         if (pci_dev_pf) {
1068                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1069                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1070
1071                 if (!nic_data_pf->vf) {
1072                         netif_info(efx, drv, efx->net_dev,
1073                                    "The VF cannot link to its parent PF; "
1074                                    "please destroy and re-create the VF\n");
1075                         return -EBUSY;
1076                 }
1077         }
1078
1079         rc = efx_ef10_probe(efx);
1080         if (rc)
1081                 return rc;
1082
1083         rc = efx_ef10_get_vf_index(efx);
1084         if (rc)
1085                 goto fail;
1086
1087         if (efx->pci_dev->is_virtfn) {
1088                 if (efx->pci_dev->physfn) {
1089                         struct efx_nic *efx_pf =
1090                                 pci_get_drvdata(efx->pci_dev->physfn);
1091                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1092                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1093
1094                         nic_data_p->vf[nic_data->vf_index].efx = efx;
1095                         nic_data_p->vf[nic_data->vf_index].pci_dev =
1096                                 efx->pci_dev;
1097                 } else
1098                         netif_info(efx, drv, efx->net_dev,
1099                                    "Could not get the PF id from VF\n");
1100         }
1101
1102         return 0;
1103
1104 fail:
1105         efx_ef10_remove(efx);
1106         return rc;
1107 }
1108 #else
1109 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1110 {
1111         return 0;
1112 }
1113 #endif
1114
1115 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1116                               unsigned int min_vis, unsigned int max_vis)
1117 {
1118         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1119         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1120         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1121         size_t outlen;
1122         int rc;
1123
1124         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1125         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1126         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1127                           outbuf, sizeof(outbuf), &outlen);
1128         if (rc != 0)
1129                 return rc;
1130
1131         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1132                 return -EIO;
1133
1134         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1135                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1136
1137         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1138         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1139         return 0;
1140 }
1141
1142 /* Note that the failure path of this function does not free
1143  * resources, as this will be done by efx_ef10_remove().
1144  */
1145 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1146 {
1147         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1148         unsigned int uc_mem_map_size, wc_mem_map_size;
1149         unsigned int min_vis = max(EFX_TXQ_TYPES,
1150                                    efx_separate_tx_channels ? 2 : 1);
1151         unsigned int channel_vis, pio_write_vi_base, max_vis;
1152         void __iomem *membase;
1153         int rc;
1154
1155         channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1156
1157 #ifdef EFX_USE_PIO
1158         /* Try to allocate PIO buffers if wanted and if the full
1159          * number of PIO buffers would be sufficient to allocate one
1160          * copy-buffer per TX channel.  Failure is non-fatal, as there
1161          * are only a small number of PIO buffers shared between all
1162          * functions of the controller.
1163          */
1164         if (efx_piobuf_size != 0 &&
1165             ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1166             efx->n_tx_channels) {
1167                 unsigned int n_piobufs =
1168                         DIV_ROUND_UP(efx->n_tx_channels,
1169                                      ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
1170
1171                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1172                 if (rc)
1173                         netif_err(efx, probe, efx->net_dev,
1174                                   "failed to allocate PIO buffers (%d)\n", rc);
1175                 else
1176                         netif_dbg(efx, probe, efx->net_dev,
1177                                   "allocated %u PIO buffers\n", n_piobufs);
1178         }
1179 #else
1180         nic_data->n_piobufs = 0;
1181 #endif
1182
1183         /* PIO buffers should be mapped with write-combining enabled,
1184          * and we want to make single UC and WC mappings rather than
1185          * several of each (in fact that's the only option if host
1186          * page size is >4K).  So we may allocate some extra VIs just
1187          * for writing PIO buffers through.
1188          *
1189          * The UC mapping contains (channel_vis - 1) complete VIs and the
1190          * first half of the next VI.  Then the WC mapping begins with
1191          * the second half of this last VI.
1192          */
1193         uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
1194                                      ER_DZ_TX_PIOBUF);
1195         if (nic_data->n_piobufs) {
1196                 /* pio_write_vi_base rounds down to give the number of complete
1197                  * VIs inside the UC mapping.
1198                  */
1199                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1200                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1201                                                nic_data->n_piobufs) *
1202                                               EFX_VI_PAGE_SIZE) -
1203                                    uc_mem_map_size);
1204                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1205         } else {
1206                 pio_write_vi_base = 0;
1207                 wc_mem_map_size = 0;
1208                 max_vis = channel_vis;
1209         }
1210
1211         /* In case the last attached driver failed to free VIs, do it now */
1212         rc = efx_ef10_free_vis(efx);
1213         if (rc != 0)
1214                 return rc;
1215
1216         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1217         if (rc != 0)
1218                 return rc;
1219
1220         if (nic_data->n_allocated_vis < channel_vis) {
1221                 netif_info(efx, drv, efx->net_dev,
1222                            "Could not allocate enough VIs to satisfy RSS"
1223                            " requirements. Performance may not be optimal.\n");
1224                 /* We didn't get the VIs to populate our channels.
1225                  * We could keep what we got but then we'd have more
1226                  * interrupts than we need.
1227                  * Instead calculate new max_channels and restart
1228                  */
1229                 efx->max_channels = nic_data->n_allocated_vis;
1230                 efx->max_tx_channels =
1231                         nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1232
1233                 efx_ef10_free_vis(efx);
1234                 return -EAGAIN;
1235         }
1236
1237         /* If we didn't get enough VIs to map all the PIO buffers, free the
1238          * PIO buffers
1239          */
1240         if (nic_data->n_piobufs &&
1241             nic_data->n_allocated_vis <
1242             pio_write_vi_base + nic_data->n_piobufs) {
1243                 netif_dbg(efx, probe, efx->net_dev,
1244                           "%u VIs are not sufficient to map %u PIO buffers\n",
1245                           nic_data->n_allocated_vis, nic_data->n_piobufs);
1246                 efx_ef10_free_piobufs(efx);
1247         }
1248
1249         /* Shrink the original UC mapping of the memory BAR */
1250         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1251         if (!membase) {
1252                 netif_err(efx, probe, efx->net_dev,
1253                           "could not shrink memory BAR to %x\n",
1254                           uc_mem_map_size);
1255                 return -ENOMEM;
1256         }
1257         iounmap(efx->membase);
1258         efx->membase = membase;
1259
1260         /* Set up the WC mapping if needed */
1261         if (wc_mem_map_size) {
1262                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1263                                                   uc_mem_map_size,
1264                                                   wc_mem_map_size);
1265                 if (!nic_data->wc_membase) {
1266                         netif_err(efx, probe, efx->net_dev,
1267                                   "could not allocate WC mapping of size %x\n",
1268                                   wc_mem_map_size);
1269                         return -ENOMEM;
1270                 }
1271                 nic_data->pio_write_vi_base = pio_write_vi_base;
1272                 nic_data->pio_write_base =
1273                         nic_data->wc_membase +
1274                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1275                          uc_mem_map_size);
1276
1277                 rc = efx_ef10_link_piobufs(efx);
1278                 if (rc)
1279                         efx_ef10_free_piobufs(efx);
1280         }
1281
1282         netif_dbg(efx, probe, efx->net_dev,
1283                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1284                   &efx->membase_phys, efx->membase, uc_mem_map_size,
1285                   nic_data->wc_membase, wc_mem_map_size);
1286
1287         return 0;
1288 }
1289
1290 static int efx_ef10_init_nic(struct efx_nic *efx)
1291 {
1292         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1293         int rc;
1294
1295         if (nic_data->must_check_datapath_caps) {
1296                 rc = efx_ef10_init_datapath_caps(efx);
1297                 if (rc)
1298                         return rc;
1299                 nic_data->must_check_datapath_caps = false;
1300         }
1301
1302         if (nic_data->must_realloc_vis) {
1303                 /* We cannot let the number of VIs change now */
1304                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1305                                         nic_data->n_allocated_vis);
1306                 if (rc)
1307                         return rc;
1308                 nic_data->must_realloc_vis = false;
1309         }
1310
1311         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1312                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1313                 if (rc == 0) {
1314                         rc = efx_ef10_link_piobufs(efx);
1315                         if (rc)
1316                                 efx_ef10_free_piobufs(efx);
1317                 }
1318
1319                 /* Log an error on failure, but this is non-fatal */
1320                 if (rc)
1321                         netif_err(efx, drv, efx->net_dev,
1322                                   "failed to restore PIO buffers (%d)\n", rc);
1323                 nic_data->must_restore_piobufs = false;
1324         }
1325
1326         /* don't fail init if RSS setup doesn't work */
1327         efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1328
1329         return 0;
1330 }
1331
1332 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1333 {
1334         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1335 #ifdef CONFIG_SFC_SRIOV
1336         unsigned int i;
1337 #endif
1338
1339         /* All our allocations have been reset */
1340         nic_data->must_realloc_vis = true;
1341         nic_data->must_restore_filters = true;
1342         nic_data->must_restore_piobufs = true;
1343         efx_ef10_forget_old_piobufs(efx);
1344         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1345
1346         /* Driver-created vswitches and vports must be re-created */
1347         nic_data->must_probe_vswitching = true;
1348         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1349 #ifdef CONFIG_SFC_SRIOV
1350         if (nic_data->vf)
1351                 for (i = 0; i < efx->vf_count; i++)
1352                         nic_data->vf[i].vport_id = 0;
1353 #endif
1354 }
1355
1356 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1357 {
1358         if (reason == RESET_TYPE_MC_FAILURE)
1359                 return RESET_TYPE_DATAPATH;
1360
1361         return efx_mcdi_map_reset_reason(reason);
1362 }
1363
1364 static int efx_ef10_map_reset_flags(u32 *flags)
1365 {
1366         enum {
1367                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1368                                    ETH_RESET_SHARED_SHIFT),
1369                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1370                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1371                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1372                                  ETH_RESET_SHARED_SHIFT)
1373         };
1374
1375         /* We assume for now that our PCI function is permitted to
1376          * reset everything.
1377          */
1378
1379         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1380                 *flags &= ~EF10_RESET_MC;
1381                 return RESET_TYPE_WORLD;
1382         }
1383
1384         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1385                 *flags &= ~EF10_RESET_PORT;
1386                 return RESET_TYPE_ALL;
1387         }
1388
1389         /* no invisible reset implemented */
1390
1391         return -EINVAL;
1392 }
1393
1394 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1395 {
1396         int rc = efx_mcdi_reset(efx, reset_type);
1397
1398         /* Unprivileged functions return -EPERM, but need to return success
1399          * here so that the datapath is brought back up.
1400          */
1401         if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1402                 rc = 0;
1403
1404         /* If it was a port reset, trigger reallocation of MC resources.
1405          * Note that on an MC reset nothing needs to be done now because we'll
1406          * detect the MC reset later and handle it then.
1407          * For an FLR, we never get an MC reset event, but the MC has reset all
1408          * resources assigned to us, so we have to trigger reallocation now.
1409          */
1410         if ((reset_type == RESET_TYPE_ALL ||
1411              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1412                 efx_ef10_reset_mc_allocations(efx);
1413         return rc;
1414 }
1415
1416 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1417         [EF10_STAT_ ## ext_name] =                              \
1418         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1419 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1420         [EF10_STAT_ ## int_name] =                              \
1421         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1422 #define EF10_OTHER_STAT(ext_name)                               \
1423         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1424 #define GENERIC_SW_STAT(ext_name)                               \
1425         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1426
1427 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1428         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1429         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1430         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1431         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1432         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1433         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1434         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1435         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1436         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1437         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1438         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1439         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1440         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1441         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1442         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1443         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1444         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1445         EF10_OTHER_STAT(port_rx_good_bytes),
1446         EF10_OTHER_STAT(port_rx_bad_bytes),
1447         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1448         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1449         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1450         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1451         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1452         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1453         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1454         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1455         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1456         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1457         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1458         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1459         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1460         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1461         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1462         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1463         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1464         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1465         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1466         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1467         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1468         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1469         GENERIC_SW_STAT(rx_nodesc_trunc),
1470         GENERIC_SW_STAT(rx_noskb_drops),
1471         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1472         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1473         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1474         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1475         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1476         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1477         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1478         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1479         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1480         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1481         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1482         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1483         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1484         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1485         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1486         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1487         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1488         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1489         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1490         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1491         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1492         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1493         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1494         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1495         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1496         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1497         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1498         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1499         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1500         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1501 };
1502
1503 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1504                                (1ULL << EF10_STAT_port_tx_packets) |    \
1505                                (1ULL << EF10_STAT_port_tx_pause) |      \
1506                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1507                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1508                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1509                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1510                                (1ULL <<                                 \
1511                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1512                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1513                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1514                                (1ULL << EF10_STAT_port_rx_packets) |    \
1515                                (1ULL << EF10_STAT_port_rx_good) |       \
1516                                (1ULL << EF10_STAT_port_rx_bad) |        \
1517                                (1ULL << EF10_STAT_port_rx_pause) |      \
1518                                (1ULL << EF10_STAT_port_rx_control) |    \
1519                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1520                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1521                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1522                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1523                                (1ULL << EF10_STAT_port_rx_64) |         \
1524                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1525                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1526                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1527                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1528                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1529                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1530                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1531                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1532                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1533                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1534                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1535                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1536
1537 /* These statistics are only provided by the 10G MAC.  For a 10G/40G
1538  * switchable port we do not expose these because they might not
1539  * include all the packets they should.
1540  */
1541 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1542                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1543                                  (1ULL << EF10_STAT_port_tx_64) |       \
1544                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1545                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1546                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1547                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1548                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1549                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1550
1551 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1552  * switchable port we do expose these because the errors will otherwise
1553  * be silent.
1554  */
1555 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1556                                   (1ULL << EF10_STAT_port_rx_length_error))
1557
1558 /* These statistics are only provided if the firmware supports the
1559  * capability PM_AND_RXDP_COUNTERS.
1560  */
1561 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1562         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1563         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1564         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1565         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1566         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1567         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1568         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1569         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1570         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1571         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1572         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1573         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1574
1575 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1576 {
1577         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1578         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1579         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1580
1581         if (!(efx->mcdi->fn_flags &
1582               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1583                 return 0;
1584
1585         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1586                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1587         else
1588                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1589
1590         if (nic_data->datapath_caps &
1591             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1592                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1593
1594         return raw_mask;
1595 }
1596
1597 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1598 {
1599         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1600         u64 raw_mask[2];
1601
1602         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1603
1604         /* Only show vadaptor stats when EVB capability is present */
1605         if (nic_data->datapath_caps &
1606             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1607                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1608                 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1609         } else {
1610                 raw_mask[1] = 0;
1611         }
1612
1613 #if BITS_PER_LONG == 64
1614         mask[0] = raw_mask[0];
1615         mask[1] = raw_mask[1];
1616 #else
1617         mask[0] = raw_mask[0] & 0xffffffff;
1618         mask[1] = raw_mask[0] >> 32;
1619         mask[2] = raw_mask[1] & 0xffffffff;
1620         mask[3] = raw_mask[1] >> 32;
1621 #endif
1622 }
1623
1624 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1625 {
1626         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1627
1628         efx_ef10_get_stat_mask(efx, mask);
1629         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1630                                       mask, names);
1631 }
1632
1633 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1634                                            struct rtnl_link_stats64 *core_stats)
1635 {
1636         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1637         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1638         u64 *stats = nic_data->stats;
1639         size_t stats_count = 0, index;
1640
1641         efx_ef10_get_stat_mask(efx, mask);
1642
1643         if (full_stats) {
1644                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1645                         if (efx_ef10_stat_desc[index].name) {
1646                                 *full_stats++ = stats[index];
1647                                 ++stats_count;
1648                         }
1649                 }
1650         }
1651
1652         if (!core_stats)
1653                 return stats_count;
1654
1655         if (nic_data->datapath_caps &
1656                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1657                 /* Use vadaptor stats. */
1658                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1659                                          stats[EF10_STAT_rx_multicast] +
1660                                          stats[EF10_STAT_rx_broadcast];
1661                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1662                                          stats[EF10_STAT_tx_multicast] +
1663                                          stats[EF10_STAT_tx_broadcast];
1664                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1665                                        stats[EF10_STAT_rx_multicast_bytes] +
1666                                        stats[EF10_STAT_rx_broadcast_bytes];
1667                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1668                                        stats[EF10_STAT_tx_multicast_bytes] +
1669                                        stats[EF10_STAT_tx_broadcast_bytes];
1670                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1671                                          stats[GENERIC_STAT_rx_noskb_drops];
1672                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1673                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1674                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1675                 core_stats->rx_errors = core_stats->rx_crc_errors;
1676                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1677         } else {
1678                 /* Use port stats. */
1679                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1680                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1681                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1682                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1683                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1684                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1685                                          stats[GENERIC_STAT_rx_noskb_drops];
1686                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1687                 core_stats->rx_length_errors =
1688                                 stats[EF10_STAT_port_rx_gtjumbo] +
1689                                 stats[EF10_STAT_port_rx_length_error];
1690                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1691                 core_stats->rx_frame_errors =
1692                                 stats[EF10_STAT_port_rx_align_error];
1693                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1694                 core_stats->rx_errors = (core_stats->rx_length_errors +
1695                                          core_stats->rx_crc_errors +
1696                                          core_stats->rx_frame_errors);
1697         }
1698
1699         return stats_count;
1700 }
1701
1702 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1703 {
1704         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1705         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1706         __le64 generation_start, generation_end;
1707         u64 *stats = nic_data->stats;
1708         __le64 *dma_stats;
1709
1710         efx_ef10_get_stat_mask(efx, mask);
1711
1712         dma_stats = efx->stats_buffer.addr;
1713         nic_data = efx->nic_data;
1714
1715         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1716         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1717                 return 0;
1718         rmb();
1719         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1720                              stats, efx->stats_buffer.addr, false);
1721         rmb();
1722         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1723         if (generation_end != generation_start)
1724                 return -EAGAIN;
1725
1726         /* Update derived statistics */
1727         efx_nic_fix_nodesc_drop_stat(efx,
1728                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1729         stats[EF10_STAT_port_rx_good_bytes] =
1730                 stats[EF10_STAT_port_rx_bytes] -
1731                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1732         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1733                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1734         efx_update_sw_stats(efx, stats);
1735         return 0;
1736 }
1737
1738
1739 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1740                                        struct rtnl_link_stats64 *core_stats)
1741 {
1742         int retry;
1743
1744         /* If we're unlucky enough to read statistics during the DMA, wait
1745          * up to 10ms for it to finish (typically takes <500us)
1746          */
1747         for (retry = 0; retry < 100; ++retry) {
1748                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1749                         break;
1750                 udelay(100);
1751         }
1752
1753         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1754 }
1755
1756 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1757 {
1758         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1759         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1760         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1761         __le64 generation_start, generation_end;
1762         u64 *stats = nic_data->stats;
1763         u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1764         struct efx_buffer stats_buf;
1765         __le64 *dma_stats;
1766         int rc;
1767
1768         spin_unlock_bh(&efx->stats_lock);
1769
1770         if (in_interrupt()) {
1771                 /* If in atomic context, cannot update stats.  Just update the
1772                  * software stats and return so the caller can continue.
1773                  */
1774                 spin_lock_bh(&efx->stats_lock);
1775                 efx_update_sw_stats(efx, stats);
1776                 return 0;
1777         }
1778
1779         efx_ef10_get_stat_mask(efx, mask);
1780
1781         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1782         if (rc) {
1783                 spin_lock_bh(&efx->stats_lock);
1784                 return rc;
1785         }
1786
1787         dma_stats = stats_buf.addr;
1788         dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1789
1790         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1791         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1792                               MAC_STATS_IN_DMA, 1);
1793         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1794         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1795
1796         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1797                                 NULL, 0, NULL);
1798         spin_lock_bh(&efx->stats_lock);
1799         if (rc) {
1800                 /* Expect ENOENT if DMA queues have not been set up */
1801                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1802                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1803                                                sizeof(inbuf), NULL, 0, rc);
1804                 goto out;
1805         }
1806
1807         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1808         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1809                 WARN_ON_ONCE(1);
1810                 goto out;
1811         }
1812         rmb();
1813         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1814                              stats, stats_buf.addr, false);
1815         rmb();
1816         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1817         if (generation_end != generation_start) {
1818                 rc = -EAGAIN;
1819                 goto out;
1820         }
1821
1822         efx_update_sw_stats(efx, stats);
1823 out:
1824         efx_nic_free_buffer(efx, &stats_buf);
1825         return rc;
1826 }
1827
1828 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1829                                        struct rtnl_link_stats64 *core_stats)
1830 {
1831         if (efx_ef10_try_update_nic_stats_vf(efx))
1832                 return 0;
1833
1834         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1835 }
1836
1837 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1838 {
1839         struct efx_nic *efx = channel->efx;
1840         unsigned int mode, usecs;
1841         efx_dword_t timer_cmd;
1842
1843         if (channel->irq_moderation_us) {
1844                 mode = 3;
1845                 usecs = channel->irq_moderation_us;
1846         } else {
1847                 mode = 0;
1848                 usecs = 0;
1849         }
1850
1851         if (EFX_EF10_WORKAROUND_61265(efx)) {
1852                 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1853                 unsigned int ns = usecs * 1000;
1854
1855                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1856                                channel->channel);
1857                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1858                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1859                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1860
1861                 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1862                                    inbuf, sizeof(inbuf), 0, NULL, 0);
1863         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1864                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1865
1866                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1867                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1868                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1869                                      ERF_DD_EVQ_IND_TIMER_VAL, ticks);
1870                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1871                                 channel->channel);
1872         } else {
1873                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1874
1875                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1876                                      ERF_DZ_TC_TIMER_VAL, ticks);
1877                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1878                                 channel->channel);
1879         }
1880 }
1881
1882 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1883                                 struct ethtool_wolinfo *wol) {}
1884
1885 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1886 {
1887         return -EOPNOTSUPP;
1888 }
1889
1890 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1891 {
1892         wol->supported = 0;
1893         wol->wolopts = 0;
1894         memset(&wol->sopass, 0, sizeof(wol->sopass));
1895 }
1896
1897 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1898 {
1899         if (type != 0)
1900                 return -EINVAL;
1901         return 0;
1902 }
1903
1904 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1905                                   const efx_dword_t *hdr, size_t hdr_len,
1906                                   const efx_dword_t *sdu, size_t sdu_len)
1907 {
1908         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1909         u8 *pdu = nic_data->mcdi_buf.addr;
1910
1911         memcpy(pdu, hdr, hdr_len);
1912         memcpy(pdu + hdr_len, sdu, sdu_len);
1913         wmb();
1914
1915         /* The hardware provides 'low' and 'high' (doorbell) registers
1916          * for passing the 64-bit address of an MCDI request to
1917          * firmware.  However the dwords are swapped by firmware.  The
1918          * least significant bits of the doorbell are then 0 for all
1919          * MCDI requests due to alignment.
1920          */
1921         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1922                     ER_DZ_MC_DB_LWRD);
1923         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1924                     ER_DZ_MC_DB_HWRD);
1925 }
1926
1927 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1928 {
1929         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1930         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1931
1932         rmb();
1933         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1934 }
1935
1936 static void
1937 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1938                             size_t offset, size_t outlen)
1939 {
1940         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1941         const u8 *pdu = nic_data->mcdi_buf.addr;
1942
1943         memcpy(outbuf, pdu + offset, outlen);
1944 }
1945
1946 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1947 {
1948         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1949
1950         /* All our allocations have been reset */
1951         efx_ef10_reset_mc_allocations(efx);
1952
1953         /* The datapath firmware might have been changed */
1954         nic_data->must_check_datapath_caps = true;
1955
1956         /* MAC statistics have been cleared on the NIC; clear the local
1957          * statistic that we update with efx_update_diff_stat().
1958          */
1959         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1960 }
1961
1962 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1963 {
1964         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1965         int rc;
1966
1967         rc = efx_ef10_get_warm_boot_count(efx);
1968         if (rc < 0) {
1969                 /* The firmware is presumably in the process of
1970                  * rebooting.  However, we are supposed to report each
1971                  * reboot just once, so we must only do that once we
1972                  * can read and store the updated warm boot count.
1973                  */
1974                 return 0;
1975         }
1976
1977         if (rc == nic_data->warm_boot_count)
1978                 return 0;
1979
1980         nic_data->warm_boot_count = rc;
1981         efx_ef10_mcdi_reboot_detected(efx);
1982
1983         return -EIO;
1984 }
1985
1986 /* Handle an MSI interrupt
1987  *
1988  * Handle an MSI hardware interrupt.  This routine schedules event
1989  * queue processing.  No interrupt acknowledgement cycle is necessary.
1990  * Also, we never need to check that the interrupt is for us, since
1991  * MSI interrupts cannot be shared.
1992  */
1993 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1994 {
1995         struct efx_msi_context *context = dev_id;
1996         struct efx_nic *efx = context->efx;
1997
1998         netif_vdbg(efx, intr, efx->net_dev,
1999                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2000
2001         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2002                 /* Note test interrupts */
2003                 if (context->index == efx->irq_level)
2004                         efx->last_irq_cpu = raw_smp_processor_id();
2005
2006                 /* Schedule processing of the channel */
2007                 efx_schedule_channel_irq(efx->channel[context->index]);
2008         }
2009
2010         return IRQ_HANDLED;
2011 }
2012
2013 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2014 {
2015         struct efx_nic *efx = dev_id;
2016         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2017         struct efx_channel *channel;
2018         efx_dword_t reg;
2019         u32 queues;
2020
2021         /* Read the ISR which also ACKs the interrupts */
2022         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2023         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2024
2025         if (queues == 0)
2026                 return IRQ_NONE;
2027
2028         if (likely(soft_enabled)) {
2029                 /* Note test interrupts */
2030                 if (queues & (1U << efx->irq_level))
2031                         efx->last_irq_cpu = raw_smp_processor_id();
2032
2033                 efx_for_each_channel(channel, efx) {
2034                         if (queues & 1)
2035                                 efx_schedule_channel_irq(channel);
2036                         queues >>= 1;
2037                 }
2038         }
2039
2040         netif_vdbg(efx, intr, efx->net_dev,
2041                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2042                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2043
2044         return IRQ_HANDLED;
2045 }
2046
2047 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
2048 {
2049         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2050
2051         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2052
2053         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2054         (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2055                             inbuf, sizeof(inbuf), NULL, 0, NULL);
2056 }
2057
2058 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2059 {
2060         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2061                                     (tx_queue->ptr_mask + 1) *
2062                                     sizeof(efx_qword_t),
2063                                     GFP_KERNEL);
2064 }
2065
2066 /* This writes to the TX_DESC_WPTR and also pushes data */
2067 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2068                                          const efx_qword_t *txd)
2069 {
2070         unsigned int write_ptr;
2071         efx_oword_t reg;
2072
2073         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2074         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2075         reg.qword[0] = *txd;
2076         efx_writeo_page(tx_queue->efx, &reg,
2077                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
2078 }
2079
2080 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2081 {
2082         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2083                                                        EFX_BUF_SIZE));
2084         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2085         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2086         struct efx_channel *channel = tx_queue->channel;
2087         struct efx_nic *efx = tx_queue->efx;
2088         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2089         size_t inlen;
2090         dma_addr_t dma_addr;
2091         efx_qword_t *txd;
2092         int rc;
2093         int i;
2094         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2095
2096         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2097         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2098         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2099         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2100         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
2101                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2102                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2103         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2104         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2105
2106         dma_addr = tx_queue->txd.buf.dma_addr;
2107
2108         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2109                   tx_queue->queue, entries, (u64)dma_addr);
2110
2111         for (i = 0; i < entries; ++i) {
2112                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2113                 dma_addr += EFX_BUF_SIZE;
2114         }
2115
2116         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2117
2118         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2119                           NULL, 0, NULL);
2120         if (rc)
2121                 goto fail;
2122
2123         /* A previous user of this TX queue might have set us up the
2124          * bomb by writing a descriptor to the TX push collector but
2125          * not the doorbell.  (Each collector belongs to a port, not a
2126          * queue or function, so cannot easily be reset.)  We must
2127          * attempt to push a no-op descriptor in its place.
2128          */
2129         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2130         tx_queue->insert_count = 1;
2131         txd = efx_tx_desc(tx_queue, 0);
2132         EFX_POPULATE_QWORD_4(*txd,
2133                              ESF_DZ_TX_DESC_IS_OPT, true,
2134                              ESF_DZ_TX_OPTION_TYPE,
2135                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2136                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2137                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2138         tx_queue->write_count = 1;
2139
2140         if (nic_data->datapath_caps &
2141             (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2142                 tx_queue->tso_version = 1;
2143         }
2144
2145         wmb();
2146         efx_ef10_push_tx_desc(tx_queue, txd);
2147
2148         return;
2149
2150 fail:
2151         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2152                     tx_queue->queue);
2153 }
2154
2155 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2156 {
2157         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2158         MCDI_DECLARE_BUF_ERR(outbuf);
2159         struct efx_nic *efx = tx_queue->efx;
2160         size_t outlen;
2161         int rc;
2162
2163         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2164                        tx_queue->queue);
2165
2166         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2167                           outbuf, sizeof(outbuf), &outlen);
2168
2169         if (rc && rc != -EALREADY)
2170                 goto fail;
2171
2172         return;
2173
2174 fail:
2175         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2176                                outbuf, outlen, rc);
2177 }
2178
2179 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2180 {
2181         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2182 }
2183
2184 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2185 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2186 {
2187         unsigned int write_ptr;
2188         efx_dword_t reg;
2189
2190         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2191         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2192         efx_writed_page(tx_queue->efx, &reg,
2193                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2194 }
2195
2196 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2197 {
2198         unsigned int old_write_count = tx_queue->write_count;
2199         struct efx_tx_buffer *buffer;
2200         unsigned int write_ptr;
2201         efx_qword_t *txd;
2202
2203         tx_queue->xmit_more_available = false;
2204         if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2205                 return;
2206
2207         do {
2208                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2209                 buffer = &tx_queue->buffer[write_ptr];
2210                 txd = efx_tx_desc(tx_queue, write_ptr);
2211                 ++tx_queue->write_count;
2212
2213                 /* Create TX descriptor ring entry */
2214                 if (buffer->flags & EFX_TX_BUF_OPTION) {
2215                         *txd = buffer->option;
2216                 } else {
2217                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2218                         EFX_POPULATE_QWORD_3(
2219                                 *txd,
2220                                 ESF_DZ_TX_KER_CONT,
2221                                 buffer->flags & EFX_TX_BUF_CONT,
2222                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2223                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2224                 }
2225         } while (tx_queue->write_count != tx_queue->insert_count);
2226
2227         wmb(); /* Ensure descriptors are written before they are fetched */
2228
2229         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2230                 txd = efx_tx_desc(tx_queue,
2231                                   old_write_count & tx_queue->ptr_mask);
2232                 efx_ef10_push_tx_desc(tx_queue, txd);
2233                 ++tx_queue->pushes;
2234         } else {
2235                 efx_ef10_notify_tx_desc(tx_queue);
2236         }
2237 }
2238
2239 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2240                                       bool exclusive, unsigned *context_size)
2241 {
2242         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2243         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2244         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2245         size_t outlen;
2246         int rc;
2247         u32 alloc_type = exclusive ?
2248                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2249                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2250         unsigned rss_spread = exclusive ?
2251                                 efx->rss_spread :
2252                                 min(rounddown_pow_of_two(efx->rss_spread),
2253                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2254
2255         if (!exclusive && rss_spread == 1) {
2256                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2257                 if (context_size)
2258                         *context_size = 1;
2259                 return 0;
2260         }
2261
2262         if (nic_data->datapath_caps &
2263             1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2264                 return -EOPNOTSUPP;
2265
2266         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2267                        nic_data->vport_id);
2268         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2269         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2270
2271         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2272                 outbuf, sizeof(outbuf), &outlen);
2273         if (rc != 0)
2274                 return rc;
2275
2276         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2277                 return -EIO;
2278
2279         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2280
2281         if (context_size)
2282                 *context_size = rss_spread;
2283
2284         return 0;
2285 }
2286
2287 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2288 {
2289         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2290         int rc;
2291
2292         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2293                        context);
2294
2295         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2296                             NULL, 0, NULL);
2297         WARN_ON(rc != 0);
2298 }
2299
2300 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2301                                        const u32 *rx_indir_table)
2302 {
2303         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2304         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2305         int i, rc;
2306
2307         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2308                        context);
2309         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2310                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2311
2312         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2313                 MCDI_PTR(tablebuf,
2314                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2315                                 (u8) rx_indir_table[i];
2316
2317         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2318                           sizeof(tablebuf), NULL, 0, NULL);
2319         if (rc != 0)
2320                 return rc;
2321
2322         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2323                        context);
2324         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2325                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2326         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2327                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
2328                         efx->rx_hash_key[i];
2329
2330         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2331                             sizeof(keybuf), NULL, 0, NULL);
2332 }
2333
2334 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2335 {
2336         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2337
2338         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2339                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2340         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2341 }
2342
2343 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2344                                               unsigned *context_size)
2345 {
2346         u32 new_rx_rss_context;
2347         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2348         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2349                                             false, context_size);
2350
2351         if (rc != 0)
2352                 return rc;
2353
2354         nic_data->rx_rss_context = new_rx_rss_context;
2355         nic_data->rx_rss_context_exclusive = false;
2356         efx_set_default_rx_indir_table(efx);
2357         return 0;
2358 }
2359
2360 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2361                                                  const u32 *rx_indir_table)
2362 {
2363         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2364         int rc;
2365         u32 new_rx_rss_context;
2366
2367         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2368             !nic_data->rx_rss_context_exclusive) {
2369                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2370                                                 true, NULL);
2371                 if (rc == -EOPNOTSUPP)
2372                         return rc;
2373                 else if (rc != 0)
2374                         goto fail1;
2375         } else {
2376                 new_rx_rss_context = nic_data->rx_rss_context;
2377         }
2378
2379         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2380                                          rx_indir_table);
2381         if (rc != 0)
2382                 goto fail2;
2383
2384         if (nic_data->rx_rss_context != new_rx_rss_context)
2385                 efx_ef10_rx_free_indir_table(efx);
2386         nic_data->rx_rss_context = new_rx_rss_context;
2387         nic_data->rx_rss_context_exclusive = true;
2388         if (rx_indir_table != efx->rx_indir_table)
2389                 memcpy(efx->rx_indir_table, rx_indir_table,
2390                        sizeof(efx->rx_indir_table));
2391         return 0;
2392
2393 fail2:
2394         if (new_rx_rss_context != nic_data->rx_rss_context)
2395                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2396 fail1:
2397         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2398         return rc;
2399 }
2400
2401 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2402                                           const u32 *rx_indir_table)
2403 {
2404         int rc;
2405
2406         if (efx->rss_spread == 1)
2407                 return 0;
2408
2409         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2410
2411         if (rc == -ENOBUFS && !user) {
2412                 unsigned context_size;
2413                 bool mismatch = false;
2414                 size_t i;
2415
2416                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2417                      i++)
2418                         mismatch = rx_indir_table[i] !=
2419                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
2420
2421                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2422                 if (rc == 0) {
2423                         if (context_size != efx->rss_spread)
2424                                 netif_warn(efx, probe, efx->net_dev,
2425                                            "Could not allocate an exclusive RSS"
2426                                            " context; allocated a shared one of"
2427                                            " different size."
2428                                            " Wanted %u, got %u.\n",
2429                                            efx->rss_spread, context_size);
2430                         else if (mismatch)
2431                                 netif_warn(efx, probe, efx->net_dev,
2432                                            "Could not allocate an exclusive RSS"
2433                                            " context; allocated a shared one but"
2434                                            " could not apply custom"
2435                                            " indirection.\n");
2436                         else
2437                                 netif_info(efx, probe, efx->net_dev,
2438                                            "Could not allocate an exclusive RSS"
2439                                            " context; allocated a shared one.\n");
2440                 }
2441         }
2442         return rc;
2443 }
2444
2445 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2446                                           const u32 *rx_indir_table
2447                                           __attribute__ ((unused)))
2448 {
2449         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2450
2451         if (user)
2452                 return -EOPNOTSUPP;
2453         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2454                 return 0;
2455         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2456 }
2457
2458 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2459 {
2460         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2461                                     (rx_queue->ptr_mask + 1) *
2462                                     sizeof(efx_qword_t),
2463                                     GFP_KERNEL);
2464 }
2465
2466 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2467 {
2468         MCDI_DECLARE_BUF(inbuf,
2469                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2470                                                 EFX_BUF_SIZE));
2471         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2472         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2473         struct efx_nic *efx = rx_queue->efx;
2474         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2475         size_t inlen;
2476         dma_addr_t dma_addr;
2477         int rc;
2478         int i;
2479         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2480
2481         rx_queue->scatter_n = 0;
2482         rx_queue->scatter_len = 0;
2483
2484         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2485         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2486         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2487         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2488                        efx_rx_queue_index(rx_queue));
2489         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2490                               INIT_RXQ_IN_FLAG_PREFIX, 1,
2491                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2492         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2493         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2494
2495         dma_addr = rx_queue->rxd.buf.dma_addr;
2496
2497         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2498                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2499
2500         for (i = 0; i < entries; ++i) {
2501                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2502                 dma_addr += EFX_BUF_SIZE;
2503         }
2504
2505         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2506
2507         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2508                           NULL, 0, NULL);
2509         if (rc)
2510                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2511                             efx_rx_queue_index(rx_queue));
2512 }
2513
2514 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2515 {
2516         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2517         MCDI_DECLARE_BUF_ERR(outbuf);
2518         struct efx_nic *efx = rx_queue->efx;
2519         size_t outlen;
2520         int rc;
2521
2522         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2523                        efx_rx_queue_index(rx_queue));
2524
2525         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2526                           outbuf, sizeof(outbuf), &outlen);
2527
2528         if (rc && rc != -EALREADY)
2529                 goto fail;
2530
2531         return;
2532
2533 fail:
2534         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2535                                outbuf, outlen, rc);
2536 }
2537
2538 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2539 {
2540         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2541 }
2542
2543 /* This creates an entry in the RX descriptor queue */
2544 static inline void
2545 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2546 {
2547         struct efx_rx_buffer *rx_buf;
2548         efx_qword_t *rxd;
2549
2550         rxd = efx_rx_desc(rx_queue, index);
2551         rx_buf = efx_rx_buffer(rx_queue, index);
2552         EFX_POPULATE_QWORD_2(*rxd,
2553                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2554                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2555 }
2556
2557 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2558 {
2559         struct efx_nic *efx = rx_queue->efx;
2560         unsigned int write_count;
2561         efx_dword_t reg;
2562
2563         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2564         write_count = rx_queue->added_count & ~7;
2565         if (rx_queue->notified_count == write_count)
2566                 return;
2567
2568         do
2569                 efx_ef10_build_rx_desc(
2570                         rx_queue,
2571                         rx_queue->notified_count & rx_queue->ptr_mask);
2572         while (++rx_queue->notified_count != write_count);
2573
2574         wmb();
2575         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2576                              write_count & rx_queue->ptr_mask);
2577         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2578                         efx_rx_queue_index(rx_queue));
2579 }
2580
2581 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2582
2583 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2584 {
2585         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2586         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2587         efx_qword_t event;
2588
2589         EFX_POPULATE_QWORD_2(event,
2590                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2591                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2592
2593         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2594
2595         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2596          * already swapped the data to little-endian order.
2597          */
2598         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2599                sizeof(efx_qword_t));
2600
2601         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2602                            inbuf, sizeof(inbuf), 0,
2603                            efx_ef10_rx_defer_refill_complete, 0);
2604 }
2605
2606 static void
2607 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2608                                   int rc, efx_dword_t *outbuf,
2609                                   size_t outlen_actual)
2610 {
2611         /* nothing to do */
2612 }
2613
2614 static int efx_ef10_ev_probe(struct efx_channel *channel)
2615 {
2616         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2617                                     (channel->eventq_mask + 1) *
2618                                     sizeof(efx_qword_t),
2619                                     GFP_KERNEL);
2620 }
2621
2622 static void efx_ef10_ev_fini(struct efx_channel *channel)
2623 {
2624         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2625         MCDI_DECLARE_BUF_ERR(outbuf);
2626         struct efx_nic *efx = channel->efx;
2627         size_t outlen;
2628         int rc;
2629
2630         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2631
2632         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2633                           outbuf, sizeof(outbuf), &outlen);
2634
2635         if (rc && rc != -EALREADY)
2636                 goto fail;
2637
2638         return;
2639
2640 fail:
2641         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2642                                outbuf, outlen, rc);
2643 }
2644
2645 static int efx_ef10_ev_init(struct efx_channel *channel)
2646 {
2647         MCDI_DECLARE_BUF(inbuf,
2648                          MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2649                                                    EFX_BUF_SIZE));
2650         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
2651         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2652         struct efx_nic *efx = channel->efx;
2653         struct efx_ef10_nic_data *nic_data;
2654         size_t inlen, outlen;
2655         unsigned int enabled, implemented;
2656         dma_addr_t dma_addr;
2657         int rc;
2658         int i;
2659
2660         nic_data = efx->nic_data;
2661
2662         /* Fill event queue with all ones (i.e. empty events) */
2663         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2664
2665         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2666         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2667         /* INIT_EVQ expects index in vector table, not absolute */
2668         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2669         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2670                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2671         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2672         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2673         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2674                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2675         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2676
2677         if (nic_data->datapath_caps2 &
2678             1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
2679                 /* Use the new generic approach to specifying event queue
2680                  * configuration, requesting lower latency or higher throughput.
2681                  * The options that actually get used appear in the output.
2682                  */
2683                 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
2684                                       INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
2685                                       INIT_EVQ_V2_IN_FLAG_TYPE,
2686                                       MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
2687         } else {
2688                 bool cut_thru = !(nic_data->datapath_caps &
2689                         1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2690
2691                 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2692                                       INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2693                                       INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2694                                       INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2695                                       INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
2696         }
2697
2698         dma_addr = channel->eventq.buf.dma_addr;
2699         for (i = 0; i < entries; ++i) {
2700                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2701                 dma_addr += EFX_BUF_SIZE;
2702         }
2703
2704         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2705
2706         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2707                           outbuf, sizeof(outbuf), &outlen);
2708
2709         if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
2710                 netif_dbg(efx, drv, efx->net_dev,
2711                           "Channel %d using event queue flags %08x\n",
2712                           channel->channel,
2713                           MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
2714
2715         /* IRQ return is ignored */
2716         if (channel->channel || rc)
2717                 return rc;
2718
2719         /* Successfully created event queue on channel 0 */
2720         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2721         if (rc == -ENOSYS) {
2722                 /* GET_WORKAROUNDS was implemented before this workaround,
2723                  * thus it must be unavailable in this firmware.
2724                  */
2725                 nic_data->workaround_26807 = false;
2726                 rc = 0;
2727         } else if (rc) {
2728                 goto fail;
2729         } else {
2730                 nic_data->workaround_26807 =
2731                         !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2732
2733                 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2734                     !nic_data->workaround_26807) {
2735                         unsigned int flags;
2736
2737                         rc = efx_mcdi_set_workaround(efx,
2738                                                      MC_CMD_WORKAROUND_BUG26807,
2739                                                      true, &flags);
2740
2741                         if (!rc) {
2742                                 if (flags &
2743                                     1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2744                                         netif_info(efx, drv, efx->net_dev,
2745                                                    "other functions on NIC have been reset\n");
2746
2747                                         /* With MCFW v4.6.x and earlier, the
2748                                          * boot count will have incremented,
2749                                          * so re-read the warm_boot_count
2750                                          * value now to ensure this function
2751                                          * doesn't think it has changed next
2752                                          * time it checks.
2753                                          */
2754                                         rc = efx_ef10_get_warm_boot_count(efx);
2755                                         if (rc >= 0) {
2756                                                 nic_data->warm_boot_count = rc;
2757                                                 rc = 0;
2758                                         }
2759                                 }
2760                                 nic_data->workaround_26807 = true;
2761                         } else if (rc == -EPERM) {
2762                                 rc = 0;
2763                         }
2764                 }
2765         }
2766
2767         if (!rc)
2768                 return 0;
2769
2770 fail:
2771         efx_ef10_ev_fini(channel);
2772         return rc;
2773 }
2774
2775 static void efx_ef10_ev_remove(struct efx_channel *channel)
2776 {
2777         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2778 }
2779
2780 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2781                                            unsigned int rx_queue_label)
2782 {
2783         struct efx_nic *efx = rx_queue->efx;
2784
2785         netif_info(efx, hw, efx->net_dev,
2786                    "rx event arrived on queue %d labeled as queue %u\n",
2787                    efx_rx_queue_index(rx_queue), rx_queue_label);
2788
2789         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2790 }
2791
2792 static void
2793 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2794                              unsigned int actual, unsigned int expected)
2795 {
2796         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2797         struct efx_nic *efx = rx_queue->efx;
2798
2799         netif_info(efx, hw, efx->net_dev,
2800                    "dropped %d events (index=%d expected=%d)\n",
2801                    dropped, actual, expected);
2802
2803         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2804 }
2805
2806 /* partially received RX was aborted. clean up. */
2807 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2808 {
2809         unsigned int rx_desc_ptr;
2810
2811         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2812                   "scattered RX aborted (dropping %u buffers)\n",
2813                   rx_queue->scatter_n);
2814
2815         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2816
2817         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2818                       0, EFX_RX_PKT_DISCARD);
2819
2820         rx_queue->removed_count += rx_queue->scatter_n;
2821         rx_queue->scatter_n = 0;
2822         rx_queue->scatter_len = 0;
2823         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2824 }
2825
2826 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2827                                     const efx_qword_t *event)
2828 {
2829         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2830         unsigned int n_descs, n_packets, i;
2831         struct efx_nic *efx = channel->efx;
2832         struct efx_rx_queue *rx_queue;
2833         bool rx_cont;
2834         u16 flags = 0;
2835
2836         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2837                 return 0;
2838
2839         /* Basic packet information */
2840         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2841         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2842         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2843         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2844         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2845
2846         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2847                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2848                             EFX_QWORD_FMT "\n",
2849                             EFX_QWORD_VAL(*event));
2850
2851         rx_queue = efx_channel_get_rx_queue(channel);
2852
2853         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2854                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2855
2856         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2857                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2858
2859         if (n_descs != rx_queue->scatter_n + 1) {
2860                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2861
2862                 /* detect rx abort */
2863                 if (unlikely(n_descs == rx_queue->scatter_n)) {
2864                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2865                                 netdev_WARN(efx->net_dev,
2866                                             "invalid RX abort: scatter_n=%u event="
2867                                             EFX_QWORD_FMT "\n",
2868                                             rx_queue->scatter_n,
2869                                             EFX_QWORD_VAL(*event));
2870                         efx_ef10_handle_rx_abort(rx_queue);
2871                         return 0;
2872                 }
2873
2874                 /* Check that RX completion merging is valid, i.e.
2875                  * the current firmware supports it and this is a
2876                  * non-scattered packet.
2877                  */
2878                 if (!(nic_data->datapath_caps &
2879                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2880                     rx_queue->scatter_n != 0 || rx_cont) {
2881                         efx_ef10_handle_rx_bad_lbits(
2882                                 rx_queue, next_ptr_lbits,
2883                                 (rx_queue->removed_count +
2884                                  rx_queue->scatter_n + 1) &
2885                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2886                         return 0;
2887                 }
2888
2889                 /* Merged completion for multiple non-scattered packets */
2890                 rx_queue->scatter_n = 1;
2891                 rx_queue->scatter_len = 0;
2892                 n_packets = n_descs;
2893                 ++channel->n_rx_merge_events;
2894                 channel->n_rx_merge_packets += n_packets;
2895                 flags |= EFX_RX_PKT_PREFIX_LEN;
2896         } else {
2897                 ++rx_queue->scatter_n;
2898                 rx_queue->scatter_len += rx_bytes;
2899                 if (rx_cont)
2900                         return 0;
2901                 n_packets = 1;
2902         }
2903
2904         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2905                 flags |= EFX_RX_PKT_DISCARD;
2906
2907         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2908                 channel->n_rx_ip_hdr_chksum_err += n_packets;
2909         } else if (unlikely(EFX_QWORD_FIELD(*event,
2910                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2911                 channel->n_rx_tcp_udp_chksum_err += n_packets;
2912         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2913                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2914                 flags |= EFX_RX_PKT_CSUMMED;
2915         }
2916
2917         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2918                 flags |= EFX_RX_PKT_TCP;
2919
2920         channel->irq_mod_score += 2 * n_packets;
2921
2922         /* Handle received packet(s) */
2923         for (i = 0; i < n_packets; i++) {
2924                 efx_rx_packet(rx_queue,
2925                               rx_queue->removed_count & rx_queue->ptr_mask,
2926                               rx_queue->scatter_n, rx_queue->scatter_len,
2927                               flags);
2928                 rx_queue->removed_count += rx_queue->scatter_n;
2929         }
2930
2931         rx_queue->scatter_n = 0;
2932         rx_queue->scatter_len = 0;
2933
2934         return n_packets;
2935 }
2936
2937 static int
2938 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2939 {
2940         struct efx_nic *efx = channel->efx;
2941         struct efx_tx_queue *tx_queue;
2942         unsigned int tx_ev_desc_ptr;
2943         unsigned int tx_ev_q_label;
2944         int tx_descs = 0;
2945
2946         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2947                 return 0;
2948
2949         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2950                 return 0;
2951
2952         /* Transmit completion */
2953         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2954         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2955         tx_queue = efx_channel_get_tx_queue(channel,
2956                                             tx_ev_q_label % EFX_TXQ_TYPES);
2957         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2958                     tx_queue->ptr_mask);
2959         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2960
2961         return tx_descs;
2962 }
2963
2964 static void
2965 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2966 {
2967         struct efx_nic *efx = channel->efx;
2968         int subcode;
2969
2970         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2971
2972         switch (subcode) {
2973         case ESE_DZ_DRV_TIMER_EV:
2974         case ESE_DZ_DRV_WAKE_UP_EV:
2975                 break;
2976         case ESE_DZ_DRV_START_UP_EV:
2977                 /* event queue init complete. ok. */
2978                 break;
2979         default:
2980                 netif_err(efx, hw, efx->net_dev,
2981                           "channel %d unknown driver event type %d"
2982                           " (data " EFX_QWORD_FMT ")\n",
2983                           channel->channel, subcode,
2984                           EFX_QWORD_VAL(*event));
2985
2986         }
2987 }
2988
2989 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2990                                                    efx_qword_t *event)
2991 {
2992         struct efx_nic *efx = channel->efx;
2993         u32 subcode;
2994
2995         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2996
2997         switch (subcode) {
2998         case EFX_EF10_TEST:
2999                 channel->event_test_cpu = raw_smp_processor_id();
3000                 break;
3001         case EFX_EF10_REFILL:
3002                 /* The queue must be empty, so we won't receive any rx
3003                  * events, so efx_process_channel() won't refill the
3004                  * queue. Refill it here
3005                  */
3006                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3007                 break;
3008         default:
3009                 netif_err(efx, hw, efx->net_dev,
3010                           "channel %d unknown driver event type %u"
3011                           " (data " EFX_QWORD_FMT ")\n",
3012                           channel->channel, (unsigned) subcode,
3013                           EFX_QWORD_VAL(*event));
3014         }
3015 }
3016
3017 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3018 {
3019         struct efx_nic *efx = channel->efx;
3020         efx_qword_t event, *p_event;
3021         unsigned int read_ptr;
3022         int ev_code;
3023         int tx_descs = 0;
3024         int spent = 0;
3025
3026         if (quota <= 0)
3027                 return spent;
3028
3029         read_ptr = channel->eventq_read_ptr;
3030
3031         for (;;) {
3032                 p_event = efx_event(channel, read_ptr);
3033                 event = *p_event;
3034
3035                 if (!efx_event_present(&event))
3036                         break;
3037
3038                 EFX_SET_QWORD(*p_event);
3039
3040                 ++read_ptr;
3041
3042                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3043
3044                 netif_vdbg(efx, drv, efx->net_dev,
3045                            "processing event on %d " EFX_QWORD_FMT "\n",
3046                            channel->channel, EFX_QWORD_VAL(event));
3047
3048                 switch (ev_code) {
3049                 case ESE_DZ_EV_CODE_MCDI_EV:
3050                         efx_mcdi_process_event(channel, &event);
3051                         break;
3052                 case ESE_DZ_EV_CODE_RX_EV:
3053                         spent += efx_ef10_handle_rx_event(channel, &event);
3054                         if (spent >= quota) {
3055                                 /* XXX can we split a merged event to
3056                                  * avoid going over-quota?
3057                                  */
3058                                 spent = quota;
3059                                 goto out;
3060                         }
3061                         break;
3062                 case ESE_DZ_EV_CODE_TX_EV:
3063                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
3064                         if (tx_descs > efx->txq_entries) {
3065                                 spent = quota;
3066                                 goto out;
3067                         } else if (++spent == quota) {
3068                                 goto out;
3069                         }
3070                         break;
3071                 case ESE_DZ_EV_CODE_DRIVER_EV:
3072                         efx_ef10_handle_driver_event(channel, &event);
3073                         if (++spent == quota)
3074                                 goto out;
3075                         break;
3076                 case EFX_EF10_DRVGEN_EV:
3077                         efx_ef10_handle_driver_generated_event(channel, &event);
3078                         break;
3079                 default:
3080                         netif_err(efx, hw, efx->net_dev,
3081                                   "channel %d unknown event type %d"
3082                                   " (data " EFX_QWORD_FMT ")\n",
3083                                   channel->channel, ev_code,
3084                                   EFX_QWORD_VAL(event));
3085                 }
3086         }
3087
3088 out:
3089         channel->eventq_read_ptr = read_ptr;
3090         return spent;
3091 }
3092
3093 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3094 {
3095         struct efx_nic *efx = channel->efx;
3096         efx_dword_t rptr;
3097
3098         if (EFX_EF10_WORKAROUND_35388(efx)) {
3099                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3100                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3101                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3102                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3103
3104                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3105                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3106                                      ERF_DD_EVQ_IND_RPTR,
3107                                      (channel->eventq_read_ptr &
3108                                       channel->eventq_mask) >>
3109                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
3110                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3111                                 channel->channel);
3112                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3113                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3114                                      ERF_DD_EVQ_IND_RPTR,
3115                                      channel->eventq_read_ptr &
3116                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3117                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3118                                 channel->channel);
3119         } else {
3120                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3121                                      channel->eventq_read_ptr &
3122                                      channel->eventq_mask);
3123                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3124         }
3125 }
3126
3127 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3128 {
3129         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3130         struct efx_nic *efx = channel->efx;
3131         efx_qword_t event;
3132         int rc;
3133
3134         EFX_POPULATE_QWORD_2(event,
3135                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3136                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
3137
3138         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3139
3140         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3141          * already swapped the data to little-endian order.
3142          */
3143         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3144                sizeof(efx_qword_t));
3145
3146         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3147                           NULL, 0, NULL);
3148         if (rc != 0)
3149                 goto fail;
3150
3151         return;
3152
3153 fail:
3154         WARN_ON(true);
3155         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3156 }
3157
3158 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3159 {
3160         if (atomic_dec_and_test(&efx->active_queues))
3161                 wake_up(&efx->flush_wq);
3162
3163         WARN_ON(atomic_read(&efx->active_queues) < 0);
3164 }
3165
3166 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3167 {
3168         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3169         struct efx_channel *channel;
3170         struct efx_tx_queue *tx_queue;
3171         struct efx_rx_queue *rx_queue;
3172         int pending;
3173
3174         /* If the MC has just rebooted, the TX/RX queues will have already been
3175          * torn down, but efx->active_queues needs to be set to zero.
3176          */
3177         if (nic_data->must_realloc_vis) {
3178                 atomic_set(&efx->active_queues, 0);
3179                 return 0;
3180         }
3181
3182         /* Do not attempt to write to the NIC during EEH recovery */
3183         if (efx->state != STATE_RECOVERY) {
3184                 efx_for_each_channel(channel, efx) {
3185                         efx_for_each_channel_rx_queue(rx_queue, channel)
3186                                 efx_ef10_rx_fini(rx_queue);
3187                         efx_for_each_channel_tx_queue(tx_queue, channel)
3188                                 efx_ef10_tx_fini(tx_queue);
3189                 }
3190
3191                 wait_event_timeout(efx->flush_wq,
3192                                    atomic_read(&efx->active_queues) == 0,
3193                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3194                 pending = atomic_read(&efx->active_queues);
3195                 if (pending) {
3196                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3197                                   pending);
3198                         return -ETIMEDOUT;
3199                 }
3200         }
3201
3202         return 0;
3203 }
3204
3205 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3206 {
3207         atomic_set(&efx->active_queues, 0);
3208 }
3209
3210 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3211                                   const struct efx_filter_spec *right)
3212 {
3213         if ((left->match_flags ^ right->match_flags) |
3214             ((left->flags ^ right->flags) &
3215              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3216                 return false;
3217
3218         return memcmp(&left->outer_vid, &right->outer_vid,
3219                       sizeof(struct efx_filter_spec) -
3220                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
3221 }
3222
3223 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3224 {
3225         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3226         return jhash2((const u32 *)&spec->outer_vid,
3227                       (sizeof(struct efx_filter_spec) -
3228                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
3229                       0);
3230         /* XXX should we randomise the initval? */
3231 }
3232
3233 /* Decide whether a filter should be exclusive or else should allow
3234  * delivery to additional recipients.  Currently we decide that
3235  * filters for specific local unicast MAC and IP addresses are
3236  * exclusive.
3237  */
3238 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3239 {
3240         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3241             !is_multicast_ether_addr(spec->loc_mac))
3242                 return true;
3243
3244         if ((spec->match_flags &
3245              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3246             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3247                 if (spec->ether_type == htons(ETH_P_IP) &&
3248                     !ipv4_is_multicast(spec->loc_host[0]))
3249                         return true;
3250                 if (spec->ether_type == htons(ETH_P_IPV6) &&
3251                     ((const u8 *)spec->loc_host)[0] != 0xff)
3252                         return true;
3253         }
3254
3255         return false;
3256 }
3257
3258 static struct efx_filter_spec *
3259 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3260                            unsigned int filter_idx)
3261 {
3262         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3263                                           ~EFX_EF10_FILTER_FLAGS);
3264 }
3265
3266 static unsigned int
3267 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3268                            unsigned int filter_idx)
3269 {
3270         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3271 }
3272
3273 static void
3274 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3275                           unsigned int filter_idx,
3276                           const struct efx_filter_spec *spec,
3277                           unsigned int flags)
3278 {
3279         table->entry[filter_idx].spec = (unsigned long)spec | flags;
3280 }
3281
3282 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3283                                       const struct efx_filter_spec *spec,
3284                                       efx_dword_t *inbuf, u64 handle,
3285                                       bool replacing)
3286 {
3287         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3288         u32 flags = spec->flags;
3289
3290         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3291
3292         /* Remove RSS flag if we don't have an RSS context. */
3293         if (flags & EFX_FILTER_FLAG_RX_RSS &&
3294             spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3295             nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3296                 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3297
3298         if (replacing) {
3299                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3300                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
3301                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3302         } else {
3303                 u32 match_fields = 0;
3304
3305                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3306                                efx_ef10_filter_is_exclusive(spec) ?
3307                                MC_CMD_FILTER_OP_IN_OP_INSERT :
3308                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3309
3310                 /* Convert match flags and values.  Unlike almost
3311                  * everything else in MCDI, these fields are in
3312                  * network byte order.
3313                  */
3314                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3315                         match_fields |=
3316                                 is_multicast_ether_addr(spec->loc_mac) ?
3317                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3318                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3319 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
3320                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
3321                         match_fields |=                                      \
3322                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
3323                                 mcdi_field ## _LBN;                          \
3324                         BUILD_BUG_ON(                                        \
3325                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3326                                 sizeof(spec->gen_field));                    \
3327                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3328                                &spec->gen_field, sizeof(spec->gen_field));   \
3329                 }
3330                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3331                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3332                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3333                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3334                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3335                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3336                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3337                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3338                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3339                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3340 #undef COPY_FIELD
3341                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3342                                match_fields);
3343         }
3344
3345         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3346         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3347                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3348                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3349                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3350         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3351         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3352                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3353         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3354                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3355                        0 : spec->dmaq_id);
3356         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3357                        (flags & EFX_FILTER_FLAG_RX_RSS) ?
3358                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3359                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3360         if (flags & EFX_FILTER_FLAG_RX_RSS)
3361                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3362                                spec->rss_context !=
3363                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3364                                spec->rss_context : nic_data->rx_rss_context);
3365 }
3366
3367 static int efx_ef10_filter_push(struct efx_nic *efx,
3368                                 const struct efx_filter_spec *spec,
3369                                 u64 *handle, bool replacing)
3370 {
3371         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3372         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3373         int rc;
3374
3375         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3376         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3377                           outbuf, sizeof(outbuf), NULL);
3378         if (rc == 0)
3379                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3380         if (rc == -ENOSPC)
3381                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3382         return rc;
3383 }
3384
3385 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
3386 {
3387         unsigned int match_flags = spec->match_flags;
3388         u32 mcdi_flags = 0;
3389
3390         if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3391                 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3392                 mcdi_flags |=
3393                         is_multicast_ether_addr(spec->loc_mac) ?
3394                         (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
3395                         (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
3396         }
3397
3398 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) {                 \
3399                 unsigned int old_match_flags = match_flags;             \
3400                 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag;          \
3401                 if (match_flags != old_match_flags)                     \
3402                         mcdi_flags |=                                   \
3403                                 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ##     \
3404                                  mcdi_field ## _LBN);                   \
3405         }
3406         MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
3407         MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
3408         MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
3409         MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
3410         MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
3411         MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
3412         MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
3413         MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
3414         MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
3415         MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
3416 #undef MAP_FILTER_TO_MCDI_FLAG
3417
3418         /* Did we map them all? */
3419         WARN_ON_ONCE(match_flags);
3420
3421         return mcdi_flags;
3422 }
3423
3424 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3425                                const struct efx_filter_spec *spec)
3426 {
3427         u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
3428         unsigned int match_pri;
3429
3430         for (match_pri = 0;
3431              match_pri < table->rx_match_count;
3432              match_pri++)
3433                 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
3434                         return match_pri;
3435
3436         return -EPROTONOSUPPORT;
3437 }
3438
3439 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3440                                   struct efx_filter_spec *spec,
3441                                   bool replace_equal)
3442 {
3443         struct efx_ef10_filter_table *table = efx->filter_state;
3444         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3445         struct efx_filter_spec *saved_spec;
3446         unsigned int match_pri, hash;
3447         unsigned int priv_flags;
3448         bool replacing = false;
3449         int ins_index = -1;
3450         DEFINE_WAIT(wait);
3451         bool is_mc_recip;
3452         s32 rc;
3453
3454         /* For now, only support RX filters */
3455         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3456             EFX_FILTER_FLAG_RX)
3457                 return -EINVAL;
3458
3459         rc = efx_ef10_filter_pri(table, spec);
3460         if (rc < 0)
3461                 return rc;
3462         match_pri = rc;
3463
3464         hash = efx_ef10_filter_hash(spec);
3465         is_mc_recip = efx_filter_is_mc_recipient(spec);
3466         if (is_mc_recip)
3467                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3468
3469         /* Find any existing filters with the same match tuple or
3470          * else a free slot to insert at.  If any of them are busy,
3471          * we have to wait and retry.
3472          */
3473         for (;;) {
3474                 unsigned int depth = 1;
3475                 unsigned int i;
3476
3477                 spin_lock_bh(&efx->filter_lock);
3478
3479                 for (;;) {
3480                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3481                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3482
3483                         if (!saved_spec) {
3484                                 if (ins_index < 0)
3485                                         ins_index = i;
3486                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3487                                 if (table->entry[i].spec &
3488                                     EFX_EF10_FILTER_FLAG_BUSY)
3489                                         break;
3490                                 if (spec->priority < saved_spec->priority &&
3491                                     spec->priority != EFX_FILTER_PRI_AUTO) {
3492                                         rc = -EPERM;
3493                                         goto out_unlock;
3494                                 }
3495                                 if (!is_mc_recip) {
3496                                         /* This is the only one */
3497                                         if (spec->priority ==
3498                                             saved_spec->priority &&
3499                                             !replace_equal) {
3500                                                 rc = -EEXIST;
3501                                                 goto out_unlock;
3502                                         }
3503                                         ins_index = i;
3504                                         goto found;
3505                                 } else if (spec->priority >
3506                                            saved_spec->priority ||
3507                                            (spec->priority ==
3508                                             saved_spec->priority &&
3509                                             replace_equal)) {
3510                                         if (ins_index < 0)
3511                                                 ins_index = i;
3512                                         else
3513                                                 __set_bit(depth, mc_rem_map);
3514                                 }
3515                         }
3516
3517                         /* Once we reach the maximum search depth, use
3518                          * the first suitable slot or return -EBUSY if
3519                          * there was none
3520                          */
3521                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3522                                 if (ins_index < 0) {
3523                                         rc = -EBUSY;
3524                                         goto out_unlock;
3525                                 }
3526                                 goto found;
3527                         }
3528
3529                         ++depth;
3530                 }
3531
3532                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3533                 spin_unlock_bh(&efx->filter_lock);
3534                 schedule();
3535         }
3536
3537 found:
3538         /* Create a software table entry if necessary, and mark it
3539          * busy.  We might yet fail to insert, but any attempt to
3540          * insert a conflicting filter while we're waiting for the
3541          * firmware must find the busy entry.
3542          */
3543         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3544         if (saved_spec) {
3545                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3546                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3547                         /* Just make sure it won't be removed */
3548                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3549                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3550                         table->entry[ins_index].spec &=
3551                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3552                         rc = ins_index;
3553                         goto out_unlock;
3554                 }
3555                 replacing = true;
3556                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3557         } else {
3558                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3559                 if (!saved_spec) {
3560                         rc = -ENOMEM;
3561                         goto out_unlock;
3562                 }
3563                 *saved_spec = *spec;
3564                 priv_flags = 0;
3565         }
3566         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3567                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3568
3569         /* Mark lower-priority multicast recipients busy prior to removal */
3570         if (is_mc_recip) {
3571                 unsigned int depth, i;
3572
3573                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3574                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3575                         if (test_bit(depth, mc_rem_map))
3576                                 table->entry[i].spec |=
3577                                         EFX_EF10_FILTER_FLAG_BUSY;
3578                 }
3579         }
3580
3581         spin_unlock_bh(&efx->filter_lock);
3582
3583         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3584                                   replacing);
3585
3586         /* Finalise the software table entry */
3587         spin_lock_bh(&efx->filter_lock);
3588         if (rc == 0) {
3589                 if (replacing) {
3590                         /* Update the fields that may differ */
3591                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3592                                 saved_spec->flags |=
3593                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
3594                         saved_spec->priority = spec->priority;
3595                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3596                         saved_spec->flags |= spec->flags;
3597                         saved_spec->rss_context = spec->rss_context;
3598                         saved_spec->dmaq_id = spec->dmaq_id;
3599                 }
3600         } else if (!replacing) {
3601                 kfree(saved_spec);
3602                 saved_spec = NULL;
3603         }
3604         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3605
3606         /* Remove and finalise entries for lower-priority multicast
3607          * recipients
3608          */
3609         if (is_mc_recip) {
3610                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3611                 unsigned int depth, i;
3612
3613                 memset(inbuf, 0, sizeof(inbuf));
3614
3615                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3616                         if (!test_bit(depth, mc_rem_map))
3617                                 continue;
3618
3619                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3620                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3621                         priv_flags = efx_ef10_filter_entry_flags(table, i);
3622
3623                         if (rc == 0) {
3624                                 spin_unlock_bh(&efx->filter_lock);
3625                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3626                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3627                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3628                                                table->entry[i].handle);
3629                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3630                                                   inbuf, sizeof(inbuf),
3631                                                   NULL, 0, NULL);
3632                                 spin_lock_bh(&efx->filter_lock);
3633                         }
3634
3635                         if (rc == 0) {
3636                                 kfree(saved_spec);
3637                                 saved_spec = NULL;
3638                                 priv_flags = 0;
3639                         } else {
3640                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3641                         }
3642                         efx_ef10_filter_set_entry(table, i, saved_spec,
3643                                                   priv_flags);
3644                 }
3645         }
3646
3647         /* If successful, return the inserted filter ID */
3648         if (rc == 0)
3649                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3650
3651         wake_up_all(&table->waitq);
3652 out_unlock:
3653         spin_unlock_bh(&efx->filter_lock);
3654         finish_wait(&table->waitq, &wait);
3655         return rc;
3656 }
3657
3658 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3659 {
3660         /* no need to do anything here on EF10 */
3661 }
3662
3663 /* Remove a filter.
3664  * If !by_index, remove by ID
3665  * If by_index, remove by index
3666  * Filter ID may come from userland and must be range-checked.
3667  */
3668 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3669                                            unsigned int priority_mask,
3670                                            u32 filter_id, bool by_index)
3671 {
3672         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3673         struct efx_ef10_filter_table *table = efx->filter_state;
3674         MCDI_DECLARE_BUF(inbuf,
3675                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3676                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3677         struct efx_filter_spec *spec;
3678         DEFINE_WAIT(wait);
3679         int rc;
3680
3681         /* Find the software table entry and mark it busy.  Don't
3682          * remove it yet; any attempt to update while we're waiting
3683          * for the firmware must find the busy entry.
3684          */
3685         for (;;) {
3686                 spin_lock_bh(&efx->filter_lock);
3687                 if (!(table->entry[filter_idx].spec &
3688                       EFX_EF10_FILTER_FLAG_BUSY))
3689                         break;
3690                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3691                 spin_unlock_bh(&efx->filter_lock);
3692                 schedule();
3693         }
3694
3695         spec = efx_ef10_filter_entry_spec(table, filter_idx);
3696         if (!spec ||
3697             (!by_index &&
3698              efx_ef10_filter_pri(table, spec) !=
3699              filter_id / HUNT_FILTER_TBL_ROWS)) {
3700                 rc = -ENOENT;
3701                 goto out_unlock;
3702         }
3703
3704         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3705             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3706                 /* Just remove flags */
3707                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3708                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3709                 rc = 0;
3710                 goto out_unlock;
3711         }
3712
3713         if (!(priority_mask & (1U << spec->priority))) {
3714                 rc = -ENOENT;
3715                 goto out_unlock;
3716         }
3717
3718         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3719         spin_unlock_bh(&efx->filter_lock);
3720
3721         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3722                 /* Reset to an automatic filter */
3723
3724                 struct efx_filter_spec new_spec = *spec;
3725
3726                 new_spec.priority = EFX_FILTER_PRI_AUTO;
3727                 new_spec.flags = (EFX_FILTER_FLAG_RX |
3728                                   (efx_rss_enabled(efx) ?
3729                                    EFX_FILTER_FLAG_RX_RSS : 0));
3730                 new_spec.dmaq_id = 0;
3731                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3732                 rc = efx_ef10_filter_push(efx, &new_spec,
3733                                           &table->entry[filter_idx].handle,
3734                                           true);
3735
3736                 spin_lock_bh(&efx->filter_lock);
3737                 if (rc == 0)
3738                         *spec = new_spec;
3739         } else {
3740                 /* Really remove the filter */
3741
3742                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3743                                efx_ef10_filter_is_exclusive(spec) ?
3744                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3745                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3746                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3747                                table->entry[filter_idx].handle);
3748                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3749                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
3750
3751                 spin_lock_bh(&efx->filter_lock);
3752                 if (rc == 0) {
3753                         kfree(spec);
3754                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3755                 }
3756         }
3757
3758         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3759         wake_up_all(&table->waitq);
3760 out_unlock:
3761         spin_unlock_bh(&efx->filter_lock);
3762         finish_wait(&table->waitq, &wait);
3763         return rc;
3764 }
3765
3766 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3767                                        enum efx_filter_priority priority,
3768                                        u32 filter_id)
3769 {
3770         return efx_ef10_filter_remove_internal(efx, 1U << priority,
3771                                                filter_id, false);
3772 }
3773
3774 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3775 {
3776         return filter_id % HUNT_FILTER_TBL_ROWS;
3777 }
3778
3779 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3780                                           enum efx_filter_priority priority,
3781                                           u32 filter_id)
3782 {
3783         if (filter_id == EFX_EF10_FILTER_ID_INVALID)
3784                 return;
3785         efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
3786 }
3787
3788 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3789                                     enum efx_filter_priority priority,
3790                                     u32 filter_id, struct efx_filter_spec *spec)
3791 {
3792         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3793         struct efx_ef10_filter_table *table = efx->filter_state;
3794         const struct efx_filter_spec *saved_spec;
3795         int rc;
3796
3797         spin_lock_bh(&efx->filter_lock);
3798         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3799         if (saved_spec && saved_spec->priority == priority &&
3800             efx_ef10_filter_pri(table, saved_spec) ==
3801             filter_id / HUNT_FILTER_TBL_ROWS) {
3802                 *spec = *saved_spec;
3803                 rc = 0;
3804         } else {
3805                 rc = -ENOENT;
3806         }
3807         spin_unlock_bh(&efx->filter_lock);
3808         return rc;
3809 }
3810
3811 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3812                                      enum efx_filter_priority priority)
3813 {
3814         unsigned int priority_mask;
3815         unsigned int i;
3816         int rc;
3817
3818         priority_mask = (((1U << (priority + 1)) - 1) &
3819                          ~(1U << EFX_FILTER_PRI_AUTO));
3820
3821         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3822                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3823                                                      i, true);
3824                 if (rc && rc != -ENOENT)
3825                         return rc;
3826         }
3827
3828         return 0;
3829 }
3830
3831 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3832                                          enum efx_filter_priority priority)
3833 {
3834         struct efx_ef10_filter_table *table = efx->filter_state;
3835         unsigned int filter_idx;
3836         s32 count = 0;
3837
3838         spin_lock_bh(&efx->filter_lock);
3839         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3840                 if (table->entry[filter_idx].spec &&
3841                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3842                     priority)
3843                         ++count;
3844         }
3845         spin_unlock_bh(&efx->filter_lock);
3846         return count;
3847 }
3848
3849 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3850 {
3851         struct efx_ef10_filter_table *table = efx->filter_state;
3852
3853         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3854 }
3855
3856 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3857                                       enum efx_filter_priority priority,
3858                                       u32 *buf, u32 size)
3859 {
3860         struct efx_ef10_filter_table *table = efx->filter_state;
3861         struct efx_filter_spec *spec;
3862         unsigned int filter_idx;
3863         s32 count = 0;
3864
3865         spin_lock_bh(&efx->filter_lock);
3866         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3867                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3868                 if (spec && spec->priority == priority) {
3869                         if (count == size) {
3870                                 count = -EMSGSIZE;
3871                                 break;
3872                         }
3873                         buf[count++] = (efx_ef10_filter_pri(table, spec) *
3874                                         HUNT_FILTER_TBL_ROWS +
3875                                         filter_idx);
3876                 }
3877         }
3878         spin_unlock_bh(&efx->filter_lock);
3879         return count;
3880 }
3881
3882 #ifdef CONFIG_RFS_ACCEL
3883
3884 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3885
3886 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3887                                       struct efx_filter_spec *spec)
3888 {
3889         struct efx_ef10_filter_table *table = efx->filter_state;
3890         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3891         struct efx_filter_spec *saved_spec;
3892         unsigned int hash, i, depth = 1;
3893         bool replacing = false;
3894         int ins_index = -1;
3895         u64 cookie;
3896         s32 rc;
3897
3898         /* Must be an RX filter without RSS and not for a multicast
3899          * destination address (RFS only works for connected sockets).
3900          * These restrictions allow us to pass only a tiny amount of
3901          * data through to the completion function.
3902          */
3903         EFX_WARN_ON_PARANOID(spec->flags !=
3904                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3905         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3906         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3907
3908         hash = efx_ef10_filter_hash(spec);
3909
3910         spin_lock_bh(&efx->filter_lock);
3911
3912         /* Find any existing filter with the same match tuple or else
3913          * a free slot to insert at.  If an existing filter is busy,
3914          * we have to give up.
3915          */
3916         for (;;) {
3917                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3918                 saved_spec = efx_ef10_filter_entry_spec(table, i);
3919
3920                 if (!saved_spec) {
3921                         if (ins_index < 0)
3922                                 ins_index = i;
3923                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3924                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3925                                 rc = -EBUSY;
3926                                 goto fail_unlock;
3927                         }
3928                         if (spec->priority < saved_spec->priority) {
3929                                 rc = -EPERM;
3930                                 goto fail_unlock;
3931                         }
3932                         ins_index = i;
3933                         break;
3934                 }
3935
3936                 /* Once we reach the maximum search depth, use the
3937                  * first suitable slot or return -EBUSY if there was
3938                  * none
3939                  */
3940                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3941                         if (ins_index < 0) {
3942                                 rc = -EBUSY;
3943                                 goto fail_unlock;
3944                         }
3945                         break;
3946                 }
3947
3948                 ++depth;
3949         }
3950
3951         /* Create a software table entry if necessary, and mark it
3952          * busy.  We might yet fail to insert, but any attempt to
3953          * insert a conflicting filter while we're waiting for the
3954          * firmware must find the busy entry.
3955          */
3956         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3957         if (saved_spec) {
3958                 replacing = true;
3959         } else {
3960                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3961                 if (!saved_spec) {
3962                         rc = -ENOMEM;
3963                         goto fail_unlock;
3964                 }
3965                 *saved_spec = *spec;
3966         }
3967         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3968                                   EFX_EF10_FILTER_FLAG_BUSY);
3969
3970         spin_unlock_bh(&efx->filter_lock);
3971
3972         /* Pack up the variables needed on completion */
3973         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3974
3975         efx_ef10_filter_push_prep(efx, spec, inbuf,
3976                                   table->entry[ins_index].handle, replacing);
3977         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3978                            MC_CMD_FILTER_OP_OUT_LEN,
3979                            efx_ef10_filter_rfs_insert_complete, cookie);
3980
3981         return ins_index;
3982
3983 fail_unlock:
3984         spin_unlock_bh(&efx->filter_lock);
3985         return rc;
3986 }
3987
3988 static void
3989 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3990                                     int rc, efx_dword_t *outbuf,
3991                                     size_t outlen_actual)
3992 {
3993         struct efx_ef10_filter_table *table = efx->filter_state;
3994         unsigned int ins_index, dmaq_id;
3995         struct efx_filter_spec *spec;
3996         bool replacing;
3997
3998         /* Unpack the cookie */
3999         replacing = cookie >> 31;
4000         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4001         dmaq_id = cookie & 0xffff;
4002
4003         spin_lock_bh(&efx->filter_lock);
4004         spec = efx_ef10_filter_entry_spec(table, ins_index);
4005         if (rc == 0) {
4006                 table->entry[ins_index].handle =
4007                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4008                 if (replacing)
4009                         spec->dmaq_id = dmaq_id;
4010         } else if (!replacing) {
4011                 kfree(spec);
4012                 spec = NULL;
4013         }
4014         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4015         spin_unlock_bh(&efx->filter_lock);
4016
4017         wake_up_all(&table->waitq);
4018 }
4019
4020 static void
4021 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4022                                     unsigned long filter_idx,
4023                                     int rc, efx_dword_t *outbuf,
4024                                     size_t outlen_actual);
4025
4026 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4027                                            unsigned int filter_idx)
4028 {
4029         struct efx_ef10_filter_table *table = efx->filter_state;
4030         struct efx_filter_spec *spec =
4031                 efx_ef10_filter_entry_spec(table, filter_idx);
4032         MCDI_DECLARE_BUF(inbuf,
4033                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4034                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4035
4036         if (!spec ||
4037             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4038             spec->priority != EFX_FILTER_PRI_HINT ||
4039             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4040                                  flow_id, filter_idx))
4041                 return false;
4042
4043         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4044                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
4045         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4046                        table->entry[filter_idx].handle);
4047         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4048                                efx_ef10_filter_rfs_expire_complete, filter_idx))
4049                 return false;
4050
4051         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4052         return true;
4053 }
4054
4055 static void
4056 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4057                                     unsigned long filter_idx,
4058                                     int rc, efx_dword_t *outbuf,
4059                                     size_t outlen_actual)
4060 {
4061         struct efx_ef10_filter_table *table = efx->filter_state;
4062         struct efx_filter_spec *spec =
4063                 efx_ef10_filter_entry_spec(table, filter_idx);
4064
4065         spin_lock_bh(&efx->filter_lock);
4066         if (rc == 0) {
4067                 kfree(spec);
4068                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4069         }
4070         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4071         wake_up_all(&table->waitq);
4072         spin_unlock_bh(&efx->filter_lock);
4073 }
4074
4075 #endif /* CONFIG_RFS_ACCEL */
4076
4077 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
4078 {
4079         int match_flags = 0;
4080
4081 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
4082                 u32 old_mcdi_flags = mcdi_flags;                        \
4083                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
4084                                 mcdi_field ## _LBN);                    \
4085                 if (mcdi_flags != old_mcdi_flags)                       \
4086                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
4087         }
4088         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4089         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4090         MAP_FLAG(REM_HOST, SRC_IP);
4091         MAP_FLAG(LOC_HOST, DST_IP);
4092         MAP_FLAG(REM_MAC, SRC_MAC);
4093         MAP_FLAG(REM_PORT, SRC_PORT);
4094         MAP_FLAG(LOC_MAC, DST_MAC);
4095         MAP_FLAG(LOC_PORT, DST_PORT);
4096         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4097         MAP_FLAG(INNER_VID, INNER_VLAN);
4098         MAP_FLAG(OUTER_VID, OUTER_VLAN);
4099         MAP_FLAG(IP_PROTO, IP_PROTO);
4100 #undef MAP_FLAG
4101
4102         /* Did we map them all? */
4103         if (mcdi_flags)
4104                 return -EINVAL;
4105
4106         return match_flags;
4107 }
4108
4109 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4110 {
4111         struct efx_ef10_filter_table *table = efx->filter_state;
4112         struct efx_ef10_filter_vlan *vlan, *next_vlan;
4113
4114         /* See comment in efx_ef10_filter_table_remove() */
4115         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4116                 return;
4117
4118         if (!table)
4119                 return;
4120
4121         list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4122                 efx_ef10_filter_del_vlan_internal(efx, vlan);
4123 }
4124
4125 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4126                                             enum efx_filter_match_flags match_flags)
4127 {
4128         unsigned int match_pri;
4129         int mf;
4130
4131         for (match_pri = 0;
4132              match_pri < table->rx_match_count;
4133              match_pri++) {
4134                 mf = efx_ef10_filter_match_flags_from_mcdi(
4135                                 table->rx_match_mcdi_flags[match_pri]);
4136                 if (mf == match_flags)
4137                         return true;
4138         }
4139
4140         return false;
4141 }
4142
4143 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4144 {
4145         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4146         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4147         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4148         struct net_device *net_dev = efx->net_dev;
4149         unsigned int pd_match_pri, pd_match_count;
4150         struct efx_ef10_filter_table *table;
4151         struct efx_ef10_vlan *vlan;
4152         size_t outlen;
4153         int rc;
4154
4155         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4156                 return -EINVAL;
4157
4158         if (efx->filter_state) /* already probed */
4159                 return 0;
4160
4161         table = kzalloc(sizeof(*table), GFP_KERNEL);
4162         if (!table)
4163                 return -ENOMEM;
4164
4165         /* Find out which RX filter types are supported, and their priorities */
4166         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4167                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4168         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4169                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4170                           &outlen);
4171         if (rc)
4172                 goto fail;
4173         pd_match_count = MCDI_VAR_ARRAY_LEN(
4174                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4175         table->rx_match_count = 0;
4176
4177         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4178                 u32 mcdi_flags =
4179                         MCDI_ARRAY_DWORD(
4180                                 outbuf,
4181                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4182                                 pd_match_pri);
4183                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
4184                 if (rc < 0) {
4185                         netif_dbg(efx, probe, efx->net_dev,
4186                                   "%s: fw flags %#x pri %u not supported in driver\n",
4187                                   __func__, mcdi_flags, pd_match_pri);
4188                 } else {
4189                         netif_dbg(efx, probe, efx->net_dev,
4190                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4191                                   __func__, mcdi_flags, pd_match_pri,
4192                                   rc, table->rx_match_count);
4193                         table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4194                         table->rx_match_count++;
4195                 }
4196         }
4197
4198         if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4199             !(efx_ef10_filter_match_supported(table,
4200                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4201               efx_ef10_filter_match_supported(table,
4202                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4203                 netif_info(efx, probe, net_dev,
4204                            "VLAN filters are not supported in this firmware variant\n");
4205                 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4206                 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4207                 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4208         }
4209
4210         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4211         if (!table->entry) {
4212                 rc = -ENOMEM;
4213                 goto fail;
4214         }
4215
4216         table->mc_promisc_last = false;
4217         table->vlan_filter =
4218                 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4219         INIT_LIST_HEAD(&table->vlan_list);
4220
4221         efx->filter_state = table;
4222         init_waitqueue_head(&table->waitq);
4223
4224         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4225                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4226                 if (rc)
4227                         goto fail_add_vlan;
4228         }
4229
4230         return 0;
4231
4232 fail_add_vlan:
4233         efx_ef10_filter_cleanup_vlans(efx);
4234         efx->filter_state = NULL;
4235 fail:
4236         kfree(table);
4237         return rc;
4238 }
4239
4240 /* Caller must hold efx->filter_sem for read if race against
4241  * efx_ef10_filter_table_remove() is possible
4242  */
4243 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4244 {
4245         struct efx_ef10_filter_table *table = efx->filter_state;
4246         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4247         struct efx_filter_spec *spec;
4248         unsigned int filter_idx;
4249         bool failed = false;
4250         int rc;
4251
4252         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4253
4254         if (!nic_data->must_restore_filters)
4255                 return;
4256
4257         if (!table)
4258                 return;
4259
4260         spin_lock_bh(&efx->filter_lock);
4261
4262         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4263                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4264                 if (!spec)
4265                         continue;
4266
4267                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4268                 spin_unlock_bh(&efx->filter_lock);
4269
4270                 rc = efx_ef10_filter_push(efx, spec,
4271                                           &table->entry[filter_idx].handle,
4272                                           false);
4273                 if (rc)
4274                         failed = true;
4275
4276                 spin_lock_bh(&efx->filter_lock);
4277                 if (rc) {
4278                         kfree(spec);
4279                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4280                 } else {
4281                         table->entry[filter_idx].spec &=
4282                                 ~EFX_EF10_FILTER_FLAG_BUSY;
4283                 }
4284         }
4285
4286         spin_unlock_bh(&efx->filter_lock);
4287
4288         if (failed)
4289                 netif_err(efx, hw, efx->net_dev,
4290                           "unable to restore all filters\n");
4291         else
4292                 nic_data->must_restore_filters = false;
4293 }
4294
4295 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4296 {
4297         struct efx_ef10_filter_table *table = efx->filter_state;
4298         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4299         struct efx_filter_spec *spec;
4300         unsigned int filter_idx;
4301         int rc;
4302
4303         efx_ef10_filter_cleanup_vlans(efx);
4304         efx->filter_state = NULL;
4305         /* If we were called without locking, then it's not safe to free
4306          * the table as others might be using it.  So we just WARN, leak
4307          * the memory, and potentially get an inconsistent filter table
4308          * state.
4309          * This should never actually happen.
4310          */
4311         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4312                 return;
4313
4314         if (!table)
4315                 return;
4316
4317         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4318                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4319                 if (!spec)
4320                         continue;
4321
4322                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4323                                efx_ef10_filter_is_exclusive(spec) ?
4324                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
4325                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4326                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4327                                table->entry[filter_idx].handle);
4328                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4329                                         sizeof(inbuf), NULL, 0, NULL);
4330                 if (rc)
4331                         netif_info(efx, drv, efx->net_dev,
4332                                    "%s: filter %04x remove failed\n",
4333                                    __func__, filter_idx);
4334                 kfree(spec);
4335         }
4336
4337         vfree(table->entry);
4338         kfree(table);
4339 }
4340
4341 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4342 {
4343         struct efx_ef10_filter_table *table = efx->filter_state;
4344         unsigned int filter_idx;
4345
4346         if (*id != EFX_EF10_FILTER_ID_INVALID) {
4347                 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4348                 if (!table->entry[filter_idx].spec)
4349                         netif_dbg(efx, drv, efx->net_dev,
4350                                   "marked null spec old %04x:%04x\n", *id,
4351                                   filter_idx);
4352                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4353                 *id = EFX_EF10_FILTER_ID_INVALID;
4354         }
4355 }
4356
4357 /* Mark old per-VLAN filters that may need to be removed */
4358 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4359                                            struct efx_ef10_filter_vlan *vlan)
4360 {
4361         struct efx_ef10_filter_table *table = efx->filter_state;
4362         unsigned int i;
4363
4364         for (i = 0; i < table->dev_uc_count; i++)
4365                 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
4366         for (i = 0; i < table->dev_mc_count; i++)
4367                 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4368         efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4369         efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4370         efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
4371 }
4372
4373 /* Mark old filters that may need to be removed.
4374  * Caller must hold efx->filter_sem for read if race against
4375  * efx_ef10_filter_table_remove() is possible
4376  */
4377 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4378 {
4379         struct efx_ef10_filter_table *table = efx->filter_state;
4380         struct efx_ef10_filter_vlan *vlan;
4381
4382         spin_lock_bh(&efx->filter_lock);
4383         list_for_each_entry(vlan, &table->vlan_list, list)
4384                 _efx_ef10_filter_vlan_mark_old(efx, vlan);
4385         spin_unlock_bh(&efx->filter_lock);
4386 }
4387
4388 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
4389 {
4390         struct efx_ef10_filter_table *table = efx->filter_state;
4391         struct net_device *net_dev = efx->net_dev;
4392         struct netdev_hw_addr *uc;
4393         int addr_count;
4394         unsigned int i;
4395
4396         addr_count = netdev_uc_count(net_dev);
4397         table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
4398         table->dev_uc_count = 1 + addr_count;
4399         ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4400         i = 1;
4401         netdev_for_each_uc_addr(uc, net_dev) {
4402                 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
4403                         table->uc_promisc = true;
4404                         break;
4405                 }
4406                 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4407                 i++;
4408         }
4409 }
4410
4411 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
4412 {
4413         struct efx_ef10_filter_table *table = efx->filter_state;
4414         struct net_device *net_dev = efx->net_dev;
4415         struct netdev_hw_addr *mc;
4416         unsigned int i, addr_count;
4417
4418         table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
4419
4420         addr_count = netdev_mc_count(net_dev);
4421         i = 0;
4422         netdev_for_each_mc_addr(mc, net_dev) {
4423                 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
4424                         table->mc_promisc = true;
4425                         break;
4426                 }
4427                 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4428                 i++;
4429         }
4430
4431         table->dev_mc_count = i;
4432 }
4433
4434 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
4435                                             struct efx_ef10_filter_vlan *vlan,
4436                                             bool multicast, bool rollback)
4437 {
4438         struct efx_ef10_filter_table *table = efx->filter_state;
4439         struct efx_ef10_dev_addr *addr_list;
4440         enum efx_filter_flags filter_flags;
4441         struct efx_filter_spec spec;
4442         u8 baddr[ETH_ALEN];
4443         unsigned int i, j;
4444         int addr_count;
4445         u16 *ids;
4446         int rc;
4447
4448         if (multicast) {
4449                 addr_list = table->dev_mc_list;
4450                 addr_count = table->dev_mc_count;
4451                 ids = vlan->mc;
4452         } else {
4453                 addr_list = table->dev_uc_list;
4454                 addr_count = table->dev_uc_count;
4455                 ids = vlan->uc;
4456         }
4457
4458         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4459
4460         /* Insert/renew filters */
4461         for (i = 0; i < addr_count; i++) {
4462                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4463                 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
4464                 rc = efx_ef10_filter_insert(efx, &spec, true);
4465                 if (rc < 0) {
4466                         if (rollback) {
4467                                 netif_info(efx, drv, efx->net_dev,
4468                                            "efx_ef10_filter_insert failed rc=%d\n",
4469                                            rc);
4470                                 /* Fall back to promiscuous */
4471                                 for (j = 0; j < i; j++) {
4472                                         efx_ef10_filter_remove_unsafe(
4473                                                 efx, EFX_FILTER_PRI_AUTO,
4474                                                 ids[j]);
4475                                         ids[j] = EFX_EF10_FILTER_ID_INVALID;
4476                                 }
4477                                 return rc;
4478                         } else {
4479                                 /* mark as not inserted, and carry on */
4480                                 rc = EFX_EF10_FILTER_ID_INVALID;
4481                         }
4482                 }
4483                 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
4484         }
4485
4486         if (multicast && rollback) {
4487                 /* Also need an Ethernet broadcast filter */
4488                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4489                 eth_broadcast_addr(baddr);
4490                 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4491                 rc = efx_ef10_filter_insert(efx, &spec, true);
4492                 if (rc < 0) {
4493                         netif_warn(efx, drv, efx->net_dev,
4494                                    "Broadcast filter insert failed rc=%d\n", rc);
4495                         /* Fall back to promiscuous */
4496                         for (j = 0; j < i; j++) {
4497                                 efx_ef10_filter_remove_unsafe(
4498                                         efx, EFX_FILTER_PRI_AUTO,
4499                                         ids[j]);
4500                                 ids[j] = EFX_EF10_FILTER_ID_INVALID;
4501                         }
4502                         return rc;
4503                 } else {
4504                         EFX_WARN_ON_PARANOID(vlan->bcast !=
4505                                              EFX_EF10_FILTER_ID_INVALID);
4506                         vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4507                 }
4508         }
4509
4510         return 0;
4511 }
4512
4513 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4514                                       struct efx_ef10_filter_vlan *vlan,
4515                                       bool multicast, bool rollback)
4516 {
4517         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4518         enum efx_filter_flags filter_flags;
4519         struct efx_filter_spec spec;
4520         u8 baddr[ETH_ALEN];
4521         int rc;
4522
4523         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4524
4525         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4526
4527         if (multicast)
4528                 efx_filter_set_mc_def(&spec);
4529         else
4530                 efx_filter_set_uc_def(&spec);
4531
4532         if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4533                 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4534
4535         rc = efx_ef10_filter_insert(efx, &spec, true);
4536         if (rc < 0) {
4537                 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4538                              efx->net_dev,
4539                              "%scast mismatch filter insert failed rc=%d\n",
4540                              multicast ? "Multi" : "Uni", rc);
4541         } else if (multicast) {
4542                 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4543                 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
4544                 if (!nic_data->workaround_26807) {
4545                         /* Also need an Ethernet broadcast filter */
4546                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4547                                            filter_flags, 0);
4548                         eth_broadcast_addr(baddr);
4549                         efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4550                         rc = efx_ef10_filter_insert(efx, &spec, true);
4551                         if (rc < 0) {
4552                                 netif_warn(efx, drv, efx->net_dev,
4553                                            "Broadcast filter insert failed rc=%d\n",
4554                                            rc);
4555                                 if (rollback) {
4556                                         /* Roll back the mc_def filter */
4557                                         efx_ef10_filter_remove_unsafe(
4558                                                         efx, EFX_FILTER_PRI_AUTO,
4559                                                         vlan->mcdef);
4560                                         vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4561                                         return rc;
4562                                 }
4563                         } else {
4564                                 EFX_WARN_ON_PARANOID(vlan->bcast !=
4565                                                      EFX_EF10_FILTER_ID_INVALID);
4566                                 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4567                         }
4568                 }
4569                 rc = 0;
4570         } else {
4571                 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4572                 vlan->ucdef = rc;
4573                 rc = 0;
4574         }
4575         return rc;
4576 }
4577
4578 /* Remove filters that weren't renewed.  Since nothing else changes the AUTO_OLD
4579  * flag or removes these filters, we don't need to hold the filter_lock while
4580  * scanning for these filters.
4581  */
4582 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4583 {
4584         struct efx_ef10_filter_table *table = efx->filter_state;
4585         int remove_failed = 0;
4586         int remove_noent = 0;
4587         int rc;
4588         int i;
4589
4590         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4591                 if (ACCESS_ONCE(table->entry[i].spec) &
4592                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4593                         rc = efx_ef10_filter_remove_internal(efx,
4594                                         1U << EFX_FILTER_PRI_AUTO, i, true);
4595                         if (rc == -ENOENT)
4596                                 remove_noent++;
4597                         else if (rc)
4598                                 remove_failed++;
4599                 }
4600         }
4601
4602         if (remove_failed)
4603                 netif_info(efx, drv, efx->net_dev,
4604                            "%s: failed to remove %d filters\n",
4605                            __func__, remove_failed);
4606         if (remove_noent)
4607                 netif_info(efx, drv, efx->net_dev,
4608                            "%s: failed to remove %d non-existent filters\n",
4609                            __func__, remove_noent);
4610 }
4611
4612 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4613 {
4614         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4615         u8 mac_old[ETH_ALEN];
4616         int rc, rc2;
4617
4618         /* Only reconfigure a PF-created vport */
4619         if (is_zero_ether_addr(nic_data->vport_mac))
4620                 return 0;
4621
4622         efx_device_detach_sync(efx);
4623         efx_net_stop(efx->net_dev);
4624         down_write(&efx->filter_sem);
4625         efx_ef10_filter_table_remove(efx);
4626         up_write(&efx->filter_sem);
4627
4628         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4629         if (rc)
4630                 goto restore_filters;
4631
4632         ether_addr_copy(mac_old, nic_data->vport_mac);
4633         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4634                                     nic_data->vport_mac);
4635         if (rc)
4636                 goto restore_vadaptor;
4637
4638         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4639                                     efx->net_dev->dev_addr);
4640         if (!rc) {
4641                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4642         } else {
4643                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4644                 if (rc2) {
4645                         /* Failed to add original MAC, so clear vport_mac */
4646                         eth_zero_addr(nic_data->vport_mac);
4647                         goto reset_nic;
4648                 }
4649         }
4650
4651 restore_vadaptor:
4652         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4653         if (rc2)
4654                 goto reset_nic;
4655 restore_filters:
4656         down_write(&efx->filter_sem);
4657         rc2 = efx_ef10_filter_table_probe(efx);
4658         up_write(&efx->filter_sem);
4659         if (rc2)
4660                 goto reset_nic;
4661
4662         rc2 = efx_net_open(efx->net_dev);
4663         if (rc2)
4664                 goto reset_nic;
4665
4666         netif_device_attach(efx->net_dev);
4667
4668         return rc;
4669
4670 reset_nic:
4671         netif_err(efx, drv, efx->net_dev,
4672                   "Failed to restore when changing MAC address - scheduling reset\n");
4673         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4674
4675         return rc ? rc : rc2;
4676 }
4677
4678 /* Caller must hold efx->filter_sem for read if race against
4679  * efx_ef10_filter_table_remove() is possible
4680  */
4681 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4682                                               struct efx_ef10_filter_vlan *vlan)
4683 {
4684         struct efx_ef10_filter_table *table = efx->filter_state;
4685         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4686
4687         /* Do not install unspecified VID if VLAN filtering is enabled.
4688          * Do not install all specified VIDs if VLAN filtering is disabled.
4689          */
4690         if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
4691                 return;
4692
4693         /* Insert/renew unicast filters */
4694         if (table->uc_promisc) {
4695                 efx_ef10_filter_insert_def(efx, vlan, false, false);
4696                 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
4697         } else {
4698                 /* If any of the filters failed to insert, fall back to
4699                  * promiscuous mode - add in the uc_def filter.  But keep
4700                  * our individual unicast filters.
4701                  */
4702                 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
4703                         efx_ef10_filter_insert_def(efx, vlan, false, false);
4704         }
4705
4706         /* Insert/renew multicast filters */
4707         /* If changing promiscuous state with cascaded multicast filters, remove
4708          * old filters first, so that packets are dropped rather than duplicated
4709          */
4710         if (nic_data->workaround_26807 &&
4711             table->mc_promisc_last != table->mc_promisc)
4712                 efx_ef10_filter_remove_old(efx);
4713         if (table->mc_promisc) {
4714                 if (nic_data->workaround_26807) {
4715                         /* If we failed to insert promiscuous filters, rollback
4716                          * and fall back to individual multicast filters
4717                          */
4718                         if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
4719                                 /* Changing promisc state, so remove old filters */
4720                                 efx_ef10_filter_remove_old(efx);
4721                                 efx_ef10_filter_insert_addr_list(efx, vlan,
4722                                                                  true, false);
4723                         }
4724                 } else {
4725                         /* If we failed to insert promiscuous filters, don't
4726                          * rollback.  Regardless, also insert the mc_list
4727                          */
4728                         efx_ef10_filter_insert_def(efx, vlan, true, false);
4729                         efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
4730                 }
4731         } else {
4732                 /* If any filters failed to insert, rollback and fall back to
4733                  * promiscuous mode - mc_def filter and maybe broadcast.  If
4734                  * that fails, roll back again and insert as many of our
4735                  * individual multicast filters as we can.
4736                  */
4737                 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
4738                         /* Changing promisc state, so remove old filters */
4739                         if (nic_data->workaround_26807)
4740                                 efx_ef10_filter_remove_old(efx);
4741                         if (efx_ef10_filter_insert_def(efx, vlan, true, true))
4742                                 efx_ef10_filter_insert_addr_list(efx, vlan,
4743                                                                  true, false);
4744                 }
4745         }
4746 }
4747
4748 /* Caller must hold efx->filter_sem for read if race against
4749  * efx_ef10_filter_table_remove() is possible
4750  */
4751 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4752 {
4753         struct efx_ef10_filter_table *table = efx->filter_state;
4754         struct net_device *net_dev = efx->net_dev;
4755         struct efx_ef10_filter_vlan *vlan;
4756         bool vlan_filter;
4757
4758         if (!efx_dev_registered(efx))
4759                 return;
4760
4761         if (!table)
4762                 return;
4763
4764         efx_ef10_filter_mark_old(efx);
4765
4766         /* Copy/convert the address lists; add the primary station
4767          * address and broadcast address
4768          */
4769         netif_addr_lock_bh(net_dev);
4770         efx_ef10_filter_uc_addr_list(efx);
4771         efx_ef10_filter_mc_addr_list(efx);
4772         netif_addr_unlock_bh(net_dev);
4773
4774         /* If VLAN filtering changes, all old filters are finally removed.
4775          * Do it in advance to avoid conflicts for unicast untagged and
4776          * VLAN 0 tagged filters.
4777          */
4778         vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4779         if (table->vlan_filter != vlan_filter) {
4780                 table->vlan_filter = vlan_filter;
4781                 efx_ef10_filter_remove_old(efx);
4782         }
4783
4784         list_for_each_entry(vlan, &table->vlan_list, list)
4785                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4786
4787         efx_ef10_filter_remove_old(efx);
4788         table->mc_promisc_last = table->mc_promisc;
4789 }
4790
4791 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
4792 {
4793         struct efx_ef10_filter_table *table = efx->filter_state;
4794         struct efx_ef10_filter_vlan *vlan;
4795
4796         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4797
4798         list_for_each_entry(vlan, &table->vlan_list, list) {
4799                 if (vlan->vid == vid)
4800                         return vlan;
4801         }
4802
4803         return NULL;
4804 }
4805
4806 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
4807 {
4808         struct efx_ef10_filter_table *table = efx->filter_state;
4809         struct efx_ef10_filter_vlan *vlan;
4810         unsigned int i;
4811
4812         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4813                 return -EINVAL;
4814
4815         vlan = efx_ef10_filter_find_vlan(efx, vid);
4816         if (WARN_ON(vlan)) {
4817                 netif_err(efx, drv, efx->net_dev,
4818                           "VLAN %u already added\n", vid);
4819                 return -EALREADY;
4820         }
4821
4822         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
4823         if (!vlan)
4824                 return -ENOMEM;
4825
4826         vlan->vid = vid;
4827
4828         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4829                 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
4830         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4831                 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
4832         vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
4833         vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
4834         vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4835
4836         list_add_tail(&vlan->list, &table->vlan_list);
4837
4838         if (efx_dev_registered(efx))
4839                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4840
4841         return 0;
4842 }
4843
4844 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
4845                                               struct efx_ef10_filter_vlan *vlan)
4846 {
4847         unsigned int i;
4848
4849         /* See comment in efx_ef10_filter_table_remove() */
4850         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4851                 return;
4852
4853         list_del(&vlan->list);
4854
4855         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4856                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4857                                               vlan->uc[i]);
4858         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4859                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4860                                               vlan->mc[i]);
4861         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
4862         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
4863         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
4864
4865         kfree(vlan);
4866 }
4867
4868 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
4869 {
4870         struct efx_ef10_filter_vlan *vlan;
4871
4872         /* See comment in efx_ef10_filter_table_remove() */
4873         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4874                 return;
4875
4876         vlan = efx_ef10_filter_find_vlan(efx, vid);
4877         if (!vlan) {
4878                 netif_err(efx, drv, efx->net_dev,
4879                           "VLAN %u not found in filter state\n", vid);
4880                 return;
4881         }
4882
4883         efx_ef10_filter_del_vlan_internal(efx, vlan);
4884 }
4885
4886 static int efx_ef10_set_mac_address(struct efx_nic *efx)
4887 {
4888         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4889         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4890         bool was_enabled = efx->port_enabled;
4891         int rc;
4892
4893         efx_device_detach_sync(efx);
4894         efx_net_stop(efx->net_dev);
4895
4896         mutex_lock(&efx->mac_lock);
4897         down_write(&efx->filter_sem);
4898         efx_ef10_filter_table_remove(efx);
4899
4900         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4901                         efx->net_dev->dev_addr);
4902         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4903                        nic_data->vport_id);
4904         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4905                                 sizeof(inbuf), NULL, 0, NULL);
4906
4907         efx_ef10_filter_table_probe(efx);
4908         up_write(&efx->filter_sem);
4909         mutex_unlock(&efx->mac_lock);
4910
4911         if (was_enabled)
4912                 efx_net_open(efx->net_dev);
4913         netif_device_attach(efx->net_dev);
4914
4915 #ifdef CONFIG_SFC_SRIOV
4916         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
4917                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4918
4919                 if (rc == -EPERM) {
4920                         struct efx_nic *efx_pf;
4921
4922                         /* Switch to PF and change MAC address on vport */
4923                         efx_pf = pci_get_drvdata(pci_dev_pf);
4924
4925                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4926                                                        nic_data->vf_index,
4927                                                        efx->net_dev->dev_addr);
4928                 } else if (!rc) {
4929                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4930                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4931                         unsigned int i;
4932
4933                         /* MAC address successfully changed by VF (with MAC
4934                          * spoofing) so update the parent PF if possible.
4935                          */
4936                         for (i = 0; i < efx_pf->vf_count; ++i) {
4937                                 struct ef10_vf *vf = nic_data->vf + i;
4938
4939                                 if (vf->efx == efx) {
4940                                         ether_addr_copy(vf->mac,
4941                                                         efx->net_dev->dev_addr);
4942                                         return 0;
4943                                 }
4944                         }
4945                 }
4946         } else
4947 #endif
4948         if (rc == -EPERM) {
4949                 netif_err(efx, drv, efx->net_dev,
4950                           "Cannot change MAC address; use sfboot to enable"
4951                           " mac-spoofing on this interface\n");
4952         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4953                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4954                  * fall-back to the method of changing the MAC address on the
4955                  * vport.  This only applies to PFs because such versions of
4956                  * MCFW do not support VFs.
4957                  */
4958                 rc = efx_ef10_vport_set_mac_address(efx);
4959         } else {
4960                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4961                                        sizeof(inbuf), NULL, 0, rc);
4962         }
4963
4964         return rc;
4965 }
4966
4967 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4968 {
4969         efx_ef10_filter_sync_rx_mode(efx);
4970
4971         return efx_mcdi_set_mac(efx);
4972 }
4973
4974 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4975 {
4976         efx_ef10_filter_sync_rx_mode(efx);
4977
4978         return 0;
4979 }
4980
4981 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4982 {
4983         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4984
4985         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4986         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4987                             NULL, 0, NULL);
4988 }
4989
4990 /* MC BISTs follow a different poll mechanism to phy BISTs.
4991  * The BIST is done in the poll handler on the MC, and the MCDI command
4992  * will block until the BIST is done.
4993  */
4994 static int efx_ef10_poll_bist(struct efx_nic *efx)
4995 {
4996         int rc;
4997         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4998         size_t outlen;
4999         u32 result;
5000
5001         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5002                            outbuf, sizeof(outbuf), &outlen);
5003         if (rc != 0)
5004                 return rc;
5005
5006         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5007                 return -EIO;
5008
5009         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5010         switch (result) {
5011         case MC_CMD_POLL_BIST_PASSED:
5012                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5013                 return 0;
5014         case MC_CMD_POLL_BIST_TIMEOUT:
5015                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5016                 return -EIO;
5017         case MC_CMD_POLL_BIST_FAILED:
5018                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5019                 return -EIO;
5020         default:
5021                 netif_err(efx, hw, efx->net_dev,
5022                           "BIST returned unknown result %u", result);
5023                 return -EIO;
5024         }
5025 }
5026
5027 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5028 {
5029         int rc;
5030
5031         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5032
5033         rc = efx_ef10_start_bist(efx, bist_type);
5034         if (rc != 0)
5035                 return rc;
5036
5037         return efx_ef10_poll_bist(efx);
5038 }
5039
5040 static int
5041 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5042 {
5043         int rc, rc2;
5044
5045         efx_reset_down(efx, RESET_TYPE_WORLD);
5046
5047         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5048                           NULL, 0, NULL, 0, NULL);
5049         if (rc != 0)
5050                 goto out;
5051
5052         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5053         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5054
5055         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5056
5057 out:
5058         if (rc == -EPERM)
5059                 rc = 0;
5060         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5061         return rc ? rc : rc2;
5062 }
5063
5064 #ifdef CONFIG_SFC_MTD
5065
5066 struct efx_ef10_nvram_type_info {
5067         u16 type, type_mask;
5068         u8 port;
5069         const char *name;
5070 };
5071
5072 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5073         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
5074         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
5075         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
5076         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
5077         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
5078         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
5079         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
5080         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
5081         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
5082         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
5083         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
5084 };
5085
5086 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5087                                         struct efx_mcdi_mtd_partition *part,
5088                                         unsigned int type)
5089 {
5090         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5091         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5092         const struct efx_ef10_nvram_type_info *info;
5093         size_t size, erase_size, outlen;
5094         bool protected;
5095         int rc;
5096
5097         for (info = efx_ef10_nvram_types; ; info++) {
5098                 if (info ==
5099                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5100                         return -ENODEV;
5101                 if ((type & ~info->type_mask) == info->type)
5102                         break;
5103         }
5104         if (info->port != efx_port_num(efx))
5105                 return -ENODEV;
5106
5107         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5108         if (rc)
5109                 return rc;
5110         if (protected)
5111                 return -ENODEV; /* hide it */
5112
5113         part->nvram_type = type;
5114
5115         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5116         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5117                           outbuf, sizeof(outbuf), &outlen);
5118         if (rc)
5119                 return rc;
5120         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5121                 return -EIO;
5122         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5123             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5124                 part->fw_subtype = MCDI_DWORD(outbuf,
5125                                               NVRAM_METADATA_OUT_SUBTYPE);
5126
5127         part->common.dev_type_name = "EF10 NVRAM manager";
5128         part->common.type_name = info->name;
5129
5130         part->common.mtd.type = MTD_NORFLASH;
5131         part->common.mtd.flags = MTD_CAP_NORFLASH;
5132         part->common.mtd.size = size;
5133         part->common.mtd.erasesize = erase_size;
5134
5135         return 0;
5136 }
5137
5138 static int efx_ef10_mtd_probe(struct efx_nic *efx)
5139 {
5140         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5141         struct efx_mcdi_mtd_partition *parts;
5142         size_t outlen, n_parts_total, i, n_parts;
5143         unsigned int type;
5144         int rc;
5145
5146         ASSERT_RTNL();
5147
5148         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5149         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5150                           outbuf, sizeof(outbuf), &outlen);
5151         if (rc)
5152                 return rc;
5153         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5154                 return -EIO;
5155
5156         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5157         if (n_parts_total >
5158             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5159                 return -EIO;
5160
5161         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5162         if (!parts)
5163                 return -ENOMEM;
5164
5165         n_parts = 0;
5166         for (i = 0; i < n_parts_total; i++) {
5167                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5168                                         i);
5169                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5170                 if (rc == 0)
5171                         n_parts++;
5172                 else if (rc != -ENODEV)
5173                         goto fail;
5174         }
5175
5176         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5177 fail:
5178         if (rc)
5179                 kfree(parts);
5180         return rc;
5181 }
5182
5183 #endif /* CONFIG_SFC_MTD */
5184
5185 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5186 {
5187         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5188 }
5189
5190 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5191                                             u32 host_time) {}
5192
5193 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5194                                            bool temp)
5195 {
5196         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5197         int rc;
5198
5199         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5200             channel->sync_events_state == SYNC_EVENTS_VALID ||
5201             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5202                 return 0;
5203         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5204
5205         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5206         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5207         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5208                        channel->channel);
5209
5210         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5211                           inbuf, sizeof(inbuf), NULL, 0, NULL);
5212
5213         if (rc != 0)
5214                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5215                                                     SYNC_EVENTS_DISABLED;
5216
5217         return rc;
5218 }
5219
5220 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5221                                             bool temp)
5222 {
5223         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5224         int rc;
5225
5226         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5227             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5228                 return 0;
5229         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5230                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5231                 return 0;
5232         }
5233         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5234                                             SYNC_EVENTS_DISABLED;
5235
5236         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5237         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5238         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5239                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5240         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5241                        channel->channel);
5242
5243         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5244                           inbuf, sizeof(inbuf), NULL, 0, NULL);
5245
5246         return rc;
5247 }
5248
5249 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5250                                            bool temp)
5251 {
5252         int (*set)(struct efx_channel *channel, bool temp);
5253         struct efx_channel *channel;
5254
5255         set = en ?
5256               efx_ef10_rx_enable_timestamping :
5257               efx_ef10_rx_disable_timestamping;
5258
5259         efx_for_each_channel(channel, efx) {
5260                 int rc = set(channel, temp);
5261                 if (en && rc != 0) {
5262                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5263                         return rc;
5264                 }
5265         }
5266
5267         return 0;
5268 }
5269
5270 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5271                                          struct hwtstamp_config *init)
5272 {
5273         return -EOPNOTSUPP;
5274 }
5275
5276 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5277                                       struct hwtstamp_config *init)
5278 {
5279         int rc;
5280
5281         switch (init->rx_filter) {
5282         case HWTSTAMP_FILTER_NONE:
5283                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5284                 /* if TX timestamping is still requested then leave PTP on */
5285                 return efx_ptp_change_mode(efx,
5286                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
5287         case HWTSTAMP_FILTER_ALL:
5288         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5289         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5290         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5291         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5292         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5293         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5294         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5295         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5296         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5297         case HWTSTAMP_FILTER_PTP_V2_EVENT:
5298         case HWTSTAMP_FILTER_PTP_V2_SYNC:
5299         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5300                 init->rx_filter = HWTSTAMP_FILTER_ALL;
5301                 rc = efx_ptp_change_mode(efx, true, 0);
5302                 if (!rc)
5303                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5304                 if (rc)
5305                         efx_ptp_change_mode(efx, false, 0);
5306                 return rc;
5307         default:
5308                 return -ERANGE;
5309         }
5310 }
5311
5312 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5313 {
5314         if (proto != htons(ETH_P_8021Q))
5315                 return -EINVAL;
5316
5317         return efx_ef10_add_vlan(efx, vid);
5318 }
5319
5320 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5321 {
5322         if (proto != htons(ETH_P_8021Q))
5323                 return -EINVAL;
5324
5325         return efx_ef10_del_vlan(efx, vid);
5326 }
5327
5328 #define EF10_OFFLOAD_FEATURES           \
5329         (NETIF_F_IP_CSUM |              \
5330          NETIF_F_HW_VLAN_CTAG_FILTER |  \
5331          NETIF_F_IPV6_CSUM |            \
5332          NETIF_F_RXHASH |               \
5333          NETIF_F_NTUPLE)
5334
5335 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
5336         .is_vf = true,
5337         .mem_bar = EFX_MEM_VF_BAR,
5338         .mem_map_size = efx_ef10_mem_map_size,
5339         .probe = efx_ef10_probe_vf,
5340         .remove = efx_ef10_remove,
5341         .dimension_resources = efx_ef10_dimension_resources,
5342         .init = efx_ef10_init_nic,
5343         .fini = efx_port_dummy_op_void,
5344         .map_reset_reason = efx_ef10_map_reset_reason,
5345         .map_reset_flags = efx_ef10_map_reset_flags,
5346         .reset = efx_ef10_reset,
5347         .probe_port = efx_mcdi_port_probe,
5348         .remove_port = efx_mcdi_port_remove,
5349         .fini_dmaq = efx_ef10_fini_dmaq,
5350         .prepare_flr = efx_ef10_prepare_flr,
5351         .finish_flr = efx_port_dummy_op_void,
5352         .describe_stats = efx_ef10_describe_stats,
5353         .update_stats = efx_ef10_update_stats_vf,
5354         .start_stats = efx_port_dummy_op_void,
5355         .pull_stats = efx_port_dummy_op_void,
5356         .stop_stats = efx_port_dummy_op_void,
5357         .set_id_led = efx_mcdi_set_id_led,
5358         .push_irq_moderation = efx_ef10_push_irq_moderation,
5359         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
5360         .check_mac_fault = efx_mcdi_mac_check_fault,
5361         .reconfigure_port = efx_mcdi_port_reconfigure,
5362         .get_wol = efx_ef10_get_wol_vf,
5363         .set_wol = efx_ef10_set_wol_vf,
5364         .resume_wol = efx_port_dummy_op_void,
5365         .mcdi_request = efx_ef10_mcdi_request,
5366         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5367         .mcdi_read_response = efx_ef10_mcdi_read_response,
5368         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5369         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5370         .irq_enable_master = efx_port_dummy_op_void,
5371         .irq_test_generate = efx_ef10_irq_test_generate,
5372         .irq_disable_non_ev = efx_port_dummy_op_void,
5373         .irq_handle_msi = efx_ef10_msi_interrupt,
5374         .irq_handle_legacy = efx_ef10_legacy_interrupt,
5375         .tx_probe = efx_ef10_tx_probe,
5376         .tx_init = efx_ef10_tx_init,
5377         .tx_remove = efx_ef10_tx_remove,
5378         .tx_write = efx_ef10_tx_write,
5379         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
5380         .rx_probe = efx_ef10_rx_probe,
5381         .rx_init = efx_ef10_rx_init,
5382         .rx_remove = efx_ef10_rx_remove,
5383         .rx_write = efx_ef10_rx_write,
5384         .rx_defer_refill = efx_ef10_rx_defer_refill,
5385         .ev_probe = efx_ef10_ev_probe,
5386         .ev_init = efx_ef10_ev_init,
5387         .ev_fini = efx_ef10_ev_fini,
5388         .ev_remove = efx_ef10_ev_remove,
5389         .ev_process = efx_ef10_ev_process,
5390         .ev_read_ack = efx_ef10_ev_read_ack,
5391         .ev_test_generate = efx_ef10_ev_test_generate,
5392         .filter_table_probe = efx_ef10_filter_table_probe,
5393         .filter_table_restore = efx_ef10_filter_table_restore,
5394         .filter_table_remove = efx_ef10_filter_table_remove,
5395         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5396         .filter_insert = efx_ef10_filter_insert,
5397         .filter_remove_safe = efx_ef10_filter_remove_safe,
5398         .filter_get_safe = efx_ef10_filter_get_safe,
5399         .filter_clear_rx = efx_ef10_filter_clear_rx,
5400         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5401         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5402         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5403 #ifdef CONFIG_RFS_ACCEL
5404         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5405         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5406 #endif
5407 #ifdef CONFIG_SFC_MTD
5408         .mtd_probe = efx_port_dummy_op_int,
5409 #endif
5410         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5411         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
5412         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5413         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5414 #ifdef CONFIG_SFC_SRIOV
5415         .vswitching_probe = efx_ef10_vswitching_probe_vf,
5416         .vswitching_restore = efx_ef10_vswitching_restore_vf,
5417         .vswitching_remove = efx_ef10_vswitching_remove_vf,
5418         .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
5419 #endif
5420         .get_mac_address = efx_ef10_get_mac_address_vf,
5421         .set_mac_address = efx_ef10_set_mac_address,
5422
5423         .revision = EFX_REV_HUNT_A0,
5424         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5425         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5426         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5427         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5428         .can_rx_scatter = true,
5429         .always_rx_scatter = true,
5430         .max_interrupt_mode = EFX_INT_MODE_MSIX,
5431         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5432         .offload_features = EF10_OFFLOAD_FEATURES,
5433         .mcdi_max_ver = 2,
5434         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5435         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5436                             1 << HWTSTAMP_FILTER_ALL,
5437 };
5438
5439 const struct efx_nic_type efx_hunt_a0_nic_type = {
5440         .is_vf = false,
5441         .mem_bar = EFX_MEM_BAR,
5442         .mem_map_size = efx_ef10_mem_map_size,
5443         .probe = efx_ef10_probe_pf,
5444         .remove = efx_ef10_remove,
5445         .dimension_resources = efx_ef10_dimension_resources,
5446         .init = efx_ef10_init_nic,
5447         .fini = efx_port_dummy_op_void,
5448         .map_reset_reason = efx_ef10_map_reset_reason,
5449         .map_reset_flags = efx_ef10_map_reset_flags,
5450         .reset = efx_ef10_reset,
5451         .probe_port = efx_mcdi_port_probe,
5452         .remove_port = efx_mcdi_port_remove,
5453         .fini_dmaq = efx_ef10_fini_dmaq,
5454         .prepare_flr = efx_ef10_prepare_flr,
5455         .finish_flr = efx_port_dummy_op_void,
5456         .describe_stats = efx_ef10_describe_stats,
5457         .update_stats = efx_ef10_update_stats_pf,
5458         .start_stats = efx_mcdi_mac_start_stats,
5459         .pull_stats = efx_mcdi_mac_pull_stats,
5460         .stop_stats = efx_mcdi_mac_stop_stats,
5461         .set_id_led = efx_mcdi_set_id_led,
5462         .push_irq_moderation = efx_ef10_push_irq_moderation,
5463         .reconfigure_mac = efx_ef10_mac_reconfigure,
5464         .check_mac_fault = efx_mcdi_mac_check_fault,
5465         .reconfigure_port = efx_mcdi_port_reconfigure,
5466         .get_wol = efx_ef10_get_wol,
5467         .set_wol = efx_ef10_set_wol,
5468         .resume_wol = efx_port_dummy_op_void,
5469         .test_chip = efx_ef10_test_chip,
5470         .test_nvram = efx_mcdi_nvram_test_all,
5471         .mcdi_request = efx_ef10_mcdi_request,
5472         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5473         .mcdi_read_response = efx_ef10_mcdi_read_response,
5474         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5475         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5476         .irq_enable_master = efx_port_dummy_op_void,
5477         .irq_test_generate = efx_ef10_irq_test_generate,
5478         .irq_disable_non_ev = efx_port_dummy_op_void,
5479         .irq_handle_msi = efx_ef10_msi_interrupt,
5480         .irq_handle_legacy = efx_ef10_legacy_interrupt,
5481         .tx_probe = efx_ef10_tx_probe,
5482         .tx_init = efx_ef10_tx_init,
5483         .tx_remove = efx_ef10_tx_remove,
5484         .tx_write = efx_ef10_tx_write,
5485         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
5486         .rx_probe = efx_ef10_rx_probe,
5487         .rx_init = efx_ef10_rx_init,
5488         .rx_remove = efx_ef10_rx_remove,
5489         .rx_write = efx_ef10_rx_write,
5490         .rx_defer_refill = efx_ef10_rx_defer_refill,
5491         .ev_probe = efx_ef10_ev_probe,
5492         .ev_init = efx_ef10_ev_init,
5493         .ev_fini = efx_ef10_ev_fini,
5494         .ev_remove = efx_ef10_ev_remove,
5495         .ev_process = efx_ef10_ev_process,
5496         .ev_read_ack = efx_ef10_ev_read_ack,
5497         .ev_test_generate = efx_ef10_ev_test_generate,
5498         .filter_table_probe = efx_ef10_filter_table_probe,
5499         .filter_table_restore = efx_ef10_filter_table_restore,
5500         .filter_table_remove = efx_ef10_filter_table_remove,
5501         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5502         .filter_insert = efx_ef10_filter_insert,
5503         .filter_remove_safe = efx_ef10_filter_remove_safe,
5504         .filter_get_safe = efx_ef10_filter_get_safe,
5505         .filter_clear_rx = efx_ef10_filter_clear_rx,
5506         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5507         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5508         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5509 #ifdef CONFIG_RFS_ACCEL
5510         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5511         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5512 #endif
5513 #ifdef CONFIG_SFC_MTD
5514         .mtd_probe = efx_ef10_mtd_probe,
5515         .mtd_rename = efx_mcdi_mtd_rename,
5516         .mtd_read = efx_mcdi_mtd_read,
5517         .mtd_erase = efx_mcdi_mtd_erase,
5518         .mtd_write = efx_mcdi_mtd_write,
5519         .mtd_sync = efx_mcdi_mtd_sync,
5520 #endif
5521         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
5522         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5523         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
5524         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5525         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5526 #ifdef CONFIG_SFC_SRIOV
5527         .sriov_configure = efx_ef10_sriov_configure,
5528         .sriov_init = efx_ef10_sriov_init,
5529         .sriov_fini = efx_ef10_sriov_fini,
5530         .sriov_wanted = efx_ef10_sriov_wanted,
5531         .sriov_reset = efx_ef10_sriov_reset,
5532         .sriov_flr = efx_ef10_sriov_flr,
5533         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5534         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5535         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5536         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
5537         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
5538         .vswitching_probe = efx_ef10_vswitching_probe_pf,
5539         .vswitching_restore = efx_ef10_vswitching_restore_pf,
5540         .vswitching_remove = efx_ef10_vswitching_remove_pf,
5541 #endif
5542         .get_mac_address = efx_ef10_get_mac_address_pf,
5543         .set_mac_address = efx_ef10_set_mac_address,
5544
5545         .revision = EFX_REV_HUNT_A0,
5546         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5547         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5548         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5549         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5550         .can_rx_scatter = true,
5551         .always_rx_scatter = true,
5552         .max_interrupt_mode = EFX_INT_MODE_MSIX,
5553         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5554         .offload_features = EF10_OFFLOAD_FEATURES,
5555         .mcdi_max_ver = 2,
5556         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5557         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5558                             1 << HWTSTAMP_FILTER_ALL,
5559 };