2 * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/stmmac.h>
20 #include <linux/bitops.h>
21 #include <linux/clk.h>
22 #include <linux/phy.h>
23 #include <linux/of_net.h>
24 #include <linux/gpio.h>
25 #include <linux/module.h>
26 #include <linux/of_gpio.h>
27 #include <linux/of_device.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/delay.h>
31 #include <linux/mfd/syscon.h>
32 #include <linux/regmap.h>
34 #include "stmmac_platform.h"
38 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
39 int tx_delay, int rx_delay);
40 void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
41 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
42 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
46 struct platform_device *pdev;
48 struct regulator *regulator;
50 const struct rk_gmac_ops *ops;
56 struct clk *gmac_clkin;
57 struct clk *mac_clk_rx;
58 struct clk *mac_clk_tx;
59 struct clk *clk_mac_ref;
60 struct clk *clk_mac_refout;
70 #define HIWORD_UPDATE(val, mask, shift) \
71 ((val) << (shift) | (mask) << ((shift) + 16))
73 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
74 #define GRF_CLR_BIT(nr) (BIT(nr+16))
76 #define RK3228_GRF_MAC_CON0 0x0900
77 #define RK3228_GRF_MAC_CON1 0x0904
79 /* RK3228_GRF_MAC_CON0 */
80 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
81 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
83 /* RK3228_GRF_MAC_CON1 */
84 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \
85 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
86 #define RK3228_GMAC_PHY_INTF_SEL_RMII \
87 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
88 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
89 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
90 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
91 #define RK3228_GMAC_SPEED_100M GRF_BIT(2)
92 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
93 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
94 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
95 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
96 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
97 #define RK3228_GMAC_RMII_MODE GRF_BIT(10)
98 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
99 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
100 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
101 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
102 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
104 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
105 int tx_delay, int rx_delay)
107 struct device *dev = &bsp_priv->pdev->dev;
109 if (IS_ERR(bsp_priv->grf)) {
110 dev_err(dev, "Missing rockchip,grf property\n");
114 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
115 RK3228_GMAC_PHY_INTF_SEL_RGMII |
116 RK3228_GMAC_RMII_MODE_CLR |
117 RK3228_GMAC_RXCLK_DLY_ENABLE |
118 RK3228_GMAC_TXCLK_DLY_ENABLE);
120 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
121 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
122 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
125 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
127 struct device *dev = &bsp_priv->pdev->dev;
129 if (IS_ERR(bsp_priv->grf)) {
130 dev_err(dev, "Missing rockchip,grf property\n");
134 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
135 RK3228_GMAC_PHY_INTF_SEL_RMII |
136 RK3228_GMAC_RMII_MODE);
138 /* set MAC to RMII mode */
139 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
142 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
144 struct device *dev = &bsp_priv->pdev->dev;
146 if (IS_ERR(bsp_priv->grf)) {
147 dev_err(dev, "Missing rockchip,grf property\n");
152 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
153 RK3228_GMAC_CLK_2_5M);
154 else if (speed == 100)
155 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
156 RK3228_GMAC_CLK_25M);
157 else if (speed == 1000)
158 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
159 RK3228_GMAC_CLK_125M);
161 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
164 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
166 struct device *dev = &bsp_priv->pdev->dev;
168 if (IS_ERR(bsp_priv->grf)) {
169 dev_err(dev, "Missing rockchip,grf property\n");
174 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
175 RK3228_GMAC_RMII_CLK_2_5M |
176 RK3228_GMAC_SPEED_10M);
177 else if (speed == 100)
178 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
179 RK3228_GMAC_RMII_CLK_25M |
180 RK3228_GMAC_SPEED_100M);
182 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
185 static const struct rk_gmac_ops rk3228_ops = {
186 .set_to_rgmii = rk3228_set_to_rgmii,
187 .set_to_rmii = rk3228_set_to_rmii,
188 .set_rgmii_speed = rk3228_set_rgmii_speed,
189 .set_rmii_speed = rk3228_set_rmii_speed,
192 #define RK3288_GRF_SOC_CON1 0x0248
193 #define RK3288_GRF_SOC_CON3 0x0250
195 /*RK3288_GRF_SOC_CON1*/
196 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
198 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
200 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
201 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
202 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
203 #define RK3288_GMAC_SPEED_100M GRF_BIT(10)
204 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
205 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
206 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
207 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
208 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
209 #define RK3288_GMAC_RMII_MODE GRF_BIT(14)
210 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
212 /*RK3288_GRF_SOC_CON3*/
213 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
214 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
215 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
216 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
217 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
218 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
220 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
221 int tx_delay, int rx_delay)
223 struct device *dev = &bsp_priv->pdev->dev;
225 if (IS_ERR(bsp_priv->grf)) {
226 dev_err(dev, "Missing rockchip,grf property\n");
230 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
231 RK3288_GMAC_PHY_INTF_SEL_RGMII |
232 RK3288_GMAC_RMII_MODE_CLR);
233 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
234 RK3288_GMAC_RXCLK_DLY_ENABLE |
235 RK3288_GMAC_TXCLK_DLY_ENABLE |
236 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
237 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
240 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
242 struct device *dev = &bsp_priv->pdev->dev;
244 if (IS_ERR(bsp_priv->grf)) {
245 dev_err(dev, "Missing rockchip,grf property\n");
249 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
250 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
253 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
255 struct device *dev = &bsp_priv->pdev->dev;
257 if (IS_ERR(bsp_priv->grf)) {
258 dev_err(dev, "Missing rockchip,grf property\n");
263 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
264 RK3288_GMAC_CLK_2_5M);
265 else if (speed == 100)
266 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
267 RK3288_GMAC_CLK_25M);
268 else if (speed == 1000)
269 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
270 RK3288_GMAC_CLK_125M);
272 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
275 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
277 struct device *dev = &bsp_priv->pdev->dev;
279 if (IS_ERR(bsp_priv->grf)) {
280 dev_err(dev, "Missing rockchip,grf property\n");
285 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
286 RK3288_GMAC_RMII_CLK_2_5M |
287 RK3288_GMAC_SPEED_10M);
288 } else if (speed == 100) {
289 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
290 RK3288_GMAC_RMII_CLK_25M |
291 RK3288_GMAC_SPEED_100M);
293 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
297 static const struct rk_gmac_ops rk3288_ops = {
298 .set_to_rgmii = rk3288_set_to_rgmii,
299 .set_to_rmii = rk3288_set_to_rmii,
300 .set_rgmii_speed = rk3288_set_rgmii_speed,
301 .set_rmii_speed = rk3288_set_rmii_speed,
304 #define RK3368_GRF_SOC_CON15 0x043c
305 #define RK3368_GRF_SOC_CON16 0x0440
307 /* RK3368_GRF_SOC_CON15 */
308 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
310 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
312 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
313 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
314 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
315 #define RK3368_GMAC_SPEED_100M GRF_BIT(7)
316 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
317 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
318 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
319 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
320 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
321 #define RK3368_GMAC_RMII_MODE GRF_BIT(6)
322 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
324 /* RK3368_GRF_SOC_CON16 */
325 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
326 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
327 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
328 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
329 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
330 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
332 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
333 int tx_delay, int rx_delay)
335 struct device *dev = &bsp_priv->pdev->dev;
337 if (IS_ERR(bsp_priv->grf)) {
338 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
342 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
343 RK3368_GMAC_PHY_INTF_SEL_RGMII |
344 RK3368_GMAC_RMII_MODE_CLR);
345 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
346 RK3368_GMAC_RXCLK_DLY_ENABLE |
347 RK3368_GMAC_TXCLK_DLY_ENABLE |
348 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
349 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
352 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
354 struct device *dev = &bsp_priv->pdev->dev;
356 if (IS_ERR(bsp_priv->grf)) {
357 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
361 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
362 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
365 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
367 struct device *dev = &bsp_priv->pdev->dev;
369 if (IS_ERR(bsp_priv->grf)) {
370 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
375 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
376 RK3368_GMAC_CLK_2_5M);
377 else if (speed == 100)
378 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
379 RK3368_GMAC_CLK_25M);
380 else if (speed == 1000)
381 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
382 RK3368_GMAC_CLK_125M);
384 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
387 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
389 struct device *dev = &bsp_priv->pdev->dev;
391 if (IS_ERR(bsp_priv->grf)) {
392 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
397 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
398 RK3368_GMAC_RMII_CLK_2_5M |
399 RK3368_GMAC_SPEED_10M);
400 } else if (speed == 100) {
401 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
402 RK3368_GMAC_RMII_CLK_25M |
403 RK3368_GMAC_SPEED_100M);
405 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
409 static const struct rk_gmac_ops rk3368_ops = {
410 .set_to_rgmii = rk3368_set_to_rgmii,
411 .set_to_rmii = rk3368_set_to_rmii,
412 .set_rgmii_speed = rk3368_set_rgmii_speed,
413 .set_rmii_speed = rk3368_set_rmii_speed,
416 static int gmac_clk_init(struct rk_priv_data *bsp_priv)
418 struct device *dev = &bsp_priv->pdev->dev;
420 bsp_priv->clk_enabled = false;
422 bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
423 if (IS_ERR(bsp_priv->mac_clk_rx))
424 dev_err(dev, "cannot get clock %s\n",
427 bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
428 if (IS_ERR(bsp_priv->mac_clk_tx))
429 dev_err(dev, "cannot get clock %s\n",
432 bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
433 if (IS_ERR(bsp_priv->aclk_mac))
434 dev_err(dev, "cannot get clock %s\n",
437 bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
438 if (IS_ERR(bsp_priv->pclk_mac))
439 dev_err(dev, "cannot get clock %s\n",
442 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
443 if (IS_ERR(bsp_priv->clk_mac))
444 dev_err(dev, "cannot get clock %s\n",
447 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
448 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
449 if (IS_ERR(bsp_priv->clk_mac_ref))
450 dev_err(dev, "cannot get clock %s\n",
453 if (!bsp_priv->clock_input) {
454 bsp_priv->clk_mac_refout =
455 devm_clk_get(dev, "clk_mac_refout");
456 if (IS_ERR(bsp_priv->clk_mac_refout))
457 dev_err(dev, "cannot get clock %s\n",
462 if (bsp_priv->clock_input) {
463 dev_info(dev, "clock input from PHY\n");
465 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
466 clk_set_rate(bsp_priv->clk_mac, 50000000);
472 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
474 int phy_iface = bsp_priv->phy_iface;
477 if (!bsp_priv->clk_enabled) {
478 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
479 if (!IS_ERR(bsp_priv->mac_clk_rx))
481 bsp_priv->mac_clk_rx);
483 if (!IS_ERR(bsp_priv->clk_mac_ref))
485 bsp_priv->clk_mac_ref);
487 if (!IS_ERR(bsp_priv->clk_mac_refout))
489 bsp_priv->clk_mac_refout);
492 if (!IS_ERR(bsp_priv->aclk_mac))
493 clk_prepare_enable(bsp_priv->aclk_mac);
495 if (!IS_ERR(bsp_priv->pclk_mac))
496 clk_prepare_enable(bsp_priv->pclk_mac);
498 if (!IS_ERR(bsp_priv->mac_clk_tx))
499 clk_prepare_enable(bsp_priv->mac_clk_tx);
502 * if (!IS_ERR(bsp_priv->clk_mac))
503 * clk_prepare_enable(bsp_priv->clk_mac);
506 bsp_priv->clk_enabled = true;
509 if (bsp_priv->clk_enabled) {
510 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
511 if (!IS_ERR(bsp_priv->mac_clk_rx))
512 clk_disable_unprepare(
513 bsp_priv->mac_clk_rx);
515 if (!IS_ERR(bsp_priv->clk_mac_ref))
516 clk_disable_unprepare(
517 bsp_priv->clk_mac_ref);
519 if (!IS_ERR(bsp_priv->clk_mac_refout))
520 clk_disable_unprepare(
521 bsp_priv->clk_mac_refout);
524 if (!IS_ERR(bsp_priv->aclk_mac))
525 clk_disable_unprepare(bsp_priv->aclk_mac);
527 if (!IS_ERR(bsp_priv->pclk_mac))
528 clk_disable_unprepare(bsp_priv->pclk_mac);
530 if (!IS_ERR(bsp_priv->mac_clk_tx))
531 clk_disable_unprepare(bsp_priv->mac_clk_tx);
533 * if (!IS_ERR(bsp_priv->clk_mac))
534 * clk_disable_unprepare(bsp_priv->clk_mac);
536 bsp_priv->clk_enabled = false;
543 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
545 struct regulator *ldo = bsp_priv->regulator;
547 struct device *dev = &bsp_priv->pdev->dev;
550 dev_err(dev, "no regulator found\n");
555 ret = regulator_enable(ldo);
557 dev_err(dev, "fail to enable phy-supply\n");
559 ret = regulator_disable(ldo);
561 dev_err(dev, "fail to disable phy-supply\n");
567 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
568 const struct rk_gmac_ops *ops)
570 struct rk_priv_data *bsp_priv;
571 struct device *dev = &pdev->dev;
573 const char *strings = NULL;
576 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
578 return ERR_PTR(-ENOMEM);
580 bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
583 bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
584 if (IS_ERR(bsp_priv->regulator)) {
585 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
586 dev_err(dev, "phy regulator is not available yet, deferred probing\n");
587 return ERR_PTR(-EPROBE_DEFER);
589 dev_err(dev, "no regulator found\n");
590 bsp_priv->regulator = NULL;
593 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
595 dev_err(dev, "Can not read property: clock_in_out.\n");
596 bsp_priv->clock_input = true;
598 dev_info(dev, "clock input or output? (%s).\n",
600 if (!strcmp(strings, "input"))
601 bsp_priv->clock_input = true;
603 bsp_priv->clock_input = false;
606 ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
608 bsp_priv->tx_delay = 0x30;
609 dev_err(dev, "Can not read property: tx_delay.");
610 dev_err(dev, "set tx_delay to 0x%x\n",
613 dev_info(dev, "TX delay(0x%x).\n", value);
614 bsp_priv->tx_delay = value;
617 ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
619 bsp_priv->rx_delay = 0x10;
620 dev_err(dev, "Can not read property: rx_delay.");
621 dev_err(dev, "set rx_delay to 0x%x\n",
624 dev_info(dev, "RX delay(0x%x).\n", value);
625 bsp_priv->rx_delay = value;
628 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
630 bsp_priv->pdev = pdev;
633 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
634 dev_info(dev, "init for RGMII\n");
635 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
637 } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
638 dev_info(dev, "init for RMII\n");
639 bsp_priv->ops->set_to_rmii(bsp_priv);
641 dev_err(dev, "NO interface defined!\n");
644 gmac_clk_init(bsp_priv);
649 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
653 ret = phy_power_on(bsp_priv, true);
657 ret = gmac_clk_enable(bsp_priv, true);
664 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
666 phy_power_on(gmac, false);
667 gmac_clk_enable(gmac, false);
670 static int rk_gmac_init(struct platform_device *pdev, void *priv)
672 struct rk_priv_data *bsp_priv = priv;
674 return rk_gmac_powerup(bsp_priv);
677 static void rk_gmac_exit(struct platform_device *pdev, void *priv)
679 struct rk_priv_data *bsp_priv = priv;
681 rk_gmac_powerdown(bsp_priv);
684 static void rk_gmac_suspend(struct platform_device *pdev, void *priv)
686 struct rk_priv_data *bsp_priv = priv;
688 /* Keep the PHY up if we use Wake-on-Lan. */
689 if (device_may_wakeup(&pdev->dev))
692 rk_gmac_powerdown(bsp_priv);
693 bsp_priv->suspended = true;
696 static void rk_gmac_resume(struct platform_device *pdev, void *priv)
698 struct rk_priv_data *bsp_priv = priv;
700 /* The PHY was up for Wake-on-Lan. */
701 if (!bsp_priv->suspended)
704 rk_gmac_powerup(bsp_priv);
705 bsp_priv->suspended = false;
708 static void rk_fix_speed(void *priv, unsigned int speed)
710 struct rk_priv_data *bsp_priv = priv;
711 struct device *dev = &bsp_priv->pdev->dev;
713 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII)
714 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
715 else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
716 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
718 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
721 static int rk_gmac_probe(struct platform_device *pdev)
723 struct plat_stmmacenet_data *plat_dat;
724 struct stmmac_resources stmmac_res;
725 const struct rk_gmac_ops *data;
728 data = of_device_get_match_data(&pdev->dev);
730 dev_err(&pdev->dev, "no of match data provided\n");
734 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
738 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
739 if (IS_ERR(plat_dat))
740 return PTR_ERR(plat_dat);
742 plat_dat->has_gmac = true;
743 plat_dat->init = rk_gmac_init;
744 plat_dat->exit = rk_gmac_exit;
745 plat_dat->fix_mac_speed = rk_fix_speed;
746 plat_dat->suspend = rk_gmac_suspend;
747 plat_dat->resume = rk_gmac_resume;
749 plat_dat->bsp_priv = rk_gmac_setup(pdev, data);
750 if (IS_ERR(plat_dat->bsp_priv))
751 return PTR_ERR(plat_dat->bsp_priv);
753 ret = rk_gmac_init(pdev, plat_dat->bsp_priv);
757 return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
760 static const struct of_device_id rk_gmac_dwmac_match[] = {
761 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
762 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
763 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
766 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
768 static struct platform_driver rk_gmac_dwmac_driver = {
769 .probe = rk_gmac_probe,
770 .remove = stmmac_pltfr_remove,
772 .name = "rk_gmac-dwmac",
773 .pm = &stmmac_pltfr_pm_ops,
774 .of_match_table = rk_gmac_dwmac_match,
777 module_platform_driver(rk_gmac_dwmac_driver);
779 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
780 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
781 MODULE_LICENSE("GPL");