drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This only implements the mac core functions for this chip.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   You should have received a copy of the GNU General Public License along with
  20   this program; if not, write to the Free Software Foundation, Inc.,
  21   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22
  23   The full GNU General Public License is included in this distribution in
  24   the file called "COPYING".
  25
  26   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  27 *******************************************************************************/
  28
  29 #include <linux/crc32.h>
  30 #include <linux/slab.h>
  31 #include <linux/ethtool.h>
  32 #include <asm/io.h>
  33 #include "dwmac1000.h"
  34
  35 static void dwmac1000_core_init(struct mac_device_info *hw, int mtu)
  36 {
  37         void __iomem *ioaddr = hw->pcsr;
  38         u32 value = readl(ioaddr + GMAC_CONTROL);
  39         value |= GMAC_CORE_INIT;
  40         if (mtu > 1500)
  41                 value |= GMAC_CONTROL_2K;
  42         if (mtu > 2000)
  43                 value |= GMAC_CONTROL_JE;
  44
  45         writel(value, ioaddr + GMAC_CONTROL);
  46
  47         /* Mask GMAC interrupts */
  48         writel(0x207, ioaddr + GMAC_INT_MASK);
  49
  50 #ifdef STMMAC_VLAN_TAG_USED
  51         /* Tag detection without filtering */
  52         writel(0x0, ioaddr + GMAC_VLAN_TAG);
  53 #endif
  54 }
  55
  56 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
  57 {
  58         void __iomem *ioaddr = hw->pcsr;
  59         u32 value = readl(ioaddr + GMAC_CONTROL);
  60
  61         value |= GMAC_CONTROL_IPC;
  62         writel(value, ioaddr + GMAC_CONTROL);
  63
  64         value = readl(ioaddr + GMAC_CONTROL);
  65
  66         return !!(value & GMAC_CONTROL_IPC);
  67 }
  68
  69 static void dwmac1000_dump_regs(struct mac_device_info *hw)
  70 {
  71         void __iomem *ioaddr = hw->pcsr;
  72         int i;
  73         pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
  74
  75         for (i = 0; i < 55; i++) {
  76                 int offset = i * 4;
  77                 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
  78                         offset, readl(ioaddr + offset));
  79         }
  80 }
  81
  82 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
  83                                     unsigned char *addr,
  84                                     unsigned int reg_n)
  85 {
  86         void __iomem *ioaddr = hw->pcsr;
  87         stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  88                             GMAC_ADDR_LOW(reg_n));
  89 }
  90
  91 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
  92                                     unsigned char *addr,
  93                                     unsigned int reg_n)
  94 {
  95         void __iomem *ioaddr = hw->pcsr;
  96         stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
  97                             GMAC_ADDR_LOW(reg_n));
  98 }
  99
 100 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
 101                                  int mcbitslog2)
 102 {
 103         int numhashregs, regs;
 104
 105         switch (mcbitslog2) {
 106         case 6:
 107                 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
 108                 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
 109                 return;
 110                 break;
 111         case 7:
 112                 numhashregs = 4;
 113                 break;
 114         case 8:
 115                 numhashregs = 8;
 116                 break;
 117         default:
 118                 pr_debug("STMMAC: err in setting mulitcast filter\n");
 119                 return;
 120                 break;
 121         }
 122         for (regs = 0; regs < numhashregs; regs++)
 123                 writel(mcfilterbits[regs],
 124                        ioaddr + GMAC_EXTHASH_BASE + regs * 4);
 125 }
 126
 127 static void dwmac1000_set_filter(struct mac_device_info *hw,
 128                                  struct net_device *dev)
 129 {
 130         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 131         unsigned int value = 0;
 132         unsigned int perfect_addr_number = hw->unicast_filter_entries;
 133         u32 mc_filter[2];
 134         int mcbitslog2 = hw->mcast_bits_log2;
 135
 136         pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
 137                  netdev_mc_count(dev), netdev_uc_count(dev));
 138
 139         memset(mc_filter, 0, sizeof(mc_filter));
 140
 141         if (dev->flags & IFF_PROMISC) {
 142                 value = GMAC_FRAME_FILTER_PR;
 143         } else if (dev->flags & IFF_ALLMULTI) {
 144                 value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
 145         } else if (!netdev_mc_empty(dev)) {
 146                 struct netdev_hw_addr *ha;
 147
 148                 /* Hash filter for multicast */
 149                 value = GMAC_FRAME_FILTER_HMC;
 150
 151                 netdev_for_each_mc_addr(ha, dev) {
 152                         /* The upper n bits of the calculated CRC are used to
 153                          * index the contents of the hash table. The number of
 154                          * bits used depends on the hardware configuration
 155                          * selected at core configuration time.
 156                          */
 157                         int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 158                                               ETH_ALEN)) >>
 159                                               (32 - mcbitslog2);
 160                         /* The most significant bit determines the register to
 161                          * use (H/L) while the other 5 bits determine the bit
 162                          * within the register.
 163                          */
 164                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 165                 }
 166         }
 167
 168         dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
 169
 170         /* Handle multiple unicast addresses (perfect filtering) */
 171         if (netdev_uc_count(dev) > perfect_addr_number)
 172                 /* Switch to promiscuous mode if more than unicast
 173                  * addresses are requested than supported by hardware.
 174                  */
 175                 value |= GMAC_FRAME_FILTER_PR;
 176         else {
 177                 int reg = 1;
 178                 struct netdev_hw_addr *ha;
 179
 180                 netdev_for_each_uc_addr(ha, dev) {
 181                         stmmac_get_mac_addr(ioaddr, ha->addr,
 182                                             GMAC_ADDR_HIGH(reg),
 183                                             GMAC_ADDR_LOW(reg));
 184                         reg++;
 185                 }
 186         }
 187
 188 #ifdef FRAME_FILTER_DEBUG
 189         /* Enable Receive all mode (to debug filtering_fail errors) */
 190         value |= GMAC_FRAME_FILTER_RA;
 191 #endif
 192         writel(value, ioaddr + GMAC_FRAME_FILTER);
 193 }
 194
 195
 196 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 197                                 unsigned int fc, unsigned int pause_time)
 198 {
 199         void __iomem *ioaddr = hw->pcsr;
 200         unsigned int flow = 0;
 201
 202         pr_debug("GMAC Flow-Control:\n");
 203         if (fc & FLOW_RX) {
 204                 pr_debug("\tReceive Flow-Control ON\n");
 205                 flow |= GMAC_FLOW_CTRL_RFE;
 206         }
 207         if (fc & FLOW_TX) {
 208                 pr_debug("\tTransmit Flow-Control ON\n");
 209                 flow |= GMAC_FLOW_CTRL_TFE;
 210         }
 211
 212         if (duplex) {
 213                 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 214                 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 215         }
 216
 217         writel(flow, ioaddr + GMAC_FLOW_CTRL);
 218 }
 219
 220 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
 221 {
 222         void __iomem *ioaddr = hw->pcsr;
 223         unsigned int pmt = 0;
 224
 225         if (mode & WAKE_MAGIC) {
 226                 pr_debug("GMAC: WOL Magic frame\n");
 227                 pmt |= power_down | magic_pkt_en;
 228         }
 229         if (mode & WAKE_UCAST) {
 230                 pr_debug("GMAC: WOL on global unicast\n");
 231                 pmt |= global_unicast;
 232         }
 233
 234         writel(pmt, ioaddr + GMAC_PMT);
 235 }
 236
 237 static int dwmac1000_irq_status(struct mac_device_info *hw,
 238                                 struct stmmac_extra_stats *x)
 239 {
 240         void __iomem *ioaddr = hw->pcsr;
 241         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 242         int ret = 0;
 243
 244         /* Not used events (e.g. MMC interrupts) are not handled. */
 245         if ((intr_status & mmc_tx_irq))
 246                 x->mmc_tx_irq_n++;
 247         if (unlikely(intr_status & mmc_rx_irq))
 248                 x->mmc_rx_irq_n++;
 249         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 250                 x->mmc_rx_csum_offload_irq_n++;
 251         if (unlikely(intr_status & pmt_irq)) {
 252                 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
 253                 readl(ioaddr + GMAC_PMT);
 254                 x->irq_receive_pmt_irq_n++;
 255         }
 256         /* MAC trx/rx EEE LPI entry/exit interrupts */
 257         if (intr_status & lpiis_irq) {
 258                 /* Clean LPI interrupt by reading the Reg 12 */
 259                 ret = readl(ioaddr + LPI_CTRL_STATUS);
 260
 261                 if (ret & LPI_CTRL_STATUS_TLPIEN)
 262                         x->irq_tx_path_in_lpi_mode_n++;
 263                 if (ret & LPI_CTRL_STATUS_TLPIEX)
 264                         x->irq_tx_path_exit_lpi_mode_n++;
 265                 if (ret & LPI_CTRL_STATUS_RLPIEN)
 266                         x->irq_rx_path_in_lpi_mode_n++;
 267                 if (ret & LPI_CTRL_STATUS_RLPIEX)
 268                         x->irq_rx_path_exit_lpi_mode_n++;
 269         }
 270
 271         if ((intr_status & pcs_ane_irq) || (intr_status & pcs_link_irq)) {
 272                 readl(ioaddr + GMAC_AN_STATUS);
 273                 x->irq_pcs_ane_n++;
 274         }
 275         if (intr_status & rgmii_irq) {
 276                 u32 status = readl(ioaddr + GMAC_S_R_GMII);
 277                 x->irq_rgmii_n++;
 278
 279                 /* Save and dump the link status. */
 280                 if (status & GMAC_S_R_GMII_LINK) {
 281                         int speed_value = (status & GMAC_S_R_GMII_SPEED) >>
 282                             GMAC_S_R_GMII_SPEED_SHIFT;
 283                         x->pcs_duplex = (status & GMAC_S_R_GMII_MODE);
 284
 285                         if (speed_value == GMAC_S_R_GMII_SPEED_125)
 286                                 x->pcs_speed = SPEED_1000;
 287                         else if (speed_value == GMAC_S_R_GMII_SPEED_25)
 288                                 x->pcs_speed = SPEED_100;
 289                         else
 290                                 x->pcs_speed = SPEED_10;
 291
 292                         x->pcs_link = 1;
 293                         pr_debug("%s: Link is Up - %d/%s\n", __func__,
 294                                  (int)x->pcs_speed,
 295                                  x->pcs_duplex ? "Full" : "Half");
 296                 } else {
 297                         x->pcs_link = 0;
 298                         pr_debug("%s: Link is Down\n", __func__);
 299                 }
 300         }
 301
 302         return ret;
 303 }
 304
 305 static void dwmac1000_set_eee_mode(struct mac_device_info *hw)
 306 {
 307         void __iomem *ioaddr = hw->pcsr;
 308         u32 value;
 309
 310         /* Enable the link status receive on RGMII, SGMII ore SMII
 311          * receive path and instruct the transmit to enter in LPI
 312          * state.
 313          */
 314         value = readl(ioaddr + LPI_CTRL_STATUS);
 315         value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 316         writel(value, ioaddr + LPI_CTRL_STATUS);
 317 }
 318
 319 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
 320 {
 321         void __iomem *ioaddr = hw->pcsr;
 322         u32 value;
 323
 324         value = readl(ioaddr + LPI_CTRL_STATUS);
 325         value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
 326         writel(value, ioaddr + LPI_CTRL_STATUS);
 327 }
 328
 329 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
 330 {
 331         void __iomem *ioaddr = hw->pcsr;
 332         u32 value;
 333
 334         value = readl(ioaddr + LPI_CTRL_STATUS);
 335
 336         if (link)
 337                 value |= LPI_CTRL_STATUS_PLS;
 338         else
 339                 value &= ~LPI_CTRL_STATUS_PLS;
 340
 341         writel(value, ioaddr + LPI_CTRL_STATUS);
 342 }
 343
 344 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 345 {
 346         void __iomem *ioaddr = hw->pcsr;
 347         int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
 348
 349         /* Program the timers in the LPI timer control register:
 350          * LS: minimum time (ms) for which the link
 351          *  status from PHY should be ok before transmitting
 352          *  the LPI pattern.
 353          * TW: minimum time (us) for which the core waits
 354          *  after it has stopped transmitting the LPI pattern.
 355          */
 356         writel(value, ioaddr + LPI_TIMER_CTRL);
 357 }
 358
 359 static void dwmac1000_ctrl_ane(struct mac_device_info *hw, bool restart)
 360 {
 361         void __iomem *ioaddr = hw->pcsr;
 362         /* auto negotiation enable and External Loopback enable */
 363         u32 value = GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_ELE;
 364
 365         if (restart)
 366                 value |= GMAC_AN_CTRL_RAN;
 367
 368         writel(value, ioaddr + GMAC_AN_CTRL);
 369 }
 370
 371 static void dwmac1000_get_adv(struct mac_device_info *hw, struct rgmii_adv *adv)
 372 {
 373         void __iomem *ioaddr = hw->pcsr;
 374         u32 value = readl(ioaddr + GMAC_ANE_ADV);
 375
 376         if (value & GMAC_ANE_FD)
 377                 adv->duplex = DUPLEX_FULL;
 378         if (value & GMAC_ANE_HD)
 379                 adv->duplex |= DUPLEX_HALF;
 380
 381         adv->pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
 382
 383         value = readl(ioaddr + GMAC_ANE_LPA);
 384
 385         if (value & GMAC_ANE_FD)
 386                 adv->lp_duplex = DUPLEX_FULL;
 387         if (value & GMAC_ANE_HD)
 388                 adv->lp_duplex = DUPLEX_HALF;
 389
 390         adv->lp_pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
 391 }
 392
 393 static const struct stmmac_ops dwmac1000_ops = {
 394         .core_init = dwmac1000_core_init,
 395         .rx_ipc = dwmac1000_rx_ipc_enable,
 396         .dump_regs = dwmac1000_dump_regs,
 397         .host_irq_status = dwmac1000_irq_status,
 398         .set_filter = dwmac1000_set_filter,
 399         .flow_ctrl = dwmac1000_flow_ctrl,
 400         .pmt = dwmac1000_pmt,
 401         .set_umac_addr = dwmac1000_set_umac_addr,
 402         .get_umac_addr = dwmac1000_get_umac_addr,
 403         .set_eee_mode = dwmac1000_set_eee_mode,
 404         .reset_eee_mode = dwmac1000_reset_eee_mode,
 405         .set_eee_timer = dwmac1000_set_eee_timer,
 406         .set_eee_pls = dwmac1000_set_eee_pls,
 407         .ctrl_ane = dwmac1000_ctrl_ane,
 408         .get_adv = dwmac1000_get_adv,
 409 };
 410
 411 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
 412                                         int perfect_uc_entries)
 413 {
 414         struct mac_device_info *mac;
 415         u32 hwid = readl(ioaddr + GMAC_VERSION);
 416
 417         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 418         if (!mac)
 419                 return NULL;
 420
 421         mac->pcsr = ioaddr;
 422         mac->multicast_filter_bins = mcbins;
 423         mac->unicast_filter_entries = perfect_uc_entries;
 424         mac->mcast_bits_log2 = 0;
 425
 426         if (mac->multicast_filter_bins)
 427                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 428
 429         mac->mac = &dwmac1000_ops;
 430         mac->dma = &dwmac1000_dma_ops;
 431
 432         mac->link.port = GMAC_CONTROL_PS;
 433         mac->link.duplex = GMAC_CONTROL_DM;
 434         mac->link.speed = GMAC_CONTROL_FES;
 435         mac->mii.addr = GMAC_MII_ADDR;
 436         mac->mii.data = GMAC_MII_DATA;
 437         mac->synopsys_uid = hwid;
 438
 439         return mac;
 440 }