drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_STMMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif
  50 #include <linux/net_tstamp.h>
  51 #include "stmmac_ptp.h"
  52 #include "stmmac.h"
  53
  54 #undef STMMAC_DEBUG
  55 /*#define STMMAC_DEBUG*/
  56 #ifdef STMMAC_DEBUG
  57 #define DBG(nlevel, klevel, fmt, args...) \
  58                 ((void)(netif_msg_##nlevel(priv) && \
  59                 printk(KERN_##klevel fmt, ## args)))
  60 #else
  61 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  62 #endif
  63
  64 #undef STMMAC_RX_DEBUG
  65 /*#define STMMAC_RX_DEBUG*/
  66 #ifdef STMMAC_RX_DEBUG
  67 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  68 #else
  69 #define RX_DBG(fmt, args...)  do { } while (0)
  70 #endif
  71
  72 #undef STMMAC_XMIT_DEBUG
  73 /*#define STMMAC_XMIT_DEBUG*/
  74 #ifdef STMMAC_XMIT_DEBUG
  75 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  76 #else
  77 #define TX_DBG(fmt, args...)  do { } while (0)
  78 #endif
  79
  80 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  81 #define JUMBO_LEN       9000
  82
  83 /* Module parameters */
  84 #define TX_TIMEO        5000
  85 static int watchdog = TX_TIMEO;
  86 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  87 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  88
  89 static int debug = -1;
  90 module_param(debug, int, S_IRUGO | S_IWUSR);
  91 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  92
  93 int phyaddr = -1;
  94 module_param(phyaddr, int, S_IRUGO);
  95 MODULE_PARM_DESC(phyaddr, "Physical device address");
  96
  97 #define DMA_TX_SIZE 256
  98 static int dma_txsize = DMA_TX_SIZE;
  99 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 100 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 101
 102 #define DMA_RX_SIZE 256
 103 static int dma_rxsize = DMA_RX_SIZE;
 104 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 106
 107 static int flow_ctrl = FLOW_OFF;
 108 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 109 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 110
 111 static int pause = PAUSE_TIME;
 112 module_param(pause, int, S_IRUGO | S_IWUSR);
 113 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 114
 115 #define TC_DEFAULT 64
 116 static int tc = TC_DEFAULT;
 117 module_param(tc, int, S_IRUGO | S_IWUSR);
 118 MODULE_PARM_DESC(tc, "DMA threshold control value");
 119
 120 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 121 static int buf_sz = DMA_BUFFER_SIZE;
 122 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 123 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 124
 125 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 126                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 127                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 128
 129 #define STMMAC_DEFAULT_LPI_TIMER        1000
 130 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 131 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 132 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 133 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
 134
 135 /* By default the driver will use the ring mode to manage tx and rx descriptors
 136  * but passing this value so user can force to use the chain instead of the ring
 137  */
 138 static unsigned int chain_mode;
 139 module_param(chain_mode, int, S_IRUGO);
 140 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 141
 142 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 143
 144 #ifdef CONFIG_STMMAC_DEBUG_FS
 145 static int stmmac_init_fs(struct net_device *dev);
 146 static void stmmac_exit_fs(void);
 147 #endif
 148
 149 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 150
 151 /**
 152  * stmmac_verify_args - verify the driver parameters.
 153  * Description: it verifies if some wrong parameter is passed to the driver.
 154  * Note that wrong parameters are replaced with the default values.
 155  */
 156 static void stmmac_verify_args(void)
 157 {
 158         if (unlikely(watchdog < 0))
 159                 watchdog = TX_TIMEO;
 160         if (unlikely(dma_rxsize < 0))
 161                 dma_rxsize = DMA_RX_SIZE;
 162         if (unlikely(dma_txsize < 0))
 163                 dma_txsize = DMA_TX_SIZE;
 164         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 165                 buf_sz = DMA_BUFFER_SIZE;
 166         if (unlikely(flow_ctrl > 1))
 167                 flow_ctrl = FLOW_AUTO;
 168         else if (likely(flow_ctrl < 0))
 169                 flow_ctrl = FLOW_OFF;
 170         if (unlikely((pause < 0) || (pause > 0xffff)))
 171                 pause = PAUSE_TIME;
 172         if (eee_timer < 0)
 173                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 174 }
 175
 176 /**
 177  * stmmac_clk_csr_set - dynamically set the MDC clock
 178  * @priv: driver private structure
 179  * Description: this is to dynamically set the MDC clock according to the csr
 180  * clock input.
 181  * Note:
 182  *      If a specific clk_csr value is passed from the platform
 183  *      this means that the CSR Clock Range selection cannot be
 184  *      changed at run-time and it is fixed (as reported in the driver
 185  *      documentation). Viceversa the driver will try to set the MDC
 186  *      clock dynamically according to the actual clock input.
 187  */
 188 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 189 {
 190         u32 clk_rate;
 191
 192         clk_rate = clk_get_rate(priv->stmmac_clk);
 193
 194         /* Platform provided default clk_csr would be assumed valid
 195          * for all other cases except for the below mentioned ones. */
 196         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 197                 if (clk_rate < CSR_F_35M)
 198                         priv->clk_csr = STMMAC_CSR_20_35M;
 199                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 200                         priv->clk_csr = STMMAC_CSR_35_60M;
 201                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 202                         priv->clk_csr = STMMAC_CSR_60_100M;
 203                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 204                         priv->clk_csr = STMMAC_CSR_100_150M;
 205                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 206                         priv->clk_csr = STMMAC_CSR_150_250M;
 207                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 208                         priv->clk_csr = STMMAC_CSR_250_300M;
 209         } /* For values higher than the IEEE 802.3 specified frequency
 210            * we can not estimate the proper divider as it is not known
 211            * the frequency of clk_csr_i. So we do not change the default
 212            * divider. */
 213 }
 214
 215 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 216 static void print_pkt(unsigned char *buf, int len)
 217 {
 218         int j;
 219         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 220         for (j = 0; j < len; j++) {
 221                 if ((j % 16) == 0)
 222                         pr_info("\n %03x:", j);
 223                 pr_info(" %02x", buf[j]);
 224         }
 225         pr_info("\n");
 226 }
 227 #endif
 228
 229 /* minimum number of free TX descriptors required to wake up TX process */
 230 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 231
 232 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 233 {
 234         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 235 }
 236
 237 /**
 238  * stmmac_hw_fix_mac_speed: callback for speed selection
 239  * @priv: driver private structure
 240  * Description: on some platforms (e.g. ST), some HW system configuraton
 241  * registers have to be set according to the link speed negotiated.
 242  */
 243 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 244 {
 245         struct phy_device *phydev = priv->phydev;
 246
 247         if (likely(priv->plat->fix_mac_speed))
 248                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
 249                                           phydev->speed);
 250 }
 251
 252 /**
 253  * stmmac_enable_eee_mode: Check and enter in LPI mode
 254  * @priv: driver private structure
 255  * Description: this function is to verify and enter in LPI mode for EEE.
 256  */
 257 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 258 {
 259         /* Check and enter in LPI mode */
 260         if ((priv->dirty_tx == priv->cur_tx) &&
 261             (priv->tx_path_in_lpi_mode == false))
 262                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 263 }
 264
 265 /**
 266  * stmmac_disable_eee_mode: disable/exit from EEE
 267  * @priv: driver private structure
 268  * Description: this function is to exit and disable EEE in case of
 269  * LPI state is true. This is called by the xmit.
 270  */
 271 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 272 {
 273         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 274         del_timer_sync(&priv->eee_ctrl_timer);
 275         priv->tx_path_in_lpi_mode = false;
 276 }
 277
 278 /**
 279  * stmmac_eee_ctrl_timer: EEE TX SW timer.
 280  * @arg : data hook
 281  * Description:
 282  *  if there is no data transfer and if we are not in LPI state,
 283  *  then MAC Transmitter can be moved to LPI state.
 284  */
 285 static void stmmac_eee_ctrl_timer(unsigned long arg)
 286 {
 287         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 288
 289         stmmac_enable_eee_mode(priv);
 290         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 291 }
 292
 293 /**
 294  * stmmac_eee_init: init EEE
 295  * @priv: driver private structure
 296  * Description:
 297  *  If the EEE support has been enabled while configuring the driver,
 298  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 299  *  phy can also manage EEE, so enable the LPI state and start the timer
 300  *  to verify if the tx path can enter in LPI state.
 301  */
 302 bool stmmac_eee_init(struct stmmac_priv *priv)
 303 {
 304         bool ret = false;
 305
 306         /* MAC core supports the EEE feature. */
 307         if (priv->dma_cap.eee) {
 308                 /* Check if the PHY supports EEE */
 309                 if (phy_init_eee(priv->phydev, 1))
 310                         goto out;
 311
 312                 priv->eee_active = 1;
 313                 init_timer(&priv->eee_ctrl_timer);
 314                 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 315                 priv->eee_ctrl_timer.data = (unsigned long)priv;
 316                 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
 317                 add_timer(&priv->eee_ctrl_timer);
 318
 319                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 320                                              STMMAC_DEFAULT_LIT_LS_TIMER,
 321                                              priv->tx_lpi_timer);
 322
 323                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 324
 325                 ret = true;
 326         }
 327 out:
 328         return ret;
 329 }
 330
 331 /**
 332  * stmmac_eee_adjust: adjust HW EEE according to the speed
 333  * @priv: driver private structure
 334  * Description:
 335  *      When the EEE has been already initialised we have to
 336  *      modify the PLS bit in the LPI ctrl & status reg according
 337  *      to the PHY link status. For this reason.
 338  */
 339 static void stmmac_eee_adjust(struct stmmac_priv *priv)
 340 {
 341         if (priv->eee_enabled)
 342                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 343 }
 344
 345 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
 346  * @priv: driver private structure
 347  * @entry : descriptor index to be used.
 348  * @skb : the socket buffer
 349  * Description :
 350  * This function will read timestamp from the descriptor & pass it to stack.
 351  * and also perform some sanity checks.
 352  */
 353 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 354                                    unsigned int entry,
 355                                    struct sk_buff *skb)
 356 {
 357         struct skb_shared_hwtstamps shhwtstamp;
 358         u64 ns;
 359         void *desc = NULL;
 360
 361         if (!priv->hwts_tx_en)
 362                 return;
 363
 364         /* if skb doesn't support hw tstamp */
 365         if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 366                 return;
 367
 368         if (priv->adv_ts)
 369                 desc = (priv->dma_etx + entry);
 370         else
 371                 desc = (priv->dma_tx + entry);
 372
 373         /* check tx tstamp status */
 374         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 375                 return;
 376
 377         /* get the valid tstamp */
 378         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 379
 380         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 381         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 382         /* pass tstamp to stack */
 383         skb_tstamp_tx(skb, &shhwtstamp);
 384
 385         return;
 386 }
 387
 388 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
 389  * @priv: driver private structure
 390  * @entry : descriptor index to be used.
 391  * @skb : the socket buffer
 392  * Description :
 393  * This function will read received packet's timestamp from the descriptor
 394  * and pass it to stack. It also perform some sanity checks.
 395  */
 396 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 397                                    unsigned int entry,
 398                                    struct sk_buff *skb)
 399 {
 400         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 401         u64 ns;
 402         void *desc = NULL;
 403
 404         if (!priv->hwts_rx_en)
 405                 return;
 406
 407         if (priv->adv_ts)
 408                 desc = (priv->dma_erx + entry);
 409         else
 410                 desc = (priv->dma_rx + entry);
 411
 412         /* if rx tstamp is not valid */
 413         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 414                 return;
 415
 416         /* get valid tstamp */
 417         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 418         shhwtstamp = skb_hwtstamps(skb);
 419         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 420         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 421 }
 422
 423 /**
 424  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 425  *  @dev: device pointer.
 426  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 427  *  a proprietary structure used to pass information to the driver.
 428  *  Description:
 429  *  This function configures the MAC to enable/disable both outgoing(TX)
 430  *  and incoming(RX) packets time stamping based on user input.
 431  *  Return Value:
 432  *  0 on success and an appropriate -ve integer on failure.
 433  */
 434 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 435 {
 436         struct stmmac_priv *priv = netdev_priv(dev);
 437         struct hwtstamp_config config;
 438         struct timespec now;
 439         u64 temp = 0;
 440         u32 ptp_v2 = 0;
 441         u32 tstamp_all = 0;
 442         u32 ptp_over_ipv4_udp = 0;
 443         u32 ptp_over_ipv6_udp = 0;
 444         u32 ptp_over_ethernet = 0;
 445         u32 snap_type_sel = 0;
 446         u32 ts_master_en = 0;
 447         u32 ts_event_en = 0;
 448         u32 value = 0;
 449
 450         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 451                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 452                 priv->hwts_tx_en = 0;
 453                 priv->hwts_rx_en = 0;
 454
 455                 return -EOPNOTSUPP;
 456         }
 457
 458         if (copy_from_user(&config, ifr->ifr_data,
 459                 sizeof(struct hwtstamp_config)))
 460                 return -EFAULT;
 461
 462         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 463                  __func__, config.flags, config.tx_type, config.rx_filter);
 464
 465         /* reserved for future extensions */
 466         if (config.flags)
 467                 return -EINVAL;
 468
 469         switch (config.tx_type) {
 470         case HWTSTAMP_TX_OFF:
 471                 priv->hwts_tx_en = 0;
 472                 break;
 473         case HWTSTAMP_TX_ON:
 474                 priv->hwts_tx_en = 1;
 475                 break;
 476         default:
 477                 return -ERANGE;
 478         }
 479
 480         if (priv->adv_ts) {
 481                 switch (config.rx_filter) {
 482                 /* time stamp no incoming packet at all */
 483                 case HWTSTAMP_FILTER_NONE:
 484                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 485                         break;
 486
 487                 /* PTP v1, UDP, any kind of event packet */
 488                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 489                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 490                         /* take time stamp for all event messages */
 491                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 492
 493                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 494                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 495                         break;
 496
 497                 /* PTP v1, UDP, Sync packet */
 498                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 499                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 500                         /* take time stamp for SYNC messages only */
 501                         ts_event_en = PTP_TCR_TSEVNTENA;
 502
 503                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 504                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 505                         break;
 506
 507                 /* PTP v1, UDP, Delay_req packet */
 508                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 509                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 510                         /* take time stamp for Delay_Req messages only */
 511                         ts_master_en = PTP_TCR_TSMSTRENA;
 512                         ts_event_en = PTP_TCR_TSEVNTENA;
 513
 514                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 515                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 516                         break;
 517
 518                 /* PTP v2, UDP, any kind of event packet */
 519                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 520                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 521                         ptp_v2 = PTP_TCR_TSVER2ENA;
 522                         /* take time stamp for all event messages */
 523                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 524
 525                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 526                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 527                         break;
 528
 529                 /* PTP v2, UDP, Sync packet */
 530                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 531                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 532                         ptp_v2 = PTP_TCR_TSVER2ENA;
 533                         /* take time stamp for SYNC messages only */
 534                         ts_event_en = PTP_TCR_TSEVNTENA;
 535
 536                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 537                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 538                         break;
 539
 540                 /* PTP v2, UDP, Delay_req packet */
 541                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 542                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 543                         ptp_v2 = PTP_TCR_TSVER2ENA;
 544                         /* take time stamp for Delay_Req messages only */
 545                         ts_master_en = PTP_TCR_TSMSTRENA;
 546                         ts_event_en = PTP_TCR_TSEVNTENA;
 547
 548                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 549                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 550                         break;
 551
 552                 /* PTP v2/802.AS1, any layer, any kind of event packet */
 553                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 554                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 555                         ptp_v2 = PTP_TCR_TSVER2ENA;
 556                         /* take time stamp for all event messages */
 557                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 558
 559                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 560                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 561                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 562                         break;
 563
 564                 /* PTP v2/802.AS1, any layer, Sync packet */
 565                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 566                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 567                         ptp_v2 = PTP_TCR_TSVER2ENA;
 568                         /* take time stamp for SYNC messages only */
 569                         ts_event_en = PTP_TCR_TSEVNTENA;
 570
 571                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 572                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 573                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 574                         break;
 575
 576                 /* PTP v2/802.AS1, any layer, Delay_req packet */
 577                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 578                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 579                         ptp_v2 = PTP_TCR_TSVER2ENA;
 580                         /* take time stamp for Delay_Req messages only */
 581                         ts_master_en = PTP_TCR_TSMSTRENA;
 582                         ts_event_en = PTP_TCR_TSEVNTENA;
 583
 584                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 585                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 586                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 587                         break;
 588
 589                 /* time stamp any incoming packet */
 590                 case HWTSTAMP_FILTER_ALL:
 591                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 592                         tstamp_all = PTP_TCR_TSENALL;
 593                         break;
 594
 595                 default:
 596                         return -ERANGE;
 597                 }
 598         } else {
 599                 switch (config.rx_filter) {
 600                 case HWTSTAMP_FILTER_NONE:
 601                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 602                         break;
 603                 default:
 604                         /* PTP v1, UDP, any kind of event packet */
 605                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 606                         break;
 607                 }
 608         }
 609         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 610
 611         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 612                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 613         else {
 614                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 615                         tstamp_all | ptp_v2 | ptp_over_ethernet |
 616                         ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 617                         ts_master_en | snap_type_sel);
 618
 619                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 620
 621                 /* program Sub Second Increment reg */
 622                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 623
 624                 /* calculate default added value:
 625                  * formula is :
 626                  * addend = (2^32)/freq_div_ratio;
 627                  * where, freq_div_ratio = STMMAC_SYSCLOCK/50MHz
 628                  * hence, addend = ((2^32) * 50MHz)/STMMAC_SYSCLOCK;
 629                  * NOTE: STMMAC_SYSCLOCK should be >= 50MHz to
 630                  *       achive 20ns accuracy.
 631                  *
 632                  * 2^x * y == (y << x), hence
 633                  * 2^32 * 50000000 ==> (50000000 << 32)
 634                  */
 635                 temp = (u64)(50000000ULL << 32);
 636                 priv->default_addend = div_u64(temp, STMMAC_SYSCLOCK);
 637                 priv->hw->ptp->config_addend(priv->ioaddr,
 638                                              priv->default_addend);
 639
 640                 /* initialize system time */
 641                 getnstimeofday(&now);
 642                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 643                                             now.tv_nsec);
 644         }
 645
 646         return copy_to_user(ifr->ifr_data, &config,
 647                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 648 }
 649
 650 /**
 651  * stmmac_init_ptp: init PTP
 652  * @priv: driver private structure
 653  * Description: this is to verify if the HW supports the PTPv1 or v2.
 654  * This is done by looking at the HW cap. register.
 655  * Also it registers the ptp driver.
 656  */
 657 static int stmmac_init_ptp(struct stmmac_priv *priv)
 658 {
 659         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 660                 return -EOPNOTSUPP;
 661
 662         if (netif_msg_hw(priv)) {
 663                 if (priv->dma_cap.time_stamp) {
 664                         pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 665                         priv->adv_ts = 0;
 666                 }
 667                 if (priv->dma_cap.atime_stamp && priv->extend_desc) {
 668                         pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 669                         priv->adv_ts = 1;
 670                 }
 671         }
 672
 673         priv->hw->ptp = &stmmac_ptp;
 674         priv->hwts_tx_en = 0;
 675         priv->hwts_rx_en = 0;
 676
 677         return stmmac_ptp_register(priv);
 678 }
 679
 680 static void stmmac_release_ptp(struct stmmac_priv *priv)
 681 {
 682         stmmac_ptp_unregister(priv);
 683 }
 684
 685 /**
 686  * stmmac_adjust_link
 687  * @dev: net device structure
 688  * Description: it adjusts the link parameters.
 689  */
 690 static void stmmac_adjust_link(struct net_device *dev)
 691 {
 692         struct stmmac_priv *priv = netdev_priv(dev);
 693         struct phy_device *phydev = priv->phydev;
 694         unsigned long flags;
 695         int new_state = 0;
 696         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 697
 698         if (phydev == NULL)
 699                 return;
 700
 701         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 702             phydev->addr, phydev->link);
 703
 704         spin_lock_irqsave(&priv->lock, flags);
 705
 706         if (phydev->link) {
 707                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 708
 709                 /* Now we make sure that we can be in full duplex mode.
 710                  * If not, we operate in half-duplex mode. */
 711                 if (phydev->duplex != priv->oldduplex) {
 712                         new_state = 1;
 713                         if (!(phydev->duplex))
 714                                 ctrl &= ~priv->hw->link.duplex;
 715                         else
 716                                 ctrl |= priv->hw->link.duplex;
 717                         priv->oldduplex = phydev->duplex;
 718                 }
 719                 /* Flow Control operation */
 720                 if (phydev->pause)
 721                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 722                                                  fc, pause_time);
 723
 724                 if (phydev->speed != priv->speed) {
 725                         new_state = 1;
 726                         switch (phydev->speed) {
 727                         case 1000:
 728                                 if (likely(priv->plat->has_gmac))
 729                                         ctrl &= ~priv->hw->link.port;
 730                                         stmmac_hw_fix_mac_speed(priv);
 731                                 break;
 732                         case 100:
 733                         case 10:
 734                                 if (priv->plat->has_gmac) {
 735                                         ctrl |= priv->hw->link.port;
 736                                         if (phydev->speed == SPEED_100) {
 737                                                 ctrl |= priv->hw->link.speed;
 738                                         } else {
 739                                                 ctrl &= ~(priv->hw->link.speed);
 740                                         }
 741                                 } else {
 742                                         ctrl &= ~priv->hw->link.port;
 743                                 }
 744                                 stmmac_hw_fix_mac_speed(priv);
 745                                 break;
 746                         default:
 747                                 if (netif_msg_link(priv))
 748                                         pr_warning("%s: Speed (%d) is not 10"
 749                                        " or 100!\n", dev->name, phydev->speed);
 750                                 break;
 751                         }
 752
 753                         priv->speed = phydev->speed;
 754                 }
 755
 756                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 757
 758                 if (!priv->oldlink) {
 759                         new_state = 1;
 760                         priv->oldlink = 1;
 761                 }
 762         } else if (priv->oldlink) {
 763                 new_state = 1;
 764                 priv->oldlink = 0;
 765                 priv->speed = 0;
 766                 priv->oldduplex = -1;
 767         }
 768
 769         if (new_state && netif_msg_link(priv))
 770                 phy_print_status(phydev);
 771
 772         stmmac_eee_adjust(priv);
 773
 774         spin_unlock_irqrestore(&priv->lock, flags);
 775
 776         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 777 }
 778
 779 /**
 780  * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
 781  * @priv: driver private structure
 782  * Description: this is to verify if the HW supports the PCS.
 783  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 784  * configured for the TBI, RTBI, or SGMII PHY interface.
 785  */
 786 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 787 {
 788         int interface = priv->plat->interface;
 789
 790         if (priv->dma_cap.pcs) {
 791                 if ((interface & PHY_INTERFACE_MODE_RGMII) ||
 792                     (interface & PHY_INTERFACE_MODE_RGMII_ID) ||
 793                     (interface & PHY_INTERFACE_MODE_RGMII_RXID) ||
 794                     (interface & PHY_INTERFACE_MODE_RGMII_TXID)) {
 795                         pr_debug("STMMAC: PCS RGMII support enable\n");
 796                         priv->pcs = STMMAC_PCS_RGMII;
 797                 } else if (interface & PHY_INTERFACE_MODE_SGMII) {
 798                         pr_debug("STMMAC: PCS SGMII support enable\n");
 799                         priv->pcs = STMMAC_PCS_SGMII;
 800                 }
 801         }
 802 }
 803
 804 /**
 805  * stmmac_init_phy - PHY initialization
 806  * @dev: net device structure
 807  * Description: it initializes the driver's PHY state, and attaches the PHY
 808  * to the mac driver.
 809  *  Return value:
 810  *  0 on success
 811  */
 812 static int stmmac_init_phy(struct net_device *dev)
 813 {
 814         struct stmmac_priv *priv = netdev_priv(dev);
 815         struct phy_device *phydev;
 816         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 817         char bus_id[MII_BUS_ID_SIZE];
 818         int interface = priv->plat->interface;
 819         priv->oldlink = 0;
 820         priv->speed = 0;
 821         priv->oldduplex = -1;
 822
 823         if (priv->plat->phy_bus_name)
 824                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 825                                 priv->plat->phy_bus_name, priv->plat->bus_id);
 826         else
 827                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 828                                 priv->plat->bus_id);
 829
 830         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 831                  priv->plat->phy_addr);
 832         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 833
 834         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 835
 836         if (IS_ERR(phydev)) {
 837                 pr_err("%s: Could not attach to PHY\n", dev->name);
 838                 return PTR_ERR(phydev);
 839         }
 840
 841         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 842         if ((interface == PHY_INTERFACE_MODE_MII) ||
 843             (interface == PHY_INTERFACE_MODE_RMII))
 844                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 845                                          SUPPORTED_1000baseT_Full);
 846
 847         /*
 848          * Broken HW is sometimes missing the pull-up resistor on the
 849          * MDIO line, which results in reads to non-existent devices returning
 850          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 851          * device as well.
 852          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 853          */
 854         if (phydev->phy_id == 0) {
 855                 phy_disconnect(phydev);
 856                 return -ENODEV;
 857         }
 858         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 859                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 860
 861         priv->phydev = phydev;
 862
 863         return 0;
 864 }
 865
 866 /**
 867  * stmmac_display_ring: display ring
 868  * @head: pointer to the head of the ring passed.
 869  * @size: size of the ring.
 870  * @extend_desc: to verify if extended descriptors are used.
 871  * Description: display the control/status and buffer descriptors.
 872  */
 873 static void stmmac_display_ring(void *head, int size, int extend_desc)
 874 {
 875         int i;
 876         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
 877         struct dma_desc *p = (struct dma_desc *) head;
 878
 879         for (i = 0; i < size; i++) {
 880                 u64 x;
 881                 if (extend_desc) {
 882                         x = *(u64 *) ep;
 883                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 884                                 i, (unsigned int) virt_to_phys(ep),
 885                                 (unsigned int) x, (unsigned int) (x >> 32),
 886                                 ep->basic.des2, ep->basic.des3);
 887                         ep++;
 888                 } else {
 889                         x = *(u64 *) p;
 890                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 891                                 i, (unsigned int) virt_to_phys(p),
 892                                 (unsigned int) x, (unsigned int) (x >> 32),
 893                                 p->des2, p->des3);
 894                         p++;
 895                 }
 896                 pr_info("\n");
 897         }
 898 }
 899
 900 static void stmmac_display_rings(struct stmmac_priv *priv)
 901 {
 902         unsigned int txsize = priv->dma_tx_size;
 903         unsigned int rxsize = priv->dma_rx_size;
 904
 905         if (priv->extend_desc) {
 906                 pr_info("Extended RX descriptor ring:\n");
 907                 stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
 908                 pr_info("Extended TX descriptor ring:\n");
 909                 stmmac_display_ring((void *) priv->dma_etx, txsize, 1);
 910         } else {
 911                 pr_info("RX descriptor ring:\n");
 912                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 913                 pr_info("TX descriptor ring:\n");
 914                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 915         }
 916 }
 917
 918 static int stmmac_set_bfsize(int mtu, int bufsize)
 919 {
 920         int ret = bufsize;
 921
 922         if (mtu >= BUF_SIZE_4KiB)
 923                 ret = BUF_SIZE_8KiB;
 924         else if (mtu >= BUF_SIZE_2KiB)
 925                 ret = BUF_SIZE_4KiB;
 926         else if (mtu >= DMA_BUFFER_SIZE)
 927                 ret = BUF_SIZE_2KiB;
 928         else
 929                 ret = DMA_BUFFER_SIZE;
 930
 931         return ret;
 932 }
 933
 934 /**
 935  * stmmac_clear_descriptors: clear descriptors
 936  * @priv: driver private structure
 937  * Description: this function is called to clear the tx and rx descriptors
 938  * in case of both basic and extended descriptors are used.
 939  */
 940 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 941 {
 942         int i;
 943         unsigned int txsize = priv->dma_tx_size;
 944         unsigned int rxsize = priv->dma_rx_size;
 945
 946         /* Clear the Rx/Tx descriptors */
 947         for (i = 0; i < rxsize; i++)
 948                 if (priv->extend_desc)
 949                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 950                                                      priv->use_riwt, priv->mode,
 951                                                      (i == rxsize - 1));
 952                 else
 953                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 954                                                      priv->use_riwt, priv->mode,
 955                                                      (i == rxsize - 1));
 956         for (i = 0; i < txsize; i++)
 957                 if (priv->extend_desc)
 958                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 959                                                      priv->mode,
 960                                                      (i == txsize - 1));
 961                 else
 962                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 963                                                      priv->mode,
 964                                                      (i == txsize - 1));
 965 }
 966
 967 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 968                                   int i)
 969 {
 970         struct sk_buff *skb;
 971
 972         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 973                                  GFP_KERNEL);
 974         if (unlikely(skb == NULL)) {
 975                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 976                 return 1;
 977         }
 978         skb_reserve(skb, NET_IP_ALIGN);
 979         priv->rx_skbuff[i] = skb;
 980         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 981                                                 priv->dma_buf_sz,
 982                                                 DMA_FROM_DEVICE);
 983
 984         p->des2 = priv->rx_skbuff_dma[i];
 985
 986         if ((priv->mode == STMMAC_RING_MODE) &&
 987             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 988                 priv->hw->ring->init_desc3(p);
 989
 990         return 0;
 991 }
 992
 993 /**
 994  * init_dma_desc_rings - init the RX/TX descriptor rings
 995  * @dev: net device structure
 996  * Description:  this function initializes the DMA RX/TX descriptors
 997  * and allocates the socket buffers. It suppors the chained and ring
 998  * modes.
 999  */
1000 static void init_dma_desc_rings(struct net_device *dev)
1001 {
1002         int i;
1003         struct stmmac_priv *priv = netdev_priv(dev);
1004         unsigned int txsize = priv->dma_tx_size;
1005         unsigned int rxsize = priv->dma_rx_size;
1006         unsigned int bfsize = 0;
1007
1008         /* Set the max buffer size according to the DESC mode
1009          * and the MTU. Note that RING mode allows 16KiB bsize. */
1010         if (priv->mode == STMMAC_RING_MODE)
1011                 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
1012
1013         if (bfsize < BUF_SIZE_16KiB)
1014                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1015
1016         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
1017             txsize, rxsize, bfsize);
1018
1019         if (priv->extend_desc) {
1020                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1021                                                    sizeof(struct
1022                                                           dma_extended_desc),
1023                                                    &priv->dma_rx_phy,
1024                                                    GFP_KERNEL);
1025                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1026                                                    sizeof(struct
1027                                                           dma_extended_desc),
1028                                                    &priv->dma_tx_phy,
1029                                                    GFP_KERNEL);
1030                 if ((!priv->dma_erx) || (!priv->dma_etx))
1031                         return;
1032         } else {
1033                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1034                                                   sizeof(struct dma_desc),
1035                                                   &priv->dma_rx_phy,
1036                                                   GFP_KERNEL);
1037                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1038                                                   sizeof(struct dma_desc),
1039                                                   &priv->dma_tx_phy,
1040                                                   GFP_KERNEL);
1041                 if ((!priv->dma_rx) || (!priv->dma_tx))
1042                         return;
1043         }
1044
1045         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1046                                             GFP_KERNEL);
1047         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1048                                         GFP_KERNEL);
1049         priv->tx_skbuff_dma = kmalloc_array(txsize, sizeof(dma_addr_t),
1050                                         GFP_KERNEL);
1051         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1052                                         GFP_KERNEL);
1053         if (netif_msg_drv(priv))
1054                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1055                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1056
1057         /* RX INITIALIZATION */
1058         DBG(probe, INFO, "stmmac: SKB addresses:\nskb\t\tskb data\tdma data\n");
1059         for (i = 0; i < rxsize; i++) {
1060                 struct dma_desc *p;
1061                 if (priv->extend_desc)
1062                         p = &((priv->dma_erx + i)->basic);
1063                 else
1064                         p = priv->dma_rx + i;
1065
1066                 if (stmmac_init_rx_buffers(priv, p, i))
1067                         break;
1068
1069                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1070                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
1071         }
1072         priv->cur_rx = 0;
1073         priv->dirty_rx = (unsigned int)(i - rxsize);
1074         priv->dma_buf_sz = bfsize;
1075         buf_sz = bfsize;
1076
1077         /* Setup the chained descriptor addresses */
1078         if (priv->mode == STMMAC_CHAIN_MODE) {
1079                 if (priv->extend_desc) {
1080                         priv->hw->chain->init(priv->dma_erx, priv->dma_rx_phy,
1081                                               rxsize, 1);
1082                         priv->hw->chain->init(priv->dma_etx, priv->dma_tx_phy,
1083                                               txsize, 1);
1084                 } else {
1085                         priv->hw->chain->init(priv->dma_rx, priv->dma_rx_phy,
1086                                               rxsize, 0);
1087                         priv->hw->chain->init(priv->dma_tx, priv->dma_tx_phy,
1088                                               txsize, 0);
1089                 }
1090         }
1091
1092         /* TX INITIALIZATION */
1093         for (i = 0; i < txsize; i++) {
1094                 struct dma_desc *p;
1095                 if (priv->extend_desc)
1096                         p = &((priv->dma_etx + i)->basic);
1097                 else
1098                         p = priv->dma_tx + i;
1099                 p->des2 = 0;
1100                 priv->tx_skbuff_dma[i] = 0;
1101                 priv->tx_skbuff[i] = NULL;
1102         }
1103
1104         priv->dirty_tx = 0;
1105         priv->cur_tx = 0;
1106
1107         stmmac_clear_descriptors(priv);
1108
1109         if (netif_msg_hw(priv))
1110                 stmmac_display_rings(priv);
1111 }
1112
1113 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1114 {
1115         int i;
1116
1117         for (i = 0; i < priv->dma_rx_size; i++) {
1118                 if (priv->rx_skbuff[i]) {
1119                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1120                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1121                         dev_kfree_skb_any(priv->rx_skbuff[i]);
1122                 }
1123                 priv->rx_skbuff[i] = NULL;
1124         }
1125 }
1126
1127 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1128 {
1129         int i;
1130
1131         for (i = 0; i < priv->dma_tx_size; i++) {
1132                 if (priv->tx_skbuff[i] != NULL) {
1133                         struct dma_desc *p;
1134                         if (priv->extend_desc)
1135                                 p = &((priv->dma_etx + i)->basic);
1136                         else
1137                                 p = priv->dma_tx + i;
1138
1139                         if (priv->tx_skbuff_dma[i])
1140                                 dma_unmap_single(priv->device,
1141                                                  priv->tx_skbuff_dma[i],
1142                                                  priv->hw->desc->get_tx_len(p),
1143                                                  DMA_TO_DEVICE);
1144                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1145                         priv->tx_skbuff[i] = NULL;
1146                         priv->tx_skbuff_dma[i] = 0;
1147                 }
1148         }
1149 }
1150
1151 static void free_dma_desc_resources(struct stmmac_priv *priv)
1152 {
1153         /* Release the DMA TX/RX socket buffers */
1154         dma_free_rx_skbufs(priv);
1155         dma_free_tx_skbufs(priv);
1156
1157         /* Free the region of consistent memory previously allocated for
1158          * the DMA */
1159         if (!priv->extend_desc) {
1160                 dma_free_coherent(priv->device,
1161                                   priv->dma_tx_size * sizeof(struct dma_desc),
1162                                   priv->dma_tx, priv->dma_tx_phy);
1163                 dma_free_coherent(priv->device,
1164                                   priv->dma_rx_size * sizeof(struct dma_desc),
1165                                   priv->dma_rx, priv->dma_rx_phy);
1166         } else {
1167                 dma_free_coherent(priv->device, priv->dma_tx_size *
1168                                   sizeof(struct dma_extended_desc),
1169                                   priv->dma_etx, priv->dma_tx_phy);
1170                 dma_free_coherent(priv->device, priv->dma_rx_size *
1171                                   sizeof(struct dma_extended_desc),
1172                                   priv->dma_erx, priv->dma_rx_phy);
1173         }
1174         kfree(priv->rx_skbuff_dma);
1175         kfree(priv->rx_skbuff);
1176         kfree(priv->tx_skbuff_dma);
1177         kfree(priv->tx_skbuff);
1178 }
1179
1180 /**
1181  *  stmmac_dma_operation_mode - HW DMA operation mode
1182  *  @priv: driver private structure
1183  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1184  *  or Store-And-Forward capability.
1185  */
1186 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1187 {
1188         if (likely(priv->plat->force_sf_dma_mode ||
1189                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
1190                 /*
1191                  * In case of GMAC, SF mode can be enabled
1192                  * to perform the TX COE in HW. This depends on:
1193                  * 1) TX COE if actually supported
1194                  * 2) There is no bugged Jumbo frame support
1195                  *    that needs to not insert csum in the TDES.
1196                  */
1197                 priv->hw->dma->dma_mode(priv->ioaddr,
1198                                         SF_DMA_MODE, SF_DMA_MODE);
1199                 tc = SF_DMA_MODE;
1200         } else
1201                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1202 }
1203
1204 /**
1205  * stmmac_tx_clean:
1206  * @priv: driver private structure
1207  * Description: it reclaims resources after transmission completes.
1208  */
1209 static void stmmac_tx_clean(struct stmmac_priv *priv)
1210 {
1211         unsigned int txsize = priv->dma_tx_size;
1212
1213         spin_lock(&priv->tx_lock);
1214
1215         priv->xstats.tx_clean++;
1216
1217         while (priv->dirty_tx != priv->cur_tx) {
1218                 int last;
1219                 unsigned int entry = priv->dirty_tx % txsize;
1220                 struct sk_buff *skb = priv->tx_skbuff[entry];
1221                 struct dma_desc *p;
1222
1223                 if (priv->extend_desc)
1224                         p = (struct dma_desc *) (priv->dma_etx + entry);
1225                 else
1226                         p = priv->dma_tx + entry;
1227
1228                 /* Check if the descriptor is owned by the DMA. */
1229                 if (priv->hw->desc->get_tx_owner(p))
1230                         break;
1231
1232                 /* Verify tx error by looking at the last segment. */
1233                 last = priv->hw->desc->get_tx_ls(p);
1234                 if (likely(last)) {
1235                         int tx_error =
1236                                 priv->hw->desc->tx_status(&priv->dev->stats,
1237                                                           &priv->xstats, p,
1238                                                           priv->ioaddr);
1239                         if (likely(tx_error == 0)) {
1240                                 priv->dev->stats.tx_packets++;
1241                                 priv->xstats.tx_pkt_n++;
1242                         } else
1243                                 priv->dev->stats.tx_errors++;
1244
1245                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1246                 }
1247                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
1248                         priv->cur_tx, priv->dirty_tx);
1249
1250                 if (likely(priv->tx_skbuff_dma[entry])) {
1251                         dma_unmap_single(priv->device,
1252                                          priv->tx_skbuff_dma[entry],
1253                                          priv->hw->desc->get_tx_len(p),
1254                                          DMA_TO_DEVICE);
1255                         priv->tx_skbuff_dma[entry] = 0;
1256                 }
1257                 priv->hw->ring->clean_desc3(priv, p);
1258
1259                 if (likely(skb != NULL)) {
1260                         dev_kfree_skb(skb);
1261                         priv->tx_skbuff[entry] = NULL;
1262                 }
1263
1264                 priv->hw->desc->release_tx_desc(p, priv->mode);
1265
1266                 priv->dirty_tx++;
1267         }
1268         if (unlikely(netif_queue_stopped(priv->dev) &&
1269                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1270                 netif_tx_lock(priv->dev);
1271                 if (netif_queue_stopped(priv->dev) &&
1272                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1273                         TX_DBG("%s: restart transmit\n", __func__);
1274                         netif_wake_queue(priv->dev);
1275                 }
1276                 netif_tx_unlock(priv->dev);
1277         }
1278
1279         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1280                 stmmac_enable_eee_mode(priv);
1281                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
1282         }
1283         spin_unlock(&priv->tx_lock);
1284 }
1285
1286 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1287 {
1288         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1289 }
1290
1291 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1292 {
1293         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1294 }
1295
1296
1297 /**
1298  * stmmac_tx_err: irq tx error mng function
1299  * @priv: driver private structure
1300  * Description: it cleans the descriptors and restarts the transmission
1301  * in case of errors.
1302  */
1303 static void stmmac_tx_err(struct stmmac_priv *priv)
1304 {
1305         int i;
1306         int txsize = priv->dma_tx_size;
1307         netif_stop_queue(priv->dev);
1308
1309         priv->hw->dma->stop_tx(priv->ioaddr);
1310         dma_free_tx_skbufs(priv);
1311         for (i = 0; i < txsize; i++)
1312                 if (priv->extend_desc)
1313                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1314                                                      priv->mode,
1315                                                      (i == txsize - 1));
1316                 else
1317                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1318                                                      priv->mode,
1319                                                      (i == txsize - 1));
1320         priv->dirty_tx = 0;
1321         priv->cur_tx = 0;
1322         priv->hw->dma->start_tx(priv->ioaddr);
1323
1324         priv->dev->stats.tx_errors++;
1325         netif_wake_queue(priv->dev);
1326 }
1327
1328 /**
1329  * stmmac_dma_interrupt: DMA ISR
1330  * @priv: driver private structure
1331  * Description: this is the DMA ISR. It is called by the main ISR.
1332  * It calls the dwmac dma routine to understand which type of interrupt
1333  * happened. In case of there is a Normal interrupt and either TX or RX
1334  * interrupt happened so the NAPI is scheduled.
1335  */
1336 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1337 {
1338         int status;
1339
1340         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1341         if (likely((status & handle_rx)) || (status & handle_tx)) {
1342                 if (likely(napi_schedule_prep(&priv->napi))) {
1343                         stmmac_disable_dma_irq(priv);
1344                         __napi_schedule(&priv->napi);
1345                 }
1346         }
1347         if (unlikely(status & tx_hard_error_bump_tc)) {
1348                 /* Try to bump up the dma threshold on this failure */
1349                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1350                         tc += 64;
1351                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1352                         priv->xstats.threshold = tc;
1353                 }
1354         } else if (unlikely(status == tx_hard_error))
1355                 stmmac_tx_err(priv);
1356 }
1357
1358 /**
1359  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1360  * @priv: driver private structure
1361  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1362  */
1363 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1364 {
1365         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1366                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1367
1368         dwmac_mmc_intr_all_mask(priv->ioaddr);
1369
1370         if (priv->dma_cap.rmon) {
1371                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1372                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1373         } else
1374                 pr_info(" No MAC Management Counters available\n");
1375 }
1376
1377 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1378 {
1379         u32 hwid = priv->hw->synopsys_uid;
1380
1381         /* Only check valid Synopsys Id because old MAC chips
1382          * have no HW registers where get the ID */
1383         if (likely(hwid)) {
1384                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1385                 u32 synid = (hwid & 0x000000ff);
1386
1387                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1388                         uid, synid);
1389
1390                 return synid;
1391         }
1392         return 0;
1393 }
1394
1395 /**
1396  * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1397  * @priv: driver private structure
1398  * Description: select the Enhanced/Alternate or Normal descriptors.
1399  * In case of Enhanced/Alternate, it looks at the extended descriptors are
1400  * supported by the HW cap. register.
1401  */
1402 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1403 {
1404         if (priv->plat->enh_desc) {
1405                 pr_info(" Enhanced/Alternate descriptors\n");
1406
1407                 /* GMAC older than 3.50 has no extended descriptors */
1408                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1409                         pr_info("\tEnabled extended descriptors\n");
1410                         priv->extend_desc = 1;
1411                 } else
1412                         pr_warn("Extended descriptors not supported\n");
1413
1414                 priv->hw->desc = &enh_desc_ops;
1415         } else {
1416                 pr_info(" Normal descriptors\n");
1417                 priv->hw->desc = &ndesc_ops;
1418         }
1419 }
1420
1421 /**
1422  * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1423  * @priv: driver private structure
1424  * Description:
1425  *  new GMAC chip generations have a new register to indicate the
1426  *  presence of the optional feature/functions.
1427  *  This can be also used to override the value passed through the
1428  *  platform and necessary for old MAC10/100 and GMAC chips.
1429  */
1430 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1431 {
1432         u32 hw_cap = 0;
1433
1434         if (priv->hw->dma->get_hw_feature) {
1435                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1436
1437                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1438                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1439                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1440                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1441                 priv->dma_cap.multi_addr =
1442                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
1443                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1444                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1445                 priv->dma_cap.pmt_remote_wake_up =
1446                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1447                 priv->dma_cap.pmt_magic_frame =
1448                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1449                 /* MMC */
1450                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1451                 /* IEEE 1588-2002*/
1452                 priv->dma_cap.time_stamp =
1453                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1454                 /* IEEE 1588-2008*/
1455                 priv->dma_cap.atime_stamp =
1456                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1457                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1458                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1459                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1460                 /* TX and RX csum */
1461                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1462                 priv->dma_cap.rx_coe_type1 =
1463                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1464                 priv->dma_cap.rx_coe_type2 =
1465                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1466                 priv->dma_cap.rxfifo_over_2048 =
1467                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1468                 /* TX and RX number of channels */
1469                 priv->dma_cap.number_rx_channel =
1470                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1471                 priv->dma_cap.number_tx_channel =
1472                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1473                 /* Alternate (enhanced) DESC mode*/
1474                 priv->dma_cap.enh_desc =
1475                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1476         }
1477
1478         return hw_cap;
1479 }
1480
1481 /**
1482  * stmmac_check_ether_addr: check if the MAC addr is valid
1483  * @priv: driver private structure
1484  * Description:
1485  * it is to verify if the MAC address is valid, in case of failures it
1486  * generates a random MAC address
1487  */
1488 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1489 {
1490         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1491                 priv->hw->mac->get_umac_addr((void __iomem *)
1492                                              priv->dev->base_addr,
1493                                              priv->dev->dev_addr, 0);
1494                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
1495                         eth_hw_addr_random(priv->dev);
1496         }
1497         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
1498                                                    priv->dev->dev_addr);
1499 }
1500
1501 /**
1502  * stmmac_init_dma_engine: DMA init.
1503  * @priv: driver private structure
1504  * Description:
1505  * It inits the DMA invoking the specific MAC/GMAC callback.
1506  * Some DMA parameters can be passed from the platform;
1507  * in case of these are not passed a default is kept for the MAC or GMAC.
1508  */
1509 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1510 {
1511         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1512         int mixed_burst = 0;
1513         int atds = 0;
1514
1515         if (priv->plat->dma_cfg) {
1516                 pbl = priv->plat->dma_cfg->pbl;
1517                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1518                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1519                 burst_len = priv->plat->dma_cfg->burst_len;
1520         }
1521
1522         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1523                 atds = 1;
1524
1525         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1526                                    burst_len, priv->dma_tx_phy,
1527                                    priv->dma_rx_phy, atds);
1528 }
1529
1530 /**
1531  * stmmac_tx_timer: mitigation sw timer for tx.
1532  * @data: data pointer
1533  * Description:
1534  * This is the timer handler to directly invoke the stmmac_tx_clean.
1535  */
1536 static void stmmac_tx_timer(unsigned long data)
1537 {
1538         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1539
1540         stmmac_tx_clean(priv);
1541 }
1542
1543 /**
1544  * stmmac_init_tx_coalesce: init tx mitigation options.
1545  * @priv: driver private structure
1546  * Description:
1547  * This inits the transmit coalesce parameters: i.e. timer rate,
1548  * timer handler and default threshold used for enabling the
1549  * interrupt on completion bit.
1550  */
1551 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1552 {
1553         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1554         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1555         init_timer(&priv->txtimer);
1556         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1557         priv->txtimer.data = (unsigned long)priv;
1558         priv->txtimer.function = stmmac_tx_timer;
1559         add_timer(&priv->txtimer);
1560 }
1561
1562 /**
1563  *  stmmac_open - open entry point of the driver
1564  *  @dev : pointer to the device structure.
1565  *  Description:
1566  *  This function is the open entry point of the driver.
1567  *  Return value:
1568  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1569  *  file on failure.
1570  */
1571 static int stmmac_open(struct net_device *dev)
1572 {
1573         struct stmmac_priv *priv = netdev_priv(dev);
1574         int ret;
1575
1576         clk_prepare_enable(priv->stmmac_clk);
1577
1578         stmmac_check_ether_addr(priv);
1579
1580         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1581             priv->pcs != STMMAC_PCS_RTBI) {
1582                 ret = stmmac_init_phy(dev);
1583                 if (ret) {
1584                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1585                                __func__, ret);
1586                         goto open_error;
1587                 }
1588         }
1589
1590         /* Create and initialize the TX/RX descriptors chains. */
1591         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1592         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1593         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1594         init_dma_desc_rings(dev);
1595
1596         /* DMA initialization and SW reset */
1597         ret = stmmac_init_dma_engine(priv);
1598         if (ret < 0) {
1599                 pr_err("%s: DMA initialization failed\n", __func__);
1600                 goto open_error;
1601         }
1602
1603         /* Copy the MAC addr into the HW  */
1604         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1605
1606         /* If required, perform hw setup of the bus. */
1607         if (priv->plat->bus_setup)
1608                 priv->plat->bus_setup(priv->ioaddr);
1609
1610         /* Initialize the MAC Core */
1611         priv->hw->mac->core_init(priv->ioaddr);
1612
1613         /* Request the IRQ lines */
1614         ret = request_irq(dev->irq, stmmac_interrupt,
1615                          IRQF_SHARED, dev->name, dev);
1616         if (unlikely(ret < 0)) {
1617                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1618                        __func__, dev->irq, ret);
1619                 goto open_error;
1620         }
1621
1622         /* Request the Wake IRQ in case of another line is used for WoL */
1623         if (priv->wol_irq != dev->irq) {
1624                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1625                                   IRQF_SHARED, dev->name, dev);
1626                 if (unlikely(ret < 0)) {
1627                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1628                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1629                         goto open_error_wolirq;
1630                 }
1631         }
1632
1633         /* Request the IRQ lines */
1634         if (priv->lpi_irq != -ENXIO) {
1635                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1636                                   dev->name, dev);
1637                 if (unlikely(ret < 0)) {
1638                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1639                                __func__, priv->lpi_irq, ret);
1640                         goto open_error_lpiirq;
1641                 }
1642         }
1643
1644         /* Enable the MAC Rx/Tx */
1645         stmmac_set_mac(priv->ioaddr, true);
1646
1647         /* Set the HW DMA mode and the COE */
1648         stmmac_dma_operation_mode(priv);
1649
1650         /* Extra statistics */
1651         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1652         priv->xstats.threshold = tc;
1653
1654         stmmac_mmc_setup(priv);
1655
1656         ret = stmmac_init_ptp(priv);
1657         if (ret)
1658                 pr_warn("%s: failed PTP initialisation\n", __func__);
1659
1660 #ifdef CONFIG_STMMAC_DEBUG_FS
1661         ret = stmmac_init_fs(dev);
1662         if (ret < 0)
1663                 pr_warning("%s: failed debugFS registration\n", __func__);
1664 #endif
1665         /* Start the ball rolling... */
1666         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1667         priv->hw->dma->start_tx(priv->ioaddr);
1668         priv->hw->dma->start_rx(priv->ioaddr);
1669
1670         /* Dump DMA/MAC registers */
1671         if (netif_msg_hw(priv)) {
1672                 priv->hw->mac->dump_regs(priv->ioaddr);
1673                 priv->hw->dma->dump_regs(priv->ioaddr);
1674         }
1675
1676         if (priv->phydev)
1677                 phy_start(priv->phydev);
1678
1679         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1680
1681         /* Using PCS we cannot dial with the phy registers at this stage
1682          * so we do not support extra feature like EEE.
1683          */
1684         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1685             priv->pcs != STMMAC_PCS_RTBI)
1686                 priv->eee_enabled = stmmac_eee_init(priv);
1687
1688         stmmac_init_tx_coalesce(priv);
1689
1690         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1691                 priv->rx_riwt = MAX_DMA_RIWT;
1692                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1693         }
1694
1695         if (priv->pcs && priv->hw->mac->ctrl_ane)
1696                 priv->hw->mac->ctrl_ane(priv->ioaddr, 0);
1697
1698         napi_enable(&priv->napi);
1699         netif_start_queue(dev);
1700
1701         return 0;
1702
1703 open_error_lpiirq:
1704         if (priv->wol_irq != dev->irq)
1705                 free_irq(priv->wol_irq, dev);
1706
1707 open_error_wolirq:
1708         free_irq(dev->irq, dev);
1709
1710 open_error:
1711         if (priv->phydev)
1712                 phy_disconnect(priv->phydev);
1713
1714         clk_disable_unprepare(priv->stmmac_clk);
1715
1716         return ret;
1717 }
1718
1719 /**
1720  *  stmmac_release - close entry point of the driver
1721  *  @dev : device pointer.
1722  *  Description:
1723  *  This is the stop entry point of the driver.
1724  */
1725 static int stmmac_release(struct net_device *dev)
1726 {
1727         struct stmmac_priv *priv = netdev_priv(dev);
1728
1729         if (priv->eee_enabled)
1730                 del_timer_sync(&priv->eee_ctrl_timer);
1731
1732         /* Stop and disconnect the PHY */
1733         if (priv->phydev) {
1734                 phy_stop(priv->phydev);
1735                 phy_disconnect(priv->phydev);
1736                 priv->phydev = NULL;
1737         }
1738
1739         netif_stop_queue(dev);
1740
1741         napi_disable(&priv->napi);
1742
1743         del_timer_sync(&priv->txtimer);
1744
1745         /* Free the IRQ lines */
1746         free_irq(dev->irq, dev);
1747         if (priv->wol_irq != dev->irq)
1748                 free_irq(priv->wol_irq, dev);
1749         if (priv->lpi_irq != -ENXIO)
1750                 free_irq(priv->lpi_irq, dev);
1751
1752         /* Stop TX/RX DMA and clear the descriptors */
1753         priv->hw->dma->stop_tx(priv->ioaddr);
1754         priv->hw->dma->stop_rx(priv->ioaddr);
1755
1756         /* Release and free the Rx/Tx resources */
1757         free_dma_desc_resources(priv);
1758
1759         /* Disable the MAC Rx/Tx */
1760         stmmac_set_mac(priv->ioaddr, false);
1761
1762         netif_carrier_off(dev);
1763
1764 #ifdef CONFIG_STMMAC_DEBUG_FS
1765         stmmac_exit_fs();
1766 #endif
1767         clk_disable_unprepare(priv->stmmac_clk);
1768
1769         stmmac_release_ptp(priv);
1770
1771         return 0;
1772 }
1773
1774 /**
1775  *  stmmac_xmit: Tx entry point of the driver
1776  *  @skb : the socket buffer
1777  *  @dev : device pointer
1778  *  Description : this is the tx entry point of the driver.
1779  *  It programs the chain or the ring and supports oversized frames
1780  *  and SG feature.
1781  */
1782 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1783 {
1784         struct stmmac_priv *priv = netdev_priv(dev);
1785         unsigned int txsize = priv->dma_tx_size;
1786         unsigned int entry;
1787         int i, csum_insertion = 0, is_jumbo = 0;
1788         int nfrags = skb_shinfo(skb)->nr_frags;
1789         struct dma_desc *desc, *first;
1790         unsigned int nopaged_len = skb_headlen(skb);
1791
1792         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1793                 if (!netif_queue_stopped(dev)) {
1794                         netif_stop_queue(dev);
1795                         /* This is a hard error, log it. */
1796                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1797                                 __func__);
1798                 }
1799                 return NETDEV_TX_BUSY;
1800         }
1801
1802         spin_lock(&priv->tx_lock);
1803
1804         if (priv->tx_path_in_lpi_mode)
1805                 stmmac_disable_eee_mode(priv);
1806
1807         entry = priv->cur_tx % txsize;
1808
1809 #ifdef STMMAC_XMIT_DEBUG
1810         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1811                 pr_debug("stmmac xmit: [entry %d]\n"
1812                          "\tskb addr %p - len: %d - nopaged_len: %d\n"
1813                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1814                          "\ttx_count_frames %d\n", entry,
1815                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1816                          !skb_is_gso(skb) ? "isn't" : "is",
1817                          priv->tx_count_frames);
1818 #endif
1819
1820         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1821
1822         if (priv->extend_desc)
1823                 desc = (struct dma_desc *) (priv->dma_etx + entry);
1824         else
1825                 desc = priv->dma_tx + entry;
1826
1827         first = desc;
1828
1829 #ifdef STMMAC_XMIT_DEBUG
1830         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1831                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1832                          "\t\tn_frags: %d, ip_summed: %d\n",
1833                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1834 #endif
1835         priv->tx_skbuff[entry] = skb;
1836
1837         /* To program the descriptors according to the size of the frame */
1838         if (priv->mode == STMMAC_RING_MODE) {
1839                 is_jumbo = priv->hw->ring->is_jumbo_frm(skb->len,
1840                                                         priv->plat->enh_desc);
1841                 if (unlikely(is_jumbo))
1842                         entry = priv->hw->ring->jumbo_frm(priv, skb,
1843                                                           csum_insertion);
1844         } else {
1845                 is_jumbo = priv->hw->chain->is_jumbo_frm(skb->len,
1846                                                         priv->plat->enh_desc);
1847                 if (unlikely(is_jumbo))
1848                         entry = priv->hw->chain->jumbo_frm(priv, skb,
1849                                                            csum_insertion);
1850         }
1851         if (likely(!is_jumbo)) {
1852                 desc->des2 = dma_map_single(priv->device, skb->data,
1853                                         nopaged_len, DMA_TO_DEVICE);
1854                 priv->tx_skbuff_dma[entry] = desc->des2;
1855                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1856                                                 csum_insertion, priv->mode);
1857         } else
1858                 desc = first;
1859
1860         for (i = 0; i < nfrags; i++) {
1861                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1862                 int len = skb_frag_size(frag);
1863
1864                 entry = (++priv->cur_tx) % txsize;
1865                 if (priv->extend_desc)
1866                         desc = (struct dma_desc *) (priv->dma_etx + entry);
1867                 else
1868                         desc = priv->dma_tx + entry;
1869
1870                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1871                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1872                                               DMA_TO_DEVICE);
1873                 priv->tx_skbuff_dma[entry] = desc->des2;
1874                 priv->tx_skbuff[entry] = NULL;
1875                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1876                                                 priv->mode);
1877                 wmb();
1878                 priv->hw->desc->set_tx_owner(desc);
1879                 wmb();
1880         }
1881
1882         /* Finalize the latest segment. */
1883         priv->hw->desc->close_tx_desc(desc);
1884
1885         wmb();
1886         /* According to the coalesce parameter the IC bit for the latest
1887          * segment could be reset and the timer re-started to invoke the
1888          * stmmac_tx function. This approach takes care about the fragments.
1889          */
1890         priv->tx_count_frames += nfrags + 1;
1891         if (priv->tx_coal_frames > priv->tx_count_frames) {
1892                 priv->hw->desc->clear_tx_ic(desc);
1893                 priv->xstats.tx_reset_ic_bit++;
1894                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1895                        priv->tx_count_frames);
1896                 mod_timer(&priv->txtimer,
1897                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1898         } else
1899                 priv->tx_count_frames = 0;
1900
1901         /* To avoid raise condition */
1902         priv->hw->desc->set_tx_owner(first);
1903         wmb();
1904
1905         priv->cur_tx++;
1906
1907 #ifdef STMMAC_XMIT_DEBUG
1908         if (netif_msg_pktdata(priv)) {
1909                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1910                        "first=%p, nfrags=%d\n",
1911                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1912                        entry, first, nfrags);
1913                 if (priv->extend_desc)
1914                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1915                 else
1916                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1917
1918                 pr_info(">>> frame to be transmitted: ");
1919                 print_pkt(skb->data, skb->len);
1920         }
1921 #endif
1922         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1923                 TX_DBG("%s: stop transmitted packets\n", __func__);
1924                 netif_stop_queue(dev);
1925         }
1926
1927         dev->stats.tx_bytes += skb->len;
1928
1929         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1930                      priv->hwts_tx_en)) {
1931                 /* declare that device is doing timestamping */
1932                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1933                 priv->hw->desc->enable_tx_timestamp(first);
1934         }
1935
1936         if (!priv->hwts_tx_en)
1937                 skb_tx_timestamp(skb);
1938
1939         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1940
1941         spin_unlock(&priv->tx_lock);
1942
1943         return NETDEV_TX_OK;
1944 }
1945
1946 /**
1947  * stmmac_rx_refill: refill used skb preallocated buffers
1948  * @priv: driver private structure
1949  * Description : this is to reallocate the skb for the reception process
1950  * that is based on zero-copy.
1951  */
1952 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1953 {
1954         unsigned int rxsize = priv->dma_rx_size;
1955         int bfsize = priv->dma_buf_sz;
1956
1957         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1958                 unsigned int entry = priv->dirty_rx % rxsize;
1959                 struct dma_desc *p;
1960
1961                 if (priv->extend_desc)
1962                         p = (struct dma_desc *) (priv->dma_erx + entry);
1963                 else
1964                         p = priv->dma_rx + entry;
1965
1966                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1967                         struct sk_buff *skb;
1968
1969                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1970
1971                         if (unlikely(skb == NULL))
1972                                 break;
1973
1974                         priv->rx_skbuff[entry] = skb;
1975                         priv->rx_skbuff_dma[entry] =
1976                             dma_map_single(priv->device, skb->data, bfsize,
1977                                            DMA_FROM_DEVICE);
1978
1979                         p->des2 = priv->rx_skbuff_dma[entry];
1980
1981                         priv->hw->ring->refill_desc3(priv, p);
1982
1983                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1984                 }
1985                 wmb();
1986                 priv->hw->desc->set_rx_owner(p);
1987                 wmb();
1988         }
1989 }
1990
1991 /**
1992  * stmmac_rx_refill: refill used skb preallocated buffers
1993  * @priv: driver private structure
1994  * @limit: napi bugget.
1995  * Description :  this the function called by the napi poll method.
1996  * It gets all the frames inside the ring.
1997  */
1998 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1999 {
2000         unsigned int rxsize = priv->dma_rx_size;
2001         unsigned int entry = priv->cur_rx % rxsize;
2002         unsigned int next_entry;
2003         unsigned int count = 0;
2004
2005 #ifdef STMMAC_RX_DEBUG
2006         if (netif_msg_hw(priv)) {
2007                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
2008                 if (priv->extend_desc)
2009                         stmmac_display_ring((void *) priv->dma_erx, rxsize, 1);
2010                 else
2011                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2012         }
2013 #endif
2014         while (count < limit) {
2015                 int status;
2016                 struct dma_desc *p, *p_next;
2017
2018                 if (priv->extend_desc)
2019                         p = (struct dma_desc *) (priv->dma_erx + entry);
2020                 else
2021                         p = priv->dma_rx + entry ;
2022
2023                 if (priv->hw->desc->get_rx_owner(p))
2024                         break;
2025
2026                 count++;
2027
2028                 next_entry = (++priv->cur_rx) % rxsize;
2029                 if (priv->extend_desc)
2030                         p_next = (struct dma_desc *) (priv->dma_erx +
2031                                                       next_entry);
2032                 else
2033                         p_next = priv->dma_rx + next_entry;
2034
2035                 prefetch(p_next);
2036
2037                 /* read the status of the incoming frame */
2038                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2039                                                    &priv->xstats, p);
2040                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2041                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2042                                                            &priv->xstats,
2043                                                            priv->dma_erx +
2044                                                            entry);
2045                 if (unlikely(status == discard_frame)) {
2046                         priv->dev->stats.rx_errors++;
2047                         if (priv->hwts_rx_en && !priv->extend_desc) {
2048                                 /* DESC2 & DESC3 will be overwitten by device
2049                                  * with timestamp value, hence reinitialize
2050                                  * them in stmmac_rx_refill() function so that
2051                                  * device can reuse it.
2052                                  */
2053                                 priv->rx_skbuff[entry] = NULL;
2054                                 dma_unmap_single(priv->device,
2055                                         priv->rx_skbuff_dma[entry],
2056                                         priv->dma_buf_sz, DMA_FROM_DEVICE);
2057                         }
2058                 } else {
2059                         struct sk_buff *skb;
2060                         int frame_len;
2061
2062                         frame_len = priv->hw->desc->get_rx_frame_len(p,
2063                                         priv->plat->rx_coe);
2064                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2065                          * Type frames (LLC/LLC-SNAP) */
2066                         if (unlikely(status != llc_snap))
2067                                 frame_len -= ETH_FCS_LEN;
2068 #ifdef STMMAC_RX_DEBUG
2069                         if (frame_len > ETH_FRAME_LEN)
2070                                 pr_debug("\tRX frame size %d, COE status: %d\n",
2071                                         frame_len, status);
2072
2073                         if (netif_msg_hw(priv))
2074                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2075                                         p, entry, p->des2);
2076 #endif
2077                         skb = priv->rx_skbuff[entry];
2078                         if (unlikely(!skb)) {
2079                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2080                                         priv->dev->name);
2081                                 priv->dev->stats.rx_dropped++;
2082                                 break;
2083                         }
2084                         prefetch(skb->data - NET_IP_ALIGN);
2085                         priv->rx_skbuff[entry] = NULL;
2086
2087                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2088
2089                         skb_put(skb, frame_len);
2090                         dma_unmap_single(priv->device,
2091                                          priv->rx_skbuff_dma[entry],
2092                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2093 #ifdef STMMAC_RX_DEBUG
2094                         if (netif_msg_pktdata(priv)) {
2095                                 pr_info(" frame received (%dbytes)", frame_len);
2096                                 print_pkt(skb->data, frame_len);
2097                         }
2098 #endif
2099                         skb->protocol = eth_type_trans(skb, priv->dev);
2100
2101                         if (unlikely(!priv->plat->rx_coe))
2102                                 skb_checksum_none_assert(skb);
2103                         else
2104                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2105
2106                         napi_gro_receive(&priv->napi, skb);
2107
2108                         priv->dev->stats.rx_packets++;
2109                         priv->dev->stats.rx_bytes += frame_len;
2110                 }
2111                 entry = next_entry;
2112         }
2113
2114         stmmac_rx_refill(priv);
2115
2116         priv->xstats.rx_pkt_n += count;
2117
2118         return count;
2119 }
2120
2121 /**
2122  *  stmmac_poll - stmmac poll method (NAPI)
2123  *  @napi : pointer to the napi structure.
2124  *  @budget : maximum number of packets that the current CPU can receive from
2125  *            all interfaces.
2126  *  Description :
2127  *  To look at the incoming frames and clear the tx resources.
2128  */
2129 static int stmmac_poll(struct napi_struct *napi, int budget)
2130 {
2131         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2132         int work_done = 0;
2133
2134         priv->xstats.napi_poll++;
2135         stmmac_tx_clean(priv);
2136
2137         work_done = stmmac_rx(priv, budget);
2138         if (work_done < budget) {
2139                 napi_complete(napi);
2140                 stmmac_enable_dma_irq(priv);
2141         }
2142         return work_done;
2143 }
2144
2145 /**
2146  *  stmmac_tx_timeout
2147  *  @dev : Pointer to net device structure
2148  *  Description: this function is called when a packet transmission fails to
2149  *   complete within a reasonable time. The driver will mark the error in the
2150  *   netdev structure and arrange for the device to be reset to a sane state
2151  *   in order to transmit a new packet.
2152  */
2153 static void stmmac_tx_timeout(struct net_device *dev)
2154 {
2155         struct stmmac_priv *priv = netdev_priv(dev);
2156
2157         /* Clear Tx resources and restart transmitting again */
2158         stmmac_tx_err(priv);
2159 }
2160
2161 /* Configuration changes (passed on by ifconfig) */
2162 static int stmmac_config(struct net_device *dev, struct ifmap *map)
2163 {
2164         if (dev->flags & IFF_UP)        /* can't act on a running interface */
2165                 return -EBUSY;
2166
2167         /* Don't allow changing the I/O address */
2168         if (map->base_addr != dev->base_addr) {
2169                 pr_warning("%s: can't change I/O address\n", dev->name);
2170                 return -EOPNOTSUPP;
2171         }
2172
2173         /* Don't allow changing the IRQ */
2174         if (map->irq != dev->irq) {
2175                 pr_warning("%s: can't change IRQ number %d\n",
2176                        dev->name, dev->irq);
2177                 return -EOPNOTSUPP;
2178         }
2179
2180         /* ignore other fields */
2181         return 0;
2182 }
2183
2184 /**
2185  *  stmmac_set_rx_mode - entry point for multicast addressing
2186  *  @dev : pointer to the device structure
2187  *  Description:
2188  *  This function is a driver entry point which gets called by the kernel
2189  *  whenever multicast addresses must be enabled/disabled.
2190  *  Return value:
2191  *  void.
2192  */
2193 static void stmmac_set_rx_mode(struct net_device *dev)
2194 {
2195         struct stmmac_priv *priv = netdev_priv(dev);
2196
2197         spin_lock(&priv->lock);
2198         priv->hw->mac->set_filter(dev, priv->synopsys_id);
2199         spin_unlock(&priv->lock);
2200 }
2201
2202 /**
2203  *  stmmac_change_mtu - entry point to change MTU size for the device.
2204  *  @dev : device pointer.
2205  *  @new_mtu : the new MTU size for the device.
2206  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2207  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2208  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2209  *  Return value:
2210  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2211  *  file on failure.
2212  */
2213 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2214 {
2215         struct stmmac_priv *priv = netdev_priv(dev);
2216         int max_mtu;
2217
2218         if (netif_running(dev)) {
2219                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2220                 return -EBUSY;
2221         }
2222
2223         if (priv->plat->enh_desc)
2224                 max_mtu = JUMBO_LEN;
2225         else
2226                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2227
2228         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2229                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2230                 return -EINVAL;
2231         }
2232
2233         dev->mtu = new_mtu;
2234         netdev_update_features(dev);
2235
2236         return 0;
2237 }
2238
2239 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2240         netdev_features_t features)
2241 {
2242         struct stmmac_priv *priv = netdev_priv(dev);
2243
2244         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2245                 features &= ~NETIF_F_RXCSUM;
2246         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2247                 features &= ~NETIF_F_IPV6_CSUM;
2248         if (!priv->plat->tx_coe)
2249                 features &= ~NETIF_F_ALL_CSUM;
2250
2251         /* Some GMAC devices have a bugged Jumbo frame support that
2252          * needs to have the Tx COE disabled for oversized frames
2253          * (due to limited buffer sizes). In this case we disable
2254          * the TX csum insertionin the TDES and not use SF. */
2255         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2256                 features &= ~NETIF_F_ALL_CSUM;
2257
2258         return features;
2259 }
2260
2261 /**
2262  *  stmmac_interrupt - main ISR
2263  *  @irq: interrupt number.
2264  *  @dev_id: to pass the net device pointer.
2265  *  Description: this is the main driver interrupt service routine.
2266  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2267  *  interrupts.
2268  */
2269 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2270 {
2271         struct net_device *dev = (struct net_device *)dev_id;
2272         struct stmmac_priv *priv = netdev_priv(dev);
2273
2274         if (unlikely(!dev)) {
2275                 pr_err("%s: invalid dev pointer\n", __func__);
2276                 return IRQ_NONE;
2277         }
2278
2279         /* To handle GMAC own interrupts */
2280         if (priv->plat->has_gmac) {
2281                 int status = priv->hw->mac->host_irq_status((void __iomem *)
2282                                                             dev->base_addr,
2283                                                             &priv->xstats);
2284                 if (unlikely(status)) {
2285                         /* For LPI we need to save the tx status */
2286                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2287                                 priv->tx_path_in_lpi_mode = true;
2288                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2289                                 priv->tx_path_in_lpi_mode = false;
2290                 }
2291         }
2292
2293         /* To handle DMA interrupts */
2294         stmmac_dma_interrupt(priv);
2295
2296         return IRQ_HANDLED;
2297 }
2298
2299 #ifdef CONFIG_NET_POLL_CONTROLLER
2300 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2301  * to allow network I/O with interrupts disabled. */
2302 static void stmmac_poll_controller(struct net_device *dev)
2303 {
2304         disable_irq(dev->irq);
2305         stmmac_interrupt(dev->irq, dev);
2306         enable_irq(dev->irq);
2307 }
2308 #endif
2309
2310 /**
2311  *  stmmac_ioctl - Entry point for the Ioctl
2312  *  @dev: Device pointer.
2313  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2314  *  a proprietary structure used to pass information to the driver.
2315  *  @cmd: IOCTL command
2316  *  Description:
2317  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2318  */
2319 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2320 {
2321         struct stmmac_priv *priv = netdev_priv(dev);
2322         int ret = -EOPNOTSUPP;
2323
2324         if (!netif_running(dev))
2325                 return -EINVAL;
2326
2327         switch (cmd) {
2328         case SIOCGMIIPHY:
2329         case SIOCGMIIREG:
2330         case SIOCSMIIREG:
2331                 if (!priv->phydev)
2332                         return -EINVAL;
2333                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2334                 break;
2335         case SIOCSHWTSTAMP:
2336                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2337                 break;
2338         default:
2339                 break;
2340         }
2341
2342         return ret;
2343 }
2344
2345 #ifdef CONFIG_STMMAC_DEBUG_FS
2346 static struct dentry *stmmac_fs_dir;
2347 static struct dentry *stmmac_rings_status;
2348 static struct dentry *stmmac_dma_cap;
2349
2350 static void sysfs_display_ring(void *head, int size, int extend_desc,
2351                                 struct seq_file *seq)
2352 {
2353         int i;
2354         struct dma_extended_desc *ep = (struct dma_extended_desc *) head;
2355         struct dma_desc *p = (struct dma_desc *) head;
2356
2357         for (i = 0; i < size; i++) {
2358                 u64 x;
2359                 if (extend_desc) {
2360                         x = *(u64 *) ep;
2361                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2362                                    i, (unsigned int) virt_to_phys(ep),
2363                                    (unsigned int) x, (unsigned int) (x >> 32),
2364                                    ep->basic.des2, ep->basic.des3);
2365                         ep++;
2366                 } else {
2367                         x = *(u64 *) p;
2368                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2369                                    i, (unsigned int) virt_to_phys(ep),
2370                                    (unsigned int) x, (unsigned int) (x >> 32),
2371                                    p->des2, p->des3);
2372                         p++;
2373                 }
2374                 seq_printf(seq, "\n");
2375         }
2376 }
2377
2378 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2379 {
2380         struct net_device *dev = seq->private;
2381         struct stmmac_priv *priv = netdev_priv(dev);
2382         unsigned int txsize = priv->dma_tx_size;
2383         unsigned int rxsize = priv->dma_rx_size;
2384
2385         if (priv->extend_desc) {
2386                 seq_printf(seq, "Extended RX descriptor ring:\n");
2387                 sysfs_display_ring((void *) priv->dma_erx, rxsize, 1, seq);
2388                 seq_printf(seq, "Extended TX descriptor ring:\n");
2389                 sysfs_display_ring((void *) priv->dma_etx, txsize, 1, seq);
2390         } else {
2391                 seq_printf(seq, "RX descriptor ring:\n");
2392                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2393                 seq_printf(seq, "TX descriptor ring:\n");
2394                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2395         }
2396
2397         return 0;
2398 }
2399
2400 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2401 {
2402         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2403 }
2404
2405 static const struct file_operations stmmac_rings_status_fops = {
2406         .owner = THIS_MODULE,
2407         .open = stmmac_sysfs_ring_open,
2408         .read = seq_read,
2409         .llseek = seq_lseek,
2410         .release = single_release,
2411 };
2412
2413 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2414 {
2415         struct net_device *dev = seq->private;
2416         struct stmmac_priv *priv = netdev_priv(dev);
2417
2418         if (!priv->hw_cap_support) {
2419                 seq_printf(seq, "DMA HW features not supported\n");
2420                 return 0;
2421         }
2422
2423         seq_printf(seq, "==============================\n");
2424         seq_printf(seq, "\tDMA HW features\n");
2425         seq_printf(seq, "==============================\n");
2426
2427         seq_printf(seq, "\t10/100 Mbps %s\n",
2428                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2429         seq_printf(seq, "\t1000 Mbps %s\n",
2430                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2431         seq_printf(seq, "\tHalf duple %s\n",
2432                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2433         seq_printf(seq, "\tHash Filter: %s\n",
2434                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2435         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2436                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2437         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2438                    (priv->dma_cap.pcs) ? "Y" : "N");
2439         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2440                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2441         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2442                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2443         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2444                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2445         seq_printf(seq, "\tRMON module: %s\n",
2446                    (priv->dma_cap.rmon) ? "Y" : "N");
2447         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2448                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2449         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2450                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2451         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2452                    (priv->dma_cap.eee) ? "Y" : "N");
2453         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2454         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2455                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2456         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2457                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2458         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2459                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2460         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2461                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2462         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2463                    priv->dma_cap.number_rx_channel);
2464         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2465                    priv->dma_cap.number_tx_channel);
2466         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2467                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2468
2469         return 0;
2470 }
2471
2472 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2473 {
2474         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2475 }
2476
2477 static const struct file_operations stmmac_dma_cap_fops = {
2478         .owner = THIS_MODULE,
2479         .open = stmmac_sysfs_dma_cap_open,
2480         .read = seq_read,
2481         .llseek = seq_lseek,
2482         .release = single_release,
2483 };
2484
2485 static int stmmac_init_fs(struct net_device *dev)
2486 {
2487         /* Create debugfs entries */
2488         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2489
2490         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2491                 pr_err("ERROR %s, debugfs create directory failed\n",
2492                        STMMAC_RESOURCE_NAME);
2493
2494                 return -ENOMEM;
2495         }
2496
2497         /* Entry to report DMA RX/TX rings */
2498         stmmac_rings_status = debugfs_create_file("descriptors_status",
2499                                            S_IRUGO, stmmac_fs_dir, dev,
2500                                            &stmmac_rings_status_fops);
2501
2502         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2503                 pr_info("ERROR creating stmmac ring debugfs file\n");
2504                 debugfs_remove(stmmac_fs_dir);
2505
2506                 return -ENOMEM;
2507         }
2508
2509         /* Entry to report the DMA HW features */
2510         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2511                                              dev, &stmmac_dma_cap_fops);
2512
2513         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2514                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2515                 debugfs_remove(stmmac_rings_status);
2516                 debugfs_remove(stmmac_fs_dir);
2517
2518                 return -ENOMEM;
2519         }
2520
2521         return 0;
2522 }
2523
2524 static void stmmac_exit_fs(void)
2525 {
2526         debugfs_remove(stmmac_rings_status);
2527         debugfs_remove(stmmac_dma_cap);
2528         debugfs_remove(stmmac_fs_dir);
2529 }
2530 #endif /* CONFIG_STMMAC_DEBUG_FS */
2531
2532 static const struct net_device_ops stmmac_netdev_ops = {
2533         .ndo_open = stmmac_open,
2534         .ndo_start_xmit = stmmac_xmit,
2535         .ndo_stop = stmmac_release,
2536         .ndo_change_mtu = stmmac_change_mtu,
2537         .ndo_fix_features = stmmac_fix_features,
2538         .ndo_set_rx_mode = stmmac_set_rx_mode,
2539         .ndo_tx_timeout = stmmac_tx_timeout,
2540         .ndo_do_ioctl = stmmac_ioctl,
2541         .ndo_set_config = stmmac_config,
2542 #ifdef CONFIG_NET_POLL_CONTROLLER
2543         .ndo_poll_controller = stmmac_poll_controller,
2544 #endif
2545         .ndo_set_mac_address = eth_mac_addr,
2546 };
2547
2548 /**
2549  *  stmmac_hw_init - Init the MAC device
2550  *  @priv: driver private structure
2551  *  Description: this function detects which MAC device
2552  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2553  *  (if supported) and sets the driver's features (for example
2554  *  to use the ring or chaine mode or support the normal/enh
2555  *  descriptor structure).
2556  */
2557 static int stmmac_hw_init(struct stmmac_priv *priv)
2558 {
2559         int ret;
2560         struct mac_device_info *mac;
2561
2562         /* Identify the MAC HW device */
2563         if (priv->plat->has_gmac) {
2564                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2565                 mac = dwmac1000_setup(priv->ioaddr);
2566         } else {
2567                 mac = dwmac100_setup(priv->ioaddr);
2568         }
2569         if (!mac)
2570                 return -ENOMEM;
2571
2572         priv->hw = mac;
2573
2574         /* Get and dump the chip ID */
2575         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2576
2577         /* To use alternate (extended) or normal descriptor structures */
2578         stmmac_selec_desc_mode(priv);
2579
2580         /* To use the chained or ring mode */
2581         if (chain_mode) {
2582                 priv->hw->chain = &chain_mode_ops;
2583                 pr_info(" Chain mode enabled\n");
2584                 priv->mode = STMMAC_CHAIN_MODE;
2585         } else {
2586                 priv->hw->ring = &ring_mode_ops;
2587                 pr_info(" Ring mode enabled\n");
2588                 priv->mode = STMMAC_RING_MODE;
2589         }
2590
2591         /* Get the HW capability (new GMAC newer than 3.50a) */
2592         priv->hw_cap_support = stmmac_get_hw_features(priv);
2593         if (priv->hw_cap_support) {
2594                 pr_info(" DMA HW capability register supported");
2595
2596                 /* We can override some gmac/dma configuration fields: e.g.
2597                  * enh_desc, tx_coe (e.g. that are passed through the
2598                  * platform) with the values from the HW capability
2599                  * register (if supported).
2600                  */
2601                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2602                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2603
2604                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2605
2606                 if (priv->dma_cap.rx_coe_type2)
2607                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2608                 else if (priv->dma_cap.rx_coe_type1)
2609                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2610
2611         } else
2612                 pr_info(" No HW DMA feature register supported");
2613
2614         /* Enable the IPC (Checksum Offload) and check if the feature has been
2615          * enabled during the core configuration. */
2616         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
2617         if (!ret) {
2618                 pr_warning(" RX IPC Checksum Offload not configured.\n");
2619                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2620         }
2621
2622         if (priv->plat->rx_coe)
2623                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2624                         priv->plat->rx_coe);
2625         if (priv->plat->tx_coe)
2626                 pr_info(" TX Checksum insertion supported\n");
2627
2628         if (priv->plat->pmt) {
2629                 pr_info(" Wake-Up On Lan supported\n");
2630                 device_set_wakeup_capable(priv->device, 1);
2631         }
2632
2633         return 0;
2634 }
2635
2636 /**
2637  * stmmac_dvr_probe
2638  * @device: device pointer
2639  * @plat_dat: platform data pointer
2640  * @addr: iobase memory address
2641  * Description: this is the main probe function used to
2642  * call the alloc_etherdev, allocate the priv structure.
2643  */
2644 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2645                                      struct plat_stmmacenet_data *plat_dat,
2646                                      void __iomem *addr)
2647 {
2648         int ret = 0;
2649         struct net_device *ndev = NULL;
2650         struct stmmac_priv *priv;
2651
2652         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2653         if (!ndev)
2654                 return NULL;
2655
2656         SET_NETDEV_DEV(ndev, device);
2657
2658         priv = netdev_priv(ndev);
2659         priv->device = device;
2660         priv->dev = ndev;
2661
2662         ether_setup(ndev);
2663
2664         stmmac_set_ethtool_ops(ndev);
2665         priv->pause = pause;
2666         priv->plat = plat_dat;
2667         priv->ioaddr = addr;
2668         priv->dev->base_addr = (unsigned long)addr;
2669
2670         /* Verify driver arguments */
2671         stmmac_verify_args();
2672
2673         /* Override with kernel parameters if supplied XXX CRS XXX
2674          * this needs to have multiple instances */
2675         if ((phyaddr >= 0) && (phyaddr <= 31))
2676                 priv->plat->phy_addr = phyaddr;
2677
2678         /* Init MAC and get the capabilities */
2679         ret = stmmac_hw_init(priv);
2680         if (ret)
2681                 goto error_free_netdev;
2682
2683         ndev->netdev_ops = &stmmac_netdev_ops;
2684
2685         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2686                             NETIF_F_RXCSUM;
2687         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2688         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2689 #ifdef STMMAC_VLAN_TAG_USED
2690         /* Both mac100 and gmac support receive VLAN tag detection */
2691         ndev->features |= NETIF_F_HW_VLAN_RX;
2692 #endif
2693         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2694
2695         if (flow_ctrl)
2696                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2697
2698         /* Rx Watchdog is available in the COREs newer than the 3.40.
2699          * In some case, for example on bugged HW this feature
2700          * has to be disable and this can be done by passing the
2701          * riwt_off field from the platform.
2702          */
2703         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2704                 priv->use_riwt = 1;
2705                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2706         }
2707
2708         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2709
2710         spin_lock_init(&priv->lock);
2711         spin_lock_init(&priv->tx_lock);
2712
2713         ret = register_netdev(ndev);
2714         if (ret) {
2715                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2716                 goto error_netdev_register;
2717         }
2718
2719         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2720         if (IS_ERR(priv->stmmac_clk)) {
2721                 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2722                 goto error_clk_get;
2723         }
2724
2725         /* If a specific clk_csr value is passed from the platform
2726          * this means that the CSR Clock Range selection cannot be
2727          * changed at run-time and it is fixed. Viceversa the driver'll try to
2728          * set the MDC clock dynamically according to the csr actual
2729          * clock input.
2730          */
2731         if (!priv->plat->clk_csr)
2732                 stmmac_clk_csr_set(priv);
2733         else
2734                 priv->clk_csr = priv->plat->clk_csr;
2735
2736         stmmac_check_pcs_mode(priv);
2737
2738         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2739             priv->pcs != STMMAC_PCS_RTBI) {
2740                 /* MDIO bus Registration */
2741                 ret = stmmac_mdio_register(ndev);
2742                 if (ret < 0) {
2743                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2744                                  __func__, priv->plat->bus_id);
2745                         goto error_mdio_register;
2746                 }
2747         }
2748
2749         return priv;
2750
2751 error_mdio_register:
2752         clk_put(priv->stmmac_clk);
2753 error_clk_get:
2754         unregister_netdev(ndev);
2755 error_netdev_register:
2756         netif_napi_del(&priv->napi);
2757 error_free_netdev:
2758         free_netdev(ndev);
2759
2760         return NULL;
2761 }
2762
2763 /**
2764  * stmmac_dvr_remove
2765  * @ndev: net device pointer
2766  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2767  * changes the link status, releases the DMA descriptor rings.
2768  */
2769 int stmmac_dvr_remove(struct net_device *ndev)
2770 {
2771         struct stmmac_priv *priv = netdev_priv(ndev);
2772
2773         pr_info("%s:\n\tremoving driver", __func__);
2774
2775         priv->hw->dma->stop_rx(priv->ioaddr);
2776         priv->hw->dma->stop_tx(priv->ioaddr);
2777
2778         stmmac_set_mac(priv->ioaddr, false);
2779         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2780             priv->pcs != STMMAC_PCS_RTBI)
2781                 stmmac_mdio_unregister(ndev);
2782         netif_carrier_off(ndev);
2783         unregister_netdev(ndev);
2784         free_netdev(ndev);
2785
2786         return 0;
2787 }
2788
2789 #ifdef CONFIG_PM
2790 int stmmac_suspend(struct net_device *ndev)
2791 {
2792         struct stmmac_priv *priv = netdev_priv(ndev);
2793         unsigned long flags;
2794
2795         if (!ndev || !netif_running(ndev))
2796                 return 0;
2797
2798         if (priv->phydev)
2799                 phy_stop(priv->phydev);
2800
2801         spin_lock_irqsave(&priv->lock, flags);
2802
2803         netif_device_detach(ndev);
2804         netif_stop_queue(ndev);
2805
2806         napi_disable(&priv->napi);
2807
2808         /* Stop TX/RX DMA */
2809         priv->hw->dma->stop_tx(priv->ioaddr);
2810         priv->hw->dma->stop_rx(priv->ioaddr);
2811
2812         stmmac_clear_descriptors(priv);
2813
2814         /* Enable Power down mode by programming the PMT regs */
2815         if (device_may_wakeup(priv->device))
2816                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2817         else {
2818                 stmmac_set_mac(priv->ioaddr, false);
2819                 /* Disable clock in case of PWM is off */
2820                 clk_disable_unprepare(priv->stmmac_clk);
2821         }
2822         spin_unlock_irqrestore(&priv->lock, flags);
2823         return 0;
2824 }
2825
2826 int stmmac_resume(struct net_device *ndev)
2827 {
2828         struct stmmac_priv *priv = netdev_priv(ndev);
2829         unsigned long flags;
2830
2831         if (!netif_running(ndev))
2832                 return 0;
2833
2834         spin_lock_irqsave(&priv->lock, flags);
2835
2836         /* Power Down bit, into the PM register, is cleared
2837          * automatically as soon as a magic packet or a Wake-up frame
2838          * is received. Anyway, it's better to manually clear
2839          * this bit because it can generate problems while resuming
2840          * from another devices (e.g. serial console). */
2841         if (device_may_wakeup(priv->device))
2842                 priv->hw->mac->pmt(priv->ioaddr, 0);
2843         else
2844                 /* enable the clk prevously disabled */
2845                 clk_prepare_enable(priv->stmmac_clk);
2846
2847         netif_device_attach(ndev);
2848
2849         /* Enable the MAC and DMA */
2850         stmmac_set_mac(priv->ioaddr, true);
2851         priv->hw->dma->start_tx(priv->ioaddr);
2852         priv->hw->dma->start_rx(priv->ioaddr);
2853
2854         napi_enable(&priv->napi);
2855
2856         netif_start_queue(ndev);
2857
2858         spin_unlock_irqrestore(&priv->lock, flags);
2859
2860         if (priv->phydev)
2861                 phy_start(priv->phydev);
2862
2863         return 0;
2864 }
2865
2866 int stmmac_freeze(struct net_device *ndev)
2867 {
2868         if (!ndev || !netif_running(ndev))
2869                 return 0;
2870
2871         return stmmac_release(ndev);
2872 }
2873
2874 int stmmac_restore(struct net_device *ndev)
2875 {
2876         if (!ndev || !netif_running(ndev))
2877                 return 0;
2878
2879         return stmmac_open(ndev);
2880 }
2881 #endif /* CONFIG_PM */
2882
2883 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2884  * depending on the configuration selected.
2885  */
2886 static int __init stmmac_init(void)
2887 {
2888         int ret;
2889
2890         ret = stmmac_register_platform();
2891         if (ret)
2892                 goto err;
2893         ret = stmmac_register_pci();
2894         if (ret)
2895                 goto err_pci;
2896         return 0;
2897 err_pci:
2898         stmmac_unregister_platform();
2899 err:
2900         pr_err("stmmac: driver registration failed\n");
2901         return ret;
2902 }
2903
2904 static void __exit stmmac_exit(void)
2905 {
2906         stmmac_unregister_platform();
2907         stmmac_unregister_pci();
2908 }
2909
2910 module_init(stmmac_init);
2911 module_exit(stmmac_exit);
2912
2913 #ifndef MODULE
2914 static int __init stmmac_cmdline_opt(char *str)
2915 {
2916         char *opt;
2917
2918         if (!str || !*str)
2919                 return -EINVAL;
2920         while ((opt = strsep(&str, ",")) != NULL) {
2921                 if (!strncmp(opt, "debug:", 6)) {
2922                         if (kstrtoint(opt + 6, 0, &debug))
2923                                 goto err;
2924                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2925                         if (kstrtoint(opt + 8, 0, &phyaddr))
2926                                 goto err;
2927                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2928                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2929                                 goto err;
2930                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2931                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2932                                 goto err;
2933                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2934                         if (kstrtoint(opt + 7, 0, &buf_sz))
2935                                 goto err;
2936                 } else if (!strncmp(opt, "tc:", 3)) {
2937                         if (kstrtoint(opt + 3, 0, &tc))
2938                                 goto err;
2939                 } else if (!strncmp(opt, "watchdog:", 9)) {
2940                         if (kstrtoint(opt + 9, 0, &watchdog))
2941                                 goto err;
2942                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2943                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2944                                 goto err;
2945                 } else if (!strncmp(opt, "pause:", 6)) {
2946                         if (kstrtoint(opt + 6, 0, &pause))
2947                                 goto err;
2948                 } else if (!strncmp(opt, "eee_timer:", 10)) {
2949                         if (kstrtoint(opt + 10, 0, &eee_timer))
2950                                 goto err;
2951                 } else if (!strncmp(opt, "chain_mode:", 11)) {
2952                         if (kstrtoint(opt + 11, 0, &chain_mode))
2953                                 goto err;
2954                 }
2955         }
2956         return 0;
2957
2958 err:
2959         pr_err("%s: ERROR broken module parameter conversion", __func__);
2960         return -EINVAL;
2961 }
2962
2963 __setup("stmmaceth=", stmmac_cmdline_opt);
2964 #endif
2965
2966 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2967 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2968 MODULE_LICENSE("GPL");