1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
56 #include "dwmac1000.h"
58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
60 /* Module parameters */
62 static int watchdog = TX_TIMEO;
63 module_param(watchdog, int, S_IRUGO | S_IWUSR);
64 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
66 static int debug = -1;
67 module_param(debug, int, S_IRUGO | S_IWUSR);
68 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
70 static int phyaddr = -1;
71 module_param(phyaddr, int, S_IRUGO);
72 MODULE_PARM_DESC(phyaddr, "Physical device address");
74 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
76 static int flow_ctrl = FLOW_OFF;
77 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
78 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
80 static int pause = PAUSE_TIME;
81 module_param(pause, int, S_IRUGO | S_IWUSR);
82 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
85 static int tc = TC_DEFAULT;
86 module_param(tc, int, S_IRUGO | S_IWUSR);
87 MODULE_PARM_DESC(tc, "DMA threshold control value");
89 #define DEFAULT_BUFSIZE 1536
90 static int buf_sz = DEFAULT_BUFSIZE;
91 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
92 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
94 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
95 NETIF_MSG_LINK | NETIF_MSG_IFUP |
96 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
98 #define STMMAC_DEFAULT_LPI_TIMER 1000
99 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
100 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
101 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
102 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
104 /* By default the driver will use the ring mode to manage tx and rx descriptors
105 * but passing this value so user can force to use the chain instead of the ring
107 static unsigned int chain_mode;
108 module_param(chain_mode, int, S_IRUGO);
109 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
111 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
113 #ifdef CONFIG_DEBUG_FS
114 static int stmmac_init_fs(struct net_device *dev);
115 static void stmmac_exit_fs(struct net_device *dev);
118 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
121 * stmmac_verify_args - verify the driver parameters.
122 * Description: it checks the driver parameters and set a default in case of
125 static void stmmac_verify_args(void)
127 if (unlikely(watchdog < 0))
129 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
130 buf_sz = DEFAULT_BUFSIZE;
131 if (unlikely(flow_ctrl > 1))
132 flow_ctrl = FLOW_AUTO;
133 else if (likely(flow_ctrl < 0))
134 flow_ctrl = FLOW_OFF;
135 if (unlikely((pause < 0) || (pause > 0xffff)))
138 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
142 * stmmac_clk_csr_set - dynamically set the MDC clock
143 * @priv: driver private structure
144 * Description: this is to dynamically set the MDC clock according to the csr
147 * If a specific clk_csr value is passed from the platform
148 * this means that the CSR Clock Range selection cannot be
149 * changed at run-time and it is fixed (as reported in the driver
150 * documentation). Viceversa the driver will try to set the MDC
151 * clock dynamically according to the actual clock input.
153 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
157 clk_rate = clk_get_rate(priv->stmmac_clk);
159 /* Platform provided default clk_csr would be assumed valid
160 * for all other cases except for the below mentioned ones.
161 * For values higher than the IEEE 802.3 specified frequency
162 * we can not estimate the proper divider as it is not known
163 * the frequency of clk_csr_i. So we do not change the default
166 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
167 if (clk_rate < CSR_F_35M)
168 priv->clk_csr = STMMAC_CSR_20_35M;
169 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
170 priv->clk_csr = STMMAC_CSR_35_60M;
171 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
172 priv->clk_csr = STMMAC_CSR_60_100M;
173 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
174 priv->clk_csr = STMMAC_CSR_100_150M;
175 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
176 priv->clk_csr = STMMAC_CSR_150_250M;
177 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
178 priv->clk_csr = STMMAC_CSR_250_300M;
182 static void print_pkt(unsigned char *buf, int len)
184 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
185 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
188 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
192 if (priv->dirty_tx > priv->cur_tx)
193 avail = priv->dirty_tx - priv->cur_tx - 1;
195 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
200 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
204 if (priv->dirty_rx <= priv->cur_rx)
205 dirty = priv->cur_rx - priv->dirty_rx;
207 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
213 * stmmac_hw_fix_mac_speed - callback for speed selection
214 * @priv: driver private structure
215 * Description: on some platforms (e.g. ST), some HW system configuraton
216 * registers have to be set according to the link speed negotiated.
218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
220 struct phy_device *phydev = priv->phydev;
222 if (likely(priv->plat->fix_mac_speed))
223 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
227 * stmmac_enable_eee_mode - check and enter in LPI mode
228 * @priv: driver private structure
229 * Description: this function is to verify and enter in LPI mode in case of
232 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
234 /* Check and enter in LPI mode */
235 if ((priv->dirty_tx == priv->cur_tx) &&
236 (priv->tx_path_in_lpi_mode == false))
237 priv->hw->mac->set_eee_mode(priv->hw);
241 * stmmac_disable_eee_mode - disable and exit from LPI mode
242 * @priv: driver private structure
243 * Description: this function is to exit and disable EEE in case of
244 * LPI state is true. This is called by the xmit.
246 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
248 priv->hw->mac->reset_eee_mode(priv->hw);
249 del_timer_sync(&priv->eee_ctrl_timer);
250 priv->tx_path_in_lpi_mode = false;
254 * stmmac_eee_ctrl_timer - EEE TX SW timer.
257 * if there is no data transfer and if we are not in LPI state,
258 * then MAC Transmitter can be moved to LPI state.
260 static void stmmac_eee_ctrl_timer(unsigned long arg)
262 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
264 stmmac_enable_eee_mode(priv);
265 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
269 * stmmac_eee_init - init EEE
270 * @priv: driver private structure
272 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
273 * can also manage EEE, this function enable the LPI state and start related
276 bool stmmac_eee_init(struct stmmac_priv *priv)
278 char *phy_bus_name = priv->plat->phy_bus_name;
282 /* Using PCS we cannot dial with the phy registers at this stage
283 * so we do not support extra feature like EEE.
285 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
286 (priv->pcs == STMMAC_PCS_RTBI))
289 /* Never init EEE in case of a switch is attached */
290 if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
293 /* MAC core supports the EEE feature. */
294 if (priv->dma_cap.eee) {
295 int tx_lpi_timer = priv->tx_lpi_timer;
297 /* Check if the PHY supports EEE */
298 if (phy_init_eee(priv->phydev, 1)) {
299 /* To manage at run-time if the EEE cannot be supported
300 * anymore (for example because the lp caps have been
302 * In that case the driver disable own timers.
304 spin_lock_irqsave(&priv->lock, flags);
305 if (priv->eee_active) {
306 pr_debug("stmmac: disable EEE\n");
307 del_timer_sync(&priv->eee_ctrl_timer);
308 priv->hw->mac->set_eee_timer(priv->hw, 0,
311 priv->eee_active = 0;
312 spin_unlock_irqrestore(&priv->lock, flags);
315 /* Activate the EEE and start timers */
316 spin_lock_irqsave(&priv->lock, flags);
317 if (!priv->eee_active) {
318 priv->eee_active = 1;
319 setup_timer(&priv->eee_ctrl_timer,
320 stmmac_eee_ctrl_timer,
321 (unsigned long)priv);
322 mod_timer(&priv->eee_ctrl_timer,
323 STMMAC_LPI_T(eee_timer));
325 priv->hw->mac->set_eee_timer(priv->hw,
326 STMMAC_DEFAULT_LIT_LS,
329 /* Set HW EEE according to the speed */
330 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
333 spin_unlock_irqrestore(&priv->lock, flags);
335 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
341 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
342 * @priv: driver private structure
343 * @entry : descriptor index to be used.
344 * @skb : the socket buffer
346 * This function will read timestamp from the descriptor & pass it to stack.
347 * and also perform some sanity checks.
349 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
350 unsigned int entry, struct sk_buff *skb)
352 struct skb_shared_hwtstamps shhwtstamp;
356 if (!priv->hwts_tx_en)
359 /* exit if skb doesn't support hw tstamp */
360 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
364 desc = (priv->dma_etx + entry);
366 desc = (priv->dma_tx + entry);
368 /* check tx tstamp status */
369 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
372 /* get the valid tstamp */
373 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
375 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
376 shhwtstamp.hwtstamp = ns_to_ktime(ns);
377 /* pass tstamp to stack */
378 skb_tstamp_tx(skb, &shhwtstamp);
383 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
384 * @priv: driver private structure
385 * @entry : descriptor index to be used.
386 * @skb : the socket buffer
388 * This function will read received packet's timestamp from the descriptor
389 * and pass it to stack. It also perform some sanity checks.
391 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
392 unsigned int entry, struct sk_buff *skb)
394 struct skb_shared_hwtstamps *shhwtstamp = NULL;
398 if (!priv->hwts_rx_en)
402 desc = (priv->dma_erx + entry);
404 desc = (priv->dma_rx + entry);
406 /* exit if rx tstamp is not valid */
407 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
410 /* get valid tstamp */
411 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
412 shhwtstamp = skb_hwtstamps(skb);
413 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
414 shhwtstamp->hwtstamp = ns_to_ktime(ns);
418 * stmmac_hwtstamp_ioctl - control hardware timestamping.
419 * @dev: device pointer.
420 * @ifr: An IOCTL specefic structure, that can contain a pointer to
421 * a proprietary structure used to pass information to the driver.
423 * This function configures the MAC to enable/disable both outgoing(TX)
424 * and incoming(RX) packets time stamping based on user input.
426 * 0 on success and an appropriate -ve integer on failure.
428 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
430 struct stmmac_priv *priv = netdev_priv(dev);
431 struct hwtstamp_config config;
432 struct timespec64 now;
436 u32 ptp_over_ipv4_udp = 0;
437 u32 ptp_over_ipv6_udp = 0;
438 u32 ptp_over_ethernet = 0;
439 u32 snap_type_sel = 0;
440 u32 ts_master_en = 0;
445 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
446 netdev_alert(priv->dev, "No support for HW time stamping\n");
447 priv->hwts_tx_en = 0;
448 priv->hwts_rx_en = 0;
453 if (copy_from_user(&config, ifr->ifr_data,
454 sizeof(struct hwtstamp_config)))
457 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
458 __func__, config.flags, config.tx_type, config.rx_filter);
460 /* reserved for future extensions */
464 if (config.tx_type != HWTSTAMP_TX_OFF &&
465 config.tx_type != HWTSTAMP_TX_ON)
469 switch (config.rx_filter) {
470 case HWTSTAMP_FILTER_NONE:
471 /* time stamp no incoming packet at all */
472 config.rx_filter = HWTSTAMP_FILTER_NONE;
475 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
476 /* PTP v1, UDP, any kind of event packet */
477 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
478 /* take time stamp for all event messages */
479 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
481 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
482 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
485 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
486 /* PTP v1, UDP, Sync packet */
487 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
488 /* take time stamp for SYNC messages only */
489 ts_event_en = PTP_TCR_TSEVNTENA;
491 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
492 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
495 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
496 /* PTP v1, UDP, Delay_req packet */
497 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
498 /* take time stamp for Delay_Req messages only */
499 ts_master_en = PTP_TCR_TSMSTRENA;
500 ts_event_en = PTP_TCR_TSEVNTENA;
502 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
503 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
506 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
507 /* PTP v2, UDP, any kind of event packet */
508 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
509 ptp_v2 = PTP_TCR_TSVER2ENA;
510 /* take time stamp for all event messages */
511 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
513 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
514 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
517 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
518 /* PTP v2, UDP, Sync packet */
519 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
520 ptp_v2 = PTP_TCR_TSVER2ENA;
521 /* take time stamp for SYNC messages only */
522 ts_event_en = PTP_TCR_TSEVNTENA;
524 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
525 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
528 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
529 /* PTP v2, UDP, Delay_req packet */
530 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
531 ptp_v2 = PTP_TCR_TSVER2ENA;
532 /* take time stamp for Delay_Req messages only */
533 ts_master_en = PTP_TCR_TSMSTRENA;
534 ts_event_en = PTP_TCR_TSEVNTENA;
536 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
537 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
540 case HWTSTAMP_FILTER_PTP_V2_EVENT:
541 /* PTP v2/802.AS1 any layer, any kind of event packet */
542 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
543 ptp_v2 = PTP_TCR_TSVER2ENA;
544 /* take time stamp for all event messages */
545 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
547 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
548 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
549 ptp_over_ethernet = PTP_TCR_TSIPENA;
552 case HWTSTAMP_FILTER_PTP_V2_SYNC:
553 /* PTP v2/802.AS1, any layer, Sync packet */
554 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
555 ptp_v2 = PTP_TCR_TSVER2ENA;
556 /* take time stamp for SYNC messages only */
557 ts_event_en = PTP_TCR_TSEVNTENA;
559 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
560 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
561 ptp_over_ethernet = PTP_TCR_TSIPENA;
564 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
565 /* PTP v2/802.AS1, any layer, Delay_req packet */
566 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
567 ptp_v2 = PTP_TCR_TSVER2ENA;
568 /* take time stamp for Delay_Req messages only */
569 ts_master_en = PTP_TCR_TSMSTRENA;
570 ts_event_en = PTP_TCR_TSEVNTENA;
572 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
573 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
574 ptp_over_ethernet = PTP_TCR_TSIPENA;
577 case HWTSTAMP_FILTER_ALL:
578 /* time stamp any incoming packet */
579 config.rx_filter = HWTSTAMP_FILTER_ALL;
580 tstamp_all = PTP_TCR_TSENALL;
587 switch (config.rx_filter) {
588 case HWTSTAMP_FILTER_NONE:
589 config.rx_filter = HWTSTAMP_FILTER_NONE;
592 /* PTP v1, UDP, any kind of event packet */
593 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
597 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
598 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
600 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
601 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
603 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
604 tstamp_all | ptp_v2 | ptp_over_ethernet |
605 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
606 ts_master_en | snap_type_sel);
607 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
609 /* program Sub Second Increment reg */
610 sec_inc = priv->hw->ptp->config_sub_second_increment(
611 priv->ioaddr, priv->clk_ptp_rate);
612 temp = div_u64(1000000000ULL, sec_inc);
614 /* calculate default added value:
616 * addend = (2^32)/freq_div_ratio;
617 * where, freq_div_ratio = 1e9ns/sec_inc
619 temp = (u64)(temp << 32);
620 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
621 priv->hw->ptp->config_addend(priv->ioaddr,
622 priv->default_addend);
624 /* initialize system time */
625 ktime_get_real_ts64(&now);
627 /* lower 32 bits of tv_sec are safe until y2106 */
628 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
632 return copy_to_user(ifr->ifr_data, &config,
633 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
637 * stmmac_init_ptp - init PTP
638 * @priv: driver private structure
639 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
640 * This is done by looking at the HW cap. register.
641 * This function also registers the ptp driver.
643 static int stmmac_init_ptp(struct stmmac_priv *priv)
645 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
648 /* Fall-back to main clock in case of no PTP ref is passed */
649 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
650 if (IS_ERR(priv->clk_ptp_ref)) {
651 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
652 priv->clk_ptp_ref = NULL;
654 clk_prepare_enable(priv->clk_ptp_ref);
655 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
659 if (priv->dma_cap.atime_stamp && priv->extend_desc)
662 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
663 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
665 if (netif_msg_hw(priv) && priv->adv_ts)
666 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
668 priv->hw->ptp = &stmmac_ptp;
669 priv->hwts_tx_en = 0;
670 priv->hwts_rx_en = 0;
672 return stmmac_ptp_register(priv);
675 static void stmmac_release_ptp(struct stmmac_priv *priv)
677 if (priv->clk_ptp_ref)
678 clk_disable_unprepare(priv->clk_ptp_ref);
679 stmmac_ptp_unregister(priv);
683 * stmmac_adjust_link - adjusts the link parameters
684 * @dev: net device structure
685 * Description: this is the helper called by the physical abstraction layer
686 * drivers to communicate the phy link status. According the speed and duplex
687 * this driver can invoke registered glue-logic as well.
688 * It also invoke the eee initialization because it could happen when switch
689 * on different networks (that are eee capable).
691 static void stmmac_adjust_link(struct net_device *dev)
693 struct stmmac_priv *priv = netdev_priv(dev);
694 struct phy_device *phydev = priv->phydev;
697 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
702 spin_lock_irqsave(&priv->lock, flags);
705 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
707 /* Now we make sure that we can be in full duplex mode.
708 * If not, we operate in half-duplex mode. */
709 if (phydev->duplex != priv->oldduplex) {
711 if (!(phydev->duplex))
712 ctrl &= ~priv->hw->link.duplex;
714 ctrl |= priv->hw->link.duplex;
715 priv->oldduplex = phydev->duplex;
717 /* Flow Control operation */
719 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
722 if (phydev->speed != priv->speed) {
724 switch (phydev->speed) {
726 if (likely(priv->plat->has_gmac))
727 ctrl &= ~priv->hw->link.port;
728 stmmac_hw_fix_mac_speed(priv);
732 if (priv->plat->has_gmac) {
733 ctrl |= priv->hw->link.port;
734 if (phydev->speed == SPEED_100) {
735 ctrl |= priv->hw->link.speed;
737 ctrl &= ~(priv->hw->link.speed);
740 ctrl &= ~priv->hw->link.port;
742 stmmac_hw_fix_mac_speed(priv);
745 if (netif_msg_link(priv))
746 pr_warn("%s: Speed (%d) not 10/100\n",
747 dev->name, phydev->speed);
751 priv->speed = phydev->speed;
754 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
756 if (!priv->oldlink) {
760 } else if (priv->oldlink) {
764 priv->oldduplex = -1;
767 if (new_state && netif_msg_link(priv))
768 phy_print_status(phydev);
770 spin_unlock_irqrestore(&priv->lock, flags);
772 /* At this stage, it could be needed to setup the EEE or adjust some
773 * MAC related HW registers.
775 priv->eee_enabled = stmmac_eee_init(priv);
779 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
780 * @priv: driver private structure
781 * Description: this is to verify if the HW supports the PCS.
782 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
783 * configured for the TBI, RTBI, or SGMII PHY interface.
785 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
787 int interface = priv->plat->interface;
789 if (priv->dma_cap.pcs) {
790 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
791 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
792 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
793 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
794 pr_debug("STMMAC: PCS RGMII support enable\n");
795 priv->pcs = STMMAC_PCS_RGMII;
796 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
797 pr_debug("STMMAC: PCS SGMII support enable\n");
798 priv->pcs = STMMAC_PCS_SGMII;
804 * stmmac_init_phy - PHY initialization
805 * @dev: net device structure
806 * Description: it initializes the driver's PHY state, and attaches the PHY
811 static int stmmac_init_phy(struct net_device *dev)
813 struct stmmac_priv *priv = netdev_priv(dev);
814 struct phy_device *phydev;
815 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
816 char bus_id[MII_BUS_ID_SIZE];
817 int interface = priv->plat->interface;
818 int max_speed = priv->plat->max_speed;
821 priv->oldduplex = -1;
823 if (priv->plat->phy_node) {
824 phydev = of_phy_connect(dev, priv->plat->phy_node,
825 &stmmac_adjust_link, 0, interface);
827 if (priv->plat->phy_bus_name)
828 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
829 priv->plat->phy_bus_name, priv->plat->bus_id);
831 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
834 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
835 priv->plat->phy_addr);
836 pr_debug("stmmac_init_phy: trying to attach to %s\n",
839 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
843 if (IS_ERR_OR_NULL(phydev)) {
844 pr_err("%s: Could not attach to PHY\n", dev->name);
848 return PTR_ERR(phydev);
851 /* Stop Advertising 1000BASE Capability if interface is not GMII */
852 if ((interface == PHY_INTERFACE_MODE_MII) ||
853 (interface == PHY_INTERFACE_MODE_RMII) ||
854 (max_speed < 1000 && max_speed > 0))
855 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
856 SUPPORTED_1000baseT_Full);
859 * Broken HW is sometimes missing the pull-up resistor on the
860 * MDIO line, which results in reads to non-existent devices returning
861 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
863 * Note: phydev->phy_id is the result of reading the UID PHY registers.
865 if (!priv->plat->phy_node && phydev->phy_id == 0) {
866 phy_disconnect(phydev);
869 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
870 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
872 priv->phydev = phydev;
878 * stmmac_display_ring - display ring
879 * @head: pointer to the head of the ring passed.
880 * @size: size of the ring.
881 * @extend_desc: to verify if extended descriptors are used.
882 * Description: display the control/status and buffer descriptors.
884 static void stmmac_display_ring(void *head, int size, int extend_desc)
887 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
888 struct dma_desc *p = (struct dma_desc *)head;
890 for (i = 0; i < size; i++) {
894 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
895 i, (unsigned int)virt_to_phys(ep),
896 (unsigned int)x, (unsigned int)(x >> 32),
897 ep->basic.des2, ep->basic.des3);
901 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
902 i, (unsigned int)virt_to_phys(p),
903 (unsigned int)x, (unsigned int)(x >> 32),
911 static void stmmac_display_rings(struct stmmac_priv *priv)
913 if (priv->extend_desc) {
914 pr_info("Extended RX descriptor ring:\n");
915 stmmac_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1);
916 pr_info("Extended TX descriptor ring:\n");
917 stmmac_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1);
919 pr_info("RX descriptor ring:\n");
920 stmmac_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0);
921 pr_info("TX descriptor ring:\n");
922 stmmac_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0);
926 static int stmmac_set_bfsize(int mtu, int bufsize)
930 if (mtu >= BUF_SIZE_4KiB)
932 else if (mtu >= BUF_SIZE_2KiB)
934 else if (mtu > DEFAULT_BUFSIZE)
937 ret = DEFAULT_BUFSIZE;
943 * stmmac_clear_descriptors - clear descriptors
944 * @priv: driver private structure
945 * Description: this function is called to clear the tx and rx descriptors
946 * in case of both basic and extended descriptors are used.
948 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
952 /* Clear the Rx/Tx descriptors */
953 for (i = 0; i < DMA_RX_SIZE; i++)
954 if (priv->extend_desc)
955 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
956 priv->use_riwt, priv->mode,
957 (i == DMA_RX_SIZE - 1));
959 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
960 priv->use_riwt, priv->mode,
961 (i == DMA_RX_SIZE - 1));
962 for (i = 0; i < DMA_TX_SIZE; i++)
963 if (priv->extend_desc)
964 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
966 (i == DMA_TX_SIZE - 1));
968 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
970 (i == DMA_TX_SIZE - 1));
974 * stmmac_init_rx_buffers - init the RX descriptor buffer.
975 * @priv: driver private structure
976 * @p: descriptor pointer
977 * @i: descriptor index
979 * Description: this function is called to allocate a receive buffer, perform
980 * the DMA mapping and init the descriptor.
982 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
987 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
989 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
992 priv->rx_skbuff[i] = skb;
993 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
996 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
997 pr_err("%s: DMA mapping error\n", __func__);
998 dev_kfree_skb_any(skb);
1002 p->des2 = priv->rx_skbuff_dma[i];
1004 if ((priv->hw->mode->init_desc3) &&
1005 (priv->dma_buf_sz == BUF_SIZE_16KiB))
1006 priv->hw->mode->init_desc3(p);
1011 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1013 if (priv->rx_skbuff[i]) {
1014 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1015 priv->dma_buf_sz, DMA_FROM_DEVICE);
1016 dev_kfree_skb_any(priv->rx_skbuff[i]);
1018 priv->rx_skbuff[i] = NULL;
1022 * init_dma_desc_rings - init the RX/TX descriptor rings
1023 * @dev: net device structure
1025 * Description: this function initializes the DMA RX/TX descriptors
1026 * and allocates the socket buffers. It suppors the chained and ring
1029 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1032 struct stmmac_priv *priv = netdev_priv(dev);
1033 unsigned int bfsize = 0;
1036 if (priv->hw->mode->set_16kib_bfsize)
1037 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1039 if (bfsize < BUF_SIZE_16KiB)
1040 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1042 priv->dma_buf_sz = bfsize;
1044 if (netif_msg_probe(priv)) {
1045 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1046 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1048 /* RX INITIALIZATION */
1049 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1051 for (i = 0; i < DMA_RX_SIZE; i++) {
1053 if (priv->extend_desc)
1054 p = &((priv->dma_erx + i)->basic);
1056 p = priv->dma_rx + i;
1058 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1060 goto err_init_rx_buffers;
1062 if (netif_msg_probe(priv))
1063 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1064 priv->rx_skbuff[i]->data,
1065 (unsigned int)priv->rx_skbuff_dma[i]);
1068 priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1071 /* Setup the chained descriptor addresses */
1072 if (priv->mode == STMMAC_CHAIN_MODE) {
1073 if (priv->extend_desc) {
1074 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1076 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1079 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1081 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1086 /* TX INITIALIZATION */
1087 for (i = 0; i < DMA_TX_SIZE; i++) {
1089 if (priv->extend_desc)
1090 p = &((priv->dma_etx + i)->basic);
1092 p = priv->dma_tx + i;
1094 priv->tx_skbuff_dma[i].buf = 0;
1095 priv->tx_skbuff_dma[i].map_as_page = false;
1096 priv->tx_skbuff_dma[i].len = 0;
1097 priv->tx_skbuff[i] = NULL;
1102 netdev_reset_queue(priv->dev);
1104 stmmac_clear_descriptors(priv);
1106 if (netif_msg_hw(priv))
1107 stmmac_display_rings(priv);
1110 err_init_rx_buffers:
1112 stmmac_free_rx_buffers(priv, i);
1116 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1120 for (i = 0; i < DMA_RX_SIZE; i++)
1121 stmmac_free_rx_buffers(priv, i);
1124 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1128 for (i = 0; i < DMA_TX_SIZE; i++) {
1131 if (priv->extend_desc)
1132 p = &((priv->dma_etx + i)->basic);
1134 p = priv->dma_tx + i;
1136 if (priv->tx_skbuff_dma[i].buf) {
1137 if (priv->tx_skbuff_dma[i].map_as_page)
1138 dma_unmap_page(priv->device,
1139 priv->tx_skbuff_dma[i].buf,
1140 priv->tx_skbuff_dma[i].len,
1143 dma_unmap_single(priv->device,
1144 priv->tx_skbuff_dma[i].buf,
1145 priv->tx_skbuff_dma[i].len,
1149 if (priv->tx_skbuff[i] != NULL) {
1150 dev_kfree_skb_any(priv->tx_skbuff[i]);
1151 priv->tx_skbuff[i] = NULL;
1152 priv->tx_skbuff_dma[i].buf = 0;
1153 priv->tx_skbuff_dma[i].map_as_page = false;
1159 * alloc_dma_desc_resources - alloc TX/RX resources.
1160 * @priv: private structure
1161 * Description: according to which descriptor can be used (extend or basic)
1162 * this function allocates the resources for TX and RX paths. In case of
1163 * reception, for example, it pre-allocated the RX socket buffer in order to
1164 * allow zero-copy mechanism.
1166 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1170 priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1172 if (!priv->rx_skbuff_dma)
1175 priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1177 if (!priv->rx_skbuff)
1180 priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1181 sizeof(*priv->tx_skbuff_dma),
1183 if (!priv->tx_skbuff_dma)
1184 goto err_tx_skbuff_dma;
1186 priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1188 if (!priv->tx_skbuff)
1191 if (priv->extend_desc) {
1192 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1200 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1205 if (!priv->dma_etx) {
1206 dma_free_coherent(priv->device, DMA_RX_SIZE *
1207 sizeof(struct dma_extended_desc),
1208 priv->dma_erx, priv->dma_rx_phy);
1212 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1213 sizeof(struct dma_desc),
1219 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1220 sizeof(struct dma_desc),
1223 if (!priv->dma_tx) {
1224 dma_free_coherent(priv->device, DMA_RX_SIZE *
1225 sizeof(struct dma_desc),
1226 priv->dma_rx, priv->dma_rx_phy);
1234 kfree(priv->tx_skbuff);
1236 kfree(priv->tx_skbuff_dma);
1238 kfree(priv->rx_skbuff);
1240 kfree(priv->rx_skbuff_dma);
1244 static void free_dma_desc_resources(struct stmmac_priv *priv)
1246 /* Release the DMA TX/RX socket buffers */
1247 dma_free_rx_skbufs(priv);
1248 dma_free_tx_skbufs(priv);
1250 /* Free DMA regions of consistent memory previously allocated */
1251 if (!priv->extend_desc) {
1252 dma_free_coherent(priv->device,
1253 DMA_TX_SIZE * sizeof(struct dma_desc),
1254 priv->dma_tx, priv->dma_tx_phy);
1255 dma_free_coherent(priv->device,
1256 DMA_RX_SIZE * sizeof(struct dma_desc),
1257 priv->dma_rx, priv->dma_rx_phy);
1259 dma_free_coherent(priv->device, DMA_TX_SIZE *
1260 sizeof(struct dma_extended_desc),
1261 priv->dma_etx, priv->dma_tx_phy);
1262 dma_free_coherent(priv->device, DMA_RX_SIZE *
1263 sizeof(struct dma_extended_desc),
1264 priv->dma_erx, priv->dma_rx_phy);
1266 kfree(priv->rx_skbuff_dma);
1267 kfree(priv->rx_skbuff);
1268 kfree(priv->tx_skbuff_dma);
1269 kfree(priv->tx_skbuff);
1273 * stmmac_dma_operation_mode - HW DMA operation mode
1274 * @priv: driver private structure
1275 * Description: it is used for configuring the DMA operation mode register in
1276 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1278 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1280 int rxfifosz = priv->plat->rx_fifo_size;
1282 if (priv->plat->force_thresh_dma_mode)
1283 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1284 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1286 * In case of GMAC, SF mode can be enabled
1287 * to perform the TX COE in HW. This depends on:
1288 * 1) TX COE if actually supported
1289 * 2) There is no bugged Jumbo frame support
1290 * that needs to not insert csum in the TDES.
1292 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1294 priv->xstats.threshold = SF_DMA_MODE;
1296 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1301 * stmmac_tx_clean - to manage the transmission completion
1302 * @priv: driver private structure
1303 * Description: it reclaims the transmit resources after transmission completes.
1305 static void stmmac_tx_clean(struct stmmac_priv *priv)
1307 unsigned int bytes_compl = 0, pkts_compl = 0;
1308 unsigned int entry = priv->dirty_tx;
1310 spin_lock(&priv->tx_lock);
1312 priv->xstats.tx_clean++;
1314 while (entry != priv->cur_tx) {
1316 struct sk_buff *skb = priv->tx_skbuff[entry];
1319 if (priv->extend_desc)
1320 p = (struct dma_desc *)(priv->dma_etx + entry);
1322 p = priv->dma_tx + entry;
1324 /* Check if the descriptor is owned by the DMA. */
1325 if (priv->hw->desc->get_tx_owner(p))
1328 /* Verify tx error by looking at the last segment. */
1329 last = priv->hw->desc->get_tx_ls(p);
1332 priv->hw->desc->tx_status(&priv->dev->stats,
1335 if (likely(tx_error == 0)) {
1336 priv->dev->stats.tx_packets++;
1337 priv->xstats.tx_pkt_n++;
1339 priv->dev->stats.tx_errors++;
1341 stmmac_get_tx_hwtstamp(priv, entry, skb);
1343 if (netif_msg_tx_done(priv))
1344 pr_debug("%s: curr %d, dirty %d\n", __func__,
1345 priv->cur_tx, priv->dirty_tx);
1347 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1348 if (priv->tx_skbuff_dma[entry].map_as_page)
1349 dma_unmap_page(priv->device,
1350 priv->tx_skbuff_dma[entry].buf,
1351 priv->tx_skbuff_dma[entry].len,
1354 dma_unmap_single(priv->device,
1355 priv->tx_skbuff_dma[entry].buf,
1356 priv->tx_skbuff_dma[entry].len,
1358 priv->tx_skbuff_dma[entry].buf = 0;
1359 priv->tx_skbuff_dma[entry].map_as_page = false;
1361 priv->hw->mode->clean_desc3(priv, p);
1363 if (likely(skb != NULL)) {
1365 bytes_compl += skb->len;
1366 dev_consume_skb_any(skb);
1367 priv->tx_skbuff[entry] = NULL;
1370 priv->hw->desc->release_tx_desc(p, priv->mode);
1372 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1373 priv->dirty_tx = entry;
1376 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1378 if (unlikely(netif_queue_stopped(priv->dev) &&
1379 stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1380 netif_tx_lock(priv->dev);
1381 if (netif_queue_stopped(priv->dev) &&
1382 stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
1383 if (netif_msg_tx_done(priv))
1384 pr_debug("%s: restart transmit\n", __func__);
1385 netif_wake_queue(priv->dev);
1387 netif_tx_unlock(priv->dev);
1390 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1391 stmmac_enable_eee_mode(priv);
1392 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1394 spin_unlock(&priv->tx_lock);
1397 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1399 priv->hw->dma->enable_dma_irq(priv->ioaddr);
1402 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1404 priv->hw->dma->disable_dma_irq(priv->ioaddr);
1408 * stmmac_tx_err - to manage the tx error
1409 * @priv: driver private structure
1410 * Description: it cleans the descriptors and restarts the transmission
1411 * in case of transmission errors.
1413 static void stmmac_tx_err(struct stmmac_priv *priv)
1416 netif_stop_queue(priv->dev);
1418 priv->hw->dma->stop_tx(priv->ioaddr);
1419 dma_free_tx_skbufs(priv);
1420 for (i = 0; i < DMA_TX_SIZE; i++)
1421 if (priv->extend_desc)
1422 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1424 (i == DMA_TX_SIZE - 1));
1426 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1428 (i == DMA_TX_SIZE - 1));
1431 netdev_reset_queue(priv->dev);
1432 priv->hw->dma->start_tx(priv->ioaddr);
1434 priv->dev->stats.tx_errors++;
1435 netif_wake_queue(priv->dev);
1439 * stmmac_dma_interrupt - DMA ISR
1440 * @priv: driver private structure
1441 * Description: this is the DMA ISR. It is called by the main ISR.
1442 * It calls the dwmac dma routine and schedule poll method in case of some
1445 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1448 int rxfifosz = priv->plat->rx_fifo_size;
1450 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1451 if (likely((status & handle_rx)) || (status & handle_tx)) {
1452 if (likely(napi_schedule_prep(&priv->napi))) {
1453 stmmac_disable_dma_irq(priv);
1454 __napi_schedule(&priv->napi);
1457 if (unlikely(status & tx_hard_error_bump_tc)) {
1458 /* Try to bump up the dma threshold on this failure */
1459 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1462 if (priv->plat->force_thresh_dma_mode)
1463 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1466 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1467 SF_DMA_MODE, rxfifosz);
1468 priv->xstats.threshold = tc;
1470 } else if (unlikely(status == tx_hard_error))
1471 stmmac_tx_err(priv);
1475 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1476 * @priv: driver private structure
1477 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1479 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1481 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1482 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1484 dwmac_mmc_intr_all_mask(priv->ioaddr);
1486 if (priv->dma_cap.rmon) {
1487 dwmac_mmc_ctrl(priv->ioaddr, mode);
1488 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1490 pr_info(" No MAC Management Counters available\n");
1494 * stmmac_get_synopsys_id - return the SYINID.
1495 * @priv: driver private structure
1496 * Description: this simple function is to decode and return the SYINID
1497 * starting from the HW core register.
1499 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1501 u32 hwid = priv->hw->synopsys_uid;
1503 /* Check Synopsys Id (not available on old chips) */
1505 u32 uid = ((hwid & 0x0000ff00) >> 8);
1506 u32 synid = (hwid & 0x000000ff);
1508 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1517 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1518 * @priv: driver private structure
1519 * Description: select the Enhanced/Alternate or Normal descriptors.
1520 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1521 * supported by the HW capability register.
1523 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1525 if (priv->plat->enh_desc) {
1526 pr_info(" Enhanced/Alternate descriptors\n");
1528 /* GMAC older than 3.50 has no extended descriptors */
1529 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1530 pr_info("\tEnabled extended descriptors\n");
1531 priv->extend_desc = 1;
1533 pr_warn("Extended descriptors not supported\n");
1535 priv->hw->desc = &enh_desc_ops;
1537 pr_info(" Normal descriptors\n");
1538 priv->hw->desc = &ndesc_ops;
1543 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1544 * @priv: driver private structure
1546 * new GMAC chip generations have a new register to indicate the
1547 * presence of the optional feature/functions.
1548 * This can be also used to override the value passed through the
1549 * platform and necessary for old MAC10/100 and GMAC chips.
1551 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1555 if (priv->hw->dma->get_hw_feature) {
1556 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1558 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1559 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1560 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1561 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1562 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1563 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1564 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1565 priv->dma_cap.pmt_remote_wake_up =
1566 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1567 priv->dma_cap.pmt_magic_frame =
1568 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1570 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1571 /* IEEE 1588-2002 */
1572 priv->dma_cap.time_stamp =
1573 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1574 /* IEEE 1588-2008 */
1575 priv->dma_cap.atime_stamp =
1576 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1577 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1578 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1579 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1580 /* TX and RX csum */
1581 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1582 priv->dma_cap.rx_coe_type1 =
1583 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1584 priv->dma_cap.rx_coe_type2 =
1585 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1586 priv->dma_cap.rxfifo_over_2048 =
1587 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1588 /* TX and RX number of channels */
1589 priv->dma_cap.number_rx_channel =
1590 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1591 priv->dma_cap.number_tx_channel =
1592 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1593 /* Alternate (enhanced) DESC mode */
1594 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1601 * stmmac_check_ether_addr - check if the MAC addr is valid
1602 * @priv: driver private structure
1604 * it is to verify if the MAC address is valid, in case of failures it
1605 * generates a random MAC address
1607 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1609 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1610 priv->hw->mac->get_umac_addr(priv->hw,
1611 priv->dev->dev_addr, 0);
1612 if (!is_valid_ether_addr(priv->dev->dev_addr))
1613 eth_hw_addr_random(priv->dev);
1614 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1615 priv->dev->dev_addr);
1620 * stmmac_init_dma_engine - DMA init.
1621 * @priv: driver private structure
1623 * It inits the DMA invoking the specific MAC/GMAC callback.
1624 * Some DMA parameters can be passed from the platform;
1625 * in case of these are not passed a default is kept for the MAC or GMAC.
1627 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1629 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
1630 int mixed_burst = 0;
1634 if (priv->plat->dma_cfg) {
1635 pbl = priv->plat->dma_cfg->pbl;
1636 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1637 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1638 aal = priv->plat->dma_cfg->aal;
1641 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1644 ret = priv->hw->dma->reset(priv->ioaddr);
1646 dev_err(priv->device, "Failed to reset the dma\n");
1650 priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1651 aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
1653 if ((priv->synopsys_id >= DWMAC_CORE_3_50) &&
1654 (priv->plat->axi && priv->hw->dma->axi))
1655 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1661 * stmmac_tx_timer - mitigation sw timer for tx.
1662 * @data: data pointer
1664 * This is the timer handler to directly invoke the stmmac_tx_clean.
1666 static void stmmac_tx_timer(unsigned long data)
1668 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1670 stmmac_tx_clean(priv);
1674 * stmmac_init_tx_coalesce - init tx mitigation options.
1675 * @priv: driver private structure
1677 * This inits the transmit coalesce parameters: i.e. timer rate,
1678 * timer handler and default threshold used for enabling the
1679 * interrupt on completion bit.
1681 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1683 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1684 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1685 init_timer(&priv->txtimer);
1686 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1687 priv->txtimer.data = (unsigned long)priv;
1688 priv->txtimer.function = stmmac_tx_timer;
1689 add_timer(&priv->txtimer);
1693 * stmmac_hw_setup - setup mac in a usable state.
1694 * @dev : pointer to the device structure.
1696 * this is the main function to setup the HW in a usable state because the
1697 * dma engine is reset, the core registers are configured (e.g. AXI,
1698 * Checksum features, timers). The DMA is ready to start receiving and
1701 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1704 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1706 struct stmmac_priv *priv = netdev_priv(dev);
1709 /* DMA initialization and SW reset */
1710 ret = stmmac_init_dma_engine(priv);
1712 pr_err("%s: DMA engine initialization failed\n", __func__);
1716 /* Copy the MAC addr into the HW */
1717 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1719 /* If required, perform hw setup of the bus. */
1720 if (priv->plat->bus_setup)
1721 priv->plat->bus_setup(priv->ioaddr);
1723 /* Initialize the MAC Core */
1724 priv->hw->mac->core_init(priv->hw, dev->mtu);
1726 ret = priv->hw->mac->rx_ipc(priv->hw);
1728 pr_warn(" RX IPC Checksum Offload disabled\n");
1729 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1730 priv->hw->rx_csum = 0;
1733 /* Enable the MAC Rx/Tx */
1734 stmmac_set_mac(priv->ioaddr, true);
1736 /* Set the HW DMA mode and the COE */
1737 stmmac_dma_operation_mode(priv);
1739 stmmac_mmc_setup(priv);
1742 ret = stmmac_init_ptp(priv);
1743 if (ret && ret != -EOPNOTSUPP)
1744 pr_warn("%s: failed PTP initialisation\n", __func__);
1747 #ifdef CONFIG_DEBUG_FS
1748 ret = stmmac_init_fs(dev);
1750 pr_warn("%s: failed debugFS registration\n", __func__);
1752 /* Start the ball rolling... */
1753 pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1754 priv->hw->dma->start_tx(priv->ioaddr);
1755 priv->hw->dma->start_rx(priv->ioaddr);
1757 /* Dump DMA/MAC registers */
1758 if (netif_msg_hw(priv)) {
1759 priv->hw->mac->dump_regs(priv->hw);
1760 priv->hw->dma->dump_regs(priv->ioaddr);
1762 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1764 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1765 priv->rx_riwt = MAX_DMA_RIWT;
1766 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1769 if (priv->pcs && priv->hw->mac->ctrl_ane)
1770 priv->hw->mac->ctrl_ane(priv->hw, 0);
1776 * stmmac_open - open entry point of the driver
1777 * @dev : pointer to the device structure.
1779 * This function is the open entry point of the driver.
1781 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1784 static int stmmac_open(struct net_device *dev)
1786 struct stmmac_priv *priv = netdev_priv(dev);
1789 stmmac_check_ether_addr(priv);
1791 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1792 priv->pcs != STMMAC_PCS_RTBI) {
1793 ret = stmmac_init_phy(dev);
1795 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1801 /* Extra statistics */
1802 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1803 priv->xstats.threshold = tc;
1805 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1807 ret = alloc_dma_desc_resources(priv);
1809 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1810 goto dma_desc_error;
1813 ret = init_dma_desc_rings(dev, GFP_KERNEL);
1815 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1819 ret = stmmac_hw_setup(dev, true);
1821 pr_err("%s: Hw setup failed\n", __func__);
1825 stmmac_init_tx_coalesce(priv);
1828 phy_start(priv->phydev);
1830 /* Request the IRQ lines */
1831 ret = request_irq(dev->irq, stmmac_interrupt,
1832 IRQF_SHARED, dev->name, dev);
1833 if (unlikely(ret < 0)) {
1834 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1835 __func__, dev->irq, ret);
1839 /* Request the Wake IRQ in case of another line is used for WoL */
1840 if (priv->wol_irq != dev->irq) {
1841 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1842 IRQF_SHARED, dev->name, dev);
1843 if (unlikely(ret < 0)) {
1844 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1845 __func__, priv->wol_irq, ret);
1850 /* Request the IRQ lines */
1851 if (priv->lpi_irq > 0) {
1852 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1854 if (unlikely(ret < 0)) {
1855 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1856 __func__, priv->lpi_irq, ret);
1861 napi_enable(&priv->napi);
1862 netif_start_queue(dev);
1867 if (priv->wol_irq != dev->irq)
1868 free_irq(priv->wol_irq, dev);
1870 free_irq(dev->irq, dev);
1873 free_dma_desc_resources(priv);
1876 phy_disconnect(priv->phydev);
1882 * stmmac_release - close entry point of the driver
1883 * @dev : device pointer.
1885 * This is the stop entry point of the driver.
1887 static int stmmac_release(struct net_device *dev)
1889 struct stmmac_priv *priv = netdev_priv(dev);
1891 if (priv->eee_enabled)
1892 del_timer_sync(&priv->eee_ctrl_timer);
1894 /* Stop and disconnect the PHY */
1896 phy_stop(priv->phydev);
1897 phy_disconnect(priv->phydev);
1898 priv->phydev = NULL;
1901 netif_stop_queue(dev);
1903 napi_disable(&priv->napi);
1905 del_timer_sync(&priv->txtimer);
1907 /* Free the IRQ lines */
1908 free_irq(dev->irq, dev);
1909 if (priv->wol_irq != dev->irq)
1910 free_irq(priv->wol_irq, dev);
1911 if (priv->lpi_irq > 0)
1912 free_irq(priv->lpi_irq, dev);
1914 /* Stop TX/RX DMA and clear the descriptors */
1915 priv->hw->dma->stop_tx(priv->ioaddr);
1916 priv->hw->dma->stop_rx(priv->ioaddr);
1918 /* Release and free the Rx/Tx resources */
1919 free_dma_desc_resources(priv);
1921 /* Disable the MAC Rx/Tx */
1922 stmmac_set_mac(priv->ioaddr, false);
1924 netif_carrier_off(dev);
1926 #ifdef CONFIG_DEBUG_FS
1927 stmmac_exit_fs(dev);
1930 stmmac_release_ptp(priv);
1936 * stmmac_xmit - Tx entry point of the driver
1937 * @skb : the socket buffer
1938 * @dev : device pointer
1939 * Description : this is the tx entry point of the driver.
1940 * It programs the chain or the ring and supports oversized frames
1943 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1945 struct stmmac_priv *priv = netdev_priv(dev);
1947 int i, csum_insertion = 0, is_jumbo = 0;
1948 int nfrags = skb_shinfo(skb)->nr_frags;
1949 struct dma_desc *desc, *first;
1950 unsigned int nopaged_len = skb_headlen(skb);
1951 unsigned int enh_desc = priv->plat->enh_desc;
1953 spin_lock(&priv->tx_lock);
1955 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1956 spin_unlock(&priv->tx_lock);
1957 if (!netif_queue_stopped(dev)) {
1958 netif_stop_queue(dev);
1959 /* This is a hard error, log it. */
1960 pr_err("%s: Tx Ring full when queue awake\n", __func__);
1962 return NETDEV_TX_BUSY;
1965 if (priv->tx_path_in_lpi_mode)
1966 stmmac_disable_eee_mode(priv);
1968 entry = priv->cur_tx;
1971 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1973 if (priv->extend_desc)
1974 desc = (struct dma_desc *)(priv->dma_etx + entry);
1976 desc = priv->dma_tx + entry;
1980 /* To program the descriptors according to the size of the frame */
1982 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1984 if (likely(!is_jumbo)) {
1985 desc->des2 = dma_map_single(priv->device, skb->data,
1986 nopaged_len, DMA_TO_DEVICE);
1987 if (dma_mapping_error(priv->device, desc->des2))
1989 priv->tx_skbuff_dma[entry].buf = desc->des2;
1990 priv->tx_skbuff_dma[entry].len = nopaged_len;
1991 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1992 csum_insertion, priv->mode);
1995 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1996 if (unlikely(entry < 0))
2000 for (i = 0; i < nfrags; i++) {
2001 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2002 int len = skb_frag_size(frag);
2004 priv->tx_skbuff[entry] = NULL;
2005 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2007 if (priv->extend_desc)
2008 desc = (struct dma_desc *)(priv->dma_etx + entry);
2010 desc = priv->dma_tx + entry;
2012 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2014 if (dma_mapping_error(priv->device, desc->des2))
2015 goto dma_map_err; /* should reuse desc w/o issues */
2017 priv->tx_skbuff_dma[entry].buf = desc->des2;
2018 priv->tx_skbuff_dma[entry].map_as_page = true;
2019 priv->tx_skbuff_dma[entry].len = len;
2020 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2023 priv->hw->desc->set_tx_owner(desc);
2027 priv->tx_skbuff[entry] = skb;
2029 /* Finalize the latest segment. */
2030 priv->hw->desc->close_tx_desc(desc);
2033 /* According to the coalesce parameter the IC bit for the latest
2034 * segment could be reset and the timer re-started to invoke the
2035 * stmmac_tx function. This approach takes care about the fragments.
2037 priv->tx_count_frames += nfrags + 1;
2038 if (priv->tx_coal_frames > priv->tx_count_frames) {
2039 priv->hw->desc->clear_tx_ic(desc);
2040 priv->xstats.tx_reset_ic_bit++;
2041 mod_timer(&priv->txtimer,
2042 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2044 priv->tx_count_frames = 0;
2046 /* To avoid raise condition */
2047 priv->hw->desc->set_tx_owner(first);
2050 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2052 priv->cur_tx = entry;
2054 if (netif_msg_pktdata(priv)) {
2055 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2056 __func__, (priv->cur_tx % DMA_TX_SIZE),
2057 (priv->dirty_tx % DMA_TX_SIZE), entry, first, nfrags);
2059 if (priv->extend_desc)
2060 stmmac_display_ring((void *)priv->dma_etx,
2063 stmmac_display_ring((void *)priv->dma_tx,
2066 pr_debug(">>> frame to be transmitted: ");
2067 print_pkt(skb->data, skb->len);
2069 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2070 if (netif_msg_hw(priv))
2071 pr_debug("%s: stop transmitted packets\n", __func__);
2072 netif_stop_queue(dev);
2075 dev->stats.tx_bytes += skb->len;
2077 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2078 priv->hwts_tx_en)) {
2079 /* declare that device is doing timestamping */
2080 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2081 priv->hw->desc->enable_tx_timestamp(first);
2084 if (!priv->hwts_tx_en)
2085 skb_tx_timestamp(skb);
2087 netdev_sent_queue(dev, skb->len);
2088 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2090 spin_unlock(&priv->tx_lock);
2091 return NETDEV_TX_OK;
2094 spin_unlock(&priv->tx_lock);
2095 dev_err(priv->device, "Tx dma map failed\n");
2097 priv->dev->stats.tx_dropped++;
2098 return NETDEV_TX_OK;
2101 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2103 struct ethhdr *ehdr;
2106 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2107 NETIF_F_HW_VLAN_CTAG_RX &&
2108 !__vlan_get_tag(skb, &vlanid)) {
2109 /* pop the vlan tag */
2110 ehdr = (struct ethhdr *)skb->data;
2111 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2112 skb_pull(skb, VLAN_HLEN);
2113 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2119 * stmmac_rx_refill - refill used skb preallocated buffers
2120 * @priv: driver private structure
2121 * Description : this is to reallocate the skb for the reception process
2122 * that is based on zero-copy.
2124 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2126 int bfsize = priv->dma_buf_sz;
2127 unsigned int entry = priv->dirty_rx;
2128 int dirty = stmmac_rx_dirty(priv);
2130 while (dirty-- > 0) {
2133 if (priv->extend_desc)
2134 p = (struct dma_desc *)(priv->dma_erx + entry);
2136 p = priv->dma_rx + entry;
2138 if (likely(priv->rx_skbuff[entry] == NULL)) {
2139 struct sk_buff *skb;
2141 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2143 if (unlikely(skb == NULL))
2146 priv->rx_skbuff[entry] = skb;
2147 priv->rx_skbuff_dma[entry] =
2148 dma_map_single(priv->device, skb->data, bfsize,
2150 if (dma_mapping_error(priv->device,
2151 priv->rx_skbuff_dma[entry])) {
2152 dev_err(priv->device, "Rx dma map failed\n");
2156 p->des2 = priv->rx_skbuff_dma[entry];
2158 priv->hw->mode->refill_desc3(priv, p);
2160 if (netif_msg_rx_status(priv))
2161 pr_debug("\trefill entry #%d\n", entry);
2164 priv->hw->desc->set_rx_owner(p);
2167 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2169 priv->dirty_rx = entry;
2173 * stmmac_rx - manage the receive process
2174 * @priv: driver private structure
2175 * @limit: napi bugget.
2176 * Description : this the function called by the napi poll method.
2177 * It gets all the frames inside the ring.
2179 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2181 unsigned int entry = priv->cur_rx;
2182 unsigned int next_entry;
2183 unsigned int count = 0;
2184 int coe = priv->hw->rx_csum;
2186 if (netif_msg_rx_status(priv)) {
2187 pr_debug("%s: descriptor ring:\n", __func__);
2188 if (priv->extend_desc)
2189 stmmac_display_ring((void *)priv->dma_erx,
2192 stmmac_display_ring((void *)priv->dma_rx,
2195 while (count < limit) {
2199 if (priv->extend_desc)
2200 p = (struct dma_desc *)(priv->dma_erx + entry);
2202 p = priv->dma_rx + entry;
2204 if (priv->hw->desc->get_rx_owner(p))
2209 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2210 next_entry = priv->cur_rx;
2212 if (priv->extend_desc)
2213 prefetch(priv->dma_erx + next_entry);
2215 prefetch(priv->dma_rx + next_entry);
2217 /* read the status of the incoming frame */
2218 status = priv->hw->desc->rx_status(&priv->dev->stats,
2220 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2221 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2225 if (unlikely(status == discard_frame)) {
2226 priv->dev->stats.rx_errors++;
2227 if (priv->hwts_rx_en && !priv->extend_desc) {
2228 /* DESC2 & DESC3 will be overwitten by device
2229 * with timestamp value, hence reinitialize
2230 * them in stmmac_rx_refill() function so that
2231 * device can reuse it.
2233 priv->rx_skbuff[entry] = NULL;
2234 dma_unmap_single(priv->device,
2235 priv->rx_skbuff_dma[entry],
2240 struct sk_buff *skb;
2243 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2245 /* check if frame_len fits the preallocated memory */
2246 if (frame_len > priv->dma_buf_sz) {
2247 priv->dev->stats.rx_length_errors++;
2251 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2252 * Type frames (LLC/LLC-SNAP)
2254 if (unlikely(status != llc_snap))
2255 frame_len -= ETH_FCS_LEN;
2257 if (netif_msg_rx_status(priv)) {
2258 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2260 if (frame_len > ETH_FRAME_LEN)
2261 pr_debug("\tframe size %d, COE: %d\n",
2264 skb = priv->rx_skbuff[entry];
2265 if (unlikely(!skb)) {
2266 pr_err("%s: Inconsistent Rx descriptor chain\n",
2268 priv->dev->stats.rx_dropped++;
2271 prefetch(skb->data - NET_IP_ALIGN);
2272 priv->rx_skbuff[entry] = NULL;
2274 stmmac_get_rx_hwtstamp(priv, entry, skb);
2276 skb_put(skb, frame_len);
2277 dma_unmap_single(priv->device,
2278 priv->rx_skbuff_dma[entry],
2279 priv->dma_buf_sz, DMA_FROM_DEVICE);
2281 if (netif_msg_pktdata(priv)) {
2282 pr_debug("frame received (%dbytes)", frame_len);
2283 print_pkt(skb->data, frame_len);
2286 stmmac_rx_vlan(priv->dev, skb);
2288 skb->protocol = eth_type_trans(skb, priv->dev);
2291 skb_checksum_none_assert(skb);
2293 skb->ip_summed = CHECKSUM_UNNECESSARY;
2295 napi_gro_receive(&priv->napi, skb);
2297 priv->dev->stats.rx_packets++;
2298 priv->dev->stats.rx_bytes += frame_len;
2303 stmmac_rx_refill(priv);
2305 priv->xstats.rx_pkt_n += count;
2311 * stmmac_poll - stmmac poll method (NAPI)
2312 * @napi : pointer to the napi structure.
2313 * @budget : maximum number of packets that the current CPU can receive from
2316 * To look at the incoming frames and clear the tx resources.
2318 static int stmmac_poll(struct napi_struct *napi, int budget)
2320 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2323 priv->xstats.napi_poll++;
2324 stmmac_tx_clean(priv);
2326 work_done = stmmac_rx(priv, budget);
2327 if (work_done < budget) {
2328 napi_complete(napi);
2329 stmmac_enable_dma_irq(priv);
2336 * @dev : Pointer to net device structure
2337 * Description: this function is called when a packet transmission fails to
2338 * complete within a reasonable time. The driver will mark the error in the
2339 * netdev structure and arrange for the device to be reset to a sane state
2340 * in order to transmit a new packet.
2342 static void stmmac_tx_timeout(struct net_device *dev)
2344 struct stmmac_priv *priv = netdev_priv(dev);
2346 /* Clear Tx resources and restart transmitting again */
2347 stmmac_tx_err(priv);
2351 * stmmac_set_rx_mode - entry point for multicast addressing
2352 * @dev : pointer to the device structure
2354 * This function is a driver entry point which gets called by the kernel
2355 * whenever multicast addresses must be enabled/disabled.
2359 static void stmmac_set_rx_mode(struct net_device *dev)
2361 struct stmmac_priv *priv = netdev_priv(dev);
2363 priv->hw->mac->set_filter(priv->hw, dev);
2367 * stmmac_change_mtu - entry point to change MTU size for the device.
2368 * @dev : device pointer.
2369 * @new_mtu : the new MTU size for the device.
2370 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2371 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2372 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2374 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2377 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2379 struct stmmac_priv *priv = netdev_priv(dev);
2382 if (netif_running(dev)) {
2383 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2387 if (priv->plat->enh_desc)
2388 max_mtu = JUMBO_LEN;
2390 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2392 if (priv->plat->maxmtu < max_mtu)
2393 max_mtu = priv->plat->maxmtu;
2395 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2396 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2401 netdev_update_features(dev);
2406 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2407 netdev_features_t features)
2409 struct stmmac_priv *priv = netdev_priv(dev);
2411 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2412 features &= ~NETIF_F_RXCSUM;
2414 if (!priv->plat->tx_coe)
2415 features &= ~NETIF_F_CSUM_MASK;
2417 /* Some GMAC devices have a bugged Jumbo frame support that
2418 * needs to have the Tx COE disabled for oversized frames
2419 * (due to limited buffer sizes). In this case we disable
2420 * the TX csum insertionin the TDES and not use SF.
2422 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2423 features &= ~NETIF_F_CSUM_MASK;
2428 static int stmmac_set_features(struct net_device *netdev,
2429 netdev_features_t features)
2431 struct stmmac_priv *priv = netdev_priv(netdev);
2433 /* Keep the COE Type in case of csum is supporting */
2434 if (features & NETIF_F_RXCSUM)
2435 priv->hw->rx_csum = priv->plat->rx_coe;
2437 priv->hw->rx_csum = 0;
2438 /* No check needed because rx_coe has been set before and it will be
2439 * fixed in case of issue.
2441 priv->hw->mac->rx_ipc(priv->hw);
2447 * stmmac_interrupt - main ISR
2448 * @irq: interrupt number.
2449 * @dev_id: to pass the net device pointer.
2450 * Description: this is the main driver interrupt service routine.
2452 * o DMA service routine (to manage incoming frame reception and transmission
2454 * o Core interrupts to manage: remote wake-up, management counter, LPI
2457 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2459 struct net_device *dev = (struct net_device *)dev_id;
2460 struct stmmac_priv *priv = netdev_priv(dev);
2463 pm_wakeup_event(priv->device, 0);
2465 if (unlikely(!dev)) {
2466 pr_err("%s: invalid dev pointer\n", __func__);
2470 /* To handle GMAC own interrupts */
2471 if (priv->plat->has_gmac) {
2472 int status = priv->hw->mac->host_irq_status(priv->hw,
2474 if (unlikely(status)) {
2475 /* For LPI we need to save the tx status */
2476 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2477 priv->tx_path_in_lpi_mode = true;
2478 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2479 priv->tx_path_in_lpi_mode = false;
2483 /* To handle DMA interrupts */
2484 stmmac_dma_interrupt(priv);
2489 #ifdef CONFIG_NET_POLL_CONTROLLER
2490 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2491 * to allow network I/O with interrupts disabled.
2493 static void stmmac_poll_controller(struct net_device *dev)
2495 disable_irq(dev->irq);
2496 stmmac_interrupt(dev->irq, dev);
2497 enable_irq(dev->irq);
2502 * stmmac_ioctl - Entry point for the Ioctl
2503 * @dev: Device pointer.
2504 * @rq: An IOCTL specefic structure, that can contain a pointer to
2505 * a proprietary structure used to pass information to the driver.
2506 * @cmd: IOCTL command
2508 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2510 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2512 struct stmmac_priv *priv = netdev_priv(dev);
2513 int ret = -EOPNOTSUPP;
2515 if (!netif_running(dev))
2524 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2527 ret = stmmac_hwtstamp_ioctl(dev, rq);
2536 #ifdef CONFIG_DEBUG_FS
2537 static struct dentry *stmmac_fs_dir;
2539 static void sysfs_display_ring(void *head, int size, int extend_desc,
2540 struct seq_file *seq)
2543 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2544 struct dma_desc *p = (struct dma_desc *)head;
2546 for (i = 0; i < size; i++) {
2550 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2551 i, (unsigned int)virt_to_phys(ep),
2552 (unsigned int)x, (unsigned int)(x >> 32),
2553 ep->basic.des2, ep->basic.des3);
2557 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2558 i, (unsigned int)virt_to_phys(ep),
2559 (unsigned int)x, (unsigned int)(x >> 32),
2563 seq_printf(seq, "\n");
2567 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2569 struct net_device *dev = seq->private;
2570 struct stmmac_priv *priv = netdev_priv(dev);
2572 if (priv->extend_desc) {
2573 seq_printf(seq, "Extended RX descriptor ring:\n");
2574 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2575 seq_printf(seq, "Extended TX descriptor ring:\n");
2576 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2578 seq_printf(seq, "RX descriptor ring:\n");
2579 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2580 seq_printf(seq, "TX descriptor ring:\n");
2581 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2587 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2589 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2592 static const struct file_operations stmmac_rings_status_fops = {
2593 .owner = THIS_MODULE,
2594 .open = stmmac_sysfs_ring_open,
2596 .llseek = seq_lseek,
2597 .release = single_release,
2600 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2602 struct net_device *dev = seq->private;
2603 struct stmmac_priv *priv = netdev_priv(dev);
2605 if (!priv->hw_cap_support) {
2606 seq_printf(seq, "DMA HW features not supported\n");
2610 seq_printf(seq, "==============================\n");
2611 seq_printf(seq, "\tDMA HW features\n");
2612 seq_printf(seq, "==============================\n");
2614 seq_printf(seq, "\t10/100 Mbps %s\n",
2615 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2616 seq_printf(seq, "\t1000 Mbps %s\n",
2617 (priv->dma_cap.mbps_1000) ? "Y" : "N");
2618 seq_printf(seq, "\tHalf duple %s\n",
2619 (priv->dma_cap.half_duplex) ? "Y" : "N");
2620 seq_printf(seq, "\tHash Filter: %s\n",
2621 (priv->dma_cap.hash_filter) ? "Y" : "N");
2622 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2623 (priv->dma_cap.multi_addr) ? "Y" : "N");
2624 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2625 (priv->dma_cap.pcs) ? "Y" : "N");
2626 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2627 (priv->dma_cap.sma_mdio) ? "Y" : "N");
2628 seq_printf(seq, "\tPMT Remote wake up: %s\n",
2629 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2630 seq_printf(seq, "\tPMT Magic Frame: %s\n",
2631 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2632 seq_printf(seq, "\tRMON module: %s\n",
2633 (priv->dma_cap.rmon) ? "Y" : "N");
2634 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2635 (priv->dma_cap.time_stamp) ? "Y" : "N");
2636 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2637 (priv->dma_cap.atime_stamp) ? "Y" : "N");
2638 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2639 (priv->dma_cap.eee) ? "Y" : "N");
2640 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2641 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2642 (priv->dma_cap.tx_coe) ? "Y" : "N");
2643 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2644 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2645 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2646 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2647 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2648 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2649 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2650 priv->dma_cap.number_rx_channel);
2651 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2652 priv->dma_cap.number_tx_channel);
2653 seq_printf(seq, "\tEnhanced descriptors: %s\n",
2654 (priv->dma_cap.enh_desc) ? "Y" : "N");
2659 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2661 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2664 static const struct file_operations stmmac_dma_cap_fops = {
2665 .owner = THIS_MODULE,
2666 .open = stmmac_sysfs_dma_cap_open,
2668 .llseek = seq_lseek,
2669 .release = single_release,
2672 static int stmmac_init_fs(struct net_device *dev)
2674 struct stmmac_priv *priv = netdev_priv(dev);
2676 /* Create per netdev entries */
2677 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2679 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2680 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2681 STMMAC_RESOURCE_NAME, dev->name);
2686 /* Entry to report DMA RX/TX rings */
2687 priv->dbgfs_rings_status =
2688 debugfs_create_file("descriptors_status", S_IRUGO,
2689 priv->dbgfs_dir, dev,
2690 &stmmac_rings_status_fops);
2692 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2693 pr_info("ERROR creating stmmac ring debugfs file\n");
2694 debugfs_remove_recursive(priv->dbgfs_dir);
2699 /* Entry to report the DMA HW features */
2700 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2702 dev, &stmmac_dma_cap_fops);
2704 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2705 pr_info("ERROR creating stmmac MMC debugfs file\n");
2706 debugfs_remove_recursive(priv->dbgfs_dir);
2714 static void stmmac_exit_fs(struct net_device *dev)
2716 struct stmmac_priv *priv = netdev_priv(dev);
2718 debugfs_remove_recursive(priv->dbgfs_dir);
2720 #endif /* CONFIG_DEBUG_FS */
2722 static const struct net_device_ops stmmac_netdev_ops = {
2723 .ndo_open = stmmac_open,
2724 .ndo_start_xmit = stmmac_xmit,
2725 .ndo_stop = stmmac_release,
2726 .ndo_change_mtu = stmmac_change_mtu,
2727 .ndo_fix_features = stmmac_fix_features,
2728 .ndo_set_features = stmmac_set_features,
2729 .ndo_set_rx_mode = stmmac_set_rx_mode,
2730 .ndo_tx_timeout = stmmac_tx_timeout,
2731 .ndo_do_ioctl = stmmac_ioctl,
2732 #ifdef CONFIG_NET_POLL_CONTROLLER
2733 .ndo_poll_controller = stmmac_poll_controller,
2735 .ndo_set_mac_address = eth_mac_addr,
2739 * stmmac_hw_init - Init the MAC device
2740 * @priv: driver private structure
2741 * Description: this function is to configure the MAC device according to
2742 * some platform parameters or the HW capability register. It prepares the
2743 * driver to use either ring or chain modes and to setup either enhanced or
2744 * normal descriptors.
2746 static int stmmac_hw_init(struct stmmac_priv *priv)
2748 struct mac_device_info *mac;
2750 /* Identify the MAC HW device */
2751 if (priv->plat->has_gmac) {
2752 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2753 mac = dwmac1000_setup(priv->ioaddr,
2754 priv->plat->multicast_filter_bins,
2755 priv->plat->unicast_filter_entries);
2757 mac = dwmac100_setup(priv->ioaddr);
2764 /* Get and dump the chip ID */
2765 priv->synopsys_id = stmmac_get_synopsys_id(priv);
2767 /* To use the chained or ring mode */
2769 priv->hw->mode = &chain_mode_ops;
2770 pr_info(" Chain mode enabled\n");
2771 priv->mode = STMMAC_CHAIN_MODE;
2773 priv->hw->mode = &ring_mode_ops;
2774 pr_info(" Ring mode enabled\n");
2775 priv->mode = STMMAC_RING_MODE;
2778 /* Get the HW capability (new GMAC newer than 3.50a) */
2779 priv->hw_cap_support = stmmac_get_hw_features(priv);
2780 if (priv->hw_cap_support) {
2781 pr_info(" DMA HW capability register supported");
2783 /* We can override some gmac/dma configuration fields: e.g.
2784 * enh_desc, tx_coe (e.g. that are passed through the
2785 * platform) with the values from the HW capability
2786 * register (if supported).
2788 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2789 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2791 /* TXCOE doesn't work in thresh DMA mode */
2792 if (priv->plat->force_thresh_dma_mode)
2793 priv->plat->tx_coe = 0;
2795 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2797 if (priv->dma_cap.rx_coe_type2)
2798 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2799 else if (priv->dma_cap.rx_coe_type1)
2800 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2803 pr_info(" No HW DMA feature register supported");
2805 /* To use alternate (extended) or normal descriptor structures */
2806 stmmac_selec_desc_mode(priv);
2808 if (priv->plat->rx_coe) {
2809 priv->hw->rx_csum = priv->plat->rx_coe;
2810 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2811 priv->plat->rx_coe);
2813 if (priv->plat->tx_coe)
2814 pr_info(" TX Checksum insertion supported\n");
2816 if (priv->plat->pmt) {
2817 pr_info(" Wake-Up On Lan supported\n");
2818 device_set_wakeup_capable(priv->device, 1);
2826 * @device: device pointer
2827 * @plat_dat: platform data pointer
2828 * @res: stmmac resource pointer
2829 * Description: this is the main probe function used to
2830 * call the alloc_etherdev, allocate the priv structure.
2832 * returns 0 on success, otherwise errno.
2834 int stmmac_dvr_probe(struct device *device,
2835 struct plat_stmmacenet_data *plat_dat,
2836 struct stmmac_resources *res)
2839 struct net_device *ndev = NULL;
2840 struct stmmac_priv *priv;
2842 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2846 SET_NETDEV_DEV(ndev, device);
2848 priv = netdev_priv(ndev);
2849 priv->device = device;
2852 stmmac_set_ethtool_ops(ndev);
2853 priv->pause = pause;
2854 priv->plat = plat_dat;
2855 priv->ioaddr = res->addr;
2856 priv->dev->base_addr = (unsigned long)res->addr;
2858 priv->dev->irq = res->irq;
2859 priv->wol_irq = res->wol_irq;
2860 priv->lpi_irq = res->lpi_irq;
2863 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2865 dev_set_drvdata(device, priv->dev);
2867 /* Verify driver arguments */
2868 stmmac_verify_args();
2870 /* Override with kernel parameters if supplied XXX CRS XXX
2871 * this needs to have multiple instances
2873 if ((phyaddr >= 0) && (phyaddr <= 31))
2874 priv->plat->phy_addr = phyaddr;
2876 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2877 if (IS_ERR(priv->stmmac_clk)) {
2878 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2880 /* If failed to obtain stmmac_clk and specific clk_csr value
2881 * is NOT passed from the platform, probe fail.
2883 if (!priv->plat->clk_csr) {
2884 ret = PTR_ERR(priv->stmmac_clk);
2887 priv->stmmac_clk = NULL;
2890 clk_prepare_enable(priv->stmmac_clk);
2892 priv->pclk = devm_clk_get(priv->device, "pclk");
2893 if (IS_ERR(priv->pclk)) {
2894 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2895 ret = -EPROBE_DEFER;
2896 goto error_pclk_get;
2900 clk_prepare_enable(priv->pclk);
2902 priv->stmmac_rst = devm_reset_control_get(priv->device,
2903 STMMAC_RESOURCE_NAME);
2904 if (IS_ERR(priv->stmmac_rst)) {
2905 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2906 ret = -EPROBE_DEFER;
2909 dev_info(priv->device, "no reset control found\n");
2910 priv->stmmac_rst = NULL;
2912 if (priv->stmmac_rst)
2913 reset_control_deassert(priv->stmmac_rst);
2915 /* Init MAC and get the capabilities */
2916 ret = stmmac_hw_init(priv);
2920 ndev->netdev_ops = &stmmac_netdev_ops;
2922 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2924 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2925 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2926 #ifdef STMMAC_VLAN_TAG_USED
2927 /* Both mac100 and gmac support receive VLAN tag detection */
2928 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2930 priv->msg_enable = netif_msg_init(debug, default_msg_level);
2933 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
2935 /* Rx Watchdog is available in the COREs newer than the 3.40.
2936 * In some case, for example on bugged HW this feature
2937 * has to be disable and this can be done by passing the
2938 * riwt_off field from the platform.
2940 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2942 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2945 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2947 spin_lock_init(&priv->lock);
2948 spin_lock_init(&priv->tx_lock);
2950 ret = register_netdev(ndev);
2952 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2953 goto error_netdev_register;
2956 /* If a specific clk_csr value is passed from the platform
2957 * this means that the CSR Clock Range selection cannot be
2958 * changed at run-time and it is fixed. Viceversa the driver'll try to
2959 * set the MDC clock dynamically according to the csr actual
2962 if (!priv->plat->clk_csr)
2963 stmmac_clk_csr_set(priv);
2965 priv->clk_csr = priv->plat->clk_csr;
2967 stmmac_check_pcs_mode(priv);
2969 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2970 priv->pcs != STMMAC_PCS_RTBI) {
2971 /* MDIO bus Registration */
2972 ret = stmmac_mdio_register(ndev);
2974 pr_debug("%s: MDIO bus (id: %d) registration failed",
2975 __func__, priv->plat->bus_id);
2976 goto error_mdio_register;
2982 error_mdio_register:
2983 unregister_netdev(ndev);
2984 error_netdev_register:
2985 netif_napi_del(&priv->napi);
2987 clk_disable_unprepare(priv->pclk);
2989 clk_disable_unprepare(priv->stmmac_clk);
2995 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2999 * @ndev: net device pointer
3000 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3001 * changes the link status, releases the DMA descriptor rings.
3003 int stmmac_dvr_remove(struct net_device *ndev)
3005 struct stmmac_priv *priv = netdev_priv(ndev);
3007 pr_info("%s:\n\tremoving driver", __func__);
3009 priv->hw->dma->stop_rx(priv->ioaddr);
3010 priv->hw->dma->stop_tx(priv->ioaddr);
3012 stmmac_set_mac(priv->ioaddr, false);
3013 netif_carrier_off(ndev);
3014 unregister_netdev(ndev);
3015 if (priv->stmmac_rst)
3016 reset_control_assert(priv->stmmac_rst);
3017 clk_disable_unprepare(priv->pclk);
3018 clk_disable_unprepare(priv->stmmac_clk);
3019 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3020 priv->pcs != STMMAC_PCS_RTBI)
3021 stmmac_mdio_unregister(ndev);
3026 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3029 * stmmac_suspend - suspend callback
3030 * @ndev: net device pointer
3031 * Description: this is the function to suspend the device and it is called
3032 * by the platform driver to stop the network queue, release the resources,
3033 * program the PMT register (for WoL), clean and release driver resources.
3035 int stmmac_suspend(struct net_device *ndev)
3037 struct stmmac_priv *priv = netdev_priv(ndev);
3038 unsigned long flags;
3040 if (!ndev || !netif_running(ndev))
3044 phy_stop(priv->phydev);
3046 spin_lock_irqsave(&priv->lock, flags);
3048 netif_device_detach(ndev);
3049 netif_stop_queue(ndev);
3051 napi_disable(&priv->napi);
3053 /* Stop TX/RX DMA */
3054 priv->hw->dma->stop_tx(priv->ioaddr);
3055 priv->hw->dma->stop_rx(priv->ioaddr);
3057 /* Enable Power down mode by programming the PMT regs */
3058 if (device_may_wakeup(priv->device)) {
3059 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3062 stmmac_set_mac(priv->ioaddr, false);
3063 pinctrl_pm_select_sleep_state(priv->device);
3064 /* Disable clock in case of PWM is off */
3065 clk_disable(priv->pclk);
3066 clk_disable(priv->stmmac_clk);
3068 spin_unlock_irqrestore(&priv->lock, flags);
3072 priv->oldduplex = -1;
3075 EXPORT_SYMBOL_GPL(stmmac_suspend);
3078 * stmmac_resume - resume callback
3079 * @ndev: net device pointer
3080 * Description: when resume this function is invoked to setup the DMA and CORE
3081 * in a usable state.
3083 int stmmac_resume(struct net_device *ndev)
3085 struct stmmac_priv *priv = netdev_priv(ndev);
3086 unsigned long flags;
3088 if (!netif_running(ndev))
3091 spin_lock_irqsave(&priv->lock, flags);
3093 /* Power Down bit, into the PM register, is cleared
3094 * automatically as soon as a magic packet or a Wake-up frame
3095 * is received. Anyway, it's better to manually clear
3096 * this bit because it can generate problems while resuming
3097 * from another devices (e.g. serial console).
3099 if (device_may_wakeup(priv->device)) {
3100 priv->hw->mac->pmt(priv->hw, 0);
3103 pinctrl_pm_select_default_state(priv->device);
3104 /* enable the clk prevously disabled */
3105 clk_enable(priv->stmmac_clk);
3106 clk_enable(priv->pclk);
3107 /* reset the phy so that it's ready */
3109 stmmac_mdio_reset(priv->mii);
3112 netif_device_attach(ndev);
3118 stmmac_clear_descriptors(priv);
3120 stmmac_hw_setup(ndev, false);
3121 stmmac_init_tx_coalesce(priv);
3122 stmmac_set_rx_mode(ndev);
3124 napi_enable(&priv->napi);
3126 netif_start_queue(ndev);
3128 spin_unlock_irqrestore(&priv->lock, flags);
3131 phy_start(priv->phydev);
3135 EXPORT_SYMBOL_GPL(stmmac_resume);
3138 static int __init stmmac_cmdline_opt(char *str)
3144 while ((opt = strsep(&str, ",")) != NULL) {
3145 if (!strncmp(opt, "debug:", 6)) {
3146 if (kstrtoint(opt + 6, 0, &debug))
3148 } else if (!strncmp(opt, "phyaddr:", 8)) {
3149 if (kstrtoint(opt + 8, 0, &phyaddr))
3151 } else if (!strncmp(opt, "buf_sz:", 7)) {
3152 if (kstrtoint(opt + 7, 0, &buf_sz))
3154 } else if (!strncmp(opt, "tc:", 3)) {
3155 if (kstrtoint(opt + 3, 0, &tc))
3157 } else if (!strncmp(opt, "watchdog:", 9)) {
3158 if (kstrtoint(opt + 9, 0, &watchdog))
3160 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3161 if (kstrtoint(opt + 10, 0, &flow_ctrl))
3163 } else if (!strncmp(opt, "pause:", 6)) {
3164 if (kstrtoint(opt + 6, 0, &pause))
3166 } else if (!strncmp(opt, "eee_timer:", 10)) {
3167 if (kstrtoint(opt + 10, 0, &eee_timer))
3169 } else if (!strncmp(opt, "chain_mode:", 11)) {
3170 if (kstrtoint(opt + 11, 0, &chain_mode))
3177 pr_err("%s: ERROR broken module parameter conversion", __func__);
3181 __setup("stmmaceth=", stmmac_cmdline_opt);
3184 static int __init stmmac_init(void)
3186 #ifdef CONFIG_DEBUG_FS
3187 /* Create debugfs main directory if it doesn't exist yet */
3188 if (!stmmac_fs_dir) {
3189 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3191 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3192 pr_err("ERROR %s, debugfs create directory failed\n",
3193 STMMAC_RESOURCE_NAME);
3203 static void __exit stmmac_exit(void)
3205 #ifdef CONFIG_DEBUG_FS
3206 debugfs_remove_recursive(stmmac_fs_dir);
3210 module_init(stmmac_init)
3211 module_exit(stmmac_exit)
3213 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3214 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3215 MODULE_LICENSE("GPL");