drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55 #include <linux/of_mdio.h>
  56 #include "dwmac1000.h"
  57
  58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  59
  60 /* Module parameters */
  61 #define TX_TIMEO        5000
  62 static int watchdog = TX_TIMEO;
  63 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  64 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  65
  66 static int debug = -1;
  67 module_param(debug, int, S_IRUGO | S_IWUSR);
  68 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  69
  70 static int phyaddr = -1;
  71 module_param(phyaddr, int, S_IRUGO);
  72 MODULE_PARM_DESC(phyaddr, "Physical device address");
  73
  74 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  75
  76 static int flow_ctrl = FLOW_OFF;
  77 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  78 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  79
  80 static int pause = PAUSE_TIME;
  81 module_param(pause, int, S_IRUGO | S_IWUSR);
  82 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  83
  84 #define TC_DEFAULT 64
  85 static int tc = TC_DEFAULT;
  86 module_param(tc, int, S_IRUGO | S_IWUSR);
  87 MODULE_PARM_DESC(tc, "DMA threshold control value");
  88
  89 #define DEFAULT_BUFSIZE 1536
  90 static int buf_sz = DEFAULT_BUFSIZE;
  91 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  92 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  93
  94 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  95                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  96                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  97
  98 #define STMMAC_DEFAULT_LPI_TIMER        1000
  99 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 100 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 101 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 102 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 103
 104 /* By default the driver will use the ring mode to manage tx and rx descriptors
 105  * but passing this value so user can force to use the chain instead of the ring
 106  */
 107 static unsigned int chain_mode;
 108 module_param(chain_mode, int, S_IRUGO);
 109 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 110
 111 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 112
 113 #ifdef CONFIG_DEBUG_FS
 114 static int stmmac_init_fs(struct net_device *dev);
 115 static void stmmac_exit_fs(struct net_device *dev);
 116 #endif
 117
 118 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 119
 120 /**
 121  * stmmac_verify_args - verify the driver parameters.
 122  * Description: it checks the driver parameters and set a default in case of
 123  * errors.
 124  */
 125 static void stmmac_verify_args(void)
 126 {
 127         if (unlikely(watchdog < 0))
 128                 watchdog = TX_TIMEO;
 129         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 130                 buf_sz = DEFAULT_BUFSIZE;
 131         if (unlikely(flow_ctrl > 1))
 132                 flow_ctrl = FLOW_AUTO;
 133         else if (likely(flow_ctrl < 0))
 134                 flow_ctrl = FLOW_OFF;
 135         if (unlikely((pause < 0) || (pause > 0xffff)))
 136                 pause = PAUSE_TIME;
 137         if (eee_timer < 0)
 138                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 139 }
 140
 141 /**
 142  * stmmac_clk_csr_set - dynamically set the MDC clock
 143  * @priv: driver private structure
 144  * Description: this is to dynamically set the MDC clock according to the csr
 145  * clock input.
 146  * Note:
 147  *      If a specific clk_csr value is passed from the platform
 148  *      this means that the CSR Clock Range selection cannot be
 149  *      changed at run-time and it is fixed (as reported in the driver
 150  *      documentation). Viceversa the driver will try to set the MDC
 151  *      clock dynamically according to the actual clock input.
 152  */
 153 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 154 {
 155         u32 clk_rate;
 156
 157         clk_rate = clk_get_rate(priv->stmmac_clk);
 158
 159         /* Platform provided default clk_csr would be assumed valid
 160          * for all other cases except for the below mentioned ones.
 161          * For values higher than the IEEE 802.3 specified frequency
 162          * we can not estimate the proper divider as it is not known
 163          * the frequency of clk_csr_i. So we do not change the default
 164          * divider.
 165          */
 166         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 167                 if (clk_rate < CSR_F_35M)
 168                         priv->clk_csr = STMMAC_CSR_20_35M;
 169                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 170                         priv->clk_csr = STMMAC_CSR_35_60M;
 171                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 172                         priv->clk_csr = STMMAC_CSR_60_100M;
 173                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 174                         priv->clk_csr = STMMAC_CSR_100_150M;
 175                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 176                         priv->clk_csr = STMMAC_CSR_150_250M;
 177                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 178                         priv->clk_csr = STMMAC_CSR_250_300M;
 179         }
 180 }
 181
 182 static void print_pkt(unsigned char *buf, int len)
 183 {
 184         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 185         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 186 }
 187
 188 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 189 {
 190         unsigned avail;
 191
 192         if (priv->dirty_tx > priv->cur_tx)
 193                 avail = priv->dirty_tx - priv->cur_tx - 1;
 194         else
 195                 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
 196
 197         return avail;
 198 }
 199
 200 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
 201 {
 202         unsigned dirty;
 203
 204         if (priv->dirty_rx <= priv->cur_rx)
 205                 dirty = priv->cur_rx - priv->dirty_rx;
 206         else
 207                 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
 208
 209         return dirty;
 210 }
 211
 212 /**
 213  * stmmac_hw_fix_mac_speed - callback for speed selection
 214  * @priv: driver private structure
 215  * Description: on some platforms (e.g. ST), some HW system configuraton
 216  * registers have to be set according to the link speed negotiated.
 217  */
 218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 219 {
 220         struct phy_device *phydev = priv->phydev;
 221
 222         if (likely(priv->plat->fix_mac_speed))
 223                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 224 }
 225
 226 /**
 227  * stmmac_enable_eee_mode - check and enter in LPI mode
 228  * @priv: driver private structure
 229  * Description: this function is to verify and enter in LPI mode in case of
 230  * EEE.
 231  */
 232 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 233 {
 234         /* Check and enter in LPI mode */
 235         if ((priv->dirty_tx == priv->cur_tx) &&
 236             (priv->tx_path_in_lpi_mode == false))
 237                 priv->hw->mac->set_eee_mode(priv->hw);
 238 }
 239
 240 /**
 241  * stmmac_disable_eee_mode - disable and exit from LPI mode
 242  * @priv: driver private structure
 243  * Description: this function is to exit and disable EEE in case of
 244  * LPI state is true. This is called by the xmit.
 245  */
 246 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 247 {
 248         priv->hw->mac->reset_eee_mode(priv->hw);
 249         del_timer_sync(&priv->eee_ctrl_timer);
 250         priv->tx_path_in_lpi_mode = false;
 251 }
 252
 253 /**
 254  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 255  * @arg : data hook
 256  * Description:
 257  *  if there is no data transfer and if we are not in LPI state,
 258  *  then MAC Transmitter can be moved to LPI state.
 259  */
 260 static void stmmac_eee_ctrl_timer(unsigned long arg)
 261 {
 262         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 263
 264         stmmac_enable_eee_mode(priv);
 265         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 266 }
 267
 268 /**
 269  * stmmac_eee_init - init EEE
 270  * @priv: driver private structure
 271  * Description:
 272  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 273  *  can also manage EEE, this function enable the LPI state and start related
 274  *  timer.
 275  */
 276 bool stmmac_eee_init(struct stmmac_priv *priv)
 277 {
 278         char *phy_bus_name = priv->plat->phy_bus_name;
 279         unsigned long flags;
 280         bool ret = false;
 281
 282         /* Using PCS we cannot dial with the phy registers at this stage
 283          * so we do not support extra feature like EEE.
 284          */
 285         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 286             (priv->pcs == STMMAC_PCS_RTBI))
 287                 goto out;
 288
 289         /* Never init EEE in case of a switch is attached */
 290         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
 291                 goto out;
 292
 293         /* MAC core supports the EEE feature. */
 294         if (priv->dma_cap.eee) {
 295                 int tx_lpi_timer = priv->tx_lpi_timer;
 296
 297                 /* Check if the PHY supports EEE */
 298                 if (phy_init_eee(priv->phydev, 1)) {
 299                         /* To manage at run-time if the EEE cannot be supported
 300                          * anymore (for example because the lp caps have been
 301                          * changed).
 302                          * In that case the driver disable own timers.
 303                          */
 304                         spin_lock_irqsave(&priv->lock, flags);
 305                         if (priv->eee_active) {
 306                                 pr_debug("stmmac: disable EEE\n");
 307                                 del_timer_sync(&priv->eee_ctrl_timer);
 308                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 309                                                              tx_lpi_timer);
 310                         }
 311                         priv->eee_active = 0;
 312                         spin_unlock_irqrestore(&priv->lock, flags);
 313                         goto out;
 314                 }
 315                 /* Activate the EEE and start timers */
 316                 spin_lock_irqsave(&priv->lock, flags);
 317                 if (!priv->eee_active) {
 318                         priv->eee_active = 1;
 319                         setup_timer(&priv->eee_ctrl_timer,
 320                                     stmmac_eee_ctrl_timer,
 321                                     (unsigned long)priv);
 322                         mod_timer(&priv->eee_ctrl_timer,
 323                                   STMMAC_LPI_T(eee_timer));
 324
 325                         priv->hw->mac->set_eee_timer(priv->hw,
 326                                                      STMMAC_DEFAULT_LIT_LS,
 327                                                      tx_lpi_timer);
 328                 }
 329                 /* Set HW EEE according to the speed */
 330                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 331
 332                 ret = true;
 333                 spin_unlock_irqrestore(&priv->lock, flags);
 334
 335                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 336         }
 337 out:
 338         return ret;
 339 }
 340
 341 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 342  * @priv: driver private structure
 343  * @entry : descriptor index to be used.
 344  * @skb : the socket buffer
 345  * Description :
 346  * This function will read timestamp from the descriptor & pass it to stack.
 347  * and also perform some sanity checks.
 348  */
 349 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 350                                    unsigned int entry, struct sk_buff *skb)
 351 {
 352         struct skb_shared_hwtstamps shhwtstamp;
 353         u64 ns;
 354         void *desc = NULL;
 355
 356         if (!priv->hwts_tx_en)
 357                 return;
 358
 359         /* exit if skb doesn't support hw tstamp */
 360         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 361                 return;
 362
 363         if (priv->adv_ts)
 364                 desc = (priv->dma_etx + entry);
 365         else
 366                 desc = (priv->dma_tx + entry);
 367
 368         /* check tx tstamp status */
 369         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 370                 return;
 371
 372         /* get the valid tstamp */
 373         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 374
 375         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 376         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 377         /* pass tstamp to stack */
 378         skb_tstamp_tx(skb, &shhwtstamp);
 379
 380         return;
 381 }
 382
 383 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 384  * @priv: driver private structure
 385  * @entry : descriptor index to be used.
 386  * @skb : the socket buffer
 387  * Description :
 388  * This function will read received packet's timestamp from the descriptor
 389  * and pass it to stack. It also perform some sanity checks.
 390  */
 391 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 392                                    unsigned int entry, struct sk_buff *skb)
 393 {
 394         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 395         u64 ns;
 396         void *desc = NULL;
 397
 398         if (!priv->hwts_rx_en)
 399                 return;
 400
 401         if (priv->adv_ts)
 402                 desc = (priv->dma_erx + entry);
 403         else
 404                 desc = (priv->dma_rx + entry);
 405
 406         /* exit if rx tstamp is not valid */
 407         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 408                 return;
 409
 410         /* get valid tstamp */
 411         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 412         shhwtstamp = skb_hwtstamps(skb);
 413         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 414         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 415 }
 416
 417 /**
 418  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 419  *  @dev: device pointer.
 420  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 421  *  a proprietary structure used to pass information to the driver.
 422  *  Description:
 423  *  This function configures the MAC to enable/disable both outgoing(TX)
 424  *  and incoming(RX) packets time stamping based on user input.
 425  *  Return Value:
 426  *  0 on success and an appropriate -ve integer on failure.
 427  */
 428 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 429 {
 430         struct stmmac_priv *priv = netdev_priv(dev);
 431         struct hwtstamp_config config;
 432         struct timespec64 now;
 433         u64 temp = 0;
 434         u32 ptp_v2 = 0;
 435         u32 tstamp_all = 0;
 436         u32 ptp_over_ipv4_udp = 0;
 437         u32 ptp_over_ipv6_udp = 0;
 438         u32 ptp_over_ethernet = 0;
 439         u32 snap_type_sel = 0;
 440         u32 ts_master_en = 0;
 441         u32 ts_event_en = 0;
 442         u32 value = 0;
 443         u32 sec_inc;
 444
 445         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 446                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 447                 priv->hwts_tx_en = 0;
 448                 priv->hwts_rx_en = 0;
 449
 450                 return -EOPNOTSUPP;
 451         }
 452
 453         if (copy_from_user(&config, ifr->ifr_data,
 454                            sizeof(struct hwtstamp_config)))
 455                 return -EFAULT;
 456
 457         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 458                  __func__, config.flags, config.tx_type, config.rx_filter);
 459
 460         /* reserved for future extensions */
 461         if (config.flags)
 462                 return -EINVAL;
 463
 464         if (config.tx_type != HWTSTAMP_TX_OFF &&
 465             config.tx_type != HWTSTAMP_TX_ON)
 466                 return -ERANGE;
 467
 468         if (priv->adv_ts) {
 469                 switch (config.rx_filter) {
 470                 case HWTSTAMP_FILTER_NONE:
 471                         /* time stamp no incoming packet at all */
 472                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 473                         break;
 474
 475                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 476                         /* PTP v1, UDP, any kind of event packet */
 477                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 478                         /* take time stamp for all event messages */
 479                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 480
 481                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 482                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 483                         break;
 484
 485                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 486                         /* PTP v1, UDP, Sync packet */
 487                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 488                         /* take time stamp for SYNC messages only */
 489                         ts_event_en = PTP_TCR_TSEVNTENA;
 490
 491                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 492                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 493                         break;
 494
 495                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 496                         /* PTP v1, UDP, Delay_req packet */
 497                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 498                         /* take time stamp for Delay_Req messages only */
 499                         ts_master_en = PTP_TCR_TSMSTRENA;
 500                         ts_event_en = PTP_TCR_TSEVNTENA;
 501
 502                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 503                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 504                         break;
 505
 506                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 507                         /* PTP v2, UDP, any kind of event packet */
 508                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 509                         ptp_v2 = PTP_TCR_TSVER2ENA;
 510                         /* take time stamp for all event messages */
 511                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 512
 513                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 514                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 515                         break;
 516
 517                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 518                         /* PTP v2, UDP, Sync packet */
 519                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 520                         ptp_v2 = PTP_TCR_TSVER2ENA;
 521                         /* take time stamp for SYNC messages only */
 522                         ts_event_en = PTP_TCR_TSEVNTENA;
 523
 524                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 525                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 526                         break;
 527
 528                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 529                         /* PTP v2, UDP, Delay_req packet */
 530                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 531                         ptp_v2 = PTP_TCR_TSVER2ENA;
 532                         /* take time stamp for Delay_Req messages only */
 533                         ts_master_en = PTP_TCR_TSMSTRENA;
 534                         ts_event_en = PTP_TCR_TSEVNTENA;
 535
 536                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 537                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 538                         break;
 539
 540                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 541                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 542                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 543                         ptp_v2 = PTP_TCR_TSVER2ENA;
 544                         /* take time stamp for all event messages */
 545                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 546
 547                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 548                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 549                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 550                         break;
 551
 552                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 553                         /* PTP v2/802.AS1, any layer, Sync packet */
 554                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 555                         ptp_v2 = PTP_TCR_TSVER2ENA;
 556                         /* take time stamp for SYNC messages only */
 557                         ts_event_en = PTP_TCR_TSEVNTENA;
 558
 559                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 560                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 561                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 562                         break;
 563
 564                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 565                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 566                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 567                         ptp_v2 = PTP_TCR_TSVER2ENA;
 568                         /* take time stamp for Delay_Req messages only */
 569                         ts_master_en = PTP_TCR_TSMSTRENA;
 570                         ts_event_en = PTP_TCR_TSEVNTENA;
 571
 572                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 573                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 574                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 575                         break;
 576
 577                 case HWTSTAMP_FILTER_ALL:
 578                         /* time stamp any incoming packet */
 579                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 580                         tstamp_all = PTP_TCR_TSENALL;
 581                         break;
 582
 583                 default:
 584                         return -ERANGE;
 585                 }
 586         } else {
 587                 switch (config.rx_filter) {
 588                 case HWTSTAMP_FILTER_NONE:
 589                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 590                         break;
 591                 default:
 592                         /* PTP v1, UDP, any kind of event packet */
 593                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 594                         break;
 595                 }
 596         }
 597         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 598         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 599
 600         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 601                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 602         else {
 603                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 604                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 605                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 606                          ts_master_en | snap_type_sel);
 607                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 608
 609                 /* program Sub Second Increment reg */
 610                 sec_inc = priv->hw->ptp->config_sub_second_increment(
 611                         priv->ioaddr, priv->clk_ptp_rate);
 612                 temp = div_u64(1000000000ULL, sec_inc);
 613
 614                 /* calculate default added value:
 615                  * formula is :
 616                  * addend = (2^32)/freq_div_ratio;
 617                  * where, freq_div_ratio = 1e9ns/sec_inc
 618                  */
 619                 temp = (u64)(temp << 32);
 620                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 621                 priv->hw->ptp->config_addend(priv->ioaddr,
 622                                              priv->default_addend);
 623
 624                 /* initialize system time */
 625                 ktime_get_real_ts64(&now);
 626
 627                 /* lower 32 bits of tv_sec are safe until y2106 */
 628                 priv->hw->ptp->init_systime(priv->ioaddr, (u32)now.tv_sec,
 629                                             now.tv_nsec);
 630         }
 631
 632         return copy_to_user(ifr->ifr_data, &config,
 633                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 634 }
 635
 636 /**
 637  * stmmac_init_ptp - init PTP
 638  * @priv: driver private structure
 639  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 640  * This is done by looking at the HW cap. register.
 641  * This function also registers the ptp driver.
 642  */
 643 static int stmmac_init_ptp(struct stmmac_priv *priv)
 644 {
 645         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 646                 return -EOPNOTSUPP;
 647
 648         /* Fall-back to main clock in case of no PTP ref is passed */
 649         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 650         if (IS_ERR(priv->clk_ptp_ref)) {
 651                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 652                 priv->clk_ptp_ref = NULL;
 653         } else {
 654                 clk_prepare_enable(priv->clk_ptp_ref);
 655                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 656         }
 657
 658         priv->adv_ts = 0;
 659         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 660                 priv->adv_ts = 1;
 661
 662         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 663                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 664
 665         if (netif_msg_hw(priv) && priv->adv_ts)
 666                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 667
 668         priv->hw->ptp = &stmmac_ptp;
 669         priv->hwts_tx_en = 0;
 670         priv->hwts_rx_en = 0;
 671
 672         return stmmac_ptp_register(priv);
 673 }
 674
 675 static void stmmac_release_ptp(struct stmmac_priv *priv)
 676 {
 677         if (priv->clk_ptp_ref)
 678                 clk_disable_unprepare(priv->clk_ptp_ref);
 679         stmmac_ptp_unregister(priv);
 680 }
 681
 682 /**
 683  * stmmac_adjust_link - adjusts the link parameters
 684  * @dev: net device structure
 685  * Description: this is the helper called by the physical abstraction layer
 686  * drivers to communicate the phy link status. According the speed and duplex
 687  * this driver can invoke registered glue-logic as well.
 688  * It also invoke the eee initialization because it could happen when switch
 689  * on different networks (that are eee capable).
 690  */
 691 static void stmmac_adjust_link(struct net_device *dev)
 692 {
 693         struct stmmac_priv *priv = netdev_priv(dev);
 694         struct phy_device *phydev = priv->phydev;
 695         unsigned long flags;
 696         int new_state = 0;
 697         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 698
 699         if (phydev == NULL)
 700                 return;
 701
 702         spin_lock_irqsave(&priv->lock, flags);
 703
 704         if (phydev->link) {
 705                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 706
 707                 /* Now we make sure that we can be in full duplex mode.
 708                  * If not, we operate in half-duplex mode. */
 709                 if (phydev->duplex != priv->oldduplex) {
 710                         new_state = 1;
 711                         if (!(phydev->duplex))
 712                                 ctrl &= ~priv->hw->link.duplex;
 713                         else
 714                                 ctrl |= priv->hw->link.duplex;
 715                         priv->oldduplex = phydev->duplex;
 716                 }
 717                 /* Flow Control operation */
 718                 if (phydev->pause)
 719                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 720                                                  fc, pause_time);
 721
 722                 if (phydev->speed != priv->speed) {
 723                         new_state = 1;
 724                         switch (phydev->speed) {
 725                         case 1000:
 726                                 if (likely(priv->plat->has_gmac))
 727                                         ctrl &= ~priv->hw->link.port;
 728                                 stmmac_hw_fix_mac_speed(priv);
 729                                 break;
 730                         case 100:
 731                         case 10:
 732                                 if (priv->plat->has_gmac) {
 733                                         ctrl |= priv->hw->link.port;
 734                                         if (phydev->speed == SPEED_100) {
 735                                                 ctrl |= priv->hw->link.speed;
 736                                         } else {
 737                                                 ctrl &= ~(priv->hw->link.speed);
 738                                         }
 739                                 } else {
 740                                         ctrl &= ~priv->hw->link.port;
 741                                 }
 742                                 stmmac_hw_fix_mac_speed(priv);
 743                                 break;
 744                         default:
 745                                 if (netif_msg_link(priv))
 746                                         pr_warn("%s: Speed (%d) not 10/100\n",
 747                                                 dev->name, phydev->speed);
 748                                 break;
 749                         }
 750
 751                         priv->speed = phydev->speed;
 752                 }
 753
 754                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 755
 756                 if (!priv->oldlink) {
 757                         new_state = 1;
 758                         priv->oldlink = 1;
 759                 }
 760         } else if (priv->oldlink) {
 761                 new_state = 1;
 762                 priv->oldlink = 0;
 763                 priv->speed = 0;
 764                 priv->oldduplex = -1;
 765         }
 766
 767         if (new_state && netif_msg_link(priv))
 768                 phy_print_status(phydev);
 769
 770         spin_unlock_irqrestore(&priv->lock, flags);
 771
 772         /* At this stage, it could be needed to setup the EEE or adjust some
 773          * MAC related HW registers.
 774          */
 775         priv->eee_enabled = stmmac_eee_init(priv);
 776 }
 777
 778 /**
 779  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 780  * @priv: driver private structure
 781  * Description: this is to verify if the HW supports the PCS.
 782  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 783  * configured for the TBI, RTBI, or SGMII PHY interface.
 784  */
 785 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 786 {
 787         int interface = priv->plat->interface;
 788
 789         if (priv->dma_cap.pcs) {
 790                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 791                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 792                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 793                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 794                         pr_debug("STMMAC: PCS RGMII support enable\n");
 795                         priv->pcs = STMMAC_PCS_RGMII;
 796                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 797                         pr_debug("STMMAC: PCS SGMII support enable\n");
 798                         priv->pcs = STMMAC_PCS_SGMII;
 799                 }
 800         }
 801 }
 802
 803 /**
 804  * stmmac_init_phy - PHY initialization
 805  * @dev: net device structure
 806  * Description: it initializes the driver's PHY state, and attaches the PHY
 807  * to the mac driver.
 808  *  Return value:
 809  *  0 on success
 810  */
 811 static int stmmac_init_phy(struct net_device *dev)
 812 {
 813         struct stmmac_priv *priv = netdev_priv(dev);
 814         struct phy_device *phydev;
 815         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 816         char bus_id[MII_BUS_ID_SIZE];
 817         int interface = priv->plat->interface;
 818         int max_speed = priv->plat->max_speed;
 819         priv->oldlink = 0;
 820         priv->speed = 0;
 821         priv->oldduplex = -1;
 822
 823         if (priv->plat->phy_node) {
 824                 phydev = of_phy_connect(dev, priv->plat->phy_node,
 825                                         &stmmac_adjust_link, 0, interface);
 826         } else {
 827                 if (priv->plat->phy_bus_name)
 828                         snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 829                                  priv->plat->phy_bus_name, priv->plat->bus_id);
 830                 else
 831                         snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 832                                  priv->plat->bus_id);
 833
 834                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 835                          priv->plat->phy_addr);
 836                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
 837                          phy_id_fmt);
 838
 839                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
 840                                      interface);
 841         }
 842
 843         if (IS_ERR_OR_NULL(phydev)) {
 844                 pr_err("%s: Could not attach to PHY\n", dev->name);
 845                 if (!phydev)
 846                         return -ENODEV;
 847
 848                 return PTR_ERR(phydev);
 849         }
 850
 851         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 852         if ((interface == PHY_INTERFACE_MODE_MII) ||
 853             (interface == PHY_INTERFACE_MODE_RMII) ||
 854                 (max_speed < 1000 && max_speed > 0))
 855                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 856                                          SUPPORTED_1000baseT_Full);
 857
 858         /*
 859          * Broken HW is sometimes missing the pull-up resistor on the
 860          * MDIO line, which results in reads to non-existent devices returning
 861          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 862          * device as well.
 863          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 864          */
 865         if (!priv->plat->phy_node && phydev->phy_id == 0) {
 866                 phy_disconnect(phydev);
 867                 return -ENODEV;
 868         }
 869         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 870                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 871
 872         priv->phydev = phydev;
 873
 874         return 0;
 875 }
 876
 877 /**
 878  * stmmac_display_ring - display ring
 879  * @head: pointer to the head of the ring passed.
 880  * @size: size of the ring.
 881  * @extend_desc: to verify if extended descriptors are used.
 882  * Description: display the control/status and buffer descriptors.
 883  */
 884 static void stmmac_display_ring(void *head, int size, int extend_desc)
 885 {
 886         int i;
 887         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 888         struct dma_desc *p = (struct dma_desc *)head;
 889
 890         for (i = 0; i < size; i++) {
 891                 u64 x;
 892                 if (extend_desc) {
 893                         x = *(u64 *) ep;
 894                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 895                                 i, (unsigned int)virt_to_phys(ep),
 896                                 (unsigned int)x, (unsigned int)(x >> 32),
 897                                 ep->basic.des2, ep->basic.des3);
 898                         ep++;
 899                 } else {
 900                         x = *(u64 *) p;
 901                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 902                                 i, (unsigned int)virt_to_phys(p),
 903                                 (unsigned int)x, (unsigned int)(x >> 32),
 904                                 p->des2, p->des3);
 905                         p++;
 906                 }
 907                 pr_info("\n");
 908         }
 909 }
 910
 911 static void stmmac_display_rings(struct stmmac_priv *priv)
 912 {
 913         if (priv->extend_desc) {
 914                 pr_info("Extended RX descriptor ring:\n");
 915                 stmmac_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1);
 916                 pr_info("Extended TX descriptor ring:\n");
 917                 stmmac_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1);
 918         } else {
 919                 pr_info("RX descriptor ring:\n");
 920                 stmmac_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0);
 921                 pr_info("TX descriptor ring:\n");
 922                 stmmac_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0);
 923         }
 924 }
 925
 926 static int stmmac_set_bfsize(int mtu, int bufsize)
 927 {
 928         int ret = bufsize;
 929
 930         if (mtu >= BUF_SIZE_4KiB)
 931                 ret = BUF_SIZE_8KiB;
 932         else if (mtu >= BUF_SIZE_2KiB)
 933                 ret = BUF_SIZE_4KiB;
 934         else if (mtu > DEFAULT_BUFSIZE)
 935                 ret = BUF_SIZE_2KiB;
 936         else
 937                 ret = DEFAULT_BUFSIZE;
 938
 939         return ret;
 940 }
 941
 942 /**
 943  * stmmac_clear_descriptors - clear descriptors
 944  * @priv: driver private structure
 945  * Description: this function is called to clear the tx and rx descriptors
 946  * in case of both basic and extended descriptors are used.
 947  */
 948 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 949 {
 950         int i;
 951
 952         /* Clear the Rx/Tx descriptors */
 953         for (i = 0; i < DMA_RX_SIZE; i++)
 954                 if (priv->extend_desc)
 955                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 956                                                      priv->use_riwt, priv->mode,
 957                                                      (i == DMA_RX_SIZE - 1));
 958                 else
 959                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 960                                                      priv->use_riwt, priv->mode,
 961                                                      (i == DMA_RX_SIZE - 1));
 962         for (i = 0; i < DMA_TX_SIZE; i++)
 963                 if (priv->extend_desc)
 964                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 965                                                      priv->mode,
 966                                                      (i == DMA_TX_SIZE - 1));
 967                 else
 968                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 969                                                      priv->mode,
 970                                                      (i == DMA_TX_SIZE - 1));
 971 }
 972
 973 /**
 974  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 975  * @priv: driver private structure
 976  * @p: descriptor pointer
 977  * @i: descriptor index
 978  * @flags: gfp flag.
 979  * Description: this function is called to allocate a receive buffer, perform
 980  * the DMA mapping and init the descriptor.
 981  */
 982 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 983                                   int i, gfp_t flags)
 984 {
 985         struct sk_buff *skb;
 986
 987         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
 988         if (!skb) {
 989                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 990                 return -ENOMEM;
 991         }
 992         priv->rx_skbuff[i] = skb;
 993         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 994                                                 priv->dma_buf_sz,
 995                                                 DMA_FROM_DEVICE);
 996         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 997                 pr_err("%s: DMA mapping error\n", __func__);
 998                 dev_kfree_skb_any(skb);
 999                 return -EINVAL;
1000         }
1001
1002         p->des2 = priv->rx_skbuff_dma[i];
1003
1004         if ((priv->hw->mode->init_desc3) &&
1005             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1006                 priv->hw->mode->init_desc3(p);
1007
1008         return 0;
1009 }
1010
1011 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1012 {
1013         if (priv->rx_skbuff[i]) {
1014                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1015                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1016                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1017         }
1018         priv->rx_skbuff[i] = NULL;
1019 }
1020
1021 /**
1022  * init_dma_desc_rings - init the RX/TX descriptor rings
1023  * @dev: net device structure
1024  * @flags: gfp flag.
1025  * Description: this function initializes the DMA RX/TX descriptors
1026  * and allocates the socket buffers. It suppors the chained and ring
1027  * modes.
1028  */
1029 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1030 {
1031         int i;
1032         struct stmmac_priv *priv = netdev_priv(dev);
1033         unsigned int bfsize = 0;
1034         int ret = -ENOMEM;
1035
1036         if (priv->hw->mode->set_16kib_bfsize)
1037                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1038
1039         if (bfsize < BUF_SIZE_16KiB)
1040                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1041
1042         priv->dma_buf_sz = bfsize;
1043
1044         if (netif_msg_probe(priv)) {
1045                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1046                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1047
1048                 /* RX INITIALIZATION */
1049                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1050         }
1051         for (i = 0; i < DMA_RX_SIZE; i++) {
1052                 struct dma_desc *p;
1053                 if (priv->extend_desc)
1054                         p = &((priv->dma_erx + i)->basic);
1055                 else
1056                         p = priv->dma_rx + i;
1057
1058                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1059                 if (ret)
1060                         goto err_init_rx_buffers;
1061
1062                 if (netif_msg_probe(priv))
1063                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1064                                  priv->rx_skbuff[i]->data,
1065                                  (unsigned int)priv->rx_skbuff_dma[i]);
1066         }
1067         priv->cur_rx = 0;
1068         priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1069         buf_sz = bfsize;
1070
1071         /* Setup the chained descriptor addresses */
1072         if (priv->mode == STMMAC_CHAIN_MODE) {
1073                 if (priv->extend_desc) {
1074                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1075                                              DMA_RX_SIZE, 1);
1076                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1077                                              DMA_TX_SIZE, 1);
1078                 } else {
1079                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1080                                              DMA_RX_SIZE, 0);
1081                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1082                                              DMA_TX_SIZE, 0);
1083                 }
1084         }
1085
1086         /* TX INITIALIZATION */
1087         for (i = 0; i < DMA_TX_SIZE; i++) {
1088                 struct dma_desc *p;
1089                 if (priv->extend_desc)
1090                         p = &((priv->dma_etx + i)->basic);
1091                 else
1092                         p = priv->dma_tx + i;
1093                 p->des2 = 0;
1094                 priv->tx_skbuff_dma[i].buf = 0;
1095                 priv->tx_skbuff_dma[i].map_as_page = false;
1096                 priv->tx_skbuff_dma[i].len = 0;
1097                 priv->tx_skbuff_dma[i].last_segment = false;
1098                 priv->tx_skbuff[i] = NULL;
1099         }
1100
1101         priv->dirty_tx = 0;
1102         priv->cur_tx = 0;
1103         netdev_reset_queue(priv->dev);
1104
1105         stmmac_clear_descriptors(priv);
1106
1107         if (netif_msg_hw(priv))
1108                 stmmac_display_rings(priv);
1109
1110         return 0;
1111 err_init_rx_buffers:
1112         while (--i >= 0)
1113                 stmmac_free_rx_buffers(priv, i);
1114         return ret;
1115 }
1116
1117 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1118 {
1119         int i;
1120
1121         for (i = 0; i < DMA_RX_SIZE; i++)
1122                 stmmac_free_rx_buffers(priv, i);
1123 }
1124
1125 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1126 {
1127         int i;
1128
1129         for (i = 0; i < DMA_TX_SIZE; i++) {
1130                 struct dma_desc *p;
1131
1132                 if (priv->extend_desc)
1133                         p = &((priv->dma_etx + i)->basic);
1134                 else
1135                         p = priv->dma_tx + i;
1136
1137                 if (priv->tx_skbuff_dma[i].buf) {
1138                         if (priv->tx_skbuff_dma[i].map_as_page)
1139                                 dma_unmap_page(priv->device,
1140                                                priv->tx_skbuff_dma[i].buf,
1141                                                priv->tx_skbuff_dma[i].len,
1142                                                DMA_TO_DEVICE);
1143                         else
1144                                 dma_unmap_single(priv->device,
1145                                                  priv->tx_skbuff_dma[i].buf,
1146                                                  priv->tx_skbuff_dma[i].len,
1147                                                  DMA_TO_DEVICE);
1148                 }
1149
1150                 if (priv->tx_skbuff[i] != NULL) {
1151                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1152                         priv->tx_skbuff[i] = NULL;
1153                         priv->tx_skbuff_dma[i].buf = 0;
1154                         priv->tx_skbuff_dma[i].map_as_page = false;
1155                 }
1156         }
1157 }
1158
1159 /**
1160  * alloc_dma_desc_resources - alloc TX/RX resources.
1161  * @priv: private structure
1162  * Description: according to which descriptor can be used (extend or basic)
1163  * this function allocates the resources for TX and RX paths. In case of
1164  * reception, for example, it pre-allocated the RX socket buffer in order to
1165  * allow zero-copy mechanism.
1166  */
1167 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1168 {
1169         int ret = -ENOMEM;
1170
1171         priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1172                                             GFP_KERNEL);
1173         if (!priv->rx_skbuff_dma)
1174                 return -ENOMEM;
1175
1176         priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1177                                         GFP_KERNEL);
1178         if (!priv->rx_skbuff)
1179                 goto err_rx_skbuff;
1180
1181         priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1182                                             sizeof(*priv->tx_skbuff_dma),
1183                                             GFP_KERNEL);
1184         if (!priv->tx_skbuff_dma)
1185                 goto err_tx_skbuff_dma;
1186
1187         priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1188                                         GFP_KERNEL);
1189         if (!priv->tx_skbuff)
1190                 goto err_tx_skbuff;
1191
1192         if (priv->extend_desc) {
1193                 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1194                                                     sizeof(struct
1195                                                            dma_extended_desc),
1196                                                     &priv->dma_rx_phy,
1197                                                     GFP_KERNEL);
1198                 if (!priv->dma_erx)
1199                         goto err_dma;
1200
1201                 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1202                                                     sizeof(struct
1203                                                            dma_extended_desc),
1204                                                     &priv->dma_tx_phy,
1205                                                     GFP_KERNEL);
1206                 if (!priv->dma_etx) {
1207                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1208                                           sizeof(struct dma_extended_desc),
1209                                           priv->dma_erx, priv->dma_rx_phy);
1210                         goto err_dma;
1211                 }
1212         } else {
1213                 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1214                                                    sizeof(struct dma_desc),
1215                                                    &priv->dma_rx_phy,
1216                                                    GFP_KERNEL);
1217                 if (!priv->dma_rx)
1218                         goto err_dma;
1219
1220                 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1221                                                    sizeof(struct dma_desc),
1222                                                    &priv->dma_tx_phy,
1223                                                    GFP_KERNEL);
1224                 if (!priv->dma_tx) {
1225                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1226                                           sizeof(struct dma_desc),
1227                                           priv->dma_rx, priv->dma_rx_phy);
1228                         goto err_dma;
1229                 }
1230         }
1231
1232         return 0;
1233
1234 err_dma:
1235         kfree(priv->tx_skbuff);
1236 err_tx_skbuff:
1237         kfree(priv->tx_skbuff_dma);
1238 err_tx_skbuff_dma:
1239         kfree(priv->rx_skbuff);
1240 err_rx_skbuff:
1241         kfree(priv->rx_skbuff_dma);
1242         return ret;
1243 }
1244
1245 static void free_dma_desc_resources(struct stmmac_priv *priv)
1246 {
1247         /* Release the DMA TX/RX socket buffers */
1248         dma_free_rx_skbufs(priv);
1249         dma_free_tx_skbufs(priv);
1250
1251         /* Free DMA regions of consistent memory previously allocated */
1252         if (!priv->extend_desc) {
1253                 dma_free_coherent(priv->device,
1254                                   DMA_TX_SIZE * sizeof(struct dma_desc),
1255                                   priv->dma_tx, priv->dma_tx_phy);
1256                 dma_free_coherent(priv->device,
1257                                   DMA_RX_SIZE * sizeof(struct dma_desc),
1258                                   priv->dma_rx, priv->dma_rx_phy);
1259         } else {
1260                 dma_free_coherent(priv->device, DMA_TX_SIZE *
1261                                   sizeof(struct dma_extended_desc),
1262                                   priv->dma_etx, priv->dma_tx_phy);
1263                 dma_free_coherent(priv->device, DMA_RX_SIZE *
1264                                   sizeof(struct dma_extended_desc),
1265                                   priv->dma_erx, priv->dma_rx_phy);
1266         }
1267         kfree(priv->rx_skbuff_dma);
1268         kfree(priv->rx_skbuff);
1269         kfree(priv->tx_skbuff_dma);
1270         kfree(priv->tx_skbuff);
1271 }
1272
1273 /**
1274  *  stmmac_dma_operation_mode - HW DMA operation mode
1275  *  @priv: driver private structure
1276  *  Description: it is used for configuring the DMA operation mode register in
1277  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1278  */
1279 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1280 {
1281         int rxfifosz = priv->plat->rx_fifo_size;
1282
1283         if (priv->plat->force_thresh_dma_mode)
1284                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1285         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1286                 /*
1287                  * In case of GMAC, SF mode can be enabled
1288                  * to perform the TX COE in HW. This depends on:
1289                  * 1) TX COE if actually supported
1290                  * 2) There is no bugged Jumbo frame support
1291                  *    that needs to not insert csum in the TDES.
1292                  */
1293                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1294                                         rxfifosz);
1295                 priv->xstats.threshold = SF_DMA_MODE;
1296         } else
1297                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1298                                         rxfifosz);
1299 }
1300
1301 /**
1302  * stmmac_tx_clean - to manage the transmission completion
1303  * @priv: driver private structure
1304  * Description: it reclaims the transmit resources after transmission completes.
1305  */
1306 static void stmmac_tx_clean(struct stmmac_priv *priv)
1307 {
1308         unsigned int bytes_compl = 0, pkts_compl = 0;
1309         unsigned int entry = priv->dirty_tx;
1310
1311         spin_lock(&priv->tx_lock);
1312
1313         priv->xstats.tx_clean++;
1314
1315         while (entry != priv->cur_tx) {
1316                 struct sk_buff *skb = priv->tx_skbuff[entry];
1317                 struct dma_desc *p;
1318                 int status;
1319
1320                 if (priv->extend_desc)
1321                         p = (struct dma_desc *)(priv->dma_etx + entry);
1322                 else
1323                         p = priv->dma_tx + entry;
1324
1325                 status = priv->hw->desc->tx_status(&priv->dev->stats,
1326                                                       &priv->xstats, p,
1327                                                       priv->ioaddr);
1328                 /* Check if the descriptor is owned by the DMA */
1329                 if (unlikely(status & tx_dma_own))
1330                         break;
1331
1332                 /* Just consider the last segment and ...*/
1333                 if (likely(!(status & tx_not_ls))) {
1334                         /* ... verify the status error condition */
1335                         if (unlikely(status & tx_err)) {
1336                                 priv->dev->stats.tx_errors++;
1337                         } else {
1338                                 priv->dev->stats.tx_packets++;
1339                                 priv->xstats.tx_pkt_n++;
1340                         }
1341                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1342                 }
1343                 if (netif_msg_tx_done(priv))
1344                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1345                                  priv->cur_tx, priv->dirty_tx);
1346
1347                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1348                         if (priv->tx_skbuff_dma[entry].map_as_page)
1349                                 dma_unmap_page(priv->device,
1350                                                priv->tx_skbuff_dma[entry].buf,
1351                                                priv->tx_skbuff_dma[entry].len,
1352                                                DMA_TO_DEVICE);
1353                         else
1354                                 dma_unmap_single(priv->device,
1355                                                  priv->tx_skbuff_dma[entry].buf,
1356                                                  priv->tx_skbuff_dma[entry].len,
1357                                                  DMA_TO_DEVICE);
1358                         priv->tx_skbuff_dma[entry].buf = 0;
1359                         priv->tx_skbuff_dma[entry].map_as_page = false;
1360                 }
1361                 priv->hw->mode->clean_desc3(priv, p);
1362                 priv->tx_skbuff_dma[entry].last_segment = false;
1363                 priv->tx_skbuff_dma[entry].is_jumbo = false;
1364
1365                 if (likely(skb != NULL)) {
1366                         pkts_compl++;
1367                         bytes_compl += skb->len;
1368                         dev_consume_skb_any(skb);
1369                         priv->tx_skbuff[entry] = NULL;
1370                 }
1371
1372                 priv->hw->desc->release_tx_desc(p, priv->mode);
1373
1374                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1375                 priv->dirty_tx = entry;
1376         }
1377
1378         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1379
1380         if (unlikely(netif_queue_stopped(priv->dev) &&
1381                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1382                 netif_tx_lock(priv->dev);
1383                 if (netif_queue_stopped(priv->dev) &&
1384                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
1385                         if (netif_msg_tx_done(priv))
1386                                 pr_debug("%s: restart transmit\n", __func__);
1387                         netif_wake_queue(priv->dev);
1388                 }
1389                 netif_tx_unlock(priv->dev);
1390         }
1391
1392         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1393                 stmmac_enable_eee_mode(priv);
1394                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1395         }
1396         spin_unlock(&priv->tx_lock);
1397 }
1398
1399 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1400 {
1401         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1402 }
1403
1404 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1405 {
1406         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1407 }
1408
1409 /**
1410  * stmmac_tx_err - to manage the tx error
1411  * @priv: driver private structure
1412  * Description: it cleans the descriptors and restarts the transmission
1413  * in case of transmission errors.
1414  */
1415 static void stmmac_tx_err(struct stmmac_priv *priv)
1416 {
1417         int i;
1418         netif_stop_queue(priv->dev);
1419
1420         priv->hw->dma->stop_tx(priv->ioaddr);
1421         dma_free_tx_skbufs(priv);
1422         for (i = 0; i < DMA_TX_SIZE; i++)
1423                 if (priv->extend_desc)
1424                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1425                                                      priv->mode,
1426                                                      (i == DMA_TX_SIZE - 1));
1427                 else
1428                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1429                                                      priv->mode,
1430                                                      (i == DMA_TX_SIZE - 1));
1431         priv->dirty_tx = 0;
1432         priv->cur_tx = 0;
1433         netdev_reset_queue(priv->dev);
1434         priv->hw->dma->start_tx(priv->ioaddr);
1435
1436         priv->dev->stats.tx_errors++;
1437         netif_wake_queue(priv->dev);
1438 }
1439
1440 /**
1441  * stmmac_dma_interrupt - DMA ISR
1442  * @priv: driver private structure
1443  * Description: this is the DMA ISR. It is called by the main ISR.
1444  * It calls the dwmac dma routine and schedule poll method in case of some
1445  * work can be done.
1446  */
1447 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1448 {
1449         int status;
1450         int rxfifosz = priv->plat->rx_fifo_size;
1451
1452         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1453         if (likely((status & handle_rx)) || (status & handle_tx)) {
1454                 if (likely(napi_schedule_prep(&priv->napi))) {
1455                         stmmac_disable_dma_irq(priv);
1456                         __napi_schedule(&priv->napi);
1457                 }
1458         }
1459         if (unlikely(status & tx_hard_error_bump_tc)) {
1460                 /* Try to bump up the dma threshold on this failure */
1461                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1462                     (tc <= 256)) {
1463                         tc += 64;
1464                         if (priv->plat->force_thresh_dma_mode)
1465                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1466                                                         rxfifosz);
1467                         else
1468                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1469                                                         SF_DMA_MODE, rxfifosz);
1470                         priv->xstats.threshold = tc;
1471                 }
1472         } else if (unlikely(status == tx_hard_error))
1473                 stmmac_tx_err(priv);
1474 }
1475
1476 /**
1477  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1478  * @priv: driver private structure
1479  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1480  */
1481 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1482 {
1483         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1484             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1485
1486         dwmac_mmc_intr_all_mask(priv->ioaddr);
1487
1488         if (priv->dma_cap.rmon) {
1489                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1490                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1491         } else
1492                 pr_info(" No MAC Management Counters available\n");
1493 }
1494
1495 /**
1496  * stmmac_get_synopsys_id - return the SYINID.
1497  * @priv: driver private structure
1498  * Description: this simple function is to decode and return the SYINID
1499  * starting from the HW core register.
1500  */
1501 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1502 {
1503         u32 hwid = priv->hw->synopsys_uid;
1504
1505         /* Check Synopsys Id (not available on old chips) */
1506         if (likely(hwid)) {
1507                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1508                 u32 synid = (hwid & 0x000000ff);
1509
1510                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1511                         uid, synid);
1512
1513                 return synid;
1514         }
1515         return 0;
1516 }
1517
1518 /**
1519  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1520  * @priv: driver private structure
1521  * Description: select the Enhanced/Alternate or Normal descriptors.
1522  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1523  * supported by the HW capability register.
1524  */
1525 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1526 {
1527         if (priv->plat->enh_desc) {
1528                 pr_info(" Enhanced/Alternate descriptors\n");
1529
1530                 /* GMAC older than 3.50 has no extended descriptors */
1531                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1532                         pr_info("\tEnabled extended descriptors\n");
1533                         priv->extend_desc = 1;
1534                 } else
1535                         pr_warn("Extended descriptors not supported\n");
1536
1537                 priv->hw->desc = &enh_desc_ops;
1538         } else {
1539                 pr_info(" Normal descriptors\n");
1540                 priv->hw->desc = &ndesc_ops;
1541         }
1542 }
1543
1544 /**
1545  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1546  * @priv: driver private structure
1547  * Description:
1548  *  new GMAC chip generations have a new register to indicate the
1549  *  presence of the optional feature/functions.
1550  *  This can be also used to override the value passed through the
1551  *  platform and necessary for old MAC10/100 and GMAC chips.
1552  */
1553 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1554 {
1555         u32 hw_cap = 0;
1556
1557         if (priv->hw->dma->get_hw_feature) {
1558                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1559
1560                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1561                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1562                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1563                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1564                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1565                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1566                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1567                 priv->dma_cap.pmt_remote_wake_up =
1568                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1569                 priv->dma_cap.pmt_magic_frame =
1570                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1571                 /* MMC */
1572                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1573                 /* IEEE 1588-2002 */
1574                 priv->dma_cap.time_stamp =
1575                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1576                 /* IEEE 1588-2008 */
1577                 priv->dma_cap.atime_stamp =
1578                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1579                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1580                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1581                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1582                 /* TX and RX csum */
1583                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1584                 priv->dma_cap.rx_coe_type1 =
1585                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1586                 priv->dma_cap.rx_coe_type2 =
1587                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1588                 priv->dma_cap.rxfifo_over_2048 =
1589                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1590                 /* TX and RX number of channels */
1591                 priv->dma_cap.number_rx_channel =
1592                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1593                 priv->dma_cap.number_tx_channel =
1594                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1595                 /* Alternate (enhanced) DESC mode */
1596                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1597         }
1598
1599         return hw_cap;
1600 }
1601
1602 /**
1603  * stmmac_check_ether_addr - check if the MAC addr is valid
1604  * @priv: driver private structure
1605  * Description:
1606  * it is to verify if the MAC address is valid, in case of failures it
1607  * generates a random MAC address
1608  */
1609 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1610 {
1611         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1612                 priv->hw->mac->get_umac_addr(priv->hw,
1613                                              priv->dev->dev_addr, 0);
1614                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1615                         eth_hw_addr_random(priv->dev);
1616                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1617                         priv->dev->dev_addr);
1618         }
1619 }
1620
1621 /**
1622  * stmmac_init_dma_engine - DMA init.
1623  * @priv: driver private structure
1624  * Description:
1625  * It inits the DMA invoking the specific MAC/GMAC callback.
1626  * Some DMA parameters can be passed from the platform;
1627  * in case of these are not passed a default is kept for the MAC or GMAC.
1628  */
1629 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1630 {
1631         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
1632         int mixed_burst = 0;
1633         int atds = 0;
1634         int ret = 0;
1635
1636         if (priv->plat->dma_cfg) {
1637                 pbl = priv->plat->dma_cfg->pbl;
1638                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1639                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1640                 aal = priv->plat->dma_cfg->aal;
1641         }
1642
1643         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1644                 atds = 1;
1645
1646         ret = priv->hw->dma->reset(priv->ioaddr);
1647         if (ret) {
1648                 dev_err(priv->device, "Failed to reset the dma\n");
1649                 return ret;
1650         }
1651
1652         priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1653                             aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
1654
1655         if ((priv->synopsys_id >= DWMAC_CORE_3_50) &&
1656             (priv->plat->axi && priv->hw->dma->axi))
1657                 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1658
1659         return ret;
1660 }
1661
1662 /**
1663  * stmmac_tx_timer - mitigation sw timer for tx.
1664  * @data: data pointer
1665  * Description:
1666  * This is the timer handler to directly invoke the stmmac_tx_clean.
1667  */
1668 static void stmmac_tx_timer(unsigned long data)
1669 {
1670         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1671
1672         stmmac_tx_clean(priv);
1673 }
1674
1675 /**
1676  * stmmac_init_tx_coalesce - init tx mitigation options.
1677  * @priv: driver private structure
1678  * Description:
1679  * This inits the transmit coalesce parameters: i.e. timer rate,
1680  * timer handler and default threshold used for enabling the
1681  * interrupt on completion bit.
1682  */
1683 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1684 {
1685         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1686         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1687         init_timer(&priv->txtimer);
1688         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1689         priv->txtimer.data = (unsigned long)priv;
1690         priv->txtimer.function = stmmac_tx_timer;
1691         add_timer(&priv->txtimer);
1692 }
1693
1694 /**
1695  * stmmac_hw_setup - setup mac in a usable state.
1696  *  @dev : pointer to the device structure.
1697  *  Description:
1698  *  this is the main function to setup the HW in a usable state because the
1699  *  dma engine is reset, the core registers are configured (e.g. AXI,
1700  *  Checksum features, timers). The DMA is ready to start receiving and
1701  *  transmitting.
1702  *  Return value:
1703  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1704  *  file on failure.
1705  */
1706 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1707 {
1708         struct stmmac_priv *priv = netdev_priv(dev);
1709         int ret;
1710
1711         /* DMA initialization and SW reset */
1712         ret = stmmac_init_dma_engine(priv);
1713         if (ret < 0) {
1714                 pr_err("%s: DMA engine initialization failed\n", __func__);
1715                 return ret;
1716         }
1717
1718         /* Copy the MAC addr into the HW  */
1719         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1720
1721         /* If required, perform hw setup of the bus. */
1722         if (priv->plat->bus_setup)
1723                 priv->plat->bus_setup(priv->ioaddr);
1724
1725         /* Initialize the MAC Core */
1726         priv->hw->mac->core_init(priv->hw, dev->mtu);
1727
1728         ret = priv->hw->mac->rx_ipc(priv->hw);
1729         if (!ret) {
1730                 pr_warn(" RX IPC Checksum Offload disabled\n");
1731                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1732                 priv->hw->rx_csum = 0;
1733         }
1734
1735         /* Enable the MAC Rx/Tx */
1736         stmmac_set_mac(priv->ioaddr, true);
1737
1738         /* Set the HW DMA mode and the COE */
1739         stmmac_dma_operation_mode(priv);
1740
1741         stmmac_mmc_setup(priv);
1742
1743         if (init_ptp) {
1744                 ret = stmmac_init_ptp(priv);
1745                 if (ret && ret != -EOPNOTSUPP)
1746                         pr_warn("%s: failed PTP initialisation\n", __func__);
1747         }
1748
1749 #ifdef CONFIG_DEBUG_FS
1750         ret = stmmac_init_fs(dev);
1751         if (ret < 0)
1752                 pr_warn("%s: failed debugFS registration\n", __func__);
1753 #endif
1754         /* Start the ball rolling... */
1755         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1756         priv->hw->dma->start_tx(priv->ioaddr);
1757         priv->hw->dma->start_rx(priv->ioaddr);
1758
1759         /* Dump DMA/MAC registers */
1760         if (netif_msg_hw(priv)) {
1761                 priv->hw->mac->dump_regs(priv->hw);
1762                 priv->hw->dma->dump_regs(priv->ioaddr);
1763         }
1764         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1765
1766         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1767                 priv->rx_riwt = MAX_DMA_RIWT;
1768                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1769         }
1770
1771         if (priv->pcs && priv->hw->mac->ctrl_ane)
1772                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1773
1774         return 0;
1775 }
1776
1777 /**
1778  *  stmmac_open - open entry point of the driver
1779  *  @dev : pointer to the device structure.
1780  *  Description:
1781  *  This function is the open entry point of the driver.
1782  *  Return value:
1783  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1784  *  file on failure.
1785  */
1786 static int stmmac_open(struct net_device *dev)
1787 {
1788         struct stmmac_priv *priv = netdev_priv(dev);
1789         int ret;
1790
1791         stmmac_check_ether_addr(priv);
1792
1793         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1794             priv->pcs != STMMAC_PCS_RTBI) {
1795                 ret = stmmac_init_phy(dev);
1796                 if (ret) {
1797                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1798                                __func__, ret);
1799                         return ret;
1800                 }
1801         }
1802
1803         /* Extra statistics */
1804         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1805         priv->xstats.threshold = tc;
1806
1807         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1808
1809         ret = alloc_dma_desc_resources(priv);
1810         if (ret < 0) {
1811                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1812                 goto dma_desc_error;
1813         }
1814
1815         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1816         if (ret < 0) {
1817                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1818                 goto init_error;
1819         }
1820
1821         ret = stmmac_hw_setup(dev, true);
1822         if (ret < 0) {
1823                 pr_err("%s: Hw setup failed\n", __func__);
1824                 goto init_error;
1825         }
1826
1827         stmmac_init_tx_coalesce(priv);
1828
1829         if (priv->phydev)
1830                 phy_start(priv->phydev);
1831
1832         /* Request the IRQ lines */
1833         ret = request_irq(dev->irq, stmmac_interrupt,
1834                           IRQF_SHARED, dev->name, dev);
1835         if (unlikely(ret < 0)) {
1836                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1837                        __func__, dev->irq, ret);
1838                 goto init_error;
1839         }
1840
1841         /* Request the Wake IRQ in case of another line is used for WoL */
1842         if (priv->wol_irq != dev->irq) {
1843                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1844                                   IRQF_SHARED, dev->name, dev);
1845                 if (unlikely(ret < 0)) {
1846                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1847                                __func__, priv->wol_irq, ret);
1848                         goto wolirq_error;
1849                 }
1850         }
1851
1852         /* Request the IRQ lines */
1853         if (priv->lpi_irq > 0) {
1854                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1855                                   dev->name, dev);
1856                 if (unlikely(ret < 0)) {
1857                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1858                                __func__, priv->lpi_irq, ret);
1859                         goto lpiirq_error;
1860                 }
1861         }
1862
1863         napi_enable(&priv->napi);
1864         netif_start_queue(dev);
1865
1866         return 0;
1867
1868 lpiirq_error:
1869         if (priv->wol_irq != dev->irq)
1870                 free_irq(priv->wol_irq, dev);
1871 wolirq_error:
1872         free_irq(dev->irq, dev);
1873
1874 init_error:
1875         free_dma_desc_resources(priv);
1876 dma_desc_error:
1877         if (priv->phydev)
1878                 phy_disconnect(priv->phydev);
1879
1880         return ret;
1881 }
1882
1883 /**
1884  *  stmmac_release - close entry point of the driver
1885  *  @dev : device pointer.
1886  *  Description:
1887  *  This is the stop entry point of the driver.
1888  */
1889 static int stmmac_release(struct net_device *dev)
1890 {
1891         struct stmmac_priv *priv = netdev_priv(dev);
1892
1893         if (priv->eee_enabled)
1894                 del_timer_sync(&priv->eee_ctrl_timer);
1895
1896         /* Stop and disconnect the PHY */
1897         if (priv->phydev) {
1898                 phy_stop(priv->phydev);
1899                 phy_disconnect(priv->phydev);
1900                 priv->phydev = NULL;
1901         }
1902
1903         netif_stop_queue(dev);
1904
1905         napi_disable(&priv->napi);
1906
1907         del_timer_sync(&priv->txtimer);
1908
1909         /* Free the IRQ lines */
1910         free_irq(dev->irq, dev);
1911         if (priv->wol_irq != dev->irq)
1912                 free_irq(priv->wol_irq, dev);
1913         if (priv->lpi_irq > 0)
1914                 free_irq(priv->lpi_irq, dev);
1915
1916         /* Stop TX/RX DMA and clear the descriptors */
1917         priv->hw->dma->stop_tx(priv->ioaddr);
1918         priv->hw->dma->stop_rx(priv->ioaddr);
1919
1920         /* Release and free the Rx/Tx resources */
1921         free_dma_desc_resources(priv);
1922
1923         /* Disable the MAC Rx/Tx */
1924         stmmac_set_mac(priv->ioaddr, false);
1925
1926         netif_carrier_off(dev);
1927
1928 #ifdef CONFIG_DEBUG_FS
1929         stmmac_exit_fs(dev);
1930 #endif
1931
1932         stmmac_release_ptp(priv);
1933
1934         return 0;
1935 }
1936
1937 /**
1938  *  stmmac_xmit - Tx entry point of the driver
1939  *  @skb : the socket buffer
1940  *  @dev : device pointer
1941  *  Description : this is the tx entry point of the driver.
1942  *  It programs the chain or the ring and supports oversized frames
1943  *  and SG feature.
1944  */
1945 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1946 {
1947         struct stmmac_priv *priv = netdev_priv(dev);
1948         int entry;
1949         int i, csum_insertion = 0, is_jumbo = 0;
1950         int nfrags = skb_shinfo(skb)->nr_frags;
1951         struct dma_desc *desc, *first;
1952         unsigned int nopaged_len = skb_headlen(skb);
1953         unsigned int enh_desc = priv->plat->enh_desc;
1954
1955         spin_lock(&priv->tx_lock);
1956
1957         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1958                 spin_unlock(&priv->tx_lock);
1959                 if (!netif_queue_stopped(dev)) {
1960                         netif_stop_queue(dev);
1961                         /* This is a hard error, log it. */
1962                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1963                 }
1964                 return NETDEV_TX_BUSY;
1965         }
1966
1967         if (priv->tx_path_in_lpi_mode)
1968                 stmmac_disable_eee_mode(priv);
1969
1970         entry = priv->cur_tx;
1971
1972
1973         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1974
1975         if (priv->extend_desc)
1976                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1977         else
1978                 desc = priv->dma_tx + entry;
1979
1980         first = desc;
1981
1982         /* To program the descriptors according to the size of the frame */
1983         if (enh_desc)
1984                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1985
1986         if (likely(!is_jumbo)) {
1987                 desc->des2 = dma_map_single(priv->device, skb->data,
1988                                             nopaged_len, DMA_TO_DEVICE);
1989                 if (dma_mapping_error(priv->device, desc->des2))
1990                         goto dma_map_err;
1991                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1992                 priv->tx_skbuff_dma[entry].len = nopaged_len;
1993                 /* do not set the own at this stage */
1994                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1995                                                 csum_insertion, priv->mode, 0,
1996                                                 nfrags == 0);
1997         } else {
1998                 desc = first;
1999                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2000                 if (unlikely(entry < 0))
2001                         goto dma_map_err;
2002         }
2003
2004         for (i = 0; i < nfrags; i++) {
2005                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2006                 int len = skb_frag_size(frag);
2007                 bool last_segment = (i == (nfrags - 1));
2008
2009                 priv->tx_skbuff[entry] = NULL;
2010                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2011
2012                 if (priv->extend_desc)
2013                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2014                 else
2015                         desc = priv->dma_tx + entry;
2016
2017                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2018                                               DMA_TO_DEVICE);
2019                 if (dma_mapping_error(priv->device, desc->des2))
2020                         goto dma_map_err; /* should reuse desc w/o issues */
2021
2022                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2023                 priv->tx_skbuff_dma[entry].map_as_page = true;
2024                 priv->tx_skbuff_dma[entry].len = len;
2025                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2026                                                 priv->mode, 1, last_segment);
2027                 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2028         }
2029
2030         priv->tx_skbuff[entry] = skb;
2031
2032         /* According to the coalesce parameter the IC bit for the latest
2033          * segment could be reset and the timer re-started to invoke the
2034          * stmmac_tx function. This approach takes care about the fragments.
2035          */
2036         priv->tx_count_frames += nfrags + 1;
2037         if (priv->tx_coal_frames > priv->tx_count_frames) {
2038                 priv->hw->desc->clear_tx_ic(desc);
2039                 priv->xstats.tx_reset_ic_bit++;
2040                 mod_timer(&priv->txtimer,
2041                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2042         } else
2043                 priv->tx_count_frames = 0;
2044
2045         /* To avoid raise condition */
2046         priv->hw->desc->set_tx_owner(first);
2047         wmb();
2048
2049         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2050
2051         priv->cur_tx = entry;
2052
2053         if (netif_msg_pktdata(priv)) {
2054                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2055                         __func__, (priv->cur_tx % DMA_TX_SIZE),
2056                         (priv->dirty_tx % DMA_TX_SIZE), entry, first, nfrags);
2057
2058                 if (priv->extend_desc)
2059                         stmmac_display_ring((void *)priv->dma_etx,
2060                                             DMA_TX_SIZE, 1);
2061                 else
2062                         stmmac_display_ring((void *)priv->dma_tx,
2063                                             DMA_TX_SIZE, 0);
2064
2065                 pr_debug(">>> frame to be transmitted: ");
2066                 print_pkt(skb->data, skb->len);
2067         }
2068         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2069                 if (netif_msg_hw(priv))
2070                         pr_debug("%s: stop transmitted packets\n", __func__);
2071                 netif_stop_queue(dev);
2072         }
2073
2074         dev->stats.tx_bytes += skb->len;
2075
2076         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2077                      priv->hwts_tx_en)) {
2078                 /* declare that device is doing timestamping */
2079                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2080                 priv->hw->desc->enable_tx_timestamp(first);
2081         }
2082
2083         if (!priv->hwts_tx_en)
2084                 skb_tx_timestamp(skb);
2085
2086         netdev_sent_queue(dev, skb->len);
2087         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2088
2089         spin_unlock(&priv->tx_lock);
2090         return NETDEV_TX_OK;
2091
2092 dma_map_err:
2093         spin_unlock(&priv->tx_lock);
2094         dev_err(priv->device, "Tx dma map failed\n");
2095         dev_kfree_skb(skb);
2096         priv->dev->stats.tx_dropped++;
2097         return NETDEV_TX_OK;
2098 }
2099
2100 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2101 {
2102         struct ethhdr *ehdr;
2103         u16 vlanid;
2104
2105         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2106             NETIF_F_HW_VLAN_CTAG_RX &&
2107             !__vlan_get_tag(skb, &vlanid)) {
2108                 /* pop the vlan tag */
2109                 ehdr = (struct ethhdr *)skb->data;
2110                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2111                 skb_pull(skb, VLAN_HLEN);
2112                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2113         }
2114 }
2115
2116
2117 /**
2118  * stmmac_rx_refill - refill used skb preallocated buffers
2119  * @priv: driver private structure
2120  * Description : this is to reallocate the skb for the reception process
2121  * that is based on zero-copy.
2122  */
2123 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2124 {
2125         int bfsize = priv->dma_buf_sz;
2126         unsigned int entry = priv->dirty_rx;
2127         int dirty = stmmac_rx_dirty(priv);
2128
2129         while (dirty-- > 0) {
2130                 struct dma_desc *p;
2131
2132                 if (priv->extend_desc)
2133                         p = (struct dma_desc *)(priv->dma_erx + entry);
2134                 else
2135                         p = priv->dma_rx + entry;
2136
2137                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2138                         struct sk_buff *skb;
2139
2140                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2141
2142                         if (unlikely(skb == NULL))
2143                                 break;
2144
2145                         priv->rx_skbuff[entry] = skb;
2146                         priv->rx_skbuff_dma[entry] =
2147                             dma_map_single(priv->device, skb->data, bfsize,
2148                                            DMA_FROM_DEVICE);
2149                         if (dma_mapping_error(priv->device,
2150                                               priv->rx_skbuff_dma[entry])) {
2151                                 dev_err(priv->device, "Rx dma map failed\n");
2152                                 dev_kfree_skb(skb);
2153                                 break;
2154                         }
2155                         p->des2 = priv->rx_skbuff_dma[entry];
2156
2157                         priv->hw->mode->refill_desc3(priv, p);
2158
2159                         if (netif_msg_rx_status(priv))
2160                                 pr_debug("\trefill entry #%d\n", entry);
2161                 }
2162                 wmb();
2163                 priv->hw->desc->set_rx_owner(p);
2164                 wmb();
2165
2166                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2167         }
2168         priv->dirty_rx = entry;
2169 }
2170
2171 /**
2172  * stmmac_rx - manage the receive process
2173  * @priv: driver private structure
2174  * @limit: napi bugget.
2175  * Description :  this the function called by the napi poll method.
2176  * It gets all the frames inside the ring.
2177  */
2178 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2179 {
2180         unsigned int entry = priv->cur_rx;
2181         unsigned int next_entry;
2182         unsigned int count = 0;
2183         int coe = priv->hw->rx_csum;
2184
2185         if (netif_msg_rx_status(priv)) {
2186                 pr_debug("%s: descriptor ring:\n", __func__);
2187                 if (priv->extend_desc)
2188                         stmmac_display_ring((void *)priv->dma_erx,
2189                                             DMA_RX_SIZE, 1);
2190                 else
2191                         stmmac_display_ring((void *)priv->dma_rx,
2192                                             DMA_RX_SIZE, 0);
2193         }
2194         while (count < limit) {
2195                 int status;
2196                 struct dma_desc *p;
2197
2198                 if (priv->extend_desc)
2199                         p = (struct dma_desc *)(priv->dma_erx + entry);
2200                 else
2201                         p = priv->dma_rx + entry;
2202
2203                 /* read the status of the incoming frame */
2204                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2205                                                    &priv->xstats, p);
2206                 /* check if managed by the DMA otherwise go ahead */
2207                 if (unlikely(status & dma_own))
2208                         break;
2209
2210                 count++;
2211
2212                 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2213                 next_entry = priv->cur_rx;
2214
2215                 if (priv->extend_desc)
2216                         prefetch(priv->dma_erx + next_entry);
2217                 else
2218                         prefetch(priv->dma_rx + next_entry);
2219
2220                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2221                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2222                                                            &priv->xstats,
2223                                                            priv->dma_erx +
2224                                                            entry);
2225                 if (unlikely(status == discard_frame)) {
2226                         priv->dev->stats.rx_errors++;
2227                         if (priv->hwts_rx_en && !priv->extend_desc) {
2228                                 /* DESC2 & DESC3 will be overwitten by device
2229                                  * with timestamp value, hence reinitialize
2230                                  * them in stmmac_rx_refill() function so that
2231                                  * device can reuse it.
2232                                  */
2233                                 priv->rx_skbuff[entry] = NULL;
2234                                 dma_unmap_single(priv->device,
2235                                                  priv->rx_skbuff_dma[entry],
2236                                                  priv->dma_buf_sz,
2237                                                  DMA_FROM_DEVICE);
2238                         }
2239                 } else {
2240                         struct sk_buff *skb;
2241                         int frame_len;
2242
2243                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2244
2245                         /*  check if frame_len fits the preallocated memory */
2246                         if (frame_len > priv->dma_buf_sz) {
2247                                 priv->dev->stats.rx_length_errors++;
2248                                 break;
2249                         }
2250
2251                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2252                          * Type frames (LLC/LLC-SNAP)
2253                          */
2254                         if (unlikely(status != llc_snap))
2255                                 frame_len -= ETH_FCS_LEN;
2256
2257                         if (netif_msg_rx_status(priv)) {
2258                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2259                                          p, entry, p->des2);
2260                                 if (frame_len > ETH_FRAME_LEN)
2261                                         pr_debug("\tframe size %d, COE: %d\n",
2262                                                  frame_len, status);
2263                         }
2264                         skb = priv->rx_skbuff[entry];
2265                         if (unlikely(!skb)) {
2266                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2267                                        priv->dev->name);
2268                                 priv->dev->stats.rx_dropped++;
2269                                 break;
2270                         }
2271                         prefetch(skb->data - NET_IP_ALIGN);
2272                         priv->rx_skbuff[entry] = NULL;
2273
2274                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2275
2276                         skb_put(skb, frame_len);
2277                         dma_unmap_single(priv->device,
2278                                          priv->rx_skbuff_dma[entry],
2279                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2280
2281                         if (netif_msg_pktdata(priv)) {
2282                                 pr_debug("frame received (%dbytes)", frame_len);
2283                                 print_pkt(skb->data, frame_len);
2284                         }
2285
2286                         stmmac_rx_vlan(priv->dev, skb);
2287
2288                         skb->protocol = eth_type_trans(skb, priv->dev);
2289
2290                         if (unlikely(!coe))
2291                                 skb_checksum_none_assert(skb);
2292                         else
2293                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2294
2295                         napi_gro_receive(&priv->napi, skb);
2296
2297                         priv->dev->stats.rx_packets++;
2298                         priv->dev->stats.rx_bytes += frame_len;
2299                 }
2300                 entry = next_entry;
2301         }
2302
2303         stmmac_rx_refill(priv);
2304
2305         priv->xstats.rx_pkt_n += count;
2306
2307         return count;
2308 }
2309
2310 /**
2311  *  stmmac_poll - stmmac poll method (NAPI)
2312  *  @napi : pointer to the napi structure.
2313  *  @budget : maximum number of packets that the current CPU can receive from
2314  *            all interfaces.
2315  *  Description :
2316  *  To look at the incoming frames and clear the tx resources.
2317  */
2318 static int stmmac_poll(struct napi_struct *napi, int budget)
2319 {
2320         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2321         int work_done = 0;
2322
2323         priv->xstats.napi_poll++;
2324         stmmac_tx_clean(priv);
2325
2326         work_done = stmmac_rx(priv, budget);
2327         if (work_done < budget) {
2328                 napi_complete(napi);
2329                 stmmac_enable_dma_irq(priv);
2330         }
2331         return work_done;
2332 }
2333
2334 /**
2335  *  stmmac_tx_timeout
2336  *  @dev : Pointer to net device structure
2337  *  Description: this function is called when a packet transmission fails to
2338  *   complete within a reasonable time. The driver will mark the error in the
2339  *   netdev structure and arrange for the device to be reset to a sane state
2340  *   in order to transmit a new packet.
2341  */
2342 static void stmmac_tx_timeout(struct net_device *dev)
2343 {
2344         struct stmmac_priv *priv = netdev_priv(dev);
2345
2346         /* Clear Tx resources and restart transmitting again */
2347         stmmac_tx_err(priv);
2348 }
2349
2350 /**
2351  *  stmmac_set_rx_mode - entry point for multicast addressing
2352  *  @dev : pointer to the device structure
2353  *  Description:
2354  *  This function is a driver entry point which gets called by the kernel
2355  *  whenever multicast addresses must be enabled/disabled.
2356  *  Return value:
2357  *  void.
2358  */
2359 static void stmmac_set_rx_mode(struct net_device *dev)
2360 {
2361         struct stmmac_priv *priv = netdev_priv(dev);
2362
2363         priv->hw->mac->set_filter(priv->hw, dev);
2364 }
2365
2366 /**
2367  *  stmmac_change_mtu - entry point to change MTU size for the device.
2368  *  @dev : device pointer.
2369  *  @new_mtu : the new MTU size for the device.
2370  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2371  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2372  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2373  *  Return value:
2374  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2375  *  file on failure.
2376  */
2377 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2378 {
2379         struct stmmac_priv *priv = netdev_priv(dev);
2380         int max_mtu;
2381
2382         if (netif_running(dev)) {
2383                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2384                 return -EBUSY;
2385         }
2386
2387         if (priv->plat->enh_desc)
2388                 max_mtu = JUMBO_LEN;
2389         else
2390                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2391
2392         if (priv->plat->maxmtu < max_mtu)
2393                 max_mtu = priv->plat->maxmtu;
2394
2395         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2396                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2397                 return -EINVAL;
2398         }
2399
2400         dev->mtu = new_mtu;
2401         netdev_update_features(dev);
2402
2403         return 0;
2404 }
2405
2406 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2407                                              netdev_features_t features)
2408 {
2409         struct stmmac_priv *priv = netdev_priv(dev);
2410
2411         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2412                 features &= ~NETIF_F_RXCSUM;
2413
2414         if (!priv->plat->tx_coe)
2415                 features &= ~NETIF_F_CSUM_MASK;
2416
2417         /* Some GMAC devices have a bugged Jumbo frame support that
2418          * needs to have the Tx COE disabled for oversized frames
2419          * (due to limited buffer sizes). In this case we disable
2420          * the TX csum insertionin the TDES and not use SF.
2421          */
2422         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2423                 features &= ~NETIF_F_CSUM_MASK;
2424
2425         return features;
2426 }
2427
2428 static int stmmac_set_features(struct net_device *netdev,
2429                                netdev_features_t features)
2430 {
2431         struct stmmac_priv *priv = netdev_priv(netdev);
2432
2433         /* Keep the COE Type in case of csum is supporting */
2434         if (features & NETIF_F_RXCSUM)
2435                 priv->hw->rx_csum = priv->plat->rx_coe;
2436         else
2437                 priv->hw->rx_csum = 0;
2438         /* No check needed because rx_coe has been set before and it will be
2439          * fixed in case of issue.
2440          */
2441         priv->hw->mac->rx_ipc(priv->hw);
2442
2443         return 0;
2444 }
2445
2446 /**
2447  *  stmmac_interrupt - main ISR
2448  *  @irq: interrupt number.
2449  *  @dev_id: to pass the net device pointer.
2450  *  Description: this is the main driver interrupt service routine.
2451  *  It can call:
2452  *  o DMA service routine (to manage incoming frame reception and transmission
2453  *    status)
2454  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2455  *    interrupts.
2456  */
2457 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2458 {
2459         struct net_device *dev = (struct net_device *)dev_id;
2460         struct stmmac_priv *priv = netdev_priv(dev);
2461
2462         if (priv->irq_wake)
2463                 pm_wakeup_event(priv->device, 0);
2464
2465         if (unlikely(!dev)) {
2466                 pr_err("%s: invalid dev pointer\n", __func__);
2467                 return IRQ_NONE;
2468         }
2469
2470         /* To handle GMAC own interrupts */
2471         if (priv->plat->has_gmac) {
2472                 int status = priv->hw->mac->host_irq_status(priv->hw,
2473                                                             &priv->xstats);
2474                 if (unlikely(status)) {
2475                         /* For LPI we need to save the tx status */
2476                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2477                                 priv->tx_path_in_lpi_mode = true;
2478                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2479                                 priv->tx_path_in_lpi_mode = false;
2480                 }
2481         }
2482
2483         /* To handle DMA interrupts */
2484         stmmac_dma_interrupt(priv);
2485
2486         return IRQ_HANDLED;
2487 }
2488
2489 #ifdef CONFIG_NET_POLL_CONTROLLER
2490 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2491  * to allow network I/O with interrupts disabled.
2492  */
2493 static void stmmac_poll_controller(struct net_device *dev)
2494 {
2495         disable_irq(dev->irq);
2496         stmmac_interrupt(dev->irq, dev);
2497         enable_irq(dev->irq);
2498 }
2499 #endif
2500
2501 /**
2502  *  stmmac_ioctl - Entry point for the Ioctl
2503  *  @dev: Device pointer.
2504  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2505  *  a proprietary structure used to pass information to the driver.
2506  *  @cmd: IOCTL command
2507  *  Description:
2508  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2509  */
2510 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2511 {
2512         struct stmmac_priv *priv = netdev_priv(dev);
2513         int ret = -EOPNOTSUPP;
2514
2515         if (!netif_running(dev))
2516                 return -EINVAL;
2517
2518         switch (cmd) {
2519         case SIOCGMIIPHY:
2520         case SIOCGMIIREG:
2521         case SIOCSMIIREG:
2522                 if (!priv->phydev)
2523                         return -EINVAL;
2524                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2525                 break;
2526         case SIOCSHWTSTAMP:
2527                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2528                 break;
2529         default:
2530                 break;
2531         }
2532
2533         return ret;
2534 }
2535
2536 #ifdef CONFIG_DEBUG_FS
2537 static struct dentry *stmmac_fs_dir;
2538
2539 static void sysfs_display_ring(void *head, int size, int extend_desc,
2540                                struct seq_file *seq)
2541 {
2542         int i;
2543         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2544         struct dma_desc *p = (struct dma_desc *)head;
2545
2546         for (i = 0; i < size; i++) {
2547                 u64 x;
2548                 if (extend_desc) {
2549                         x = *(u64 *) ep;
2550                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2551                                    i, (unsigned int)virt_to_phys(ep),
2552                                    (unsigned int)x, (unsigned int)(x >> 32),
2553                                    ep->basic.des2, ep->basic.des3);
2554                         ep++;
2555                 } else {
2556                         x = *(u64 *) p;
2557                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2558                                    i, (unsigned int)virt_to_phys(ep),
2559                                    (unsigned int)x, (unsigned int)(x >> 32),
2560                                    p->des2, p->des3);
2561                         p++;
2562                 }
2563                 seq_printf(seq, "\n");
2564         }
2565 }
2566
2567 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2568 {
2569         struct net_device *dev = seq->private;
2570         struct stmmac_priv *priv = netdev_priv(dev);
2571
2572         if (priv->extend_desc) {
2573                 seq_printf(seq, "Extended RX descriptor ring:\n");
2574                 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2575                 seq_printf(seq, "Extended TX descriptor ring:\n");
2576                 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2577         } else {
2578                 seq_printf(seq, "RX descriptor ring:\n");
2579                 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2580                 seq_printf(seq, "TX descriptor ring:\n");
2581                 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2582         }
2583
2584         return 0;
2585 }
2586
2587 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2588 {
2589         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2590 }
2591
2592 static const struct file_operations stmmac_rings_status_fops = {
2593         .owner = THIS_MODULE,
2594         .open = stmmac_sysfs_ring_open,
2595         .read = seq_read,
2596         .llseek = seq_lseek,
2597         .release = single_release,
2598 };
2599
2600 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2601 {
2602         struct net_device *dev = seq->private;
2603         struct stmmac_priv *priv = netdev_priv(dev);
2604
2605         if (!priv->hw_cap_support) {
2606                 seq_printf(seq, "DMA HW features not supported\n");
2607                 return 0;
2608         }
2609
2610         seq_printf(seq, "==============================\n");
2611         seq_printf(seq, "\tDMA HW features\n");
2612         seq_printf(seq, "==============================\n");
2613
2614         seq_printf(seq, "\t10/100 Mbps %s\n",
2615                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2616         seq_printf(seq, "\t1000 Mbps %s\n",
2617                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2618         seq_printf(seq, "\tHalf duple %s\n",
2619                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2620         seq_printf(seq, "\tHash Filter: %s\n",
2621                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2622         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2623                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2624         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2625                    (priv->dma_cap.pcs) ? "Y" : "N");
2626         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2627                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2628         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2629                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2630         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2631                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2632         seq_printf(seq, "\tRMON module: %s\n",
2633                    (priv->dma_cap.rmon) ? "Y" : "N");
2634         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2635                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2636         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2637                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2638         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2639                    (priv->dma_cap.eee) ? "Y" : "N");
2640         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2641         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2642                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2643         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2644                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2645         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2646                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2647         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2648                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2649         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2650                    priv->dma_cap.number_rx_channel);
2651         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2652                    priv->dma_cap.number_tx_channel);
2653         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2654                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2655
2656         return 0;
2657 }
2658
2659 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2660 {
2661         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2662 }
2663
2664 static const struct file_operations stmmac_dma_cap_fops = {
2665         .owner = THIS_MODULE,
2666         .open = stmmac_sysfs_dma_cap_open,
2667         .read = seq_read,
2668         .llseek = seq_lseek,
2669         .release = single_release,
2670 };
2671
2672 static int stmmac_init_fs(struct net_device *dev)
2673 {
2674         struct stmmac_priv *priv = netdev_priv(dev);
2675
2676         /* Create per netdev entries */
2677         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
2678
2679         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
2680                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2681                        STMMAC_RESOURCE_NAME, dev->name);
2682
2683                 return -ENOMEM;
2684         }
2685
2686         /* Entry to report DMA RX/TX rings */
2687         priv->dbgfs_rings_status =
2688                 debugfs_create_file("descriptors_status", S_IRUGO,
2689                                     priv->dbgfs_dir, dev,
2690                                     &stmmac_rings_status_fops);
2691
2692         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
2693                 pr_info("ERROR creating stmmac ring debugfs file\n");
2694                 debugfs_remove_recursive(priv->dbgfs_dir);
2695
2696                 return -ENOMEM;
2697         }
2698
2699         /* Entry to report the DMA HW features */
2700         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
2701                                             priv->dbgfs_dir,
2702                                             dev, &stmmac_dma_cap_fops);
2703
2704         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
2705                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2706                 debugfs_remove_recursive(priv->dbgfs_dir);
2707
2708                 return -ENOMEM;
2709         }
2710
2711         return 0;
2712 }
2713
2714 static void stmmac_exit_fs(struct net_device *dev)
2715 {
2716         struct stmmac_priv *priv = netdev_priv(dev);
2717
2718         debugfs_remove_recursive(priv->dbgfs_dir);
2719 }
2720 #endif /* CONFIG_DEBUG_FS */
2721
2722 static const struct net_device_ops stmmac_netdev_ops = {
2723         .ndo_open = stmmac_open,
2724         .ndo_start_xmit = stmmac_xmit,
2725         .ndo_stop = stmmac_release,
2726         .ndo_change_mtu = stmmac_change_mtu,
2727         .ndo_fix_features = stmmac_fix_features,
2728         .ndo_set_features = stmmac_set_features,
2729         .ndo_set_rx_mode = stmmac_set_rx_mode,
2730         .ndo_tx_timeout = stmmac_tx_timeout,
2731         .ndo_do_ioctl = stmmac_ioctl,
2732 #ifdef CONFIG_NET_POLL_CONTROLLER
2733         .ndo_poll_controller = stmmac_poll_controller,
2734 #endif
2735         .ndo_set_mac_address = eth_mac_addr,
2736 };
2737
2738 /**
2739  *  stmmac_hw_init - Init the MAC device
2740  *  @priv: driver private structure
2741  *  Description: this function is to configure the MAC device according to
2742  *  some platform parameters or the HW capability register. It prepares the
2743  *  driver to use either ring or chain modes and to setup either enhanced or
2744  *  normal descriptors.
2745  */
2746 static int stmmac_hw_init(struct stmmac_priv *priv)
2747 {
2748         struct mac_device_info *mac;
2749
2750         /* Identify the MAC HW device */
2751         if (priv->plat->has_gmac) {
2752                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2753                 mac = dwmac1000_setup(priv->ioaddr,
2754                                       priv->plat->multicast_filter_bins,
2755                                       priv->plat->unicast_filter_entries);
2756         } else {
2757                 mac = dwmac100_setup(priv->ioaddr);
2758         }
2759         if (!mac)
2760                 return -ENOMEM;
2761
2762         priv->hw = mac;
2763
2764         /* Get and dump the chip ID */
2765         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2766
2767         /* To use the chained or ring mode */
2768         if (chain_mode) {
2769                 priv->hw->mode = &chain_mode_ops;
2770                 pr_info(" Chain mode enabled\n");
2771                 priv->mode = STMMAC_CHAIN_MODE;
2772         } else {
2773                 priv->hw->mode = &ring_mode_ops;
2774                 pr_info(" Ring mode enabled\n");
2775                 priv->mode = STMMAC_RING_MODE;
2776         }
2777
2778         /* Get the HW capability (new GMAC newer than 3.50a) */
2779         priv->hw_cap_support = stmmac_get_hw_features(priv);
2780         if (priv->hw_cap_support) {
2781                 pr_info(" DMA HW capability register supported");
2782
2783                 /* We can override some gmac/dma configuration fields: e.g.
2784                  * enh_desc, tx_coe (e.g. that are passed through the
2785                  * platform) with the values from the HW capability
2786                  * register (if supported).
2787                  */
2788                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2789                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2790
2791                 /* TXCOE doesn't work in thresh DMA mode */
2792                 if (priv->plat->force_thresh_dma_mode)
2793                         priv->plat->tx_coe = 0;
2794                 else
2795                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
2796
2797                 if (priv->dma_cap.rx_coe_type2)
2798                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2799                 else if (priv->dma_cap.rx_coe_type1)
2800                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2801
2802         } else
2803                 pr_info(" No HW DMA feature register supported");
2804
2805         /* To use alternate (extended) or normal descriptor structures */
2806         stmmac_selec_desc_mode(priv);
2807
2808         if (priv->plat->rx_coe) {
2809                 priv->hw->rx_csum = priv->plat->rx_coe;
2810                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2811                         priv->plat->rx_coe);
2812         }
2813         if (priv->plat->tx_coe)
2814                 pr_info(" TX Checksum insertion supported\n");
2815
2816         if (priv->plat->pmt) {
2817                 pr_info(" Wake-Up On Lan supported\n");
2818                 device_set_wakeup_capable(priv->device, 1);
2819         }
2820
2821         return 0;
2822 }
2823
2824 /**
2825  * stmmac_dvr_probe
2826  * @device: device pointer
2827  * @plat_dat: platform data pointer
2828  * @res: stmmac resource pointer
2829  * Description: this is the main probe function used to
2830  * call the alloc_etherdev, allocate the priv structure.
2831  * Return:
2832  * returns 0 on success, otherwise errno.
2833  */
2834 int stmmac_dvr_probe(struct device *device,
2835                      struct plat_stmmacenet_data *plat_dat,
2836                      struct stmmac_resources *res)
2837 {
2838         int ret = 0;
2839         struct net_device *ndev = NULL;
2840         struct stmmac_priv *priv;
2841
2842         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2843         if (!ndev)
2844                 return -ENOMEM;
2845
2846         SET_NETDEV_DEV(ndev, device);
2847
2848         priv = netdev_priv(ndev);
2849         priv->device = device;
2850         priv->dev = ndev;
2851
2852         stmmac_set_ethtool_ops(ndev);
2853         priv->pause = pause;
2854         priv->plat = plat_dat;
2855         priv->ioaddr = res->addr;
2856         priv->dev->base_addr = (unsigned long)res->addr;
2857
2858         priv->dev->irq = res->irq;
2859         priv->wol_irq = res->wol_irq;
2860         priv->lpi_irq = res->lpi_irq;
2861
2862         if (res->mac)
2863                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2864
2865         dev_set_drvdata(device, priv->dev);
2866
2867         /* Verify driver arguments */
2868         stmmac_verify_args();
2869
2870         /* Override with kernel parameters if supplied XXX CRS XXX
2871          * this needs to have multiple instances
2872          */
2873         if ((phyaddr >= 0) && (phyaddr <= 31))
2874                 priv->plat->phy_addr = phyaddr;
2875
2876         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2877         if (IS_ERR(priv->stmmac_clk)) {
2878                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2879                          __func__);
2880                 /* If failed to obtain stmmac_clk and specific clk_csr value
2881                  * is NOT passed from the platform, probe fail.
2882                  */
2883                 if (!priv->plat->clk_csr) {
2884                         ret = PTR_ERR(priv->stmmac_clk);
2885                         goto error_clk_get;
2886                 } else {
2887                         priv->stmmac_clk = NULL;
2888                 }
2889         }
2890         clk_prepare_enable(priv->stmmac_clk);
2891
2892         priv->pclk = devm_clk_get(priv->device, "pclk");
2893         if (IS_ERR(priv->pclk)) {
2894                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2895                         ret = -EPROBE_DEFER;
2896                         goto error_pclk_get;
2897                 }
2898                 priv->pclk = NULL;
2899         }
2900         clk_prepare_enable(priv->pclk);
2901
2902         priv->stmmac_rst = devm_reset_control_get(priv->device,
2903                                                   STMMAC_RESOURCE_NAME);
2904         if (IS_ERR(priv->stmmac_rst)) {
2905                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2906                         ret = -EPROBE_DEFER;
2907                         goto error_hw_init;
2908                 }
2909                 dev_info(priv->device, "no reset control found\n");
2910                 priv->stmmac_rst = NULL;
2911         }
2912         if (priv->stmmac_rst)
2913                 reset_control_deassert(priv->stmmac_rst);
2914
2915         /* Init MAC and get the capabilities */
2916         ret = stmmac_hw_init(priv);
2917         if (ret)
2918                 goto error_hw_init;
2919
2920         ndev->netdev_ops = &stmmac_netdev_ops;
2921
2922         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2923                             NETIF_F_RXCSUM;
2924         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2925         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2926 #ifdef STMMAC_VLAN_TAG_USED
2927         /* Both mac100 and gmac support receive VLAN tag detection */
2928         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2929 #endif
2930         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2931
2932         if (flow_ctrl)
2933                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2934
2935         /* Rx Watchdog is available in the COREs newer than the 3.40.
2936          * In some case, for example on bugged HW this feature
2937          * has to be disable and this can be done by passing the
2938          * riwt_off field from the platform.
2939          */
2940         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2941                 priv->use_riwt = 1;
2942                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2943         }
2944
2945         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2946
2947         spin_lock_init(&priv->lock);
2948         spin_lock_init(&priv->tx_lock);
2949
2950         ret = register_netdev(ndev);
2951         if (ret) {
2952                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2953                 goto error_netdev_register;
2954         }
2955
2956         /* If a specific clk_csr value is passed from the platform
2957          * this means that the CSR Clock Range selection cannot be
2958          * changed at run-time and it is fixed. Viceversa the driver'll try to
2959          * set the MDC clock dynamically according to the csr actual
2960          * clock input.
2961          */
2962         if (!priv->plat->clk_csr)
2963                 stmmac_clk_csr_set(priv);
2964         else
2965                 priv->clk_csr = priv->plat->clk_csr;
2966
2967         stmmac_check_pcs_mode(priv);
2968
2969         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2970             priv->pcs != STMMAC_PCS_RTBI) {
2971                 /* MDIO bus Registration */
2972                 ret = stmmac_mdio_register(ndev);
2973                 if (ret < 0) {
2974                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2975                                  __func__, priv->plat->bus_id);
2976                         goto error_mdio_register;
2977                 }
2978         }
2979
2980         return 0;
2981
2982 error_mdio_register:
2983         unregister_netdev(ndev);
2984 error_netdev_register:
2985         netif_napi_del(&priv->napi);
2986 error_hw_init:
2987         clk_disable_unprepare(priv->pclk);
2988 error_pclk_get:
2989         clk_disable_unprepare(priv->stmmac_clk);
2990 error_clk_get:
2991         free_netdev(ndev);
2992
2993         return ret;
2994 }
2995 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2996
2997 /**
2998  * stmmac_dvr_remove
2999  * @ndev: net device pointer
3000  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3001  * changes the link status, releases the DMA descriptor rings.
3002  */
3003 int stmmac_dvr_remove(struct net_device *ndev)
3004 {
3005         struct stmmac_priv *priv = netdev_priv(ndev);
3006
3007         pr_info("%s:\n\tremoving driver", __func__);
3008
3009         priv->hw->dma->stop_rx(priv->ioaddr);
3010         priv->hw->dma->stop_tx(priv->ioaddr);
3011
3012         stmmac_set_mac(priv->ioaddr, false);
3013         netif_carrier_off(ndev);
3014         unregister_netdev(ndev);
3015         if (priv->stmmac_rst)
3016                 reset_control_assert(priv->stmmac_rst);
3017         clk_disable_unprepare(priv->pclk);
3018         clk_disable_unprepare(priv->stmmac_clk);
3019         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
3020             priv->pcs != STMMAC_PCS_RTBI)
3021                 stmmac_mdio_unregister(ndev);
3022         free_netdev(ndev);
3023
3024         return 0;
3025 }
3026 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3027
3028 /**
3029  * stmmac_suspend - suspend callback
3030  * @ndev: net device pointer
3031  * Description: this is the function to suspend the device and it is called
3032  * by the platform driver to stop the network queue, release the resources,
3033  * program the PMT register (for WoL), clean and release driver resources.
3034  */
3035 int stmmac_suspend(struct net_device *ndev)
3036 {
3037         struct stmmac_priv *priv = netdev_priv(ndev);
3038         unsigned long flags;
3039
3040         if (!ndev || !netif_running(ndev))
3041                 return 0;
3042
3043         if (priv->phydev)
3044                 phy_stop(priv->phydev);
3045
3046         spin_lock_irqsave(&priv->lock, flags);
3047
3048         netif_device_detach(ndev);
3049         netif_stop_queue(ndev);
3050
3051         napi_disable(&priv->napi);
3052
3053         /* Stop TX/RX DMA */
3054         priv->hw->dma->stop_tx(priv->ioaddr);
3055         priv->hw->dma->stop_rx(priv->ioaddr);
3056
3057         /* Enable Power down mode by programming the PMT regs */
3058         if (device_may_wakeup(priv->device)) {
3059                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3060                 priv->irq_wake = 1;
3061         } else {
3062                 stmmac_set_mac(priv->ioaddr, false);
3063                 pinctrl_pm_select_sleep_state(priv->device);
3064                 /* Disable clock in case of PWM is off */
3065                 clk_disable(priv->pclk);
3066                 clk_disable(priv->stmmac_clk);
3067         }
3068         spin_unlock_irqrestore(&priv->lock, flags);
3069
3070         priv->oldlink = 0;
3071         priv->speed = 0;
3072         priv->oldduplex = -1;
3073         return 0;
3074 }
3075 EXPORT_SYMBOL_GPL(stmmac_suspend);
3076
3077 /**
3078  * stmmac_resume - resume callback
3079  * @ndev: net device pointer
3080  * Description: when resume this function is invoked to setup the DMA and CORE
3081  * in a usable state.
3082  */
3083 int stmmac_resume(struct net_device *ndev)
3084 {
3085         struct stmmac_priv *priv = netdev_priv(ndev);
3086         unsigned long flags;
3087
3088         if (!netif_running(ndev))
3089                 return 0;
3090
3091         spin_lock_irqsave(&priv->lock, flags);
3092
3093         /* Power Down bit, into the PM register, is cleared
3094          * automatically as soon as a magic packet or a Wake-up frame
3095          * is received. Anyway, it's better to manually clear
3096          * this bit because it can generate problems while resuming
3097          * from another devices (e.g. serial console).
3098          */
3099         if (device_may_wakeup(priv->device)) {
3100                 priv->hw->mac->pmt(priv->hw, 0);
3101                 priv->irq_wake = 0;
3102         } else {
3103                 pinctrl_pm_select_default_state(priv->device);
3104                 /* enable the clk prevously disabled */
3105                 clk_enable(priv->stmmac_clk);
3106                 clk_enable(priv->pclk);
3107                 /* reset the phy so that it's ready */
3108                 if (priv->mii)
3109                         stmmac_mdio_reset(priv->mii);
3110         }
3111
3112         netif_device_attach(ndev);
3113
3114         priv->cur_rx = 0;
3115         priv->dirty_rx = 0;
3116         priv->dirty_tx = 0;
3117         priv->cur_tx = 0;
3118         stmmac_clear_descriptors(priv);
3119
3120         stmmac_hw_setup(ndev, false);
3121         stmmac_init_tx_coalesce(priv);
3122         stmmac_set_rx_mode(ndev);
3123
3124         napi_enable(&priv->napi);
3125
3126         netif_start_queue(ndev);
3127
3128         spin_unlock_irqrestore(&priv->lock, flags);
3129
3130         if (priv->phydev)
3131                 phy_start(priv->phydev);
3132
3133         return 0;
3134 }
3135 EXPORT_SYMBOL_GPL(stmmac_resume);
3136
3137 #ifndef MODULE
3138 static int __init stmmac_cmdline_opt(char *str)
3139 {
3140         char *opt;
3141
3142         if (!str || !*str)
3143                 return -EINVAL;
3144         while ((opt = strsep(&str, ",")) != NULL) {
3145                 if (!strncmp(opt, "debug:", 6)) {
3146                         if (kstrtoint(opt + 6, 0, &debug))
3147                                 goto err;
3148                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3149                         if (kstrtoint(opt + 8, 0, &phyaddr))
3150                                 goto err;
3151                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3152                         if (kstrtoint(opt + 7, 0, &buf_sz))
3153                                 goto err;
3154                 } else if (!strncmp(opt, "tc:", 3)) {
3155                         if (kstrtoint(opt + 3, 0, &tc))
3156                                 goto err;
3157                 } else if (!strncmp(opt, "watchdog:", 9)) {
3158                         if (kstrtoint(opt + 9, 0, &watchdog))
3159                                 goto err;
3160                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3161                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3162                                 goto err;
3163                 } else if (!strncmp(opt, "pause:", 6)) {
3164                         if (kstrtoint(opt + 6, 0, &pause))
3165                                 goto err;
3166                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3167                         if (kstrtoint(opt + 10, 0, &eee_timer))
3168                                 goto err;
3169                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3170                         if (kstrtoint(opt + 11, 0, &chain_mode))
3171                                 goto err;
3172                 }
3173         }
3174         return 0;
3175
3176 err:
3177         pr_err("%s: ERROR broken module parameter conversion", __func__);
3178         return -EINVAL;
3179 }
3180
3181 __setup("stmmaceth=", stmmac_cmdline_opt);
3182 #endif /* MODULE */
3183
3184 static int __init stmmac_init(void)
3185 {
3186 #ifdef CONFIG_DEBUG_FS
3187         /* Create debugfs main directory if it doesn't exist yet */
3188         if (!stmmac_fs_dir) {
3189                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3190
3191                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3192                         pr_err("ERROR %s, debugfs create directory failed\n",
3193                                STMMAC_RESOURCE_NAME);
3194
3195                         return -ENOMEM;
3196                 }
3197         }
3198 #endif
3199
3200         return 0;
3201 }
3202
3203 static void __exit stmmac_exit(void)
3204 {
3205 #ifdef CONFIG_DEBUG_FS
3206         debugfs_remove_recursive(stmmac_fs_dir);
3207 #endif
3208 }
3209
3210 module_init(stmmac_init)
3211 module_exit(stmmac_exit)
3212
3213 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3214 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3215 MODULE_LICENSE("GPL");