drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_STMMAC_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_STMMAC_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55
  56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  57
  58 /* Module parameters */
  59 #define TX_TIMEO        5000
  60 static int watchdog = TX_TIMEO;
  61 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  63
  64 static int debug = -1;
  65 module_param(debug, int, S_IRUGO | S_IWUSR);
  66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  67
  68 static int phyaddr = -1;
  69 module_param(phyaddr, int, S_IRUGO);
  70 MODULE_PARM_DESC(phyaddr, "Physical device address");
  71
  72 #define DMA_TX_SIZE 256
  73 static int dma_txsize = DMA_TX_SIZE;
  74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  76
  77 #define DMA_RX_SIZE 256
  78 static int dma_rxsize = DMA_RX_SIZE;
  79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
  80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
  81
  82 static int flow_ctrl = FLOW_OFF;
  83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  85
  86 static int pause = PAUSE_TIME;
  87 module_param(pause, int, S_IRUGO | S_IWUSR);
  88 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  89
  90 #define TC_DEFAULT 64
  91 static int tc = TC_DEFAULT;
  92 module_param(tc, int, S_IRUGO | S_IWUSR);
  93 MODULE_PARM_DESC(tc, "DMA threshold control value");
  94
  95 #define DEFAULT_BUFSIZE 1536
  96 static int buf_sz = DEFAULT_BUFSIZE;
  97 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  99
 100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 101                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 102                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 103
 104 #define STMMAC_DEFAULT_LPI_TIMER        1000
 105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 106 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 109
 110 /* By default the driver will use the ring mode to manage tx and rx descriptors
 111  * but passing this value so user can force to use the chain instead of the ring
 112  */
 113 static unsigned int chain_mode;
 114 module_param(chain_mode, int, S_IRUGO);
 115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 116
 117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 118
 119 #ifdef CONFIG_STMMAC_DEBUG_FS
 120 static int stmmac_init_fs(struct net_device *dev);
 121 static void stmmac_exit_fs(void);
 122 #endif
 123
 124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 125
 126 /**
 127  * stmmac_verify_args - verify the driver parameters.
 128  * Description: it verifies if some wrong parameter is passed to the driver.
 129  * Note that wrong parameters are replaced with the default values.
 130  */
 131 static void stmmac_verify_args(void)
 132 {
 133         if (unlikely(watchdog < 0))
 134                 watchdog = TX_TIMEO;
 135         if (unlikely(dma_rxsize < 0))
 136                 dma_rxsize = DMA_RX_SIZE;
 137         if (unlikely(dma_txsize < 0))
 138                 dma_txsize = DMA_TX_SIZE;
 139         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 140                 buf_sz = DEFAULT_BUFSIZE;
 141         if (unlikely(flow_ctrl > 1))
 142                 flow_ctrl = FLOW_AUTO;
 143         else if (likely(flow_ctrl < 0))
 144                 flow_ctrl = FLOW_OFF;
 145         if (unlikely((pause < 0) || (pause > 0xffff)))
 146                 pause = PAUSE_TIME;
 147         if (eee_timer < 0)
 148                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 149 }
 150
 151 /**
 152  * stmmac_clk_csr_set - dynamically set the MDC clock
 153  * @priv: driver private structure
 154  * Description: this is to dynamically set the MDC clock according to the csr
 155  * clock input.
 156  * Note:
 157  *      If a specific clk_csr value is passed from the platform
 158  *      this means that the CSR Clock Range selection cannot be
 159  *      changed at run-time and it is fixed (as reported in the driver
 160  *      documentation). Viceversa the driver will try to set the MDC
 161  *      clock dynamically according to the actual clock input.
 162  */
 163 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 164 {
 165         u32 clk_rate;
 166
 167         clk_rate = clk_get_rate(priv->stmmac_clk);
 168
 169         /* Platform provided default clk_csr would be assumed valid
 170          * for all other cases except for the below mentioned ones.
 171          * For values higher than the IEEE 802.3 specified frequency
 172          * we can not estimate the proper divider as it is not known
 173          * the frequency of clk_csr_i. So we do not change the default
 174          * divider.
 175          */
 176         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 177                 if (clk_rate < CSR_F_35M)
 178                         priv->clk_csr = STMMAC_CSR_20_35M;
 179                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 180                         priv->clk_csr = STMMAC_CSR_35_60M;
 181                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 182                         priv->clk_csr = STMMAC_CSR_60_100M;
 183                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 184                         priv->clk_csr = STMMAC_CSR_100_150M;
 185                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 186                         priv->clk_csr = STMMAC_CSR_150_250M;
 187                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 188                         priv->clk_csr = STMMAC_CSR_250_300M;
 189         }
 190 }
 191
 192 static void print_pkt(unsigned char *buf, int len)
 193 {
 194         int j;
 195         pr_debug("len = %d byte, buf addr: 0x%p", len, buf);
 196         for (j = 0; j < len; j++) {
 197                 if ((j % 16) == 0)
 198                         pr_debug("\n %03x:", j);
 199                 pr_debug(" %02x", buf[j]);
 200         }
 201         pr_debug("\n");
 202 }
 203
 204 /* minimum number of free TX descriptors required to wake up TX process */
 205 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 206
 207 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 208 {
 209         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 210 }
 211
 212 /**
 213  * stmmac_hw_fix_mac_speed: callback for speed selection
 214  * @priv: driver private structure
 215  * Description: on some platforms (e.g. ST), some HW system configuraton
 216  * registers have to be set according to the link speed negotiated.
 217  */
 218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 219 {
 220         struct phy_device *phydev = priv->phydev;
 221
 222         if (likely(priv->plat->fix_mac_speed))
 223                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 224 }
 225
 226 /**
 227  * stmmac_enable_eee_mode: Check and enter in LPI mode
 228  * @priv: driver private structure
 229  * Description: this function is to verify and enter in LPI mode for EEE.
 230  */
 231 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 232 {
 233         /* Check and enter in LPI mode */
 234         if ((priv->dirty_tx == priv->cur_tx) &&
 235             (priv->tx_path_in_lpi_mode == false))
 236                 priv->hw->mac->set_eee_mode(priv->hw);
 237 }
 238
 239 /**
 240  * stmmac_disable_eee_mode: disable/exit from EEE
 241  * @priv: driver private structure
 242  * Description: this function is to exit and disable EEE in case of
 243  * LPI state is true. This is called by the xmit.
 244  */
 245 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 246 {
 247         priv->hw->mac->reset_eee_mode(priv->hw);
 248         del_timer_sync(&priv->eee_ctrl_timer);
 249         priv->tx_path_in_lpi_mode = false;
 250 }
 251
 252 /**
 253  * stmmac_eee_ctrl_timer: EEE TX SW timer.
 254  * @arg : data hook
 255  * Description:
 256  *  if there is no data transfer and if we are not in LPI state,
 257  *  then MAC Transmitter can be moved to LPI state.
 258  */
 259 static void stmmac_eee_ctrl_timer(unsigned long arg)
 260 {
 261         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 262
 263         stmmac_enable_eee_mode(priv);
 264         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 265 }
 266
 267 /**
 268  * stmmac_eee_init: init EEE
 269  * @priv: driver private structure
 270  * Description:
 271  *  If the EEE support has been enabled while configuring the driver,
 272  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 273  *  phy can also manage EEE, so enable the LPI state and start the timer
 274  *  to verify if the tx path can enter in LPI state.
 275  */
 276 bool stmmac_eee_init(struct stmmac_priv *priv)
 277 {
 278         bool ret = false;
 279
 280         /* Using PCS we cannot dial with the phy registers at this stage
 281          * so we do not support extra feature like EEE.
 282          */
 283         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 284             (priv->pcs == STMMAC_PCS_RTBI))
 285                 goto out;
 286
 287         /* MAC core supports the EEE feature. */
 288         if (priv->dma_cap.eee) {
 289                 int tx_lpi_timer = priv->tx_lpi_timer;
 290
 291                 /* Check if the PHY supports EEE */
 292                 if (phy_init_eee(priv->phydev, 1)) {
 293                         /* To manage at run-time if the EEE cannot be supported
 294                          * anymore (for example because the lp caps have been
 295                          * changed).
 296                          * In that case the driver disable own timers.
 297                          */
 298                         if (priv->eee_active) {
 299                                 pr_debug("stmmac: disable EEE\n");
 300                                 del_timer_sync(&priv->eee_ctrl_timer);
 301                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 302                                                              tx_lpi_timer);
 303                         }
 304                         priv->eee_active = 0;
 305                         goto out;
 306                 }
 307                 /* Activate the EEE and start timers */
 308                 if (!priv->eee_active) {
 309                         priv->eee_active = 1;
 310                         init_timer(&priv->eee_ctrl_timer);
 311                         priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 312                         priv->eee_ctrl_timer.data = (unsigned long)priv;
 313                         priv->eee_ctrl_timer.expires = STMMAC_LPI_T(eee_timer);
 314                         add_timer(&priv->eee_ctrl_timer);
 315
 316                         priv->hw->mac->set_eee_timer(priv->hw,
 317                                                      STMMAC_DEFAULT_LIT_LS,
 318                                                      tx_lpi_timer);
 319                 } else
 320                         /* Set HW EEE according to the speed */
 321                         priv->hw->mac->set_eee_pls(priv->hw,
 322                                                    priv->phydev->link);
 323
 324                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 325
 326                 ret = true;
 327         }
 328 out:
 329         return ret;
 330 }
 331
 332 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
 333  * @priv: driver private structure
 334  * @entry : descriptor index to be used.
 335  * @skb : the socket buffer
 336  * Description :
 337  * This function will read timestamp from the descriptor & pass it to stack.
 338  * and also perform some sanity checks.
 339  */
 340 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 341                                    unsigned int entry, struct sk_buff *skb)
 342 {
 343         struct skb_shared_hwtstamps shhwtstamp;
 344         u64 ns;
 345         void *desc = NULL;
 346
 347         if (!priv->hwts_tx_en)
 348                 return;
 349
 350         /* exit if skb doesn't support hw tstamp */
 351         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 352                 return;
 353
 354         if (priv->adv_ts)
 355                 desc = (priv->dma_etx + entry);
 356         else
 357                 desc = (priv->dma_tx + entry);
 358
 359         /* check tx tstamp status */
 360         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 361                 return;
 362
 363         /* get the valid tstamp */
 364         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 365
 366         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 367         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 368         /* pass tstamp to stack */
 369         skb_tstamp_tx(skb, &shhwtstamp);
 370
 371         return;
 372 }
 373
 374 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
 375  * @priv: driver private structure
 376  * @entry : descriptor index to be used.
 377  * @skb : the socket buffer
 378  * Description :
 379  * This function will read received packet's timestamp from the descriptor
 380  * and pass it to stack. It also perform some sanity checks.
 381  */
 382 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 383                                    unsigned int entry, struct sk_buff *skb)
 384 {
 385         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 386         u64 ns;
 387         void *desc = NULL;
 388
 389         if (!priv->hwts_rx_en)
 390                 return;
 391
 392         if (priv->adv_ts)
 393                 desc = (priv->dma_erx + entry);
 394         else
 395                 desc = (priv->dma_rx + entry);
 396
 397         /* exit if rx tstamp is not valid */
 398         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 399                 return;
 400
 401         /* get valid tstamp */
 402         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 403         shhwtstamp = skb_hwtstamps(skb);
 404         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 405         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 406 }
 407
 408 /**
 409  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 410  *  @dev: device pointer.
 411  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 412  *  a proprietary structure used to pass information to the driver.
 413  *  Description:
 414  *  This function configures the MAC to enable/disable both outgoing(TX)
 415  *  and incoming(RX) packets time stamping based on user input.
 416  *  Return Value:
 417  *  0 on success and an appropriate -ve integer on failure.
 418  */
 419 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 420 {
 421         struct stmmac_priv *priv = netdev_priv(dev);
 422         struct hwtstamp_config config;
 423         struct timespec now;
 424         u64 temp = 0;
 425         u32 ptp_v2 = 0;
 426         u32 tstamp_all = 0;
 427         u32 ptp_over_ipv4_udp = 0;
 428         u32 ptp_over_ipv6_udp = 0;
 429         u32 ptp_over_ethernet = 0;
 430         u32 snap_type_sel = 0;
 431         u32 ts_master_en = 0;
 432         u32 ts_event_en = 0;
 433         u32 value = 0;
 434
 435         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 436                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 437                 priv->hwts_tx_en = 0;
 438                 priv->hwts_rx_en = 0;
 439
 440                 return -EOPNOTSUPP;
 441         }
 442
 443         if (copy_from_user(&config, ifr->ifr_data,
 444                            sizeof(struct hwtstamp_config)))
 445                 return -EFAULT;
 446
 447         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 448                  __func__, config.flags, config.tx_type, config.rx_filter);
 449
 450         /* reserved for future extensions */
 451         if (config.flags)
 452                 return -EINVAL;
 453
 454         if (config.tx_type != HWTSTAMP_TX_OFF &&
 455             config.tx_type != HWTSTAMP_TX_ON)
 456                 return -ERANGE;
 457
 458         if (priv->adv_ts) {
 459                 switch (config.rx_filter) {
 460                 case HWTSTAMP_FILTER_NONE:
 461                         /* time stamp no incoming packet at all */
 462                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 463                         break;
 464
 465                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 466                         /* PTP v1, UDP, any kind of event packet */
 467                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 468                         /* take time stamp for all event messages */
 469                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 470
 471                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 472                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 473                         break;
 474
 475                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 476                         /* PTP v1, UDP, Sync packet */
 477                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 478                         /* take time stamp for SYNC messages only */
 479                         ts_event_en = PTP_TCR_TSEVNTENA;
 480
 481                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 482                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 483                         break;
 484
 485                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 486                         /* PTP v1, UDP, Delay_req packet */
 487                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 488                         /* take time stamp for Delay_Req messages only */
 489                         ts_master_en = PTP_TCR_TSMSTRENA;
 490                         ts_event_en = PTP_TCR_TSEVNTENA;
 491
 492                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 493                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 494                         break;
 495
 496                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 497                         /* PTP v2, UDP, any kind of event packet */
 498                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 499                         ptp_v2 = PTP_TCR_TSVER2ENA;
 500                         /* take time stamp for all event messages */
 501                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 502
 503                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 504                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 505                         break;
 506
 507                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 508                         /* PTP v2, UDP, Sync packet */
 509                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 510                         ptp_v2 = PTP_TCR_TSVER2ENA;
 511                         /* take time stamp for SYNC messages only */
 512                         ts_event_en = PTP_TCR_TSEVNTENA;
 513
 514                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 515                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 516                         break;
 517
 518                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 519                         /* PTP v2, UDP, Delay_req packet */
 520                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 521                         ptp_v2 = PTP_TCR_TSVER2ENA;
 522                         /* take time stamp for Delay_Req messages only */
 523                         ts_master_en = PTP_TCR_TSMSTRENA;
 524                         ts_event_en = PTP_TCR_TSEVNTENA;
 525
 526                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 527                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 528                         break;
 529
 530                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 531                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 532                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 533                         ptp_v2 = PTP_TCR_TSVER2ENA;
 534                         /* take time stamp for all event messages */
 535                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 536
 537                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 538                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 539                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 540                         break;
 541
 542                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 543                         /* PTP v2/802.AS1, any layer, Sync packet */
 544                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 545                         ptp_v2 = PTP_TCR_TSVER2ENA;
 546                         /* take time stamp for SYNC messages only */
 547                         ts_event_en = PTP_TCR_TSEVNTENA;
 548
 549                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 550                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 551                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 552                         break;
 553
 554                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 555                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 556                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 557                         ptp_v2 = PTP_TCR_TSVER2ENA;
 558                         /* take time stamp for Delay_Req messages only */
 559                         ts_master_en = PTP_TCR_TSMSTRENA;
 560                         ts_event_en = PTP_TCR_TSEVNTENA;
 561
 562                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 563                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 564                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 565                         break;
 566
 567                 case HWTSTAMP_FILTER_ALL:
 568                         /* time stamp any incoming packet */
 569                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 570                         tstamp_all = PTP_TCR_TSENALL;
 571                         break;
 572
 573                 default:
 574                         return -ERANGE;
 575                 }
 576         } else {
 577                 switch (config.rx_filter) {
 578                 case HWTSTAMP_FILTER_NONE:
 579                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 580                         break;
 581                 default:
 582                         /* PTP v1, UDP, any kind of event packet */
 583                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 584                         break;
 585                 }
 586         }
 587         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 588         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 589
 590         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 591                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 592         else {
 593                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 594                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 595                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 596                          ts_master_en | snap_type_sel);
 597
 598                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 599
 600                 /* program Sub Second Increment reg */
 601                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 602
 603                 /* calculate default added value:
 604                  * formula is :
 605                  * addend = (2^32)/freq_div_ratio;
 606                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
 607                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
 608                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
 609                  *       achive 20ns accuracy.
 610                  *
 611                  * 2^x * y == (y << x), hence
 612                  * 2^32 * 50000000 ==> (50000000 << 32)
 613                  */
 614                 temp = (u64) (50000000ULL << 32);
 615                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 616                 priv->hw->ptp->config_addend(priv->ioaddr,
 617                                              priv->default_addend);
 618
 619                 /* initialize system time */
 620                 getnstimeofday(&now);
 621                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 622                                             now.tv_nsec);
 623         }
 624
 625         return copy_to_user(ifr->ifr_data, &config,
 626                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 627 }
 628
 629 /**
 630  * stmmac_init_ptp: init PTP
 631  * @priv: driver private structure
 632  * Description: this is to verify if the HW supports the PTPv1 or v2.
 633  * This is done by looking at the HW cap. register.
 634  * Also it registers the ptp driver.
 635  */
 636 static int stmmac_init_ptp(struct stmmac_priv *priv)
 637 {
 638         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 639                 return -EOPNOTSUPP;
 640
 641         /* Fall-back to main clock in case of no PTP ref is passed */
 642         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 643         if (IS_ERR(priv->clk_ptp_ref)) {
 644                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 645                 priv->clk_ptp_ref = NULL;
 646         } else {
 647                 clk_prepare_enable(priv->clk_ptp_ref);
 648                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 649         }
 650
 651         priv->adv_ts = 0;
 652         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 653                 priv->adv_ts = 1;
 654
 655         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 656                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 657
 658         if (netif_msg_hw(priv) && priv->adv_ts)
 659                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 660
 661         priv->hw->ptp = &stmmac_ptp;
 662         priv->hwts_tx_en = 0;
 663         priv->hwts_rx_en = 0;
 664
 665         return stmmac_ptp_register(priv);
 666 }
 667
 668 static void stmmac_release_ptp(struct stmmac_priv *priv)
 669 {
 670         if (priv->clk_ptp_ref)
 671                 clk_disable_unprepare(priv->clk_ptp_ref);
 672         stmmac_ptp_unregister(priv);
 673 }
 674
 675 /**
 676  * stmmac_adjust_link
 677  * @dev: net device structure
 678  * Description: it adjusts the link parameters.
 679  */
 680 static void stmmac_adjust_link(struct net_device *dev)
 681 {
 682         struct stmmac_priv *priv = netdev_priv(dev);
 683         struct phy_device *phydev = priv->phydev;
 684         unsigned long flags;
 685         int new_state = 0;
 686         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 687
 688         if (phydev == NULL)
 689                 return;
 690
 691         spin_lock_irqsave(&priv->lock, flags);
 692
 693         if (phydev->link) {
 694                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 695
 696                 /* Now we make sure that we can be in full duplex mode.
 697                  * If not, we operate in half-duplex mode. */
 698                 if (phydev->duplex != priv->oldduplex) {
 699                         new_state = 1;
 700                         if (!(phydev->duplex))
 701                                 ctrl &= ~priv->hw->link.duplex;
 702                         else
 703                                 ctrl |= priv->hw->link.duplex;
 704                         priv->oldduplex = phydev->duplex;
 705                 }
 706                 /* Flow Control operation */
 707                 if (phydev->pause)
 708                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 709                                                  fc, pause_time);
 710
 711                 if (phydev->speed != priv->speed) {
 712                         new_state = 1;
 713                         switch (phydev->speed) {
 714                         case 1000:
 715                                 if (likely(priv->plat->has_gmac))
 716                                         ctrl &= ~priv->hw->link.port;
 717                                 stmmac_hw_fix_mac_speed(priv);
 718                                 break;
 719                         case 100:
 720                         case 10:
 721                                 if (priv->plat->has_gmac) {
 722                                         ctrl |= priv->hw->link.port;
 723                                         if (phydev->speed == SPEED_100) {
 724                                                 ctrl |= priv->hw->link.speed;
 725                                         } else {
 726                                                 ctrl &= ~(priv->hw->link.speed);
 727                                         }
 728                                 } else {
 729                                         ctrl &= ~priv->hw->link.port;
 730                                 }
 731                                 stmmac_hw_fix_mac_speed(priv);
 732                                 break;
 733                         default:
 734                                 if (netif_msg_link(priv))
 735                                         pr_warn("%s: Speed (%d) not 10/100\n",
 736                                                 dev->name, phydev->speed);
 737                                 break;
 738                         }
 739
 740                         priv->speed = phydev->speed;
 741                 }
 742
 743                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 744
 745                 if (!priv->oldlink) {
 746                         new_state = 1;
 747                         priv->oldlink = 1;
 748                 }
 749         } else if (priv->oldlink) {
 750                 new_state = 1;
 751                 priv->oldlink = 0;
 752                 priv->speed = 0;
 753                 priv->oldduplex = -1;
 754         }
 755
 756         if (new_state && netif_msg_link(priv))
 757                 phy_print_status(phydev);
 758
 759         /* At this stage, it could be needed to setup the EEE or adjust some
 760          * MAC related HW registers.
 761          */
 762         priv->eee_enabled = stmmac_eee_init(priv);
 763
 764         spin_unlock_irqrestore(&priv->lock, flags);
 765 }
 766
 767 /**
 768  * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
 769  * @priv: driver private structure
 770  * Description: this is to verify if the HW supports the PCS.
 771  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 772  * configured for the TBI, RTBI, or SGMII PHY interface.
 773  */
 774 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 775 {
 776         int interface = priv->plat->interface;
 777
 778         if (priv->dma_cap.pcs) {
 779                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 780                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 781                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 782                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 783                         pr_debug("STMMAC: PCS RGMII support enable\n");
 784                         priv->pcs = STMMAC_PCS_RGMII;
 785                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 786                         pr_debug("STMMAC: PCS SGMII support enable\n");
 787                         priv->pcs = STMMAC_PCS_SGMII;
 788                 }
 789         }
 790 }
 791
 792 /**
 793  * stmmac_init_phy - PHY initialization
 794  * @dev: net device structure
 795  * Description: it initializes the driver's PHY state, and attaches the PHY
 796  * to the mac driver.
 797  *  Return value:
 798  *  0 on success
 799  */
 800 static int stmmac_init_phy(struct net_device *dev)
 801 {
 802         struct stmmac_priv *priv = netdev_priv(dev);
 803         struct phy_device *phydev;
 804         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 805         char bus_id[MII_BUS_ID_SIZE];
 806         int interface = priv->plat->interface;
 807         int max_speed = priv->plat->max_speed;
 808         priv->oldlink = 0;
 809         priv->speed = 0;
 810         priv->oldduplex = -1;
 811
 812         if (priv->plat->phy_bus_name)
 813                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 814                          priv->plat->phy_bus_name, priv->plat->bus_id);
 815         else
 816                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 817                          priv->plat->bus_id);
 818
 819         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 820                  priv->plat->phy_addr);
 821         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 822
 823         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 824
 825         if (IS_ERR(phydev)) {
 826                 pr_err("%s: Could not attach to PHY\n", dev->name);
 827                 return PTR_ERR(phydev);
 828         }
 829
 830         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 831         if ((interface == PHY_INTERFACE_MODE_MII) ||
 832             (interface == PHY_INTERFACE_MODE_RMII) ||
 833                 (max_speed < 1000 &&  max_speed > 0))
 834                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 835                                          SUPPORTED_1000baseT_Full);
 836
 837         /*
 838          * Broken HW is sometimes missing the pull-up resistor on the
 839          * MDIO line, which results in reads to non-existent devices returning
 840          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 841          * device as well.
 842          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 843          */
 844         if (phydev->phy_id == 0) {
 845                 phy_disconnect(phydev);
 846                 return -ENODEV;
 847         }
 848         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 849                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 850
 851         priv->phydev = phydev;
 852
 853         return 0;
 854 }
 855
 856 /**
 857  * stmmac_display_ring: display ring
 858  * @head: pointer to the head of the ring passed.
 859  * @size: size of the ring.
 860  * @extend_desc: to verify if extended descriptors are used.
 861  * Description: display the control/status and buffer descriptors.
 862  */
 863 static void stmmac_display_ring(void *head, int size, int extend_desc)
 864 {
 865         int i;
 866         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 867         struct dma_desc *p = (struct dma_desc *)head;
 868
 869         for (i = 0; i < size; i++) {
 870                 u64 x;
 871                 if (extend_desc) {
 872                         x = *(u64 *) ep;
 873                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 874                                 i, (unsigned int)virt_to_phys(ep),
 875                                 (unsigned int)x, (unsigned int)(x >> 32),
 876                                 ep->basic.des2, ep->basic.des3);
 877                         ep++;
 878                 } else {
 879                         x = *(u64 *) p;
 880                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 881                                 i, (unsigned int)virt_to_phys(p),
 882                                 (unsigned int)x, (unsigned int)(x >> 32),
 883                                 p->des2, p->des3);
 884                         p++;
 885                 }
 886                 pr_info("\n");
 887         }
 888 }
 889
 890 static void stmmac_display_rings(struct stmmac_priv *priv)
 891 {
 892         unsigned int txsize = priv->dma_tx_size;
 893         unsigned int rxsize = priv->dma_rx_size;
 894
 895         if (priv->extend_desc) {
 896                 pr_info("Extended RX descriptor ring:\n");
 897                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 898                 pr_info("Extended TX descriptor ring:\n");
 899                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 900         } else {
 901                 pr_info("RX descriptor ring:\n");
 902                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 903                 pr_info("TX descriptor ring:\n");
 904                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 905         }
 906 }
 907
 908 static int stmmac_set_bfsize(int mtu, int bufsize)
 909 {
 910         int ret = bufsize;
 911
 912         if (mtu >= BUF_SIZE_4KiB)
 913                 ret = BUF_SIZE_8KiB;
 914         else if (mtu >= BUF_SIZE_2KiB)
 915                 ret = BUF_SIZE_4KiB;
 916         else if (mtu > DEFAULT_BUFSIZE)
 917                 ret = BUF_SIZE_2KiB;
 918         else
 919                 ret = DEFAULT_BUFSIZE;
 920
 921         return ret;
 922 }
 923
 924 /**
 925  * stmmac_clear_descriptors: clear descriptors
 926  * @priv: driver private structure
 927  * Description: this function is called to clear the tx and rx descriptors
 928  * in case of both basic and extended descriptors are used.
 929  */
 930 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 931 {
 932         int i;
 933         unsigned int txsize = priv->dma_tx_size;
 934         unsigned int rxsize = priv->dma_rx_size;
 935
 936         /* Clear the Rx/Tx descriptors */
 937         for (i = 0; i < rxsize; i++)
 938                 if (priv->extend_desc)
 939                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 940                                                      priv->use_riwt, priv->mode,
 941                                                      (i == rxsize - 1));
 942                 else
 943                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 944                                                      priv->use_riwt, priv->mode,
 945                                                      (i == rxsize - 1));
 946         for (i = 0; i < txsize; i++)
 947                 if (priv->extend_desc)
 948                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 949                                                      priv->mode,
 950                                                      (i == txsize - 1));
 951                 else
 952                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 953                                                      priv->mode,
 954                                                      (i == txsize - 1));
 955 }
 956
 957 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 958                                   int i)
 959 {
 960         struct sk_buff *skb;
 961
 962         skb = __netdev_alloc_skb(priv->dev, priv->dma_buf_sz + NET_IP_ALIGN,
 963                                  GFP_KERNEL);
 964         if (!skb) {
 965                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 966                 return -ENOMEM;
 967         }
 968         skb_reserve(skb, NET_IP_ALIGN);
 969         priv->rx_skbuff[i] = skb;
 970         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 971                                                 priv->dma_buf_sz,
 972                                                 DMA_FROM_DEVICE);
 973         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 974                 pr_err("%s: DMA mapping error\n", __func__);
 975                 dev_kfree_skb_any(skb);
 976                 return -EINVAL;
 977         }
 978
 979         p->des2 = priv->rx_skbuff_dma[i];
 980
 981         if ((priv->hw->mode->init_desc3) &&
 982             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 983                 priv->hw->mode->init_desc3(p);
 984
 985         return 0;
 986 }
 987
 988 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
 989 {
 990         if (priv->rx_skbuff[i]) {
 991                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 992                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
 993                 dev_kfree_skb_any(priv->rx_skbuff[i]);
 994         }
 995         priv->rx_skbuff[i] = NULL;
 996 }
 997
 998 /**
 999  * init_dma_desc_rings - init the RX/TX descriptor rings
1000  * @dev: net device structure
1001  * Description:  this function initializes the DMA RX/TX descriptors
1002  * and allocates the socket buffers. It suppors the chained and ring
1003  * modes.
1004  */
1005 static int init_dma_desc_rings(struct net_device *dev)
1006 {
1007         int i;
1008         struct stmmac_priv *priv = netdev_priv(dev);
1009         unsigned int txsize = priv->dma_tx_size;
1010         unsigned int rxsize = priv->dma_rx_size;
1011         unsigned int bfsize = 0;
1012         int ret = -ENOMEM;
1013
1014         if (priv->hw->mode->set_16kib_bfsize)
1015                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1016
1017         if (bfsize < BUF_SIZE_16KiB)
1018                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1019
1020         priv->dma_buf_sz = bfsize;
1021
1022         if (netif_msg_probe(priv))
1023                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1024                          txsize, rxsize, bfsize);
1025
1026         if (netif_msg_probe(priv)) {
1027                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1028                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1029
1030                 /* RX INITIALIZATION */
1031                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1032         }
1033         for (i = 0; i < rxsize; i++) {
1034                 struct dma_desc *p;
1035                 if (priv->extend_desc)
1036                         p = &((priv->dma_erx + i)->basic);
1037                 else
1038                         p = priv->dma_rx + i;
1039
1040                 ret = stmmac_init_rx_buffers(priv, p, i);
1041                 if (ret)
1042                         goto err_init_rx_buffers;
1043
1044                 if (netif_msg_probe(priv))
1045                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1046                                  priv->rx_skbuff[i]->data,
1047                                  (unsigned int)priv->rx_skbuff_dma[i]);
1048         }
1049         priv->cur_rx = 0;
1050         priv->dirty_rx = (unsigned int)(i - rxsize);
1051         buf_sz = bfsize;
1052
1053         /* Setup the chained descriptor addresses */
1054         if (priv->mode == STMMAC_CHAIN_MODE) {
1055                 if (priv->extend_desc) {
1056                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1057                                              rxsize, 1);
1058                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1059                                              txsize, 1);
1060                 } else {
1061                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1062                                              rxsize, 0);
1063                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1064                                              txsize, 0);
1065                 }
1066         }
1067
1068         /* TX INITIALIZATION */
1069         for (i = 0; i < txsize; i++) {
1070                 struct dma_desc *p;
1071                 if (priv->extend_desc)
1072                         p = &((priv->dma_etx + i)->basic);
1073                 else
1074                         p = priv->dma_tx + i;
1075                 p->des2 = 0;
1076                 priv->tx_skbuff_dma[i].buf = 0;
1077                 priv->tx_skbuff_dma[i].map_as_page = false;
1078                 priv->tx_skbuff[i] = NULL;
1079         }
1080
1081         priv->dirty_tx = 0;
1082         priv->cur_tx = 0;
1083
1084         stmmac_clear_descriptors(priv);
1085
1086         if (netif_msg_hw(priv))
1087                 stmmac_display_rings(priv);
1088
1089         return 0;
1090 err_init_rx_buffers:
1091         while (--i >= 0)
1092                 stmmac_free_rx_buffers(priv, i);
1093         return ret;
1094 }
1095
1096 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1097 {
1098         int i;
1099
1100         for (i = 0; i < priv->dma_rx_size; i++)
1101                 stmmac_free_rx_buffers(priv, i);
1102 }
1103
1104 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1105 {
1106         int i;
1107
1108         for (i = 0; i < priv->dma_tx_size; i++) {
1109                 struct dma_desc *p;
1110
1111                 if (priv->extend_desc)
1112                         p = &((priv->dma_etx + i)->basic);
1113                 else
1114                         p = priv->dma_tx + i;
1115
1116                 if (priv->tx_skbuff_dma[i].buf) {
1117                         if (priv->tx_skbuff_dma[i].map_as_page)
1118                                 dma_unmap_page(priv->device,
1119                                                priv->tx_skbuff_dma[i].buf,
1120                                                priv->hw->desc->get_tx_len(p),
1121                                                DMA_TO_DEVICE);
1122                         else
1123                                 dma_unmap_single(priv->device,
1124                                                  priv->tx_skbuff_dma[i].buf,
1125                                                  priv->hw->desc->get_tx_len(p),
1126                                                  DMA_TO_DEVICE);
1127                 }
1128
1129                 if (priv->tx_skbuff[i] != NULL) {
1130                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1131                         priv->tx_skbuff[i] = NULL;
1132                         priv->tx_skbuff_dma[i].buf = 0;
1133                         priv->tx_skbuff_dma[i].map_as_page = false;
1134                 }
1135         }
1136 }
1137
1138 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1139 {
1140         unsigned int txsize = priv->dma_tx_size;
1141         unsigned int rxsize = priv->dma_rx_size;
1142         int ret = -ENOMEM;
1143
1144         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1145                                             GFP_KERNEL);
1146         if (!priv->rx_skbuff_dma)
1147                 return -ENOMEM;
1148
1149         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1150                                         GFP_KERNEL);
1151         if (!priv->rx_skbuff)
1152                 goto err_rx_skbuff;
1153
1154         priv->tx_skbuff_dma = kmalloc_array(txsize,
1155                                             sizeof(*priv->tx_skbuff_dma),
1156                                             GFP_KERNEL);
1157         if (!priv->tx_skbuff_dma)
1158                 goto err_tx_skbuff_dma;
1159
1160         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1161                                         GFP_KERNEL);
1162         if (!priv->tx_skbuff)
1163                 goto err_tx_skbuff;
1164
1165         if (priv->extend_desc) {
1166                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1167                                                    sizeof(struct
1168                                                           dma_extended_desc),
1169                                                    &priv->dma_rx_phy,
1170                                                    GFP_KERNEL);
1171                 if (!priv->dma_erx)
1172                         goto err_dma;
1173
1174                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1175                                                    sizeof(struct
1176                                                           dma_extended_desc),
1177                                                    &priv->dma_tx_phy,
1178                                                    GFP_KERNEL);
1179                 if (!priv->dma_etx) {
1180                         dma_free_coherent(priv->device, priv->dma_rx_size *
1181                                         sizeof(struct dma_extended_desc),
1182                                         priv->dma_erx, priv->dma_rx_phy);
1183                         goto err_dma;
1184                 }
1185         } else {
1186                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1187                                                   sizeof(struct dma_desc),
1188                                                   &priv->dma_rx_phy,
1189                                                   GFP_KERNEL);
1190                 if (!priv->dma_rx)
1191                         goto err_dma;
1192
1193                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1194                                                   sizeof(struct dma_desc),
1195                                                   &priv->dma_tx_phy,
1196                                                   GFP_KERNEL);
1197                 if (!priv->dma_tx) {
1198                         dma_free_coherent(priv->device, priv->dma_rx_size *
1199                                         sizeof(struct dma_desc),
1200                                         priv->dma_rx, priv->dma_rx_phy);
1201                         goto err_dma;
1202                 }
1203         }
1204
1205         return 0;
1206
1207 err_dma:
1208         kfree(priv->tx_skbuff);
1209 err_tx_skbuff:
1210         kfree(priv->tx_skbuff_dma);
1211 err_tx_skbuff_dma:
1212         kfree(priv->rx_skbuff);
1213 err_rx_skbuff:
1214         kfree(priv->rx_skbuff_dma);
1215         return ret;
1216 }
1217
1218 static void free_dma_desc_resources(struct stmmac_priv *priv)
1219 {
1220         /* Release the DMA TX/RX socket buffers */
1221         dma_free_rx_skbufs(priv);
1222         dma_free_tx_skbufs(priv);
1223
1224         /* Free DMA regions of consistent memory previously allocated */
1225         if (!priv->extend_desc) {
1226                 dma_free_coherent(priv->device,
1227                                   priv->dma_tx_size * sizeof(struct dma_desc),
1228                                   priv->dma_tx, priv->dma_tx_phy);
1229                 dma_free_coherent(priv->device,
1230                                   priv->dma_rx_size * sizeof(struct dma_desc),
1231                                   priv->dma_rx, priv->dma_rx_phy);
1232         } else {
1233                 dma_free_coherent(priv->device, priv->dma_tx_size *
1234                                   sizeof(struct dma_extended_desc),
1235                                   priv->dma_etx, priv->dma_tx_phy);
1236                 dma_free_coherent(priv->device, priv->dma_rx_size *
1237                                   sizeof(struct dma_extended_desc),
1238                                   priv->dma_erx, priv->dma_rx_phy);
1239         }
1240         kfree(priv->rx_skbuff_dma);
1241         kfree(priv->rx_skbuff);
1242         kfree(priv->tx_skbuff_dma);
1243         kfree(priv->tx_skbuff);
1244 }
1245
1246 /**
1247  *  stmmac_dma_operation_mode - HW DMA operation mode
1248  *  @priv: driver private structure
1249  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
1250  *  or Store-And-Forward capability.
1251  */
1252 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1253 {
1254         if (priv->plat->force_thresh_dma_mode)
1255                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc);
1256         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1257                 /*
1258                  * In case of GMAC, SF mode can be enabled
1259                  * to perform the TX COE in HW. This depends on:
1260                  * 1) TX COE if actually supported
1261                  * 2) There is no bugged Jumbo frame support
1262                  *    that needs to not insert csum in the TDES.
1263                  */
1264                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE);
1265                 tc = SF_DMA_MODE;
1266         } else
1267                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1268 }
1269
1270 /**
1271  * stmmac_tx_clean:
1272  * @priv: driver private structure
1273  * Description: it reclaims resources after transmission completes.
1274  */
1275 static void stmmac_tx_clean(struct stmmac_priv *priv)
1276 {
1277         unsigned int txsize = priv->dma_tx_size;
1278
1279         spin_lock(&priv->tx_lock);
1280
1281         priv->xstats.tx_clean++;
1282
1283         while (priv->dirty_tx != priv->cur_tx) {
1284                 int last;
1285                 unsigned int entry = priv->dirty_tx % txsize;
1286                 struct sk_buff *skb = priv->tx_skbuff[entry];
1287                 struct dma_desc *p;
1288
1289                 if (priv->extend_desc)
1290                         p = (struct dma_desc *)(priv->dma_etx + entry);
1291                 else
1292                         p = priv->dma_tx + entry;
1293
1294                 /* Check if the descriptor is owned by the DMA. */
1295                 if (priv->hw->desc->get_tx_owner(p))
1296                         break;
1297
1298                 /* Verify tx error by looking at the last segment. */
1299                 last = priv->hw->desc->get_tx_ls(p);
1300                 if (likely(last)) {
1301                         int tx_error =
1302                             priv->hw->desc->tx_status(&priv->dev->stats,
1303                                                       &priv->xstats, p,
1304                                                       priv->ioaddr);
1305                         if (likely(tx_error == 0)) {
1306                                 priv->dev->stats.tx_packets++;
1307                                 priv->xstats.tx_pkt_n++;
1308                         } else
1309                                 priv->dev->stats.tx_errors++;
1310
1311                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1312                 }
1313                 if (netif_msg_tx_done(priv))
1314                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1315                                  priv->cur_tx, priv->dirty_tx);
1316
1317                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1318                         if (priv->tx_skbuff_dma[entry].map_as_page)
1319                                 dma_unmap_page(priv->device,
1320                                                priv->tx_skbuff_dma[entry].buf,
1321                                                priv->hw->desc->get_tx_len(p),
1322                                                DMA_TO_DEVICE);
1323                         else
1324                                 dma_unmap_single(priv->device,
1325                                                  priv->tx_skbuff_dma[entry].buf,
1326                                                  priv->hw->desc->get_tx_len(p),
1327                                                  DMA_TO_DEVICE);
1328                         priv->tx_skbuff_dma[entry].buf = 0;
1329                         priv->tx_skbuff_dma[entry].map_as_page = false;
1330                 }
1331                 priv->hw->mode->clean_desc3(priv, p);
1332
1333                 if (likely(skb != NULL)) {
1334                         dev_consume_skb_any(skb);
1335                         priv->tx_skbuff[entry] = NULL;
1336                 }
1337
1338                 priv->hw->desc->release_tx_desc(p, priv->mode);
1339
1340                 priv->dirty_tx++;
1341         }
1342         if (unlikely(netif_queue_stopped(priv->dev) &&
1343                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1344                 netif_tx_lock(priv->dev);
1345                 if (netif_queue_stopped(priv->dev) &&
1346                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1347                         if (netif_msg_tx_done(priv))
1348                                 pr_debug("%s: restart transmit\n", __func__);
1349                         netif_wake_queue(priv->dev);
1350                 }
1351                 netif_tx_unlock(priv->dev);
1352         }
1353
1354         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1355                 stmmac_enable_eee_mode(priv);
1356                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1357         }
1358         spin_unlock(&priv->tx_lock);
1359 }
1360
1361 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1362 {
1363         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1364 }
1365
1366 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1367 {
1368         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1369 }
1370
1371 /**
1372  * stmmac_tx_err: irq tx error mng function
1373  * @priv: driver private structure
1374  * Description: it cleans the descriptors and restarts the transmission
1375  * in case of errors.
1376  */
1377 static void stmmac_tx_err(struct stmmac_priv *priv)
1378 {
1379         int i;
1380         int txsize = priv->dma_tx_size;
1381         netif_stop_queue(priv->dev);
1382
1383         priv->hw->dma->stop_tx(priv->ioaddr);
1384         dma_free_tx_skbufs(priv);
1385         for (i = 0; i < txsize; i++)
1386                 if (priv->extend_desc)
1387                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1388                                                      priv->mode,
1389                                                      (i == txsize - 1));
1390                 else
1391                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1392                                                      priv->mode,
1393                                                      (i == txsize - 1));
1394         priv->dirty_tx = 0;
1395         priv->cur_tx = 0;
1396         priv->hw->dma->start_tx(priv->ioaddr);
1397
1398         priv->dev->stats.tx_errors++;
1399         netif_wake_queue(priv->dev);
1400 }
1401
1402 /**
1403  * stmmac_dma_interrupt: DMA ISR
1404  * @priv: driver private structure
1405  * Description: this is the DMA ISR. It is called by the main ISR.
1406  * It calls the dwmac dma routine to understand which type of interrupt
1407  * happened. In case of there is a Normal interrupt and either TX or RX
1408  * interrupt happened so the NAPI is scheduled.
1409  */
1410 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1411 {
1412         int status;
1413
1414         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1415         if (likely((status & handle_rx)) || (status & handle_tx)) {
1416                 if (likely(napi_schedule_prep(&priv->napi))) {
1417                         stmmac_disable_dma_irq(priv);
1418                         __napi_schedule(&priv->napi);
1419                 }
1420         }
1421         if (unlikely(status & tx_hard_error_bump_tc)) {
1422                 /* Try to bump up the dma threshold on this failure */
1423                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
1424                         tc += 64;
1425                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
1426                         priv->xstats.threshold = tc;
1427                 }
1428         } else if (unlikely(status == tx_hard_error))
1429                 stmmac_tx_err(priv);
1430 }
1431
1432 /**
1433  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1434  * @priv: driver private structure
1435  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1436  */
1437 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1438 {
1439         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1440             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1441
1442         dwmac_mmc_intr_all_mask(priv->ioaddr);
1443
1444         if (priv->dma_cap.rmon) {
1445                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1446                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1447         } else
1448                 pr_info(" No MAC Management Counters available\n");
1449 }
1450
1451 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1452 {
1453         u32 hwid = priv->hw->synopsys_uid;
1454
1455         /* Check Synopsys Id (not available on old chips) */
1456         if (likely(hwid)) {
1457                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1458                 u32 synid = (hwid & 0x000000ff);
1459
1460                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1461                         uid, synid);
1462
1463                 return synid;
1464         }
1465         return 0;
1466 }
1467
1468 /**
1469  * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1470  * @priv: driver private structure
1471  * Description: select the Enhanced/Alternate or Normal descriptors.
1472  * In case of Enhanced/Alternate, it looks at the extended descriptors are
1473  * supported by the HW cap. register.
1474  */
1475 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1476 {
1477         if (priv->plat->enh_desc) {
1478                 pr_info(" Enhanced/Alternate descriptors\n");
1479
1480                 /* GMAC older than 3.50 has no extended descriptors */
1481                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1482                         pr_info("\tEnabled extended descriptors\n");
1483                         priv->extend_desc = 1;
1484                 } else
1485                         pr_warn("Extended descriptors not supported\n");
1486
1487                 priv->hw->desc = &enh_desc_ops;
1488         } else {
1489                 pr_info(" Normal descriptors\n");
1490                 priv->hw->desc = &ndesc_ops;
1491         }
1492 }
1493
1494 /**
1495  * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1496  * @priv: driver private structure
1497  * Description:
1498  *  new GMAC chip generations have a new register to indicate the
1499  *  presence of the optional feature/functions.
1500  *  This can be also used to override the value passed through the
1501  *  platform and necessary for old MAC10/100 and GMAC chips.
1502  */
1503 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1504 {
1505         u32 hw_cap = 0;
1506
1507         if (priv->hw->dma->get_hw_feature) {
1508                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1509
1510                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1511                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1512                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1513                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1514                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1515                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1516                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1517                 priv->dma_cap.pmt_remote_wake_up =
1518                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1519                 priv->dma_cap.pmt_magic_frame =
1520                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1521                 /* MMC */
1522                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1523                 /* IEEE 1588-2002 */
1524                 priv->dma_cap.time_stamp =
1525                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1526                 /* IEEE 1588-2008 */
1527                 priv->dma_cap.atime_stamp =
1528                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1529                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1530                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1531                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1532                 /* TX and RX csum */
1533                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1534                 priv->dma_cap.rx_coe_type1 =
1535                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1536                 priv->dma_cap.rx_coe_type2 =
1537                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1538                 priv->dma_cap.rxfifo_over_2048 =
1539                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1540                 /* TX and RX number of channels */
1541                 priv->dma_cap.number_rx_channel =
1542                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1543                 priv->dma_cap.number_tx_channel =
1544                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1545                 /* Alternate (enhanced) DESC mode */
1546                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1547         }
1548
1549         return hw_cap;
1550 }
1551
1552 /**
1553  * stmmac_check_ether_addr: check if the MAC addr is valid
1554  * @priv: driver private structure
1555  * Description:
1556  * it is to verify if the MAC address is valid, in case of failures it
1557  * generates a random MAC address
1558  */
1559 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1560 {
1561         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1562                 priv->hw->mac->get_umac_addr(priv->hw,
1563                                              priv->dev->dev_addr, 0);
1564                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1565                         eth_hw_addr_random(priv->dev);
1566                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1567                         priv->dev->dev_addr);
1568         }
1569 }
1570
1571 /**
1572  * stmmac_init_dma_engine: DMA init.
1573  * @priv: driver private structure
1574  * Description:
1575  * It inits the DMA invoking the specific MAC/GMAC callback.
1576  * Some DMA parameters can be passed from the platform;
1577  * in case of these are not passed a default is kept for the MAC or GMAC.
1578  */
1579 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1580 {
1581         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1582         int mixed_burst = 0;
1583         int atds = 0;
1584
1585         if (priv->plat->dma_cfg) {
1586                 pbl = priv->plat->dma_cfg->pbl;
1587                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1588                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1589                 burst_len = priv->plat->dma_cfg->burst_len;
1590         }
1591
1592         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1593                 atds = 1;
1594
1595         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1596                                    burst_len, priv->dma_tx_phy,
1597                                    priv->dma_rx_phy, atds);
1598 }
1599
1600 /**
1601  * stmmac_tx_timer: mitigation sw timer for tx.
1602  * @data: data pointer
1603  * Description:
1604  * This is the timer handler to directly invoke the stmmac_tx_clean.
1605  */
1606 static void stmmac_tx_timer(unsigned long data)
1607 {
1608         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1609
1610         stmmac_tx_clean(priv);
1611 }
1612
1613 /**
1614  * stmmac_init_tx_coalesce: init tx mitigation options.
1615  * @priv: driver private structure
1616  * Description:
1617  * This inits the transmit coalesce parameters: i.e. timer rate,
1618  * timer handler and default threshold used for enabling the
1619  * interrupt on completion bit.
1620  */
1621 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1622 {
1623         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1624         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1625         init_timer(&priv->txtimer);
1626         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1627         priv->txtimer.data = (unsigned long)priv;
1628         priv->txtimer.function = stmmac_tx_timer;
1629         add_timer(&priv->txtimer);
1630 }
1631
1632 /**
1633  * stmmac_hw_setup: setup mac in a usable state.
1634  *  @dev : pointer to the device structure.
1635  *  Description:
1636  *  This function sets up the ip in a usable state.
1637  *  Return value:
1638  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1639  *  file on failure.
1640  */
1641 static int stmmac_hw_setup(struct net_device *dev)
1642 {
1643         struct stmmac_priv *priv = netdev_priv(dev);
1644         int ret;
1645
1646         ret = init_dma_desc_rings(dev);
1647         if (ret < 0) {
1648                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1649                 return ret;
1650         }
1651         /* DMA initialization and SW reset */
1652         ret = stmmac_init_dma_engine(priv);
1653         if (ret < 0) {
1654                 pr_err("%s: DMA engine initialization failed\n", __func__);
1655                 return ret;
1656         }
1657
1658         /* Copy the MAC addr into the HW  */
1659         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1660
1661         /* If required, perform hw setup of the bus. */
1662         if (priv->plat->bus_setup)
1663                 priv->plat->bus_setup(priv->ioaddr);
1664
1665         /* Initialize the MAC Core */
1666         priv->hw->mac->core_init(priv->hw, dev->mtu);
1667
1668         ret = priv->hw->mac->rx_ipc(priv->hw);
1669         if (!ret) {
1670                 pr_warn(" RX IPC Checksum Offload disabled\n");
1671                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1672         }
1673
1674         /* Enable the MAC Rx/Tx */
1675         stmmac_set_mac(priv->ioaddr, true);
1676
1677         /* Set the HW DMA mode and the COE */
1678         stmmac_dma_operation_mode(priv);
1679
1680         stmmac_mmc_setup(priv);
1681
1682         ret = stmmac_init_ptp(priv);
1683         if (ret && ret != -EOPNOTSUPP)
1684                 pr_warn("%s: failed PTP initialisation\n", __func__);
1685
1686 #ifdef CONFIG_STMMAC_DEBUG_FS
1687         ret = stmmac_init_fs(dev);
1688         if (ret < 0)
1689                 pr_warn("%s: failed debugFS registration\n", __func__);
1690 #endif
1691         /* Start the ball rolling... */
1692         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1693         priv->hw->dma->start_tx(priv->ioaddr);
1694         priv->hw->dma->start_rx(priv->ioaddr);
1695
1696         /* Dump DMA/MAC registers */
1697         if (netif_msg_hw(priv)) {
1698                 priv->hw->mac->dump_regs(priv->hw);
1699                 priv->hw->dma->dump_regs(priv->ioaddr);
1700         }
1701         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1702
1703         priv->eee_enabled = stmmac_eee_init(priv);
1704
1705         stmmac_init_tx_coalesce(priv);
1706
1707         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1708                 priv->rx_riwt = MAX_DMA_RIWT;
1709                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1710         }
1711
1712         if (priv->pcs && priv->hw->mac->ctrl_ane)
1713                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1714
1715         return 0;
1716 }
1717
1718 /**
1719  *  stmmac_open - open entry point of the driver
1720  *  @dev : pointer to the device structure.
1721  *  Description:
1722  *  This function is the open entry point of the driver.
1723  *  Return value:
1724  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1725  *  file on failure.
1726  */
1727 static int stmmac_open(struct net_device *dev)
1728 {
1729         struct stmmac_priv *priv = netdev_priv(dev);
1730         int ret;
1731
1732         stmmac_check_ether_addr(priv);
1733
1734         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1735             priv->pcs != STMMAC_PCS_RTBI) {
1736                 ret = stmmac_init_phy(dev);
1737                 if (ret) {
1738                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1739                                __func__, ret);
1740                         return ret;
1741                 }
1742         }
1743
1744         /* Extra statistics */
1745         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1746         priv->xstats.threshold = tc;
1747
1748         /* Create and initialize the TX/RX descriptors chains. */
1749         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1750         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1751         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1752
1753         ret = alloc_dma_desc_resources(priv);
1754         if (ret < 0) {
1755                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1756                 goto dma_desc_error;
1757         }
1758
1759         ret = stmmac_hw_setup(dev);
1760         if (ret < 0) {
1761                 pr_err("%s: Hw setup failed\n", __func__);
1762                 goto init_error;
1763         }
1764
1765         if (priv->phydev)
1766                 phy_start(priv->phydev);
1767
1768         /* Request the IRQ lines */
1769         ret = request_irq(dev->irq, stmmac_interrupt,
1770                           IRQF_SHARED, dev->name, dev);
1771         if (unlikely(ret < 0)) {
1772                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1773                        __func__, dev->irq, ret);
1774                 goto init_error;
1775         }
1776
1777         /* Request the Wake IRQ in case of another line is used for WoL */
1778         if (priv->wol_irq != dev->irq) {
1779                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1780                                   IRQF_SHARED, dev->name, dev);
1781                 if (unlikely(ret < 0)) {
1782                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1783                                __func__, priv->wol_irq, ret);
1784                         goto wolirq_error;
1785                 }
1786         }
1787
1788         /* Request the IRQ lines */
1789         if (priv->lpi_irq > 0) {
1790                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1791                                   dev->name, dev);
1792                 if (unlikely(ret < 0)) {
1793                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1794                                __func__, priv->lpi_irq, ret);
1795                         goto lpiirq_error;
1796                 }
1797         }
1798
1799         napi_enable(&priv->napi);
1800         netif_start_queue(dev);
1801
1802         return 0;
1803
1804 lpiirq_error:
1805         if (priv->wol_irq != dev->irq)
1806                 free_irq(priv->wol_irq, dev);
1807 wolirq_error:
1808         free_irq(dev->irq, dev);
1809
1810 init_error:
1811         free_dma_desc_resources(priv);
1812 dma_desc_error:
1813         if (priv->phydev)
1814                 phy_disconnect(priv->phydev);
1815
1816         return ret;
1817 }
1818
1819 /**
1820  *  stmmac_release - close entry point of the driver
1821  *  @dev : device pointer.
1822  *  Description:
1823  *  This is the stop entry point of the driver.
1824  */
1825 static int stmmac_release(struct net_device *dev)
1826 {
1827         struct stmmac_priv *priv = netdev_priv(dev);
1828
1829         if (priv->eee_enabled)
1830                 del_timer_sync(&priv->eee_ctrl_timer);
1831
1832         /* Stop and disconnect the PHY */
1833         if (priv->phydev) {
1834                 phy_stop(priv->phydev);
1835                 phy_disconnect(priv->phydev);
1836                 priv->phydev = NULL;
1837         }
1838
1839         netif_stop_queue(dev);
1840
1841         napi_disable(&priv->napi);
1842
1843         del_timer_sync(&priv->txtimer);
1844
1845         /* Free the IRQ lines */
1846         free_irq(dev->irq, dev);
1847         if (priv->wol_irq != dev->irq)
1848                 free_irq(priv->wol_irq, dev);
1849         if (priv->lpi_irq > 0)
1850                 free_irq(priv->lpi_irq, dev);
1851
1852         /* Stop TX/RX DMA and clear the descriptors */
1853         priv->hw->dma->stop_tx(priv->ioaddr);
1854         priv->hw->dma->stop_rx(priv->ioaddr);
1855
1856         /* Release and free the Rx/Tx resources */
1857         free_dma_desc_resources(priv);
1858
1859         /* Disable the MAC Rx/Tx */
1860         stmmac_set_mac(priv->ioaddr, false);
1861
1862         netif_carrier_off(dev);
1863
1864 #ifdef CONFIG_STMMAC_DEBUG_FS
1865         stmmac_exit_fs();
1866 #endif
1867
1868         stmmac_release_ptp(priv);
1869
1870         return 0;
1871 }
1872
1873 /**
1874  *  stmmac_xmit: Tx entry point of the driver
1875  *  @skb : the socket buffer
1876  *  @dev : device pointer
1877  *  Description : this is the tx entry point of the driver.
1878  *  It programs the chain or the ring and supports oversized frames
1879  *  and SG feature.
1880  */
1881 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1882 {
1883         struct stmmac_priv *priv = netdev_priv(dev);
1884         unsigned int txsize = priv->dma_tx_size;
1885         unsigned int entry;
1886         int i, csum_insertion = 0, is_jumbo = 0;
1887         int nfrags = skb_shinfo(skb)->nr_frags;
1888         struct dma_desc *desc, *first;
1889         unsigned int nopaged_len = skb_headlen(skb);
1890         unsigned int enh_desc = priv->plat->enh_desc;
1891
1892         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1893                 if (!netif_queue_stopped(dev)) {
1894                         netif_stop_queue(dev);
1895                         /* This is a hard error, log it. */
1896                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1897                 }
1898                 return NETDEV_TX_BUSY;
1899         }
1900
1901         spin_lock(&priv->tx_lock);
1902
1903         if (priv->tx_path_in_lpi_mode)
1904                 stmmac_disable_eee_mode(priv);
1905
1906         entry = priv->cur_tx % txsize;
1907
1908         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1909
1910         if (priv->extend_desc)
1911                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1912         else
1913                 desc = priv->dma_tx + entry;
1914
1915         first = desc;
1916
1917         /* To program the descriptors according to the size of the frame */
1918         if (enh_desc)
1919                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1920
1921         if (likely(!is_jumbo)) {
1922                 desc->des2 = dma_map_single(priv->device, skb->data,
1923                                             nopaged_len, DMA_TO_DEVICE);
1924                 if (dma_mapping_error(priv->device, desc->des2))
1925                         goto dma_map_err;
1926                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1927                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1928                                                 csum_insertion, priv->mode);
1929         } else {
1930                 desc = first;
1931                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1932                 if (unlikely(entry < 0))
1933                         goto dma_map_err;
1934         }
1935
1936         for (i = 0; i < nfrags; i++) {
1937                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1938                 int len = skb_frag_size(frag);
1939
1940                 priv->tx_skbuff[entry] = NULL;
1941                 entry = (++priv->cur_tx) % txsize;
1942                 if (priv->extend_desc)
1943                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1944                 else
1945                         desc = priv->dma_tx + entry;
1946
1947                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1948                                               DMA_TO_DEVICE);
1949                 if (dma_mapping_error(priv->device, desc->des2))
1950                         goto dma_map_err; /* should reuse desc w/o issues */
1951
1952                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1953                 priv->tx_skbuff_dma[entry].map_as_page = true;
1954                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
1955                                                 priv->mode);
1956                 wmb();
1957                 priv->hw->desc->set_tx_owner(desc);
1958                 wmb();
1959         }
1960
1961         priv->tx_skbuff[entry] = skb;
1962
1963         /* Finalize the latest segment. */
1964         priv->hw->desc->close_tx_desc(desc);
1965
1966         wmb();
1967         /* According to the coalesce parameter the IC bit for the latest
1968          * segment could be reset and the timer re-started to invoke the
1969          * stmmac_tx function. This approach takes care about the fragments.
1970          */
1971         priv->tx_count_frames += nfrags + 1;
1972         if (priv->tx_coal_frames > priv->tx_count_frames) {
1973                 priv->hw->desc->clear_tx_ic(desc);
1974                 priv->xstats.tx_reset_ic_bit++;
1975                 mod_timer(&priv->txtimer,
1976                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1977         } else
1978                 priv->tx_count_frames = 0;
1979
1980         /* To avoid raise condition */
1981         priv->hw->desc->set_tx_owner(first);
1982         wmb();
1983
1984         priv->cur_tx++;
1985
1986         if (netif_msg_pktdata(priv)) {
1987                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1988                         __func__, (priv->cur_tx % txsize),
1989                         (priv->dirty_tx % txsize), entry, first, nfrags);
1990
1991                 if (priv->extend_desc)
1992                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
1993                 else
1994                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
1995
1996                 pr_debug(">>> frame to be transmitted: ");
1997                 print_pkt(skb->data, skb->len);
1998         }
1999         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2000                 if (netif_msg_hw(priv))
2001                         pr_debug("%s: stop transmitted packets\n", __func__);
2002                 netif_stop_queue(dev);
2003         }
2004
2005         dev->stats.tx_bytes += skb->len;
2006
2007         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2008                      priv->hwts_tx_en)) {
2009                 /* declare that device is doing timestamping */
2010                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2011                 priv->hw->desc->enable_tx_timestamp(first);
2012         }
2013
2014         if (!priv->hwts_tx_en)
2015                 skb_tx_timestamp(skb);
2016
2017         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2018
2019         spin_unlock(&priv->tx_lock);
2020         return NETDEV_TX_OK;
2021
2022 dma_map_err:
2023         dev_err(priv->device, "Tx dma map failed\n");
2024         dev_kfree_skb(skb);
2025         priv->dev->stats.tx_dropped++;
2026         return NETDEV_TX_OK;
2027 }
2028
2029 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2030 {
2031         struct ethhdr *ehdr;
2032         u16 vlanid;
2033
2034         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2035             NETIF_F_HW_VLAN_CTAG_RX &&
2036             !__vlan_get_tag(skb, &vlanid)) {
2037                 /* pop the vlan tag */
2038                 ehdr = (struct ethhdr *)skb->data;
2039                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2040                 skb_pull(skb, VLAN_HLEN);
2041                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2042         }
2043 }
2044
2045
2046 /**
2047  * stmmac_rx_refill: refill used skb preallocated buffers
2048  * @priv: driver private structure
2049  * Description : this is to reallocate the skb for the reception process
2050  * that is based on zero-copy.
2051  */
2052 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2053 {
2054         unsigned int rxsize = priv->dma_rx_size;
2055         int bfsize = priv->dma_buf_sz;
2056
2057         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2058                 unsigned int entry = priv->dirty_rx % rxsize;
2059                 struct dma_desc *p;
2060
2061                 if (priv->extend_desc)
2062                         p = (struct dma_desc *)(priv->dma_erx + entry);
2063                 else
2064                         p = priv->dma_rx + entry;
2065
2066                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2067                         struct sk_buff *skb;
2068
2069                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2070
2071                         if (unlikely(skb == NULL))
2072                                 break;
2073
2074                         priv->rx_skbuff[entry] = skb;
2075                         priv->rx_skbuff_dma[entry] =
2076                             dma_map_single(priv->device, skb->data, bfsize,
2077                                            DMA_FROM_DEVICE);
2078                         if (dma_mapping_error(priv->device,
2079                                               priv->rx_skbuff_dma[entry])) {
2080                                 dev_err(priv->device, "Rx dma map failed\n");
2081                                 dev_kfree_skb(skb);
2082                                 break;
2083                         }
2084                         p->des2 = priv->rx_skbuff_dma[entry];
2085
2086                         priv->hw->mode->refill_desc3(priv, p);
2087
2088                         if (netif_msg_rx_status(priv))
2089                                 pr_debug("\trefill entry #%d\n", entry);
2090                 }
2091                 wmb();
2092                 priv->hw->desc->set_rx_owner(p);
2093                 wmb();
2094         }
2095 }
2096
2097 /**
2098  * stmmac_rx_refill: refill used skb preallocated buffers
2099  * @priv: driver private structure
2100  * @limit: napi bugget.
2101  * Description :  this the function called by the napi poll method.
2102  * It gets all the frames inside the ring.
2103  */
2104 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2105 {
2106         unsigned int rxsize = priv->dma_rx_size;
2107         unsigned int entry = priv->cur_rx % rxsize;
2108         unsigned int next_entry;
2109         unsigned int count = 0;
2110         int coe = priv->plat->rx_coe;
2111
2112         if (netif_msg_rx_status(priv)) {
2113                 pr_debug("%s: descriptor ring:\n", __func__);
2114                 if (priv->extend_desc)
2115                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2116                 else
2117                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2118         }
2119         while (count < limit) {
2120                 int status;
2121                 struct dma_desc *p;
2122
2123                 if (priv->extend_desc)
2124                         p = (struct dma_desc *)(priv->dma_erx + entry);
2125                 else
2126                         p = priv->dma_rx + entry;
2127
2128                 if (priv->hw->desc->get_rx_owner(p))
2129                         break;
2130
2131                 count++;
2132
2133                 next_entry = (++priv->cur_rx) % rxsize;
2134                 if (priv->extend_desc)
2135                         prefetch(priv->dma_erx + next_entry);
2136                 else
2137                         prefetch(priv->dma_rx + next_entry);
2138
2139                 /* read the status of the incoming frame */
2140                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2141                                                    &priv->xstats, p);
2142                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2143                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2144                                                            &priv->xstats,
2145                                                            priv->dma_erx +
2146                                                            entry);
2147                 if (unlikely(status == discard_frame)) {
2148                         priv->dev->stats.rx_errors++;
2149                         if (priv->hwts_rx_en && !priv->extend_desc) {
2150                                 /* DESC2 & DESC3 will be overwitten by device
2151                                  * with timestamp value, hence reinitialize
2152                                  * them in stmmac_rx_refill() function so that
2153                                  * device can reuse it.
2154                                  */
2155                                 priv->rx_skbuff[entry] = NULL;
2156                                 dma_unmap_single(priv->device,
2157                                                  priv->rx_skbuff_dma[entry],
2158                                                  priv->dma_buf_sz,
2159                                                  DMA_FROM_DEVICE);
2160                         }
2161                 } else {
2162                         struct sk_buff *skb;
2163                         int frame_len;
2164
2165                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2166
2167                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2168                          * Type frames (LLC/LLC-SNAP)
2169                          */
2170                         if (unlikely(status != llc_snap))
2171                                 frame_len -= ETH_FCS_LEN;
2172
2173                         if (netif_msg_rx_status(priv)) {
2174                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2175                                          p, entry, p->des2);
2176                                 if (frame_len > ETH_FRAME_LEN)
2177                                         pr_debug("\tframe size %d, COE: %d\n",
2178                                                  frame_len, status);
2179                         }
2180                         skb = priv->rx_skbuff[entry];
2181                         if (unlikely(!skb)) {
2182                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2183                                        priv->dev->name);
2184                                 priv->dev->stats.rx_dropped++;
2185                                 break;
2186                         }
2187                         prefetch(skb->data - NET_IP_ALIGN);
2188                         priv->rx_skbuff[entry] = NULL;
2189
2190                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2191
2192                         skb_put(skb, frame_len);
2193                         dma_unmap_single(priv->device,
2194                                          priv->rx_skbuff_dma[entry],
2195                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2196
2197                         if (netif_msg_pktdata(priv)) {
2198                                 pr_debug("frame received (%dbytes)", frame_len);
2199                                 print_pkt(skb->data, frame_len);
2200                         }
2201
2202                         stmmac_rx_vlan(priv->dev, skb);
2203
2204                         skb->protocol = eth_type_trans(skb, priv->dev);
2205
2206                         if (unlikely(!coe))
2207                                 skb_checksum_none_assert(skb);
2208                         else
2209                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2210
2211                         napi_gro_receive(&priv->napi, skb);
2212
2213                         priv->dev->stats.rx_packets++;
2214                         priv->dev->stats.rx_bytes += frame_len;
2215                 }
2216                 entry = next_entry;
2217         }
2218
2219         stmmac_rx_refill(priv);
2220
2221         priv->xstats.rx_pkt_n += count;
2222
2223         return count;
2224 }
2225
2226 /**
2227  *  stmmac_poll - stmmac poll method (NAPI)
2228  *  @napi : pointer to the napi structure.
2229  *  @budget : maximum number of packets that the current CPU can receive from
2230  *            all interfaces.
2231  *  Description :
2232  *  To look at the incoming frames and clear the tx resources.
2233  */
2234 static int stmmac_poll(struct napi_struct *napi, int budget)
2235 {
2236         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2237         int work_done = 0;
2238
2239         priv->xstats.napi_poll++;
2240         stmmac_tx_clean(priv);
2241
2242         work_done = stmmac_rx(priv, budget);
2243         if (work_done < budget) {
2244                 napi_complete(napi);
2245                 stmmac_enable_dma_irq(priv);
2246         }
2247         return work_done;
2248 }
2249
2250 /**
2251  *  stmmac_tx_timeout
2252  *  @dev : Pointer to net device structure
2253  *  Description: this function is called when a packet transmission fails to
2254  *   complete within a reasonable time. The driver will mark the error in the
2255  *   netdev structure and arrange for the device to be reset to a sane state
2256  *   in order to transmit a new packet.
2257  */
2258 static void stmmac_tx_timeout(struct net_device *dev)
2259 {
2260         struct stmmac_priv *priv = netdev_priv(dev);
2261
2262         /* Clear Tx resources and restart transmitting again */
2263         stmmac_tx_err(priv);
2264 }
2265
2266 /**
2267  *  stmmac_set_rx_mode - entry point for multicast addressing
2268  *  @dev : pointer to the device structure
2269  *  Description:
2270  *  This function is a driver entry point which gets called by the kernel
2271  *  whenever multicast addresses must be enabled/disabled.
2272  *  Return value:
2273  *  void.
2274  */
2275 static void stmmac_set_rx_mode(struct net_device *dev)
2276 {
2277         struct stmmac_priv *priv = netdev_priv(dev);
2278
2279         spin_lock(&priv->lock);
2280         priv->hw->mac->set_filter(priv->hw, dev);
2281         spin_unlock(&priv->lock);
2282 }
2283
2284 /**
2285  *  stmmac_change_mtu - entry point to change MTU size for the device.
2286  *  @dev : device pointer.
2287  *  @new_mtu : the new MTU size for the device.
2288  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2289  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2290  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2291  *  Return value:
2292  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2293  *  file on failure.
2294  */
2295 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2296 {
2297         struct stmmac_priv *priv = netdev_priv(dev);
2298         int max_mtu;
2299
2300         if (netif_running(dev)) {
2301                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2302                 return -EBUSY;
2303         }
2304
2305         if (priv->plat->enh_desc)
2306                 max_mtu = JUMBO_LEN;
2307         else
2308                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2309
2310         if (priv->plat->maxmtu < max_mtu)
2311                 max_mtu = priv->plat->maxmtu;
2312
2313         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2314                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2315                 return -EINVAL;
2316         }
2317
2318         dev->mtu = new_mtu;
2319         netdev_update_features(dev);
2320
2321         return 0;
2322 }
2323
2324 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2325                                              netdev_features_t features)
2326 {
2327         struct stmmac_priv *priv = netdev_priv(dev);
2328
2329         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2330                 features &= ~NETIF_F_RXCSUM;
2331         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
2332                 features &= ~NETIF_F_IPV6_CSUM;
2333         if (!priv->plat->tx_coe)
2334                 features &= ~NETIF_F_ALL_CSUM;
2335
2336         /* Some GMAC devices have a bugged Jumbo frame support that
2337          * needs to have the Tx COE disabled for oversized frames
2338          * (due to limited buffer sizes). In this case we disable
2339          * the TX csum insertionin the TDES and not use SF.
2340          */
2341         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2342                 features &= ~NETIF_F_ALL_CSUM;
2343
2344         return features;
2345 }
2346
2347 /**
2348  *  stmmac_interrupt - main ISR
2349  *  @irq: interrupt number.
2350  *  @dev_id: to pass the net device pointer.
2351  *  Description: this is the main driver interrupt service routine.
2352  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2353  *  interrupts.
2354  */
2355 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2356 {
2357         struct net_device *dev = (struct net_device *)dev_id;
2358         struct stmmac_priv *priv = netdev_priv(dev);
2359
2360         if (priv->irq_wake)
2361                 pm_wakeup_event(priv->device, 0);
2362
2363         if (unlikely(!dev)) {
2364                 pr_err("%s: invalid dev pointer\n", __func__);
2365                 return IRQ_NONE;
2366         }
2367
2368         /* To handle GMAC own interrupts */
2369         if (priv->plat->has_gmac) {
2370                 int status = priv->hw->mac->host_irq_status(priv->hw,
2371                                                             &priv->xstats);
2372                 if (unlikely(status)) {
2373                         /* For LPI we need to save the tx status */
2374                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2375                                 priv->tx_path_in_lpi_mode = true;
2376                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2377                                 priv->tx_path_in_lpi_mode = false;
2378                 }
2379         }
2380
2381         /* To handle DMA interrupts */
2382         stmmac_dma_interrupt(priv);
2383
2384         return IRQ_HANDLED;
2385 }
2386
2387 #ifdef CONFIG_NET_POLL_CONTROLLER
2388 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2389  * to allow network I/O with interrupts disabled.
2390  */
2391 static void stmmac_poll_controller(struct net_device *dev)
2392 {
2393         disable_irq(dev->irq);
2394         stmmac_interrupt(dev->irq, dev);
2395         enable_irq(dev->irq);
2396 }
2397 #endif
2398
2399 /**
2400  *  stmmac_ioctl - Entry point for the Ioctl
2401  *  @dev: Device pointer.
2402  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2403  *  a proprietary structure used to pass information to the driver.
2404  *  @cmd: IOCTL command
2405  *  Description:
2406  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2407  */
2408 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2409 {
2410         struct stmmac_priv *priv = netdev_priv(dev);
2411         int ret = -EOPNOTSUPP;
2412
2413         if (!netif_running(dev))
2414                 return -EINVAL;
2415
2416         switch (cmd) {
2417         case SIOCGMIIPHY:
2418         case SIOCGMIIREG:
2419         case SIOCSMIIREG:
2420                 if (!priv->phydev)
2421                         return -EINVAL;
2422                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2423                 break;
2424         case SIOCSHWTSTAMP:
2425                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2426                 break;
2427         default:
2428                 break;
2429         }
2430
2431         return ret;
2432 }
2433
2434 #ifdef CONFIG_STMMAC_DEBUG_FS
2435 static struct dentry *stmmac_fs_dir;
2436 static struct dentry *stmmac_rings_status;
2437 static struct dentry *stmmac_dma_cap;
2438
2439 static void sysfs_display_ring(void *head, int size, int extend_desc,
2440                                struct seq_file *seq)
2441 {
2442         int i;
2443         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2444         struct dma_desc *p = (struct dma_desc *)head;
2445
2446         for (i = 0; i < size; i++) {
2447                 u64 x;
2448                 if (extend_desc) {
2449                         x = *(u64 *) ep;
2450                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2451                                    i, (unsigned int)virt_to_phys(ep),
2452                                    (unsigned int)x, (unsigned int)(x >> 32),
2453                                    ep->basic.des2, ep->basic.des3);
2454                         ep++;
2455                 } else {
2456                         x = *(u64 *) p;
2457                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2458                                    i, (unsigned int)virt_to_phys(ep),
2459                                    (unsigned int)x, (unsigned int)(x >> 32),
2460                                    p->des2, p->des3);
2461                         p++;
2462                 }
2463                 seq_printf(seq, "\n");
2464         }
2465 }
2466
2467 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2468 {
2469         struct net_device *dev = seq->private;
2470         struct stmmac_priv *priv = netdev_priv(dev);
2471         unsigned int txsize = priv->dma_tx_size;
2472         unsigned int rxsize = priv->dma_rx_size;
2473
2474         if (priv->extend_desc) {
2475                 seq_printf(seq, "Extended RX descriptor ring:\n");
2476                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2477                 seq_printf(seq, "Extended TX descriptor ring:\n");
2478                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2479         } else {
2480                 seq_printf(seq, "RX descriptor ring:\n");
2481                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2482                 seq_printf(seq, "TX descriptor ring:\n");
2483                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2484         }
2485
2486         return 0;
2487 }
2488
2489 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2490 {
2491         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2492 }
2493
2494 static const struct file_operations stmmac_rings_status_fops = {
2495         .owner = THIS_MODULE,
2496         .open = stmmac_sysfs_ring_open,
2497         .read = seq_read,
2498         .llseek = seq_lseek,
2499         .release = single_release,
2500 };
2501
2502 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2503 {
2504         struct net_device *dev = seq->private;
2505         struct stmmac_priv *priv = netdev_priv(dev);
2506
2507         if (!priv->hw_cap_support) {
2508                 seq_printf(seq, "DMA HW features not supported\n");
2509                 return 0;
2510         }
2511
2512         seq_printf(seq, "==============================\n");
2513         seq_printf(seq, "\tDMA HW features\n");
2514         seq_printf(seq, "==============================\n");
2515
2516         seq_printf(seq, "\t10/100 Mbps %s\n",
2517                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2518         seq_printf(seq, "\t1000 Mbps %s\n",
2519                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2520         seq_printf(seq, "\tHalf duple %s\n",
2521                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2522         seq_printf(seq, "\tHash Filter: %s\n",
2523                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2524         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2525                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2526         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2527                    (priv->dma_cap.pcs) ? "Y" : "N");
2528         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2529                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2530         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2531                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2532         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2533                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2534         seq_printf(seq, "\tRMON module: %s\n",
2535                    (priv->dma_cap.rmon) ? "Y" : "N");
2536         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2537                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2538         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2539                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2540         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2541                    (priv->dma_cap.eee) ? "Y" : "N");
2542         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2543         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2544                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2545         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2546                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2547         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2548                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2549         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2550                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2551         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2552                    priv->dma_cap.number_rx_channel);
2553         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2554                    priv->dma_cap.number_tx_channel);
2555         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2556                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2557
2558         return 0;
2559 }
2560
2561 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2562 {
2563         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2564 }
2565
2566 static const struct file_operations stmmac_dma_cap_fops = {
2567         .owner = THIS_MODULE,
2568         .open = stmmac_sysfs_dma_cap_open,
2569         .read = seq_read,
2570         .llseek = seq_lseek,
2571         .release = single_release,
2572 };
2573
2574 static int stmmac_init_fs(struct net_device *dev)
2575 {
2576         /* Create debugfs entries */
2577         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2578
2579         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2580                 pr_err("ERROR %s, debugfs create directory failed\n",
2581                        STMMAC_RESOURCE_NAME);
2582
2583                 return -ENOMEM;
2584         }
2585
2586         /* Entry to report DMA RX/TX rings */
2587         stmmac_rings_status = debugfs_create_file("descriptors_status",
2588                                                   S_IRUGO, stmmac_fs_dir, dev,
2589                                                   &stmmac_rings_status_fops);
2590
2591         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2592                 pr_info("ERROR creating stmmac ring debugfs file\n");
2593                 debugfs_remove(stmmac_fs_dir);
2594
2595                 return -ENOMEM;
2596         }
2597
2598         /* Entry to report the DMA HW features */
2599         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2600                                              dev, &stmmac_dma_cap_fops);
2601
2602         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2603                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2604                 debugfs_remove(stmmac_rings_status);
2605                 debugfs_remove(stmmac_fs_dir);
2606
2607                 return -ENOMEM;
2608         }
2609
2610         return 0;
2611 }
2612
2613 static void stmmac_exit_fs(void)
2614 {
2615         debugfs_remove(stmmac_rings_status);
2616         debugfs_remove(stmmac_dma_cap);
2617         debugfs_remove(stmmac_fs_dir);
2618 }
2619 #endif /* CONFIG_STMMAC_DEBUG_FS */
2620
2621 static const struct net_device_ops stmmac_netdev_ops = {
2622         .ndo_open = stmmac_open,
2623         .ndo_start_xmit = stmmac_xmit,
2624         .ndo_stop = stmmac_release,
2625         .ndo_change_mtu = stmmac_change_mtu,
2626         .ndo_fix_features = stmmac_fix_features,
2627         .ndo_set_rx_mode = stmmac_set_rx_mode,
2628         .ndo_tx_timeout = stmmac_tx_timeout,
2629         .ndo_do_ioctl = stmmac_ioctl,
2630 #ifdef CONFIG_NET_POLL_CONTROLLER
2631         .ndo_poll_controller = stmmac_poll_controller,
2632 #endif
2633         .ndo_set_mac_address = eth_mac_addr,
2634 };
2635
2636 /**
2637  *  stmmac_hw_init - Init the MAC device
2638  *  @priv: driver private structure
2639  *  Description: this function detects which MAC device
2640  *  (GMAC/MAC10-100) has to attached, checks the HW capability
2641  *  (if supported) and sets the driver's features (for example
2642  *  to use the ring or chaine mode or support the normal/enh
2643  *  descriptor structure).
2644  */
2645 static int stmmac_hw_init(struct stmmac_priv *priv)
2646 {
2647         struct mac_device_info *mac;
2648
2649         /* Identify the MAC HW device */
2650         if (priv->plat->has_gmac) {
2651                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2652                 mac = dwmac1000_setup(priv->ioaddr,
2653                                       priv->plat->multicast_filter_bins,
2654                                       priv->plat->unicast_filter_entries);
2655         } else {
2656                 mac = dwmac100_setup(priv->ioaddr);
2657         }
2658         if (!mac)
2659                 return -ENOMEM;
2660
2661         priv->hw = mac;
2662
2663         /* Get and dump the chip ID */
2664         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2665
2666         /* To use the chained or ring mode */
2667         if (chain_mode) {
2668                 priv->hw->mode = &chain_mode_ops;
2669                 pr_info(" Chain mode enabled\n");
2670                 priv->mode = STMMAC_CHAIN_MODE;
2671         } else {
2672                 priv->hw->mode = &ring_mode_ops;
2673                 pr_info(" Ring mode enabled\n");
2674                 priv->mode = STMMAC_RING_MODE;
2675         }
2676
2677         /* Get the HW capability (new GMAC newer than 3.50a) */
2678         priv->hw_cap_support = stmmac_get_hw_features(priv);
2679         if (priv->hw_cap_support) {
2680                 pr_info(" DMA HW capability register supported");
2681
2682                 /* We can override some gmac/dma configuration fields: e.g.
2683                  * enh_desc, tx_coe (e.g. that are passed through the
2684                  * platform) with the values from the HW capability
2685                  * register (if supported).
2686                  */
2687                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2688                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2689
2690                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
2691
2692                 if (priv->dma_cap.rx_coe_type2)
2693                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2694                 else if (priv->dma_cap.rx_coe_type1)
2695                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2696
2697         } else
2698                 pr_info(" No HW DMA feature register supported");
2699
2700         /* To use alternate (extended) or normal descriptor structures */
2701         stmmac_selec_desc_mode(priv);
2702
2703         if (priv->plat->rx_coe)
2704                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2705                         priv->plat->rx_coe);
2706         if (priv->plat->tx_coe)
2707                 pr_info(" TX Checksum insertion supported\n");
2708
2709         if (priv->plat->pmt) {
2710                 pr_info(" Wake-Up On Lan supported\n");
2711                 device_set_wakeup_capable(priv->device, 1);
2712         }
2713
2714         return 0;
2715 }
2716
2717 /**
2718  * stmmac_dvr_probe
2719  * @device: device pointer
2720  * @plat_dat: platform data pointer
2721  * @addr: iobase memory address
2722  * Description: this is the main probe function used to
2723  * call the alloc_etherdev, allocate the priv structure.
2724  */
2725 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
2726                                      struct plat_stmmacenet_data *plat_dat,
2727                                      void __iomem *addr)
2728 {
2729         int ret = 0;
2730         struct net_device *ndev = NULL;
2731         struct stmmac_priv *priv;
2732
2733         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2734         if (!ndev)
2735                 return NULL;
2736
2737         SET_NETDEV_DEV(ndev, device);
2738
2739         priv = netdev_priv(ndev);
2740         priv->device = device;
2741         priv->dev = ndev;
2742
2743         ether_setup(ndev);
2744
2745         stmmac_set_ethtool_ops(ndev);
2746         priv->pause = pause;
2747         priv->plat = plat_dat;
2748         priv->ioaddr = addr;
2749         priv->dev->base_addr = (unsigned long)addr;
2750
2751         /* Verify driver arguments */
2752         stmmac_verify_args();
2753
2754         /* Override with kernel parameters if supplied XXX CRS XXX
2755          * this needs to have multiple instances
2756          */
2757         if ((phyaddr >= 0) && (phyaddr <= 31))
2758                 priv->plat->phy_addr = phyaddr;
2759
2760         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2761         if (IS_ERR(priv->stmmac_clk)) {
2762                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2763                          __func__);
2764                 ret = PTR_ERR(priv->stmmac_clk);
2765                 goto error_clk_get;
2766         }
2767         clk_prepare_enable(priv->stmmac_clk);
2768
2769         priv->stmmac_rst = devm_reset_control_get(priv->device,
2770                                                   STMMAC_RESOURCE_NAME);
2771         if (IS_ERR(priv->stmmac_rst)) {
2772                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2773                         ret = -EPROBE_DEFER;
2774                         goto error_hw_init;
2775                 }
2776                 dev_info(priv->device, "no reset control found\n");
2777                 priv->stmmac_rst = NULL;
2778         }
2779         if (priv->stmmac_rst)
2780                 reset_control_deassert(priv->stmmac_rst);
2781
2782         /* Init MAC and get the capabilities */
2783         ret = stmmac_hw_init(priv);
2784         if (ret)
2785                 goto error_hw_init;
2786
2787         ndev->netdev_ops = &stmmac_netdev_ops;
2788
2789         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2790                             NETIF_F_RXCSUM;
2791         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2792         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2793 #ifdef STMMAC_VLAN_TAG_USED
2794         /* Both mac100 and gmac support receive VLAN tag detection */
2795         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2796 #endif
2797         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2798
2799         if (flow_ctrl)
2800                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2801
2802         /* Rx Watchdog is available in the COREs newer than the 3.40.
2803          * In some case, for example on bugged HW this feature
2804          * has to be disable and this can be done by passing the
2805          * riwt_off field from the platform.
2806          */
2807         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2808                 priv->use_riwt = 1;
2809                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2810         }
2811
2812         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2813
2814         spin_lock_init(&priv->lock);
2815         spin_lock_init(&priv->tx_lock);
2816
2817         ret = register_netdev(ndev);
2818         if (ret) {
2819                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2820                 goto error_netdev_register;
2821         }
2822
2823         /* If a specific clk_csr value is passed from the platform
2824          * this means that the CSR Clock Range selection cannot be
2825          * changed at run-time and it is fixed. Viceversa the driver'll try to
2826          * set the MDC clock dynamically according to the csr actual
2827          * clock input.
2828          */
2829         if (!priv->plat->clk_csr)
2830                 stmmac_clk_csr_set(priv);
2831         else
2832                 priv->clk_csr = priv->plat->clk_csr;
2833
2834         stmmac_check_pcs_mode(priv);
2835
2836         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2837             priv->pcs != STMMAC_PCS_RTBI) {
2838                 /* MDIO bus Registration */
2839                 ret = stmmac_mdio_register(ndev);
2840                 if (ret < 0) {
2841                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2842                                  __func__, priv->plat->bus_id);
2843                         goto error_mdio_register;
2844                 }
2845         }
2846
2847         return priv;
2848
2849 error_mdio_register:
2850         unregister_netdev(ndev);
2851 error_netdev_register:
2852         netif_napi_del(&priv->napi);
2853 error_hw_init:
2854         clk_disable_unprepare(priv->stmmac_clk);
2855 error_clk_get:
2856         free_netdev(ndev);
2857
2858         return ERR_PTR(ret);
2859 }
2860
2861 /**
2862  * stmmac_dvr_remove
2863  * @ndev: net device pointer
2864  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2865  * changes the link status, releases the DMA descriptor rings.
2866  */
2867 int stmmac_dvr_remove(struct net_device *ndev)
2868 {
2869         struct stmmac_priv *priv = netdev_priv(ndev);
2870
2871         pr_info("%s:\n\tremoving driver", __func__);
2872
2873         priv->hw->dma->stop_rx(priv->ioaddr);
2874         priv->hw->dma->stop_tx(priv->ioaddr);
2875
2876         stmmac_set_mac(priv->ioaddr, false);
2877         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2878             priv->pcs != STMMAC_PCS_RTBI)
2879                 stmmac_mdio_unregister(ndev);
2880         netif_carrier_off(ndev);
2881         unregister_netdev(ndev);
2882         if (priv->stmmac_rst)
2883                 reset_control_assert(priv->stmmac_rst);
2884         clk_disable_unprepare(priv->stmmac_clk);
2885         free_netdev(ndev);
2886
2887         return 0;
2888 }
2889
2890 #ifdef CONFIG_PM
2891 int stmmac_suspend(struct net_device *ndev)
2892 {
2893         struct stmmac_priv *priv = netdev_priv(ndev);
2894         unsigned long flags;
2895
2896         if (!ndev || !netif_running(ndev))
2897                 return 0;
2898
2899         if (priv->phydev)
2900                 phy_stop(priv->phydev);
2901
2902         spin_lock_irqsave(&priv->lock, flags);
2903
2904         netif_device_detach(ndev);
2905         netif_stop_queue(ndev);
2906
2907         napi_disable(&priv->napi);
2908
2909         /* Stop TX/RX DMA */
2910         priv->hw->dma->stop_tx(priv->ioaddr);
2911         priv->hw->dma->stop_rx(priv->ioaddr);
2912
2913         stmmac_clear_descriptors(priv);
2914
2915         /* Enable Power down mode by programming the PMT regs */
2916         if (device_may_wakeup(priv->device)) {
2917                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
2918                 priv->irq_wake = 1;
2919         } else {
2920                 stmmac_set_mac(priv->ioaddr, false);
2921                 pinctrl_pm_select_sleep_state(priv->device);
2922                 /* Disable clock in case of PWM is off */
2923                 clk_disable_unprepare(priv->stmmac_clk);
2924         }
2925         spin_unlock_irqrestore(&priv->lock, flags);
2926
2927         priv->oldlink = 0;
2928         priv->speed = 0;
2929         priv->oldduplex = -1;
2930         return 0;
2931 }
2932
2933 int stmmac_resume(struct net_device *ndev)
2934 {
2935         struct stmmac_priv *priv = netdev_priv(ndev);
2936         unsigned long flags;
2937
2938         if (!netif_running(ndev))
2939                 return 0;
2940
2941         spin_lock_irqsave(&priv->lock, flags);
2942
2943         /* Power Down bit, into the PM register, is cleared
2944          * automatically as soon as a magic packet or a Wake-up frame
2945          * is received. Anyway, it's better to manually clear
2946          * this bit because it can generate problems while resuming
2947          * from another devices (e.g. serial console).
2948          */
2949         if (device_may_wakeup(priv->device)) {
2950                 priv->hw->mac->pmt(priv->hw, 0);
2951                 priv->irq_wake = 0;
2952         } else {
2953                 pinctrl_pm_select_default_state(priv->device);
2954                 /* enable the clk prevously disabled */
2955                 clk_prepare_enable(priv->stmmac_clk);
2956                 /* reset the phy so that it's ready */
2957                 if (priv->mii)
2958                         stmmac_mdio_reset(priv->mii);
2959         }
2960
2961         netif_device_attach(ndev);
2962
2963         stmmac_hw_setup(ndev);
2964
2965         napi_enable(&priv->napi);
2966
2967         netif_start_queue(ndev);
2968
2969         spin_unlock_irqrestore(&priv->lock, flags);
2970
2971         if (priv->phydev)
2972                 phy_start(priv->phydev);
2973
2974         return 0;
2975 }
2976 #endif /* CONFIG_PM */
2977
2978 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2979  * depending on the configuration selected.
2980  */
2981 static int __init stmmac_init(void)
2982 {
2983         int ret;
2984
2985         ret = stmmac_register_platform();
2986         if (ret)
2987                 goto err;
2988         ret = stmmac_register_pci();
2989         if (ret)
2990                 goto err_pci;
2991         return 0;
2992 err_pci:
2993         stmmac_unregister_platform();
2994 err:
2995         pr_err("stmmac: driver registration failed\n");
2996         return ret;
2997 }
2998
2999 static void __exit stmmac_exit(void)
3000 {
3001         stmmac_unregister_platform();
3002         stmmac_unregister_pci();
3003 }
3004
3005 module_init(stmmac_init);
3006 module_exit(stmmac_exit);
3007
3008 #ifndef MODULE
3009 static int __init stmmac_cmdline_opt(char *str)
3010 {
3011         char *opt;
3012
3013         if (!str || !*str)
3014                 return -EINVAL;
3015         while ((opt = strsep(&str, ",")) != NULL) {
3016                 if (!strncmp(opt, "debug:", 6)) {
3017                         if (kstrtoint(opt + 6, 0, &debug))
3018                                 goto err;
3019                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3020                         if (kstrtoint(opt + 8, 0, &phyaddr))
3021                                 goto err;
3022                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3023                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3024                                 goto err;
3025                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3026                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3027                                 goto err;
3028                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3029                         if (kstrtoint(opt + 7, 0, &buf_sz))
3030                                 goto err;
3031                 } else if (!strncmp(opt, "tc:", 3)) {
3032                         if (kstrtoint(opt + 3, 0, &tc))
3033                                 goto err;
3034                 } else if (!strncmp(opt, "watchdog:", 9)) {
3035                         if (kstrtoint(opt + 9, 0, &watchdog))
3036                                 goto err;
3037                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3038                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3039                                 goto err;
3040                 } else if (!strncmp(opt, "pause:", 6)) {
3041                         if (kstrtoint(opt + 6, 0, &pause))
3042                                 goto err;
3043                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3044                         if (kstrtoint(opt + 10, 0, &eee_timer))
3045                                 goto err;
3046                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3047                         if (kstrtoint(opt + 11, 0, &chain_mode))
3048                                 goto err;
3049                 }
3050         }
3051         return 0;
3052
3053 err:
3054         pr_err("%s: ERROR broken module parameter conversion", __func__);
3055         return -EINVAL;
3056 }
3057
3058 __setup("stmmaceth=", stmmac_cmdline_opt);
3059 #endif /* MODULE */
3060
3061 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3062 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3063 MODULE_LICENSE("GPL");