2 * Xilinx Axi Ethernet device driver
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
8 * Copyright (c) 2010 - 2011 PetaLogix
9 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
11 * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
15 * - Add Axi Fifo support.
16 * - Factor out Axi DMA code into separate driver.
17 * - Test and fix basic multicast filtering.
18 * - Add support for extended multicast filtering.
19 * - Test basic VLAN support.
20 * - Add support for extended VLAN support.
23 #include <linux/delay.h>
24 #include <linux/etherdevice.h>
25 #include <linux/module.h>
26 #include <linux/netdevice.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_platform.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_address.h>
31 #include <linux/skbuff.h>
32 #include <linux/spinlock.h>
33 #include <linux/phy.h>
34 #include <linux/mii.h>
35 #include <linux/ethtool.h>
37 #include "xilinx_axienet.h"
39 /* Descriptors defines for Tx and Rx DMA - 2^n for the best performance */
43 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */
44 #define DRIVER_NAME "xaxienet"
45 #define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
46 #define DRIVER_VERSION "1.00a"
48 #define AXIENET_REGS_N 32
50 /* Match table for of_platform binding */
51 static const struct of_device_id axienet_of_match[] = {
52 { .compatible = "xlnx,axi-ethernet-1.00.a", },
53 { .compatible = "xlnx,axi-ethernet-1.01.a", },
54 { .compatible = "xlnx,axi-ethernet-2.01.a", },
58 MODULE_DEVICE_TABLE(of, axienet_of_match);
60 /* Option table for setting up Axi Ethernet hardware options */
61 static struct axienet_option axienet_options[] = {
62 /* Turn on jumbo packet support for both Rx and Tx */
64 .opt = XAE_OPTION_JUMBO,
66 .m_or = XAE_TC_JUM_MASK,
68 .opt = XAE_OPTION_JUMBO,
69 .reg = XAE_RCW1_OFFSET,
70 .m_or = XAE_RCW1_JUM_MASK,
71 }, { /* Turn on VLAN packet support for both Rx and Tx */
72 .opt = XAE_OPTION_VLAN,
74 .m_or = XAE_TC_VLAN_MASK,
76 .opt = XAE_OPTION_VLAN,
77 .reg = XAE_RCW1_OFFSET,
78 .m_or = XAE_RCW1_VLAN_MASK,
79 }, { /* Turn on FCS stripping on receive packets */
80 .opt = XAE_OPTION_FCS_STRIP,
81 .reg = XAE_RCW1_OFFSET,
82 .m_or = XAE_RCW1_FCS_MASK,
83 }, { /* Turn on FCS insertion on transmit packets */
84 .opt = XAE_OPTION_FCS_INSERT,
86 .m_or = XAE_TC_FCS_MASK,
87 }, { /* Turn off length/type field checking on receive packets */
88 .opt = XAE_OPTION_LENTYPE_ERR,
89 .reg = XAE_RCW1_OFFSET,
90 .m_or = XAE_RCW1_LT_DIS_MASK,
91 }, { /* Turn on Rx flow control */
92 .opt = XAE_OPTION_FLOW_CONTROL,
93 .reg = XAE_FCC_OFFSET,
94 .m_or = XAE_FCC_FCRX_MASK,
95 }, { /* Turn on Tx flow control */
96 .opt = XAE_OPTION_FLOW_CONTROL,
97 .reg = XAE_FCC_OFFSET,
98 .m_or = XAE_FCC_FCTX_MASK,
99 }, { /* Turn on promiscuous frame filtering */
100 .opt = XAE_OPTION_PROMISC,
101 .reg = XAE_FMI_OFFSET,
102 .m_or = XAE_FMI_PM_MASK,
103 }, { /* Enable transmitter */
104 .opt = XAE_OPTION_TXEN,
105 .reg = XAE_TC_OFFSET,
106 .m_or = XAE_TC_TX_MASK,
107 }, { /* Enable receiver */
108 .opt = XAE_OPTION_RXEN,
109 .reg = XAE_RCW1_OFFSET,
110 .m_or = XAE_RCW1_RX_MASK,
116 * axienet_dma_in32 - Memory mapped Axi DMA register read
117 * @lp: Pointer to axienet local structure
118 * @reg: Address offset from the base address of the Axi DMA core
120 * returns: The contents of the Axi DMA register
122 * This function returns the contents of the corresponding Axi DMA register.
124 static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
126 return in_be32(lp->dma_regs + reg);
130 * axienet_dma_out32 - Memory mapped Axi DMA register write.
131 * @lp: Pointer to axienet local structure
132 * @reg: Address offset from the base address of the Axi DMA core
133 * @value: Value to be written into the Axi DMA register
135 * This function writes the desired value into the corresponding Axi DMA
138 static inline void axienet_dma_out32(struct axienet_local *lp,
139 off_t reg, u32 value)
141 out_be32((lp->dma_regs + reg), value);
145 * axienet_dma_bd_release - Release buffer descriptor rings
146 * @ndev: Pointer to the net_device structure
148 * This function is used to release the descriptors allocated in
149 * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
150 * driver stop api is called.
152 static void axienet_dma_bd_release(struct net_device *ndev)
155 struct axienet_local *lp = netdev_priv(ndev);
157 for (i = 0; i < RX_BD_NUM; i++) {
158 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
159 lp->max_frm_size, DMA_FROM_DEVICE);
160 dev_kfree_skb((struct sk_buff *)
161 (lp->rx_bd_v[i].sw_id_offset));
165 dma_free_coherent(ndev->dev.parent,
166 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
171 dma_free_coherent(ndev->dev.parent,
172 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
179 * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
180 * @ndev: Pointer to the net_device structure
182 * returns: 0, on success
183 * -ENOMEM, on failure
185 * This function is called to initialize the Rx and Tx DMA descriptor
186 * rings. This initializes the descriptors with required default values
187 * and is called when Axi Ethernet driver reset is called.
189 static int axienet_dma_bd_init(struct net_device *ndev)
194 struct axienet_local *lp = netdev_priv(ndev);
196 /* Reset the indexes which are used for accessing the BDs */
202 * Allocate the Tx and Rx buffer descriptors.
204 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
205 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
206 &lp->tx_bd_p, GFP_KERNEL);
210 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
211 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
212 &lp->rx_bd_p, GFP_KERNEL);
216 for (i = 0; i < TX_BD_NUM; i++) {
217 lp->tx_bd_v[i].next = lp->tx_bd_p +
218 sizeof(*lp->tx_bd_v) *
219 ((i + 1) % TX_BD_NUM);
222 for (i = 0; i < RX_BD_NUM; i++) {
223 lp->rx_bd_v[i].next = lp->rx_bd_p +
224 sizeof(*lp->rx_bd_v) *
225 ((i + 1) % RX_BD_NUM);
227 skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
231 lp->rx_bd_v[i].sw_id_offset = (u32) skb;
232 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
236 lp->rx_bd_v[i].cntrl = lp->max_frm_size;
239 /* Start updating the Rx channel control register */
240 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
241 /* Update the interrupt coalesce count */
242 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
243 ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
244 /* Update the delay timer count */
245 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
246 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
247 /* Enable coalesce, delay timer and error interrupts */
248 cr |= XAXIDMA_IRQ_ALL_MASK;
249 /* Write to the Rx channel control register */
250 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
252 /* Start updating the Tx channel control register */
253 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
254 /* Update the interrupt coalesce count */
255 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
256 ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
257 /* Update the delay timer count */
258 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
259 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
260 /* Enable coalesce, delay timer and error interrupts */
261 cr |= XAXIDMA_IRQ_ALL_MASK;
262 /* Write to the Tx channel control register */
263 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
265 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
266 * halted state. This will make the Rx side ready for reception.*/
267 axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
268 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
269 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
270 cr | XAXIDMA_CR_RUNSTOP_MASK);
271 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
272 (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
274 /* Write to the RS (Run-stop) bit in the Tx channel control register.
275 * Tx channel is now ready to run. But only after we write to the
276 * tail pointer register that the Tx channel will start transmitting */
277 axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
278 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
279 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
280 cr | XAXIDMA_CR_RUNSTOP_MASK);
284 axienet_dma_bd_release(ndev);
289 * axienet_set_mac_address - Write the MAC address
290 * @ndev: Pointer to the net_device structure
291 * @address: 6 byte Address to be written as MAC address
293 * This function is called to initialize the MAC address of the Axi Ethernet
294 * core. It writes to the UAW0 and UAW1 registers of the core.
296 static void axienet_set_mac_address(struct net_device *ndev, void *address)
298 struct axienet_local *lp = netdev_priv(ndev);
301 memcpy(ndev->dev_addr, address, ETH_ALEN);
302 if (!is_valid_ether_addr(ndev->dev_addr))
303 eth_random_addr(ndev->dev_addr);
305 /* Set up unicast MAC address filter set its mac address */
306 axienet_iow(lp, XAE_UAW0_OFFSET,
307 (ndev->dev_addr[0]) |
308 (ndev->dev_addr[1] << 8) |
309 (ndev->dev_addr[2] << 16) |
310 (ndev->dev_addr[3] << 24));
311 axienet_iow(lp, XAE_UAW1_OFFSET,
312 (((axienet_ior(lp, XAE_UAW1_OFFSET)) &
313 ~XAE_UAW1_UNICASTADDR_MASK) |
315 (ndev->dev_addr[5] << 8))));
319 * netdev_set_mac_address - Write the MAC address (from outside the driver)
320 * @ndev: Pointer to the net_device structure
321 * @p: 6 byte Address to be written as MAC address
323 * returns: 0 for all conditions. Presently, there is no failure case.
325 * This function is called to initialize the MAC address of the Axi Ethernet
326 * core. It calls the core specific axienet_set_mac_address. This is the
327 * function that goes into net_device_ops structure entry ndo_set_mac_address.
329 static int netdev_set_mac_address(struct net_device *ndev, void *p)
331 struct sockaddr *addr = p;
332 axienet_set_mac_address(ndev, addr->sa_data);
337 * axienet_set_multicast_list - Prepare the multicast table
338 * @ndev: Pointer to the net_device structure
340 * This function is called to initialize the multicast table during
341 * initialization. The Axi Ethernet basic multicast support has a four-entry
342 * multicast table which is initialized here. Additionally this function
343 * goes into the net_device_ops structure entry ndo_set_multicast_list. This
344 * means whenever the multicast table entries need to be updated this
345 * function gets called.
347 static void axienet_set_multicast_list(struct net_device *ndev)
350 u32 reg, af0reg, af1reg;
351 struct axienet_local *lp = netdev_priv(ndev);
353 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
354 netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
355 /* We must make the kernel realize we had to move into
356 * promiscuous mode. If it was a promiscuous mode request
357 * the flag is already set. If not we set it. */
358 ndev->flags |= IFF_PROMISC;
359 reg = axienet_ior(lp, XAE_FMI_OFFSET);
360 reg |= XAE_FMI_PM_MASK;
361 axienet_iow(lp, XAE_FMI_OFFSET, reg);
362 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
363 } else if (!netdev_mc_empty(ndev)) {
364 struct netdev_hw_addr *ha;
367 netdev_for_each_mc_addr(ha, ndev) {
368 if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
371 af0reg = (ha->addr[0]);
372 af0reg |= (ha->addr[1] << 8);
373 af0reg |= (ha->addr[2] << 16);
374 af0reg |= (ha->addr[3] << 24);
376 af1reg = (ha->addr[4]);
377 af1reg |= (ha->addr[5] << 8);
379 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
382 axienet_iow(lp, XAE_FMI_OFFSET, reg);
383 axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
384 axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
388 reg = axienet_ior(lp, XAE_FMI_OFFSET);
389 reg &= ~XAE_FMI_PM_MASK;
391 axienet_iow(lp, XAE_FMI_OFFSET, reg);
393 for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
394 reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
397 axienet_iow(lp, XAE_FMI_OFFSET, reg);
398 axienet_iow(lp, XAE_AF0_OFFSET, 0);
399 axienet_iow(lp, XAE_AF1_OFFSET, 0);
402 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
407 * axienet_setoptions - Set an Axi Ethernet option
408 * @ndev: Pointer to the net_device structure
409 * @options: Option to be enabled/disabled
411 * The Axi Ethernet core has multiple features which can be selectively turned
412 * on or off. The typical options could be jumbo frame option, basic VLAN
413 * option, promiscuous mode option etc. This function is used to set or clear
414 * these options in the Axi Ethernet hardware. This is done through
415 * axienet_option structure .
417 static void axienet_setoptions(struct net_device *ndev, u32 options)
420 struct axienet_local *lp = netdev_priv(ndev);
421 struct axienet_option *tp = &axienet_options[0];
424 reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
425 if (options & tp->opt)
427 axienet_iow(lp, tp->reg, reg);
431 lp->options |= options;
434 static void __axienet_device_reset(struct axienet_local *lp,
435 struct device *dev, off_t offset)
438 /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
439 * process of Axi DMA takes a while to complete as all pending
440 * commands/transfers will be flushed or completed during this
442 axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
443 timeout = DELAY_OF_ONE_MILLISEC;
444 while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
446 if (--timeout == 0) {
447 netdev_err(lp->ndev, "%s: DMA reset timeout!\n",
455 * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
456 * @ndev: Pointer to the net_device structure
458 * This function is called to reset and initialize the Axi Ethernet core. This
459 * is typically called during initialization. It does a reset of the Axi DMA
460 * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
461 * areconnected to Axi Ethernet reset lines, this in turn resets the Axi
462 * Ethernet core. No separate hardware reset is done for the Axi Ethernet
465 static void axienet_device_reset(struct net_device *ndev)
468 struct axienet_local *lp = netdev_priv(ndev);
470 __axienet_device_reset(lp, &ndev->dev, XAXIDMA_TX_CR_OFFSET);
471 __axienet_device_reset(lp, &ndev->dev, XAXIDMA_RX_CR_OFFSET);
473 lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
474 lp->options |= XAE_OPTION_VLAN;
475 lp->options &= (~XAE_OPTION_JUMBO);
477 if ((ndev->mtu > XAE_MTU) &&
478 (ndev->mtu <= XAE_JUMBO_MTU)) {
479 lp->max_frm_size = ndev->mtu + VLAN_ETH_HLEN +
482 if (lp->max_frm_size <= lp->rxmem)
483 lp->options |= XAE_OPTION_JUMBO;
486 if (axienet_dma_bd_init(ndev)) {
487 netdev_err(ndev, "%s: descriptor allocation failed\n",
491 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
492 axienet_status &= ~XAE_RCW1_RX_MASK;
493 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
495 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
496 if (axienet_status & XAE_INT_RXRJECT_MASK)
497 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
499 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
501 /* Sync default options with HW but leave receiver and
502 * transmitter disabled.*/
503 axienet_setoptions(ndev, lp->options &
504 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
505 axienet_set_mac_address(ndev, NULL);
506 axienet_set_multicast_list(ndev);
507 axienet_setoptions(ndev, lp->options);
509 ndev->trans_start = jiffies;
513 * axienet_adjust_link - Adjust the PHY link speed/duplex.
514 * @ndev: Pointer to the net_device structure
516 * This function is called to change the speed and duplex setting after
517 * auto negotiation is done by the PHY. This is the function that gets
518 * registered with the PHY interface through the "of_phy_connect" call.
520 static void axienet_adjust_link(struct net_device *ndev)
525 struct axienet_local *lp = netdev_priv(ndev);
526 struct phy_device *phy = lp->phy_dev;
528 link_state = phy->speed | (phy->duplex << 1) | phy->link;
529 if (lp->last_link != link_state) {
530 if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) {
531 if (lp->phy_type == XAE_PHY_TYPE_1000BASE_X)
534 if ((phy->speed == SPEED_1000) &&
535 (lp->phy_type == XAE_PHY_TYPE_MII))
540 emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
541 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
543 switch (phy->speed) {
545 emmc_reg |= XAE_EMMC_LINKSPD_1000;
548 emmc_reg |= XAE_EMMC_LINKSPD_100;
551 emmc_reg |= XAE_EMMC_LINKSPD_10;
554 dev_err(&ndev->dev, "Speed other than 10, 100 "
555 "or 1Gbps is not supported\n");
559 axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
560 lp->last_link = link_state;
561 phy_print_status(phy);
564 "Error setting Axi Ethernet mac speed\n");
570 * axienet_start_xmit_done - Invoked once a transmit is completed by the
571 * Axi DMA Tx channel.
572 * @ndev: Pointer to the net_device structure
574 * This function is invoked from the Axi DMA Tx isr to notify the completion
575 * of transmit operation. It clears fields in the corresponding Tx BDs and
576 * unmaps the corresponding buffer so that CPU can regain ownership of the
577 * buffer. It finally invokes "netif_wake_queue" to restart transmission if
580 static void axienet_start_xmit_done(struct net_device *ndev)
584 struct axienet_local *lp = netdev_priv(ndev);
585 struct axidma_bd *cur_p;
586 unsigned int status = 0;
588 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
589 status = cur_p->status;
590 while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
591 dma_unmap_single(ndev->dev.parent, cur_p->phys,
592 (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
595 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
603 size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
607 lp->tx_bd_ci %= TX_BD_NUM;
608 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
609 status = cur_p->status;
612 ndev->stats.tx_packets += packets;
613 ndev->stats.tx_bytes += size;
614 netif_wake_queue(ndev);
618 * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
619 * @lp: Pointer to the axienet_local structure
620 * @num_frag: The number of BDs to check for
622 * returns: 0, on success
623 * NETDEV_TX_BUSY, if any of the descriptors are not free
625 * This function is invoked before BDs are allocated and transmission starts.
626 * This function returns 0 if a BD or group of BDs can be allocated for
627 * transmission. If the BD or any of the BDs are not free the function
628 * returns a busy status. This is invoked from axienet_start_xmit.
630 static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
633 struct axidma_bd *cur_p;
634 cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % TX_BD_NUM];
635 if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
636 return NETDEV_TX_BUSY;
641 * axienet_start_xmit - Starts the transmission.
642 * @skb: sk_buff pointer that contains data to be Txed.
643 * @ndev: Pointer to net_device structure.
645 * returns: NETDEV_TX_OK, on success
646 * NETDEV_TX_BUSY, if any of the descriptors are not free
648 * This function is invoked from upper layers to initiate transmission. The
649 * function uses the next available free BDs and populates their fields to
650 * start the transmission. Additionally if checksum offloading is supported,
651 * it populates AXI Stream Control fields with appropriate values.
653 static int axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
661 struct axienet_local *lp = netdev_priv(ndev);
662 struct axidma_bd *cur_p;
664 num_frag = skb_shinfo(skb)->nr_frags;
665 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
667 if (axienet_check_tx_bd_space(lp, num_frag)) {
668 if (!netif_queue_stopped(ndev))
669 netif_stop_queue(ndev);
670 return NETDEV_TX_BUSY;
673 if (skb->ip_summed == CHECKSUM_PARTIAL) {
674 if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
675 /* Tx Full Checksum Offload Enabled */
677 } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) {
678 csum_start_off = skb_transport_offset(skb);
679 csum_index_off = csum_start_off + skb->csum_offset;
680 /* Tx Partial Checksum Offload Enabled */
682 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
684 } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
685 cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
688 cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
689 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
690 skb_headlen(skb), DMA_TO_DEVICE);
692 for (ii = 0; ii < num_frag; ii++) {
694 lp->tx_bd_tail %= TX_BD_NUM;
695 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
696 frag = &skb_shinfo(skb)->frags[ii];
697 cur_p->phys = dma_map_single(ndev->dev.parent,
698 skb_frag_address(frag),
701 cur_p->cntrl = skb_frag_size(frag);
704 cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
705 cur_p->app4 = (unsigned long)skb;
707 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
708 /* Start the transfer */
709 axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
711 lp->tx_bd_tail %= TX_BD_NUM;
717 * axienet_recv - Is called from Axi DMA Rx Isr to complete the received
719 * @ndev: Pointer to net_device structure.
721 * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
722 * does minimal processing and invokes "netif_rx" to complete further
725 static void axienet_recv(struct net_device *ndev)
731 dma_addr_t tail_p = 0;
732 struct axienet_local *lp = netdev_priv(ndev);
733 struct sk_buff *skb, *new_skb;
734 struct axidma_bd *cur_p;
736 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
738 while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
739 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
740 skb = (struct sk_buff *) (cur_p->sw_id_offset);
741 length = cur_p->app4 & 0x0000FFFF;
743 dma_unmap_single(ndev->dev.parent, cur_p->phys,
747 skb_put(skb, length);
748 skb->protocol = eth_type_trans(skb, ndev);
749 /*skb_checksum_none_assert(skb);*/
750 skb->ip_summed = CHECKSUM_NONE;
752 /* if we're doing Rx csum offload, set it up */
753 if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
754 csumstatus = (cur_p->app2 &
755 XAE_FULL_CSUM_STATUS_MASK) >> 3;
756 if ((csumstatus == XAE_IP_TCP_CSUM_VALIDATED) ||
757 (csumstatus == XAE_IP_UDP_CSUM_VALIDATED)) {
758 skb->ip_summed = CHECKSUM_UNNECESSARY;
760 } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
761 skb->protocol == htons(ETH_P_IP) &&
763 skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
764 skb->ip_summed = CHECKSUM_COMPLETE;
772 new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
776 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
779 cur_p->cntrl = lp->max_frm_size;
781 cur_p->sw_id_offset = (u32) new_skb;
784 lp->rx_bd_ci %= RX_BD_NUM;
785 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
788 ndev->stats.rx_packets += packets;
789 ndev->stats.rx_bytes += size;
792 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
796 * axienet_tx_irq - Tx Done Isr.
798 * @_ndev: net_device pointer
800 * returns: IRQ_HANDLED for all cases.
802 * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
803 * to complete the BD processing.
805 static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
809 struct net_device *ndev = _ndev;
810 struct axienet_local *lp = netdev_priv(ndev);
812 status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
813 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
814 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
815 axienet_start_xmit_done(lp->ndev);
818 if (!(status & XAXIDMA_IRQ_ALL_MASK))
819 dev_err(&ndev->dev, "No interrupts asserted in Tx path");
820 if (status & XAXIDMA_IRQ_ERROR_MASK) {
821 dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status);
822 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
823 (lp->tx_bd_v[lp->tx_bd_ci]).phys);
825 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
826 /* Disable coalesce, delay timer and error interrupts */
827 cr &= (~XAXIDMA_IRQ_ALL_MASK);
828 /* Write to the Tx channel control register */
829 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
831 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
832 /* Disable coalesce, delay timer and error interrupts */
833 cr &= (~XAXIDMA_IRQ_ALL_MASK);
834 /* Write to the Rx channel control register */
835 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
837 tasklet_schedule(&lp->dma_err_tasklet);
838 axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
845 * axienet_rx_irq - Rx Isr.
847 * @_ndev: net_device pointer
849 * returns: IRQ_HANDLED for all cases.
851 * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
854 static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
858 struct net_device *ndev = _ndev;
859 struct axienet_local *lp = netdev_priv(ndev);
861 status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
862 if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
863 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
864 axienet_recv(lp->ndev);
867 if (!(status & XAXIDMA_IRQ_ALL_MASK))
868 dev_err(&ndev->dev, "No interrupts asserted in Rx path");
869 if (status & XAXIDMA_IRQ_ERROR_MASK) {
870 dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status);
871 dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
872 (lp->rx_bd_v[lp->rx_bd_ci]).phys);
874 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
875 /* Disable coalesce, delay timer and error interrupts */
876 cr &= (~XAXIDMA_IRQ_ALL_MASK);
877 /* Finally write to the Tx channel control register */
878 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
880 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
881 /* Disable coalesce, delay timer and error interrupts */
882 cr &= (~XAXIDMA_IRQ_ALL_MASK);
883 /* write to the Rx channel control register */
884 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
886 tasklet_schedule(&lp->dma_err_tasklet);
887 axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
893 static void axienet_dma_err_handler(unsigned long data);
896 * axienet_open - Driver open routine.
897 * @ndev: Pointer to net_device structure
899 * returns: 0, on success.
900 * -ENODEV, if PHY cannot be connected to
901 * non-zero error value on failure
903 * This is the driver open routine. It calls phy_start to start the PHY device.
904 * It also allocates interrupt service routines, enables the interrupt lines
905 * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
906 * descriptors are initialized.
908 static int axienet_open(struct net_device *ndev)
911 struct axienet_local *lp = netdev_priv(ndev);
913 dev_dbg(&ndev->dev, "axienet_open()\n");
915 mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
916 ret = axienet_mdio_wait_until_ready(lp);
919 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
920 * When we do an Axi Ethernet reset, it resets the complete core
921 * including the MDIO. If MDIO is not disabled when the reset
922 * process is started, MDIO will be broken afterwards. */
923 axienet_iow(lp, XAE_MDIO_MC_OFFSET,
924 (mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
925 axienet_device_reset(ndev);
926 /* Enable the MDIO */
927 axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
928 ret = axienet_mdio_wait_until_ready(lp);
933 if (lp->phy_type == XAE_PHY_TYPE_GMII) {
934 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
935 axienet_adjust_link, 0,
936 PHY_INTERFACE_MODE_GMII);
937 } else if (lp->phy_type == XAE_PHY_TYPE_RGMII_2_0) {
938 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
939 axienet_adjust_link, 0,
940 PHY_INTERFACE_MODE_RGMII_ID);
944 dev_err(lp->dev, "of_phy_connect() failed\n");
946 phy_start(lp->phy_dev);
949 /* Enable tasklets for Axi DMA error handling */
950 tasklet_init(&lp->dma_err_tasklet, axienet_dma_err_handler,
953 /* Enable interrupts for Axi DMA Tx */
954 ret = request_irq(lp->tx_irq, axienet_tx_irq, 0, ndev->name, ndev);
957 /* Enable interrupts for Axi DMA Rx */
958 ret = request_irq(lp->rx_irq, axienet_rx_irq, 0, ndev->name, ndev);
965 free_irq(lp->tx_irq, ndev);
968 phy_disconnect(lp->phy_dev);
970 tasklet_kill(&lp->dma_err_tasklet);
971 dev_err(lp->dev, "request_irq() failed\n");
976 * axienet_stop - Driver stop routine.
977 * @ndev: Pointer to net_device structure
979 * returns: 0, on success.
981 * This is the driver stop routine. It calls phy_disconnect to stop the PHY
982 * device. It also removes the interrupt handlers and disables the interrupts.
983 * The Axi DMA Tx/Rx BDs are released.
985 static int axienet_stop(struct net_device *ndev)
988 struct axienet_local *lp = netdev_priv(ndev);
990 dev_dbg(&ndev->dev, "axienet_close()\n");
992 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
993 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
994 cr & (~XAXIDMA_CR_RUNSTOP_MASK));
995 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
996 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
997 cr & (~XAXIDMA_CR_RUNSTOP_MASK));
998 axienet_setoptions(ndev, lp->options &
999 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1001 tasklet_kill(&lp->dma_err_tasklet);
1003 free_irq(lp->tx_irq, ndev);
1004 free_irq(lp->rx_irq, ndev);
1007 phy_disconnect(lp->phy_dev);
1010 axienet_dma_bd_release(ndev);
1015 * axienet_change_mtu - Driver change mtu routine.
1016 * @ndev: Pointer to net_device structure
1017 * @new_mtu: New mtu value to be applied
1019 * returns: Always returns 0 (success).
1021 * This is the change mtu driver routine. It checks if the Axi Ethernet
1022 * hardware supports jumbo frames before changing the mtu. This can be
1023 * called only when the device is not up.
1025 static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
1027 struct axienet_local *lp = netdev_priv(ndev);
1029 if (netif_running(ndev))
1032 if ((new_mtu + VLAN_ETH_HLEN +
1033 XAE_TRL_SIZE) > lp->rxmem)
1036 if ((new_mtu > XAE_JUMBO_MTU) || (new_mtu < 64))
1039 ndev->mtu = new_mtu;
1044 #ifdef CONFIG_NET_POLL_CONTROLLER
1046 * axienet_poll_controller - Axi Ethernet poll mechanism.
1047 * @ndev: Pointer to net_device structure
1049 * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1050 * to polling the ISRs and are enabled back after the polling is done.
1052 static void axienet_poll_controller(struct net_device *ndev)
1054 struct axienet_local *lp = netdev_priv(ndev);
1055 disable_irq(lp->tx_irq);
1056 disable_irq(lp->rx_irq);
1057 axienet_rx_irq(lp->tx_irq, ndev);
1058 axienet_tx_irq(lp->rx_irq, ndev);
1059 enable_irq(lp->tx_irq);
1060 enable_irq(lp->rx_irq);
1064 static const struct net_device_ops axienet_netdev_ops = {
1065 .ndo_open = axienet_open,
1066 .ndo_stop = axienet_stop,
1067 .ndo_start_xmit = axienet_start_xmit,
1068 .ndo_change_mtu = axienet_change_mtu,
1069 .ndo_set_mac_address = netdev_set_mac_address,
1070 .ndo_validate_addr = eth_validate_addr,
1071 .ndo_set_rx_mode = axienet_set_multicast_list,
1072 #ifdef CONFIG_NET_POLL_CONTROLLER
1073 .ndo_poll_controller = axienet_poll_controller,
1078 * axienet_ethtools_get_settings - Get Axi Ethernet settings related to PHY.
1079 * @ndev: Pointer to net_device structure
1080 * @ecmd: Pointer to ethtool_cmd structure
1082 * This implements ethtool command for getting PHY settings. If PHY could
1083 * not be found, the function returns -ENODEV. This function calls the
1084 * relevant PHY ethtool API to get the PHY settings.
1085 * Issue "ethtool ethX" under linux prompt to execute this function.
1087 static int axienet_ethtools_get_settings(struct net_device *ndev,
1088 struct ethtool_cmd *ecmd)
1090 struct axienet_local *lp = netdev_priv(ndev);
1091 struct phy_device *phydev = lp->phy_dev;
1094 return phy_ethtool_gset(phydev, ecmd);
1098 * axienet_ethtools_set_settings - Set PHY settings as passed in the argument.
1099 * @ndev: Pointer to net_device structure
1100 * @ecmd: Pointer to ethtool_cmd structure
1102 * This implements ethtool command for setting various PHY settings. If PHY
1103 * could not be found, the function returns -ENODEV. This function calls the
1104 * relevant PHY ethtool API to set the PHY.
1105 * Issue e.g. "ethtool -s ethX speed 1000" under linux prompt to execute this
1108 static int axienet_ethtools_set_settings(struct net_device *ndev,
1109 struct ethtool_cmd *ecmd)
1111 struct axienet_local *lp = netdev_priv(ndev);
1112 struct phy_device *phydev = lp->phy_dev;
1115 return phy_ethtool_sset(phydev, ecmd);
1119 * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1120 * @ndev: Pointer to net_device structure
1121 * @ed: Pointer to ethtool_drvinfo structure
1123 * This implements ethtool command for getting the driver information.
1124 * Issue "ethtool -i ethX" under linux prompt to execute this function.
1126 static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
1127 struct ethtool_drvinfo *ed)
1129 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1130 strlcpy(ed->version, DRIVER_VERSION, sizeof(ed->version));
1131 ed->regdump_len = sizeof(u32) * AXIENET_REGS_N;
1135 * axienet_ethtools_get_regs_len - Get the total regs length present in the
1137 * @ndev: Pointer to net_device structure
1139 * This implements ethtool command for getting the total register length
1142 static int axienet_ethtools_get_regs_len(struct net_device *ndev)
1144 return sizeof(u32) * AXIENET_REGS_N;
1148 * axienet_ethtools_get_regs - Dump the contents of all registers present
1149 * in AxiEthernet core.
1150 * @ndev: Pointer to net_device structure
1151 * @regs: Pointer to ethtool_regs structure
1152 * @ret: Void pointer used to return the contents of the registers.
1154 * This implements ethtool command for getting the Axi Ethernet register dump.
1155 * Issue "ethtool -d ethX" to execute this function.
1157 static void axienet_ethtools_get_regs(struct net_device *ndev,
1158 struct ethtool_regs *regs, void *ret)
1160 u32 *data = (u32 *) ret;
1161 size_t len = sizeof(u32) * AXIENET_REGS_N;
1162 struct axienet_local *lp = netdev_priv(ndev);
1167 memset(data, 0, len);
1168 data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
1169 data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
1170 data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
1171 data[3] = axienet_ior(lp, XAE_IS_OFFSET);
1172 data[4] = axienet_ior(lp, XAE_IP_OFFSET);
1173 data[5] = axienet_ior(lp, XAE_IE_OFFSET);
1174 data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
1175 data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
1176 data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
1177 data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
1178 data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
1179 data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
1180 data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
1181 data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
1182 data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
1183 data[15] = axienet_ior(lp, XAE_TC_OFFSET);
1184 data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
1185 data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
1186 data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
1187 data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1188 data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
1189 data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
1190 data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
1191 data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET);
1192 data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET);
1193 data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET);
1194 data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET);
1195 data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
1196 data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
1197 data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
1198 data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
1199 data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
1203 * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1205 * @ndev: Pointer to net_device structure
1206 * @epauseparm: Pointer to ethtool_pauseparam structure.
1208 * This implements ethtool command for getting axi ethernet pause frame
1209 * setting. Issue "ethtool -a ethX" to execute this function.
1212 axienet_ethtools_get_pauseparam(struct net_device *ndev,
1213 struct ethtool_pauseparam *epauseparm)
1216 struct axienet_local *lp = netdev_priv(ndev);
1217 epauseparm->autoneg = 0;
1218 regval = axienet_ior(lp, XAE_FCC_OFFSET);
1219 epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK;
1220 epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK;
1224 * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1226 * @ndev: Pointer to net_device structure
1227 * @epauseparam:Pointer to ethtool_pauseparam structure
1229 * This implements ethtool command for enabling flow control on Rx and Tx
1230 * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1234 axienet_ethtools_set_pauseparam(struct net_device *ndev,
1235 struct ethtool_pauseparam *epauseparm)
1238 struct axienet_local *lp = netdev_priv(ndev);
1240 if (netif_running(ndev)) {
1242 "Please stop netif before applying configuration\n");
1246 regval = axienet_ior(lp, XAE_FCC_OFFSET);
1247 if (epauseparm->tx_pause)
1248 regval |= XAE_FCC_FCTX_MASK;
1250 regval &= ~XAE_FCC_FCTX_MASK;
1251 if (epauseparm->rx_pause)
1252 regval |= XAE_FCC_FCRX_MASK;
1254 regval &= ~XAE_FCC_FCRX_MASK;
1255 axienet_iow(lp, XAE_FCC_OFFSET, regval);
1261 * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1262 * @ndev: Pointer to net_device structure
1263 * @ecoalesce: Pointer to ethtool_coalesce structure
1265 * This implements ethtool command for getting the DMA interrupt coalescing
1266 * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1267 * execute this function.
1269 static int axienet_ethtools_get_coalesce(struct net_device *ndev,
1270 struct ethtool_coalesce *ecoalesce)
1273 struct axienet_local *lp = netdev_priv(ndev);
1274 regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1275 ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1276 >> XAXIDMA_COALESCE_SHIFT;
1277 regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1278 ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1279 >> XAXIDMA_COALESCE_SHIFT;
1284 * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1285 * @ndev: Pointer to net_device structure
1286 * @ecoalesce: Pointer to ethtool_coalesce structure
1288 * This implements ethtool command for setting the DMA interrupt coalescing
1289 * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1290 * prompt to execute this function.
1292 static int axienet_ethtools_set_coalesce(struct net_device *ndev,
1293 struct ethtool_coalesce *ecoalesce)
1295 struct axienet_local *lp = netdev_priv(ndev);
1297 if (netif_running(ndev)) {
1299 "Please stop netif before applying configuration\n");
1303 if ((ecoalesce->rx_coalesce_usecs) ||
1304 (ecoalesce->rx_coalesce_usecs_irq) ||
1305 (ecoalesce->rx_max_coalesced_frames_irq) ||
1306 (ecoalesce->tx_coalesce_usecs) ||
1307 (ecoalesce->tx_coalesce_usecs_irq) ||
1308 (ecoalesce->tx_max_coalesced_frames_irq) ||
1309 (ecoalesce->stats_block_coalesce_usecs) ||
1310 (ecoalesce->use_adaptive_rx_coalesce) ||
1311 (ecoalesce->use_adaptive_tx_coalesce) ||
1312 (ecoalesce->pkt_rate_low) ||
1313 (ecoalesce->rx_coalesce_usecs_low) ||
1314 (ecoalesce->rx_max_coalesced_frames_low) ||
1315 (ecoalesce->tx_coalesce_usecs_low) ||
1316 (ecoalesce->tx_max_coalesced_frames_low) ||
1317 (ecoalesce->pkt_rate_high) ||
1318 (ecoalesce->rx_coalesce_usecs_high) ||
1319 (ecoalesce->rx_max_coalesced_frames_high) ||
1320 (ecoalesce->tx_coalesce_usecs_high) ||
1321 (ecoalesce->tx_max_coalesced_frames_high) ||
1322 (ecoalesce->rate_sample_interval))
1324 if (ecoalesce->rx_max_coalesced_frames)
1325 lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1326 if (ecoalesce->tx_max_coalesced_frames)
1327 lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1332 static struct ethtool_ops axienet_ethtool_ops = {
1333 .get_settings = axienet_ethtools_get_settings,
1334 .set_settings = axienet_ethtools_set_settings,
1335 .get_drvinfo = axienet_ethtools_get_drvinfo,
1336 .get_regs_len = axienet_ethtools_get_regs_len,
1337 .get_regs = axienet_ethtools_get_regs,
1338 .get_link = ethtool_op_get_link,
1339 .get_pauseparam = axienet_ethtools_get_pauseparam,
1340 .set_pauseparam = axienet_ethtools_set_pauseparam,
1341 .get_coalesce = axienet_ethtools_get_coalesce,
1342 .set_coalesce = axienet_ethtools_set_coalesce,
1346 * axienet_dma_err_handler - Tasklet handler for Axi DMA Error
1347 * @data: Data passed
1349 * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1352 static void axienet_dma_err_handler(unsigned long data)
1357 struct axienet_local *lp = (struct axienet_local *) data;
1358 struct net_device *ndev = lp->ndev;
1359 struct axidma_bd *cur_p;
1361 axienet_setoptions(ndev, lp->options &
1362 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1363 mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1364 axienet_mdio_wait_until_ready(lp);
1365 /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1366 * When we do an Axi Ethernet reset, it resets the complete core
1367 * including the MDIO. So if MDIO is not disabled when the reset
1368 * process is started, MDIO will be broken afterwards. */
1369 axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
1370 ~XAE_MDIO_MC_MDIOEN_MASK));
1372 __axienet_device_reset(lp, &ndev->dev, XAXIDMA_TX_CR_OFFSET);
1373 __axienet_device_reset(lp, &ndev->dev, XAXIDMA_RX_CR_OFFSET);
1375 axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
1376 axienet_mdio_wait_until_ready(lp);
1378 for (i = 0; i < TX_BD_NUM; i++) {
1379 cur_p = &lp->tx_bd_v[i];
1381 dma_unmap_single(ndev->dev.parent, cur_p->phys,
1383 XAXIDMA_BD_CTRL_LENGTH_MASK),
1386 dev_kfree_skb_irq((struct sk_buff *) cur_p->app4);
1395 cur_p->sw_id_offset = 0;
1398 for (i = 0; i < RX_BD_NUM; i++) {
1399 cur_p = &lp->rx_bd_v[i];
1412 /* Start updating the Rx channel control register */
1413 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1414 /* Update the interrupt coalesce count */
1415 cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
1416 (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1417 /* Update the delay timer count */
1418 cr = ((cr & ~XAXIDMA_DELAY_MASK) |
1419 (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1420 /* Enable coalesce, delay timer and error interrupts */
1421 cr |= XAXIDMA_IRQ_ALL_MASK;
1422 /* Finally write to the Rx channel control register */
1423 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1425 /* Start updating the Tx channel control register */
1426 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1427 /* Update the interrupt coalesce count */
1428 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
1429 (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1430 /* Update the delay timer count */
1431 cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
1432 (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1433 /* Enable coalesce, delay timer and error interrupts */
1434 cr |= XAXIDMA_IRQ_ALL_MASK;
1435 /* Finally write to the Tx channel control register */
1436 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1438 /* Populate the tail pointer and bring the Rx Axi DMA engine out of
1439 * halted state. This will make the Rx side ready for reception.*/
1440 axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
1441 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1442 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1443 cr | XAXIDMA_CR_RUNSTOP_MASK);
1444 axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
1445 (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
1447 /* Write to the RS (Run-stop) bit in the Tx channel control register.
1448 * Tx channel is now ready to run. But only after we write to the
1449 * tail pointer register that the Tx channel will start transmitting */
1450 axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
1451 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1452 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1453 cr | XAXIDMA_CR_RUNSTOP_MASK);
1455 axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
1456 axienet_status &= ~XAE_RCW1_RX_MASK;
1457 axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
1459 axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
1460 if (axienet_status & XAE_INT_RXRJECT_MASK)
1461 axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
1462 axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
1464 /* Sync default options with HW but leave receiver and
1465 * transmitter disabled.*/
1466 axienet_setoptions(ndev, lp->options &
1467 ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1468 axienet_set_mac_address(ndev, NULL);
1469 axienet_set_multicast_list(ndev);
1470 axienet_setoptions(ndev, lp->options);
1474 * axienet_of_probe - Axi Ethernet probe function.
1475 * @op: Pointer to platform device structure.
1476 * @match: Pointer to device id structure
1478 * returns: 0, on success
1479 * Non-zero error value on failure.
1481 * This is the probe routine for Axi Ethernet driver. This is called before
1482 * any other driver routines are invoked. It allocates and sets up the Ethernet
1483 * device. Parses through device tree and populates fields of
1484 * axienet_local. It registers the Ethernet device.
1486 static int axienet_of_probe(struct platform_device *op)
1490 struct device_node *np;
1491 struct axienet_local *lp;
1492 struct net_device *ndev;
1495 ndev = alloc_etherdev(sizeof(*lp));
1499 platform_set_drvdata(op, ndev);
1501 SET_NETDEV_DEV(ndev, &op->dev);
1502 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1503 ndev->features = NETIF_F_SG;
1504 ndev->netdev_ops = &axienet_netdev_ops;
1505 ndev->ethtool_ops = &axienet_ethtool_ops;
1507 lp = netdev_priv(ndev);
1510 lp->options = XAE_OPTION_DEFAULTS;
1511 /* Map device registers */
1512 lp->regs = of_iomap(op->dev.of_node, 0);
1514 dev_err(&op->dev, "could not map Axi Ethernet regs.\n");
1518 /* Setup checksum offload, but default to off if not specified */
1521 p = (__be32 *) of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1523 switch (be32_to_cpup(p)) {
1525 lp->csum_offload_on_tx_path =
1526 XAE_FEATURE_PARTIAL_TX_CSUM;
1527 lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
1528 /* Can checksum TCP/UDP over IPv4. */
1529 ndev->features |= NETIF_F_IP_CSUM;
1532 lp->csum_offload_on_tx_path =
1533 XAE_FEATURE_FULL_TX_CSUM;
1534 lp->features |= XAE_FEATURE_FULL_TX_CSUM;
1535 /* Can checksum TCP/UDP over IPv4. */
1536 ndev->features |= NETIF_F_IP_CSUM;
1539 lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
1542 p = (__be32 *) of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1544 switch (be32_to_cpup(p)) {
1546 lp->csum_offload_on_rx_path =
1547 XAE_FEATURE_PARTIAL_RX_CSUM;
1548 lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
1551 lp->csum_offload_on_rx_path =
1552 XAE_FEATURE_FULL_RX_CSUM;
1553 lp->features |= XAE_FEATURE_FULL_RX_CSUM;
1556 lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
1559 /* For supporting jumbo frames, the Axi Ethernet hardware must have
1560 * a larger Rx/Tx Memory. Typically, the size must be large so that
1561 * we can enable jumbo option and start supporting jumbo frames.
1562 * Here we check for memory allocated for Rx/Tx in the hardware from
1563 * the device-tree and accordingly set flags.
1565 p = (__be32 *) of_get_property(op->dev.of_node, "xlnx,rxmem", NULL);
1567 lp->rxmem = be32_to_cpup(p);
1568 p = (__be32 *) of_get_property(op->dev.of_node, "xlnx,phy-type", NULL);
1570 lp->phy_type = be32_to_cpup(p);
1572 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1573 np = of_parse_phandle(op->dev.of_node, "axistream-connected", 0);
1575 dev_err(&op->dev, "could not find DMA node\n");
1579 lp->dma_regs = of_iomap(np, 0);
1581 dev_dbg(&op->dev, "MEM base: %p\n", lp->dma_regs);
1583 dev_err(&op->dev, "unable to map DMA registers\n");
1586 lp->rx_irq = irq_of_parse_and_map(np, 1);
1587 lp->tx_irq = irq_of_parse_and_map(np, 0);
1589 if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
1590 dev_err(&op->dev, "could not determine irqs\n");
1595 /* Retrieve the MAC address */
1596 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1597 if ((!addr) || (size != 6)) {
1598 dev_err(&op->dev, "could not find MAC address\n");
1602 axienet_set_mac_address(ndev, (void *) addr);
1604 lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1605 lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1607 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1609 ret = axienet_mdio_setup(lp, op->dev.of_node);
1611 dev_warn(&op->dev, "error registering MDIO bus\n");
1613 ret = register_netdev(lp->ndev);
1615 dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
1623 iounmap(lp->dma_regs);
1632 static int axienet_of_remove(struct platform_device *op)
1634 struct net_device *ndev = platform_get_drvdata(op);
1635 struct axienet_local *lp = netdev_priv(ndev);
1637 axienet_mdio_teardown(lp);
1638 unregister_netdev(ndev);
1640 of_node_put(lp->phy_node);
1641 lp->phy_node = NULL;
1645 iounmap(lp->dma_regs);
1651 static struct platform_driver axienet_of_driver = {
1652 .probe = axienet_of_probe,
1653 .remove = axienet_of_remove,
1655 .name = "xilinx_axienet",
1656 .of_match_table = axienet_of_match,
1660 module_platform_driver(axienet_of_driver);
1662 MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
1663 MODULE_AUTHOR("Xilinx");
1664 MODULE_LICENSE("GPL");