drivers/net/igb/igb_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for igb */
  29
  30 #include <linux/vmalloc.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/pci.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39
  40 #include "igb.h"
  41
  42 struct igb_stats {
  43         char stat_string[ETH_GSTRING_LEN];
  44         int sizeof_stat;
  45         int stat_offset;
  46 };
  47
  48 #define IGB_STAT(_name, _stat) { \
  49         .stat_string = _name, \
  50         .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
  51         .stat_offset = offsetof(struct igb_adapter, _stat) \
  52 }
  53 static const struct igb_stats igb_gstrings_stats[] = {
  54         IGB_STAT("rx_packets", stats.gprc),
  55         IGB_STAT("tx_packets", stats.gptc),
  56         IGB_STAT("rx_bytes", stats.gorc),
  57         IGB_STAT("tx_bytes", stats.gotc),
  58         IGB_STAT("rx_broadcast", stats.bprc),
  59         IGB_STAT("tx_broadcast", stats.bptc),
  60         IGB_STAT("rx_multicast", stats.mprc),
  61         IGB_STAT("tx_multicast", stats.mptc),
  62         IGB_STAT("multicast", stats.mprc),
  63         IGB_STAT("collisions", stats.colc),
  64         IGB_STAT("rx_crc_errors", stats.crcerrs),
  65         IGB_STAT("rx_no_buffer_count", stats.rnbc),
  66         IGB_STAT("rx_missed_errors", stats.mpc),
  67         IGB_STAT("tx_aborted_errors", stats.ecol),
  68         IGB_STAT("tx_carrier_errors", stats.tncrs),
  69         IGB_STAT("tx_window_errors", stats.latecol),
  70         IGB_STAT("tx_abort_late_coll", stats.latecol),
  71         IGB_STAT("tx_deferred_ok", stats.dc),
  72         IGB_STAT("tx_single_coll_ok", stats.scc),
  73         IGB_STAT("tx_multi_coll_ok", stats.mcc),
  74         IGB_STAT("tx_timeout_count", tx_timeout_count),
  75         IGB_STAT("rx_long_length_errors", stats.roc),
  76         IGB_STAT("rx_short_length_errors", stats.ruc),
  77         IGB_STAT("rx_align_errors", stats.algnerrc),
  78         IGB_STAT("tx_tcp_seg_good", stats.tsctc),
  79         IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
  80         IGB_STAT("rx_flow_control_xon", stats.xonrxc),
  81         IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
  82         IGB_STAT("tx_flow_control_xon", stats.xontxc),
  83         IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
  84         IGB_STAT("rx_long_byte_count", stats.gorc),
  85         IGB_STAT("tx_dma_out_of_sync", stats.doosync),
  86         IGB_STAT("tx_smbus", stats.mgptc),
  87         IGB_STAT("rx_smbus", stats.mgprc),
  88         IGB_STAT("dropped_smbus", stats.mgpdc),
  89         IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
  90         IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
  91         IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
  92         IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
  93 };
  94
  95 #define IGB_NETDEV_STAT(_net_stat) { \
  96         .stat_string = __stringify(_net_stat), \
  97         .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
  98         .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
  99 }
 100 static const struct igb_stats igb_gstrings_net_stats[] = {
 101         IGB_NETDEV_STAT(rx_errors),
 102         IGB_NETDEV_STAT(tx_errors),
 103         IGB_NETDEV_STAT(tx_dropped),
 104         IGB_NETDEV_STAT(rx_length_errors),
 105         IGB_NETDEV_STAT(rx_over_errors),
 106         IGB_NETDEV_STAT(rx_frame_errors),
 107         IGB_NETDEV_STAT(rx_fifo_errors),
 108         IGB_NETDEV_STAT(tx_fifo_errors),
 109         IGB_NETDEV_STAT(tx_heartbeat_errors)
 110 };
 111
 112 #define IGB_GLOBAL_STATS_LEN    \
 113         (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
 114 #define IGB_NETDEV_STATS_LEN    \
 115         (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
 116 #define IGB_RX_QUEUE_STATS_LEN \
 117         (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
 118
 119 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
 120
 121 #define IGB_QUEUE_STATS_LEN \
 122         ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
 123           IGB_RX_QUEUE_STATS_LEN) + \
 124          (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
 125           IGB_TX_QUEUE_STATS_LEN))
 126 #define IGB_STATS_LEN \
 127         (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
 128
 129 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 130         "Register test  (offline)", "Eeprom test    (offline)",
 131         "Interrupt test (offline)", "Loopback test  (offline)",
 132         "Link test   (on/offline)"
 133 };
 134 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
 135
 136 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 137 {
 138         struct igb_adapter *adapter = netdev_priv(netdev);
 139         struct e1000_hw *hw = &adapter->hw;
 140         u32 status;
 141
 142         if (hw->phy.media_type == e1000_media_type_copper) {
 143
 144                 ecmd->supported = (SUPPORTED_10baseT_Half |
 145                                    SUPPORTED_10baseT_Full |
 146                                    SUPPORTED_100baseT_Half |
 147                                    SUPPORTED_100baseT_Full |
 148                                    SUPPORTED_1000baseT_Full|
 149                                    SUPPORTED_Autoneg |
 150                                    SUPPORTED_TP);
 151                 ecmd->advertising = ADVERTISED_TP;
 152
 153                 if (hw->mac.autoneg == 1) {
 154                         ecmd->advertising |= ADVERTISED_Autoneg;
 155                         /* the e1000 autoneg seems to match ethtool nicely */
 156                         ecmd->advertising |= hw->phy.autoneg_advertised;
 157                 }
 158
 159                 ecmd->port = PORT_TP;
 160                 ecmd->phy_address = hw->phy.addr;
 161         } else {
 162                 ecmd->supported   = (SUPPORTED_1000baseT_Full |
 163                                      SUPPORTED_FIBRE |
 164                                      SUPPORTED_Autoneg);
 165
 166                 ecmd->advertising = (ADVERTISED_1000baseT_Full |
 167                                      ADVERTISED_FIBRE |
 168                                      ADVERTISED_Autoneg);
 169
 170                 ecmd->port = PORT_FIBRE;
 171         }
 172
 173         ecmd->transceiver = XCVR_INTERNAL;
 174
 175         status = rd32(E1000_STATUS);
 176
 177         if (status & E1000_STATUS_LU) {
 178
 179                 if ((status & E1000_STATUS_SPEED_1000) ||
 180                     hw->phy.media_type != e1000_media_type_copper)
 181                         ecmd->speed = SPEED_1000;
 182                 else if (status & E1000_STATUS_SPEED_100)
 183                         ecmd->speed = SPEED_100;
 184                 else
 185                         ecmd->speed = SPEED_10;
 186
 187                 if ((status & E1000_STATUS_FD) ||
 188                     hw->phy.media_type != e1000_media_type_copper)
 189                         ecmd->duplex = DUPLEX_FULL;
 190                 else
 191                         ecmd->duplex = DUPLEX_HALF;
 192         } else {
 193                 ecmd->speed = -1;
 194                 ecmd->duplex = -1;
 195         }
 196
 197         ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
 198         return 0;
 199 }
 200
 201 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 202 {
 203         struct igb_adapter *adapter = netdev_priv(netdev);
 204         struct e1000_hw *hw = &adapter->hw;
 205
 206         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 207          * cannot be changed */
 208         if (igb_check_reset_block(hw)) {
 209                 dev_err(&adapter->pdev->dev, "Cannot change link "
 210                         "characteristics when SoL/IDER is active.\n");
 211                 return -EINVAL;
 212         }
 213
 214         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 215                 msleep(1);
 216
 217         if (ecmd->autoneg == AUTONEG_ENABLE) {
 218                 hw->mac.autoneg = 1;
 219                 hw->phy.autoneg_advertised = ecmd->advertising |
 220                                              ADVERTISED_TP |
 221                                              ADVERTISED_Autoneg;
 222                 ecmd->advertising = hw->phy.autoneg_advertised;
 223                 if (adapter->fc_autoneg)
 224                         hw->fc.requested_mode = e1000_fc_default;
 225         } else {
 226                 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
 227                         clear_bit(__IGB_RESETTING, &adapter->state);
 228                         return -EINVAL;
 229                 }
 230         }
 231
 232         /* reset the link */
 233         if (netif_running(adapter->netdev)) {
 234                 igb_down(adapter);
 235                 igb_up(adapter);
 236         } else
 237                 igb_reset(adapter);
 238
 239         clear_bit(__IGB_RESETTING, &adapter->state);
 240         return 0;
 241 }
 242
 243 static u32 igb_get_link(struct net_device *netdev)
 244 {
 245         struct igb_adapter *adapter = netdev_priv(netdev);
 246         struct e1000_mac_info *mac = &adapter->hw.mac;
 247
 248         /*
 249          * If the link is not reported up to netdev, interrupts are disabled,
 250          * and so the physical link state may have changed since we last
 251          * looked. Set get_link_status to make sure that the true link
 252          * state is interrogated, rather than pulling a cached and possibly
 253          * stale link state from the driver.
 254          */
 255         if (!netif_carrier_ok(netdev))
 256                 mac->get_link_status = 1;
 257
 258         return igb_has_link(adapter);
 259 }
 260
 261 static void igb_get_pauseparam(struct net_device *netdev,
 262                                struct ethtool_pauseparam *pause)
 263 {
 264         struct igb_adapter *adapter = netdev_priv(netdev);
 265         struct e1000_hw *hw = &adapter->hw;
 266
 267         pause->autoneg =
 268                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 269
 270         if (hw->fc.current_mode == e1000_fc_rx_pause)
 271                 pause->rx_pause = 1;
 272         else if (hw->fc.current_mode == e1000_fc_tx_pause)
 273                 pause->tx_pause = 1;
 274         else if (hw->fc.current_mode == e1000_fc_full) {
 275                 pause->rx_pause = 1;
 276                 pause->tx_pause = 1;
 277         }
 278 }
 279
 280 static int igb_set_pauseparam(struct net_device *netdev,
 281                               struct ethtool_pauseparam *pause)
 282 {
 283         struct igb_adapter *adapter = netdev_priv(netdev);
 284         struct e1000_hw *hw = &adapter->hw;
 285         int retval = 0;
 286
 287         adapter->fc_autoneg = pause->autoneg;
 288
 289         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 290                 msleep(1);
 291
 292         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 293                 hw->fc.requested_mode = e1000_fc_default;
 294                 if (netif_running(adapter->netdev)) {
 295                         igb_down(adapter);
 296                         igb_up(adapter);
 297                 } else {
 298                         igb_reset(adapter);
 299                 }
 300         } else {
 301                 if (pause->rx_pause && pause->tx_pause)
 302                         hw->fc.requested_mode = e1000_fc_full;
 303                 else if (pause->rx_pause && !pause->tx_pause)
 304                         hw->fc.requested_mode = e1000_fc_rx_pause;
 305                 else if (!pause->rx_pause && pause->tx_pause)
 306                         hw->fc.requested_mode = e1000_fc_tx_pause;
 307                 else if (!pause->rx_pause && !pause->tx_pause)
 308                         hw->fc.requested_mode = e1000_fc_none;
 309
 310                 hw->fc.current_mode = hw->fc.requested_mode;
 311
 312                 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
 313                           igb_force_mac_fc(hw) : igb_setup_link(hw));
 314         }
 315
 316         clear_bit(__IGB_RESETTING, &adapter->state);
 317         return retval;
 318 }
 319
 320 static u32 igb_get_rx_csum(struct net_device *netdev)
 321 {
 322         struct igb_adapter *adapter = netdev_priv(netdev);
 323         return !!(adapter->rx_ring[0]->flags & IGB_RING_FLAG_RX_CSUM);
 324 }
 325
 326 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
 327 {
 328         struct igb_adapter *adapter = netdev_priv(netdev);
 329         int i;
 330
 331         for (i = 0; i < adapter->num_rx_queues; i++) {
 332                 if (data)
 333                         adapter->rx_ring[i]->flags |= IGB_RING_FLAG_RX_CSUM;
 334                 else
 335                         adapter->rx_ring[i]->flags &= ~IGB_RING_FLAG_RX_CSUM;
 336         }
 337
 338         return 0;
 339 }
 340
 341 static u32 igb_get_tx_csum(struct net_device *netdev)
 342 {
 343         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 344 }
 345
 346 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
 347 {
 348         struct igb_adapter *adapter = netdev_priv(netdev);
 349
 350         if (data) {
 351                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 352                 if (adapter->hw.mac.type >= e1000_82576)
 353                         netdev->features |= NETIF_F_SCTP_CSUM;
 354         } else {
 355                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 356                                       NETIF_F_SCTP_CSUM);
 357         }
 358
 359         return 0;
 360 }
 361
 362 static int igb_set_tso(struct net_device *netdev, u32 data)
 363 {
 364         struct igb_adapter *adapter = netdev_priv(netdev);
 365
 366         if (data) {
 367                 netdev->features |= NETIF_F_TSO;
 368                 netdev->features |= NETIF_F_TSO6;
 369         } else {
 370                 netdev->features &= ~NETIF_F_TSO;
 371                 netdev->features &= ~NETIF_F_TSO6;
 372         }
 373
 374         dev_info(&adapter->pdev->dev, "TSO is %s\n",
 375                  data ? "Enabled" : "Disabled");
 376         return 0;
 377 }
 378
 379 static u32 igb_get_msglevel(struct net_device *netdev)
 380 {
 381         struct igb_adapter *adapter = netdev_priv(netdev);
 382         return adapter->msg_enable;
 383 }
 384
 385 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 386 {
 387         struct igb_adapter *adapter = netdev_priv(netdev);
 388         adapter->msg_enable = data;
 389 }
 390
 391 static int igb_get_regs_len(struct net_device *netdev)
 392 {
 393 #define IGB_REGS_LEN 551
 394         return IGB_REGS_LEN * sizeof(u32);
 395 }
 396
 397 static void igb_get_regs(struct net_device *netdev,
 398                          struct ethtool_regs *regs, void *p)
 399 {
 400         struct igb_adapter *adapter = netdev_priv(netdev);
 401         struct e1000_hw *hw = &adapter->hw;
 402         u32 *regs_buff = p;
 403         u8 i;
 404
 405         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 406
 407         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 408
 409         /* General Registers */
 410         regs_buff[0] = rd32(E1000_CTRL);
 411         regs_buff[1] = rd32(E1000_STATUS);
 412         regs_buff[2] = rd32(E1000_CTRL_EXT);
 413         regs_buff[3] = rd32(E1000_MDIC);
 414         regs_buff[4] = rd32(E1000_SCTL);
 415         regs_buff[5] = rd32(E1000_CONNSW);
 416         regs_buff[6] = rd32(E1000_VET);
 417         regs_buff[7] = rd32(E1000_LEDCTL);
 418         regs_buff[8] = rd32(E1000_PBA);
 419         regs_buff[9] = rd32(E1000_PBS);
 420         regs_buff[10] = rd32(E1000_FRTIMER);
 421         regs_buff[11] = rd32(E1000_TCPTIMER);
 422
 423         /* NVM Register */
 424         regs_buff[12] = rd32(E1000_EECD);
 425
 426         /* Interrupt */
 427         /* Reading EICS for EICR because they read the
 428          * same but EICS does not clear on read */
 429         regs_buff[13] = rd32(E1000_EICS);
 430         regs_buff[14] = rd32(E1000_EICS);
 431         regs_buff[15] = rd32(E1000_EIMS);
 432         regs_buff[16] = rd32(E1000_EIMC);
 433         regs_buff[17] = rd32(E1000_EIAC);
 434         regs_buff[18] = rd32(E1000_EIAM);
 435         /* Reading ICS for ICR because they read the
 436          * same but ICS does not clear on read */
 437         regs_buff[19] = rd32(E1000_ICS);
 438         regs_buff[20] = rd32(E1000_ICS);
 439         regs_buff[21] = rd32(E1000_IMS);
 440         regs_buff[22] = rd32(E1000_IMC);
 441         regs_buff[23] = rd32(E1000_IAC);
 442         regs_buff[24] = rd32(E1000_IAM);
 443         regs_buff[25] = rd32(E1000_IMIRVP);
 444
 445         /* Flow Control */
 446         regs_buff[26] = rd32(E1000_FCAL);
 447         regs_buff[27] = rd32(E1000_FCAH);
 448         regs_buff[28] = rd32(E1000_FCTTV);
 449         regs_buff[29] = rd32(E1000_FCRTL);
 450         regs_buff[30] = rd32(E1000_FCRTH);
 451         regs_buff[31] = rd32(E1000_FCRTV);
 452
 453         /* Receive */
 454         regs_buff[32] = rd32(E1000_RCTL);
 455         regs_buff[33] = rd32(E1000_RXCSUM);
 456         regs_buff[34] = rd32(E1000_RLPML);
 457         regs_buff[35] = rd32(E1000_RFCTL);
 458         regs_buff[36] = rd32(E1000_MRQC);
 459         regs_buff[37] = rd32(E1000_VT_CTL);
 460
 461         /* Transmit */
 462         regs_buff[38] = rd32(E1000_TCTL);
 463         regs_buff[39] = rd32(E1000_TCTL_EXT);
 464         regs_buff[40] = rd32(E1000_TIPG);
 465         regs_buff[41] = rd32(E1000_DTXCTL);
 466
 467         /* Wake Up */
 468         regs_buff[42] = rd32(E1000_WUC);
 469         regs_buff[43] = rd32(E1000_WUFC);
 470         regs_buff[44] = rd32(E1000_WUS);
 471         regs_buff[45] = rd32(E1000_IPAV);
 472         regs_buff[46] = rd32(E1000_WUPL);
 473
 474         /* MAC */
 475         regs_buff[47] = rd32(E1000_PCS_CFG0);
 476         regs_buff[48] = rd32(E1000_PCS_LCTL);
 477         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 478         regs_buff[50] = rd32(E1000_PCS_ANADV);
 479         regs_buff[51] = rd32(E1000_PCS_LPAB);
 480         regs_buff[52] = rd32(E1000_PCS_NPTX);
 481         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 482
 483         /* Statistics */
 484         regs_buff[54] = adapter->stats.crcerrs;
 485         regs_buff[55] = adapter->stats.algnerrc;
 486         regs_buff[56] = adapter->stats.symerrs;
 487         regs_buff[57] = adapter->stats.rxerrc;
 488         regs_buff[58] = adapter->stats.mpc;
 489         regs_buff[59] = adapter->stats.scc;
 490         regs_buff[60] = adapter->stats.ecol;
 491         regs_buff[61] = adapter->stats.mcc;
 492         regs_buff[62] = adapter->stats.latecol;
 493         regs_buff[63] = adapter->stats.colc;
 494         regs_buff[64] = adapter->stats.dc;
 495         regs_buff[65] = adapter->stats.tncrs;
 496         regs_buff[66] = adapter->stats.sec;
 497         regs_buff[67] = adapter->stats.htdpmc;
 498         regs_buff[68] = adapter->stats.rlec;
 499         regs_buff[69] = adapter->stats.xonrxc;
 500         regs_buff[70] = adapter->stats.xontxc;
 501         regs_buff[71] = adapter->stats.xoffrxc;
 502         regs_buff[72] = adapter->stats.xofftxc;
 503         regs_buff[73] = adapter->stats.fcruc;
 504         regs_buff[74] = adapter->stats.prc64;
 505         regs_buff[75] = adapter->stats.prc127;
 506         regs_buff[76] = adapter->stats.prc255;
 507         regs_buff[77] = adapter->stats.prc511;
 508         regs_buff[78] = adapter->stats.prc1023;
 509         regs_buff[79] = adapter->stats.prc1522;
 510         regs_buff[80] = adapter->stats.gprc;
 511         regs_buff[81] = adapter->stats.bprc;
 512         regs_buff[82] = adapter->stats.mprc;
 513         regs_buff[83] = adapter->stats.gptc;
 514         regs_buff[84] = adapter->stats.gorc;
 515         regs_buff[86] = adapter->stats.gotc;
 516         regs_buff[88] = adapter->stats.rnbc;
 517         regs_buff[89] = adapter->stats.ruc;
 518         regs_buff[90] = adapter->stats.rfc;
 519         regs_buff[91] = adapter->stats.roc;
 520         regs_buff[92] = adapter->stats.rjc;
 521         regs_buff[93] = adapter->stats.mgprc;
 522         regs_buff[94] = adapter->stats.mgpdc;
 523         regs_buff[95] = adapter->stats.mgptc;
 524         regs_buff[96] = adapter->stats.tor;
 525         regs_buff[98] = adapter->stats.tot;
 526         regs_buff[100] = adapter->stats.tpr;
 527         regs_buff[101] = adapter->stats.tpt;
 528         regs_buff[102] = adapter->stats.ptc64;
 529         regs_buff[103] = adapter->stats.ptc127;
 530         regs_buff[104] = adapter->stats.ptc255;
 531         regs_buff[105] = adapter->stats.ptc511;
 532         regs_buff[106] = adapter->stats.ptc1023;
 533         regs_buff[107] = adapter->stats.ptc1522;
 534         regs_buff[108] = adapter->stats.mptc;
 535         regs_buff[109] = adapter->stats.bptc;
 536         regs_buff[110] = adapter->stats.tsctc;
 537         regs_buff[111] = adapter->stats.iac;
 538         regs_buff[112] = adapter->stats.rpthc;
 539         regs_buff[113] = adapter->stats.hgptc;
 540         regs_buff[114] = adapter->stats.hgorc;
 541         regs_buff[116] = adapter->stats.hgotc;
 542         regs_buff[118] = adapter->stats.lenerrs;
 543         regs_buff[119] = adapter->stats.scvpc;
 544         regs_buff[120] = adapter->stats.hrmpc;
 545
 546         for (i = 0; i < 4; i++)
 547                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 548         for (i = 0; i < 4; i++)
 549                 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
 550         for (i = 0; i < 4; i++)
 551                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 552         for (i = 0; i < 4; i++)
 553                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 554         for (i = 0; i < 4; i++)
 555                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 556         for (i = 0; i < 4; i++)
 557                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 558         for (i = 0; i < 4; i++)
 559                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 560         for (i = 0; i < 4; i++)
 561                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 562
 563         for (i = 0; i < 10; i++)
 564                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 565         for (i = 0; i < 8; i++)
 566                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 567         for (i = 0; i < 8; i++)
 568                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 569         for (i = 0; i < 16; i++)
 570                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 571         for (i = 0; i < 16; i++)
 572                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 573
 574         for (i = 0; i < 4; i++)
 575                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 576         for (i = 0; i < 4; i++)
 577                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 578         for (i = 0; i < 4; i++)
 579                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 580         for (i = 0; i < 4; i++)
 581                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 582         for (i = 0; i < 4; i++)
 583                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 584         for (i = 0; i < 4; i++)
 585                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 586         for (i = 0; i < 4; i++)
 587                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 588         for (i = 0; i < 4; i++)
 589                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 590         for (i = 0; i < 4; i++)
 591                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 592
 593         for (i = 0; i < 4; i++)
 594                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 595         for (i = 0; i < 4; i++)
 596                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 597         for (i = 0; i < 32; i++)
 598                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 599         for (i = 0; i < 128; i++)
 600                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 601         for (i = 0; i < 128; i++)
 602                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 603         for (i = 0; i < 4; i++)
 604                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 605
 606         regs_buff[547] = rd32(E1000_TDFH);
 607         regs_buff[548] = rd32(E1000_TDFT);
 608         regs_buff[549] = rd32(E1000_TDFHS);
 609         regs_buff[550] = rd32(E1000_TDFPC);
 610         regs_buff[551] = adapter->stats.o2bgptc;
 611         regs_buff[552] = adapter->stats.b2ospc;
 612         regs_buff[553] = adapter->stats.o2bspc;
 613         regs_buff[554] = adapter->stats.b2ogprc;
 614 }
 615
 616 static int igb_get_eeprom_len(struct net_device *netdev)
 617 {
 618         struct igb_adapter *adapter = netdev_priv(netdev);
 619         return adapter->hw.nvm.word_size * 2;
 620 }
 621
 622 static int igb_get_eeprom(struct net_device *netdev,
 623                           struct ethtool_eeprom *eeprom, u8 *bytes)
 624 {
 625         struct igb_adapter *adapter = netdev_priv(netdev);
 626         struct e1000_hw *hw = &adapter->hw;
 627         u16 *eeprom_buff;
 628         int first_word, last_word;
 629         int ret_val = 0;
 630         u16 i;
 631
 632         if (eeprom->len == 0)
 633                 return -EINVAL;
 634
 635         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 636
 637         first_word = eeprom->offset >> 1;
 638         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 639
 640         eeprom_buff = kmalloc(sizeof(u16) *
 641                         (last_word - first_word + 1), GFP_KERNEL);
 642         if (!eeprom_buff)
 643                 return -ENOMEM;
 644
 645         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 646                 ret_val = hw->nvm.ops.read(hw, first_word,
 647                                             last_word - first_word + 1,
 648                                             eeprom_buff);
 649         else {
 650                 for (i = 0; i < last_word - first_word + 1; i++) {
 651                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
 652                                                     &eeprom_buff[i]);
 653                         if (ret_val)
 654                                 break;
 655                 }
 656         }
 657
 658         /* Device's eeprom is always little-endian, word addressable */
 659         for (i = 0; i < last_word - first_word + 1; i++)
 660                 le16_to_cpus(&eeprom_buff[i]);
 661
 662         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 663                         eeprom->len);
 664         kfree(eeprom_buff);
 665
 666         return ret_val;
 667 }
 668
 669 static int igb_set_eeprom(struct net_device *netdev,
 670                           struct ethtool_eeprom *eeprom, u8 *bytes)
 671 {
 672         struct igb_adapter *adapter = netdev_priv(netdev);
 673         struct e1000_hw *hw = &adapter->hw;
 674         u16 *eeprom_buff;
 675         void *ptr;
 676         int max_len, first_word, last_word, ret_val = 0;
 677         u16 i;
 678
 679         if (eeprom->len == 0)
 680                 return -EOPNOTSUPP;
 681
 682         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 683                 return -EFAULT;
 684
 685         max_len = hw->nvm.word_size * 2;
 686
 687         first_word = eeprom->offset >> 1;
 688         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 689         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 690         if (!eeprom_buff)
 691                 return -ENOMEM;
 692
 693         ptr = (void *)eeprom_buff;
 694
 695         if (eeprom->offset & 1) {
 696                 /* need read/modify/write of first changed EEPROM word */
 697                 /* only the second byte of the word is being modified */
 698                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
 699                                             &eeprom_buff[0]);
 700                 ptr++;
 701         }
 702         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 703                 /* need read/modify/write of last changed EEPROM word */
 704                 /* only the first byte of the word is being modified */
 705                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
 706                                    &eeprom_buff[last_word - first_word]);
 707         }
 708
 709         /* Device's eeprom is always little-endian, word addressable */
 710         for (i = 0; i < last_word - first_word + 1; i++)
 711                 le16_to_cpus(&eeprom_buff[i]);
 712
 713         memcpy(ptr, bytes, eeprom->len);
 714
 715         for (i = 0; i < last_word - first_word + 1; i++)
 716                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 717
 718         ret_val = hw->nvm.ops.write(hw, first_word,
 719                                      last_word - first_word + 1, eeprom_buff);
 720
 721         /* Update the checksum over the first part of the EEPROM if needed
 722          * and flush shadow RAM for 82573 controllers */
 723         if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
 724                 hw->nvm.ops.update(hw);
 725
 726         kfree(eeprom_buff);
 727         return ret_val;
 728 }
 729
 730 static void igb_get_drvinfo(struct net_device *netdev,
 731                             struct ethtool_drvinfo *drvinfo)
 732 {
 733         struct igb_adapter *adapter = netdev_priv(netdev);
 734         char firmware_version[32];
 735         u16 eeprom_data;
 736
 737         strncpy(drvinfo->driver,  igb_driver_name, sizeof(drvinfo->driver) - 1);
 738         strncpy(drvinfo->version, igb_driver_version,
 739                 sizeof(drvinfo->version) - 1);
 740
 741         /* EEPROM image version # is reported as firmware version # for
 742          * 82575 controllers */
 743         adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
 744         sprintf(firmware_version, "%d.%d-%d",
 745                 (eeprom_data & 0xF000) >> 12,
 746                 (eeprom_data & 0x0FF0) >> 4,
 747                 eeprom_data & 0x000F);
 748
 749         strncpy(drvinfo->fw_version, firmware_version,
 750                 sizeof(drvinfo->fw_version) - 1);
 751         strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
 752                 sizeof(drvinfo->bus_info) - 1);
 753         drvinfo->n_stats = IGB_STATS_LEN;
 754         drvinfo->testinfo_len = IGB_TEST_LEN;
 755         drvinfo->regdump_len = igb_get_regs_len(netdev);
 756         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
 757 }
 758
 759 static void igb_get_ringparam(struct net_device *netdev,
 760                               struct ethtool_ringparam *ring)
 761 {
 762         struct igb_adapter *adapter = netdev_priv(netdev);
 763
 764         ring->rx_max_pending = IGB_MAX_RXD;
 765         ring->tx_max_pending = IGB_MAX_TXD;
 766         ring->rx_mini_max_pending = 0;
 767         ring->rx_jumbo_max_pending = 0;
 768         ring->rx_pending = adapter->rx_ring_count;
 769         ring->tx_pending = adapter->tx_ring_count;
 770         ring->rx_mini_pending = 0;
 771         ring->rx_jumbo_pending = 0;
 772 }
 773
 774 static int igb_set_ringparam(struct net_device *netdev,
 775                              struct ethtool_ringparam *ring)
 776 {
 777         struct igb_adapter *adapter = netdev_priv(netdev);
 778         struct igb_ring *temp_ring;
 779         int i, err = 0;
 780         u16 new_rx_count, new_tx_count;
 781
 782         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 783                 return -EINVAL;
 784
 785         new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
 786         new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
 787         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 788
 789         new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
 790         new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
 791         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 792
 793         if ((new_tx_count == adapter->tx_ring_count) &&
 794             (new_rx_count == adapter->rx_ring_count)) {
 795                 /* nothing to do */
 796                 return 0;
 797         }
 798
 799         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 800                 msleep(1);
 801
 802         if (!netif_running(adapter->netdev)) {
 803                 for (i = 0; i < adapter->num_tx_queues; i++)
 804                         adapter->tx_ring[i]->count = new_tx_count;
 805                 for (i = 0; i < adapter->num_rx_queues; i++)
 806                         adapter->rx_ring[i]->count = new_rx_count;
 807                 adapter->tx_ring_count = new_tx_count;
 808                 adapter->rx_ring_count = new_rx_count;
 809                 goto clear_reset;
 810         }
 811
 812         if (adapter->num_tx_queues > adapter->num_rx_queues)
 813                 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
 814         else
 815                 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
 816
 817         if (!temp_ring) {
 818                 err = -ENOMEM;
 819                 goto clear_reset;
 820         }
 821
 822         igb_down(adapter);
 823
 824         /*
 825          * We can't just free everything and then setup again,
 826          * because the ISRs in MSI-X mode get passed pointers
 827          * to the tx and rx ring structs.
 828          */
 829         if (new_tx_count != adapter->tx_ring_count) {
 830                 for (i = 0; i < adapter->num_tx_queues; i++) {
 831                         memcpy(&temp_ring[i], adapter->tx_ring[i],
 832                                sizeof(struct igb_ring));
 833
 834                         temp_ring[i].count = new_tx_count;
 835                         err = igb_setup_tx_resources(&temp_ring[i]);
 836                         if (err) {
 837                                 while (i) {
 838                                         i--;
 839                                         igb_free_tx_resources(&temp_ring[i]);
 840                                 }
 841                                 goto err_setup;
 842                         }
 843                 }
 844
 845                 for (i = 0; i < adapter->num_tx_queues; i++) {
 846                         igb_free_tx_resources(adapter->tx_ring[i]);
 847
 848                         memcpy(adapter->tx_ring[i], &temp_ring[i],
 849                                sizeof(struct igb_ring));
 850                 }
 851
 852                 adapter->tx_ring_count = new_tx_count;
 853         }
 854
 855         if (new_rx_count != adapter->rx_ring_count) {
 856                 for (i = 0; i < adapter->num_rx_queues; i++) {
 857                         memcpy(&temp_ring[i], adapter->rx_ring[i],
 858                                sizeof(struct igb_ring));
 859
 860                         temp_ring[i].count = new_rx_count;
 861                         err = igb_setup_rx_resources(&temp_ring[i]);
 862                         if (err) {
 863                                 while (i) {
 864                                         i--;
 865                                         igb_free_rx_resources(&temp_ring[i]);
 866                                 }
 867                                 goto err_setup;
 868                         }
 869
 870                 }
 871
 872                 for (i = 0; i < adapter->num_rx_queues; i++) {
 873                         igb_free_rx_resources(adapter->rx_ring[i]);
 874
 875                         memcpy(adapter->rx_ring[i], &temp_ring[i],
 876                                sizeof(struct igb_ring));
 877                 }
 878
 879                 adapter->rx_ring_count = new_rx_count;
 880         }
 881 err_setup:
 882         igb_up(adapter);
 883         vfree(temp_ring);
 884 clear_reset:
 885         clear_bit(__IGB_RESETTING, &adapter->state);
 886         return err;
 887 }
 888
 889 /* ethtool register test data */
 890 struct igb_reg_test {
 891         u16 reg;
 892         u16 reg_offset;
 893         u16 array_len;
 894         u16 test_type;
 895         u32 mask;
 896         u32 write;
 897 };
 898
 899 /* In the hardware, registers are laid out either singly, in arrays
 900  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
 901  * most tests take place on arrays or single registers (handled
 902  * as a single-element array) and special-case the tables.
 903  * Table tests are always pattern tests.
 904  *
 905  * We also make provision for some required setup steps by specifying
 906  * registers to be written without any read-back testing.
 907  */
 908
 909 #define PATTERN_TEST    1
 910 #define SET_READ_TEST   2
 911 #define WRITE_NO_TEST   3
 912 #define TABLE32_TEST    4
 913 #define TABLE64_TEST_LO 5
 914 #define TABLE64_TEST_HI 6
 915
 916 /* i350 reg test */
 917 static struct igb_reg_test reg_test_i350[] = {
 918         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 919         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 920         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 921         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
 922         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 923         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 924         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 925         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 926         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 927         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 928         /* RDH is read-only for i350, only test RDT. */
 929         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 930         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 931         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 932         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 933         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 934         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 935         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 936         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 937         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 938         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 939         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 940         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 941         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 942         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 943         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 944         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 945         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 946         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 947                                                 0xFFFFFFFF, 0xFFFFFFFF },
 948         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 949                                                 0xC3FFFFFF, 0xFFFFFFFF },
 950         { E1000_RA2,       0, 16, TABLE64_TEST_LO,
 951                                                 0xFFFFFFFF, 0xFFFFFFFF },
 952         { E1000_RA2,       0, 16, TABLE64_TEST_HI,
 953                                                 0xC3FFFFFF, 0xFFFFFFFF },
 954         { E1000_MTA,       0, 128, TABLE32_TEST,
 955                                                 0xFFFFFFFF, 0xFFFFFFFF },
 956         { 0, 0, 0, 0 }
 957 };
 958
 959 /* 82580 reg test */
 960 static struct igb_reg_test reg_test_82580[] = {
 961         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 962         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 963         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 964         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 965         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 966         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 967         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 968         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 969         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 970         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 971         /* RDH is read-only for 82580, only test RDT. */
 972         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 973         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 974         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 975         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 976         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 977         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 978         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 979         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 980         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 981         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 982         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 983         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 984         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 985         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 986         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 987         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 988         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 989         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 990                                                 0xFFFFFFFF, 0xFFFFFFFF },
 991         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 992                                                 0x83FFFFFF, 0xFFFFFFFF },
 993         { E1000_RA2,       0, 8, TABLE64_TEST_LO,
 994                                                 0xFFFFFFFF, 0xFFFFFFFF },
 995         { E1000_RA2,       0, 8, TABLE64_TEST_HI,
 996                                                 0x83FFFFFF, 0xFFFFFFFF },
 997         { E1000_MTA,       0, 128, TABLE32_TEST,
 998                                                 0xFFFFFFFF, 0xFFFFFFFF },
 999         { 0, 0, 0, 0 }
1000 };
1001
1002 /* 82576 reg test */
1003 static struct igb_reg_test reg_test_82576[] = {
1004         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1005         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1006         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1007         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1008         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1009         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1010         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1011         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1012         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1013         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1014         /* Enable all RX queues before testing. */
1015         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1016         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1017         /* RDH is read-only for 82576, only test RDT. */
1018         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1019         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1020         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
1021         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
1022         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1023         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1024         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1025         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1026         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1027         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1028         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1029         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1030         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1031         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1032         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1033         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1034         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1035         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1036         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1037         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1038         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1039         { E1000_MTA,       0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1040         { 0, 0, 0, 0 }
1041 };
1042
1043 /* 82575 register test */
1044 static struct igb_reg_test reg_test_82575[] = {
1045         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1046         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1047         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1048         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1049         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1050         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1051         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1052         /* Enable all four RX queues before testing. */
1053         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1054         /* RDH is read-only for 82575, only test RDT. */
1055         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1056         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1057         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1058         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1059         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1060         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1061         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1062         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1063         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1064         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1065         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1066         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1067         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1068         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1069         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1070         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1071         { 0, 0, 0, 0 }
1072 };
1073
1074 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1075                              int reg, u32 mask, u32 write)
1076 {
1077         struct e1000_hw *hw = &adapter->hw;
1078         u32 pat, val;
1079         static const u32 _test[] =
1080                 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1081         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1082                 wr32(reg, (_test[pat] & write));
1083                 val = rd32(reg) & mask;
1084                 if (val != (_test[pat] & write & mask)) {
1085                         dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1086                                 "failed: got 0x%08X expected 0x%08X\n",
1087                                 reg, val, (_test[pat] & write & mask));
1088                         *data = reg;
1089                         return 1;
1090                 }
1091         }
1092
1093         return 0;
1094 }
1095
1096 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1097                               int reg, u32 mask, u32 write)
1098 {
1099         struct e1000_hw *hw = &adapter->hw;
1100         u32 val;
1101         wr32(reg, write & mask);
1102         val = rd32(reg);
1103         if ((write & mask) != (val & mask)) {
1104                 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
1105                         " got 0x%08X expected 0x%08X\n", reg,
1106                         (val & mask), (write & mask));
1107                 *data = reg;
1108                 return 1;
1109         }
1110
1111         return 0;
1112 }
1113
1114 #define REG_PATTERN_TEST(reg, mask, write) \
1115         do { \
1116                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1117                         return 1; \
1118         } while (0)
1119
1120 #define REG_SET_AND_CHECK(reg, mask, write) \
1121         do { \
1122                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1123                         return 1; \
1124         } while (0)
1125
1126 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1127 {
1128         struct e1000_hw *hw = &adapter->hw;
1129         struct igb_reg_test *test;
1130         u32 value, before, after;
1131         u32 i, toggle;
1132
1133         switch (adapter->hw.mac.type) {
1134         case e1000_i350:
1135                 test = reg_test_i350;
1136                 toggle = 0x7FEFF3FF;
1137                 break;
1138         case e1000_82580:
1139                 test = reg_test_82580;
1140                 toggle = 0x7FEFF3FF;
1141                 break;
1142         case e1000_82576:
1143                 test = reg_test_82576;
1144                 toggle = 0x7FFFF3FF;
1145                 break;
1146         default:
1147                 test = reg_test_82575;
1148                 toggle = 0x7FFFF3FF;
1149                 break;
1150         }
1151
1152         /* Because the status register is such a special case,
1153          * we handle it separately from the rest of the register
1154          * tests.  Some bits are read-only, some toggle, and some
1155          * are writable on newer MACs.
1156          */
1157         before = rd32(E1000_STATUS);
1158         value = (rd32(E1000_STATUS) & toggle);
1159         wr32(E1000_STATUS, toggle);
1160         after = rd32(E1000_STATUS) & toggle;
1161         if (value != after) {
1162                 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1163                         "got: 0x%08X expected: 0x%08X\n", after, value);
1164                 *data = 1;
1165                 return 1;
1166         }
1167         /* restore previous status */
1168         wr32(E1000_STATUS, before);
1169
1170         /* Perform the remainder of the register test, looping through
1171          * the test table until we either fail or reach the null entry.
1172          */
1173         while (test->reg) {
1174                 for (i = 0; i < test->array_len; i++) {
1175                         switch (test->test_type) {
1176                         case PATTERN_TEST:
1177                                 REG_PATTERN_TEST(test->reg +
1178                                                 (i * test->reg_offset),
1179                                                 test->mask,
1180                                                 test->write);
1181                                 break;
1182                         case SET_READ_TEST:
1183                                 REG_SET_AND_CHECK(test->reg +
1184                                                 (i * test->reg_offset),
1185                                                 test->mask,
1186                                                 test->write);
1187                                 break;
1188                         case WRITE_NO_TEST:
1189                                 writel(test->write,
1190                                     (adapter->hw.hw_addr + test->reg)
1191                                         + (i * test->reg_offset));
1192                                 break;
1193                         case TABLE32_TEST:
1194                                 REG_PATTERN_TEST(test->reg + (i * 4),
1195                                                 test->mask,
1196                                                 test->write);
1197                                 break;
1198                         case TABLE64_TEST_LO:
1199                                 REG_PATTERN_TEST(test->reg + (i * 8),
1200                                                 test->mask,
1201                                                 test->write);
1202                                 break;
1203                         case TABLE64_TEST_HI:
1204                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1205                                                 test->mask,
1206                                                 test->write);
1207                                 break;
1208                         }
1209                 }
1210                 test++;
1211         }
1212
1213         *data = 0;
1214         return 0;
1215 }
1216
1217 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1218 {
1219         u16 temp;
1220         u16 checksum = 0;
1221         u16 i;
1222
1223         *data = 0;
1224         /* Read and add up the contents of the EEPROM */
1225         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1226                 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
1227                         *data = 1;
1228                         break;
1229                 }
1230                 checksum += temp;
1231         }
1232
1233         /* If Checksum is not Correct return error else test passed */
1234         if ((checksum != (u16) NVM_SUM) && !(*data))
1235                 *data = 2;
1236
1237         return *data;
1238 }
1239
1240 static irqreturn_t igb_test_intr(int irq, void *data)
1241 {
1242         struct igb_adapter *adapter = (struct igb_adapter *) data;
1243         struct e1000_hw *hw = &adapter->hw;
1244
1245         adapter->test_icr |= rd32(E1000_ICR);
1246
1247         return IRQ_HANDLED;
1248 }
1249
1250 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1251 {
1252         struct e1000_hw *hw = &adapter->hw;
1253         struct net_device *netdev = adapter->netdev;
1254         u32 mask, ics_mask, i = 0, shared_int = true;
1255         u32 irq = adapter->pdev->irq;
1256
1257         *data = 0;
1258
1259         /* Hook up test interrupt handler just for this test */
1260         if (adapter->msix_entries) {
1261                 if (request_irq(adapter->msix_entries[0].vector,
1262                                 igb_test_intr, 0, netdev->name, adapter)) {
1263                         *data = 1;
1264                         return -1;
1265                 }
1266         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1267                 shared_int = false;
1268                 if (request_irq(irq,
1269                                 igb_test_intr, 0, netdev->name, adapter)) {
1270                         *data = 1;
1271                         return -1;
1272                 }
1273         } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1274                                 netdev->name, adapter)) {
1275                 shared_int = false;
1276         } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1277                  netdev->name, adapter)) {
1278                 *data = 1;
1279                 return -1;
1280         }
1281         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1282                 (shared_int ? "shared" : "unshared"));
1283
1284         /* Disable all the interrupts */
1285         wr32(E1000_IMC, ~0);
1286         msleep(10);
1287
1288         /* Define all writable bits for ICS */
1289         switch (hw->mac.type) {
1290         case e1000_82575:
1291                 ics_mask = 0x37F47EDD;
1292                 break;
1293         case e1000_82576:
1294                 ics_mask = 0x77D4FBFD;
1295                 break;
1296         case e1000_82580:
1297                 ics_mask = 0x77DCFED5;
1298                 break;
1299         case e1000_i350:
1300                 ics_mask = 0x77DCFED5;
1301                 break;
1302         default:
1303                 ics_mask = 0x7FFFFFFF;
1304                 break;
1305         }
1306
1307         /* Test each interrupt */
1308         for (; i < 31; i++) {
1309                 /* Interrupt to test */
1310                 mask = 1 << i;
1311
1312                 if (!(mask & ics_mask))
1313                         continue;
1314
1315                 if (!shared_int) {
1316                         /* Disable the interrupt to be reported in
1317                          * the cause register and then force the same
1318                          * interrupt and see if one gets posted.  If
1319                          * an interrupt was posted to the bus, the
1320                          * test failed.
1321                          */
1322                         adapter->test_icr = 0;
1323
1324                         /* Flush any pending interrupts */
1325                         wr32(E1000_ICR, ~0);
1326
1327                         wr32(E1000_IMC, mask);
1328                         wr32(E1000_ICS, mask);
1329                         msleep(10);
1330
1331                         if (adapter->test_icr & mask) {
1332                                 *data = 3;
1333                                 break;
1334                         }
1335                 }
1336
1337                 /* Enable the interrupt to be reported in
1338                  * the cause register and then force the same
1339                  * interrupt and see if one gets posted.  If
1340                  * an interrupt was not posted to the bus, the
1341                  * test failed.
1342                  */
1343                 adapter->test_icr = 0;
1344
1345                 /* Flush any pending interrupts */
1346                 wr32(E1000_ICR, ~0);
1347
1348                 wr32(E1000_IMS, mask);
1349                 wr32(E1000_ICS, mask);
1350                 msleep(10);
1351
1352                 if (!(adapter->test_icr & mask)) {
1353                         *data = 4;
1354                         break;
1355                 }
1356
1357                 if (!shared_int) {
1358                         /* Disable the other interrupts to be reported in
1359                          * the cause register and then force the other
1360                          * interrupts and see if any get posted.  If
1361                          * an interrupt was posted to the bus, the
1362                          * test failed.
1363                          */
1364                         adapter->test_icr = 0;
1365
1366                         /* Flush any pending interrupts */
1367                         wr32(E1000_ICR, ~0);
1368
1369                         wr32(E1000_IMC, ~mask);
1370                         wr32(E1000_ICS, ~mask);
1371                         msleep(10);
1372
1373                         if (adapter->test_icr & mask) {
1374                                 *data = 5;
1375                                 break;
1376                         }
1377                 }
1378         }
1379
1380         /* Disable all the interrupts */
1381         wr32(E1000_IMC, ~0);
1382         msleep(10);
1383
1384         /* Unhook test interrupt handler */
1385         if (adapter->msix_entries)
1386                 free_irq(adapter->msix_entries[0].vector, adapter);
1387         else
1388                 free_irq(irq, adapter);
1389
1390         return *data;
1391 }
1392
1393 static void igb_free_desc_rings(struct igb_adapter *adapter)
1394 {
1395         igb_free_tx_resources(&adapter->test_tx_ring);
1396         igb_free_rx_resources(&adapter->test_rx_ring);
1397 }
1398
1399 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1400 {
1401         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1402         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1403         struct e1000_hw *hw = &adapter->hw;
1404         int ret_val;
1405
1406         /* Setup Tx descriptor ring and Tx buffers */
1407         tx_ring->count = IGB_DEFAULT_TXD;
1408         tx_ring->dev = &adapter->pdev->dev;
1409         tx_ring->netdev = adapter->netdev;
1410         tx_ring->reg_idx = adapter->vfs_allocated_count;
1411
1412         if (igb_setup_tx_resources(tx_ring)) {
1413                 ret_val = 1;
1414                 goto err_nomem;
1415         }
1416
1417         igb_setup_tctl(adapter);
1418         igb_configure_tx_ring(adapter, tx_ring);
1419
1420         /* Setup Rx descriptor ring and Rx buffers */
1421         rx_ring->count = IGB_DEFAULT_RXD;
1422         rx_ring->dev = &adapter->pdev->dev;
1423         rx_ring->netdev = adapter->netdev;
1424         rx_ring->rx_buffer_len = IGB_RXBUFFER_2048;
1425         rx_ring->reg_idx = adapter->vfs_allocated_count;
1426
1427         if (igb_setup_rx_resources(rx_ring)) {
1428                 ret_val = 3;
1429                 goto err_nomem;
1430         }
1431
1432         /* set the default queue to queue 0 of PF */
1433         wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1434
1435         /* enable receive ring */
1436         igb_setup_rctl(adapter);
1437         igb_configure_rx_ring(adapter, rx_ring);
1438
1439         igb_alloc_rx_buffers_adv(rx_ring, igb_desc_unused(rx_ring));
1440
1441         return 0;
1442
1443 err_nomem:
1444         igb_free_desc_rings(adapter);
1445         return ret_val;
1446 }
1447
1448 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1449 {
1450         struct e1000_hw *hw = &adapter->hw;
1451
1452         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1453         igb_write_phy_reg(hw, 29, 0x001F);
1454         igb_write_phy_reg(hw, 30, 0x8FFC);
1455         igb_write_phy_reg(hw, 29, 0x001A);
1456         igb_write_phy_reg(hw, 30, 0x8FF0);
1457 }
1458
1459 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1460 {
1461         struct e1000_hw *hw = &adapter->hw;
1462         u32 ctrl_reg = 0;
1463
1464         hw->mac.autoneg = false;
1465
1466         if (hw->phy.type == e1000_phy_m88) {
1467                 /* Auto-MDI/MDIX Off */
1468                 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1469                 /* reset to update Auto-MDI/MDIX */
1470                 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1471                 /* autoneg off */
1472                 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1473         } else if (hw->phy.type == e1000_phy_82580) {
1474                 /* enable MII loopback */
1475                 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1476         }
1477
1478         ctrl_reg = rd32(E1000_CTRL);
1479
1480         /* force 1000, set loopback */
1481         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1482
1483         /* Now set up the MAC to the same speed/duplex as the PHY. */
1484         ctrl_reg = rd32(E1000_CTRL);
1485         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1486         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1487                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1488                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1489                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1490                      E1000_CTRL_SLU);    /* Set link up enable bit */
1491
1492         if (hw->phy.type == e1000_phy_m88)
1493                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1494
1495         wr32(E1000_CTRL, ctrl_reg);
1496
1497         /* Disable the receiver on the PHY so when a cable is plugged in, the
1498          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1499          */
1500         if (hw->phy.type == e1000_phy_m88)
1501                 igb_phy_disable_receiver(adapter);
1502
1503         udelay(500);
1504
1505         return 0;
1506 }
1507
1508 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1509 {
1510         return igb_integrated_phy_loopback(adapter);
1511 }
1512
1513 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1514 {
1515         struct e1000_hw *hw = &adapter->hw;
1516         u32 reg;
1517
1518         reg = rd32(E1000_CTRL_EXT);
1519
1520         /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1521         if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1522                 reg = rd32(E1000_RCTL);
1523                 reg |= E1000_RCTL_LBM_TCVR;
1524                 wr32(E1000_RCTL, reg);
1525
1526                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1527
1528                 reg = rd32(E1000_CTRL);
1529                 reg &= ~(E1000_CTRL_RFCE |
1530                          E1000_CTRL_TFCE |
1531                          E1000_CTRL_LRST);
1532                 reg |= E1000_CTRL_SLU |
1533                        E1000_CTRL_FD;
1534                 wr32(E1000_CTRL, reg);
1535
1536                 /* Unset switch control to serdes energy detect */
1537                 reg = rd32(E1000_CONNSW);
1538                 reg &= ~E1000_CONNSW_ENRGSRC;
1539                 wr32(E1000_CONNSW, reg);
1540
1541                 /* Set PCS register for forced speed */
1542                 reg = rd32(E1000_PCS_LCTL);
1543                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1544                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1545                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1546                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1547                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1548                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1549                 wr32(E1000_PCS_LCTL, reg);
1550
1551                 return 0;
1552         }
1553
1554         return igb_set_phy_loopback(adapter);
1555 }
1556
1557 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1558 {
1559         struct e1000_hw *hw = &adapter->hw;
1560         u32 rctl;
1561         u16 phy_reg;
1562
1563         rctl = rd32(E1000_RCTL);
1564         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1565         wr32(E1000_RCTL, rctl);
1566
1567         hw->mac.autoneg = true;
1568         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1569         if (phy_reg & MII_CR_LOOPBACK) {
1570                 phy_reg &= ~MII_CR_LOOPBACK;
1571                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1572                 igb_phy_sw_reset(hw);
1573         }
1574 }
1575
1576 static void igb_create_lbtest_frame(struct sk_buff *skb,
1577                                     unsigned int frame_size)
1578 {
1579         memset(skb->data, 0xFF, frame_size);
1580         frame_size /= 2;
1581         memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1582         memset(&skb->data[frame_size + 10], 0xBE, 1);
1583         memset(&skb->data[frame_size + 12], 0xAF, 1);
1584 }
1585
1586 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1587 {
1588         frame_size /= 2;
1589         if (*(skb->data + 3) == 0xFF) {
1590                 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1591                    (*(skb->data + frame_size + 12) == 0xAF)) {
1592                         return 0;
1593                 }
1594         }
1595         return 13;
1596 }
1597
1598 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1599                                 struct igb_ring *tx_ring,
1600                                 unsigned int size)
1601 {
1602         union e1000_adv_rx_desc *rx_desc;
1603         struct igb_buffer *buffer_info;
1604         int rx_ntc, tx_ntc, count = 0;
1605         u32 staterr;
1606
1607         /* initialize next to clean and descriptor values */
1608         rx_ntc = rx_ring->next_to_clean;
1609         tx_ntc = tx_ring->next_to_clean;
1610         rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1611         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1612
1613         while (staterr & E1000_RXD_STAT_DD) {
1614                 /* check rx buffer */
1615                 buffer_info = &rx_ring->buffer_info[rx_ntc];
1616
1617                 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
1618                 dma_unmap_single(rx_ring->dev,
1619                                  buffer_info->dma,
1620                                  rx_ring->rx_buffer_len,
1621                                  DMA_FROM_DEVICE);
1622                 buffer_info->dma = 0;
1623
1624                 /* verify contents of skb */
1625                 if (!igb_check_lbtest_frame(buffer_info->skb, size))
1626                         count++;
1627
1628                 /* unmap buffer on tx side */
1629                 buffer_info = &tx_ring->buffer_info[tx_ntc];
1630                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
1631
1632                 /* increment rx/tx next to clean counters */
1633                 rx_ntc++;
1634                 if (rx_ntc == rx_ring->count)
1635                         rx_ntc = 0;
1636                 tx_ntc++;
1637                 if (tx_ntc == tx_ring->count)
1638                         tx_ntc = 0;
1639
1640                 /* fetch next descriptor */
1641                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc);
1642                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1643         }
1644
1645         /* re-map buffers to ring, store next to clean values */
1646         igb_alloc_rx_buffers_adv(rx_ring, count);
1647         rx_ring->next_to_clean = rx_ntc;
1648         tx_ring->next_to_clean = tx_ntc;
1649
1650         return count;
1651 }
1652
1653 static int igb_run_loopback_test(struct igb_adapter *adapter)
1654 {
1655         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1656         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1657         int i, j, lc, good_cnt, ret_val = 0;
1658         unsigned int size = 1024;
1659         netdev_tx_t tx_ret_val;
1660         struct sk_buff *skb;
1661
1662         /* allocate test skb */
1663         skb = alloc_skb(size, GFP_KERNEL);
1664         if (!skb)
1665                 return 11;
1666
1667         /* place data into test skb */
1668         igb_create_lbtest_frame(skb, size);
1669         skb_put(skb, size);
1670
1671         /*
1672          * Calculate the loop count based on the largest descriptor ring
1673          * The idea is to wrap the largest ring a number of times using 64
1674          * send/receive pairs during each loop
1675          */
1676
1677         if (rx_ring->count <= tx_ring->count)
1678                 lc = ((tx_ring->count / 64) * 2) + 1;
1679         else
1680                 lc = ((rx_ring->count / 64) * 2) + 1;
1681
1682         for (j = 0; j <= lc; j++) { /* loop count loop */
1683                 /* reset count of good packets */
1684                 good_cnt = 0;
1685
1686                 /* place 64 packets on the transmit queue*/
1687                 for (i = 0; i < 64; i++) {
1688                         skb_get(skb);
1689                         tx_ret_val = igb_xmit_frame_ring_adv(skb, tx_ring);
1690                         if (tx_ret_val == NETDEV_TX_OK)
1691                                 good_cnt++;
1692                 }
1693
1694                 if (good_cnt != 64) {
1695                         ret_val = 12;
1696                         break;
1697                 }
1698
1699                 /* allow 200 milliseconds for packets to go from tx to rx */
1700                 msleep(200);
1701
1702                 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1703                 if (good_cnt != 64) {
1704                         ret_val = 13;
1705                         break;
1706                 }
1707         } /* end loop count loop */
1708
1709         /* free the original skb */
1710         kfree_skb(skb);
1711
1712         return ret_val;
1713 }
1714
1715 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1716 {
1717         /* PHY loopback cannot be performed if SoL/IDER
1718          * sessions are active */
1719         if (igb_check_reset_block(&adapter->hw)) {
1720                 dev_err(&adapter->pdev->dev,
1721                         "Cannot do PHY loopback test "
1722                         "when SoL/IDER is active.\n");
1723                 *data = 0;
1724                 goto out;
1725         }
1726         *data = igb_setup_desc_rings(adapter);
1727         if (*data)
1728                 goto out;
1729         *data = igb_setup_loopback_test(adapter);
1730         if (*data)
1731                 goto err_loopback;
1732         *data = igb_run_loopback_test(adapter);
1733         igb_loopback_cleanup(adapter);
1734
1735 err_loopback:
1736         igb_free_desc_rings(adapter);
1737 out:
1738         return *data;
1739 }
1740
1741 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1742 {
1743         struct e1000_hw *hw = &adapter->hw;
1744         *data = 0;
1745         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1746                 int i = 0;
1747                 hw->mac.serdes_has_link = false;
1748
1749                 /* On some blade server designs, link establishment
1750                  * could take as long as 2-3 minutes */
1751                 do {
1752                         hw->mac.ops.check_for_link(&adapter->hw);
1753                         if (hw->mac.serdes_has_link)
1754                                 return *data;
1755                         msleep(20);
1756                 } while (i++ < 3750);
1757
1758                 *data = 1;
1759         } else {
1760                 hw->mac.ops.check_for_link(&adapter->hw);
1761                 if (hw->mac.autoneg)
1762                         msleep(4000);
1763
1764                 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1765                         *data = 1;
1766         }
1767         return *data;
1768 }
1769
1770 static void igb_diag_test(struct net_device *netdev,
1771                           struct ethtool_test *eth_test, u64 *data)
1772 {
1773         struct igb_adapter *adapter = netdev_priv(netdev);
1774         u16 autoneg_advertised;
1775         u8 forced_speed_duplex, autoneg;
1776         bool if_running = netif_running(netdev);
1777
1778         set_bit(__IGB_TESTING, &adapter->state);
1779         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1780                 /* Offline tests */
1781
1782                 /* save speed, duplex, autoneg settings */
1783                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1784                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1785                 autoneg = adapter->hw.mac.autoneg;
1786
1787                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1788
1789                 /* power up link for link test */
1790                 igb_power_up_link(adapter);
1791
1792                 /* Link test performed before hardware reset so autoneg doesn't
1793                  * interfere with test result */
1794                 if (igb_link_test(adapter, &data[4]))
1795                         eth_test->flags |= ETH_TEST_FL_FAILED;
1796
1797                 if (if_running)
1798                         /* indicate we're in test mode */
1799                         dev_close(netdev);
1800                 else
1801                         igb_reset(adapter);
1802
1803                 if (igb_reg_test(adapter, &data[0]))
1804                         eth_test->flags |= ETH_TEST_FL_FAILED;
1805
1806                 igb_reset(adapter);
1807                 if (igb_eeprom_test(adapter, &data[1]))
1808                         eth_test->flags |= ETH_TEST_FL_FAILED;
1809
1810                 igb_reset(adapter);
1811                 if (igb_intr_test(adapter, &data[2]))
1812                         eth_test->flags |= ETH_TEST_FL_FAILED;
1813
1814                 igb_reset(adapter);
1815                 /* power up link for loopback test */
1816                 igb_power_up_link(adapter);
1817                 if (igb_loopback_test(adapter, &data[3]))
1818                         eth_test->flags |= ETH_TEST_FL_FAILED;
1819
1820                 /* restore speed, duplex, autoneg settings */
1821                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1822                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1823                 adapter->hw.mac.autoneg = autoneg;
1824
1825                 /* force this routine to wait until autoneg complete/timeout */
1826                 adapter->hw.phy.autoneg_wait_to_complete = true;
1827                 igb_reset(adapter);
1828                 adapter->hw.phy.autoneg_wait_to_complete = false;
1829
1830                 clear_bit(__IGB_TESTING, &adapter->state);
1831                 if (if_running)
1832                         dev_open(netdev);
1833         } else {
1834                 dev_info(&adapter->pdev->dev, "online testing starting\n");
1835
1836                 /* PHY is powered down when interface is down */
1837                 if (if_running && igb_link_test(adapter, &data[4]))
1838                         eth_test->flags |= ETH_TEST_FL_FAILED;
1839                 else
1840                         data[4] = 0;
1841
1842                 /* Online tests aren't run; pass by default */
1843                 data[0] = 0;
1844                 data[1] = 0;
1845                 data[2] = 0;
1846                 data[3] = 0;
1847
1848                 clear_bit(__IGB_TESTING, &adapter->state);
1849         }
1850         msleep_interruptible(4 * 1000);
1851 }
1852
1853 static int igb_wol_exclusion(struct igb_adapter *adapter,
1854                              struct ethtool_wolinfo *wol)
1855 {
1856         struct e1000_hw *hw = &adapter->hw;
1857         int retval = 1; /* fail by default */
1858
1859         switch (hw->device_id) {
1860         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1861                 /* WoL not supported */
1862                 wol->supported = 0;
1863                 break;
1864         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1865         case E1000_DEV_ID_82576_FIBER:
1866         case E1000_DEV_ID_82576_SERDES:
1867                 /* Wake events not supported on port B */
1868                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1869                         wol->supported = 0;
1870                         break;
1871                 }
1872                 /* return success for non excluded adapter ports */
1873                 retval = 0;
1874                 break;
1875         case E1000_DEV_ID_82576_QUAD_COPPER:
1876         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
1877                 /* quad port adapters only support WoL on port A */
1878                 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1879                         wol->supported = 0;
1880                         break;
1881                 }
1882                 /* return success for non excluded adapter ports */
1883                 retval = 0;
1884                 break;
1885         default:
1886                 /* dual port cards only support WoL on port A from now on
1887                  * unless it was enabled in the eeprom for port B
1888                  * so exclude FUNC_1 ports from having WoL enabled */
1889                 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) &&
1890                     !adapter->eeprom_wol) {
1891                         wol->supported = 0;
1892                         break;
1893                 }
1894
1895                 retval = 0;
1896         }
1897
1898         return retval;
1899 }
1900
1901 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1902 {
1903         struct igb_adapter *adapter = netdev_priv(netdev);
1904
1905         wol->supported = WAKE_UCAST | WAKE_MCAST |
1906                          WAKE_BCAST | WAKE_MAGIC |
1907                          WAKE_PHY;
1908         wol->wolopts = 0;
1909
1910         /* this function will set ->supported = 0 and return 1 if wol is not
1911          * supported by this hardware */
1912         if (igb_wol_exclusion(adapter, wol) ||
1913             !device_can_wakeup(&adapter->pdev->dev))
1914                 return;
1915
1916         /* apply any specific unsupported masks here */
1917         switch (adapter->hw.device_id) {
1918         default:
1919                 break;
1920         }
1921
1922         if (adapter->wol & E1000_WUFC_EX)
1923                 wol->wolopts |= WAKE_UCAST;
1924         if (adapter->wol & E1000_WUFC_MC)
1925                 wol->wolopts |= WAKE_MCAST;
1926         if (adapter->wol & E1000_WUFC_BC)
1927                 wol->wolopts |= WAKE_BCAST;
1928         if (adapter->wol & E1000_WUFC_MAG)
1929                 wol->wolopts |= WAKE_MAGIC;
1930         if (adapter->wol & E1000_WUFC_LNKC)
1931                 wol->wolopts |= WAKE_PHY;
1932 }
1933
1934 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1935 {
1936         struct igb_adapter *adapter = netdev_priv(netdev);
1937
1938         if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
1939                 return -EOPNOTSUPP;
1940
1941         if (igb_wol_exclusion(adapter, wol) ||
1942             !device_can_wakeup(&adapter->pdev->dev))
1943                 return wol->wolopts ? -EOPNOTSUPP : 0;
1944
1945         /* these settings will always override what we currently have */
1946         adapter->wol = 0;
1947
1948         if (wol->wolopts & WAKE_UCAST)
1949                 adapter->wol |= E1000_WUFC_EX;
1950         if (wol->wolopts & WAKE_MCAST)
1951                 adapter->wol |= E1000_WUFC_MC;
1952         if (wol->wolopts & WAKE_BCAST)
1953                 adapter->wol |= E1000_WUFC_BC;
1954         if (wol->wolopts & WAKE_MAGIC)
1955                 adapter->wol |= E1000_WUFC_MAG;
1956         if (wol->wolopts & WAKE_PHY)
1957                 adapter->wol |= E1000_WUFC_LNKC;
1958         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1959
1960         return 0;
1961 }
1962
1963 /* bit defines for adapter->led_status */
1964 #define IGB_LED_ON              0
1965
1966 static int igb_phys_id(struct net_device *netdev, u32 data)
1967 {
1968         struct igb_adapter *adapter = netdev_priv(netdev);
1969         struct e1000_hw *hw = &adapter->hw;
1970         unsigned long timeout;
1971
1972         timeout = data * 1000;
1973
1974         /*
1975          *  msleep_interruptable only accepts unsigned int so we are limited
1976          * in how long a duration we can wait
1977          */
1978         if (!timeout || timeout > UINT_MAX)
1979                 timeout = UINT_MAX;
1980
1981         igb_blink_led(hw);
1982         msleep_interruptible(timeout);
1983
1984         igb_led_off(hw);
1985         clear_bit(IGB_LED_ON, &adapter->led_status);
1986         igb_cleanup_led(hw);
1987
1988         return 0;
1989 }
1990
1991 static int igb_set_coalesce(struct net_device *netdev,
1992                             struct ethtool_coalesce *ec)
1993 {
1994         struct igb_adapter *adapter = netdev_priv(netdev);
1995         int i;
1996
1997         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1998             ((ec->rx_coalesce_usecs > 3) &&
1999              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2000             (ec->rx_coalesce_usecs == 2))
2001                 return -EINVAL;
2002
2003         if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2004             ((ec->tx_coalesce_usecs > 3) &&
2005              (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2006             (ec->tx_coalesce_usecs == 2))
2007                 return -EINVAL;
2008
2009         if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2010                 return -EINVAL;
2011
2012         /* If ITR is disabled, disable DMAC */
2013         if (ec->rx_coalesce_usecs == 0) {
2014                 if (adapter->flags & IGB_FLAG_DMAC)
2015                         adapter->flags &= ~IGB_FLAG_DMAC;
2016         }
2017
2018         /* convert to rate of irq's per second */
2019         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2020                 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2021         else
2022                 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2023
2024         /* convert to rate of irq's per second */
2025         if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2026                 adapter->tx_itr_setting = adapter->rx_itr_setting;
2027         else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2028                 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2029         else
2030                 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2031
2032         for (i = 0; i < adapter->num_q_vectors; i++) {
2033                 struct igb_q_vector *q_vector = adapter->q_vector[i];
2034                 if (q_vector->rx_ring)
2035                         q_vector->itr_val = adapter->rx_itr_setting;
2036                 else
2037                         q_vector->itr_val = adapter->tx_itr_setting;
2038                 if (q_vector->itr_val && q_vector->itr_val <= 3)
2039                         q_vector->itr_val = IGB_START_ITR;
2040                 q_vector->set_itr = 1;
2041         }
2042
2043         return 0;
2044 }
2045
2046 static int igb_get_coalesce(struct net_device *netdev,
2047                             struct ethtool_coalesce *ec)
2048 {
2049         struct igb_adapter *adapter = netdev_priv(netdev);
2050
2051         if (adapter->rx_itr_setting <= 3)
2052                 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2053         else
2054                 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2055
2056         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2057                 if (adapter->tx_itr_setting <= 3)
2058                         ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2059                 else
2060                         ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2061         }
2062
2063         return 0;
2064 }
2065
2066 static int igb_nway_reset(struct net_device *netdev)
2067 {
2068         struct igb_adapter *adapter = netdev_priv(netdev);
2069         if (netif_running(netdev))
2070                 igb_reinit_locked(adapter);
2071         return 0;
2072 }
2073
2074 static int igb_get_sset_count(struct net_device *netdev, int sset)
2075 {
2076         switch (sset) {
2077         case ETH_SS_STATS:
2078                 return IGB_STATS_LEN;
2079         case ETH_SS_TEST:
2080                 return IGB_TEST_LEN;
2081         default:
2082                 return -ENOTSUPP;
2083         }
2084 }
2085
2086 static void igb_get_ethtool_stats(struct net_device *netdev,
2087                                   struct ethtool_stats *stats, u64 *data)
2088 {
2089         struct igb_adapter *adapter = netdev_priv(netdev);
2090         struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2091         unsigned int start;
2092         struct igb_ring *ring;
2093         int i, j;
2094         char *p;
2095
2096         spin_lock(&adapter->stats64_lock);
2097         igb_update_stats(adapter, net_stats);
2098
2099         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2100                 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2101                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2102                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2103         }
2104         for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2105                 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2106                 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2107                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2108         }
2109         for (j = 0; j < adapter->num_tx_queues; j++) {
2110                 u64     restart2;
2111
2112                 ring = adapter->tx_ring[j];
2113                 do {
2114                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2115                         data[i]   = ring->tx_stats.packets;
2116                         data[i+1] = ring->tx_stats.bytes;
2117                         data[i+2] = ring->tx_stats.restart_queue;
2118                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2119                 do {
2120                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2121                         restart2  = ring->tx_stats.restart_queue2;
2122                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2123                 data[i+2] += restart2;
2124
2125                 i += IGB_TX_QUEUE_STATS_LEN;
2126         }
2127         for (j = 0; j < adapter->num_rx_queues; j++) {
2128                 ring = adapter->rx_ring[j];
2129                 do {
2130                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2131                         data[i]   = ring->rx_stats.packets;
2132                         data[i+1] = ring->rx_stats.bytes;
2133                         data[i+2] = ring->rx_stats.drops;
2134                         data[i+3] = ring->rx_stats.csum_err;
2135                         data[i+4] = ring->rx_stats.alloc_failed;
2136                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2137                 i += IGB_RX_QUEUE_STATS_LEN;
2138         }
2139         spin_unlock(&adapter->stats64_lock);
2140 }
2141
2142 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2143 {
2144         struct igb_adapter *adapter = netdev_priv(netdev);
2145         u8 *p = data;
2146         int i;
2147
2148         switch (stringset) {
2149         case ETH_SS_TEST:
2150                 memcpy(data, *igb_gstrings_test,
2151                         IGB_TEST_LEN*ETH_GSTRING_LEN);
2152                 break;
2153         case ETH_SS_STATS:
2154                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2155                         memcpy(p, igb_gstrings_stats[i].stat_string,
2156                                ETH_GSTRING_LEN);
2157                         p += ETH_GSTRING_LEN;
2158                 }
2159                 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2160                         memcpy(p, igb_gstrings_net_stats[i].stat_string,
2161                                ETH_GSTRING_LEN);
2162                         p += ETH_GSTRING_LEN;
2163                 }
2164                 for (i = 0; i < adapter->num_tx_queues; i++) {
2165                         sprintf(p, "tx_queue_%u_packets", i);
2166                         p += ETH_GSTRING_LEN;
2167                         sprintf(p, "tx_queue_%u_bytes", i);
2168                         p += ETH_GSTRING_LEN;
2169                         sprintf(p, "tx_queue_%u_restart", i);
2170                         p += ETH_GSTRING_LEN;
2171                 }
2172                 for (i = 0; i < adapter->num_rx_queues; i++) {
2173                         sprintf(p, "rx_queue_%u_packets", i);
2174                         p += ETH_GSTRING_LEN;
2175                         sprintf(p, "rx_queue_%u_bytes", i);
2176                         p += ETH_GSTRING_LEN;
2177                         sprintf(p, "rx_queue_%u_drops", i);
2178                         p += ETH_GSTRING_LEN;
2179                         sprintf(p, "rx_queue_%u_csum_err", i);
2180                         p += ETH_GSTRING_LEN;
2181                         sprintf(p, "rx_queue_%u_alloc_failed", i);
2182                         p += ETH_GSTRING_LEN;
2183                 }
2184 /*              BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2185                 break;
2186         }
2187 }
2188
2189 static const struct ethtool_ops igb_ethtool_ops = {
2190         .get_settings           = igb_get_settings,
2191         .set_settings           = igb_set_settings,
2192         .get_drvinfo            = igb_get_drvinfo,
2193         .get_regs_len           = igb_get_regs_len,
2194         .get_regs               = igb_get_regs,
2195         .get_wol                = igb_get_wol,
2196         .set_wol                = igb_set_wol,
2197         .get_msglevel           = igb_get_msglevel,
2198         .set_msglevel           = igb_set_msglevel,
2199         .nway_reset             = igb_nway_reset,
2200         .get_link               = igb_get_link,
2201         .get_eeprom_len         = igb_get_eeprom_len,
2202         .get_eeprom             = igb_get_eeprom,
2203         .set_eeprom             = igb_set_eeprom,
2204         .get_ringparam          = igb_get_ringparam,
2205         .set_ringparam          = igb_set_ringparam,
2206         .get_pauseparam         = igb_get_pauseparam,
2207         .set_pauseparam         = igb_set_pauseparam,
2208         .get_rx_csum            = igb_get_rx_csum,
2209         .set_rx_csum            = igb_set_rx_csum,
2210         .get_tx_csum            = igb_get_tx_csum,
2211         .set_tx_csum            = igb_set_tx_csum,
2212         .get_sg                 = ethtool_op_get_sg,
2213         .set_sg                 = ethtool_op_set_sg,
2214         .get_tso                = ethtool_op_get_tso,
2215         .set_tso                = igb_set_tso,
2216         .self_test              = igb_diag_test,
2217         .get_strings            = igb_get_strings,
2218         .phys_id                = igb_phys_id,
2219         .get_sset_count         = igb_get_sset_count,
2220         .get_ethtool_stats      = igb_get_ethtool_stats,
2221         .get_coalesce           = igb_get_coalesce,
2222         .set_coalesce           = igb_set_coalesce,
2223 };
2224
2225 void igb_set_ethtool_ops(struct net_device *netdev)
2226 {
2227         SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2228 }