drivers/net/ixgbe/ixgbe_82598.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82598_MAX_TX_QUEUES 32
  36 #define IXGBE_82598_MAX_RX_QUEUES 64
  37 #define IXGBE_82598_RAR_ENTRIES   16
  38 #define IXGBE_82598_MC_TBL_SIZE  128
  39 #define IXGBE_82598_VFT_TBL_SIZE 128
  40
  41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
  42                                              ixgbe_link_speed *speed,
  43                                              bool *autoneg);
  44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
  45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
  46                                                ixgbe_link_speed speed,
  47                                                bool autoneg,
  48                                                bool autoneg_wait_to_complete);
  49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  50                                        u8 *eeprom_data);
  51
  52 /**
  53  *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Read PCIe configuration space, and get the MSI-X vector count from
  57  *  the capabilities table.
  58  **/
  59 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_adapter *adapter = hw->back;
  62         u16 msix_count;
  63         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
  64                              &msix_count);
  65         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  66
  67         /* MSI-X count is zero-based in HW, so increment to give proper value */
  68         msix_count++;
  69
  70         return msix_count;
  71 }
  72
  73 /**
  74  */
  75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
  76 {
  77         struct ixgbe_mac_info *mac = &hw->mac;
  78
  79         /* Call PHY identify routine to get the phy type */
  80         ixgbe_identify_phy_generic(hw);
  81
  82         mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
  83         mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
  84         mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
  85         mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
  86         mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
  87         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
  88
  89         return 0;
  90 }
  91
  92 /**
  93  *  ixgbe_init_phy_ops_82598 - PHY/SFP specific init
  94  *  @hw: pointer to hardware structure
  95  *
  96  *  Initialize any function pointers that were not able to be
  97  *  set during get_invariants because the PHY/SFP type was
  98  *  not known.  Perform the SFP init if necessary.
  99  *
 100  **/
 101 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
 102 {
 103         struct ixgbe_mac_info *mac = &hw->mac;
 104         struct ixgbe_phy_info *phy = &hw->phy;
 105         s32 ret_val = 0;
 106         u16 list_offset, data_offset;
 107
 108         /* Identify the PHY */
 109         phy->ops.identify(hw);
 110
 111         /* Overwrite the link function pointers if copper PHY */
 112         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 113                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
 114                 mac->ops.setup_link_speed =
 115                                      &ixgbe_setup_copper_link_speed_82598;
 116                 mac->ops.get_link_capabilities =
 117                                   &ixgbe_get_copper_link_capabilities_82598;
 118         }
 119
 120         switch (hw->phy.type) {
 121         case ixgbe_phy_tn:
 122                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 123                 phy->ops.get_firmware_version =
 124                              &ixgbe_get_phy_firmware_version_tnx;
 125                 break;
 126         case ixgbe_phy_nl:
 127                 phy->ops.reset = &ixgbe_reset_phy_nl;
 128
 129                 /* Call SFP+ identify routine to get the SFP+ module type */
 130                 ret_val = phy->ops.identify_sfp(hw);
 131                 if (ret_val != 0)
 132                         goto out;
 133                 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
 134                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 135                         goto out;
 136                 }
 137
 138                 /* Check to see if SFP+ module is supported */
 139                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
 140                                                             &list_offset,
 141                                                             &data_offset);
 142                 if (ret_val != 0) {
 143                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 144                         goto out;
 145                 }
 146                 break;
 147         default:
 148                 break;
 149         }
 150
 151 out:
 152         return ret_val;
 153 }
 154
 155 /**
 156  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
 157  *  @hw: pointer to hardware structure
 158  *  @speed: pointer to link speed
 159  *  @autoneg: boolean auto-negotiation value
 160  *
 161  *  Determines the link capabilities by reading the AUTOC register.
 162  **/
 163 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
 164                                              ixgbe_link_speed *speed,
 165                                              bool *autoneg)
 166 {
 167         s32 status = 0;
 168         u32 autoc = 0;
 169
 170         /*
 171          * Determine link capabilities based on the stored value of AUTOC,
 172          * which represents EEPROM defaults.  If AUTOC value has not been
 173          * stored, use the current register value.
 174          */
 175         if (hw->mac.orig_link_settings_stored)
 176                 autoc = hw->mac.orig_autoc;
 177         else
 178                 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 179
 180         switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 181         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 182                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 183                 *autoneg = false;
 184                 break;
 185
 186         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 187                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 188                 *autoneg = false;
 189                 break;
 190
 191         case IXGBE_AUTOC_LMS_1G_AN:
 192                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 193                 *autoneg = true;
 194                 break;
 195
 196         case IXGBE_AUTOC_LMS_KX4_AN:
 197         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
 198                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 199                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
 200                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 201                 if (autoc & IXGBE_AUTOC_KX_SUPP)
 202                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 203                 *autoneg = true;
 204                 break;
 205
 206         default:
 207                 status = IXGBE_ERR_LINK_SETUP;
 208                 break;
 209         }
 210
 211         return status;
 212 }
 213
 214 /**
 215  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
 216  *  @hw: pointer to hardware structure
 217  *  @speed: pointer to link speed
 218  *  @autoneg: boolean auto-negotiation value
 219  *
 220  *  Determines the link capabilities by reading the AUTOC register.
 221  **/
 222 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
 223                                                     ixgbe_link_speed *speed,
 224                                                     bool *autoneg)
 225 {
 226         s32 status = IXGBE_ERR_LINK_SETUP;
 227         u16 speed_ability;
 228
 229         *speed = 0;
 230         *autoneg = true;
 231
 232         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 233                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 234                                       &speed_ability);
 235
 236         if (status == 0) {
 237                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 238                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 239                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 240                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 241         }
 242
 243         return status;
 244 }
 245
 246 /**
 247  *  ixgbe_get_media_type_82598 - Determines media type
 248  *  @hw: pointer to hardware structure
 249  *
 250  *  Returns the media type (fiber, copper, backplane)
 251  **/
 252 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
 253 {
 254         enum ixgbe_media_type media_type;
 255
 256         /* Media type for I82598 is based on device ID */
 257         switch (hw->device_id) {
 258         case IXGBE_DEV_ID_82598:
 259         case IXGBE_DEV_ID_82598_BX:
 260                 media_type = ixgbe_media_type_backplane;
 261                 break;
 262         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
 263         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
 264         case IXGBE_DEV_ID_82598EB_CX4:
 265         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
 266         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
 267         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
 268         case IXGBE_DEV_ID_82598EB_XF_LR:
 269         case IXGBE_DEV_ID_82598EB_SFP_LOM:
 270                 media_type = ixgbe_media_type_fiber;
 271                 break;
 272         case IXGBE_DEV_ID_82598AT:
 273                 media_type = ixgbe_media_type_copper;
 274                 break;
 275         default:
 276                 media_type = ixgbe_media_type_unknown;
 277                 break;
 278         }
 279
 280         return media_type;
 281 }
 282
 283 /**
 284  *  ixgbe_fc_enable_82598 - Enable flow control
 285  *  @hw: pointer to hardware structure
 286  *  @packetbuf_num: packet buffer number (0-7)
 287  *
 288  *  Enable flow control according to the current settings.
 289  **/
 290 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 291 {
 292         s32 ret_val = 0;
 293         u32 fctrl_reg;
 294         u32 rmcs_reg;
 295         u32 reg;
 296
 297         fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 298         fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
 299
 300         rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 301         rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
 302
 303         /*
 304          * The possible values of fc.current_mode are:
 305          * 0: Flow control is completely disabled
 306          * 1: Rx flow control is enabled (we can receive pause frames,
 307          *    but not send pause frames).
 308          * 2:  Tx flow control is enabled (we can send pause frames but
 309          *     we do not support receiving pause frames).
 310          * 3: Both Rx and Tx flow control (symmetric) are enabled.
 311          * other: Invalid.
 312          */
 313         switch (hw->fc.current_mode) {
 314         case ixgbe_fc_none:
 315                 /* Flow control completely disabled by software override. */
 316                 break;
 317         case ixgbe_fc_rx_pause:
 318                 /*
 319                  * Rx Flow control is enabled and Tx Flow control is
 320                  * disabled by software override. Since there really
 321                  * isn't a way to advertise that we are capable of RX
 322                  * Pause ONLY, we will advertise that we support both
 323                  * symmetric and asymmetric Rx PAUSE.  Later, we will
 324                  * disable the adapter's ability to send PAUSE frames.
 325                  */
 326                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 327                 break;
 328         case ixgbe_fc_tx_pause:
 329                 /*
 330                  * Tx Flow control is enabled, and Rx Flow control is
 331                  * disabled by software override.
 332                  */
 333                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 334                 break;
 335         case ixgbe_fc_full:
 336                 /* Flow control (both Rx and Tx) is enabled by SW override. */
 337                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 338                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 339                 break;
 340         default:
 341                 hw_dbg(hw, "Flow control param set incorrectly\n");
 342                 ret_val = -IXGBE_ERR_CONFIG;
 343                 goto out;
 344                 break;
 345         }
 346
 347         /* Enable 802.3x based flow control settings. */
 348         fctrl_reg |= IXGBE_FCTRL_DPF;
 349         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
 350         IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 351
 352         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
 353         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
 354                 if (hw->fc.send_xon) {
 355                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 356                                         (hw->fc.low_water | IXGBE_FCRTL_XONE));
 357                 } else {
 358                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 359                                         hw->fc.low_water);
 360                 }
 361
 362                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
 363                                 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
 364         }
 365
 366         /* Configure pause time (2 TCs per register) */
 367         reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
 368         if ((packetbuf_num & 1) == 0)
 369                 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
 370         else
 371                 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
 372         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
 373
 374         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 375
 376 out:
 377         return ret_val;
 378 }
 379
 380 /**
 381  *  ixgbe_setup_fc_82598 - Configure flow control settings
 382  *  @hw: pointer to hardware structure
 383  *  @packetbuf_num: packet buffer number (0-7)
 384  *
 385  *  Configures the flow control settings based on SW configuration.  This
 386  *  function is used for 802.3x flow control configuration only.
 387  **/
 388 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 389 {
 390         s32 ret_val = 0;
 391         ixgbe_link_speed speed;
 392         bool link_up;
 393
 394         /* Validate the packetbuf configuration */
 395         if (packetbuf_num < 0 || packetbuf_num > 7) {
 396                 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
 397                           " 0-7\n", packetbuf_num);
 398                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 399                 goto out;
 400         }
 401
 402         /*
 403          * Validate the water mark configuration.  Zero water marks are invalid
 404          * because it causes the controller to just blast out fc packets.
 405          */
 406         if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
 407                 if (hw->fc.requested_mode != ixgbe_fc_none) {
 408                         hw_dbg(hw, "Invalid water mark configuration\n");
 409                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 410                         goto out;
 411                 }
 412         }
 413
 414         /*
 415          * Validate the requested mode.  Strict IEEE mode does not allow
 416          * ixgbe_fc_rx_pause because it will cause testing anomalies.
 417          */
 418         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 419                 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 420                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 421                 goto out;
 422         }
 423
 424         /*
 425          * 10gig parts do not have a word in the EEPROM to determine the
 426          * default flow control setting, so we explicitly set it to full.
 427          */
 428         if (hw->fc.requested_mode == ixgbe_fc_default)
 429                 hw->fc.requested_mode = ixgbe_fc_full;
 430
 431         /*
 432          * Save off the requested flow control mode for use later.  Depending
 433          * on the link partner's capabilities, we may or may not use this mode.
 434          */
 435
 436         hw->fc.current_mode = hw->fc.requested_mode;
 437
 438         /* Decide whether to use autoneg or not. */
 439         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 440         if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
 441             (speed == IXGBE_LINK_SPEED_1GB_FULL))
 442                 ret_val = ixgbe_fc_autoneg(hw);
 443
 444         if (ret_val)
 445                 goto out;
 446
 447         ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
 448
 449 out:
 450         return ret_val;
 451 }
 452
 453 /**
 454  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
 455  *  @hw: pointer to hardware structure
 456  *
 457  *  Configures link settings based on values in the ixgbe_hw struct.
 458  *  Restarts the link.  Performs autonegotiation if needed.
 459  **/
 460 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
 461 {
 462         u32 autoc_reg;
 463         u32 links_reg;
 464         u32 i;
 465         s32 status = 0;
 466
 467         /* Restart link */
 468         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 469         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 470         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 471
 472         /* Only poll for autoneg to complete if specified to do so */
 473         if (hw->phy.autoneg_wait_to_complete) {
 474                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 475                      IXGBE_AUTOC_LMS_KX4_AN ||
 476                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 477                      IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 478                         links_reg = 0; /* Just in case Autoneg time = 0 */
 479                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 480                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 481                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 482                                         break;
 483                                 msleep(100);
 484                         }
 485                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 486                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 487                                 hw_dbg(hw, "Autonegotiation did not complete.\n");
 488                         }
 489                 }
 490         }
 491
 492         /*
 493          * We want to save off the original Flow Control configuration just in
 494          * case we get disconnected and then reconnected into a different hub
 495          * or switch with different Flow Control capabilities.
 496          */
 497         ixgbe_setup_fc_82598(hw, 0);
 498
 499         /* Add delay to filter out noises during initial link setup */
 500         msleep(50);
 501
 502         return status;
 503 }
 504
 505 /**
 506  *  ixgbe_check_mac_link_82598 - Get link/speed status
 507  *  @hw: pointer to hardware structure
 508  *  @speed: pointer to link speed
 509  *  @link_up: true is link is up, false otherwise
 510  *  @link_up_wait_to_complete: bool used to wait for link up or not
 511  *
 512  *  Reads the links register to determine if link is up and the current speed
 513  **/
 514 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
 515                                       ixgbe_link_speed *speed, bool *link_up,
 516                                       bool link_up_wait_to_complete)
 517 {
 518         u32 links_reg;
 519         u32 i;
 520         u16 link_reg, adapt_comp_reg;
 521
 522         /*
 523          * SERDES PHY requires us to read link status from register 0xC79F.
 524          * Bit 0 set indicates link is up/ready; clear indicates link down.
 525          * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
 526          * clear indicates active; set indicates inactive.
 527          */
 528         if (hw->phy.type == ixgbe_phy_nl) {
 529                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 530                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 531                 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
 532                                      &adapt_comp_reg);
 533                 if (link_up_wait_to_complete) {
 534                         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 535                                 if ((link_reg & 1) &&
 536                                     ((adapt_comp_reg & 1) == 0)) {
 537                                         *link_up = true;
 538                                         break;
 539                                 } else {
 540                                         *link_up = false;
 541                                 }
 542                                 msleep(100);
 543                                 hw->phy.ops.read_reg(hw, 0xC79F,
 544                                                      IXGBE_TWINAX_DEV,
 545                                                      &link_reg);
 546                                 hw->phy.ops.read_reg(hw, 0xC00C,
 547                                                      IXGBE_TWINAX_DEV,
 548                                                      &adapt_comp_reg);
 549                         }
 550                 } else {
 551                         if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
 552                                 *link_up = true;
 553                         else
 554                                 *link_up = false;
 555                 }
 556
 557                 if (*link_up == false)
 558                         goto out;
 559         }
 560
 561         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 562         if (link_up_wait_to_complete) {
 563                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 564                         if (links_reg & IXGBE_LINKS_UP) {
 565                                 *link_up = true;
 566                                 break;
 567                         } else {
 568                                 *link_up = false;
 569                         }
 570                         msleep(100);
 571                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 572                 }
 573         } else {
 574                 if (links_reg & IXGBE_LINKS_UP)
 575                         *link_up = true;
 576                 else
 577                         *link_up = false;
 578         }
 579
 580         if (links_reg & IXGBE_LINKS_SPEED)
 581                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 582         else
 583                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 584
 585 out:
 586         return 0;
 587 }
 588
 589
 590 /**
 591  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
 592  *  @hw: pointer to hardware structure
 593  *  @speed: new link speed
 594  *  @autoneg: true if auto-negotiation enabled
 595  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 596  *
 597  *  Set the link speed in the AUTOC register and restarts link.
 598  **/
 599 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
 600                                            ixgbe_link_speed speed, bool autoneg,
 601                                            bool autoneg_wait_to_complete)
 602 {
 603         s32              status            = 0;
 604         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 605         u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 606         u32              autoc             = curr_autoc;
 607         u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
 608
 609         /* Check to see if speed passed in is supported. */
 610         ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
 611         speed &= link_capabilities;
 612
 613         if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 614                 status = IXGBE_ERR_LINK_SETUP;
 615
 616         /* Set KX4/KX support according to speed requested */
 617         else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
 618                  link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 619                 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 620                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 621                         autoc |= IXGBE_AUTOC_KX4_SUPP;
 622                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 623                         autoc |= IXGBE_AUTOC_KX_SUPP;
 624                 if (autoc != curr_autoc)
 625                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 626         }
 627
 628         if (status == 0) {
 629                 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
 630
 631                 /*
 632                  * Setup and restart the link based on the new values in
 633                  * ixgbe_hw This will write the AUTOC register based on the new
 634                  * stored values
 635                  */
 636                 status = ixgbe_setup_mac_link_82598(hw);
 637         }
 638
 639         return status;
 640 }
 641
 642
 643 /**
 644  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
 645  *  @hw: pointer to hardware structure
 646  *
 647  *  Configures link settings based on values in the ixgbe_hw struct.
 648  *  Restarts the link.  Performs autonegotiation if needed.  Restart
 649  *  phy and wait for autonegotiate to finish.  Then synchronize the
 650  *  MAC and PHY.
 651  **/
 652 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
 653 {
 654         s32 status;
 655
 656         /* Restart autonegotiation on PHY */
 657         status = hw->phy.ops.setup_link(hw);
 658
 659         /* Set up MAC */
 660         ixgbe_setup_mac_link_82598(hw);
 661
 662         return status;
 663 }
 664
 665 /**
 666  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
 667  *  @hw: pointer to hardware structure
 668  *  @speed: new link speed
 669  *  @autoneg: true if autonegotiation enabled
 670  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 671  *
 672  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
 673  **/
 674 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
 675                                                ixgbe_link_speed speed,
 676                                                bool autoneg,
 677                                                bool autoneg_wait_to_complete)
 678 {
 679         s32 status;
 680
 681         /* Setup the PHY according to input speed */
 682         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 683                                               autoneg_wait_to_complete);
 684
 685         /* Set up MAC */
 686         ixgbe_setup_mac_link_82598(hw);
 687
 688         return status;
 689 }
 690
 691 /**
 692  *  ixgbe_reset_hw_82598 - Performs hardware reset
 693  *  @hw: pointer to hardware structure
 694  *
 695  *  Resets the hardware by resetting the transmit and receive units, masks and
 696  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
 697  *  reset.
 698  **/
 699 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 700 {
 701         s32 status = 0;
 702         u32 ctrl;
 703         u32 gheccr;
 704         u32 i;
 705         u32 autoc;
 706         u8  analog_val;
 707
 708         /* Call adapter stop to disable tx/rx and clear interrupts */
 709         hw->mac.ops.stop_adapter(hw);
 710
 711         /*
 712          * Power up the Atlas Tx lanes if they are currently powered down.
 713          * Atlas Tx lanes are powered down for MAC loopback tests, but
 714          * they are not automatically restored on reset.
 715          */
 716         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
 717         if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
 718                 /* Enable Tx Atlas so packets can be transmitted again */
 719                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 720                                              &analog_val);
 721                 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
 722                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 723                                               analog_val);
 724
 725                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 726                                              &analog_val);
 727                 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
 728                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 729                                               analog_val);
 730
 731                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 732                                              &analog_val);
 733                 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
 734                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 735                                               analog_val);
 736
 737                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 738                                              &analog_val);
 739                 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
 740                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 741                                               analog_val);
 742         }
 743
 744         /* Reset PHY */
 745         if (hw->phy.reset_disable == false) {
 746                 /* PHY ops must be identified and initialized prior to reset */
 747
 748                 /* Init PHY and function pointers, perform SFP setup */
 749                 status = hw->phy.ops.init(hw);
 750                 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 751                         goto reset_hw_out;
 752
 753                 hw->phy.ops.reset(hw);
 754         }
 755
 756         /*
 757          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 758          * access and verify no pending requests before reset
 759          */
 760         status = ixgbe_disable_pcie_master(hw);
 761         if (status != 0) {
 762                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 763                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 764         }
 765
 766         /*
 767          * Issue global reset to the MAC.  This needs to be a SW reset.
 768          * If link reset is used, it might reset the MAC when mng is using it
 769          */
 770         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 771         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 772         IXGBE_WRITE_FLUSH(hw);
 773
 774         /* Poll for reset bit to self-clear indicating reset is complete */
 775         for (i = 0; i < 10; i++) {
 776                 udelay(1);
 777                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 778                 if (!(ctrl & IXGBE_CTRL_RST))
 779                         break;
 780         }
 781         if (ctrl & IXGBE_CTRL_RST) {
 782                 status = IXGBE_ERR_RESET_FAILED;
 783                 hw_dbg(hw, "Reset polling failed to complete.\n");
 784         }
 785
 786         msleep(50);
 787
 788         gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
 789         gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
 790         IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
 791
 792         /*
 793          * Store the original AUTOC value if it has not been
 794          * stored off yet.  Otherwise restore the stored original
 795          * AUTOC value since the reset operation sets back to deaults.
 796          */
 797         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 798         if (hw->mac.orig_link_settings_stored == false) {
 799                 hw->mac.orig_autoc = autoc;
 800                 hw->mac.orig_link_settings_stored = true;
 801         } else if (autoc != hw->mac.orig_autoc) {
 802                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 803         }
 804
 805         /* Store the permanent mac address */
 806         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 807
 808 reset_hw_out:
 809         return status;
 810 }
 811
 812 /**
 813  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
 814  *  @hw: pointer to hardware struct
 815  *  @rar: receive address register index to associate with a VMDq index
 816  *  @vmdq: VMDq set index
 817  **/
 818 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 819 {
 820         u32 rar_high;
 821
 822         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 823         rar_high &= ~IXGBE_RAH_VIND_MASK;
 824         rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
 825         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 826         return 0;
 827 }
 828
 829 /**
 830  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
 831  *  @hw: pointer to hardware struct
 832  *  @rar: receive address register index to associate with a VMDq index
 833  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
 834  **/
 835 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 836 {
 837         u32 rar_high;
 838         u32 rar_entries = hw->mac.num_rar_entries;
 839
 840         if (rar < rar_entries) {
 841                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 842                 if (rar_high & IXGBE_RAH_VIND_MASK) {
 843                         rar_high &= ~IXGBE_RAH_VIND_MASK;
 844                         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 845                 }
 846         } else {
 847                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 848         }
 849
 850         return 0;
 851 }
 852
 853 /**
 854  *  ixgbe_set_vfta_82598 - Set VLAN filter table
 855  *  @hw: pointer to hardware structure
 856  *  @vlan: VLAN id to write to VLAN filter
 857  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
 858  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
 859  *
 860  *  Turn on/off specified VLAN in the VLAN filter table.
 861  **/
 862 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 863                                 bool vlan_on)
 864 {
 865         u32 regindex;
 866         u32 bitindex;
 867         u32 bits;
 868         u32 vftabyte;
 869
 870         if (vlan > 4095)
 871                 return IXGBE_ERR_PARAM;
 872
 873         /* Determine 32-bit word position in array */
 874         regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
 875
 876         /* Determine the location of the (VMD) queue index */
 877         vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
 878         bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
 879
 880         /* Set the nibble for VMD queue index */
 881         bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
 882         bits &= (~(0x0F << bitindex));
 883         bits |= (vind << bitindex);
 884         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
 885
 886         /* Determine the location of the bit for this VLAN id */
 887         bitindex = vlan & 0x1F;   /* lower five bits */
 888
 889         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 890         if (vlan_on)
 891                 /* Turn on this VLAN id */
 892                 bits |= (1 << bitindex);
 893         else
 894                 /* Turn off this VLAN id */
 895                 bits &= ~(1 << bitindex);
 896         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 897
 898         return 0;
 899 }
 900
 901 /**
 902  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
 903  *  @hw: pointer to hardware structure
 904  *
 905  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 906  **/
 907 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
 908 {
 909         u32 offset;
 910         u32 vlanbyte;
 911
 912         for (offset = 0; offset < hw->mac.vft_size; offset++)
 913                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 914
 915         for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
 916                 for (offset = 0; offset < hw->mac.vft_size; offset++)
 917                         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
 918                                         0);
 919
 920         return 0;
 921 }
 922
 923 /**
 924  *  ixgbe_blink_led_start_82598 - Blink LED based on index.
 925  *  @hw: pointer to hardware structure
 926  *  @index: led number to blink
 927  **/
 928 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
 929 {
 930         ixgbe_link_speed speed = 0;
 931         bool link_up = 0;
 932         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 933         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 934
 935         /*
 936          * Link must be up to auto-blink the LEDs on the 82598EB MAC;
 937          * force it if link is down.
 938          */
 939         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 940
 941         if (!link_up) {
 942                 autoc_reg |= IXGBE_AUTOC_FLU;
 943                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 944                 msleep(10);
 945         }
 946
 947         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 948         led_reg |= IXGBE_LED_BLINK(index);
 949         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 950         IXGBE_WRITE_FLUSH(hw);
 951
 952         return 0;
 953 }
 954
 955 /**
 956  *  ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
 957  *  @hw: pointer to hardware structure
 958  *  @index: led number to stop blinking
 959  **/
 960 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
 961 {
 962         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 963         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 964
 965         autoc_reg &= ~IXGBE_AUTOC_FLU;
 966         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 967         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 968
 969         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 970         led_reg &= ~IXGBE_LED_BLINK(index);
 971         led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 972         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 973         IXGBE_WRITE_FLUSH(hw);
 974
 975         return 0;
 976 }
 977
 978 /**
 979  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
 980  *  @hw: pointer to hardware structure
 981  *  @reg: analog register to read
 982  *  @val: read value
 983  *
 984  *  Performs read operation to Atlas analog register specified.
 985  **/
 986 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
 987 {
 988         u32  atlas_ctl;
 989
 990         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
 991                         IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 992         IXGBE_WRITE_FLUSH(hw);
 993         udelay(10);
 994         atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 995         *val = (u8)atlas_ctl;
 996
 997         return 0;
 998 }
 999
1000 /**
1001  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1002  *  @hw: pointer to hardware structure
1003  *  @reg: atlas register to write
1004  *  @val: value to write
1005  *
1006  *  Performs write operation to Atlas analog register specified.
1007  **/
1008 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1009 {
1010         u32  atlas_ctl;
1011
1012         atlas_ctl = (reg << 8) | val;
1013         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1014         IXGBE_WRITE_FLUSH(hw);
1015         udelay(10);
1016
1017         return 0;
1018 }
1019
1020 /**
1021  *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
1022  *  over I2C interface through an intermediate phy.
1023  *  @hw: pointer to hardware structure
1024  *  @byte_offset: EEPROM byte offset to read
1025  *  @eeprom_data: value read
1026  *
1027  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1028  **/
1029 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1030                                        u8 *eeprom_data)
1031 {
1032         s32 status = 0;
1033         u16 sfp_addr = 0;
1034         u16 sfp_data = 0;
1035         u16 sfp_stat = 0;
1036         u32 i;
1037
1038         if (hw->phy.type == ixgbe_phy_nl) {
1039                 /*
1040                  * phy SDA/SCL registers are at addresses 0xC30A to
1041                  * 0xC30D.  These registers are used to talk to the SFP+
1042                  * module's EEPROM through the SDA/SCL (I2C) interface.
1043                  */
1044                 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1045                 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1046                 hw->phy.ops.write_reg(hw,
1047                                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1048                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1049                                       sfp_addr);
1050
1051                 /* Poll status */
1052                 for (i = 0; i < 100; i++) {
1053                         hw->phy.ops.read_reg(hw,
1054                                              IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1055                                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1056                                              &sfp_stat);
1057                         sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1058                         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1059                                 break;
1060                         msleep(10);
1061                 }
1062
1063                 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1064                         hw_dbg(hw, "EEPROM read did not pass.\n");
1065                         status = IXGBE_ERR_SFP_NOT_PRESENT;
1066                         goto out;
1067                 }
1068
1069                 /* Read data */
1070                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1071                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1072
1073                 *eeprom_data = (u8)(sfp_data >> 8);
1074         } else {
1075                 status = IXGBE_ERR_PHY;
1076                 goto out;
1077         }
1078
1079 out:
1080         return status;
1081 }
1082
1083 /**
1084  *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1085  *  @hw: pointer to hardware structure
1086  *
1087  *  Determines physical layer capabilities of the current configuration.
1088  **/
1089 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1090 {
1091         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1092
1093         switch (hw->device_id) {
1094         case IXGBE_DEV_ID_82598:
1095                 /* Default device ID is mezzanine card KX/KX4 */
1096                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1097                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1098                 break;
1099         case IXGBE_DEV_ID_82598_BX:
1100                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1101         case IXGBE_DEV_ID_82598EB_CX4:
1102         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1103                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1104                 break;
1105         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1106                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1107                 break;
1108         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1109         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1110         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1111                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1112                 break;
1113         case IXGBE_DEV_ID_82598EB_XF_LR:
1114                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1115                 break;
1116         case IXGBE_DEV_ID_82598AT:
1117                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1118                                   IXGBE_PHYSICAL_LAYER_1000BASE_T);
1119                 break;
1120         case IXGBE_DEV_ID_82598EB_SFP_LOM:
1121                 hw->phy.ops.identify_sfp(hw);
1122
1123                 switch (hw->phy.sfp_type) {
1124                 case ixgbe_sfp_type_da_cu:
1125                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1126                         break;
1127                 case ixgbe_sfp_type_sr:
1128                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1129                         break;
1130                 case ixgbe_sfp_type_lr:
1131                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1132                         break;
1133                 default:
1134                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1135                         break;
1136                 }
1137                 break;
1138
1139         default:
1140                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1141                 break;
1142         }
1143
1144         return physical_layer;
1145 }
1146
1147 static struct ixgbe_mac_operations mac_ops_82598 = {
1148         .init_hw                = &ixgbe_init_hw_generic,
1149         .reset_hw               = &ixgbe_reset_hw_82598,
1150         .start_hw               = &ixgbe_start_hw_generic,
1151         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1152         .get_media_type         = &ixgbe_get_media_type_82598,
1153         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1154         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
1155         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1156         .stop_adapter           = &ixgbe_stop_adapter_generic,
1157         .get_bus_info           = &ixgbe_get_bus_info_generic,
1158         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1159         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
1160         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
1161         .setup_link             = &ixgbe_setup_mac_link_82598,
1162         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82598,
1163         .check_link             = &ixgbe_check_mac_link_82598,
1164         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1165         .led_on                 = &ixgbe_led_on_generic,
1166         .led_off                = &ixgbe_led_off_generic,
1167         .blink_led_start        = &ixgbe_blink_led_start_82598,
1168         .blink_led_stop         = &ixgbe_blink_led_stop_82598,
1169         .set_rar                = &ixgbe_set_rar_generic,
1170         .clear_rar              = &ixgbe_clear_rar_generic,
1171         .set_vmdq               = &ixgbe_set_vmdq_82598,
1172         .clear_vmdq             = &ixgbe_clear_vmdq_82598,
1173         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1174         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1175         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1176         .enable_mc              = &ixgbe_enable_mc_generic,
1177         .disable_mc             = &ixgbe_disable_mc_generic,
1178         .clear_vfta             = &ixgbe_clear_vfta_82598,
1179         .set_vfta               = &ixgbe_set_vfta_82598,
1180         .setup_fc               = &ixgbe_setup_fc_82598,
1181 };
1182
1183 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1184         .init_params            = &ixgbe_init_eeprom_params_generic,
1185         .read                   = &ixgbe_read_eeprom_generic,
1186         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1187         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1188 };
1189
1190 static struct ixgbe_phy_operations phy_ops_82598 = {
1191         .identify               = &ixgbe_identify_phy_generic,
1192         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1193         .init                   = &ixgbe_init_phy_ops_82598,
1194         .reset                  = &ixgbe_reset_phy_generic,
1195         .read_reg               = &ixgbe_read_phy_reg_generic,
1196         .write_reg              = &ixgbe_write_phy_reg_generic,
1197         .setup_link             = &ixgbe_setup_phy_link_generic,
1198         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1199         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_82598,
1200 };
1201
1202 struct ixgbe_info ixgbe_82598_info = {
1203         .mac                    = ixgbe_mac_82598EB,
1204         .get_invariants         = &ixgbe_get_invariants_82598,
1205         .mac_ops                = &mac_ops_82598,
1206         .eeprom_ops             = &eeprom_ops_82598,
1207         .phy_ops                = &phy_ops_82598,
1208 };
1209