drivers/net/ixgbe/ixgbe_82599.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82599_MAX_TX_QUEUES 128
  36 #define IXGBE_82599_MAX_RX_QUEUES 128
  37 #define IXGBE_82599_RAR_ENTRIES   128
  38 #define IXGBE_82599_MC_TBL_SIZE   128
  39 #define IXGBE_82599_VFT_TBL_SIZE  128
  40
  41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
  42                                       ixgbe_link_speed *speed,
  43                                       bool *autoneg);
  44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
  45 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
  46 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
  47                                      ixgbe_link_speed speed, bool autoneg,
  48                                      bool autoneg_wait_to_complete);
  49 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
  50 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
  51                                ixgbe_link_speed *speed,
  52                                bool *link_up, bool link_up_wait_to_complete);
  53 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
  54                                      ixgbe_link_speed speed,
  55                                      bool autoneg,
  56                                      bool autoneg_wait_to_complete);
  57 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
  58                                              ixgbe_link_speed *speed,
  59                                              bool *autoneg);
  60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
  61 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
  62                                                ixgbe_link_speed speed,
  63                                                bool autoneg,
  64                                                bool autoneg_wait_to_complete);
  65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
  66 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  67 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
  68 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
  69                          u32 vind, bool vlan_on);
  70 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
  71 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
  72 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
  73 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
  74 s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
  75 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
  76 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
  77 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
  78
  79 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
  80 {
  81         struct ixgbe_mac_info *mac = &hw->mac;
  82         if (hw->phy.multispeed_fiber) {
  83                 /* Set up dual speed SFP+ support */
  84                 mac->ops.setup_link =
  85                           &ixgbe_setup_mac_link_multispeed_fiber;
  86                 mac->ops.setup_link_speed =
  87                           &ixgbe_setup_mac_link_speed_multispeed_fiber;
  88         } else {
  89                 mac->ops.setup_link =
  90                           &ixgbe_setup_mac_link_82599;
  91                 mac->ops.setup_link_speed =
  92                           &ixgbe_setup_mac_link_speed_82599;
  93         }
  94 }
  95
  96 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
  97 {
  98         s32 ret_val = 0;
  99         u16 list_offset, data_offset, data_value;
 100
 101         if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
 102                 ixgbe_init_mac_link_ops_82599(hw);
 103
 104                 hw->phy.ops.reset = NULL;
 105
 106                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 107                                                               &data_offset);
 108
 109                 if (ret_val != 0)
 110                         goto setup_sfp_out;
 111
 112                 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 113                 while (data_value != 0xffff) {
 114                         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
 115                         IXGBE_WRITE_FLUSH(hw);
 116                         hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 117                 }
 118                 /* Now restart DSP */
 119                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
 120                 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
 121                 IXGBE_WRITE_FLUSH(hw);
 122         }
 123
 124 setup_sfp_out:
 125         return ret_val;
 126 }
 127
 128 /**
 129  *  ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
 130  *  @hw: pointer to hardware structure
 131  *
 132  *  Read PCIe configuration space, and get the MSI-X vector count from
 133  *  the capabilities table.
 134  **/
 135 u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
 136 {
 137         struct ixgbe_adapter *adapter = hw->back;
 138         u16 msix_count;
 139         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
 140                              &msix_count);
 141         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
 142
 143         /* MSI-X count is zero-based in HW, so increment to give proper value */
 144         msix_count++;
 145
 146         return msix_count;
 147 }
 148
 149 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
 150 {
 151         struct ixgbe_mac_info *mac = &hw->mac;
 152
 153         ixgbe_init_mac_link_ops_82599(hw);
 154
 155         mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
 156         mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
 157         mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
 158         mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
 159         mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
 160         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
 161
 162         return 0;
 163 }
 164
 165 /**
 166  *  ixgbe_init_phy_ops_82599 - PHY/SFP specific init
 167  *  @hw: pointer to hardware structure
 168  *
 169  *  Initialize any function pointers that were not able to be
 170  *  set during get_invariants because the PHY/SFP type was
 171  *  not known.  Perform the SFP init if necessary.
 172  *
 173  **/
 174 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
 175 {
 176         struct ixgbe_mac_info *mac = &hw->mac;
 177         struct ixgbe_phy_info *phy = &hw->phy;
 178         s32 ret_val = 0;
 179
 180         /* Identify the PHY or SFP module */
 181         ret_val = phy->ops.identify(hw);
 182
 183         /* Setup function pointers based on detected SFP module and speeds */
 184         ixgbe_init_mac_link_ops_82599(hw);
 185
 186         /* If copper media, overwrite with copper function pointers */
 187         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 188                 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
 189                 mac->ops.setup_link_speed =
 190                                      &ixgbe_setup_copper_link_speed_82599;
 191                 mac->ops.get_link_capabilities =
 192                                   &ixgbe_get_copper_link_capabilities_82599;
 193         }
 194
 195         /* Set necessary function pointers based on phy type */
 196         switch (hw->phy.type) {
 197         case ixgbe_phy_tn:
 198                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 199                 phy->ops.get_firmware_version =
 200                              &ixgbe_get_phy_firmware_version_tnx;
 201                 break;
 202         default:
 203                 break;
 204         }
 205
 206         return ret_val;
 207 }
 208
 209 /**
 210  *  ixgbe_get_link_capabilities_82599 - Determines link capabilities
 211  *  @hw: pointer to hardware structure
 212  *  @speed: pointer to link speed
 213  *  @negotiation: true when autoneg or autotry is enabled
 214  *
 215  *  Determines the link capabilities by reading the AUTOC register.
 216  **/
 217 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
 218                                       ixgbe_link_speed *speed,
 219                                       bool *negotiation)
 220 {
 221         s32 status = 0;
 222         u32 autoc = 0;
 223
 224         /*
 225          * Determine link capabilities based on the stored value of AUTOC,
 226          * which represents EEPROM defaults.  If AUTOC value has not been
 227          * stored, use the current register value.
 228          */
 229         if (hw->mac.orig_link_settings_stored)
 230                 autoc = hw->mac.orig_autoc;
 231         else
 232                 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 233
 234         switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 235         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 236                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 237                 *negotiation = false;
 238                 break;
 239
 240         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 241                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 242                 *negotiation = false;
 243                 break;
 244
 245         case IXGBE_AUTOC_LMS_1G_AN:
 246                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 247                 *negotiation = true;
 248                 break;
 249
 250         case IXGBE_AUTOC_LMS_10G_SERIAL:
 251                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 252                 *negotiation = false;
 253                 break;
 254
 255         case IXGBE_AUTOC_LMS_KX4_KX_KR:
 256         case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
 257                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 258                 if (autoc & IXGBE_AUTOC_KR_SUPP)
 259                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 260                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
 261                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 262                 if (autoc & IXGBE_AUTOC_KX_SUPP)
 263                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 264                 *negotiation = true;
 265                 break;
 266
 267         case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
 268                 *speed = IXGBE_LINK_SPEED_100_FULL;
 269                 if (autoc & IXGBE_AUTOC_KR_SUPP)
 270                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 271                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
 272                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 273                 if (autoc & IXGBE_AUTOC_KX_SUPP)
 274                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 275                 *negotiation = true;
 276                 break;
 277
 278         case IXGBE_AUTOC_LMS_SGMII_1G_100M:
 279                 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
 280                 *negotiation = false;
 281                 break;
 282
 283         default:
 284                 status = IXGBE_ERR_LINK_SETUP;
 285                 goto out;
 286                 break;
 287         }
 288
 289         if (hw->phy.multispeed_fiber) {
 290                 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
 291                           IXGBE_LINK_SPEED_1GB_FULL;
 292                 *negotiation = true;
 293         }
 294
 295 out:
 296         return status;
 297 }
 298
 299 /**
 300  *  ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
 301  *  @hw: pointer to hardware structure
 302  *  @speed: pointer to link speed
 303  *  @autoneg: boolean auto-negotiation value
 304  *
 305  *  Determines the link capabilities by reading the AUTOC register.
 306  **/
 307 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
 308                                                     ixgbe_link_speed *speed,
 309                                                     bool *autoneg)
 310 {
 311         s32 status = IXGBE_ERR_LINK_SETUP;
 312         u16 speed_ability;
 313
 314         *speed = 0;
 315         *autoneg = true;
 316
 317         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 318                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 319                                       &speed_ability);
 320
 321         if (status == 0) {
 322                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 323                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 324                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 325                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 326         }
 327
 328         return status;
 329 }
 330
 331 /**
 332  *  ixgbe_get_media_type_82599 - Get media type
 333  *  @hw: pointer to hardware structure
 334  *
 335  *  Returns the media type (fiber, copper, backplane)
 336  **/
 337 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
 338 {
 339         enum ixgbe_media_type media_type;
 340
 341         /* Detect if there is a copper PHY attached. */
 342         if (hw->phy.type == ixgbe_phy_cu_unknown ||
 343             hw->phy.type == ixgbe_phy_tn) {
 344                 media_type = ixgbe_media_type_copper;
 345                 goto out;
 346         }
 347
 348         switch (hw->device_id) {
 349         case IXGBE_DEV_ID_82599:
 350         case IXGBE_DEV_ID_82599_KX4:
 351                 /* Default device ID is mezzanine card KX/KX4 */
 352                 media_type = ixgbe_media_type_backplane;
 353                 break;
 354         case IXGBE_DEV_ID_82599_SFP:
 355                 media_type = ixgbe_media_type_fiber;
 356                 break;
 357         default:
 358                 media_type = ixgbe_media_type_unknown;
 359                 break;
 360         }
 361 out:
 362         return media_type;
 363 }
 364
 365 /**
 366  *  ixgbe_setup_mac_link_82599 - Setup MAC link settings
 367  *  @hw: pointer to hardware structure
 368  *
 369  *  Configures link settings based on values in the ixgbe_hw struct.
 370  *  Restarts the link.  Performs autonegotiation if needed.
 371  **/
 372 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
 373 {
 374         u32 autoc_reg;
 375         u32 links_reg;
 376         u32 i;
 377         s32 status = 0;
 378
 379         /* Restart link */
 380         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 381         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 382         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 383
 384         /* Only poll for autoneg to complete if specified to do so */
 385         if (hw->phy.autoneg_wait_to_complete) {
 386                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 387                      IXGBE_AUTOC_LMS_KX4_KX_KR ||
 388                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 389                      IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 390                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 391                      IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 392                         links_reg = 0; /* Just in case Autoneg time = 0 */
 393                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 394                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 395                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 396                                         break;
 397                                 msleep(100);
 398                         }
 399                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 400                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 401                                 hw_dbg(hw, "Autoneg did not complete.\n");
 402                         }
 403                 }
 404         }
 405
 406         /* Set up flow control */
 407         status = ixgbe_setup_fc_generic(hw, 0);
 408
 409         /* Add delay to filter out noises during initial link setup */
 410         msleep(50);
 411
 412         return status;
 413 }
 414
 415 /**
 416  *  ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
 417  *  @hw: pointer to hardware structure
 418  *
 419  *  Configures link settings based on values in the ixgbe_hw struct.
 420  *  Restarts the link for multi-speed fiber at 1G speed, if link
 421  *  fails at 10G.
 422  *  Performs autonegotiation if needed.
 423  **/
 424 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
 425 {
 426         s32 status = 0;
 427         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
 428         status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
 429                                                              true, true);
 430         return status;
 431 }
 432
 433 /**
 434  *  ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
 435  *  @hw: pointer to hardware structure
 436  *  @speed: new link speed
 437  *  @autoneg: true if autonegotiation enabled
 438  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 439  *
 440  *  Set the link speed in the AUTOC register and restarts link.
 441  **/
 442 s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
 443                                                 ixgbe_link_speed speed,
 444                                                 bool autoneg,
 445                                                 bool autoneg_wait_to_complete)
 446 {
 447         s32 status = 0;
 448         ixgbe_link_speed phy_link_speed;
 449         ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 450         u32 speedcnt = 0;
 451         u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 452         bool link_up = false;
 453         bool negotiation;
 454
 455         /* Mask off requested but non-supported speeds */
 456         hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
 457         speed &= phy_link_speed;
 458
 459         /*
 460          * Try each speed one by one, highest priority first.  We do this in
 461          * software because 10gb fiber doesn't support speed autonegotiation.
 462          */
 463         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 464                 speedcnt++;
 465                 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
 466
 467                 /* Set hardware SDP's */
 468                 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
 469                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 470
 471                 ixgbe_setup_mac_link_speed_82599(hw,
 472                                                  IXGBE_LINK_SPEED_10GB_FULL,
 473                                                  autoneg,
 474                                                  autoneg_wait_to_complete);
 475
 476                 msleep(50);
 477
 478                 /* If we have link, just jump out */
 479                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
 480                 if (link_up)
 481                         goto out;
 482         }
 483
 484         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 485                 speedcnt++;
 486                 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
 487                         highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
 488
 489                 /* Set hardware SDP's */
 490                 esdp_reg &= ~IXGBE_ESDP_SDP5;
 491                 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
 492                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 493
 494                 ixgbe_setup_mac_link_speed_82599(
 495                         hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
 496                         autoneg_wait_to_complete);
 497
 498                 msleep(50);
 499
 500                 /* If we have link, just jump out */
 501                 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
 502                 if (link_up)
 503                         goto out;
 504         }
 505
 506         /*
 507          * We didn't get link.  Configure back to the highest speed we tried,
 508          * (if there was more than one).  We call ourselves back with just the
 509          * single highest speed that the user requested.
 510          */
 511         if (speedcnt > 1)
 512                 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
 513                                                      highest_link_speed,
 514                                                      autoneg,
 515                                                      autoneg_wait_to_complete);
 516
 517 out:
 518         return status;
 519 }
 520
 521 /**
 522  *  ixgbe_check_mac_link_82599 - Determine link and speed status
 523  *  @hw: pointer to hardware structure
 524  *  @speed: pointer to link speed
 525  *  @link_up: true when link is up
 526  *  @link_up_wait_to_complete: bool used to wait for link up or not
 527  *
 528  *  Reads the links register to determine if link is up and the current speed
 529  **/
 530 s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 531                                bool *link_up, bool link_up_wait_to_complete)
 532 {
 533         u32 links_reg;
 534         u32 i;
 535
 536         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 537         if (link_up_wait_to_complete) {
 538                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 539                         if (links_reg & IXGBE_LINKS_UP) {
 540                                 *link_up = true;
 541                                 break;
 542                         } else {
 543                                 *link_up = false;
 544                         }
 545                         msleep(100);
 546                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 547                 }
 548         } else {
 549                 if (links_reg & IXGBE_LINKS_UP)
 550                         *link_up = true;
 551                 else
 552                         *link_up = false;
 553         }
 554
 555         if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 556             IXGBE_LINKS_SPEED_10G_82599)
 557                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 558         else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 559                  IXGBE_LINKS_SPEED_1G_82599)
 560                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 561         else
 562                 *speed = IXGBE_LINK_SPEED_100_FULL;
 563
 564
 565         return 0;
 566 }
 567
 568 /**
 569  *  ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
 570  *  @hw: pointer to hardware structure
 571  *  @speed: new link speed
 572  *  @autoneg: true if autonegotiation enabled
 573  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 574  *
 575  *  Set the link speed in the AUTOC register and restarts link.
 576  **/
 577 s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
 578                                      ixgbe_link_speed speed, bool autoneg,
 579                                      bool autoneg_wait_to_complete)
 580 {
 581         s32 status = 0;
 582         u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 583         u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 584         u32 orig_autoc = 0;
 585         u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
 586         u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
 587         u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
 588         u32 links_reg;
 589         u32 i;
 590         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 591
 592         /* Check to see if speed passed in is supported. */
 593         hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
 594         speed &= link_capabilities;
 595
 596         /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
 597         if (hw->mac.orig_link_settings_stored)
 598                 orig_autoc = hw->mac.orig_autoc;
 599         else
 600                 orig_autoc = autoc;
 601
 602
 603         if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
 604                 status = IXGBE_ERR_LINK_SETUP;
 605         } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 606                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 607                    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 608                 /* Set KX4/KX/KR support according to speed requested */
 609                 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
 610                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 611                         if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 612                                 autoc |= IXGBE_AUTOC_KX4_SUPP;
 613                         if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
 614                                 autoc |= IXGBE_AUTOC_KR_SUPP;
 615                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 616                         autoc |= IXGBE_AUTOC_KX_SUPP;
 617         } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
 618                    (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
 619                     link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
 620                 /* Switch from 1G SFI to 10G SFI if requested */
 621                 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
 622                     (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
 623                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
 624                         autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
 625                 }
 626         } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
 627                    (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
 628                 /* Switch from 10G SFI to 1G SFI if requested */
 629                 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
 630                     (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
 631                         autoc &= ~IXGBE_AUTOC_LMS_MASK;
 632                         if (autoneg)
 633                                 autoc |= IXGBE_AUTOC_LMS_1G_AN;
 634                         else
 635                                 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
 636                 }
 637         }
 638
 639         if (status == 0) {
 640                 /* Restart link */
 641                 autoc |= IXGBE_AUTOC_AN_RESTART;
 642                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 643
 644                 /* Only poll for autoneg to complete if specified to do so */
 645                 if (autoneg_wait_to_complete) {
 646                         if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 647                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 648                             link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 649                                 links_reg = 0; /*Just in case Autoneg time=0*/
 650                                 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 651                                         links_reg =
 652                                                IXGBE_READ_REG(hw, IXGBE_LINKS);
 653                                         if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 654                                                 break;
 655                                         msleep(100);
 656                                 }
 657                                 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 658                                         status =
 659                                                 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 660                                         hw_dbg(hw, "Autoneg did not "
 661                                                "complete.\n");
 662                                 }
 663                         }
 664                 }
 665
 666                 /* Set up flow control */
 667                 status = ixgbe_setup_fc_generic(hw, 0);
 668
 669                 /* Add delay to filter out noises during initial link setup */
 670                 msleep(50);
 671         }
 672
 673         return status;
 674 }
 675
 676 /**
 677  *  ixgbe_setup_copper_link_82599 - Setup copper link settings
 678  *  @hw: pointer to hardware structure
 679  *
 680  *  Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
 681  **/
 682 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
 683 {
 684         s32 status;
 685
 686         /* Restart autonegotiation on PHY */
 687         status = hw->phy.ops.setup_link(hw);
 688
 689         /* Set up MAC */
 690         ixgbe_setup_mac_link_82599(hw);
 691
 692         return status;
 693 }
 694
 695 /**
 696  *  ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
 697  *  @hw: pointer to hardware structure
 698  *  @speed: new link speed
 699  *  @autoneg: true if autonegotiation enabled
 700  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 701  *
 702  *  Restarts link on PHY and MAC based on settings passed in.
 703  **/
 704 static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
 705                                                ixgbe_link_speed speed,
 706                                                bool autoneg,
 707                                                bool autoneg_wait_to_complete)
 708 {
 709         s32 status;
 710
 711         /* Setup the PHY according to input speed */
 712         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 713                                               autoneg_wait_to_complete);
 714         /* Set up MAC */
 715         ixgbe_setup_mac_link_82599(hw);
 716
 717         return status;
 718 }
 719
 720 /**
 721  *  ixgbe_reset_hw_82599 - Perform hardware reset
 722  *  @hw: pointer to hardware structure
 723  *
 724  *  Resets the hardware by resetting the transmit and receive units, masks
 725  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
 726  *  reset.
 727  **/
 728 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
 729 {
 730         s32 status = 0;
 731         u32 ctrl, ctrl_ext;
 732         u32 i;
 733         u32 autoc;
 734         u32 autoc2;
 735
 736         /* Call adapter stop to disable tx/rx and clear interrupts */
 737         hw->mac.ops.stop_adapter(hw);
 738
 739         /* PHY ops must be identified and initialized prior to reset */
 740
 741         /* Init PHY and function pointers, perform SFP setup */
 742         status = hw->phy.ops.init(hw);
 743
 744         if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 745                 goto reset_hw_out;
 746
 747         /* Setup SFP module if there is one present. */
 748         if (hw->phy.sfp_setup_needed) {
 749                 status = hw->mac.ops.setup_sfp(hw);
 750                 hw->phy.sfp_setup_needed = false;
 751         }
 752
 753         /* Reset PHY */
 754         if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
 755                 hw->phy.ops.reset(hw);
 756
 757         /*
 758          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 759          * access and verify no pending requests before reset
 760          */
 761         status = ixgbe_disable_pcie_master(hw);
 762         if (status != 0) {
 763                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 764                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 765         }
 766
 767         /*
 768          * Issue global reset to the MAC.  This needs to be a SW reset.
 769          * If link reset is used, it might reset the MAC when mng is using it
 770          */
 771         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 772         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 773         IXGBE_WRITE_FLUSH(hw);
 774
 775         /* Poll for reset bit to self-clear indicating reset is complete */
 776         for (i = 0; i < 10; i++) {
 777                 udelay(1);
 778                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 779                 if (!(ctrl & IXGBE_CTRL_RST))
 780                         break;
 781         }
 782         if (ctrl & IXGBE_CTRL_RST) {
 783                 status = IXGBE_ERR_RESET_FAILED;
 784                 hw_dbg(hw, "Reset polling failed to complete.\n");
 785         }
 786         /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
 787         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 788         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 789         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 790
 791         msleep(50);
 792
 793
 794
 795         /*
 796          * Store the original AUTOC/AUTOC2 values if they have not been
 797          * stored off yet.  Otherwise restore the stored original
 798          * values since the reset operation sets back to defaults.
 799          */
 800         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 801         autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 802         if (hw->mac.orig_link_settings_stored == false) {
 803                 hw->mac.orig_autoc = autoc;
 804                 hw->mac.orig_autoc2 = autoc2;
 805                 hw->mac.orig_link_settings_stored = true;
 806         } else {
 807                 if (autoc != hw->mac.orig_autoc)
 808                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
 809                                         IXGBE_AUTOC_AN_RESTART));
 810
 811                 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
 812                     (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
 813                         autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
 814                         autoc2 |= (hw->mac.orig_autoc2 &
 815                                    IXGBE_AUTOC2_UPPER_MASK);
 816                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 817                 }
 818         }
 819
 820         /* Store the permanent mac address */
 821         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 822
 823 reset_hw_out:
 824         return status;
 825 }
 826
 827 /**
 828  *  ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
 829  *  @hw: pointer to hardware struct
 830  *  @rar: receive address register index to disassociate
 831  *  @vmdq: VMDq pool index to remove from the rar
 832  **/
 833 s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 834 {
 835         u32 mpsar_lo, mpsar_hi;
 836         u32 rar_entries = hw->mac.num_rar_entries;
 837
 838         if (rar < rar_entries) {
 839                 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 840                 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 841
 842                 if (!mpsar_lo && !mpsar_hi)
 843                         goto done;
 844
 845                 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
 846                         if (mpsar_lo) {
 847                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
 848                                 mpsar_lo = 0;
 849                         }
 850                         if (mpsar_hi) {
 851                                 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
 852                                 mpsar_hi = 0;
 853                         }
 854                 } else if (vmdq < 32) {
 855                         mpsar_lo &= ~(1 << vmdq);
 856                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
 857                 } else {
 858                         mpsar_hi &= ~(1 << (vmdq - 32));
 859                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
 860                 }
 861
 862                 /* was that the last pool using this rar? */
 863                 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
 864                         hw->mac.ops.clear_rar(hw, rar);
 865         } else {
 866                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 867         }
 868
 869 done:
 870         return 0;
 871 }
 872
 873 /**
 874  *  ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
 875  *  @hw: pointer to hardware struct
 876  *  @rar: receive address register index to associate with a VMDq index
 877  *  @vmdq: VMDq pool index
 878  **/
 879 s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 880 {
 881         u32 mpsar;
 882         u32 rar_entries = hw->mac.num_rar_entries;
 883
 884         if (rar < rar_entries) {
 885                 if (vmdq < 32) {
 886                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 887                         mpsar |= 1 << vmdq;
 888                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
 889                 } else {
 890                         mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 891                         mpsar |= 1 << (vmdq - 32);
 892                         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
 893                 }
 894         } else {
 895                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 896         }
 897         return 0;
 898 }
 899
 900 /**
 901  *  ixgbe_set_vfta_82599 - Set VLAN filter table
 902  *  @hw: pointer to hardware structure
 903  *  @vlan: VLAN id to write to VLAN filter
 904  *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
 905  *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
 906  *
 907  *  Turn on/off specified VLAN in the VLAN filter table.
 908  **/
 909 s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 910                          bool vlan_on)
 911 {
 912         u32 regindex;
 913         u32 bitindex;
 914         u32 bits;
 915         u32 first_empty_slot;
 916
 917         if (vlan > 4095)
 918                 return IXGBE_ERR_PARAM;
 919
 920         /*
 921          * this is a 2 part operation - first the VFTA, then the
 922          * VLVF and VLVFB if vind is set
 923          */
 924
 925         /* Part 1
 926          * The VFTA is a bitstring made up of 128 32-bit registers
 927          * that enable the particular VLAN id, much like the MTA:
 928          *    bits[11-5]: which register
 929          *    bits[4-0]:  which bit in the register
 930          */
 931         regindex = (vlan >> 5) & 0x7F;
 932         bitindex = vlan & 0x1F;
 933         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 934         if (vlan_on)
 935                 bits |= (1 << bitindex);
 936         else
 937                 bits &= ~(1 << bitindex);
 938         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 939
 940
 941         /* Part 2
 942          * If the vind is set
 943          *   Either vlan_on
 944          *     make sure the vlan is in VLVF
 945          *     set the vind bit in the matching VLVFB
 946          *   Or !vlan_on
 947          *     clear the pool bit and possibly the vind
 948          */
 949         if (vind) {
 950                 /* find the vlanid or the first empty slot */
 951                 first_empty_slot = 0;
 952
 953                 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
 954                         bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
 955                         if (!bits && !first_empty_slot)
 956                                 first_empty_slot = regindex;
 957                         else if ((bits & 0x0FFF) == vlan)
 958                                 break;
 959                 }
 960
 961                 if (regindex >= IXGBE_VLVF_ENTRIES) {
 962                         if (first_empty_slot)
 963                                 regindex = first_empty_slot;
 964                         else {
 965                                 hw_dbg(hw, "No space in VLVF.\n");
 966                                 goto out;
 967                         }
 968                 }
 969
 970                 if (vlan_on) {
 971                         /* set the pool bit */
 972                         if (vind < 32) {
 973                                 bits = IXGBE_READ_REG(hw,
 974                                                     IXGBE_VLVFB(regindex * 2));
 975                                 bits |= (1 << vind);
 976                                 IXGBE_WRITE_REG(hw,
 977                                               IXGBE_VLVFB(regindex * 2), bits);
 978                         } else {
 979                                 bits = IXGBE_READ_REG(hw,
 980                                               IXGBE_VLVFB((regindex * 2) + 1));
 981                                 bits |= (1 << vind);
 982                                 IXGBE_WRITE_REG(hw,
 983                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
 984                         }
 985                 } else {
 986                         /* clear the pool bit */
 987                         if (vind < 32) {
 988                                 bits = IXGBE_READ_REG(hw,
 989                                      IXGBE_VLVFB(regindex * 2));
 990                         bits &= ~(1 << vind);
 991                                 IXGBE_WRITE_REG(hw,
 992                                               IXGBE_VLVFB(regindex * 2), bits);
 993                                 bits |= IXGBE_READ_REG(hw,
 994                                               IXGBE_VLVFB((regindex * 2) + 1));
 995                         } else {
 996                                 bits = IXGBE_READ_REG(hw,
 997                                               IXGBE_VLVFB((regindex * 2) + 1));
 998                                 bits &= ~(1 << vind);
 999                                 IXGBE_WRITE_REG(hw,
1000                                         IXGBE_VLVFB((regindex * 2) + 1), bits);
1001                                 bits |= IXGBE_READ_REG(hw,
1002                                                     IXGBE_VLVFB(regindex * 2));
1003                         }
1004                 }
1005
1006                 if (bits)
1007                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1008                                         (IXGBE_VLVF_VIEN | vlan));
1009                 else
1010                         IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1011         }
1012
1013 out:
1014         return 0;
1015 }
1016
1017 /**
1018  *  ixgbe_clear_vfta_82599 - Clear VLAN filter table
1019  *  @hw: pointer to hardware structure
1020  *
1021  *  Clears the VLAN filer table, and the VMDq index associated with the filter
1022  **/
1023 s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1024 {
1025         u32 offset;
1026
1027         for (offset = 0; offset < hw->mac.vft_size; offset++)
1028                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1029
1030         for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1031                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1032                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1033                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1034         }
1035
1036         return 0;
1037 }
1038
1039 /**
1040  *  ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1041  *  @hw: pointer to hardware structure
1042  **/
1043 s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1044 {
1045         int i;
1046         hw_dbg(hw, " Clearing UTA\n");
1047
1048         for (i = 0; i < 128; i++)
1049                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1050
1051         return 0;
1052 }
1053
1054 /**
1055  *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1056  *  @hw: pointer to hardware structure
1057  *  @reg: analog register to read
1058  *  @val: read value
1059  *
1060  *  Performs read operation to Omer analog register specified.
1061  **/
1062 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1063 {
1064         u32  core_ctl;
1065
1066         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1067                         (reg << 8));
1068         IXGBE_WRITE_FLUSH(hw);
1069         udelay(10);
1070         core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1071         *val = (u8)core_ctl;
1072
1073         return 0;
1074 }
1075
1076 /**
1077  *  ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1078  *  @hw: pointer to hardware structure
1079  *  @reg: atlas register to write
1080  *  @val: value to write
1081  *
1082  *  Performs write operation to Omer analog register specified.
1083  **/
1084 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1085 {
1086         u32  core_ctl;
1087
1088         core_ctl = (reg << 8) | val;
1089         IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1090         IXGBE_WRITE_FLUSH(hw);
1091         udelay(10);
1092
1093         return 0;
1094 }
1095
1096 /**
1097  *  ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1098  *  @hw: pointer to hardware structure
1099  *
1100  *  Starts the hardware using the generic start_hw function.
1101  *  Then performs device-specific:
1102  *  Clears the rate limiter registers.
1103  **/
1104 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1105 {
1106         u32 q_num;
1107
1108         ixgbe_start_hw_generic(hw);
1109
1110         /* Clear the rate limiters */
1111         for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1112                 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1113                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1114         }
1115         IXGBE_WRITE_FLUSH(hw);
1116
1117         return 0;
1118 }
1119
1120 /**
1121  *  ixgbe_identify_phy_82599 - Get physical layer module
1122  *  @hw: pointer to hardware structure
1123  *
1124  *  Determines the physical layer module found on the current adapter.
1125  **/
1126 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1127 {
1128         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1129         status = ixgbe_identify_phy_generic(hw);
1130         if (status != 0)
1131                 status = ixgbe_identify_sfp_module_generic(hw);
1132         return status;
1133 }
1134
1135 /**
1136  *  ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1137  *  @hw: pointer to hardware structure
1138  *
1139  *  Determines physical layer capabilities of the current configuration.
1140  **/
1141 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1142 {
1143         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1144         u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1145         u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1146         u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1147         u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1148         u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1149         u16 ext_ability = 0;
1150         u8 comp_codes_10g = 0;
1151
1152         hw->phy.ops.identify(hw);
1153
1154         if (hw->phy.type == ixgbe_phy_tn ||
1155             hw->phy.type == ixgbe_phy_cu_unknown) {
1156                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1157                 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1158                 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1159                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1160                 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1161                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1162                 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1163                         physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1164                 goto out;
1165         }
1166
1167         switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1168         case IXGBE_AUTOC_LMS_1G_AN:
1169         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1170                 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1171                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1172                             IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1173                         goto out;
1174                 } else
1175                         /* SFI mode so read SFP module */
1176                         goto sfp_check;
1177                 break;
1178         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1179                 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1180                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1181                 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1182                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1183                 goto out;
1184                 break;
1185         case IXGBE_AUTOC_LMS_10G_SERIAL:
1186                 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1187                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1188                         goto out;
1189                 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1190                         goto sfp_check;
1191                 break;
1192         case IXGBE_AUTOC_LMS_KX4_KX_KR:
1193         case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1194                 if (autoc & IXGBE_AUTOC_KX_SUPP)
1195                         physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1196                 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1197                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1198                 if (autoc & IXGBE_AUTOC_KR_SUPP)
1199                         physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1200                 goto out;
1201                 break;
1202         default:
1203                 goto out;
1204                 break;
1205         }
1206
1207 sfp_check:
1208         /* SFP check must be done last since DA modules are sometimes used to
1209          * test KR mode -  we need to id KR mode correctly before SFP module.
1210          * Call identify_sfp because the pluggable module may have changed */
1211         hw->phy.ops.identify_sfp(hw);
1212         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1213                 goto out;
1214
1215         switch (hw->phy.type) {
1216         case ixgbe_phy_tw_tyco:
1217         case ixgbe_phy_tw_unknown:
1218                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1219                 break;
1220         case ixgbe_phy_sfp_avago:
1221         case ixgbe_phy_sfp_ftl:
1222         case ixgbe_phy_sfp_intel:
1223         case ixgbe_phy_sfp_unknown:
1224                 hw->phy.ops.read_i2c_eeprom(hw,
1225                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1226                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1227                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1228                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1229                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1230                 break;
1231         default:
1232                 break;
1233         }
1234
1235 out:
1236         return physical_layer;
1237 }
1238
1239 /**
1240  *  ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1241  *  @hw: pointer to hardware structure
1242  *  @regval: register value to write to RXCTRL
1243  *
1244  *  Enables the Rx DMA unit for 82599
1245  **/
1246 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1247 {
1248 #define IXGBE_MAX_SECRX_POLL 30
1249         int i;
1250         int secrxreg;
1251
1252         /*
1253          * Workaround for 82599 silicon errata when enabling the Rx datapath.
1254          * If traffic is incoming before we enable the Rx unit, it could hang
1255          * the Rx DMA unit.  Therefore, make sure the security engine is
1256          * completely disabled prior to enabling the Rx unit.
1257          */
1258         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1259         secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1260         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1261         for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1262                 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1263                 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1264                         break;
1265                 else
1266                         udelay(10);
1267         }
1268
1269         /* For informational purposes only */
1270         if (i >= IXGBE_MAX_SECRX_POLL)
1271                 hw_dbg(hw, "Rx unit being enabled before security "
1272                        "path fully disabled.  Continuing with init.\n");
1273
1274         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1275         secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1276         secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1277         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1278         IXGBE_WRITE_FLUSH(hw);
1279
1280         return 0;
1281 }
1282
1283 /**
1284  *  ixgbe_get_device_caps_82599 - Get additional device capabilities
1285  *  @hw: pointer to hardware structure
1286  *  @device_caps: the EEPROM word with the extra device capabilities
1287  *
1288  *  This function will read the EEPROM location for the device capabilities,
1289  *  and return the word through device_caps.
1290  **/
1291 s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1292 {
1293         hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1294
1295         return 0;
1296 }
1297
1298
1299 static struct ixgbe_mac_operations mac_ops_82599 = {
1300         .init_hw                = &ixgbe_init_hw_generic,
1301         .reset_hw               = &ixgbe_reset_hw_82599,
1302         .start_hw               = &ixgbe_start_hw_82599,
1303         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1304         .get_media_type         = &ixgbe_get_media_type_82599,
1305         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1306         .enable_rx_dma          = &ixgbe_enable_rx_dma_82599,
1307         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1308         .get_device_caps        = &ixgbe_get_device_caps_82599,
1309         .stop_adapter           = &ixgbe_stop_adapter_generic,
1310         .get_bus_info           = &ixgbe_get_bus_info_generic,
1311         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1312         .read_analog_reg8       = &ixgbe_read_analog_reg8_82599,
1313         .write_analog_reg8      = &ixgbe_write_analog_reg8_82599,
1314         .setup_link             = &ixgbe_setup_mac_link_82599,
1315         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82599,
1316         .check_link             = &ixgbe_check_mac_link_82599,
1317         .get_link_capabilities  = &ixgbe_get_link_capabilities_82599,
1318         .led_on                 = &ixgbe_led_on_generic,
1319         .led_off                = &ixgbe_led_off_generic,
1320         .blink_led_start        = &ixgbe_blink_led_start_generic,
1321         .blink_led_stop         = &ixgbe_blink_led_stop_generic,
1322         .set_rar                = &ixgbe_set_rar_generic,
1323         .clear_rar              = &ixgbe_clear_rar_generic,
1324         .set_vmdq               = &ixgbe_set_vmdq_82599,
1325         .clear_vmdq             = &ixgbe_clear_vmdq_82599,
1326         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1327         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1328         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1329         .enable_mc              = &ixgbe_enable_mc_generic,
1330         .disable_mc             = &ixgbe_disable_mc_generic,
1331         .clear_vfta             = &ixgbe_clear_vfta_82599,
1332         .set_vfta               = &ixgbe_set_vfta_82599,
1333         .setup_fc               = &ixgbe_setup_fc_generic,
1334         .init_uta_tables        = &ixgbe_init_uta_tables_82599,
1335         .setup_sfp              = &ixgbe_setup_sfp_modules_82599,
1336 };
1337
1338 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1339         .init_params            = &ixgbe_init_eeprom_params_generic,
1340         .read                   = &ixgbe_read_eeprom_generic,
1341         .write                  = &ixgbe_write_eeprom_generic,
1342         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1343         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1344 };
1345
1346 static struct ixgbe_phy_operations phy_ops_82599 = {
1347         .identify               = &ixgbe_identify_phy_82599,
1348         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1349         .init                   = &ixgbe_init_phy_ops_82599,
1350         .reset                  = &ixgbe_reset_phy_generic,
1351         .read_reg               = &ixgbe_read_phy_reg_generic,
1352         .write_reg              = &ixgbe_write_phy_reg_generic,
1353         .setup_link             = &ixgbe_setup_phy_link_generic,
1354         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1355         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
1356         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
1357         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
1358         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
1359 };
1360
1361 struct ixgbe_info ixgbe_82599_info = {
1362         .mac                    = ixgbe_mac_82599EB,
1363         .get_invariants         = &ixgbe_get_invariants_82599,
1364         .mac_ops                = &mac_ops_82599,
1365         .eeprom_ops             = &eeprom_ops_82599,
1366         .phy_ops                = &phy_ops_82599,
1367 };