drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  * Support : Micrel Phys:
  17  *              Giga phys: ksz9021, ksz9031
  18  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  19  *                         ksz8021, ksz8031, ksz8051,
  20  *                         ksz8081, ksz8091,
  21  *                         ksz8061,
  22  *              Switch : ksz8873, ksz886x
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/phy.h>
  28 #include <linux/micrel_phy.h>
  29 #include <linux/of.h>
  30 #include <linux/clk.h>
  31
  32 /* Operation Mode Strap Override */
  33 #define MII_KSZPHY_OMSO                         0x16
  34 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  35 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  36 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  37 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  38
  39 /* general Interrupt control/status reg in vendor specific block. */
  40 #define MII_KSZPHY_INTCS                        0x1B
  41 #define KSZPHY_INTCS_JABBER                     BIT(15)
  42 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  43 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  44 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  45 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  46 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  47 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  48 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  49 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  50                                                 KSZPHY_INTCS_LINK_DOWN)
  51
  52 /* PHY Control 1 */
  53 #define MII_KSZPHY_CTRL_1                       0x1e
  54
  55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  56 #define MII_KSZPHY_CTRL_2                       0x1f
  57 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  58 /* bitmap of PHY register to set interrupt mode */
  59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  60 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  61
  62 /* Write/read to/from extended registers */
  63 #define MII_KSZPHY_EXTREG                       0x0b
  64 #define KSZPHY_EXTREG_WRITE                     0x8000
  65
  66 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  67 #define MII_KSZPHY_EXTREG_READ                  0x0d
  68
  69 /* Extended registers */
  70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  71 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  72 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  73
  74 #define PS_TO_REG                               200
  75
  76 struct kszphy_hw_stat {
  77         const char *string;
  78         u8 reg;
  79         u8 bits;
  80 };
  81
  82 static struct kszphy_hw_stat kszphy_hw_stats[] = {
  83         { "phy_receive_errors", 21, 16},
  84         { "phy_idle_errors", 10, 8 },
  85 };
  86
  87 struct kszphy_type {
  88         u32 led_mode_reg;
  89         u16 interrupt_level_mask;
  90         bool has_broadcast_disable;
  91         bool has_nand_tree_disable;
  92         bool has_rmii_ref_clk_sel;
  93 };
  94
  95 struct kszphy_priv {
  96         const struct kszphy_type *type;
  97         int led_mode;
  98         bool rmii_ref_clk_sel;
  99         bool rmii_ref_clk_sel_val;
 100         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 101 };
 102
 103 static const struct kszphy_type ksz8021_type = {
 104         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 105         .has_broadcast_disable  = true,
 106         .has_nand_tree_disable  = true,
 107         .has_rmii_ref_clk_sel   = true,
 108 };
 109
 110 static const struct kszphy_type ksz8041_type = {
 111         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 112 };
 113
 114 static const struct kszphy_type ksz8051_type = {
 115         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 116         .has_nand_tree_disable  = true,
 117 };
 118
 119 static const struct kszphy_type ksz8081_type = {
 120         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 121         .has_broadcast_disable  = true,
 122         .has_nand_tree_disable  = true,
 123         .has_rmii_ref_clk_sel   = true,
 124 };
 125
 126 static const struct kszphy_type ks8737_type = {
 127         .interrupt_level_mask   = BIT(14),
 128 };
 129
 130 static const struct kszphy_type ksz9021_type = {
 131         .interrupt_level_mask   = BIT(14),
 132 };
 133
 134 static int kszphy_extended_write(struct phy_device *phydev,
 135                                 u32 regnum, u16 val)
 136 {
 137         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 138         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 139 }
 140
 141 static int kszphy_extended_read(struct phy_device *phydev,
 142                                 u32 regnum)
 143 {
 144         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 145         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 146 }
 147
 148 static int kszphy_ack_interrupt(struct phy_device *phydev)
 149 {
 150         /* bit[7..0] int status, which is a read and clear register. */
 151         int rc;
 152
 153         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 154
 155         return (rc < 0) ? rc : 0;
 156 }
 157
 158 static int kszphy_config_intr(struct phy_device *phydev)
 159 {
 160         const struct kszphy_type *type = phydev->drv->driver_data;
 161         int temp;
 162         u16 mask;
 163
 164         if (type && type->interrupt_level_mask)
 165                 mask = type->interrupt_level_mask;
 166         else
 167                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 168
 169         /* set the interrupt pin active low */
 170         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 171         if (temp < 0)
 172                 return temp;
 173         temp &= ~mask;
 174         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 175
 176         /* enable / disable interrupts */
 177         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 178                 temp = KSZPHY_INTCS_ALL;
 179         else
 180                 temp = 0;
 181
 182         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 183 }
 184
 185 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 186 {
 187         int ctrl;
 188
 189         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 190         if (ctrl < 0)
 191                 return ctrl;
 192
 193         if (val)
 194                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 195         else
 196                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 197
 198         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 199 }
 200
 201 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 202 {
 203         int rc, temp, shift;
 204
 205         switch (reg) {
 206         case MII_KSZPHY_CTRL_1:
 207                 shift = 14;
 208                 break;
 209         case MII_KSZPHY_CTRL_2:
 210                 shift = 4;
 211                 break;
 212         default:
 213                 return -EINVAL;
 214         }
 215
 216         temp = phy_read(phydev, reg);
 217         if (temp < 0) {
 218                 rc = temp;
 219                 goto out;
 220         }
 221
 222         temp &= ~(3 << shift);
 223         temp |= val << shift;
 224         rc = phy_write(phydev, reg, temp);
 225 out:
 226         if (rc < 0)
 227                 phydev_err(phydev, "failed to set led mode\n");
 228
 229         return rc;
 230 }
 231
 232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 233  * unique (non-broadcast) address on a shared bus.
 234  */
 235 static int kszphy_broadcast_disable(struct phy_device *phydev)
 236 {
 237         int ret;
 238
 239         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 240         if (ret < 0)
 241                 goto out;
 242
 243         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 244 out:
 245         if (ret)
 246                 phydev_err(phydev, "failed to disable broadcast address\n");
 247
 248         return ret;
 249 }
 250
 251 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 252 {
 253         int ret;
 254
 255         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 256         if (ret < 0)
 257                 goto out;
 258
 259         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 260                 return 0;
 261
 262         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 263                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 264 out:
 265         if (ret)
 266                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 267
 268         return ret;
 269 }
 270
 271 static int kszphy_config_init(struct phy_device *phydev)
 272 {
 273         struct kszphy_priv *priv = phydev->priv;
 274         const struct kszphy_type *type;
 275         int ret;
 276
 277         if (!priv)
 278                 return 0;
 279
 280         type = priv->type;
 281
 282         if (type->has_broadcast_disable)
 283                 kszphy_broadcast_disable(phydev);
 284
 285         if (type->has_nand_tree_disable)
 286                 kszphy_nand_tree_disable(phydev);
 287
 288         if (priv->rmii_ref_clk_sel) {
 289                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 290                 if (ret) {
 291                         phydev_err(phydev,
 292                                    "failed to set rmii reference clock\n");
 293                         return ret;
 294                 }
 295         }
 296
 297         if (priv->led_mode >= 0)
 298                 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
 299
 300         return 0;
 301 }
 302
 303 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 304                                        const struct device_node *of_node,
 305                                        u16 reg,
 306                                        const char *field1, const char *field2,
 307                                        const char *field3, const char *field4)
 308 {
 309         int val1 = -1;
 310         int val2 = -2;
 311         int val3 = -3;
 312         int val4 = -4;
 313         int newval;
 314         int matches = 0;
 315
 316         if (!of_property_read_u32(of_node, field1, &val1))
 317                 matches++;
 318
 319         if (!of_property_read_u32(of_node, field2, &val2))
 320                 matches++;
 321
 322         if (!of_property_read_u32(of_node, field3, &val3))
 323                 matches++;
 324
 325         if (!of_property_read_u32(of_node, field4, &val4))
 326                 matches++;
 327
 328         if (!matches)
 329                 return 0;
 330
 331         if (matches < 4)
 332                 newval = kszphy_extended_read(phydev, reg);
 333         else
 334                 newval = 0;
 335
 336         if (val1 != -1)
 337                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 338
 339         if (val2 != -2)
 340                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 341
 342         if (val3 != -3)
 343                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 344
 345         if (val4 != -4)
 346                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 347
 348         return kszphy_extended_write(phydev, reg, newval);
 349 }
 350
 351 static int ksz9021_config_init(struct phy_device *phydev)
 352 {
 353         const struct device *dev = &phydev->mdio.dev;
 354         const struct device_node *of_node = dev->of_node;
 355         const struct device *dev_walker;
 356
 357         /* The Micrel driver has a deprecated option to place phy OF
 358          * properties in the MAC node. Walk up the tree of devices to
 359          * find a device with an OF node.
 360          */
 361         dev_walker = &phydev->mdio.dev;
 362         do {
 363                 of_node = dev_walker->of_node;
 364                 dev_walker = dev_walker->parent;
 365
 366         } while (!of_node && dev_walker);
 367
 368         if (of_node) {
 369                 ksz9021_load_values_from_of(phydev, of_node,
 370                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 371                                     "txen-skew-ps", "txc-skew-ps",
 372                                     "rxdv-skew-ps", "rxc-skew-ps");
 373                 ksz9021_load_values_from_of(phydev, of_node,
 374                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 375                                     "rxd0-skew-ps", "rxd1-skew-ps",
 376                                     "rxd2-skew-ps", "rxd3-skew-ps");
 377                 ksz9021_load_values_from_of(phydev, of_node,
 378                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 379                                     "txd0-skew-ps", "txd1-skew-ps",
 380                                     "txd2-skew-ps", "txd3-skew-ps");
 381         }
 382         return 0;
 383 }
 384
 385 #define MII_KSZ9031RN_MMD_CTRL_REG      0x0d
 386 #define MII_KSZ9031RN_MMD_REGDATA_REG   0x0e
 387 #define OP_DATA                         1
 388 #define KSZ9031_PS_TO_REG               60
 389
 390 /* Extended registers */
 391 /* MMD Address 0x0 */
 392 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 393 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 394
 395 /* MMD Address 0x2 */
 396 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 397 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 398 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 399 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 400
 401 static int ksz9031_extended_write(struct phy_device *phydev,
 402                                   u8 mode, u32 dev_addr, u32 regnum, u16 val)
 403 {
 404         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 405         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 406         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 407         return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
 408 }
 409
 410 static int ksz9031_extended_read(struct phy_device *phydev,
 411                                  u8 mode, u32 dev_addr, u32 regnum)
 412 {
 413         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 414         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 415         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 416         return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
 417 }
 418
 419 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 420                                        const struct device_node *of_node,
 421                                        u16 reg, size_t field_sz,
 422                                        const char *field[], u8 numfields)
 423 {
 424         int val[4] = {-1, -2, -3, -4};
 425         int matches = 0;
 426         u16 mask;
 427         u16 maxval;
 428         u16 newval;
 429         int i;
 430
 431         for (i = 0; i < numfields; i++)
 432                 if (!of_property_read_u32(of_node, field[i], val + i))
 433                         matches++;
 434
 435         if (!matches)
 436                 return 0;
 437
 438         if (matches < numfields)
 439                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 440         else
 441                 newval = 0;
 442
 443         maxval = (field_sz == 4) ? 0xf : 0x1f;
 444         for (i = 0; i < numfields; i++)
 445                 if (val[i] != -(i + 1)) {
 446                         mask = 0xffff;
 447                         mask ^= maxval << (field_sz * i);
 448                         newval = (newval & mask) |
 449                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 450                                         << (field_sz * i));
 451                 }
 452
 453         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 454 }
 455
 456 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 457 {
 458         int result;
 459
 460         /* Center KSZ9031RNX FLP timing at 16ms. */
 461         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 462                                         MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
 463         result = ksz9031_extended_write(phydev, OP_DATA, 0,
 464                                         MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
 465
 466         if (result)
 467                 return result;
 468
 469         return genphy_restart_aneg(phydev);
 470 }
 471
 472 static int ksz9031_config_init(struct phy_device *phydev)
 473 {
 474         const struct device *dev = &phydev->mdio.dev;
 475         const struct device_node *of_node = dev->of_node;
 476         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 477         static const char *rx_data_skews[4] = {
 478                 "rxd0-skew-ps", "rxd1-skew-ps",
 479                 "rxd2-skew-ps", "rxd3-skew-ps"
 480         };
 481         static const char *tx_data_skews[4] = {
 482                 "txd0-skew-ps", "txd1-skew-ps",
 483                 "txd2-skew-ps", "txd3-skew-ps"
 484         };
 485         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 486         const struct device *dev_walker;
 487
 488         /* The Micrel driver has a deprecated option to place phy OF
 489          * properties in the MAC node. Walk up the tree of devices to
 490          * find a device with an OF node.
 491          */
 492         dev_walker = &phydev->mdio.dev;
 493         do {
 494                 of_node = dev_walker->of_node;
 495                 dev_walker = dev_walker->parent;
 496         } while (!of_node && dev_walker);
 497
 498         if (of_node) {
 499                 ksz9031_of_load_skew_values(phydev, of_node,
 500                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 501                                 clk_skews, 2);
 502
 503                 ksz9031_of_load_skew_values(phydev, of_node,
 504                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 505                                 control_skews, 2);
 506
 507                 ksz9031_of_load_skew_values(phydev, of_node,
 508                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 509                                 rx_data_skews, 4);
 510
 511                 ksz9031_of_load_skew_values(phydev, of_node,
 512                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 513                                 tx_data_skews, 4);
 514         }
 515
 516         return ksz9031_center_flp_timing(phydev);
 517 }
 518
 519 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 520 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 521 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 522 static int ksz8873mll_read_status(struct phy_device *phydev)
 523 {
 524         int regval;
 525
 526         /* dummy read */
 527         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 528
 529         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 530
 531         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 532                 phydev->duplex = DUPLEX_HALF;
 533         else
 534                 phydev->duplex = DUPLEX_FULL;
 535
 536         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 537                 phydev->speed = SPEED_10;
 538         else
 539                 phydev->speed = SPEED_100;
 540
 541         phydev->link = 1;
 542         phydev->pause = phydev->asym_pause = 0;
 543
 544         return 0;
 545 }
 546
 547 static int ksz9031_read_status(struct phy_device *phydev)
 548 {
 549         int err;
 550         int regval;
 551
 552         err = genphy_read_status(phydev);
 553         if (err)
 554                 return err;
 555
 556         /* Make sure the PHY is not broken. Read idle error count,
 557          * and reset the PHY if it is maxed out.
 558          */
 559         regval = phy_read(phydev, MII_STAT1000);
 560         if ((regval & 0xFF) == 0xFF) {
 561                 phy_init_hw(phydev);
 562                 phydev->link = 0;
 563         }
 564
 565         return 0;
 566 }
 567
 568 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 569 {
 570         return 0;
 571 }
 572
 573 /* This routine returns -1 as an indication to the caller that the
 574  * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
 575  * MMD extended PHY registers.
 576  */
 577 static int
 578 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 579                       int regnum)
 580 {
 581         return -1;
 582 }
 583
 584 /* This routine does nothing since the Micrel ksz9021 does not support
 585  * standard IEEE MMD extended PHY registers.
 586  */
 587 static void
 588 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 589                       int regnum, u32 val)
 590 {
 591 }
 592
 593 static int kszphy_get_sset_count(struct phy_device *phydev)
 594 {
 595         return ARRAY_SIZE(kszphy_hw_stats);
 596 }
 597
 598 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
 599 {
 600         int i;
 601
 602         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
 603                 memcpy(data + i * ETH_GSTRING_LEN,
 604                        kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
 605         }
 606 }
 607
 608 #ifndef UINT64_MAX
 609 #define UINT64_MAX              (u64)(~((u64)0))
 610 #endif
 611 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
 612 {
 613         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
 614         struct kszphy_priv *priv = phydev->priv;
 615         u64 val;
 616
 617         val = phy_read(phydev, stat.reg);
 618         if (val < 0) {
 619                 val = UINT64_MAX;
 620         } else {
 621                 val = val & ((1 << stat.bits) - 1);
 622                 priv->stats[i] += val;
 623                 val = priv->stats[i];
 624         }
 625
 626         return val;
 627 }
 628
 629 static void kszphy_get_stats(struct phy_device *phydev,
 630                              struct ethtool_stats *stats, u64 *data)
 631 {
 632         int i;
 633
 634         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
 635                 data[i] = kszphy_get_stat(phydev, i);
 636 }
 637
 638 static int kszphy_resume(struct phy_device *phydev)
 639 {
 640         int value;
 641
 642         mutex_lock(&phydev->lock);
 643
 644         value = phy_read(phydev, MII_BMCR);
 645         phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
 646
 647         kszphy_config_intr(phydev);
 648         mutex_unlock(&phydev->lock);
 649
 650         return 0;
 651 }
 652
 653 static int kszphy_probe(struct phy_device *phydev)
 654 {
 655         const struct kszphy_type *type = phydev->drv->driver_data;
 656         const struct device_node *np = phydev->mdio.dev.of_node;
 657         struct kszphy_priv *priv;
 658         struct clk *clk;
 659         int ret;
 660
 661         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
 662         if (!priv)
 663                 return -ENOMEM;
 664
 665         phydev->priv = priv;
 666
 667         priv->type = type;
 668
 669         if (type->led_mode_reg) {
 670                 ret = of_property_read_u32(np, "micrel,led-mode",
 671                                 &priv->led_mode);
 672                 if (ret)
 673                         priv->led_mode = -1;
 674
 675                 if (priv->led_mode > 3) {
 676                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
 677                                    priv->led_mode);
 678                         priv->led_mode = -1;
 679                 }
 680         } else {
 681                 priv->led_mode = -1;
 682         }
 683
 684         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
 685         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 686         if (!IS_ERR_OR_NULL(clk)) {
 687                 unsigned long rate = clk_get_rate(clk);
 688                 bool rmii_ref_clk_sel_25_mhz;
 689
 690                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 691                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 692                                 "micrel,rmii-reference-clock-select-25-mhz");
 693
 694                 if (rate > 24500000 && rate < 25500000) {
 695                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 696                 } else if (rate > 49500000 && rate < 50500000) {
 697                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 698                 } else {
 699                         phydev_err(phydev, "Clock rate out of range: %ld\n",
 700                                    rate);
 701                         return -EINVAL;
 702                 }
 703         }
 704
 705         /* Support legacy board-file configuration */
 706         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 707                 priv->rmii_ref_clk_sel = true;
 708                 priv->rmii_ref_clk_sel_val = true;
 709         }
 710
 711         return 0;
 712 }
 713
 714 static struct phy_driver ksphy_driver[] = {
 715 {
 716         .phy_id         = PHY_ID_KS8737,
 717         .phy_id_mask    = 0x00fffff0,
 718         .name           = "Micrel KS8737",
 719         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 720         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 721         .driver_data    = &ks8737_type,
 722         .config_init    = kszphy_config_init,
 723         .config_aneg    = genphy_config_aneg,
 724         .read_status    = genphy_read_status,
 725         .ack_interrupt  = kszphy_ack_interrupt,
 726         .config_intr    = kszphy_config_intr,
 727         .get_sset_count = kszphy_get_sset_count,
 728         .get_strings    = kszphy_get_strings,
 729         .get_stats      = kszphy_get_stats,
 730         .suspend        = genphy_suspend,
 731         .resume         = genphy_resume,
 732 }, {
 733         .phy_id         = PHY_ID_KSZ8021,
 734         .phy_id_mask    = 0x00ffffff,
 735         .name           = "Micrel KSZ8021 or KSZ8031",
 736         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 737                            SUPPORTED_Asym_Pause),
 738         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 739         .driver_data    = &ksz8021_type,
 740         .probe          = kszphy_probe,
 741         .config_init    = kszphy_config_init,
 742         .config_aneg    = genphy_config_aneg,
 743         .read_status    = genphy_read_status,
 744         .ack_interrupt  = kszphy_ack_interrupt,
 745         .config_intr    = kszphy_config_intr,
 746         .get_sset_count = kszphy_get_sset_count,
 747         .get_strings    = kszphy_get_strings,
 748         .get_stats      = kszphy_get_stats,
 749         .suspend        = genphy_suspend,
 750         .resume         = genphy_resume,
 751 }, {
 752         .phy_id         = PHY_ID_KSZ8031,
 753         .phy_id_mask    = 0x00ffffff,
 754         .name           = "Micrel KSZ8031",
 755         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 756                            SUPPORTED_Asym_Pause),
 757         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 758         .driver_data    = &ksz8021_type,
 759         .probe          = kszphy_probe,
 760         .config_init    = kszphy_config_init,
 761         .config_aneg    = genphy_config_aneg,
 762         .read_status    = genphy_read_status,
 763         .ack_interrupt  = kszphy_ack_interrupt,
 764         .config_intr    = kszphy_config_intr,
 765         .get_sset_count = kszphy_get_sset_count,
 766         .get_strings    = kszphy_get_strings,
 767         .get_stats      = kszphy_get_stats,
 768         .suspend        = genphy_suspend,
 769         .resume         = genphy_resume,
 770 }, {
 771         .phy_id         = PHY_ID_KSZ8041,
 772         .phy_id_mask    = 0x00fffff0,
 773         .name           = "Micrel KSZ8041",
 774         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 775                                 | SUPPORTED_Asym_Pause),
 776         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 777         .driver_data    = &ksz8041_type,
 778         .probe          = kszphy_probe,
 779         .config_init    = kszphy_config_init,
 780         .config_aneg    = genphy_config_aneg,
 781         .read_status    = genphy_read_status,
 782         .ack_interrupt  = kszphy_ack_interrupt,
 783         .config_intr    = kszphy_config_intr,
 784         .get_sset_count = kszphy_get_sset_count,
 785         .get_strings    = kszphy_get_strings,
 786         .get_stats      = kszphy_get_stats,
 787         .suspend        = genphy_suspend,
 788         .resume         = genphy_resume,
 789 }, {
 790         .phy_id         = PHY_ID_KSZ8041RNLI,
 791         .phy_id_mask    = 0x00fffff0,
 792         .name           = "Micrel KSZ8041RNLI",
 793         .features       = PHY_BASIC_FEATURES |
 794                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 795         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 796         .driver_data    = &ksz8041_type,
 797         .probe          = kszphy_probe,
 798         .config_init    = kszphy_config_init,
 799         .config_aneg    = genphy_config_aneg,
 800         .read_status    = genphy_read_status,
 801         .ack_interrupt  = kszphy_ack_interrupt,
 802         .config_intr    = kszphy_config_intr,
 803         .get_sset_count = kszphy_get_sset_count,
 804         .get_strings    = kszphy_get_strings,
 805         .get_stats      = kszphy_get_stats,
 806         .suspend        = genphy_suspend,
 807         .resume         = genphy_resume,
 808 }, {
 809         .phy_id         = PHY_ID_KSZ8051,
 810         .phy_id_mask    = 0x00fffff0,
 811         .name           = "Micrel KSZ8051",
 812         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 813                                 | SUPPORTED_Asym_Pause),
 814         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 815         .driver_data    = &ksz8051_type,
 816         .probe          = kszphy_probe,
 817         .config_init    = kszphy_config_init,
 818         .config_aneg    = genphy_config_aneg,
 819         .read_status    = genphy_read_status,
 820         .ack_interrupt  = kszphy_ack_interrupt,
 821         .config_intr    = kszphy_config_intr,
 822         .get_sset_count = kszphy_get_sset_count,
 823         .get_strings    = kszphy_get_strings,
 824         .get_stats      = kszphy_get_stats,
 825         .suspend        = genphy_suspend,
 826         .resume         = genphy_resume,
 827 }, {
 828         .phy_id         = PHY_ID_KSZ8001,
 829         .name           = "Micrel KSZ8001 or KS8721",
 830         .phy_id_mask    = 0x00ffffff,
 831         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 832         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 833         .driver_data    = &ksz8041_type,
 834         .probe          = kszphy_probe,
 835         .config_init    = kszphy_config_init,
 836         .config_aneg    = genphy_config_aneg,
 837         .read_status    = genphy_read_status,
 838         .ack_interrupt  = kszphy_ack_interrupt,
 839         .config_intr    = kszphy_config_intr,
 840         .get_sset_count = kszphy_get_sset_count,
 841         .get_strings    = kszphy_get_strings,
 842         .get_stats      = kszphy_get_stats,
 843         .suspend        = genphy_suspend,
 844         .resume         = genphy_resume,
 845 }, {
 846         .phy_id         = PHY_ID_KSZ8081,
 847         .name           = "Micrel KSZ8081 or KSZ8091",
 848         .phy_id_mask    = 0x00fffff0,
 849         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 850         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 851         .driver_data    = &ksz8081_type,
 852         .probe          = kszphy_probe,
 853         .config_init    = kszphy_config_init,
 854         .config_aneg    = genphy_config_aneg,
 855         .read_status    = genphy_read_status,
 856         .ack_interrupt  = kszphy_ack_interrupt,
 857         .config_intr    = kszphy_config_intr,
 858         .get_sset_count = kszphy_get_sset_count,
 859         .get_strings    = kszphy_get_strings,
 860         .get_stats      = kszphy_get_stats,
 861         .suspend        = genphy_suspend,
 862         .resume         = kszphy_resume,
 863 }, {
 864         .phy_id         = PHY_ID_KSZ8061,
 865         .name           = "Micrel KSZ8061",
 866         .phy_id_mask    = 0x00fffff0,
 867         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 868         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 869         .config_init    = kszphy_config_init,
 870         .config_aneg    = genphy_config_aneg,
 871         .read_status    = genphy_read_status,
 872         .ack_interrupt  = kszphy_ack_interrupt,
 873         .config_intr    = kszphy_config_intr,
 874         .get_sset_count = kszphy_get_sset_count,
 875         .get_strings    = kszphy_get_strings,
 876         .get_stats      = kszphy_get_stats,
 877         .suspend        = genphy_suspend,
 878         .resume         = genphy_resume,
 879 }, {
 880         .phy_id         = PHY_ID_KSZ9021,
 881         .phy_id_mask    = 0x000ffffe,
 882         .name           = "Micrel KSZ9021 Gigabit PHY",
 883         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 884         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 885         .driver_data    = &ksz9021_type,
 886         .config_init    = ksz9021_config_init,
 887         .config_aneg    = genphy_config_aneg,
 888         .read_status    = genphy_read_status,
 889         .ack_interrupt  = kszphy_ack_interrupt,
 890         .config_intr    = kszphy_config_intr,
 891         .get_sset_count = kszphy_get_sset_count,
 892         .get_strings    = kszphy_get_strings,
 893         .get_stats      = kszphy_get_stats,
 894         .suspend        = genphy_suspend,
 895         .resume         = genphy_resume,
 896         .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
 897         .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
 898 }, {
 899         .phy_id         = PHY_ID_KSZ9031,
 900         .phy_id_mask    = 0x00fffff0,
 901         .name           = "Micrel KSZ9031 Gigabit PHY",
 902         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 903         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 904         .driver_data    = &ksz9021_type,
 905         .config_init    = ksz9031_config_init,
 906         .config_aneg    = genphy_config_aneg,
 907         .read_status    = ksz9031_read_status,
 908         .ack_interrupt  = kszphy_ack_interrupt,
 909         .config_intr    = kszphy_config_intr,
 910         .get_sset_count = kszphy_get_sset_count,
 911         .get_strings    = kszphy_get_strings,
 912         .get_stats      = kszphy_get_stats,
 913         .suspend        = genphy_suspend,
 914         .resume         = genphy_resume,
 915 }, {
 916         .phy_id         = PHY_ID_KSZ8873MLL,
 917         .phy_id_mask    = 0x00fffff0,
 918         .name           = "Micrel KSZ8873MLL Switch",
 919         .features       = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
 920         .flags          = PHY_HAS_MAGICANEG,
 921         .config_init    = kszphy_config_init,
 922         .config_aneg    = ksz8873mll_config_aneg,
 923         .read_status    = ksz8873mll_read_status,
 924         .get_sset_count = kszphy_get_sset_count,
 925         .get_strings    = kszphy_get_strings,
 926         .get_stats      = kszphy_get_stats,
 927         .suspend        = genphy_suspend,
 928         .resume         = genphy_resume,
 929 }, {
 930         .phy_id         = PHY_ID_KSZ886X,
 931         .phy_id_mask    = 0x00fffff0,
 932         .name           = "Micrel KSZ886X Switch",
 933         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 934         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 935         .config_init    = kszphy_config_init,
 936         .config_aneg    = genphy_config_aneg,
 937         .read_status    = genphy_read_status,
 938         .get_sset_count = kszphy_get_sset_count,
 939         .get_strings    = kszphy_get_strings,
 940         .get_stats      = kszphy_get_stats,
 941         .suspend        = genphy_suspend,
 942         .resume         = genphy_resume,
 943 } };
 944
 945 module_phy_driver(ksphy_driver);
 946
 947 MODULE_DESCRIPTION("Micrel PHY driver");
 948 MODULE_AUTHOR("David J. Choi");
 949 MODULE_LICENSE("GPL");
 950
 951 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
 952         { PHY_ID_KSZ9021, 0x000ffffe },
 953         { PHY_ID_KSZ9031, 0x00fffff0 },
 954         { PHY_ID_KSZ8001, 0x00ffffff },
 955         { PHY_ID_KS8737, 0x00fffff0 },
 956         { PHY_ID_KSZ8021, 0x00ffffff },
 957         { PHY_ID_KSZ8031, 0x00ffffff },
 958         { PHY_ID_KSZ8041, 0x00fffff0 },
 959         { PHY_ID_KSZ8051, 0x00fffff0 },
 960         { PHY_ID_KSZ8061, 0x00fffff0 },
 961         { PHY_ID_KSZ8081, 0x00fffff0 },
 962         { PHY_ID_KSZ8873MLL, 0x00fffff0 },
 963         { PHY_ID_KSZ886X, 0x00fffff0 },
 964         { }
 965 };
 966
 967 MODULE_DEVICE_TABLE(mdio, micrel_tbl);