drivers/net/qla3xxx.c

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/mempool.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/kthread.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/ip.h>
  25 #include <linux/in.h>
  26 #include <linux/if_arp.h>
  27 #include <linux/if_ether.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/rtnetlink.h>
  33 #include <linux/if_vlan.h>
  34 #include <linux/init.h>
  35 #include <linux/delay.h>
  36 #include <linux/mm.h>
  37
  38 #include "qla3xxx.h"
  39
  40 #define DRV_NAME        "qla3xxx"
  41 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
  42 #define DRV_VERSION     "v2.02.00-k36"
  43 #define PFX             DRV_NAME " "
  44
  45 static const char ql3xxx_driver_name[] = DRV_NAME;
  46 static const char ql3xxx_driver_version[] = DRV_VERSION;
  47
  48 MODULE_AUTHOR("QLogic Corporation");
  49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
  50 MODULE_LICENSE("GPL");
  51 MODULE_VERSION(DRV_VERSION);
  52
  53 static const u32 default_msg
  54     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  55     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  56
  57 static int debug = -1;          /* defaults above */
  58 module_param(debug, int, 0);
  59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  60
  61 static int msi;
  62 module_param(msi, int, 0);
  63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
  64
  65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
  66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
  67         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
  68         /* required last entry */
  69         {0,}
  70 };
  71
  72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
  73
  74 /*
  75  * Caller must take hw_lock.
  76  */
  77 static int ql_sem_spinlock(struct ql3_adapter *qdev,
  78                             u32 sem_mask, u32 sem_bits)
  79 {
  80         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  81         u32 value;
  82         unsigned int seconds = 3;
  83
  84         do {
  85                 writel((sem_mask | sem_bits),
  86                        &port_regs->CommonRegs.semaphoreReg);
  87                 value = readl(&port_regs->CommonRegs.semaphoreReg);
  88                 if ((value & (sem_mask >> 16)) == sem_bits)
  89                         return 0;
  90                 ssleep(1);
  91         } while(--seconds);
  92         return -1;
  93 }
  94
  95 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
  96 {
  97         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  98         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
  99         readl(&port_regs->CommonRegs.semaphoreReg);
 100 }
 101
 102 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
 103 {
 104         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 105         u32 value;
 106
 107         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
 108         value = readl(&port_regs->CommonRegs.semaphoreReg);
 109         return ((value & (sem_mask >> 16)) == sem_bits);
 110 }
 111
 112 /*
 113  * Caller holds hw_lock.
 114  */
 115 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
 116 {
 117         int i = 0;
 118
 119         while (1) {
 120                 if (!ql_sem_lock(qdev,
 121                                  QL_DRVR_SEM_MASK,
 122                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
 123                                   * 2) << 1)) {
 124                         if (i < 10) {
 125                                 ssleep(1);
 126                                 i++;
 127                         } else {
 128                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
 129                                        "driver lock...\n",
 130                                        qdev->ndev->name);
 131                                 return 0;
 132                         }
 133                 } else {
 134                         printk(KERN_DEBUG PFX
 135                                "%s: driver lock acquired.\n",
 136                                qdev->ndev->name);
 137                         return 1;
 138                 }
 139         }
 140 }
 141
 142 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
 143 {
 144         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 145
 146         writel(((ISP_CONTROL_NP_MASK << 16) | page),
 147                         &port_regs->CommonRegs.ispControlStatus);
 148         readl(&port_regs->CommonRegs.ispControlStatus);
 149         qdev->current_page = page;
 150 }
 151
 152 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
 153                               u32 __iomem * reg)
 154 {
 155         u32 value;
 156         unsigned long hw_flags;
 157
 158         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 159         value = readl(reg);
 160         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 161
 162         return value;
 163 }
 164
 165 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
 166                               u32 __iomem * reg)
 167 {
 168         return readl(reg);
 169 }
 170
 171 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
 172 {
 173         u32 value;
 174         unsigned long hw_flags;
 175
 176         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 177
 178         if (qdev->current_page != 0)
 179                 ql_set_register_page(qdev,0);
 180         value = readl(reg);
 181
 182         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 183         return value;
 184 }
 185
 186 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
 187 {
 188         if (qdev->current_page != 0)
 189                 ql_set_register_page(qdev,0);
 190         return readl(reg);
 191 }
 192
 193 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
 194                                 u32 __iomem *reg, u32 value)
 195 {
 196         unsigned long hw_flags;
 197
 198         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 199         writel(value, reg);
 200         readl(reg);
 201         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 202         return;
 203 }
 204
 205 static void ql_write_common_reg(struct ql3_adapter *qdev,
 206                                 u32 __iomem *reg, u32 value)
 207 {
 208         writel(value, reg);
 209         readl(reg);
 210         return;
 211 }
 212
 213 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
 214                                 u32 __iomem *reg, u32 value)
 215 {
 216         writel(value, reg);
 217         readl(reg);
 218         udelay(1);
 219         return;
 220 }
 221
 222 static void ql_write_page0_reg(struct ql3_adapter *qdev,
 223                                u32 __iomem *reg, u32 value)
 224 {
 225         if (qdev->current_page != 0)
 226                 ql_set_register_page(qdev,0);
 227         writel(value, reg);
 228         readl(reg);
 229         return;
 230 }
 231
 232 /*
 233  * Caller holds hw_lock. Only called during init.
 234  */
 235 static void ql_write_page1_reg(struct ql3_adapter *qdev,
 236                                u32 __iomem *reg, u32 value)
 237 {
 238         if (qdev->current_page != 1)
 239                 ql_set_register_page(qdev,1);
 240         writel(value, reg);
 241         readl(reg);
 242         return;
 243 }
 244
 245 /*
 246  * Caller holds hw_lock. Only called during init.
 247  */
 248 static void ql_write_page2_reg(struct ql3_adapter *qdev,
 249                                u32 __iomem *reg, u32 value)
 250 {
 251         if (qdev->current_page != 2)
 252                 ql_set_register_page(qdev,2);
 253         writel(value, reg);
 254         readl(reg);
 255         return;
 256 }
 257
 258 static void ql_disable_interrupts(struct ql3_adapter *qdev)
 259 {
 260         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 261
 262         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 263                             (ISP_IMR_ENABLE_INT << 16));
 264
 265 }
 266
 267 static void ql_enable_interrupts(struct ql3_adapter *qdev)
 268 {
 269         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 270
 271         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 272                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
 273
 274 }
 275
 276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
 277                                             struct ql_rcv_buf_cb *lrg_buf_cb)
 278 {
 279         dma_addr_t map;
 280         int err;
 281         lrg_buf_cb->next = NULL;
 282
 283         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
 284                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
 285         } else {
 286                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
 287                 qdev->lrg_buf_free_tail = lrg_buf_cb;
 288         }
 289
 290         if (!lrg_buf_cb->skb) {
 291                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
 292                                                    qdev->lrg_buffer_len);
 293                 if (unlikely(!lrg_buf_cb->skb)) {
 294                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
 295                                qdev->ndev->name);
 296                         qdev->lrg_buf_skb_check++;
 297                 } else {
 298                         /*
 299                          * We save some space to copy the ethhdr from first
 300                          * buffer
 301                          */
 302                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
 303                         map = pci_map_single(qdev->pdev,
 304                                              lrg_buf_cb->skb->data,
 305                                              qdev->lrg_buffer_len -
 306                                              QL_HEADER_SPACE,
 307                                              PCI_DMA_FROMDEVICE);
 308                         err = pci_dma_mapping_error(map);
 309                         if(err) {
 310                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
 311                                        qdev->ndev->name, err);
 312                                 dev_kfree_skb(lrg_buf_cb->skb);
 313                                 lrg_buf_cb->skb = NULL;
 314
 315                                 qdev->lrg_buf_skb_check++;
 316                                 return;
 317                         }
 318
 319                         lrg_buf_cb->buf_phy_addr_low =
 320                             cpu_to_le32(LS_64BITS(map));
 321                         lrg_buf_cb->buf_phy_addr_high =
 322                             cpu_to_le32(MS_64BITS(map));
 323                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
 324                         pci_unmap_len_set(lrg_buf_cb, maplen,
 325                                           qdev->lrg_buffer_len -
 326                                           QL_HEADER_SPACE);
 327                 }
 328         }
 329
 330         qdev->lrg_buf_free_count++;
 331 }
 332
 333 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
 334                                                            *qdev)
 335 {
 336         struct ql_rcv_buf_cb *lrg_buf_cb;
 337
 338         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
 339                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
 340                         qdev->lrg_buf_free_tail = NULL;
 341                 qdev->lrg_buf_free_count--;
 342         }
 343
 344         return lrg_buf_cb;
 345 }
 346
 347 static u32 addrBits = EEPROM_NO_ADDR_BITS;
 348 static u32 dataBits = EEPROM_NO_DATA_BITS;
 349
 350 static void fm93c56a_deselect(struct ql3_adapter *qdev);
 351 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
 352                             unsigned short *value);
 353
 354 /*
 355  * Caller holds hw_lock.
 356  */
 357 static void fm93c56a_select(struct ql3_adapter *qdev)
 358 {
 359         struct ql3xxx_port_registers __iomem *port_regs =
 360                         qdev->mem_map_registers;
 361
 362         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
 363         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 364                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 365         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 366                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
 367 }
 368
 369 /*
 370  * Caller holds hw_lock.
 371  */
 372 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
 373 {
 374         int i;
 375         u32 mask;
 376         u32 dataBit;
 377         u32 previousBit;
 378         struct ql3xxx_port_registers __iomem *port_regs =
 379                         qdev->mem_map_registers;
 380
 381         /* Clock in a zero, then do the start bit */
 382         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 383                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 384                             AUBURN_EEPROM_DO_1);
 385         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 386                             ISP_NVRAM_MASK | qdev->
 387                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 388                             AUBURN_EEPROM_CLK_RISE);
 389         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 390                             ISP_NVRAM_MASK | qdev->
 391                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 392                             AUBURN_EEPROM_CLK_FALL);
 393
 394         mask = 1 << (FM93C56A_CMD_BITS - 1);
 395         /* Force the previous data bit to be different */
 396         previousBit = 0xffff;
 397         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
 398                 dataBit =
 399                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
 400                 if (previousBit != dataBit) {
 401                         /*
 402                          * If the bit changed, then change the DO state to
 403                          * match
 404                          */
 405                         ql_write_nvram_reg(qdev,
 406                                             &port_regs->CommonRegs.
 407                                             serialPortInterfaceReg,
 408                                             ISP_NVRAM_MASK | qdev->
 409                                             eeprom_cmd_data | dataBit);
 410                         previousBit = dataBit;
 411                 }
 412                 ql_write_nvram_reg(qdev,
 413                                     &port_regs->CommonRegs.
 414                                     serialPortInterfaceReg,
 415                                     ISP_NVRAM_MASK | qdev->
 416                                     eeprom_cmd_data | dataBit |
 417                                     AUBURN_EEPROM_CLK_RISE);
 418                 ql_write_nvram_reg(qdev,
 419                                     &port_regs->CommonRegs.
 420                                     serialPortInterfaceReg,
 421                                     ISP_NVRAM_MASK | qdev->
 422                                     eeprom_cmd_data | dataBit |
 423                                     AUBURN_EEPROM_CLK_FALL);
 424                 cmd = cmd << 1;
 425         }
 426
 427         mask = 1 << (addrBits - 1);
 428         /* Force the previous data bit to be different */
 429         previousBit = 0xffff;
 430         for (i = 0; i < addrBits; i++) {
 431                 dataBit =
 432                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
 433                     AUBURN_EEPROM_DO_0;
 434                 if (previousBit != dataBit) {
 435                         /*
 436                          * If the bit changed, then change the DO state to
 437                          * match
 438                          */
 439                         ql_write_nvram_reg(qdev,
 440                                             &port_regs->CommonRegs.
 441                                             serialPortInterfaceReg,
 442                                             ISP_NVRAM_MASK | qdev->
 443                                             eeprom_cmd_data | dataBit);
 444                         previousBit = dataBit;
 445                 }
 446                 ql_write_nvram_reg(qdev,
 447                                     &port_regs->CommonRegs.
 448                                     serialPortInterfaceReg,
 449                                     ISP_NVRAM_MASK | qdev->
 450                                     eeprom_cmd_data | dataBit |
 451                                     AUBURN_EEPROM_CLK_RISE);
 452                 ql_write_nvram_reg(qdev,
 453                                     &port_regs->CommonRegs.
 454                                     serialPortInterfaceReg,
 455                                     ISP_NVRAM_MASK | qdev->
 456                                     eeprom_cmd_data | dataBit |
 457                                     AUBURN_EEPROM_CLK_FALL);
 458                 eepromAddr = eepromAddr << 1;
 459         }
 460 }
 461
 462 /*
 463  * Caller holds hw_lock.
 464  */
 465 static void fm93c56a_deselect(struct ql3_adapter *qdev)
 466 {
 467         struct ql3xxx_port_registers __iomem *port_regs =
 468                         qdev->mem_map_registers;
 469         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
 470         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 471                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 472 }
 473
 474 /*
 475  * Caller holds hw_lock.
 476  */
 477 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
 478 {
 479         int i;
 480         u32 data = 0;
 481         u32 dataBit;
 482         struct ql3xxx_port_registers __iomem *port_regs =
 483                         qdev->mem_map_registers;
 484
 485         /* Read the data bits */
 486         /* The first bit is a dummy.  Clock right over it. */
 487         for (i = 0; i < dataBits; i++) {
 488                 ql_write_nvram_reg(qdev,
 489                                     &port_regs->CommonRegs.
 490                                     serialPortInterfaceReg,
 491                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 492                                     AUBURN_EEPROM_CLK_RISE);
 493                 ql_write_nvram_reg(qdev,
 494                                     &port_regs->CommonRegs.
 495                                     serialPortInterfaceReg,
 496                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 497                                     AUBURN_EEPROM_CLK_FALL);
 498                 dataBit =
 499                     (ql_read_common_reg
 500                      (qdev,
 501                       &port_regs->CommonRegs.
 502                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
 503                 data = (data << 1) | dataBit;
 504         }
 505         *value = (u16) data;
 506 }
 507
 508 /*
 509  * Caller holds hw_lock.
 510  */
 511 static void eeprom_readword(struct ql3_adapter *qdev,
 512                             u32 eepromAddr, unsigned short *value)
 513 {
 514         fm93c56a_select(qdev);
 515         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
 516         fm93c56a_datain(qdev, value);
 517         fm93c56a_deselect(qdev);
 518 }
 519
 520 static void ql_swap_mac_addr(u8 * macAddress)
 521 {
 522 #ifdef __BIG_ENDIAN
 523         u8 temp;
 524         temp = macAddress[0];
 525         macAddress[0] = macAddress[1];
 526         macAddress[1] = temp;
 527         temp = macAddress[2];
 528         macAddress[2] = macAddress[3];
 529         macAddress[3] = temp;
 530         temp = macAddress[4];
 531         macAddress[4] = macAddress[5];
 532         macAddress[5] = temp;
 533 #endif
 534 }
 535
 536 static int ql_get_nvram_params(struct ql3_adapter *qdev)
 537 {
 538         u16 *pEEPROMData;
 539         u16 checksum = 0;
 540         u32 index;
 541         unsigned long hw_flags;
 542
 543         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 544
 545         pEEPROMData = (u16 *) & qdev->nvram_data;
 546         qdev->eeprom_cmd_data = 0;
 547         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
 548                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
 549                          2) << 10)) {
 550                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
 551                         __func__);
 552                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 553                 return -1;
 554         }
 555
 556         for (index = 0; index < EEPROM_SIZE; index++) {
 557                 eeprom_readword(qdev, index, pEEPROMData);
 558                 checksum += *pEEPROMData;
 559                 pEEPROMData++;
 560         }
 561         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
 562
 563         if (checksum != 0) {
 564                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
 565                        qdev->ndev->name, checksum);
 566                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 567                 return -1;
 568         }
 569
 570         /*
 571          * We have a problem with endianness for the MAC addresses
 572          * and the two 8-bit values version, and numPorts.  We
 573          * have to swap them on big endian systems.
 574          */
 575         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
 576         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
 577         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
 578         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
 579         pEEPROMData = (u16 *) & qdev->nvram_data.version;
 580         *pEEPROMData = le16_to_cpu(*pEEPROMData);
 581
 582         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 583         return checksum;
 584 }
 585
 586 static const u32 PHYAddr[2] = {
 587         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
 588 };
 589
 590 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
 591 {
 592         struct ql3xxx_port_registers __iomem *port_regs =
 593                         qdev->mem_map_registers;
 594         u32 temp;
 595         int count = 1000;
 596
 597         while (count) {
 598                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
 599                 if (!(temp & MAC_MII_STATUS_BSY))
 600                         return 0;
 601                 udelay(10);
 602                 count--;
 603         }
 604         return -1;
 605 }
 606
 607 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
 608 {
 609         struct ql3xxx_port_registers __iomem *port_regs =
 610                         qdev->mem_map_registers;
 611         u32 scanControl;
 612
 613         if (qdev->numPorts > 1) {
 614                 /* Auto scan will cycle through multiple ports */
 615                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
 616         } else {
 617                 scanControl = MAC_MII_CONTROL_SC;
 618         }
 619
 620         /*
 621          * Scan register 1 of PHY/PETBI,
 622          * Set up to scan both devices
 623          * The autoscan starts from the first register, completes
 624          * the last one before rolling over to the first
 625          */
 626         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 627                            PHYAddr[0] | MII_SCAN_REGISTER);
 628
 629         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 630                            (scanControl) |
 631                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
 632 }
 633
 634 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
 635 {
 636         u8 ret;
 637         struct ql3xxx_port_registers __iomem *port_regs =
 638                                         qdev->mem_map_registers;
 639
 640         /* See if scan mode is enabled before we turn it off */
 641         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
 642             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
 643                 /* Scan is enabled */
 644                 ret = 1;
 645         } else {
 646                 /* Scan is disabled */
 647                 ret = 0;
 648         }
 649
 650         /*
 651          * When disabling scan mode you must first change the MII register
 652          * address
 653          */
 654         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 655                            PHYAddr[0] | MII_SCAN_REGISTER);
 656
 657         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 658                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
 659                              MAC_MII_CONTROL_RC) << 16));
 660
 661         return ret;
 662 }
 663
 664 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
 665                                u16 regAddr, u16 value, u32 mac_index)
 666 {
 667         struct ql3xxx_port_registers __iomem *port_regs =
 668                         qdev->mem_map_registers;
 669         u8 scanWasEnabled;
 670
 671         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 672
 673         if (ql_wait_for_mii_ready(qdev)) {
 674                 if (netif_msg_link(qdev))
 675                         printk(KERN_WARNING PFX
 676                                "%s Timed out waiting for management port to "
 677                                "get free before issuing command.\n",
 678                                qdev->ndev->name);
 679                 return -1;
 680         }
 681
 682         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 683                            PHYAddr[mac_index] | regAddr);
 684
 685         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 686
 687         /* Wait for write to complete 9/10/04 SJP */
 688         if (ql_wait_for_mii_ready(qdev)) {
 689                 if (netif_msg_link(qdev))
 690                         printk(KERN_WARNING PFX
 691                                "%s: Timed out waiting for management port to"
 692                                "get free before issuing command.\n",
 693                                qdev->ndev->name);
 694                 return -1;
 695         }
 696
 697         if (scanWasEnabled)
 698                 ql_mii_enable_scan_mode(qdev);
 699
 700         return 0;
 701 }
 702
 703 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
 704                               u16 * value, u32 mac_index)
 705 {
 706         struct ql3xxx_port_registers __iomem *port_regs =
 707                         qdev->mem_map_registers;
 708         u8 scanWasEnabled;
 709         u32 temp;
 710
 711         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 712
 713         if (ql_wait_for_mii_ready(qdev)) {
 714                 if (netif_msg_link(qdev))
 715                         printk(KERN_WARNING PFX
 716                                "%s: Timed out waiting for management port to "
 717                                "get free before issuing command.\n",
 718                                qdev->ndev->name);
 719                 return -1;
 720         }
 721
 722         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 723                            PHYAddr[mac_index] | regAddr);
 724
 725         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 726                            (MAC_MII_CONTROL_RC << 16));
 727
 728         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 729                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 730
 731         /* Wait for the read to complete */
 732         if (ql_wait_for_mii_ready(qdev)) {
 733                 if (netif_msg_link(qdev))
 734                         printk(KERN_WARNING PFX
 735                                "%s: Timed out waiting for management port to "
 736                                "get free after issuing command.\n",
 737                                qdev->ndev->name);
 738                 return -1;
 739         }
 740
 741         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 742         *value = (u16) temp;
 743
 744         if (scanWasEnabled)
 745                 ql_mii_enable_scan_mode(qdev);
 746
 747         return 0;
 748 }
 749
 750 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
 751 {
 752         struct ql3xxx_port_registers __iomem *port_regs =
 753                         qdev->mem_map_registers;
 754
 755         ql_mii_disable_scan_mode(qdev);
 756
 757         if (ql_wait_for_mii_ready(qdev)) {
 758                 if (netif_msg_link(qdev))
 759                         printk(KERN_WARNING PFX
 760                                "%s: Timed out waiting for management port to "
 761                                "get free before issuing command.\n",
 762                                qdev->ndev->name);
 763                 return -1;
 764         }
 765
 766         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 767                            qdev->PHYAddr | regAddr);
 768
 769         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 770
 771         /* Wait for write to complete. */
 772         if (ql_wait_for_mii_ready(qdev)) {
 773                 if (netif_msg_link(qdev))
 774                         printk(KERN_WARNING PFX
 775                                "%s: Timed out waiting for management port to "
 776                                "get free before issuing command.\n",
 777                                qdev->ndev->name);
 778                 return -1;
 779         }
 780
 781         ql_mii_enable_scan_mode(qdev);
 782
 783         return 0;
 784 }
 785
 786 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
 787 {
 788         u32 temp;
 789         struct ql3xxx_port_registers __iomem *port_regs =
 790                         qdev->mem_map_registers;
 791
 792         ql_mii_disable_scan_mode(qdev);
 793
 794         if (ql_wait_for_mii_ready(qdev)) {
 795                 if (netif_msg_link(qdev))
 796                         printk(KERN_WARNING PFX
 797                                "%s: Timed out waiting for management port to "
 798                                "get free before issuing command.\n",
 799                                qdev->ndev->name);
 800                 return -1;
 801         }
 802
 803         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 804                            qdev->PHYAddr | regAddr);
 805
 806         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 807                            (MAC_MII_CONTROL_RC << 16));
 808
 809         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 810                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 811
 812         /* Wait for the read to complete */
 813         if (ql_wait_for_mii_ready(qdev)) {
 814                 if (netif_msg_link(qdev))
 815                         printk(KERN_WARNING PFX
 816                                "%s: Timed out waiting for management port to "
 817                                "get free before issuing command.\n",
 818                                qdev->ndev->name);
 819                 return -1;
 820         }
 821
 822         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 823         *value = (u16) temp;
 824
 825         ql_mii_enable_scan_mode(qdev);
 826
 827         return 0;
 828 }
 829
 830 static void ql_petbi_reset(struct ql3_adapter *qdev)
 831 {
 832         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
 833 }
 834
 835 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
 836 {
 837         u16 reg;
 838
 839         /* Enable Auto-negotiation sense */
 840         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
 841         reg |= PETBI_TBI_AUTO_SENSE;
 842         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
 843
 844         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
 845                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
 846
 847         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
 848                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 849                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
 850
 851 }
 852
 853 static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
 854 {
 855         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
 856                             mac_index);
 857 }
 858
 859 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
 860 {
 861         u16 reg;
 862
 863         /* Enable Auto-negotiation sense */
 864         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
 865         reg |= PETBI_TBI_AUTO_SENSE;
 866         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
 867
 868         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
 869                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
 870
 871         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
 872                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 873                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
 874                             mac_index);
 875 }
 876
 877 static void ql_petbi_init(struct ql3_adapter *qdev)
 878 {
 879         ql_petbi_reset(qdev);
 880         ql_petbi_start_neg(qdev);
 881 }
 882
 883 static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
 884 {
 885         ql_petbi_reset_ex(qdev, mac_index);
 886         ql_petbi_start_neg_ex(qdev, mac_index);
 887 }
 888
 889 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
 890 {
 891         u16 reg;
 892
 893         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
 894                 return 0;
 895
 896         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
 897 }
 898
 899 static int ql_phy_get_speed(struct ql3_adapter *qdev)
 900 {
 901         u16 reg;
 902
 903         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
 904                 return 0;
 905
 906         reg = (((reg & 0x18) >> 3) & 3);
 907
 908         if (reg == 2)
 909                 return SPEED_1000;
 910         else if (reg == 1)
 911                 return SPEED_100;
 912         else if (reg == 0)
 913                 return SPEED_10;
 914         else
 915                 return -1;
 916 }
 917
 918 static int ql_is_full_dup(struct ql3_adapter *qdev)
 919 {
 920         u16 reg;
 921
 922         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
 923                 return 0;
 924
 925         return (reg & PHY_AUX_DUPLEX_STAT) != 0;
 926 }
 927
 928 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
 929 {
 930         u16 reg;
 931
 932         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
 933                 return 0;
 934
 935         return (reg & PHY_NEG_PAUSE) != 0;
 936 }
 937
 938 /*
 939  * Caller holds hw_lock.
 940  */
 941 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
 942 {
 943         struct ql3xxx_port_registers __iomem *port_regs =
 944                         qdev->mem_map_registers;
 945         u32 value;
 946
 947         if (enable)
 948                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
 949         else
 950                 value = (MAC_CONFIG_REG_PE << 16);
 951
 952         if (qdev->mac_index)
 953                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 954         else
 955                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 956 }
 957
 958 /*
 959  * Caller holds hw_lock.
 960  */
 961 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
 962 {
 963         struct ql3xxx_port_registers __iomem *port_regs =
 964                         qdev->mem_map_registers;
 965         u32 value;
 966
 967         if (enable)
 968                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
 969         else
 970                 value = (MAC_CONFIG_REG_SR << 16);
 971
 972         if (qdev->mac_index)
 973                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 974         else
 975                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 976 }
 977
 978 /*
 979  * Caller holds hw_lock.
 980  */
 981 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
 982 {
 983         struct ql3xxx_port_registers __iomem *port_regs =
 984                         qdev->mem_map_registers;
 985         u32 value;
 986
 987         if (enable)
 988                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
 989         else
 990                 value = (MAC_CONFIG_REG_GM << 16);
 991
 992         if (qdev->mac_index)
 993                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 994         else
 995                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 996 }
 997
 998 /*
 999  * Caller holds hw_lock.
1000  */
1001 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1002 {
1003         struct ql3xxx_port_registers __iomem *port_regs =
1004                         qdev->mem_map_registers;
1005         u32 value;
1006
1007         if (enable)
1008                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1009         else
1010                 value = (MAC_CONFIG_REG_FD << 16);
1011
1012         if (qdev->mac_index)
1013                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1014         else
1015                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1016 }
1017
1018 /*
1019  * Caller holds hw_lock.
1020  */
1021 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1022 {
1023         struct ql3xxx_port_registers __iomem *port_regs =
1024                         qdev->mem_map_registers;
1025         u32 value;
1026
1027         if (enable)
1028                 value =
1029                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1030                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1031         else
1032                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1033
1034         if (qdev->mac_index)
1035                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1036         else
1037                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1038 }
1039
1040 /*
1041  * Caller holds hw_lock.
1042  */
1043 static int ql_is_fiber(struct ql3_adapter *qdev)
1044 {
1045         struct ql3xxx_port_registers __iomem *port_regs =
1046                         qdev->mem_map_registers;
1047         u32 bitToCheck = 0;
1048         u32 temp;
1049
1050         switch (qdev->mac_index) {
1051         case 0:
1052                 bitToCheck = PORT_STATUS_SM0;
1053                 break;
1054         case 1:
1055                 bitToCheck = PORT_STATUS_SM1;
1056                 break;
1057         }
1058
1059         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1060         return (temp & bitToCheck) != 0;
1061 }
1062
1063 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1064 {
1065         u16 reg;
1066         ql_mii_read_reg(qdev, 0x00, &reg);
1067         return (reg & 0x1000) != 0;
1068 }
1069
1070 /*
1071  * Caller holds hw_lock.
1072  */
1073 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1074 {
1075         struct ql3xxx_port_registers __iomem *port_regs =
1076                         qdev->mem_map_registers;
1077         u32 bitToCheck = 0;
1078         u32 temp;
1079
1080         switch (qdev->mac_index) {
1081         case 0:
1082                 bitToCheck = PORT_STATUS_AC0;
1083                 break;
1084         case 1:
1085                 bitToCheck = PORT_STATUS_AC1;
1086                 break;
1087         }
1088
1089         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1090         if (temp & bitToCheck) {
1091                 if (netif_msg_link(qdev))
1092                         printk(KERN_INFO PFX
1093                                "%s: Auto-Negotiate complete.\n",
1094                                qdev->ndev->name);
1095                 return 1;
1096         } else {
1097                 if (netif_msg_link(qdev))
1098                         printk(KERN_WARNING PFX
1099                                "%s: Auto-Negotiate incomplete.\n",
1100                                qdev->ndev->name);
1101                 return 0;
1102         }
1103 }
1104
1105 /*
1106  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1107  */
1108 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1109 {
1110         if (ql_is_fiber(qdev))
1111                 return ql_is_petbi_neg_pause(qdev);
1112         else
1113                 return ql_is_phy_neg_pause(qdev);
1114 }
1115
1116 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1117 {
1118         struct ql3xxx_port_registers __iomem *port_regs =
1119                         qdev->mem_map_registers;
1120         u32 bitToCheck = 0;
1121         u32 temp;
1122
1123         switch (qdev->mac_index) {
1124         case 0:
1125                 bitToCheck = PORT_STATUS_AE0;
1126                 break;
1127         case 1:
1128                 bitToCheck = PORT_STATUS_AE1;
1129                 break;
1130         }
1131         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1132         return (temp & bitToCheck) != 0;
1133 }
1134
1135 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1136 {
1137         if (ql_is_fiber(qdev))
1138                 return SPEED_1000;
1139         else
1140                 return ql_phy_get_speed(qdev);
1141 }
1142
1143 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1144 {
1145         if (ql_is_fiber(qdev))
1146                 return 1;
1147         else
1148                 return ql_is_full_dup(qdev);
1149 }
1150
1151 /*
1152  * Caller holds hw_lock.
1153  */
1154 static int ql_link_down_detect(struct ql3_adapter *qdev)
1155 {
1156         struct ql3xxx_port_registers __iomem *port_regs =
1157                         qdev->mem_map_registers;
1158         u32 bitToCheck = 0;
1159         u32 temp;
1160
1161         switch (qdev->mac_index) {
1162         case 0:
1163                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1164                 break;
1165         case 1:
1166                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1167                 break;
1168         }
1169
1170         temp =
1171             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1172         return (temp & bitToCheck) != 0;
1173 }
1174
1175 /*
1176  * Caller holds hw_lock.
1177  */
1178 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1179 {
1180         struct ql3xxx_port_registers __iomem *port_regs =
1181                         qdev->mem_map_registers;
1182
1183         switch (qdev->mac_index) {
1184         case 0:
1185                 ql_write_common_reg(qdev,
1186                                     &port_regs->CommonRegs.ispControlStatus,
1187                                     (ISP_CONTROL_LINK_DN_0) |
1188                                     (ISP_CONTROL_LINK_DN_0 << 16));
1189                 break;
1190
1191         case 1:
1192                 ql_write_common_reg(qdev,
1193                                     &port_regs->CommonRegs.ispControlStatus,
1194                                     (ISP_CONTROL_LINK_DN_1) |
1195                                     (ISP_CONTROL_LINK_DN_1 << 16));
1196                 break;
1197
1198         default:
1199                 return 1;
1200         }
1201
1202         return 0;
1203 }
1204
1205 /*
1206  * Caller holds hw_lock.
1207  */
1208 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1209                                          u32 mac_index)
1210 {
1211         struct ql3xxx_port_registers __iomem *port_regs =
1212                         qdev->mem_map_registers;
1213         u32 bitToCheck = 0;
1214         u32 temp;
1215
1216         switch (mac_index) {
1217         case 0:
1218                 bitToCheck = PORT_STATUS_F1_ENABLED;
1219                 break;
1220         case 1:
1221                 bitToCheck = PORT_STATUS_F3_ENABLED;
1222                 break;
1223         default:
1224                 break;
1225         }
1226
1227         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1228         if (temp & bitToCheck) {
1229                 if (netif_msg_link(qdev))
1230                         printk(KERN_DEBUG PFX
1231                                "%s: is not link master.\n", qdev->ndev->name);
1232                 return 0;
1233         } else {
1234                 if (netif_msg_link(qdev))
1235                         printk(KERN_DEBUG PFX
1236                                "%s: is link master.\n", qdev->ndev->name);
1237                 return 1;
1238         }
1239 }
1240
1241 static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1242 {
1243         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1244 }
1245
1246 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1247 {
1248         u16 reg;
1249
1250         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1251                             PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1252
1253         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1254         ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1255                             mac_index);
1256 }
1257
1258 static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1259 {
1260         ql_phy_reset_ex(qdev, mac_index);
1261         ql_phy_start_neg_ex(qdev, mac_index);
1262 }
1263
1264 /*
1265  * Caller holds hw_lock.
1266  */
1267 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1268 {
1269         struct ql3xxx_port_registers __iomem *port_regs =
1270                         qdev->mem_map_registers;
1271         u32 bitToCheck = 0;
1272         u32 temp, linkState;
1273
1274         switch (qdev->mac_index) {
1275         case 0:
1276                 bitToCheck = PORT_STATUS_UP0;
1277                 break;
1278         case 1:
1279                 bitToCheck = PORT_STATUS_UP1;
1280                 break;
1281         }
1282         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1283         if (temp & bitToCheck) {
1284                 linkState = LS_UP;
1285         } else {
1286                 linkState = LS_DOWN;
1287                 if (netif_msg_link(qdev))
1288                         printk(KERN_WARNING PFX
1289                                "%s: Link is down.\n", qdev->ndev->name);
1290         }
1291         return linkState;
1292 }
1293
1294 static int ql_port_start(struct ql3_adapter *qdev)
1295 {
1296         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1297                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1298                          2) << 7))
1299                 return -1;
1300
1301         if (ql_is_fiber(qdev)) {
1302                 ql_petbi_init(qdev);
1303         } else {
1304                 /* Copper port */
1305                 ql_phy_init_ex(qdev, qdev->mac_index);
1306         }
1307
1308         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1309         return 0;
1310 }
1311
1312 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1313 {
1314
1315         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1316                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1317                          2) << 7))
1318                 return -1;
1319
1320         if (!ql_auto_neg_error(qdev)) {
1321                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1322                         /* configure the MAC */
1323                         if (netif_msg_link(qdev))
1324                                 printk(KERN_DEBUG PFX
1325                                        "%s: Configuring link.\n",
1326                                        qdev->ndev->
1327                                        name);
1328                         ql_mac_cfg_soft_reset(qdev, 1);
1329                         ql_mac_cfg_gig(qdev,
1330                                        (ql_get_link_speed
1331                                         (qdev) ==
1332                                         SPEED_1000));
1333                         ql_mac_cfg_full_dup(qdev,
1334                                             ql_is_link_full_dup
1335                                             (qdev));
1336                         ql_mac_cfg_pause(qdev,
1337                                          ql_is_neg_pause
1338                                          (qdev));
1339                         ql_mac_cfg_soft_reset(qdev, 0);
1340
1341                         /* enable the MAC */
1342                         if (netif_msg_link(qdev))
1343                                 printk(KERN_DEBUG PFX
1344                                        "%s: Enabling mac.\n",
1345                                        qdev->ndev->
1346                                                name);
1347                         ql_mac_enable(qdev, 1);
1348                 }
1349
1350                 if (netif_msg_link(qdev))
1351                         printk(KERN_DEBUG PFX
1352                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1353                                qdev->ndev->name);
1354                 qdev->port_link_state = LS_UP;
1355                 netif_start_queue(qdev->ndev);
1356                 netif_carrier_on(qdev->ndev);
1357                 if (netif_msg_link(qdev))
1358                         printk(KERN_INFO PFX
1359                                "%s: Link is up at %d Mbps, %s duplex.\n",
1360                                qdev->ndev->name,
1361                                ql_get_link_speed(qdev),
1362                                ql_is_link_full_dup(qdev)
1363                                ? "full" : "half");
1364
1365         } else {        /* Remote error detected */
1366
1367                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1368                         if (netif_msg_link(qdev))
1369                                 printk(KERN_DEBUG PFX
1370                                        "%s: Remote error detected. "
1371                                        "Calling ql_port_start().\n",
1372                                        qdev->ndev->
1373                                        name);
1374                         /*
1375                          * ql_port_start() is shared code and needs
1376                          * to lock the PHY on it's own.
1377                          */
1378                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1379                         if(ql_port_start(qdev)) {/* Restart port */
1380                                 return -1;
1381                         } else
1382                                 return 0;
1383                 }
1384         }
1385         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1386         return 0;
1387 }
1388
1389 static void ql_link_state_machine(struct ql3_adapter *qdev)
1390 {
1391         u32 curr_link_state;
1392         unsigned long hw_flags;
1393
1394         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1395
1396         curr_link_state = ql_get_link_state(qdev);
1397
1398         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1399                 if (netif_msg_link(qdev))
1400                         printk(KERN_INFO PFX
1401                                "%s: Reset in progress, skip processing link "
1402                                "state.\n", qdev->ndev->name);
1403
1404                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1405                 return;
1406         }
1407
1408         switch (qdev->port_link_state) {
1409         default:
1410                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1411                         ql_port_start(qdev);
1412                 }
1413                 qdev->port_link_state = LS_DOWN;
1414                 /* Fall Through */
1415
1416         case LS_DOWN:
1417                 if (netif_msg_link(qdev))
1418                         printk(KERN_DEBUG PFX
1419                                "%s: port_link_state = LS_DOWN.\n",
1420                                qdev->ndev->name);
1421                 if (curr_link_state == LS_UP) {
1422                         if (netif_msg_link(qdev))
1423                                 printk(KERN_DEBUG PFX
1424                                        "%s: curr_link_state = LS_UP.\n",
1425                                        qdev->ndev->name);
1426                         if (ql_is_auto_neg_complete(qdev))
1427                                 ql_finish_auto_neg(qdev);
1428
1429                         if (qdev->port_link_state == LS_UP)
1430                                 ql_link_down_detect_clear(qdev);
1431
1432                 }
1433                 break;
1434
1435         case LS_UP:
1436                 /*
1437                  * See if the link is currently down or went down and came
1438                  * back up
1439                  */
1440                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1441                         if (netif_msg_link(qdev))
1442                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1443                                        qdev->ndev->name);
1444                         qdev->port_link_state = LS_DOWN;
1445                 }
1446                 break;
1447         }
1448         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1449 }
1450
1451 /*
1452  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1453  */
1454 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1455 {
1456         if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1457                 set_bit(QL_LINK_MASTER,&qdev->flags);
1458         else
1459                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1460 }
1461
1462 /*
1463  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1464  */
1465 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1466 {
1467         ql_mii_enable_scan_mode(qdev);
1468
1469         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1470                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1471                         ql_petbi_init_ex(qdev, qdev->mac_index);
1472         } else {
1473                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1474                         ql_phy_init_ex(qdev, qdev->mac_index);
1475         }
1476 }
1477
1478 /*
1479  * MII_Setup needs to be called before taking the PHY out of reset so that the
1480  * management interface clock speed can be set properly.  It would be better if
1481  * we had a way to disable MDC until after the PHY is out of reset, but we
1482  * don't have that capability.
1483  */
1484 static int ql_mii_setup(struct ql3_adapter *qdev)
1485 {
1486         u32 reg;
1487         struct ql3xxx_port_registers __iomem *port_regs =
1488                         qdev->mem_map_registers;
1489
1490         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1491                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1492                          2) << 7))
1493                 return -1;
1494
1495         if (qdev->device_id == QL3032_DEVICE_ID)
1496                 ql_write_page0_reg(qdev,
1497                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1498
1499         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1500         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1501
1502         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1503                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1504
1505         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1506         return 0;
1507 }
1508
1509 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1510 {
1511         u32 supported;
1512
1513         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1514                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1515                     | SUPPORTED_Autoneg;
1516         } else {
1517                 supported = SUPPORTED_10baseT_Half
1518                     | SUPPORTED_10baseT_Full
1519                     | SUPPORTED_100baseT_Half
1520                     | SUPPORTED_100baseT_Full
1521                     | SUPPORTED_1000baseT_Half
1522                     | SUPPORTED_1000baseT_Full
1523                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1524         }
1525
1526         return supported;
1527 }
1528
1529 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1530 {
1531         int status;
1532         unsigned long hw_flags;
1533         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1534         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1535                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1536                          2) << 7)) {
1537                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1538                 return 0;
1539         }
1540         status = ql_is_auto_cfg(qdev);
1541         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1542         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1543         return status;
1544 }
1545
1546 static u32 ql_get_speed(struct ql3_adapter *qdev)
1547 {
1548         u32 status;
1549         unsigned long hw_flags;
1550         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1551         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1552                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1553                          2) << 7)) {
1554                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1555                 return 0;
1556         }
1557         status = ql_get_link_speed(qdev);
1558         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1559         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1560         return status;
1561 }
1562
1563 static int ql_get_full_dup(struct ql3_adapter *qdev)
1564 {
1565         int status;
1566         unsigned long hw_flags;
1567         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1568         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1569                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1570                          2) << 7)) {
1571                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1572                 return 0;
1573         }
1574         status = ql_is_link_full_dup(qdev);
1575         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1576         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1577         return status;
1578 }
1579
1580
1581 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1582 {
1583         struct ql3_adapter *qdev = netdev_priv(ndev);
1584
1585         ecmd->transceiver = XCVR_INTERNAL;
1586         ecmd->supported = ql_supported_modes(qdev);
1587
1588         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1589                 ecmd->port = PORT_FIBRE;
1590         } else {
1591                 ecmd->port = PORT_TP;
1592                 ecmd->phy_address = qdev->PHYAddr;
1593         }
1594         ecmd->advertising = ql_supported_modes(qdev);
1595         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1596         ecmd->speed = ql_get_speed(qdev);
1597         ecmd->duplex = ql_get_full_dup(qdev);
1598         return 0;
1599 }
1600
1601 static void ql_get_drvinfo(struct net_device *ndev,
1602                            struct ethtool_drvinfo *drvinfo)
1603 {
1604         struct ql3_adapter *qdev = netdev_priv(ndev);
1605         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1606         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1607         strncpy(drvinfo->fw_version, "N/A", 32);
1608         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1609         drvinfo->n_stats = 0;
1610         drvinfo->testinfo_len = 0;
1611         drvinfo->regdump_len = 0;
1612         drvinfo->eedump_len = 0;
1613 }
1614
1615 static u32 ql_get_msglevel(struct net_device *ndev)
1616 {
1617         struct ql3_adapter *qdev = netdev_priv(ndev);
1618         return qdev->msg_enable;
1619 }
1620
1621 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1622 {
1623         struct ql3_adapter *qdev = netdev_priv(ndev);
1624         qdev->msg_enable = value;
1625 }
1626
1627 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1628         .get_settings = ql_get_settings,
1629         .get_drvinfo = ql_get_drvinfo,
1630         .get_perm_addr = ethtool_op_get_perm_addr,
1631         .get_link = ethtool_op_get_link,
1632         .get_msglevel = ql_get_msglevel,
1633         .set_msglevel = ql_set_msglevel,
1634 };
1635
1636 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1637 {
1638         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1639         dma_addr_t map;
1640         int err;
1641
1642         while (lrg_buf_cb) {
1643                 if (!lrg_buf_cb->skb) {
1644                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1645                                                            qdev->lrg_buffer_len);
1646                         if (unlikely(!lrg_buf_cb->skb)) {
1647                                 printk(KERN_DEBUG PFX
1648                                        "%s: Failed netdev_alloc_skb().\n",
1649                                        qdev->ndev->name);
1650                                 break;
1651                         } else {
1652                                 /*
1653                                  * We save some space to copy the ethhdr from
1654                                  * first buffer
1655                                  */
1656                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1657                                 map = pci_map_single(qdev->pdev,
1658                                                      lrg_buf_cb->skb->data,
1659                                                      qdev->lrg_buffer_len -
1660                                                      QL_HEADER_SPACE,
1661                                                      PCI_DMA_FROMDEVICE);
1662
1663                                 err = pci_dma_mapping_error(map);
1664                                 if(err) {
1665                                         printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1666                                                qdev->ndev->name, err);
1667                                         dev_kfree_skb(lrg_buf_cb->skb);
1668                                         lrg_buf_cb->skb = NULL;
1669                                         break;
1670                                 }
1671
1672
1673                                 lrg_buf_cb->buf_phy_addr_low =
1674                                     cpu_to_le32(LS_64BITS(map));
1675                                 lrg_buf_cb->buf_phy_addr_high =
1676                                     cpu_to_le32(MS_64BITS(map));
1677                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1678                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1679                                                   qdev->lrg_buffer_len -
1680                                                   QL_HEADER_SPACE);
1681                                 --qdev->lrg_buf_skb_check;
1682                                 if (!qdev->lrg_buf_skb_check)
1683                                         return 1;
1684                         }
1685                 }
1686                 lrg_buf_cb = lrg_buf_cb->next;
1687         }
1688         return 0;
1689 }
1690
1691 /*
1692  * Caller holds hw_lock.
1693  */
1694 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1695 {
1696         struct bufq_addr_element *lrg_buf_q_ele;
1697         int i;
1698         struct ql_rcv_buf_cb *lrg_buf_cb;
1699         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1700
1701         if ((qdev->lrg_buf_free_count >= 8)
1702             && (qdev->lrg_buf_release_cnt >= 16)) {
1703
1704                 if (qdev->lrg_buf_skb_check)
1705                         if (!ql_populate_free_queue(qdev))
1706                                 return;
1707
1708                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1709
1710                 while ((qdev->lrg_buf_release_cnt >= 16)
1711                        && (qdev->lrg_buf_free_count >= 8)) {
1712
1713                         for (i = 0; i < 8; i++) {
1714                                 lrg_buf_cb =
1715                                     ql_get_from_lrg_buf_free_list(qdev);
1716                                 lrg_buf_q_ele->addr_high =
1717                                     lrg_buf_cb->buf_phy_addr_high;
1718                                 lrg_buf_q_ele->addr_low =
1719                                     lrg_buf_cb->buf_phy_addr_low;
1720                                 lrg_buf_q_ele++;
1721
1722                                 qdev->lrg_buf_release_cnt--;
1723                         }
1724
1725                         qdev->lrg_buf_q_producer_index++;
1726
1727                         if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
1728                                 qdev->lrg_buf_q_producer_index = 0;
1729
1730                         if (qdev->lrg_buf_q_producer_index ==
1731                             (qdev->num_lbufq_entries - 1)) {
1732                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1733                         }
1734                 }
1735
1736                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1737
1738                 ql_write_common_reg(qdev,
1739                                     &port_regs->CommonRegs.
1740                                     rxLargeQProducerIndex,
1741                                     qdev->lrg_buf_q_producer_index);
1742         }
1743 }
1744
1745 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1746                                    struct ob_mac_iocb_rsp *mac_rsp)
1747 {
1748         struct ql_tx_buf_cb *tx_cb;
1749         int i;
1750
1751         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1752         pci_unmap_single(qdev->pdev,
1753                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
1754                          pci_unmap_len(&tx_cb->map[0], maplen),
1755                          PCI_DMA_TODEVICE);
1756         tx_cb->seg_count--;
1757         if (tx_cb->seg_count) {
1758                 for (i = 1; i < tx_cb->seg_count; i++) {
1759                         pci_unmap_page(qdev->pdev,
1760                                        pci_unmap_addr(&tx_cb->map[i],
1761                                                       mapaddr),
1762                                        pci_unmap_len(&tx_cb->map[i], maplen),
1763                                        PCI_DMA_TODEVICE);
1764                 }
1765         }
1766         qdev->stats.tx_packets++;
1767         qdev->stats.tx_bytes += tx_cb->skb->len;
1768         dev_kfree_skb_irq(tx_cb->skb);
1769         tx_cb->skb = NULL;
1770         atomic_inc(&qdev->tx_count);
1771 }
1772
1773 void ql_get_sbuf(struct ql3_adapter *qdev)
1774 {
1775         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1776                 qdev->small_buf_index = 0;
1777         qdev->small_buf_release_cnt++;
1778 }
1779
1780 struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1781 {
1782         struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1783         lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1784         qdev->lrg_buf_release_cnt++;
1785         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1786                 qdev->lrg_buf_index = 0;
1787         return(lrg_buf_cb);
1788 }
1789
1790 /*
1791  * The difference between 3022 and 3032 for inbound completions:
1792  * 3022 uses two buffers per completion.  The first buffer contains
1793  * (some) header info, the second the remainder of the headers plus
1794  * the data.  For this chip we reserve some space at the top of the
1795  * receive buffer so that the header info in buffer one can be
1796  * prepended to the buffer two.  Buffer two is the sent up while
1797  * buffer one is returned to the hardware to be reused.
1798  * 3032 receives all of it's data and headers in one buffer for a
1799  * simpler process.  3032 also supports checksum verification as
1800  * can be seen in ql_process_macip_rx_intr().
1801  */
1802 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1803                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1804 {
1805         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1806         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1807         struct sk_buff *skb;
1808         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1809
1810         /*
1811          * Get the inbound address list (small buffer).
1812          */
1813         ql_get_sbuf(qdev);
1814
1815         if (qdev->device_id == QL3022_DEVICE_ID)
1816                 lrg_buf_cb1 = ql_get_lbuf(qdev);
1817
1818         /* start of second buffer */
1819         lrg_buf_cb2 = ql_get_lbuf(qdev);
1820         skb = lrg_buf_cb2->skb;
1821
1822         qdev->stats.rx_packets++;
1823         qdev->stats.rx_bytes += length;
1824
1825         skb_put(skb, length);
1826         pci_unmap_single(qdev->pdev,
1827                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1828                          pci_unmap_len(lrg_buf_cb2, maplen),
1829                          PCI_DMA_FROMDEVICE);
1830         prefetch(skb->data);
1831         skb->dev = qdev->ndev;
1832         skb->ip_summed = CHECKSUM_NONE;
1833         skb->protocol = eth_type_trans(skb, qdev->ndev);
1834
1835         netif_receive_skb(skb);
1836         qdev->ndev->last_rx = jiffies;
1837         lrg_buf_cb2->skb = NULL;
1838
1839         if (qdev->device_id == QL3022_DEVICE_ID)
1840                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1841         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1842 }
1843
1844 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1845                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1846 {
1847         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1848         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1849         struct sk_buff *skb1 = NULL, *skb2;
1850         struct net_device *ndev = qdev->ndev;
1851         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1852         u16 size = 0;
1853
1854         /*
1855          * Get the inbound address list (small buffer).
1856          */
1857
1858         ql_get_sbuf(qdev);
1859
1860         if (qdev->device_id == QL3022_DEVICE_ID) {
1861                 /* start of first buffer on 3022 */
1862                 lrg_buf_cb1 = ql_get_lbuf(qdev);
1863                 skb1 = lrg_buf_cb1->skb;
1864                 size = ETH_HLEN;
1865                 if (*((u16 *) skb1->data) != 0xFFFF)
1866                         size += VLAN_ETH_HLEN - ETH_HLEN;
1867         }
1868
1869         /* start of second buffer */
1870         lrg_buf_cb2 = ql_get_lbuf(qdev);
1871         skb2 = lrg_buf_cb2->skb;
1872
1873         skb_put(skb2, length);  /* Just the second buffer length here. */
1874         pci_unmap_single(qdev->pdev,
1875                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1876                          pci_unmap_len(lrg_buf_cb2, maplen),
1877                          PCI_DMA_FROMDEVICE);
1878         prefetch(skb2->data);
1879
1880         skb2->ip_summed = CHECKSUM_NONE;
1881         if (qdev->device_id == QL3022_DEVICE_ID) {
1882                 /*
1883                  * Copy the ethhdr from first buffer to second. This
1884                  * is necessary for 3022 IP completions.
1885                  */
1886                 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1887         } else {
1888                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1889                 if (checksum &
1890                         (IB_IP_IOCB_RSP_3032_ICE |
1891                          IB_IP_IOCB_RSP_3032_CE |
1892                          IB_IP_IOCB_RSP_3032_NUC)) {
1893                         printk(KERN_ERR
1894                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
1895                                __func__,
1896                                ((checksum &
1897                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1898                                 "UDP"),checksum);
1899                 } else if (checksum & IB_IP_IOCB_RSP_3032_TCP) {
1900                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
1901                 }
1902         }
1903         skb2->dev = qdev->ndev;
1904         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1905
1906         netif_receive_skb(skb2);
1907         qdev->stats.rx_packets++;
1908         qdev->stats.rx_bytes += length;
1909         ndev->last_rx = jiffies;
1910         lrg_buf_cb2->skb = NULL;
1911
1912         if (qdev->device_id == QL3022_DEVICE_ID)
1913                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1914         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1915 }
1916
1917 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1918                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
1919 {
1920         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1921         struct net_rsp_iocb *net_rsp;
1922         struct net_device *ndev = qdev->ndev;
1923         unsigned long hw_flags;
1924         int work_done = 0;
1925
1926         /* While there are entries in the completion queue. */
1927         while ((cpu_to_le32(*(qdev->prsp_producer_index)) !=
1928                 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
1929
1930                 net_rsp = qdev->rsp_current;
1931                 switch (net_rsp->opcode) {
1932
1933                 case OPCODE_OB_MAC_IOCB_FN0:
1934                 case OPCODE_OB_MAC_IOCB_FN2:
1935                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1936                                                net_rsp);
1937                         (*tx_cleaned)++;
1938                         break;
1939
1940                 case OPCODE_IB_MAC_IOCB:
1941                 case OPCODE_IB_3032_MAC_IOCB:
1942                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1943                                                net_rsp);
1944                         (*rx_cleaned)++;
1945                         break;
1946
1947                 case OPCODE_IB_IP_IOCB:
1948                 case OPCODE_IB_3032_IP_IOCB:
1949                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1950                                                  net_rsp);
1951                         (*rx_cleaned)++;
1952                         break;
1953                 default:
1954                         {
1955                                 u32 *tmp = (u32 *) net_rsp;
1956                                 printk(KERN_ERR PFX
1957                                        "%s: Hit default case, not "
1958                                        "handled!\n"
1959                                        "        dropping the packet, opcode = "
1960                                        "%x.\n",
1961                                        ndev->name, net_rsp->opcode);
1962                                 printk(KERN_ERR PFX
1963                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1964                                        (unsigned long int)tmp[0],
1965                                        (unsigned long int)tmp[1],
1966                                        (unsigned long int)tmp[2],
1967                                        (unsigned long int)tmp[3]);
1968                         }
1969                 }
1970
1971                 qdev->rsp_consumer_index++;
1972
1973                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
1974                         qdev->rsp_consumer_index = 0;
1975                         qdev->rsp_current = qdev->rsp_q_virt_addr;
1976                 } else {
1977                         qdev->rsp_current++;
1978                 }
1979
1980                 work_done = *tx_cleaned + *rx_cleaned;
1981         }
1982
1983         if(work_done) {
1984                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1985
1986                 ql_update_lrg_bufq_prod_index(qdev);
1987
1988                 if (qdev->small_buf_release_cnt >= 16) {
1989                         while (qdev->small_buf_release_cnt >= 16) {
1990                                 qdev->small_buf_q_producer_index++;
1991
1992                                 if (qdev->small_buf_q_producer_index ==
1993                                     NUM_SBUFQ_ENTRIES)
1994                                         qdev->small_buf_q_producer_index = 0;
1995                                 qdev->small_buf_release_cnt -= 8;
1996                         }
1997
1998                         wmb();
1999                         ql_write_common_reg(qdev,
2000                                             &port_regs->CommonRegs.
2001                                             rxSmallQProducerIndex,
2002                                             qdev->small_buf_q_producer_index);
2003
2004                 }
2005
2006                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2007
2008                 if (unlikely(netif_queue_stopped(qdev->ndev))) {
2009                         if (netif_queue_stopped(qdev->ndev) &&
2010                             (atomic_read(&qdev->tx_count) >
2011                              (NUM_REQ_Q_ENTRIES / 4)))
2012                                 netif_wake_queue(qdev->ndev);
2013                 }
2014         }
2015
2016         return *tx_cleaned + *rx_cleaned;
2017 }
2018
2019 static int ql_poll(struct net_device *ndev, int *budget)
2020 {
2021         struct ql3_adapter *qdev = netdev_priv(ndev);
2022         int work_to_do = min(*budget, ndev->quota);
2023         int rx_cleaned = 0, tx_cleaned = 0;
2024         unsigned long hw_flags;
2025         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2026
2027         if (!netif_carrier_ok(ndev))
2028                 goto quit_polling;
2029
2030         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2031         *budget -= rx_cleaned;
2032         ndev->quota -= rx_cleaned;
2033
2034         if ((!tx_cleaned && !rx_cleaned) || !netif_running(ndev)) {
2035 quit_polling:
2036                 netif_rx_complete(ndev);
2037
2038                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2039                 ql_write_common_reg(qdev,
2040                                     &port_regs->CommonRegs.rspQConsumerIndex,
2041                                     qdev->rsp_consumer_index);
2042                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2043
2044                 ql_enable_interrupts(qdev);
2045                 return 0;
2046         }
2047         return 1;
2048 }
2049
2050 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2051 {
2052
2053         struct net_device *ndev = dev_id;
2054         struct ql3_adapter *qdev = netdev_priv(ndev);
2055         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2056         u32 value;
2057         int handled = 1;
2058         u32 var;
2059
2060         port_regs = qdev->mem_map_registers;
2061
2062         value =
2063             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2064
2065         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2066                 spin_lock(&qdev->adapter_lock);
2067                 netif_stop_queue(qdev->ndev);
2068                 netif_carrier_off(qdev->ndev);
2069                 ql_disable_interrupts(qdev);
2070                 qdev->port_link_state = LS_DOWN;
2071                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2072
2073                 if (value & ISP_CONTROL_FE) {
2074                         /*
2075                          * Chip Fatal Error.
2076                          */
2077                         var =
2078                             ql_read_page0_reg_l(qdev,
2079                                               &port_regs->PortFatalErrStatus);
2080                         printk(KERN_WARNING PFX
2081                                "%s: Resetting chip. PortFatalErrStatus "
2082                                "register = 0x%x\n", ndev->name, var);
2083                         set_bit(QL_RESET_START,&qdev->flags) ;
2084                 } else {
2085                         /*
2086                          * Soft Reset Requested.
2087                          */
2088                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2089                         printk(KERN_ERR PFX
2090                                "%s: Another function issued a reset to the "
2091                                "chip. ISR value = %x.\n", ndev->name, value);
2092                 }
2093                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2094                 spin_unlock(&qdev->adapter_lock);
2095         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2096                 if (likely(netif_rx_schedule_prep(ndev))) {
2097                         ql_disable_interrupts(qdev);
2098                         __netif_rx_schedule(ndev);
2099                 }
2100         } else {
2101                 return IRQ_NONE;
2102         }
2103
2104         return IRQ_RETVAL(handled);
2105 }
2106
2107 /*
2108  * Get the total number of segments needed for the
2109  * given number of fragments.  This is necessary because
2110  * outbound address lists (OAL) will be used when more than
2111  * two frags are given.  Each address list has 5 addr/len
2112  * pairs.  The 5th pair in each AOL is used to  point to
2113  * the next AOL if more frags are coming.
2114  * That is why the frags:segment count  ratio is not linear.
2115  */
2116 static int ql_get_seg_count(unsigned short frags)
2117 {
2118         switch(frags) {
2119         case 0: return 1;       /* just the skb->data seg */
2120         case 1: return 2;       /* skb->data + 1 frag */
2121         case 2: return 3;       /* skb->data + 2 frags */
2122         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2123         case 4: return 6;
2124         case 5: return 7;
2125         case 6: return 8;
2126         case 7: return 10;
2127         case 8: return 11;
2128         case 9: return 12;
2129         case 10: return 13;
2130         case 11: return 15;
2131         case 12: return 16;
2132         case 13: return 17;
2133         case 14: return 18;
2134         case 15: return 20;
2135         case 16: return 21;
2136         case 17: return 22;
2137         case 18: return 23;
2138         }
2139         return -1;
2140 }
2141
2142 static void ql_hw_csum_setup(struct sk_buff *skb,
2143                              struct ob_mac_iocb_req *mac_iocb_ptr)
2144 {
2145         struct ethhdr *eth;
2146         struct iphdr *ip = NULL;
2147         u8 offset = ETH_HLEN;
2148
2149         eth = (struct ethhdr *)(skb->data);
2150
2151         if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2152                 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2153         } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2154                    ((struct vlan_ethhdr *)skb->data)->
2155                    h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2156                 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2157                 offset = VLAN_ETH_HLEN;
2158         }
2159
2160         if (ip) {
2161                 if (ip->protocol == IPPROTO_TCP) {
2162                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2163                         OB_3032MAC_IOCB_REQ_IC;
2164                         mac_iocb_ptr->ip_hdr_off = offset;
2165                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2166                 } else if (ip->protocol == IPPROTO_UDP) {
2167                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2168                         OB_3032MAC_IOCB_REQ_IC;
2169                         mac_iocb_ptr->ip_hdr_off = offset;
2170                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2171                 }
2172         }
2173 }
2174
2175 /*
2176  * Map the buffers for this transmit.  This will return
2177  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2178  */
2179 static int ql_send_map(struct ql3_adapter *qdev,
2180                                 struct ob_mac_iocb_req *mac_iocb_ptr,
2181                                 struct ql_tx_buf_cb *tx_cb,
2182                                 struct sk_buff *skb)
2183 {
2184         struct oal *oal;
2185         struct oal_entry *oal_entry;
2186         int len = skb_headlen(skb);
2187         dma_addr_t map;
2188         int err;
2189         int completed_segs, i;
2190         int seg_cnt, seg = 0;
2191         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2192
2193         seg_cnt = tx_cb->seg_count = ql_get_seg_count((skb_shinfo(skb)->nr_frags));
2194         if(seg_cnt == -1) {
2195                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2196                 return NETDEV_TX_BUSY;
2197         }
2198         /*
2199          * Map the skb buffer first.
2200          */
2201         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2202
2203         err = pci_dma_mapping_error(map);
2204         if(err) {
2205                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2206                        qdev->ndev->name, err);
2207
2208                 return NETDEV_TX_BUSY;
2209         }
2210
2211         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2212         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2213         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2214         oal_entry->len = cpu_to_le32(len);
2215         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2216         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2217         seg++;
2218
2219         if (!skb_shinfo(skb)->nr_frags) {
2220                 /* Terminate the last segment. */
2221                 oal_entry->len =
2222                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2223         } else {
2224                 oal = tx_cb->oal;
2225                 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2226                         skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2227                         oal_entry++;
2228                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2229                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2230                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2231                             (seg == 17 && seg_cnt > 18)) {
2232                                 /* Continuation entry points to outbound address list. */
2233                                 map = pci_map_single(qdev->pdev, oal,
2234                                                      sizeof(struct oal),
2235                                                      PCI_DMA_TODEVICE);
2236
2237                                 err = pci_dma_mapping_error(map);
2238                                 if(err) {
2239
2240                                         printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2241                                                qdev->ndev->name, err);
2242                                         goto map_error;
2243                                 }
2244
2245                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2246                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2247                                 oal_entry->len =
2248                                     cpu_to_le32(sizeof(struct oal) |
2249                                                 OAL_CONT_ENTRY);
2250                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2251                                                    map);
2252                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2253                                                   len);
2254                                 oal_entry = (struct oal_entry *)oal;
2255                                 oal++;
2256                                 seg++;
2257                         }
2258
2259                         map =
2260                             pci_map_page(qdev->pdev, frag->page,
2261                                          frag->page_offset, frag->size,
2262                                          PCI_DMA_TODEVICE);
2263
2264                         err = pci_dma_mapping_error(map);
2265                         if(err) {
2266                                 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2267                                        qdev->ndev->name, err);
2268                                 goto map_error;
2269                         }
2270
2271                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2272                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2273                         oal_entry->len = cpu_to_le32(frag->size);
2274                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2275                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2276                                           frag->size);
2277                 }
2278                 /* Terminate the last segment. */
2279                 oal_entry->len =
2280                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2281         }
2282
2283         return NETDEV_TX_OK;
2284
2285 map_error:
2286         /* A PCI mapping failed and now we will need to back out
2287          * We need to traverse through the oal's and associated pages which
2288          * have been mapped and now we must unmap them to clean up properly
2289          */
2290
2291         seg = 1;
2292         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2293         oal = tx_cb->oal;
2294         for (i=0; i<completed_segs; i++,seg++) {
2295                 oal_entry++;
2296
2297                 if((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2298                    (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2299                    (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2300                    (seg == 17 && seg_cnt > 18)) {
2301                         pci_unmap_single(qdev->pdev,
2302                                 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2303                                 pci_unmap_len(&tx_cb->map[seg], maplen),
2304                                  PCI_DMA_TODEVICE);
2305                         oal++;
2306                         seg++;
2307                 }
2308
2309                 pci_unmap_page(qdev->pdev,
2310                                pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2311                                pci_unmap_len(&tx_cb->map[seg], maplen),
2312                                PCI_DMA_TODEVICE);
2313         }
2314
2315         pci_unmap_single(qdev->pdev,
2316                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2317                          pci_unmap_addr(&tx_cb->map[0], maplen),
2318                          PCI_DMA_TODEVICE);
2319
2320         return NETDEV_TX_BUSY;
2321
2322 }
2323
2324 /*
2325  * The difference between 3022 and 3032 sends:
2326  * 3022 only supports a simple single segment transmission.
2327  * 3032 supports checksumming and scatter/gather lists (fragments).
2328  * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2329  * in the IOCB plus a chain of outbound address lists (OAL) that
2330  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th)
2331  * will used to point to an OAL when more ALP entries are required.
2332  * The IOCB is always the top of the chain followed by one or more
2333  * OALs (when necessary).
2334  */
2335 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2336 {
2337         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2338         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2339         struct ql_tx_buf_cb *tx_cb;
2340         u32 tot_len = skb->len;
2341         struct ob_mac_iocb_req *mac_iocb_ptr;
2342
2343         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2344                 if (!netif_queue_stopped(ndev))
2345                         netif_stop_queue(ndev);
2346                 return NETDEV_TX_BUSY;
2347         }
2348
2349         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2350         if((tx_cb->seg_count = ql_get_seg_count((skb_shinfo(skb)->nr_frags))) == -1) {
2351                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2352                 return NETDEV_TX_OK;
2353         }
2354
2355         mac_iocb_ptr = tx_cb->queue_entry;
2356         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2357         mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2358         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2359         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2360         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2361         tx_cb->skb = skb;
2362         if (skb->ip_summed == CHECKSUM_PARTIAL)
2363                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2364
2365         if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2366                 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2367                 return NETDEV_TX_BUSY;
2368         }
2369
2370         wmb();
2371         qdev->req_producer_index++;
2372         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2373                 qdev->req_producer_index = 0;
2374         wmb();
2375         ql_write_common_reg_l(qdev,
2376                             &port_regs->CommonRegs.reqQProducerIndex,
2377                             qdev->req_producer_index);
2378
2379         ndev->trans_start = jiffies;
2380         if (netif_msg_tx_queued(qdev))
2381                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2382                        ndev->name, qdev->req_producer_index, skb->len);
2383
2384         atomic_dec(&qdev->tx_count);
2385         return NETDEV_TX_OK;
2386 }
2387
2388 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2389 {
2390         qdev->req_q_size =
2391             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2392
2393         qdev->req_q_virt_addr =
2394             pci_alloc_consistent(qdev->pdev,
2395                                  (size_t) qdev->req_q_size,
2396                                  &qdev->req_q_phy_addr);
2397
2398         if ((qdev->req_q_virt_addr == NULL) ||
2399             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2400                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2401                        qdev->ndev->name);
2402                 return -ENOMEM;
2403         }
2404
2405         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2406
2407         qdev->rsp_q_virt_addr =
2408             pci_alloc_consistent(qdev->pdev,
2409                                  (size_t) qdev->rsp_q_size,
2410                                  &qdev->rsp_q_phy_addr);
2411
2412         if ((qdev->rsp_q_virt_addr == NULL) ||
2413             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2414                 printk(KERN_ERR PFX
2415                        "%s: rspQ allocation failed\n",
2416                        qdev->ndev->name);
2417                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2418                                     qdev->req_q_virt_addr,
2419                                     qdev->req_q_phy_addr);
2420                 return -ENOMEM;
2421         }
2422
2423         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2424
2425         return 0;
2426 }
2427
2428 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2429 {
2430         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2431                 printk(KERN_INFO PFX
2432                        "%s: Already done.\n", qdev->ndev->name);
2433                 return;
2434         }
2435
2436         pci_free_consistent(qdev->pdev,
2437                             qdev->req_q_size,
2438                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2439
2440         qdev->req_q_virt_addr = NULL;
2441
2442         pci_free_consistent(qdev->pdev,
2443                             qdev->rsp_q_size,
2444                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2445
2446         qdev->rsp_q_virt_addr = NULL;
2447
2448         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2449 }
2450
2451 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2452 {
2453         /* Create Large Buffer Queue */
2454         qdev->lrg_buf_q_size =
2455             qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2456         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2457                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2458         else
2459                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2460
2461         qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2462         if (qdev->lrg_buf == NULL) {
2463                 printk(KERN_ERR PFX
2464                        "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2465                 return -ENOMEM;
2466         }
2467
2468         qdev->lrg_buf_q_alloc_virt_addr =
2469             pci_alloc_consistent(qdev->pdev,
2470                                  qdev->lrg_buf_q_alloc_size,
2471                                  &qdev->lrg_buf_q_alloc_phy_addr);
2472
2473         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2474                 printk(KERN_ERR PFX
2475                        "%s: lBufQ failed\n", qdev->ndev->name);
2476                 return -ENOMEM;
2477         }
2478         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2479         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2480
2481         /* Create Small Buffer Queue */
2482         qdev->small_buf_q_size =
2483             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2484         if (qdev->small_buf_q_size < PAGE_SIZE)
2485                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2486         else
2487                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2488
2489         qdev->small_buf_q_alloc_virt_addr =
2490             pci_alloc_consistent(qdev->pdev,
2491                                  qdev->small_buf_q_alloc_size,
2492                                  &qdev->small_buf_q_alloc_phy_addr);
2493
2494         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2495                 printk(KERN_ERR PFX
2496                        "%s: Small Buffer Queue allocation failed.\n",
2497                        qdev->ndev->name);
2498                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2499                                     qdev->lrg_buf_q_alloc_virt_addr,
2500                                     qdev->lrg_buf_q_alloc_phy_addr);
2501                 return -ENOMEM;
2502         }
2503
2504         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2505         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2506         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2507         return 0;
2508 }
2509
2510 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2511 {
2512         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2513                 printk(KERN_INFO PFX
2514                        "%s: Already done.\n", qdev->ndev->name);
2515                 return;
2516         }
2517         if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2518         pci_free_consistent(qdev->pdev,
2519                             qdev->lrg_buf_q_alloc_size,
2520                             qdev->lrg_buf_q_alloc_virt_addr,
2521                             qdev->lrg_buf_q_alloc_phy_addr);
2522
2523         qdev->lrg_buf_q_virt_addr = NULL;
2524
2525         pci_free_consistent(qdev->pdev,
2526                             qdev->small_buf_q_alloc_size,
2527                             qdev->small_buf_q_alloc_virt_addr,
2528                             qdev->small_buf_q_alloc_phy_addr);
2529
2530         qdev->small_buf_q_virt_addr = NULL;
2531
2532         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2533 }
2534
2535 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2536 {
2537         int i;
2538         struct bufq_addr_element *small_buf_q_entry;
2539
2540         /* Currently we allocate on one of memory and use it for smallbuffers */
2541         qdev->small_buf_total_size =
2542             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2543              QL_SMALL_BUFFER_SIZE);
2544
2545         qdev->small_buf_virt_addr =
2546             pci_alloc_consistent(qdev->pdev,
2547                                  qdev->small_buf_total_size,
2548                                  &qdev->small_buf_phy_addr);
2549
2550         if (qdev->small_buf_virt_addr == NULL) {
2551                 printk(KERN_ERR PFX
2552                        "%s: Failed to get small buffer memory.\n",
2553                        qdev->ndev->name);
2554                 return -ENOMEM;
2555         }
2556
2557         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2558         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2559
2560         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2561
2562         /* Initialize the small buffer queue. */
2563         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2564                 small_buf_q_entry->addr_high =
2565                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2566                 small_buf_q_entry->addr_low =
2567                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2568                                 (i * QL_SMALL_BUFFER_SIZE));
2569                 small_buf_q_entry++;
2570         }
2571         qdev->small_buf_index = 0;
2572         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2573         return 0;
2574 }
2575
2576 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2577 {
2578         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2579                 printk(KERN_INFO PFX
2580                        "%s: Already done.\n", qdev->ndev->name);
2581                 return;
2582         }
2583         if (qdev->small_buf_virt_addr != NULL) {
2584                 pci_free_consistent(qdev->pdev,
2585                                     qdev->small_buf_total_size,
2586                                     qdev->small_buf_virt_addr,
2587                                     qdev->small_buf_phy_addr);
2588
2589                 qdev->small_buf_virt_addr = NULL;
2590         }
2591 }
2592
2593 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2594 {
2595         int i = 0;
2596         struct ql_rcv_buf_cb *lrg_buf_cb;
2597
2598         for (i = 0; i < qdev->num_large_buffers; i++) {
2599                 lrg_buf_cb = &qdev->lrg_buf[i];
2600                 if (lrg_buf_cb->skb) {
2601                         dev_kfree_skb(lrg_buf_cb->skb);
2602                         pci_unmap_single(qdev->pdev,
2603                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2604                                          pci_unmap_len(lrg_buf_cb, maplen),
2605                                          PCI_DMA_FROMDEVICE);
2606                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2607                 } else {
2608                         break;
2609                 }
2610         }
2611 }
2612
2613 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2614 {
2615         int i;
2616         struct ql_rcv_buf_cb *lrg_buf_cb;
2617         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2618
2619         for (i = 0; i < qdev->num_large_buffers; i++) {
2620                 lrg_buf_cb = &qdev->lrg_buf[i];
2621                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2622                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2623                 buf_addr_ele++;
2624         }
2625         qdev->lrg_buf_index = 0;
2626         qdev->lrg_buf_skb_check = 0;
2627 }
2628
2629 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2630 {
2631         int i;
2632         struct ql_rcv_buf_cb *lrg_buf_cb;
2633         struct sk_buff *skb;
2634         dma_addr_t map;
2635         int err;
2636
2637         for (i = 0; i < qdev->num_large_buffers; i++) {
2638                 skb = netdev_alloc_skb(qdev->ndev,
2639                                        qdev->lrg_buffer_len);
2640                 if (unlikely(!skb)) {
2641                         /* Better luck next round */
2642                         printk(KERN_ERR PFX
2643                                "%s: large buff alloc failed, "
2644                                "for %d bytes at index %d.\n",
2645                                qdev->ndev->name,
2646                                qdev->lrg_buffer_len * 2, i);
2647                         ql_free_large_buffers(qdev);
2648                         return -ENOMEM;
2649                 } else {
2650
2651                         lrg_buf_cb = &qdev->lrg_buf[i];
2652                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2653                         lrg_buf_cb->index = i;
2654                         lrg_buf_cb->skb = skb;
2655                         /*
2656                          * We save some space to copy the ethhdr from first
2657                          * buffer
2658                          */
2659                         skb_reserve(skb, QL_HEADER_SPACE);
2660                         map = pci_map_single(qdev->pdev,
2661                                              skb->data,
2662                                              qdev->lrg_buffer_len -
2663                                              QL_HEADER_SPACE,
2664                                              PCI_DMA_FROMDEVICE);
2665
2666                         err = pci_dma_mapping_error(map);
2667                         if(err) {
2668                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2669                                        qdev->ndev->name, err);
2670                                 ql_free_large_buffers(qdev);
2671                                 return -ENOMEM;
2672                         }
2673
2674                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2675                         pci_unmap_len_set(lrg_buf_cb, maplen,
2676                                           qdev->lrg_buffer_len -
2677                                           QL_HEADER_SPACE);
2678                         lrg_buf_cb->buf_phy_addr_low =
2679                             cpu_to_le32(LS_64BITS(map));
2680                         lrg_buf_cb->buf_phy_addr_high =
2681                             cpu_to_le32(MS_64BITS(map));
2682                 }
2683         }
2684         return 0;
2685 }
2686
2687 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2688 {
2689         struct ql_tx_buf_cb *tx_cb;
2690         int i;
2691
2692         tx_cb = &qdev->tx_buf[0];
2693         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2694                 if (tx_cb->oal) {
2695                         kfree(tx_cb->oal);
2696                         tx_cb->oal = NULL;
2697                 }
2698                 tx_cb++;
2699         }
2700 }
2701
2702 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2703 {
2704         struct ql_tx_buf_cb *tx_cb;
2705         int i;
2706         struct ob_mac_iocb_req *req_q_curr =
2707                                         qdev->req_q_virt_addr;
2708
2709         /* Create free list of transmit buffers */
2710         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2711
2712                 tx_cb = &qdev->tx_buf[i];
2713                 tx_cb->skb = NULL;
2714                 tx_cb->queue_entry = req_q_curr;
2715                 req_q_curr++;
2716                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2717                 if (tx_cb->oal == NULL)
2718                         return -1;
2719         }
2720         return 0;
2721 }
2722
2723 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2724 {
2725         if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2726                 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2727                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2728         }
2729         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2730                 /*
2731                  * Bigger buffers, so less of them.
2732                  */
2733                 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2734                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2735         } else {
2736                 printk(KERN_ERR PFX
2737                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
2738                        qdev->ndev->name);
2739                 return -ENOMEM;
2740         }
2741         qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2742         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2743         qdev->max_frame_size =
2744             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2745
2746         /*
2747          * First allocate a page of shared memory and use it for shadow
2748          * locations of Network Request Queue Consumer Address Register and
2749          * Network Completion Queue Producer Index Register
2750          */
2751         qdev->shadow_reg_virt_addr =
2752             pci_alloc_consistent(qdev->pdev,
2753                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2754
2755         if (qdev->shadow_reg_virt_addr != NULL) {
2756                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2757                 qdev->req_consumer_index_phy_addr_high =
2758                     MS_64BITS(qdev->shadow_reg_phy_addr);
2759                 qdev->req_consumer_index_phy_addr_low =
2760                     LS_64BITS(qdev->shadow_reg_phy_addr);
2761
2762                 qdev->prsp_producer_index =
2763                     (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2764                 qdev->rsp_producer_index_phy_addr_high =
2765                     qdev->req_consumer_index_phy_addr_high;
2766                 qdev->rsp_producer_index_phy_addr_low =
2767                     qdev->req_consumer_index_phy_addr_low + 8;
2768         } else {
2769                 printk(KERN_ERR PFX
2770                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2771                 return -ENOMEM;
2772         }
2773
2774         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2775                 printk(KERN_ERR PFX
2776                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
2777                        qdev->ndev->name);
2778                 goto err_req_rsp;
2779         }
2780
2781         if (ql_alloc_buffer_queues(qdev) != 0) {
2782                 printk(KERN_ERR PFX
2783                        "%s: ql_alloc_buffer_queues failed.\n",
2784                        qdev->ndev->name);
2785                 goto err_buffer_queues;
2786         }
2787
2788         if (ql_alloc_small_buffers(qdev) != 0) {
2789                 printk(KERN_ERR PFX
2790                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2791                 goto err_small_buffers;
2792         }
2793
2794         if (ql_alloc_large_buffers(qdev) != 0) {
2795                 printk(KERN_ERR PFX
2796                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2797                 goto err_small_buffers;
2798         }
2799
2800         /* Initialize the large buffer queue. */
2801         ql_init_large_buffers(qdev);
2802         if (ql_create_send_free_list(qdev))
2803                 goto err_free_list;
2804
2805         qdev->rsp_current = qdev->rsp_q_virt_addr;
2806
2807         return 0;
2808 err_free_list:
2809         ql_free_send_free_list(qdev);
2810 err_small_buffers:
2811         ql_free_buffer_queues(qdev);
2812 err_buffer_queues:
2813         ql_free_net_req_rsp_queues(qdev);
2814 err_req_rsp:
2815         pci_free_consistent(qdev->pdev,
2816                             PAGE_SIZE,
2817                             qdev->shadow_reg_virt_addr,
2818                             qdev->shadow_reg_phy_addr);
2819
2820         return -ENOMEM;
2821 }
2822
2823 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2824 {
2825         ql_free_send_free_list(qdev);
2826         ql_free_large_buffers(qdev);
2827         ql_free_small_buffers(qdev);
2828         ql_free_buffer_queues(qdev);
2829         ql_free_net_req_rsp_queues(qdev);
2830         if (qdev->shadow_reg_virt_addr != NULL) {
2831                 pci_free_consistent(qdev->pdev,
2832                                     PAGE_SIZE,
2833                                     qdev->shadow_reg_virt_addr,
2834                                     qdev->shadow_reg_phy_addr);
2835                 qdev->shadow_reg_virt_addr = NULL;
2836         }
2837 }
2838
2839 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2840 {
2841         struct ql3xxx_local_ram_registers __iomem *local_ram =
2842             (void __iomem *)qdev->mem_map_registers;
2843
2844         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2845                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2846                          2) << 4))
2847                 return -1;
2848
2849         ql_write_page2_reg(qdev,
2850                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2851
2852         ql_write_page2_reg(qdev,
2853                            &local_ram->maxBufletCount,
2854                            qdev->nvram_data.bufletCount);
2855
2856         ql_write_page2_reg(qdev,
2857                            &local_ram->freeBufletThresholdLow,
2858                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2859                            (qdev->nvram_data.tcpWindowThreshold0));
2860
2861         ql_write_page2_reg(qdev,
2862                            &local_ram->freeBufletThresholdHigh,
2863                            qdev->nvram_data.tcpWindowThreshold50);
2864
2865         ql_write_page2_reg(qdev,
2866                            &local_ram->ipHashTableBase,
2867                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
2868                            qdev->nvram_data.ipHashTableBaseLo);
2869         ql_write_page2_reg(qdev,
2870                            &local_ram->ipHashTableCount,
2871                            qdev->nvram_data.ipHashTableSize);
2872         ql_write_page2_reg(qdev,
2873                            &local_ram->tcpHashTableBase,
2874                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2875                            qdev->nvram_data.tcpHashTableBaseLo);
2876         ql_write_page2_reg(qdev,
2877                            &local_ram->tcpHashTableCount,
2878                            qdev->nvram_data.tcpHashTableSize);
2879         ql_write_page2_reg(qdev,
2880                            &local_ram->ncbBase,
2881                            (qdev->nvram_data.ncbTableBaseHi << 16) |
2882                            qdev->nvram_data.ncbTableBaseLo);
2883         ql_write_page2_reg(qdev,
2884                            &local_ram->maxNcbCount,
2885                            qdev->nvram_data.ncbTableSize);
2886         ql_write_page2_reg(qdev,
2887                            &local_ram->drbBase,
2888                            (qdev->nvram_data.drbTableBaseHi << 16) |
2889                            qdev->nvram_data.drbTableBaseLo);
2890         ql_write_page2_reg(qdev,
2891                            &local_ram->maxDrbCount,
2892                            qdev->nvram_data.drbTableSize);
2893         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2894         return 0;
2895 }
2896
2897 static int ql_adapter_initialize(struct ql3_adapter *qdev)
2898 {
2899         u32 value;
2900         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2901         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2902                                                 (void __iomem *)port_regs;
2903         u32 delay = 10;
2904         int status = 0;
2905
2906         if(ql_mii_setup(qdev))
2907                 return -1;
2908
2909         /* Bring out PHY out of reset */
2910         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2911                             (ISP_SERIAL_PORT_IF_WE |
2912                              (ISP_SERIAL_PORT_IF_WE << 16)));
2913
2914         qdev->port_link_state = LS_DOWN;
2915         netif_carrier_off(qdev->ndev);
2916
2917         /* V2 chip fix for ARS-39168. */
2918         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2919                             (ISP_SERIAL_PORT_IF_SDE |
2920                              (ISP_SERIAL_PORT_IF_SDE << 16)));
2921
2922         /* Request Queue Registers */
2923         *((u32 *) (qdev->preq_consumer_index)) = 0;
2924         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2925         qdev->req_producer_index = 0;
2926
2927         ql_write_page1_reg(qdev,
2928                            &hmem_regs->reqConsumerIndexAddrHigh,
2929                            qdev->req_consumer_index_phy_addr_high);
2930         ql_write_page1_reg(qdev,
2931                            &hmem_regs->reqConsumerIndexAddrLow,
2932                            qdev->req_consumer_index_phy_addr_low);
2933
2934         ql_write_page1_reg(qdev,
2935                            &hmem_regs->reqBaseAddrHigh,
2936                            MS_64BITS(qdev->req_q_phy_addr));
2937         ql_write_page1_reg(qdev,
2938                            &hmem_regs->reqBaseAddrLow,
2939                            LS_64BITS(qdev->req_q_phy_addr));
2940         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2941
2942         /* Response Queue Registers */
2943         *((u16 *) (qdev->prsp_producer_index)) = 0;
2944         qdev->rsp_consumer_index = 0;
2945         qdev->rsp_current = qdev->rsp_q_virt_addr;
2946
2947         ql_write_page1_reg(qdev,
2948                            &hmem_regs->rspProducerIndexAddrHigh,
2949                            qdev->rsp_producer_index_phy_addr_high);
2950
2951         ql_write_page1_reg(qdev,
2952                            &hmem_regs->rspProducerIndexAddrLow,
2953                            qdev->rsp_producer_index_phy_addr_low);
2954
2955         ql_write_page1_reg(qdev,
2956                            &hmem_regs->rspBaseAddrHigh,
2957                            MS_64BITS(qdev->rsp_q_phy_addr));
2958
2959         ql_write_page1_reg(qdev,
2960                            &hmem_regs->rspBaseAddrLow,
2961                            LS_64BITS(qdev->rsp_q_phy_addr));
2962
2963         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2964
2965         /* Large Buffer Queue */
2966         ql_write_page1_reg(qdev,
2967                            &hmem_regs->rxLargeQBaseAddrHigh,
2968                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
2969
2970         ql_write_page1_reg(qdev,
2971                            &hmem_regs->rxLargeQBaseAddrLow,
2972                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
2973
2974         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
2975
2976         ql_write_page1_reg(qdev,
2977                            &hmem_regs->rxLargeBufferLength,
2978                            qdev->lrg_buffer_len);
2979
2980         /* Small Buffer Queue */
2981         ql_write_page1_reg(qdev,
2982                            &hmem_regs->rxSmallQBaseAddrHigh,
2983                            MS_64BITS(qdev->small_buf_q_phy_addr));
2984
2985         ql_write_page1_reg(qdev,
2986                            &hmem_regs->rxSmallQBaseAddrLow,
2987                            LS_64BITS(qdev->small_buf_q_phy_addr));
2988
2989         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
2990         ql_write_page1_reg(qdev,
2991                            &hmem_regs->rxSmallBufferLength,
2992                            QL_SMALL_BUFFER_SIZE);
2993
2994         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
2995         qdev->small_buf_release_cnt = 8;
2996         qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
2997         qdev->lrg_buf_release_cnt = 8;
2998         qdev->lrg_buf_next_free =
2999             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3000         qdev->small_buf_index = 0;
3001         qdev->lrg_buf_index = 0;
3002         qdev->lrg_buf_free_count = 0;
3003         qdev->lrg_buf_free_head = NULL;
3004         qdev->lrg_buf_free_tail = NULL;
3005
3006         ql_write_common_reg(qdev,
3007                             &port_regs->CommonRegs.
3008                             rxSmallQProducerIndex,
3009                             qdev->small_buf_q_producer_index);
3010         ql_write_common_reg(qdev,
3011                             &port_regs->CommonRegs.
3012                             rxLargeQProducerIndex,
3013                             qdev->lrg_buf_q_producer_index);
3014
3015         /*
3016          * Find out if the chip has already been initialized.  If it has, then
3017          * we skip some of the initialization.
3018          */
3019         clear_bit(QL_LINK_MASTER, &qdev->flags);
3020         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3021         if ((value & PORT_STATUS_IC) == 0) {
3022
3023                 /* Chip has not been configured yet, so let it rip. */
3024                 if(ql_init_misc_registers(qdev)) {
3025                         status = -1;
3026                         goto out;
3027                 }
3028
3029                 if (qdev->mac_index)
3030                         ql_write_page0_reg(qdev,
3031                                            &port_regs->mac1MaxFrameLengthReg,
3032                                            qdev->max_frame_size);
3033                 else
3034                         ql_write_page0_reg(qdev,
3035                                            &port_regs->mac0MaxFrameLengthReg,
3036                                            qdev->max_frame_size);
3037
3038                 value = qdev->nvram_data.tcpMaxWindowSize;
3039                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3040
3041                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3042
3043                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3044                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3045                                  * 2) << 13)) {
3046                         status = -1;
3047                         goto out;
3048                 }
3049                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3050                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3051                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3052                                      16) | (INTERNAL_CHIP_SD |
3053                                             INTERNAL_CHIP_WE)));
3054                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3055         }
3056
3057
3058         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3059                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3060                          2) << 7)) {
3061                 status = -1;
3062                 goto out;
3063         }
3064
3065         ql_init_scan_mode(qdev);
3066         ql_get_phy_owner(qdev);
3067
3068         /* Load the MAC Configuration */
3069
3070         /* Program lower 32 bits of the MAC address */
3071         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3072                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3073         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3074                            ((qdev->ndev->dev_addr[2] << 24)
3075                             | (qdev->ndev->dev_addr[3] << 16)
3076                             | (qdev->ndev->dev_addr[4] << 8)
3077                             | qdev->ndev->dev_addr[5]));
3078
3079         /* Program top 16 bits of the MAC address */
3080         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3081                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3082         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3083                            ((qdev->ndev->dev_addr[0] << 8)
3084                             | qdev->ndev->dev_addr[1]));
3085
3086         /* Enable Primary MAC */
3087         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3088                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3089                             MAC_ADDR_INDIRECT_PTR_REG_PE));
3090
3091         /* Clear Primary and Secondary IP addresses */
3092         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3093                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3094                             (qdev->mac_index << 2)));
3095         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3096
3097         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3098                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3099                             ((qdev->mac_index << 2) + 1)));
3100         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3101
3102         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3103
3104         /* Indicate Configuration Complete */
3105         ql_write_page0_reg(qdev,
3106                            &port_regs->portControl,
3107                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3108
3109         do {
3110                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3111                 if (value & PORT_STATUS_IC)
3112                         break;
3113                 msleep(500);
3114         } while (--delay);
3115
3116         if (delay == 0) {
3117                 printk(KERN_ERR PFX
3118                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3119                 status = -1;
3120                 goto out;
3121         }
3122
3123         /* Enable Ethernet Function */
3124         if (qdev->device_id == QL3032_DEVICE_ID) {
3125                 value =
3126                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3127                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4);
3128                 ql_write_page0_reg(qdev, &port_regs->functionControl,
3129                                    ((value << 16) | value));
3130         } else {
3131                 value =
3132                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3133                      PORT_CONTROL_HH);
3134                 ql_write_page0_reg(qdev, &port_regs->portControl,
3135                                    ((value << 16) | value));
3136         }
3137
3138
3139 out:
3140         return status;
3141 }
3142
3143 /*
3144  * Caller holds hw_lock.
3145  */
3146 static int ql_adapter_reset(struct ql3_adapter *qdev)
3147 {
3148         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3149         int status = 0;
3150         u16 value;
3151         int max_wait_time;
3152
3153         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3154         clear_bit(QL_RESET_DONE, &qdev->flags);
3155
3156         /*
3157          * Issue soft reset to chip.
3158          */
3159         printk(KERN_DEBUG PFX
3160                "%s: Issue soft reset to chip.\n",
3161                qdev->ndev->name);
3162         ql_write_common_reg(qdev,
3163                             &port_regs->CommonRegs.ispControlStatus,
3164                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3165
3166         /* Wait 3 seconds for reset to complete. */
3167         printk(KERN_DEBUG PFX
3168                "%s: Wait 10 milliseconds for reset to complete.\n",
3169                qdev->ndev->name);
3170
3171         /* Wait until the firmware tells us the Soft Reset is done */
3172         max_wait_time = 5;
3173         do {
3174                 value =
3175                     ql_read_common_reg(qdev,
3176                                        &port_regs->CommonRegs.ispControlStatus);
3177                 if ((value & ISP_CONTROL_SR) == 0)
3178                         break;
3179
3180                 ssleep(1);
3181         } while ((--max_wait_time));
3182
3183         /*
3184          * Also, make sure that the Network Reset Interrupt bit has been
3185          * cleared after the soft reset has taken place.
3186          */
3187         value =
3188             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3189         if (value & ISP_CONTROL_RI) {
3190                 printk(KERN_DEBUG PFX
3191                        "ql_adapter_reset: clearing RI after reset.\n");
3192                 ql_write_common_reg(qdev,
3193                                     &port_regs->CommonRegs.
3194                                     ispControlStatus,
3195                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3196         }
3197
3198         if (max_wait_time == 0) {
3199                 /* Issue Force Soft Reset */
3200                 ql_write_common_reg(qdev,
3201                                     &port_regs->CommonRegs.
3202                                     ispControlStatus,
3203                                     ((ISP_CONTROL_FSR << 16) |
3204                                      ISP_CONTROL_FSR));
3205                 /*
3206                  * Wait until the firmware tells us the Force Soft Reset is
3207                  * done
3208                  */
3209                 max_wait_time = 5;
3210                 do {
3211                         value =
3212                             ql_read_common_reg(qdev,
3213                                                &port_regs->CommonRegs.
3214                                                ispControlStatus);
3215                         if ((value & ISP_CONTROL_FSR) == 0) {
3216                                 break;
3217                         }
3218                         ssleep(1);
3219                 } while ((--max_wait_time));
3220         }
3221         if (max_wait_time == 0)
3222                 status = 1;
3223
3224         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3225         set_bit(QL_RESET_DONE, &qdev->flags);
3226         return status;
3227 }
3228
3229 static void ql_set_mac_info(struct ql3_adapter *qdev)
3230 {
3231         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3232         u32 value, port_status;
3233         u8 func_number;
3234
3235         /* Get the function number */
3236         value =
3237             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3238         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3239         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3240         switch (value & ISP_CONTROL_FN_MASK) {
3241         case ISP_CONTROL_FN0_NET:
3242                 qdev->mac_index = 0;
3243                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3244                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3245                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3246                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3247                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3248                 if (port_status & PORT_STATUS_SM0)
3249                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3250                 else
3251                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3252                 break;
3253
3254         case ISP_CONTROL_FN1_NET:
3255                 qdev->mac_index = 1;
3256                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3257                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3258                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3259                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3260                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3261                 if (port_status & PORT_STATUS_SM1)
3262                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3263                 else
3264                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3265                 break;
3266
3267         case ISP_CONTROL_FN0_SCSI:
3268         case ISP_CONTROL_FN1_SCSI:
3269         default:
3270                 printk(KERN_DEBUG PFX
3271                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3272                        qdev->ndev->name,value);
3273                 break;
3274         }
3275         qdev->numPorts = qdev->nvram_data.numPorts;
3276 }
3277
3278 static void ql_display_dev_info(struct net_device *ndev)
3279 {
3280         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3281         struct pci_dev *pdev = qdev->pdev;
3282
3283         printk(KERN_INFO PFX
3284                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3285                DRV_NAME, qdev->index, qdev->chip_rev_id,
3286                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3287                qdev->pci_slot);
3288         printk(KERN_INFO PFX
3289                "%s Interface.\n",
3290                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3291
3292         /*
3293          * Print PCI bus width/type.
3294          */
3295         printk(KERN_INFO PFX
3296                "Bus interface is %s %s.\n",
3297                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3298                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3299
3300         printk(KERN_INFO PFX
3301                "mem  IO base address adjusted = 0x%p\n",
3302                qdev->mem_map_registers);
3303         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3304
3305         if (netif_msg_probe(qdev))
3306                 printk(KERN_INFO PFX
3307                        "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3308                        ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3309                        ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3310                        ndev->dev_addr[5]);
3311 }
3312
3313 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3314 {
3315         struct net_device *ndev = qdev->ndev;
3316         int retval = 0;
3317
3318         netif_stop_queue(ndev);
3319         netif_carrier_off(ndev);
3320
3321         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3322         clear_bit(QL_LINK_MASTER,&qdev->flags);
3323
3324         ql_disable_interrupts(qdev);
3325
3326         free_irq(qdev->pdev->irq, ndev);
3327
3328         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3329                 printk(KERN_INFO PFX
3330                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3331                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3332                 pci_disable_msi(qdev->pdev);
3333         }
3334
3335         del_timer_sync(&qdev->adapter_timer);
3336
3337         netif_poll_disable(ndev);
3338
3339         if (do_reset) {
3340                 int soft_reset;
3341                 unsigned long hw_flags;
3342
3343                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3344                 if (ql_wait_for_drvr_lock(qdev)) {
3345                         if ((soft_reset = ql_adapter_reset(qdev))) {
3346                                 printk(KERN_ERR PFX
3347                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3348                                        ndev->name, qdev->index);
3349                         }
3350                         printk(KERN_ERR PFX
3351                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3352                 } else {
3353                         printk(KERN_ERR PFX
3354                                "%s: Could not acquire driver lock to do "
3355                                "reset!\n", ndev->name);
3356                         retval = -1;
3357                 }
3358                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3359         }
3360         ql_free_mem_resources(qdev);
3361         return retval;
3362 }
3363
3364 static int ql_adapter_up(struct ql3_adapter *qdev)
3365 {
3366         struct net_device *ndev = qdev->ndev;
3367         int err;
3368         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3369         unsigned long hw_flags;
3370
3371         if (ql_alloc_mem_resources(qdev)) {
3372                 printk(KERN_ERR PFX
3373                        "%s Unable to  allocate buffers.\n", ndev->name);
3374                 return -ENOMEM;
3375         }
3376
3377         if (qdev->msi) {
3378                 if (pci_enable_msi(qdev->pdev)) {
3379                         printk(KERN_ERR PFX
3380                                "%s: User requested MSI, but MSI failed to "
3381                                "initialize.  Continuing without MSI.\n",
3382                                qdev->ndev->name);
3383                         qdev->msi = 0;
3384                 } else {
3385                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3386                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3387                         irq_flags &= ~IRQF_SHARED;
3388                 }
3389         }
3390
3391         if ((err = request_irq(qdev->pdev->irq,
3392                                ql3xxx_isr,
3393                                irq_flags, ndev->name, ndev))) {
3394                 printk(KERN_ERR PFX
3395                        "%s: Failed to reserve interrupt %d already in use.\n",
3396                        ndev->name, qdev->pdev->irq);
3397                 goto err_irq;
3398         }
3399
3400         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3401
3402         if ((err = ql_wait_for_drvr_lock(qdev))) {
3403                 if ((err = ql_adapter_initialize(qdev))) {
3404                         printk(KERN_ERR PFX
3405                                "%s: Unable to initialize adapter.\n",
3406                                ndev->name);
3407                         goto err_init;
3408                 }
3409                 printk(KERN_ERR PFX
3410                                 "%s: Releaseing driver lock.\n",ndev->name);
3411                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3412         } else {
3413                 printk(KERN_ERR PFX
3414                        "%s: Could not aquire driver lock.\n",
3415                        ndev->name);
3416                 goto err_lock;
3417         }
3418
3419         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3420
3421         set_bit(QL_ADAPTER_UP,&qdev->flags);
3422
3423         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3424
3425         netif_poll_enable(ndev);
3426         ql_enable_interrupts(qdev);
3427         return 0;
3428
3429 err_init:
3430         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3431 err_lock:
3432         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3433         free_irq(qdev->pdev->irq, ndev);
3434 err_irq:
3435         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3436                 printk(KERN_INFO PFX
3437                        "%s: calling pci_disable_msi().\n",
3438                        qdev->ndev->name);
3439                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3440                 pci_disable_msi(qdev->pdev);
3441         }
3442         return err;
3443 }
3444
3445 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3446 {
3447         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3448                 printk(KERN_ERR PFX
3449                                 "%s: Driver up/down cycle failed, "
3450                                 "closing device\n",qdev->ndev->name);
3451                 dev_close(qdev->ndev);
3452                 return -1;
3453         }
3454         return 0;
3455 }
3456
3457 static int ql3xxx_close(struct net_device *ndev)
3458 {
3459         struct ql3_adapter *qdev = netdev_priv(ndev);
3460
3461         /*
3462          * Wait for device to recover from a reset.
3463          * (Rarely happens, but possible.)
3464          */
3465         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3466                 msleep(50);
3467
3468         ql_adapter_down(qdev,QL_DO_RESET);
3469         return 0;
3470 }
3471
3472 static int ql3xxx_open(struct net_device *ndev)
3473 {
3474         struct ql3_adapter *qdev = netdev_priv(ndev);
3475         return (ql_adapter_up(qdev));
3476 }
3477
3478 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3479 {
3480         struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3481         return &qdev->stats;
3482 }
3483
3484 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3485 {
3486         /*
3487          * We are manually parsing the list in the net_device structure.
3488          */
3489         return;
3490 }
3491
3492 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3493 {
3494         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3495         struct ql3xxx_port_registers __iomem *port_regs =
3496                         qdev->mem_map_registers;
3497         struct sockaddr *addr = p;
3498         unsigned long hw_flags;
3499
3500         if (netif_running(ndev))
3501                 return -EBUSY;
3502
3503         if (!is_valid_ether_addr(addr->sa_data))
3504                 return -EADDRNOTAVAIL;
3505
3506         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3507
3508         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3509         /* Program lower 32 bits of the MAC address */
3510         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3511                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3512         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3513                            ((ndev->dev_addr[2] << 24) | (ndev->
3514                                                          dev_addr[3] << 16) |
3515                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3516
3517         /* Program top 16 bits of the MAC address */
3518         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3519                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3520         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3521                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3522         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3523
3524         return 0;
3525 }
3526
3527 static void ql3xxx_tx_timeout(struct net_device *ndev)
3528 {
3529         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3530
3531         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3532         /*
3533          * Stop the queues, we've got a problem.
3534          */
3535         netif_stop_queue(ndev);
3536
3537         /*
3538          * Wake up the worker to process this event.
3539          */
3540         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3541 }
3542
3543 static void ql_reset_work(struct work_struct *work)
3544 {
3545         struct ql3_adapter *qdev =
3546                 container_of(work, struct ql3_adapter, reset_work.work);
3547         struct net_device *ndev = qdev->ndev;
3548         u32 value;
3549         struct ql_tx_buf_cb *tx_cb;
3550         int max_wait_time, i;
3551         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3552         unsigned long hw_flags;
3553
3554         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3555                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3556
3557                 /*
3558                  * Loop through the active list and return the skb.
3559                  */
3560                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3561                         int j;
3562                         tx_cb = &qdev->tx_buf[i];
3563                         if (tx_cb->skb) {
3564                                 printk(KERN_DEBUG PFX
3565                                        "%s: Freeing lost SKB.\n",
3566                                        qdev->ndev->name);
3567                                 pci_unmap_single(qdev->pdev,
3568                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3569                                          pci_unmap_len(&tx_cb->map[0], maplen),
3570                                          PCI_DMA_TODEVICE);
3571                                 for(j=1;j<tx_cb->seg_count;j++) {
3572                                         pci_unmap_page(qdev->pdev,
3573                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3574                                                pci_unmap_len(&tx_cb->map[j],maplen),
3575                                                PCI_DMA_TODEVICE);
3576                                 }
3577                                 dev_kfree_skb(tx_cb->skb);
3578                                 tx_cb->skb = NULL;
3579                         }
3580                 }
3581
3582                 printk(KERN_ERR PFX
3583                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3584                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3585                 ql_write_common_reg(qdev,
3586                                     &port_regs->CommonRegs.
3587                                     ispControlStatus,
3588                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3589                 /*
3590                  * Wait the for Soft Reset to Complete.
3591                  */
3592                 max_wait_time = 10;
3593                 do {
3594                         value = ql_read_common_reg(qdev,
3595                                                    &port_regs->CommonRegs.
3596
3597                                                    ispControlStatus);
3598                         if ((value & ISP_CONTROL_SR) == 0) {
3599                                 printk(KERN_DEBUG PFX
3600                                        "%s: reset completed.\n",
3601                                        qdev->ndev->name);
3602                                 break;
3603                         }
3604
3605                         if (value & ISP_CONTROL_RI) {
3606                                 printk(KERN_DEBUG PFX
3607                                        "%s: clearing NRI after reset.\n",
3608                                        qdev->ndev->name);
3609                                 ql_write_common_reg(qdev,
3610                                                     &port_regs->
3611                                                     CommonRegs.
3612                                                     ispControlStatus,
3613                                                     ((ISP_CONTROL_RI <<
3614                                                       16) | ISP_CONTROL_RI));
3615                         }
3616
3617                         ssleep(1);
3618                 } while (--max_wait_time);
3619                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3620
3621                 if (value & ISP_CONTROL_SR) {
3622
3623                         /*
3624                          * Set the reset flags and clear the board again.
3625                          * Nothing else to do...
3626                          */
3627                         printk(KERN_ERR PFX
3628                                "%s: Timed out waiting for reset to "
3629                                "complete.\n", ndev->name);
3630                         printk(KERN_ERR PFX
3631                                "%s: Do a reset.\n", ndev->name);
3632                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3633                         clear_bit(QL_RESET_START,&qdev->flags);
3634                         ql_cycle_adapter(qdev,QL_DO_RESET);
3635                         return;
3636                 }
3637
3638                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3639                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3640                 clear_bit(QL_RESET_START,&qdev->flags);
3641                 ql_cycle_adapter(qdev,QL_NO_RESET);
3642         }
3643 }
3644
3645 static void ql_tx_timeout_work(struct work_struct *work)
3646 {
3647         struct ql3_adapter *qdev =
3648                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3649
3650         ql_cycle_adapter(qdev, QL_DO_RESET);
3651 }
3652
3653 static void ql_get_board_info(struct ql3_adapter *qdev)
3654 {
3655         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3656         u32 value;
3657
3658         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3659
3660         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3661         if (value & PORT_STATUS_64)
3662                 qdev->pci_width = 64;
3663         else
3664                 qdev->pci_width = 32;
3665         if (value & PORT_STATUS_X)
3666                 qdev->pci_x = 1;
3667         else
3668                 qdev->pci_x = 0;
3669         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3670 }
3671
3672 static void ql3xxx_timer(unsigned long ptr)
3673 {
3674         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3675
3676         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3677                 printk(KERN_DEBUG PFX
3678                        "%s: Reset in progress.\n",
3679                        qdev->ndev->name);
3680                 goto end;
3681         }
3682
3683         ql_link_state_machine(qdev);
3684
3685         /* Restart timer on 2 second interval. */
3686 end:
3687         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3688 }
3689
3690 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3691                                   const struct pci_device_id *pci_entry)
3692 {
3693         struct net_device *ndev = NULL;
3694         struct ql3_adapter *qdev = NULL;
3695         static int cards_found = 0;
3696         int pci_using_dac, err;
3697
3698         err = pci_enable_device(pdev);
3699         if (err) {
3700                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3701                        pci_name(pdev));
3702                 goto err_out;
3703         }
3704
3705         err = pci_request_regions(pdev, DRV_NAME);
3706         if (err) {
3707                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3708                        pci_name(pdev));
3709                 goto err_out_disable_pdev;
3710         }
3711
3712         pci_set_master(pdev);
3713
3714         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3715                 pci_using_dac = 1;
3716                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3717         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3718                 pci_using_dac = 0;
3719                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3720         }
3721
3722         if (err) {
3723                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3724                        pci_name(pdev));
3725                 goto err_out_free_regions;
3726         }
3727
3728         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3729         if (!ndev) {
3730                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3731                        pci_name(pdev));
3732                 err = -ENOMEM;
3733                 goto err_out_free_regions;
3734         }
3735
3736         SET_MODULE_OWNER(ndev);
3737         SET_NETDEV_DEV(ndev, &pdev->dev);
3738
3739         pci_set_drvdata(pdev, ndev);
3740
3741         qdev = netdev_priv(ndev);
3742         qdev->index = cards_found;
3743         qdev->ndev = ndev;
3744         qdev->pdev = pdev;
3745         qdev->device_id = pci_entry->device;
3746         qdev->port_link_state = LS_DOWN;
3747         if (msi)
3748                 qdev->msi = 1;
3749
3750         qdev->msg_enable = netif_msg_init(debug, default_msg);
3751
3752         if (pci_using_dac)
3753                 ndev->features |= NETIF_F_HIGHDMA;
3754         if (qdev->device_id == QL3032_DEVICE_ID)
3755                 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3756
3757         qdev->mem_map_registers =
3758             ioremap_nocache(pci_resource_start(pdev, 1),
3759                             pci_resource_len(qdev->pdev, 1));
3760         if (!qdev->mem_map_registers) {
3761                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3762                        pci_name(pdev));
3763                 err = -EIO;
3764                 goto err_out_free_ndev;
3765         }
3766
3767         spin_lock_init(&qdev->adapter_lock);
3768         spin_lock_init(&qdev->hw_lock);
3769
3770         /* Set driver entry points */
3771         ndev->open = ql3xxx_open;
3772         ndev->hard_start_xmit = ql3xxx_send;
3773         ndev->stop = ql3xxx_close;
3774         ndev->get_stats = ql3xxx_get_stats;
3775         ndev->set_multicast_list = ql3xxx_set_multicast_list;
3776         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3777         ndev->set_mac_address = ql3xxx_set_mac_address;
3778         ndev->tx_timeout = ql3xxx_tx_timeout;
3779         ndev->watchdog_timeo = 5 * HZ;
3780
3781         ndev->poll = &ql_poll;
3782         ndev->weight = 64;
3783
3784         ndev->irq = pdev->irq;
3785
3786         /* make sure the EEPROM is good */
3787         if (ql_get_nvram_params(qdev)) {
3788                 printk(KERN_ALERT PFX
3789                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3790                        qdev->index);
3791                 err = -EIO;
3792                 goto err_out_iounmap;
3793         }
3794
3795         ql_set_mac_info(qdev);
3796
3797         /* Validate and set parameters */
3798         if (qdev->mac_index) {
3799                 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3800                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3801                        ETH_ALEN);
3802         } else {
3803                 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3804                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3805                        ETH_ALEN);
3806         }
3807         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3808
3809         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3810
3811         /* Turn off support for multicasting */
3812         ndev->flags &= ~IFF_MULTICAST;
3813
3814         /* Record PCI bus information. */
3815         ql_get_board_info(qdev);
3816
3817         /*
3818          * Set the Maximum Memory Read Byte Count value. We do this to handle
3819          * jumbo frames.
3820          */
3821         if (qdev->pci_x) {
3822                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3823         }
3824
3825         err = register_netdev(ndev);
3826         if (err) {
3827                 printk(KERN_ERR PFX "%s: cannot register net device\n",
3828                        pci_name(pdev));
3829                 goto err_out_iounmap;
3830         }
3831
3832         /* we're going to reset, so assume we have no link for now */
3833
3834         netif_carrier_off(ndev);
3835         netif_stop_queue(ndev);
3836
3837         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3838         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3839         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3840
3841         init_timer(&qdev->adapter_timer);
3842         qdev->adapter_timer.function = ql3xxx_timer;
3843         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3844         qdev->adapter_timer.data = (unsigned long)qdev;
3845
3846         if(!cards_found) {
3847                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3848                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3849                    DRV_NAME, DRV_VERSION);
3850         }
3851         ql_display_dev_info(ndev);
3852
3853         cards_found++;
3854         return 0;
3855
3856 err_out_iounmap:
3857         iounmap(qdev->mem_map_registers);
3858 err_out_free_ndev:
3859         free_netdev(ndev);
3860 err_out_free_regions:
3861         pci_release_regions(pdev);
3862 err_out_disable_pdev:
3863         pci_disable_device(pdev);
3864         pci_set_drvdata(pdev, NULL);
3865 err_out:
3866         return err;
3867 }
3868
3869 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3870 {
3871         struct net_device *ndev = pci_get_drvdata(pdev);
3872         struct ql3_adapter *qdev = netdev_priv(ndev);
3873
3874         unregister_netdev(ndev);
3875         qdev = netdev_priv(ndev);
3876
3877         ql_disable_interrupts(qdev);
3878
3879         if (qdev->workqueue) {
3880                 cancel_delayed_work(&qdev->reset_work);
3881                 cancel_delayed_work(&qdev->tx_timeout_work);
3882                 destroy_workqueue(qdev->workqueue);
3883                 qdev->workqueue = NULL;
3884         }
3885
3886         iounmap(qdev->mem_map_registers);
3887         pci_release_regions(pdev);
3888         pci_set_drvdata(pdev, NULL);
3889         free_netdev(ndev);
3890 }
3891
3892 static struct pci_driver ql3xxx_driver = {
3893
3894         .name = DRV_NAME,
3895         .id_table = ql3xxx_pci_tbl,
3896         .probe = ql3xxx_probe,
3897         .remove = __devexit_p(ql3xxx_remove),
3898 };
3899
3900 static int __init ql3xxx_init_module(void)
3901 {
3902         return pci_register_driver(&ql3xxx_driver);
3903 }
3904
3905 static void __exit ql3xxx_exit(void)
3906 {
3907         pci_unregister_driver(&ql3xxx_driver);
3908 }
3909
3910 module_init(ql3xxx_init_module);
3911 module_exit(ql3xxx_exit);