drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  45
  46 #ifdef RTL8169_DEBUG
  47 #define assert(expr) \
  48         if (!(expr)) {                                  \
  49                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  50                 #expr,__FILE__,__func__,__LINE__);              \
  51         }
  52 #define dprintk(fmt, args...) \
  53         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  54 #else
  55 #define assert(expr) do {} while (0)
  56 #define dprintk(fmt, args...)   do {} while (0)
  57 #endif /* RTL8169_DEBUG */
  58
  59 #define R8169_MSG_DEFAULT \
  60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62 #define TX_BUFFS_AVAIL(tp) \
  63         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  64
  65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  66    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  67 static const int multicast_filter_limit = 32;
  68
  69 /* MAC address length */
  70 #define MAC_ADDR_LEN    6
  71
  72 #define MAX_READ_REQUEST_SHIFT  12
  73 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  74 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  75 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  76
  77 #define R8169_REGS_SIZE         256
  78 #define R8169_NAPI_WEIGHT       64
  79 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  80 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  81 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  82 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  83 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  84
  85 #define RTL8169_TX_TIMEOUT      (6*HZ)
  86 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  87
  88 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  89 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  90 #define RTL_EEPROM_SIG_ADDR     0x0000
  91
  92 /* write/read MMIO register */
  93 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  94 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  95 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  96 #define RTL_R8(reg)             readb (ioaddr + (reg))
  97 #define RTL_R16(reg)            readw (ioaddr + (reg))
  98 #define RTL_R32(reg)            readl (ioaddr + (reg))
  99
 100 enum mac_version {
 101         RTL_GIGA_MAC_VER_01 = 0,
 102         RTL_GIGA_MAC_VER_02,
 103         RTL_GIGA_MAC_VER_03,
 104         RTL_GIGA_MAC_VER_04,
 105         RTL_GIGA_MAC_VER_05,
 106         RTL_GIGA_MAC_VER_06,
 107         RTL_GIGA_MAC_VER_07,
 108         RTL_GIGA_MAC_VER_08,
 109         RTL_GIGA_MAC_VER_09,
 110         RTL_GIGA_MAC_VER_10,
 111         RTL_GIGA_MAC_VER_11,
 112         RTL_GIGA_MAC_VER_12,
 113         RTL_GIGA_MAC_VER_13,
 114         RTL_GIGA_MAC_VER_14,
 115         RTL_GIGA_MAC_VER_15,
 116         RTL_GIGA_MAC_VER_16,
 117         RTL_GIGA_MAC_VER_17,
 118         RTL_GIGA_MAC_VER_18,
 119         RTL_GIGA_MAC_VER_19,
 120         RTL_GIGA_MAC_VER_20,
 121         RTL_GIGA_MAC_VER_21,
 122         RTL_GIGA_MAC_VER_22,
 123         RTL_GIGA_MAC_VER_23,
 124         RTL_GIGA_MAC_VER_24,
 125         RTL_GIGA_MAC_VER_25,
 126         RTL_GIGA_MAC_VER_26,
 127         RTL_GIGA_MAC_VER_27,
 128         RTL_GIGA_MAC_VER_28,
 129         RTL_GIGA_MAC_VER_29,
 130         RTL_GIGA_MAC_VER_30,
 131         RTL_GIGA_MAC_VER_31,
 132         RTL_GIGA_MAC_VER_32,
 133         RTL_GIGA_MAC_VER_33,
 134         RTL_GIGA_MAC_NONE   = 0xff,
 135 };
 136
 137 enum rtl_tx_desc_version {
 138         RTL_TD_0        = 0,
 139         RTL_TD_1        = 1,
 140 };
 141
 142 #define _R(NAME,TD,FW) \
 143         { .name = NAME, .txd_version = TD, .fw_name = FW }
 144
 145 static const struct {
 146         const char *name;
 147         enum rtl_tx_desc_version txd_version;
 148         const char *fw_name;
 149 } rtl_chip_infos[] = {
 150         /* PCI devices. */
 151         [RTL_GIGA_MAC_VER_01] =
 152                 _R("RTL8169",           RTL_TD_0, NULL),
 153         [RTL_GIGA_MAC_VER_02] =
 154                 _R("RTL8169s",          RTL_TD_0, NULL),
 155         [RTL_GIGA_MAC_VER_03] =
 156                 _R("RTL8110s",          RTL_TD_0, NULL),
 157         [RTL_GIGA_MAC_VER_04] =
 158                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
 159         [RTL_GIGA_MAC_VER_05] =
 160                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 161         [RTL_GIGA_MAC_VER_06] =
 162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 163         /* PCI-E devices. */
 164         [RTL_GIGA_MAC_VER_07] =
 165                 _R("RTL8102e",          RTL_TD_1, NULL),
 166         [RTL_GIGA_MAC_VER_08] =
 167                 _R("RTL8102e",          RTL_TD_1, NULL),
 168         [RTL_GIGA_MAC_VER_09] =
 169                 _R("RTL8102e",          RTL_TD_1, NULL),
 170         [RTL_GIGA_MAC_VER_10] =
 171                 _R("RTL8101e",          RTL_TD_0, NULL),
 172         [RTL_GIGA_MAC_VER_11] =
 173                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 174         [RTL_GIGA_MAC_VER_12] =
 175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 176         [RTL_GIGA_MAC_VER_13] =
 177                 _R("RTL8101e",          RTL_TD_0, NULL),
 178         [RTL_GIGA_MAC_VER_14] =
 179                 _R("RTL8100e",          RTL_TD_0, NULL),
 180         [RTL_GIGA_MAC_VER_15] =
 181                 _R("RTL8100e",          RTL_TD_0, NULL),
 182         [RTL_GIGA_MAC_VER_16] =
 183                 _R("RTL8101e",          RTL_TD_0, NULL),
 184         [RTL_GIGA_MAC_VER_17] =
 185                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 186         [RTL_GIGA_MAC_VER_18] =
 187                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 188         [RTL_GIGA_MAC_VER_19] =
 189                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 190         [RTL_GIGA_MAC_VER_20] =
 191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 192         [RTL_GIGA_MAC_VER_21] =
 193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 194         [RTL_GIGA_MAC_VER_22] =
 195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 196         [RTL_GIGA_MAC_VER_23] =
 197                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 198         [RTL_GIGA_MAC_VER_24] =
 199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 200         [RTL_GIGA_MAC_VER_25] =
 201                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
 202         [RTL_GIGA_MAC_VER_26] =
 203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
 204         [RTL_GIGA_MAC_VER_27] =
 205                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 206         [RTL_GIGA_MAC_VER_28] =
 207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 208         [RTL_GIGA_MAC_VER_29] =
 209                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 210         [RTL_GIGA_MAC_VER_30] =
 211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 212         [RTL_GIGA_MAC_VER_31] =
 213                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 214         [RTL_GIGA_MAC_VER_32] =
 215                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
 216         [RTL_GIGA_MAC_VER_33] =
 217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2)
 218 };
 219 #undef _R
 220
 221 enum cfg_version {
 222         RTL_CFG_0 = 0x00,
 223         RTL_CFG_1,
 224         RTL_CFG_2
 225 };
 226
 227 static void rtl_hw_start_8169(struct net_device *);
 228 static void rtl_hw_start_8168(struct net_device *);
 229 static void rtl_hw_start_8101(struct net_device *);
 230
 231 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 232         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 233         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 234         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 235         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 237         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 238         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 239         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 240         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 241                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 242         { 0x0001,                               0x8168,
 243                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 244         {0,},
 245 };
 246
 247 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 248
 249 static int rx_buf_sz = 16383;
 250 static int use_dac;
 251 static struct {
 252         u32 msg_enable;
 253 } debug = { -1 };
 254
 255 enum rtl_registers {
 256         MAC0            = 0,    /* Ethernet hardware address. */
 257         MAC4            = 4,
 258         MAR0            = 8,    /* Multicast filter. */
 259         CounterAddrLow          = 0x10,
 260         CounterAddrHigh         = 0x14,
 261         TxDescStartAddrLow      = 0x20,
 262         TxDescStartAddrHigh     = 0x24,
 263         TxHDescStartAddrLow     = 0x28,
 264         TxHDescStartAddrHigh    = 0x2c,
 265         FLASH           = 0x30,
 266         ERSR            = 0x36,
 267         ChipCmd         = 0x37,
 268         TxPoll          = 0x38,
 269         IntrMask        = 0x3c,
 270         IntrStatus      = 0x3e,
 271
 272         TxConfig        = 0x40,
 273 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 274 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 275
 276         RxConfig        = 0x44,
 277 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 278 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 279 #define RXCFG_FIFO_SHIFT                13
 280                                         /* No threshold before first PCI xfer */
 281 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 282 #define RXCFG_DMA_SHIFT                 8
 283                                         /* Unlimited maximum PCI burst. */
 284 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 285 #define RTL_RX_CONFIG_MASK              0xff7e1880u
 286
 287         RxMissed        = 0x4c,
 288         Cfg9346         = 0x50,
 289         Config0         = 0x51,
 290         Config1         = 0x52,
 291         Config2         = 0x53,
 292         Config3         = 0x54,
 293         Config4         = 0x55,
 294         Config5         = 0x56,
 295         MultiIntr       = 0x5c,
 296         PHYAR           = 0x60,
 297         PHYstatus       = 0x6c,
 298         RxMaxSize       = 0xda,
 299         CPlusCmd        = 0xe0,
 300         IntrMitigate    = 0xe2,
 301         RxDescAddrLow   = 0xe4,
 302         RxDescAddrHigh  = 0xe8,
 303         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 304
 305 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 306
 307         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 308
 309 #define TxPacketMax     (8064 >> 7)
 310
 311         FuncEvent       = 0xf0,
 312         FuncEventMask   = 0xf4,
 313         FuncPresetState = 0xf8,
 314         FuncForceEvent  = 0xfc,
 315 };
 316
 317 enum rtl8110_registers {
 318         TBICSR                  = 0x64,
 319         TBI_ANAR                = 0x68,
 320         TBI_LPAR                = 0x6a,
 321 };
 322
 323 enum rtl8168_8101_registers {
 324         CSIDR                   = 0x64,
 325         CSIAR                   = 0x68,
 326 #define CSIAR_FLAG                      0x80000000
 327 #define CSIAR_WRITE_CMD                 0x80000000
 328 #define CSIAR_BYTE_ENABLE               0x0f
 329 #define CSIAR_BYTE_ENABLE_SHIFT         12
 330 #define CSIAR_ADDR_MASK                 0x0fff
 331         PMCH                    = 0x6f,
 332         EPHYAR                  = 0x80,
 333 #define EPHYAR_FLAG                     0x80000000
 334 #define EPHYAR_WRITE_CMD                0x80000000
 335 #define EPHYAR_REG_MASK                 0x1f
 336 #define EPHYAR_REG_SHIFT                16
 337 #define EPHYAR_DATA_MASK                0xffff
 338         DLLPR                   = 0xd0,
 339 #define PFM_EN                          (1 << 6)
 340         DBG_REG                 = 0xd1,
 341 #define FIX_NAK_1                       (1 << 4)
 342 #define FIX_NAK_2                       (1 << 3)
 343         TWSI                    = 0xd2,
 344         MCU                     = 0xd3,
 345 #define NOW_IS_OOB                      (1 << 7)
 346 #define EN_NDP                          (1 << 3)
 347 #define EN_OOB_RESET                    (1 << 2)
 348         EFUSEAR                 = 0xdc,
 349 #define EFUSEAR_FLAG                    0x80000000
 350 #define EFUSEAR_WRITE_CMD               0x80000000
 351 #define EFUSEAR_READ_CMD                0x00000000
 352 #define EFUSEAR_REG_MASK                0x03ff
 353 #define EFUSEAR_REG_SHIFT               8
 354 #define EFUSEAR_DATA_MASK               0xff
 355 };
 356
 357 enum rtl8168_registers {
 358         LED_FREQ                = 0x1a,
 359         EEE_LED                 = 0x1b,
 360         ERIDR                   = 0x70,
 361         ERIAR                   = 0x74,
 362 #define ERIAR_FLAG                      0x80000000
 363 #define ERIAR_WRITE_CMD                 0x80000000
 364 #define ERIAR_READ_CMD                  0x00000000
 365 #define ERIAR_ADDR_BYTE_ALIGN           4
 366 #define ERIAR_TYPE_SHIFT                16
 367 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 368 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 369 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 370 #define ERIAR_MASK_SHIFT                12
 371 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 372 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 373 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 374         EPHY_RXER_NUM           = 0x7c,
 375         OCPDR                   = 0xb0, /* OCP GPHY access */
 376 #define OCPDR_WRITE_CMD                 0x80000000
 377 #define OCPDR_READ_CMD                  0x00000000
 378 #define OCPDR_REG_MASK                  0x7f
 379 #define OCPDR_GPHY_REG_SHIFT            16
 380 #define OCPDR_DATA_MASK                 0xffff
 381         OCPAR                   = 0xb4,
 382 #define OCPAR_FLAG                      0x80000000
 383 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 384 #define OCPAR_GPHY_READ_CMD             0x0000f060
 385         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 386         MISC                    = 0xf0, /* 8168e only. */
 387 #define TXPLA_RST                       (1 << 29)
 388 #define PWM_EN                          (1 << 22)
 389 };
 390
 391 enum rtl_register_content {
 392         /* InterruptStatusBits */
 393         SYSErr          = 0x8000,
 394         PCSTimeout      = 0x4000,
 395         SWInt           = 0x0100,
 396         TxDescUnavail   = 0x0080,
 397         RxFIFOOver      = 0x0040,
 398         LinkChg         = 0x0020,
 399         RxOverflow      = 0x0010,
 400         TxErr           = 0x0008,
 401         TxOK            = 0x0004,
 402         RxErr           = 0x0002,
 403         RxOK            = 0x0001,
 404
 405         /* RxStatusDesc */
 406         RxFOVF  = (1 << 23),
 407         RxRWT   = (1 << 22),
 408         RxRES   = (1 << 21),
 409         RxRUNT  = (1 << 20),
 410         RxCRC   = (1 << 19),
 411
 412         /* ChipCmdBits */
 413         StopReq         = 0x80,
 414         CmdReset        = 0x10,
 415         CmdRxEnb        = 0x08,
 416         CmdTxEnb        = 0x04,
 417         RxBufEmpty      = 0x01,
 418
 419         /* TXPoll register p.5 */
 420         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 421         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 422         FSWInt          = 0x01,         /* Forced software interrupt */
 423
 424         /* Cfg9346Bits */
 425         Cfg9346_Lock    = 0x00,
 426         Cfg9346_Unlock  = 0xc0,
 427
 428         /* rx_mode_bits */
 429         AcceptErr       = 0x20,
 430         AcceptRunt      = 0x10,
 431         AcceptBroadcast = 0x08,
 432         AcceptMulticast = 0x04,
 433         AcceptMyPhys    = 0x02,
 434         AcceptAllPhys   = 0x01,
 435
 436         /* TxConfigBits */
 437         TxInterFrameGapShift = 24,
 438         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 439
 440         /* Config1 register p.24 */
 441         LEDS1           = (1 << 7),
 442         LEDS0           = (1 << 6),
 443         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 444         Speed_down      = (1 << 4),
 445         MEMMAP          = (1 << 3),
 446         IOMAP           = (1 << 2),
 447         VPD             = (1 << 1),
 448         PMEnable        = (1 << 0),     /* Power Management Enable */
 449
 450         /* Config2 register p. 25 */
 451         PCI_Clock_66MHz = 0x01,
 452         PCI_Clock_33MHz = 0x00,
 453
 454         /* Config3 register p.25 */
 455         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 456         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 457         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 458
 459         /* Config5 register p.27 */
 460         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 461         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 462         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 463         Spi_en          = (1 << 3),
 464         LanWake         = (1 << 1),     /* LanWake enable/disable */
 465         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 466
 467         /* TBICSR p.28 */
 468         TBIReset        = 0x80000000,
 469         TBILoopback     = 0x40000000,
 470         TBINwEnable     = 0x20000000,
 471         TBINwRestart    = 0x10000000,
 472         TBILinkOk       = 0x02000000,
 473         TBINwComplete   = 0x01000000,
 474
 475         /* CPlusCmd p.31 */
 476         EnableBist      = (1 << 15),    // 8168 8101
 477         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 478         Normal_mode     = (1 << 13),    // unused
 479         Force_half_dup  = (1 << 12),    // 8168 8101
 480         Force_rxflow_en = (1 << 11),    // 8168 8101
 481         Force_txflow_en = (1 << 10),    // 8168 8101
 482         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 483         ASF             = (1 << 8),     // 8168 8101
 484         PktCntrDisable  = (1 << 7),     // 8168 8101
 485         Mac_dbgo_sel    = 0x001c,       // 8168
 486         RxVlan          = (1 << 6),
 487         RxChkSum        = (1 << 5),
 488         PCIDAC          = (1 << 4),
 489         PCIMulRW        = (1 << 3),
 490         INTT_0          = 0x0000,       // 8168
 491         INTT_1          = 0x0001,       // 8168
 492         INTT_2          = 0x0002,       // 8168
 493         INTT_3          = 0x0003,       // 8168
 494
 495         /* rtl8169_PHYstatus */
 496         TBI_Enable      = 0x80,
 497         TxFlowCtrl      = 0x40,
 498         RxFlowCtrl      = 0x20,
 499         _1000bpsF       = 0x10,
 500         _100bps         = 0x08,
 501         _10bps          = 0x04,
 502         LinkStatus      = 0x02,
 503         FullDup         = 0x01,
 504
 505         /* _TBICSRBit */
 506         TBILinkOK       = 0x02000000,
 507
 508         /* DumpCounterCommand */
 509         CounterDump     = 0x8,
 510 };
 511
 512 enum rtl_desc_bit {
 513         /* First doubleword. */
 514         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 515         RingEnd         = (1 << 30), /* End of descriptor ring */
 516         FirstFrag       = (1 << 29), /* First segment of a packet */
 517         LastFrag        = (1 << 28), /* Final segment of a packet */
 518 };
 519
 520 /* Generic case. */
 521 enum rtl_tx_desc_bit {
 522         /* First doubleword. */
 523         TD_LSO          = (1 << 27),            /* Large Send Offload */
 524 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 525
 526         /* Second doubleword. */
 527         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 528 };
 529
 530 /* 8169, 8168b and 810x except 8102e. */
 531 enum rtl_tx_desc_bit_0 {
 532         /* First doubleword. */
 533 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 534         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 535         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 536         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 537 };
 538
 539 /* 8102e, 8168c and beyond. */
 540 enum rtl_tx_desc_bit_1 {
 541         /* Second doubleword. */
 542 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 543         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 544         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 545         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 546 };
 547
 548 static const struct rtl_tx_desc_info {
 549         struct {
 550                 u32 udp;
 551                 u32 tcp;
 552         } checksum;
 553         u16 mss_shift;
 554         u16 opts_offset;
 555 } tx_desc_info [] = {
 556         [RTL_TD_0] = {
 557                 .checksum = {
 558                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 559                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 560                 },
 561                 .mss_shift      = TD0_MSS_SHIFT,
 562                 .opts_offset    = 0
 563         },
 564         [RTL_TD_1] = {
 565                 .checksum = {
 566                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 567                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 568                 },
 569                 .mss_shift      = TD1_MSS_SHIFT,
 570                 .opts_offset    = 1
 571         }
 572 };
 573
 574 enum rtl_rx_desc_bit {
 575         /* Rx private */
 576         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 577         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 578
 579 #define RxProtoUDP      (PID1)
 580 #define RxProtoTCP      (PID0)
 581 #define RxProtoIP       (PID1 | PID0)
 582 #define RxProtoMask     RxProtoIP
 583
 584         IPFail          = (1 << 16), /* IP checksum failed */
 585         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 586         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 587         RxVlanTag       = (1 << 16), /* VLAN tag available */
 588 };
 589
 590 #define RsvdMask        0x3fffc000
 591
 592 struct TxDesc {
 593         __le32 opts1;
 594         __le32 opts2;
 595         __le64 addr;
 596 };
 597
 598 struct RxDesc {
 599         __le32 opts1;
 600         __le32 opts2;
 601         __le64 addr;
 602 };
 603
 604 struct ring_info {
 605         struct sk_buff  *skb;
 606         u32             len;
 607         u8              __pad[sizeof(void *) - sizeof(u32)];
 608 };
 609
 610 enum features {
 611         RTL_FEATURE_WOL         = (1 << 0),
 612         RTL_FEATURE_MSI         = (1 << 1),
 613         RTL_FEATURE_GMII        = (1 << 2),
 614 };
 615
 616 struct rtl8169_counters {
 617         __le64  tx_packets;
 618         __le64  rx_packets;
 619         __le64  tx_errors;
 620         __le32  rx_errors;
 621         __le16  rx_missed;
 622         __le16  align_errors;
 623         __le32  tx_one_collision;
 624         __le32  tx_multi_collision;
 625         __le64  rx_unicast;
 626         __le64  rx_broadcast;
 627         __le32  rx_multicast;
 628         __le16  tx_aborted;
 629         __le16  tx_underun;
 630 };
 631
 632 struct rtl8169_private {
 633         void __iomem *mmio_addr;        /* memory map physical address */
 634         struct pci_dev *pci_dev;
 635         struct net_device *dev;
 636         struct napi_struct napi;
 637         spinlock_t lock;
 638         u32 msg_enable;
 639         u16 txd_version;
 640         u16 mac_version;
 641         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 642         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 643         u32 dirty_rx;
 644         u32 dirty_tx;
 645         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 646         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 647         dma_addr_t TxPhyAddr;
 648         dma_addr_t RxPhyAddr;
 649         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 650         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 651         struct timer_list timer;
 652         u16 cp_cmd;
 653         u16 intr_event;
 654         u16 napi_event;
 655         u16 intr_mask;
 656
 657         struct mdio_ops {
 658                 void (*write)(void __iomem *, int, int);
 659                 int (*read)(void __iomem *, int);
 660         } mdio_ops;
 661
 662         struct pll_power_ops {
 663                 void (*down)(struct rtl8169_private *);
 664                 void (*up)(struct rtl8169_private *);
 665         } pll_power_ops;
 666
 667         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 668         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 669         void (*phy_reset_enable)(struct rtl8169_private *tp);
 670         void (*hw_start)(struct net_device *);
 671         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 672         unsigned int (*link_ok)(void __iomem *);
 673         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 674         struct delayed_work task;
 675         unsigned features;
 676
 677         struct mii_if_info mii;
 678         struct rtl8169_counters counters;
 679         u32 saved_wolopts;
 680
 681         struct rtl_fw {
 682                 const struct firmware *fw;
 683
 684 #define RTL_VER_SIZE            32
 685
 686                 char version[RTL_VER_SIZE];
 687
 688                 struct rtl_fw_phy_action {
 689                         __le32 *code;
 690                         size_t size;
 691                 } phy_action;
 692         } *rtl_fw;
 693 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
 694 };
 695
 696 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 697 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 698 module_param(use_dac, int, 0);
 699 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 700 module_param_named(debug, debug.msg_enable, int, 0);
 701 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 702 MODULE_LICENSE("GPL");
 703 MODULE_VERSION(RTL8169_VERSION);
 704 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 705 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 706 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 707 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 708 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 709
 710 static int rtl8169_open(struct net_device *dev);
 711 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 712                                       struct net_device *dev);
 713 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 714 static int rtl8169_init_ring(struct net_device *dev);
 715 static void rtl_hw_start(struct net_device *dev);
 716 static int rtl8169_close(struct net_device *dev);
 717 static void rtl_set_rx_mode(struct net_device *dev);
 718 static void rtl8169_tx_timeout(struct net_device *dev);
 719 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 720 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 721                                 void __iomem *, u32 budget);
 722 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 723 static void rtl8169_down(struct net_device *dev);
 724 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 725 static int rtl8169_poll(struct napi_struct *napi, int budget);
 726
 727 static const unsigned int rtl8169_rx_config = RX_FIFO_THRESH | RX_DMA_BURST;
 728
 729 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 730 {
 731         void __iomem *ioaddr = tp->mmio_addr;
 732         int i;
 733
 734         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 735         for (i = 0; i < 20; i++) {
 736                 udelay(100);
 737                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 738                         break;
 739         }
 740         return RTL_R32(OCPDR);
 741 }
 742
 743 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 744 {
 745         void __iomem *ioaddr = tp->mmio_addr;
 746         int i;
 747
 748         RTL_W32(OCPDR, data);
 749         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 750         for (i = 0; i < 20; i++) {
 751                 udelay(100);
 752                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 753                         break;
 754         }
 755 }
 756
 757 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 758 {
 759         void __iomem *ioaddr = tp->mmio_addr;
 760         int i;
 761
 762         RTL_W8(ERIDR, cmd);
 763         RTL_W32(ERIAR, 0x800010e8);
 764         msleep(2);
 765         for (i = 0; i < 5; i++) {
 766                 udelay(100);
 767                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 768                         break;
 769         }
 770
 771         ocp_write(tp, 0x1, 0x30, 0x00000001);
 772 }
 773
 774 #define OOB_CMD_RESET           0x00
 775 #define OOB_CMD_DRIVER_START    0x05
 776 #define OOB_CMD_DRIVER_STOP     0x06
 777
 778 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 779 {
 780         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 781 }
 782
 783 static void rtl8168_driver_start(struct rtl8169_private *tp)
 784 {
 785         u16 reg;
 786         int i;
 787
 788         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 789
 790         reg = rtl8168_get_ocp_reg(tp);
 791
 792         for (i = 0; i < 10; i++) {
 793                 msleep(10);
 794                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 795                         break;
 796         }
 797 }
 798
 799 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 800 {
 801         u16 reg;
 802         int i;
 803
 804         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 805
 806         reg = rtl8168_get_ocp_reg(tp);
 807
 808         for (i = 0; i < 10; i++) {
 809                 msleep(10);
 810                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 811                         break;
 812         }
 813 }
 814
 815 static int r8168dp_check_dash(struct rtl8169_private *tp)
 816 {
 817         u16 reg = rtl8168_get_ocp_reg(tp);
 818
 819         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 820 }
 821
 822 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 823 {
 824         int i;
 825
 826         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 827
 828         for (i = 20; i > 0; i--) {
 829                 /*
 830                  * Check if the RTL8169 has completed writing to the specified
 831                  * MII register.
 832                  */
 833                 if (!(RTL_R32(PHYAR) & 0x80000000))
 834                         break;
 835                 udelay(25);
 836         }
 837         /*
 838          * According to hardware specs a 20us delay is required after write
 839          * complete indication, but before sending next command.
 840          */
 841         udelay(20);
 842 }
 843
 844 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 845 {
 846         int i, value = -1;
 847
 848         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 849
 850         for (i = 20; i > 0; i--) {
 851                 /*
 852                  * Check if the RTL8169 has completed retrieving data from
 853                  * the specified MII register.
 854                  */
 855                 if (RTL_R32(PHYAR) & 0x80000000) {
 856                         value = RTL_R32(PHYAR) & 0xffff;
 857                         break;
 858                 }
 859                 udelay(25);
 860         }
 861         /*
 862          * According to hardware specs a 20us delay is required after read
 863          * complete indication, but before sending next command.
 864          */
 865         udelay(20);
 866
 867         return value;
 868 }
 869
 870 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 871 {
 872         int i;
 873
 874         RTL_W32(OCPDR, data |
 875                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 876         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 877         RTL_W32(EPHY_RXER_NUM, 0);
 878
 879         for (i = 0; i < 100; i++) {
 880                 mdelay(1);
 881                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 882                         break;
 883         }
 884 }
 885
 886 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 887 {
 888         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 889                 (value & OCPDR_DATA_MASK));
 890 }
 891
 892 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 893 {
 894         int i;
 895
 896         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 897
 898         mdelay(1);
 899         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 900         RTL_W32(EPHY_RXER_NUM, 0);
 901
 902         for (i = 0; i < 100; i++) {
 903                 mdelay(1);
 904                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 905                         break;
 906         }
 907
 908         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 909 }
 910
 911 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 912
 913 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 914 {
 915         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 916 }
 917
 918 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 919 {
 920         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 921 }
 922
 923 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 924 {
 925         r8168dp_2_mdio_start(ioaddr);
 926
 927         r8169_mdio_write(ioaddr, reg_addr, value);
 928
 929         r8168dp_2_mdio_stop(ioaddr);
 930 }
 931
 932 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 933 {
 934         int value;
 935
 936         r8168dp_2_mdio_start(ioaddr);
 937
 938         value = r8169_mdio_read(ioaddr, reg_addr);
 939
 940         r8168dp_2_mdio_stop(ioaddr);
 941
 942         return value;
 943 }
 944
 945 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 946 {
 947         tp->mdio_ops.write(tp->mmio_addr, location, val);
 948 }
 949
 950 static int rtl_readphy(struct rtl8169_private *tp, int location)
 951 {
 952         return tp->mdio_ops.read(tp->mmio_addr, location);
 953 }
 954
 955 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 956 {
 957         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 958 }
 959
 960 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 961 {
 962         int val;
 963
 964         val = rtl_readphy(tp, reg_addr);
 965         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 966 }
 967
 968 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 969                            int val)
 970 {
 971         struct rtl8169_private *tp = netdev_priv(dev);
 972
 973         rtl_writephy(tp, location, val);
 974 }
 975
 976 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 977 {
 978         struct rtl8169_private *tp = netdev_priv(dev);
 979
 980         return rtl_readphy(tp, location);
 981 }
 982
 983 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 984 {
 985         unsigned int i;
 986
 987         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 988                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 989
 990         for (i = 0; i < 100; i++) {
 991                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 992                         break;
 993                 udelay(10);
 994         }
 995 }
 996
 997 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 998 {
 999         u16 value = 0xffff;
1000         unsigned int i;
1001
1002         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1003
1004         for (i = 0; i < 100; i++) {
1005                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1006                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1007                         break;
1008                 }
1009                 udelay(10);
1010         }
1011
1012         return value;
1013 }
1014
1015 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1016 {
1017         unsigned int i;
1018
1019         RTL_W32(CSIDR, value);
1020         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1021                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1022
1023         for (i = 0; i < 100; i++) {
1024                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1025                         break;
1026                 udelay(10);
1027         }
1028 }
1029
1030 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1031 {
1032         u32 value = ~0x00;
1033         unsigned int i;
1034
1035         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1036                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1037
1038         for (i = 0; i < 100; i++) {
1039                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1040                         value = RTL_R32(CSIDR);
1041                         break;
1042                 }
1043                 udelay(10);
1044         }
1045
1046         return value;
1047 }
1048
1049 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1050 {
1051         u8 value = 0xff;
1052         unsigned int i;
1053
1054         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1055
1056         for (i = 0; i < 300; i++) {
1057                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1058                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1059                         break;
1060                 }
1061                 udelay(100);
1062         }
1063
1064         return value;
1065 }
1066
1067 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1068 {
1069         RTL_W16(IntrMask, 0x0000);
1070
1071         RTL_W16(IntrStatus, 0xffff);
1072 }
1073
1074 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1075 {
1076         void __iomem *ioaddr = tp->mmio_addr;
1077
1078         return RTL_R32(TBICSR) & TBIReset;
1079 }
1080
1081 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1082 {
1083         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1084 }
1085
1086 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1087 {
1088         return RTL_R32(TBICSR) & TBILinkOk;
1089 }
1090
1091 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1092 {
1093         return RTL_R8(PHYstatus) & LinkStatus;
1094 }
1095
1096 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1097 {
1098         void __iomem *ioaddr = tp->mmio_addr;
1099
1100         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1101 }
1102
1103 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1104 {
1105         unsigned int val;
1106
1107         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1108         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1109 }
1110
1111 static void __rtl8169_check_link_status(struct net_device *dev,
1112                                         struct rtl8169_private *tp,
1113                                         void __iomem *ioaddr, bool pm)
1114 {
1115         unsigned long flags;
1116
1117         spin_lock_irqsave(&tp->lock, flags);
1118         if (tp->link_ok(ioaddr)) {
1119                 /* This is to cancel a scheduled suspend if there's one. */
1120                 if (pm)
1121                         pm_request_resume(&tp->pci_dev->dev);
1122                 netif_carrier_on(dev);
1123                 if (net_ratelimit())
1124                         netif_info(tp, ifup, dev, "link up\n");
1125         } else {
1126                 netif_carrier_off(dev);
1127                 netif_info(tp, ifdown, dev, "link down\n");
1128                 if (pm)
1129                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1130         }
1131         spin_unlock_irqrestore(&tp->lock, flags);
1132 }
1133
1134 static void rtl8169_check_link_status(struct net_device *dev,
1135                                       struct rtl8169_private *tp,
1136                                       void __iomem *ioaddr)
1137 {
1138         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1139 }
1140
1141 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1142
1143 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1144 {
1145         void __iomem *ioaddr = tp->mmio_addr;
1146         u8 options;
1147         u32 wolopts = 0;
1148
1149         options = RTL_R8(Config1);
1150         if (!(options & PMEnable))
1151                 return 0;
1152
1153         options = RTL_R8(Config3);
1154         if (options & LinkUp)
1155                 wolopts |= WAKE_PHY;
1156         if (options & MagicPacket)
1157                 wolopts |= WAKE_MAGIC;
1158
1159         options = RTL_R8(Config5);
1160         if (options & UWF)
1161                 wolopts |= WAKE_UCAST;
1162         if (options & BWF)
1163                 wolopts |= WAKE_BCAST;
1164         if (options & MWF)
1165                 wolopts |= WAKE_MCAST;
1166
1167         return wolopts;
1168 }
1169
1170 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1171 {
1172         struct rtl8169_private *tp = netdev_priv(dev);
1173
1174         spin_lock_irq(&tp->lock);
1175
1176         wol->supported = WAKE_ANY;
1177         wol->wolopts = __rtl8169_get_wol(tp);
1178
1179         spin_unlock_irq(&tp->lock);
1180 }
1181
1182 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1183 {
1184         void __iomem *ioaddr = tp->mmio_addr;
1185         unsigned int i;
1186         static const struct {
1187                 u32 opt;
1188                 u16 reg;
1189                 u8  mask;
1190         } cfg[] = {
1191                 { WAKE_ANY,   Config1, PMEnable },
1192                 { WAKE_PHY,   Config3, LinkUp },
1193                 { WAKE_MAGIC, Config3, MagicPacket },
1194                 { WAKE_UCAST, Config5, UWF },
1195                 { WAKE_BCAST, Config5, BWF },
1196                 { WAKE_MCAST, Config5, MWF },
1197                 { WAKE_ANY,   Config5, LanWake }
1198         };
1199
1200         RTL_W8(Cfg9346, Cfg9346_Unlock);
1201
1202         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1203                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1204                 if (wolopts & cfg[i].opt)
1205                         options |= cfg[i].mask;
1206                 RTL_W8(cfg[i].reg, options);
1207         }
1208
1209         RTL_W8(Cfg9346, Cfg9346_Lock);
1210 }
1211
1212 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1213 {
1214         struct rtl8169_private *tp = netdev_priv(dev);
1215
1216         spin_lock_irq(&tp->lock);
1217
1218         if (wol->wolopts)
1219                 tp->features |= RTL_FEATURE_WOL;
1220         else
1221                 tp->features &= ~RTL_FEATURE_WOL;
1222         __rtl8169_set_wol(tp, wol->wolopts);
1223         spin_unlock_irq(&tp->lock);
1224
1225         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1226
1227         return 0;
1228 }
1229
1230 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1231 {
1232         return rtl_chip_infos[tp->mac_version].fw_name;
1233 }
1234
1235 static void rtl8169_get_drvinfo(struct net_device *dev,
1236                                 struct ethtool_drvinfo *info)
1237 {
1238         struct rtl8169_private *tp = netdev_priv(dev);
1239         struct rtl_fw *rtl_fw = tp->rtl_fw;
1240
1241         strcpy(info->driver, MODULENAME);
1242         strcpy(info->version, RTL8169_VERSION);
1243         strcpy(info->bus_info, pci_name(tp->pci_dev));
1244         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1245         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1246                rtl_fw->version);
1247 }
1248
1249 static int rtl8169_get_regs_len(struct net_device *dev)
1250 {
1251         return R8169_REGS_SIZE;
1252 }
1253
1254 static int rtl8169_set_speed_tbi(struct net_device *dev,
1255                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1256 {
1257         struct rtl8169_private *tp = netdev_priv(dev);
1258         void __iomem *ioaddr = tp->mmio_addr;
1259         int ret = 0;
1260         u32 reg;
1261
1262         reg = RTL_R32(TBICSR);
1263         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1264             (duplex == DUPLEX_FULL)) {
1265                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1266         } else if (autoneg == AUTONEG_ENABLE)
1267                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1268         else {
1269                 netif_warn(tp, link, dev,
1270                            "incorrect speed setting refused in TBI mode\n");
1271                 ret = -EOPNOTSUPP;
1272         }
1273
1274         return ret;
1275 }
1276
1277 static int rtl8169_set_speed_xmii(struct net_device *dev,
1278                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1279 {
1280         struct rtl8169_private *tp = netdev_priv(dev);
1281         int giga_ctrl, bmcr;
1282         int rc = -EINVAL;
1283
1284         rtl_writephy(tp, 0x1f, 0x0000);
1285
1286         if (autoneg == AUTONEG_ENABLE) {
1287                 int auto_nego;
1288
1289                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1290                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1291                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1292
1293                 if (adv & ADVERTISED_10baseT_Half)
1294                         auto_nego |= ADVERTISE_10HALF;
1295                 if (adv & ADVERTISED_10baseT_Full)
1296                         auto_nego |= ADVERTISE_10FULL;
1297                 if (adv & ADVERTISED_100baseT_Half)
1298                         auto_nego |= ADVERTISE_100HALF;
1299                 if (adv & ADVERTISED_100baseT_Full)
1300                         auto_nego |= ADVERTISE_100FULL;
1301
1302                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1303
1304                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1305                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1306
1307                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1308                 if (tp->mii.supports_gmii) {
1309                         if (adv & ADVERTISED_1000baseT_Half)
1310                                 giga_ctrl |= ADVERTISE_1000HALF;
1311                         if (adv & ADVERTISED_1000baseT_Full)
1312                                 giga_ctrl |= ADVERTISE_1000FULL;
1313                 } else if (adv & (ADVERTISED_1000baseT_Half |
1314                                   ADVERTISED_1000baseT_Full)) {
1315                         netif_info(tp, link, dev,
1316                                    "PHY does not support 1000Mbps\n");
1317                         goto out;
1318                 }
1319
1320                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1321
1322                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1323                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1324         } else {
1325                 giga_ctrl = 0;
1326
1327                 if (speed == SPEED_10)
1328                         bmcr = 0;
1329                 else if (speed == SPEED_100)
1330                         bmcr = BMCR_SPEED100;
1331                 else
1332                         goto out;
1333
1334                 if (duplex == DUPLEX_FULL)
1335                         bmcr |= BMCR_FULLDPLX;
1336         }
1337
1338         rtl_writephy(tp, MII_BMCR, bmcr);
1339
1340         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1341             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1342                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1343                         rtl_writephy(tp, 0x17, 0x2138);
1344                         rtl_writephy(tp, 0x0e, 0x0260);
1345                 } else {
1346                         rtl_writephy(tp, 0x17, 0x2108);
1347                         rtl_writephy(tp, 0x0e, 0x0000);
1348                 }
1349         }
1350
1351         rc = 0;
1352 out:
1353         return rc;
1354 }
1355
1356 static int rtl8169_set_speed(struct net_device *dev,
1357                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1358 {
1359         struct rtl8169_private *tp = netdev_priv(dev);
1360         int ret;
1361
1362         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1363         if (ret < 0)
1364                 goto out;
1365
1366         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1367             (advertising & ADVERTISED_1000baseT_Full)) {
1368                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1369         }
1370 out:
1371         return ret;
1372 }
1373
1374 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1375 {
1376         struct rtl8169_private *tp = netdev_priv(dev);
1377         unsigned long flags;
1378         int ret;
1379
1380         del_timer_sync(&tp->timer);
1381
1382         spin_lock_irqsave(&tp->lock, flags);
1383         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1384                                 cmd->duplex, cmd->advertising);
1385         spin_unlock_irqrestore(&tp->lock, flags);
1386
1387         return ret;
1388 }
1389
1390 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1391 {
1392         if (dev->mtu > TD_MSS_MAX)
1393                 features &= ~NETIF_F_ALL_TSO;
1394
1395         return features;
1396 }
1397
1398 static int rtl8169_set_features(struct net_device *dev, u32 features)
1399 {
1400         struct rtl8169_private *tp = netdev_priv(dev);
1401         void __iomem *ioaddr = tp->mmio_addr;
1402         unsigned long flags;
1403
1404         spin_lock_irqsave(&tp->lock, flags);
1405
1406         if (features & NETIF_F_RXCSUM)
1407                 tp->cp_cmd |= RxChkSum;
1408         else
1409                 tp->cp_cmd &= ~RxChkSum;
1410
1411         if (dev->features & NETIF_F_HW_VLAN_RX)
1412                 tp->cp_cmd |= RxVlan;
1413         else
1414                 tp->cp_cmd &= ~RxVlan;
1415
1416         RTL_W16(CPlusCmd, tp->cp_cmd);
1417         RTL_R16(CPlusCmd);
1418
1419         spin_unlock_irqrestore(&tp->lock, flags);
1420
1421         return 0;
1422 }
1423
1424 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1425                                       struct sk_buff *skb)
1426 {
1427         return (vlan_tx_tag_present(skb)) ?
1428                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1429 }
1430
1431 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1432 {
1433         u32 opts2 = le32_to_cpu(desc->opts2);
1434
1435         if (opts2 & RxVlanTag)
1436                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1437
1438         desc->opts2 = 0;
1439 }
1440
1441 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1442 {
1443         struct rtl8169_private *tp = netdev_priv(dev);
1444         void __iomem *ioaddr = tp->mmio_addr;
1445         u32 status;
1446
1447         cmd->supported =
1448                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1449         cmd->port = PORT_FIBRE;
1450         cmd->transceiver = XCVR_INTERNAL;
1451
1452         status = RTL_R32(TBICSR);
1453         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1454         cmd->autoneg = !!(status & TBINwEnable);
1455
1456         ethtool_cmd_speed_set(cmd, SPEED_1000);
1457         cmd->duplex = DUPLEX_FULL; /* Always set */
1458
1459         return 0;
1460 }
1461
1462 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1463 {
1464         struct rtl8169_private *tp = netdev_priv(dev);
1465
1466         return mii_ethtool_gset(&tp->mii, cmd);
1467 }
1468
1469 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1470 {
1471         struct rtl8169_private *tp = netdev_priv(dev);
1472         unsigned long flags;
1473         int rc;
1474
1475         spin_lock_irqsave(&tp->lock, flags);
1476
1477         rc = tp->get_settings(dev, cmd);
1478
1479         spin_unlock_irqrestore(&tp->lock, flags);
1480         return rc;
1481 }
1482
1483 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1484                              void *p)
1485 {
1486         struct rtl8169_private *tp = netdev_priv(dev);
1487         unsigned long flags;
1488
1489         if (regs->len > R8169_REGS_SIZE)
1490                 regs->len = R8169_REGS_SIZE;
1491
1492         spin_lock_irqsave(&tp->lock, flags);
1493         memcpy_fromio(p, tp->mmio_addr, regs->len);
1494         spin_unlock_irqrestore(&tp->lock, flags);
1495 }
1496
1497 static u32 rtl8169_get_msglevel(struct net_device *dev)
1498 {
1499         struct rtl8169_private *tp = netdev_priv(dev);
1500
1501         return tp->msg_enable;
1502 }
1503
1504 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1505 {
1506         struct rtl8169_private *tp = netdev_priv(dev);
1507
1508         tp->msg_enable = value;
1509 }
1510
1511 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1512         "tx_packets",
1513         "rx_packets",
1514         "tx_errors",
1515         "rx_errors",
1516         "rx_missed",
1517         "align_errors",
1518         "tx_single_collisions",
1519         "tx_multi_collisions",
1520         "unicast",
1521         "broadcast",
1522         "multicast",
1523         "tx_aborted",
1524         "tx_underrun",
1525 };
1526
1527 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1528 {
1529         switch (sset) {
1530         case ETH_SS_STATS:
1531                 return ARRAY_SIZE(rtl8169_gstrings);
1532         default:
1533                 return -EOPNOTSUPP;
1534         }
1535 }
1536
1537 static void rtl8169_update_counters(struct net_device *dev)
1538 {
1539         struct rtl8169_private *tp = netdev_priv(dev);
1540         void __iomem *ioaddr = tp->mmio_addr;
1541         struct device *d = &tp->pci_dev->dev;
1542         struct rtl8169_counters *counters;
1543         dma_addr_t paddr;
1544         u32 cmd;
1545         int wait = 1000;
1546
1547         /*
1548          * Some chips are unable to dump tally counters when the receiver
1549          * is disabled.
1550          */
1551         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1552                 return;
1553
1554         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1555         if (!counters)
1556                 return;
1557
1558         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1559         cmd = (u64)paddr & DMA_BIT_MASK(32);
1560         RTL_W32(CounterAddrLow, cmd);
1561         RTL_W32(CounterAddrLow, cmd | CounterDump);
1562
1563         while (wait--) {
1564                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1565                         memcpy(&tp->counters, counters, sizeof(*counters));
1566                         break;
1567                 }
1568                 udelay(10);
1569         }
1570
1571         RTL_W32(CounterAddrLow, 0);
1572         RTL_W32(CounterAddrHigh, 0);
1573
1574         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1575 }
1576
1577 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1578                                       struct ethtool_stats *stats, u64 *data)
1579 {
1580         struct rtl8169_private *tp = netdev_priv(dev);
1581
1582         ASSERT_RTNL();
1583
1584         rtl8169_update_counters(dev);
1585
1586         data[0] = le64_to_cpu(tp->counters.tx_packets);
1587         data[1] = le64_to_cpu(tp->counters.rx_packets);
1588         data[2] = le64_to_cpu(tp->counters.tx_errors);
1589         data[3] = le32_to_cpu(tp->counters.rx_errors);
1590         data[4] = le16_to_cpu(tp->counters.rx_missed);
1591         data[5] = le16_to_cpu(tp->counters.align_errors);
1592         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1593         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1594         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1595         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1596         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1597         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1598         data[12] = le16_to_cpu(tp->counters.tx_underun);
1599 }
1600
1601 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1602 {
1603         switch(stringset) {
1604         case ETH_SS_STATS:
1605                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1606                 break;
1607         }
1608 }
1609
1610 static const struct ethtool_ops rtl8169_ethtool_ops = {
1611         .get_drvinfo            = rtl8169_get_drvinfo,
1612         .get_regs_len           = rtl8169_get_regs_len,
1613         .get_link               = ethtool_op_get_link,
1614         .get_settings           = rtl8169_get_settings,
1615         .set_settings           = rtl8169_set_settings,
1616         .get_msglevel           = rtl8169_get_msglevel,
1617         .set_msglevel           = rtl8169_set_msglevel,
1618         .get_regs               = rtl8169_get_regs,
1619         .get_wol                = rtl8169_get_wol,
1620         .set_wol                = rtl8169_set_wol,
1621         .get_strings            = rtl8169_get_strings,
1622         .get_sset_count         = rtl8169_get_sset_count,
1623         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1624 };
1625
1626 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1627                                     struct net_device *dev, u8 default_version)
1628 {
1629         void __iomem *ioaddr = tp->mmio_addr;
1630         /*
1631          * The driver currently handles the 8168Bf and the 8168Be identically
1632          * but they can be identified more specifically through the test below
1633          * if needed:
1634          *
1635          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1636          *
1637          * Same thing for the 8101Eb and the 8101Ec:
1638          *
1639          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1640          */
1641         static const struct rtl_mac_info {
1642                 u32 mask;
1643                 u32 val;
1644                 int mac_version;
1645         } mac_info[] = {
1646                 /* 8168E family. */
1647                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1648                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1649                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1650
1651                 /* 8168D family. */
1652                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1653                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1654                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1655
1656                 /* 8168DP family. */
1657                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1658                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1659                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1660
1661                 /* 8168C family. */
1662                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1663                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1664                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1665                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1666                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1667                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1668                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1669                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1670                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1671
1672                 /* 8168B family. */
1673                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1674                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1675                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1676                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1677
1678                 /* 8101 family. */
1679                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1680                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1681                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1682                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1683                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1684                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1685                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1686                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1687                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1688                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1689                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1690                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1691                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1692                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1693                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1694                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1695                 /* FIXME: where did these entries come from ? -- FR */
1696                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1697                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1698
1699                 /* 8110 family. */
1700                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1701                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1702                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1703                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1704                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1705                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1706
1707                 /* Catch-all */
1708                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1709         };
1710         const struct rtl_mac_info *p = mac_info;
1711         u32 reg;
1712
1713         reg = RTL_R32(TxConfig);
1714         while ((reg & p->mask) != p->val)
1715                 p++;
1716         tp->mac_version = p->mac_version;
1717
1718         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1719                 netif_notice(tp, probe, dev,
1720                              "unknown MAC, using family default\n");
1721                 tp->mac_version = default_version;
1722         }
1723 }
1724
1725 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1726 {
1727         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1728 }
1729
1730 struct phy_reg {
1731         u16 reg;
1732         u16 val;
1733 };
1734
1735 static void rtl_writephy_batch(struct rtl8169_private *tp,
1736                                const struct phy_reg *regs, int len)
1737 {
1738         while (len-- > 0) {
1739                 rtl_writephy(tp, regs->reg, regs->val);
1740                 regs++;
1741         }
1742 }
1743
1744 #define PHY_READ                0x00000000
1745 #define PHY_DATA_OR             0x10000000
1746 #define PHY_DATA_AND            0x20000000
1747 #define PHY_BJMPN               0x30000000
1748 #define PHY_READ_EFUSE          0x40000000
1749 #define PHY_READ_MAC_BYTE       0x50000000
1750 #define PHY_WRITE_MAC_BYTE      0x60000000
1751 #define PHY_CLEAR_READCOUNT     0x70000000
1752 #define PHY_WRITE               0x80000000
1753 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1754 #define PHY_COMP_EQ_SKIPN       0xa0000000
1755 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1756 #define PHY_WRITE_PREVIOUS      0xc0000000
1757 #define PHY_SKIPN               0xd0000000
1758 #define PHY_DELAY_MS            0xe0000000
1759 #define PHY_WRITE_ERI_WORD      0xf0000000
1760
1761 struct fw_info {
1762         u32     magic;
1763         char    version[RTL_VER_SIZE];
1764         __le32  fw_start;
1765         __le32  fw_len;
1766         u8      chksum;
1767 } __packed;
1768
1769 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1770
1771 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1772 {
1773         const struct firmware *fw = rtl_fw->fw;
1774         struct fw_info *fw_info = (struct fw_info *)fw->data;
1775         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1776         char *version = rtl_fw->version;
1777         bool rc = false;
1778
1779         if (fw->size < FW_OPCODE_SIZE)
1780                 goto out;
1781
1782         if (!fw_info->magic) {
1783                 size_t i, size, start;
1784                 u8 checksum = 0;
1785
1786                 if (fw->size < sizeof(*fw_info))
1787                         goto out;
1788
1789                 for (i = 0; i < fw->size; i++)
1790                         checksum += fw->data[i];
1791                 if (checksum != 0)
1792                         goto out;
1793
1794                 start = le32_to_cpu(fw_info->fw_start);
1795                 if (start > fw->size)
1796                         goto out;
1797
1798                 size = le32_to_cpu(fw_info->fw_len);
1799                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1800                         goto out;
1801
1802                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1803
1804                 pa->code = (__le32 *)(fw->data + start);
1805                 pa->size = size;
1806         } else {
1807                 if (fw->size % FW_OPCODE_SIZE)
1808                         goto out;
1809
1810                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1811
1812                 pa->code = (__le32 *)fw->data;
1813                 pa->size = fw->size / FW_OPCODE_SIZE;
1814         }
1815         version[RTL_VER_SIZE - 1] = 0;
1816
1817         rc = true;
1818 out:
1819         return rc;
1820 }
1821
1822 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1823                            struct rtl_fw_phy_action *pa)
1824 {
1825         bool rc = false;
1826         size_t index;
1827
1828         for (index = 0; index < pa->size; index++) {
1829                 u32 action = le32_to_cpu(pa->code[index]);
1830                 u32 regno = (action & 0x0fff0000) >> 16;
1831
1832                 switch(action & 0xf0000000) {
1833                 case PHY_READ:
1834                 case PHY_DATA_OR:
1835                 case PHY_DATA_AND:
1836                 case PHY_READ_EFUSE:
1837                 case PHY_CLEAR_READCOUNT:
1838                 case PHY_WRITE:
1839                 case PHY_WRITE_PREVIOUS:
1840                 case PHY_DELAY_MS:
1841                         break;
1842
1843                 case PHY_BJMPN:
1844                         if (regno > index) {
1845                                 netif_err(tp, ifup, tp->dev,
1846                                           "Out of range of firmware\n");
1847                                 goto out;
1848                         }
1849                         break;
1850                 case PHY_READCOUNT_EQ_SKIP:
1851                         if (index + 2 >= pa->size) {
1852                                 netif_err(tp, ifup, tp->dev,
1853                                           "Out of range of firmware\n");
1854                                 goto out;
1855                         }
1856                         break;
1857                 case PHY_COMP_EQ_SKIPN:
1858                 case PHY_COMP_NEQ_SKIPN:
1859                 case PHY_SKIPN:
1860                         if (index + 1 + regno >= pa->size) {
1861                                 netif_err(tp, ifup, tp->dev,
1862                                           "Out of range of firmware\n");
1863                                 goto out;
1864                         }
1865                         break;
1866
1867                 case PHY_READ_MAC_BYTE:
1868                 case PHY_WRITE_MAC_BYTE:
1869                 case PHY_WRITE_ERI_WORD:
1870                 default:
1871                         netif_err(tp, ifup, tp->dev,
1872                                   "Invalid action 0x%08x\n", action);
1873                         goto out;
1874                 }
1875         }
1876         rc = true;
1877 out:
1878         return rc;
1879 }
1880
1881 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1882 {
1883         struct net_device *dev = tp->dev;
1884         int rc = -EINVAL;
1885
1886         if (!rtl_fw_format_ok(tp, rtl_fw)) {
1887                 netif_err(tp, ifup, dev, "invalid firwmare\n");
1888                 goto out;
1889         }
1890
1891         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1892                 rc = 0;
1893 out:
1894         return rc;
1895 }
1896
1897 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1898 {
1899         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1900         u32 predata, count;
1901         size_t index;
1902
1903         predata = count = 0;
1904
1905         for (index = 0; index < pa->size; ) {
1906                 u32 action = le32_to_cpu(pa->code[index]);
1907                 u32 data = action & 0x0000ffff;
1908                 u32 regno = (action & 0x0fff0000) >> 16;
1909
1910                 if (!action)
1911                         break;
1912
1913                 switch(action & 0xf0000000) {
1914                 case PHY_READ:
1915                         predata = rtl_readphy(tp, regno);
1916                         count++;
1917                         index++;
1918                         break;
1919                 case PHY_DATA_OR:
1920                         predata |= data;
1921                         index++;
1922                         break;
1923                 case PHY_DATA_AND:
1924                         predata &= data;
1925                         index++;
1926                         break;
1927                 case PHY_BJMPN:
1928                         index -= regno;
1929                         break;
1930                 case PHY_READ_EFUSE:
1931                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1932                         index++;
1933                         break;
1934                 case PHY_CLEAR_READCOUNT:
1935                         count = 0;
1936                         index++;
1937                         break;
1938                 case PHY_WRITE:
1939                         rtl_writephy(tp, regno, data);
1940                         index++;
1941                         break;
1942                 case PHY_READCOUNT_EQ_SKIP:
1943                         index += (count == data) ? 2 : 1;
1944                         break;
1945                 case PHY_COMP_EQ_SKIPN:
1946                         if (predata == data)
1947                                 index += regno;
1948                         index++;
1949                         break;
1950                 case PHY_COMP_NEQ_SKIPN:
1951                         if (predata != data)
1952                                 index += regno;
1953                         index++;
1954                         break;
1955                 case PHY_WRITE_PREVIOUS:
1956                         rtl_writephy(tp, regno, predata);
1957                         index++;
1958                         break;
1959                 case PHY_SKIPN:
1960                         index += regno + 1;
1961                         break;
1962                 case PHY_DELAY_MS:
1963                         mdelay(data);
1964                         index++;
1965                         break;
1966
1967                 case PHY_READ_MAC_BYTE:
1968                 case PHY_WRITE_MAC_BYTE:
1969                 case PHY_WRITE_ERI_WORD:
1970                 default:
1971                         BUG();
1972                 }
1973         }
1974 }
1975
1976 static void rtl_release_firmware(struct rtl8169_private *tp)
1977 {
1978         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
1979                 release_firmware(tp->rtl_fw->fw);
1980                 kfree(tp->rtl_fw);
1981         }
1982         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
1983 }
1984
1985 static void rtl_apply_firmware(struct rtl8169_private *tp)
1986 {
1987         struct rtl_fw *rtl_fw = tp->rtl_fw;
1988
1989         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1990         if (!IS_ERR_OR_NULL(rtl_fw))
1991                 rtl_phy_write_fw(tp, rtl_fw);
1992 }
1993
1994 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1995 {
1996         if (rtl_readphy(tp, reg) != val)
1997                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1998         else
1999                 rtl_apply_firmware(tp);
2000 }
2001
2002 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2003 {
2004         static const struct phy_reg phy_reg_init[] = {
2005                 { 0x1f, 0x0001 },
2006                 { 0x06, 0x006e },
2007                 { 0x08, 0x0708 },
2008                 { 0x15, 0x4000 },
2009                 { 0x18, 0x65c7 },
2010
2011                 { 0x1f, 0x0001 },
2012                 { 0x03, 0x00a1 },
2013                 { 0x02, 0x0008 },
2014                 { 0x01, 0x0120 },
2015                 { 0x00, 0x1000 },
2016                 { 0x04, 0x0800 },
2017                 { 0x04, 0x0000 },
2018
2019                 { 0x03, 0xff41 },
2020                 { 0x02, 0xdf60 },
2021                 { 0x01, 0x0140 },
2022                 { 0x00, 0x0077 },
2023                 { 0x04, 0x7800 },
2024                 { 0x04, 0x7000 },
2025
2026                 { 0x03, 0x802f },
2027                 { 0x02, 0x4f02 },
2028                 { 0x01, 0x0409 },
2029                 { 0x00, 0xf0f9 },
2030                 { 0x04, 0x9800 },
2031                 { 0x04, 0x9000 },
2032
2033                 { 0x03, 0xdf01 },
2034                 { 0x02, 0xdf20 },
2035                 { 0x01, 0xff95 },
2036                 { 0x00, 0xba00 },
2037                 { 0x04, 0xa800 },
2038                 { 0x04, 0xa000 },
2039
2040                 { 0x03, 0xff41 },
2041                 { 0x02, 0xdf20 },
2042                 { 0x01, 0x0140 },
2043                 { 0x00, 0x00bb },
2044                 { 0x04, 0xb800 },
2045                 { 0x04, 0xb000 },
2046
2047                 { 0x03, 0xdf41 },
2048                 { 0x02, 0xdc60 },
2049                 { 0x01, 0x6340 },
2050                 { 0x00, 0x007d },
2051                 { 0x04, 0xd800 },
2052                 { 0x04, 0xd000 },
2053
2054                 { 0x03, 0xdf01 },
2055                 { 0x02, 0xdf20 },
2056                 { 0x01, 0x100a },
2057                 { 0x00, 0xa0ff },
2058                 { 0x04, 0xf800 },
2059                 { 0x04, 0xf000 },
2060
2061                 { 0x1f, 0x0000 },
2062                 { 0x0b, 0x0000 },
2063                 { 0x00, 0x9200 }
2064         };
2065
2066         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2067 }
2068
2069 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2070 {
2071         static const struct phy_reg phy_reg_init[] = {
2072                 { 0x1f, 0x0002 },
2073                 { 0x01, 0x90d0 },
2074                 { 0x1f, 0x0000 }
2075         };
2076
2077         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2078 }
2079
2080 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2081 {
2082         struct pci_dev *pdev = tp->pci_dev;
2083         u16 vendor_id, device_id;
2084
2085         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2086         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2087
2088         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2089                 return;
2090
2091         rtl_writephy(tp, 0x1f, 0x0001);
2092         rtl_writephy(tp, 0x10, 0xf01b);
2093         rtl_writephy(tp, 0x1f, 0x0000);
2094 }
2095
2096 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2097 {
2098         static const struct phy_reg phy_reg_init[] = {
2099                 { 0x1f, 0x0001 },
2100                 { 0x04, 0x0000 },
2101                 { 0x03, 0x00a1 },
2102                 { 0x02, 0x0008 },
2103                 { 0x01, 0x0120 },
2104                 { 0x00, 0x1000 },
2105                 { 0x04, 0x0800 },
2106                 { 0x04, 0x9000 },
2107                 { 0x03, 0x802f },
2108                 { 0x02, 0x4f02 },
2109                 { 0x01, 0x0409 },
2110                 { 0x00, 0xf099 },
2111                 { 0x04, 0x9800 },
2112                 { 0x04, 0xa000 },
2113                 { 0x03, 0xdf01 },
2114                 { 0x02, 0xdf20 },
2115                 { 0x01, 0xff95 },
2116                 { 0x00, 0xba00 },
2117                 { 0x04, 0xa800 },
2118                 { 0x04, 0xf000 },
2119                 { 0x03, 0xdf01 },
2120                 { 0x02, 0xdf20 },
2121                 { 0x01, 0x101a },
2122                 { 0x00, 0xa0ff },
2123                 { 0x04, 0xf800 },
2124                 { 0x04, 0x0000 },
2125                 { 0x1f, 0x0000 },
2126
2127                 { 0x1f, 0x0001 },
2128                 { 0x10, 0xf41b },
2129                 { 0x14, 0xfb54 },
2130                 { 0x18, 0xf5c7 },
2131                 { 0x1f, 0x0000 },
2132
2133                 { 0x1f, 0x0001 },
2134                 { 0x17, 0x0cc0 },
2135                 { 0x1f, 0x0000 }
2136         };
2137
2138         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2139
2140         rtl8169scd_hw_phy_config_quirk(tp);
2141 }
2142
2143 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2144 {
2145         static const struct phy_reg phy_reg_init[] = {
2146                 { 0x1f, 0x0001 },
2147                 { 0x04, 0x0000 },
2148                 { 0x03, 0x00a1 },
2149                 { 0x02, 0x0008 },
2150                 { 0x01, 0x0120 },
2151                 { 0x00, 0x1000 },
2152                 { 0x04, 0x0800 },
2153                 { 0x04, 0x9000 },
2154                 { 0x03, 0x802f },
2155                 { 0x02, 0x4f02 },
2156                 { 0x01, 0x0409 },
2157                 { 0x00, 0xf099 },
2158                 { 0x04, 0x9800 },
2159                 { 0x04, 0xa000 },
2160                 { 0x03, 0xdf01 },
2161                 { 0x02, 0xdf20 },
2162                 { 0x01, 0xff95 },
2163                 { 0x00, 0xba00 },
2164                 { 0x04, 0xa800 },
2165                 { 0x04, 0xf000 },
2166                 { 0x03, 0xdf01 },
2167                 { 0x02, 0xdf20 },
2168                 { 0x01, 0x101a },
2169                 { 0x00, 0xa0ff },
2170                 { 0x04, 0xf800 },
2171                 { 0x04, 0x0000 },
2172                 { 0x1f, 0x0000 },
2173
2174                 { 0x1f, 0x0001 },
2175                 { 0x0b, 0x8480 },
2176                 { 0x1f, 0x0000 },
2177
2178                 { 0x1f, 0x0001 },
2179                 { 0x18, 0x67c7 },
2180                 { 0x04, 0x2000 },
2181                 { 0x03, 0x002f },
2182                 { 0x02, 0x4360 },
2183                 { 0x01, 0x0109 },
2184                 { 0x00, 0x3022 },
2185                 { 0x04, 0x2800 },
2186                 { 0x1f, 0x0000 },
2187
2188                 { 0x1f, 0x0001 },
2189                 { 0x17, 0x0cc0 },
2190                 { 0x1f, 0x0000 }
2191         };
2192
2193         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2194 }
2195
2196 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2197 {
2198         static const struct phy_reg phy_reg_init[] = {
2199                 { 0x10, 0xf41b },
2200                 { 0x1f, 0x0000 }
2201         };
2202
2203         rtl_writephy(tp, 0x1f, 0x0001);
2204         rtl_patchphy(tp, 0x16, 1 << 0);
2205
2206         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2207 }
2208
2209 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2210 {
2211         static const struct phy_reg phy_reg_init[] = {
2212                 { 0x1f, 0x0001 },
2213                 { 0x10, 0xf41b },
2214                 { 0x1f, 0x0000 }
2215         };
2216
2217         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2218 }
2219
2220 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2221 {
2222         static const struct phy_reg phy_reg_init[] = {
2223                 { 0x1f, 0x0000 },
2224                 { 0x1d, 0x0f00 },
2225                 { 0x1f, 0x0002 },
2226                 { 0x0c, 0x1ec8 },
2227                 { 0x1f, 0x0000 }
2228         };
2229
2230         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2231 }
2232
2233 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2234 {
2235         static const struct phy_reg phy_reg_init[] = {
2236                 { 0x1f, 0x0001 },
2237                 { 0x1d, 0x3d98 },
2238                 { 0x1f, 0x0000 }
2239         };
2240
2241         rtl_writephy(tp, 0x1f, 0x0000);
2242         rtl_patchphy(tp, 0x14, 1 << 5);
2243         rtl_patchphy(tp, 0x0d, 1 << 5);
2244
2245         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2246 }
2247
2248 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2249 {
2250         static const struct phy_reg phy_reg_init[] = {
2251                 { 0x1f, 0x0001 },
2252                 { 0x12, 0x2300 },
2253                 { 0x1f, 0x0002 },
2254                 { 0x00, 0x88d4 },
2255                 { 0x01, 0x82b1 },
2256                 { 0x03, 0x7002 },
2257                 { 0x08, 0x9e30 },
2258                 { 0x09, 0x01f0 },
2259                 { 0x0a, 0x5500 },
2260                 { 0x0c, 0x00c8 },
2261                 { 0x1f, 0x0003 },
2262                 { 0x12, 0xc096 },
2263                 { 0x16, 0x000a },
2264                 { 0x1f, 0x0000 },
2265                 { 0x1f, 0x0000 },
2266                 { 0x09, 0x2000 },
2267                 { 0x09, 0x0000 }
2268         };
2269
2270         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2271
2272         rtl_patchphy(tp, 0x14, 1 << 5);
2273         rtl_patchphy(tp, 0x0d, 1 << 5);
2274         rtl_writephy(tp, 0x1f, 0x0000);
2275 }
2276
2277 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2278 {
2279         static const struct phy_reg phy_reg_init[] = {
2280                 { 0x1f, 0x0001 },
2281                 { 0x12, 0x2300 },
2282                 { 0x03, 0x802f },
2283                 { 0x02, 0x4f02 },
2284                 { 0x01, 0x0409 },
2285                 { 0x00, 0xf099 },
2286                 { 0x04, 0x9800 },
2287                 { 0x04, 0x9000 },
2288                 { 0x1d, 0x3d98 },
2289                 { 0x1f, 0x0002 },
2290                 { 0x0c, 0x7eb8 },
2291                 { 0x06, 0x0761 },
2292                 { 0x1f, 0x0003 },
2293                 { 0x16, 0x0f0a },
2294                 { 0x1f, 0x0000 }
2295         };
2296
2297         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2298
2299         rtl_patchphy(tp, 0x16, 1 << 0);
2300         rtl_patchphy(tp, 0x14, 1 << 5);
2301         rtl_patchphy(tp, 0x0d, 1 << 5);
2302         rtl_writephy(tp, 0x1f, 0x0000);
2303 }
2304
2305 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2306 {
2307         static const struct phy_reg phy_reg_init[] = {
2308                 { 0x1f, 0x0001 },
2309                 { 0x12, 0x2300 },
2310                 { 0x1d, 0x3d98 },
2311                 { 0x1f, 0x0002 },
2312                 { 0x0c, 0x7eb8 },
2313                 { 0x06, 0x5461 },
2314                 { 0x1f, 0x0003 },
2315                 { 0x16, 0x0f0a },
2316                 { 0x1f, 0x0000 }
2317         };
2318
2319         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2320
2321         rtl_patchphy(tp, 0x16, 1 << 0);
2322         rtl_patchphy(tp, 0x14, 1 << 5);
2323         rtl_patchphy(tp, 0x0d, 1 << 5);
2324         rtl_writephy(tp, 0x1f, 0x0000);
2325 }
2326
2327 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2328 {
2329         rtl8168c_3_hw_phy_config(tp);
2330 }
2331
2332 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2333 {
2334         static const struct phy_reg phy_reg_init_0[] = {
2335                 /* Channel Estimation */
2336                 { 0x1f, 0x0001 },
2337                 { 0x06, 0x4064 },
2338                 { 0x07, 0x2863 },
2339                 { 0x08, 0x059c },
2340                 { 0x09, 0x26b4 },
2341                 { 0x0a, 0x6a19 },
2342                 { 0x0b, 0xdcc8 },
2343                 { 0x10, 0xf06d },
2344                 { 0x14, 0x7f68 },
2345                 { 0x18, 0x7fd9 },
2346                 { 0x1c, 0xf0ff },
2347                 { 0x1d, 0x3d9c },
2348                 { 0x1f, 0x0003 },
2349                 { 0x12, 0xf49f },
2350                 { 0x13, 0x070b },
2351                 { 0x1a, 0x05ad },
2352                 { 0x14, 0x94c0 },
2353
2354                 /*
2355                  * Tx Error Issue
2356                  * Enhance line driver power
2357                  */
2358                 { 0x1f, 0x0002 },
2359                 { 0x06, 0x5561 },
2360                 { 0x1f, 0x0005 },
2361                 { 0x05, 0x8332 },
2362                 { 0x06, 0x5561 },
2363
2364                 /*
2365                  * Can not link to 1Gbps with bad cable
2366                  * Decrease SNR threshold form 21.07dB to 19.04dB
2367                  */
2368                 { 0x1f, 0x0001 },
2369                 { 0x17, 0x0cc0 },
2370
2371                 { 0x1f, 0x0000 },
2372                 { 0x0d, 0xf880 }
2373         };
2374         void __iomem *ioaddr = tp->mmio_addr;
2375
2376         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2377
2378         /*
2379          * Rx Error Issue
2380          * Fine Tune Switching regulator parameter
2381          */
2382         rtl_writephy(tp, 0x1f, 0x0002);
2383         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2384         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2385
2386         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2387                 static const struct phy_reg phy_reg_init[] = {
2388                         { 0x1f, 0x0002 },
2389                         { 0x05, 0x669a },
2390                         { 0x1f, 0x0005 },
2391                         { 0x05, 0x8330 },
2392                         { 0x06, 0x669a },
2393                         { 0x1f, 0x0002 }
2394                 };
2395                 int val;
2396
2397                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2398
2399                 val = rtl_readphy(tp, 0x0d);
2400
2401                 if ((val & 0x00ff) != 0x006c) {
2402                         static const u32 set[] = {
2403                                 0x0065, 0x0066, 0x0067, 0x0068,
2404                                 0x0069, 0x006a, 0x006b, 0x006c
2405                         };
2406                         int i;
2407
2408                         rtl_writephy(tp, 0x1f, 0x0002);
2409
2410                         val &= 0xff00;
2411                         for (i = 0; i < ARRAY_SIZE(set); i++)
2412                                 rtl_writephy(tp, 0x0d, val | set[i]);
2413                 }
2414         } else {
2415                 static const struct phy_reg phy_reg_init[] = {
2416                         { 0x1f, 0x0002 },
2417                         { 0x05, 0x6662 },
2418                         { 0x1f, 0x0005 },
2419                         { 0x05, 0x8330 },
2420                         { 0x06, 0x6662 }
2421                 };
2422
2423                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2424         }
2425
2426         /* RSET couple improve */
2427         rtl_writephy(tp, 0x1f, 0x0002);
2428         rtl_patchphy(tp, 0x0d, 0x0300);
2429         rtl_patchphy(tp, 0x0f, 0x0010);
2430
2431         /* Fine tune PLL performance */
2432         rtl_writephy(tp, 0x1f, 0x0002);
2433         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2434         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2435
2436         rtl_writephy(tp, 0x1f, 0x0005);
2437         rtl_writephy(tp, 0x05, 0x001b);
2438
2439         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2440
2441         rtl_writephy(tp, 0x1f, 0x0000);
2442 }
2443
2444 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2445 {
2446         static const struct phy_reg phy_reg_init_0[] = {
2447                 /* Channel Estimation */
2448                 { 0x1f, 0x0001 },
2449                 { 0x06, 0x4064 },
2450                 { 0x07, 0x2863 },
2451                 { 0x08, 0x059c },
2452                 { 0x09, 0x26b4 },
2453                 { 0x0a, 0x6a19 },
2454                 { 0x0b, 0xdcc8 },
2455                 { 0x10, 0xf06d },
2456                 { 0x14, 0x7f68 },
2457                 { 0x18, 0x7fd9 },
2458                 { 0x1c, 0xf0ff },
2459                 { 0x1d, 0x3d9c },
2460                 { 0x1f, 0x0003 },
2461                 { 0x12, 0xf49f },
2462                 { 0x13, 0x070b },
2463                 { 0x1a, 0x05ad },
2464                 { 0x14, 0x94c0 },
2465
2466                 /*
2467                  * Tx Error Issue
2468                  * Enhance line driver power
2469                  */
2470                 { 0x1f, 0x0002 },
2471                 { 0x06, 0x5561 },
2472                 { 0x1f, 0x0005 },
2473                 { 0x05, 0x8332 },
2474                 { 0x06, 0x5561 },
2475
2476                 /*
2477                  * Can not link to 1Gbps with bad cable
2478                  * Decrease SNR threshold form 21.07dB to 19.04dB
2479                  */
2480                 { 0x1f, 0x0001 },
2481                 { 0x17, 0x0cc0 },
2482
2483                 { 0x1f, 0x0000 },
2484                 { 0x0d, 0xf880 }
2485         };
2486         void __iomem *ioaddr = tp->mmio_addr;
2487
2488         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2489
2490         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2491                 static const struct phy_reg phy_reg_init[] = {
2492                         { 0x1f, 0x0002 },
2493                         { 0x05, 0x669a },
2494                         { 0x1f, 0x0005 },
2495                         { 0x05, 0x8330 },
2496                         { 0x06, 0x669a },
2497
2498                         { 0x1f, 0x0002 }
2499                 };
2500                 int val;
2501
2502                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2503
2504                 val = rtl_readphy(tp, 0x0d);
2505                 if ((val & 0x00ff) != 0x006c) {
2506                         static const u32 set[] = {
2507                                 0x0065, 0x0066, 0x0067, 0x0068,
2508                                 0x0069, 0x006a, 0x006b, 0x006c
2509                         };
2510                         int i;
2511
2512                         rtl_writephy(tp, 0x1f, 0x0002);
2513
2514                         val &= 0xff00;
2515                         for (i = 0; i < ARRAY_SIZE(set); i++)
2516                                 rtl_writephy(tp, 0x0d, val | set[i]);
2517                 }
2518         } else {
2519                 static const struct phy_reg phy_reg_init[] = {
2520                         { 0x1f, 0x0002 },
2521                         { 0x05, 0x2642 },
2522                         { 0x1f, 0x0005 },
2523                         { 0x05, 0x8330 },
2524                         { 0x06, 0x2642 }
2525                 };
2526
2527                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2528         }
2529
2530         /* Fine tune PLL performance */
2531         rtl_writephy(tp, 0x1f, 0x0002);
2532         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2533         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2534
2535         /* Switching regulator Slew rate */
2536         rtl_writephy(tp, 0x1f, 0x0002);
2537         rtl_patchphy(tp, 0x0f, 0x0017);
2538
2539         rtl_writephy(tp, 0x1f, 0x0005);
2540         rtl_writephy(tp, 0x05, 0x001b);
2541
2542         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2543
2544         rtl_writephy(tp, 0x1f, 0x0000);
2545 }
2546
2547 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2548 {
2549         static const struct phy_reg phy_reg_init[] = {
2550                 { 0x1f, 0x0002 },
2551                 { 0x10, 0x0008 },
2552                 { 0x0d, 0x006c },
2553
2554                 { 0x1f, 0x0000 },
2555                 { 0x0d, 0xf880 },
2556
2557                 { 0x1f, 0x0001 },
2558                 { 0x17, 0x0cc0 },
2559
2560                 { 0x1f, 0x0001 },
2561                 { 0x0b, 0xa4d8 },
2562                 { 0x09, 0x281c },
2563                 { 0x07, 0x2883 },
2564                 { 0x0a, 0x6b35 },
2565                 { 0x1d, 0x3da4 },
2566                 { 0x1c, 0xeffd },
2567                 { 0x14, 0x7f52 },
2568                 { 0x18, 0x7fc6 },
2569                 { 0x08, 0x0601 },
2570                 { 0x06, 0x4063 },
2571                 { 0x10, 0xf074 },
2572                 { 0x1f, 0x0003 },
2573                 { 0x13, 0x0789 },
2574                 { 0x12, 0xf4bd },
2575                 { 0x1a, 0x04fd },
2576                 { 0x14, 0x84b0 },
2577                 { 0x1f, 0x0000 },
2578                 { 0x00, 0x9200 },
2579
2580                 { 0x1f, 0x0005 },
2581                 { 0x01, 0x0340 },
2582                 { 0x1f, 0x0001 },
2583                 { 0x04, 0x4000 },
2584                 { 0x03, 0x1d21 },
2585                 { 0x02, 0x0c32 },
2586                 { 0x01, 0x0200 },
2587                 { 0x00, 0x5554 },
2588                 { 0x04, 0x4800 },
2589                 { 0x04, 0x4000 },
2590                 { 0x04, 0xf000 },
2591                 { 0x03, 0xdf01 },
2592                 { 0x02, 0xdf20 },
2593                 { 0x01, 0x101a },
2594                 { 0x00, 0xa0ff },
2595                 { 0x04, 0xf800 },
2596                 { 0x04, 0xf000 },
2597                 { 0x1f, 0x0000 },
2598
2599                 { 0x1f, 0x0007 },
2600                 { 0x1e, 0x0023 },
2601                 { 0x16, 0x0000 },
2602                 { 0x1f, 0x0000 }
2603         };
2604
2605         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2606 }
2607
2608 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2609 {
2610         static const struct phy_reg phy_reg_init[] = {
2611                 { 0x1f, 0x0001 },
2612                 { 0x17, 0x0cc0 },
2613
2614                 { 0x1f, 0x0007 },
2615                 { 0x1e, 0x002d },
2616                 { 0x18, 0x0040 },
2617                 { 0x1f, 0x0000 }
2618         };
2619
2620         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2621         rtl_patchphy(tp, 0x0d, 1 << 5);
2622 }
2623
2624 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2625 {
2626         static const struct phy_reg phy_reg_init[] = {
2627                 /* Enable Delay cap */
2628                 { 0x1f, 0x0005 },
2629                 { 0x05, 0x8b80 },
2630                 { 0x06, 0xc896 },
2631                 { 0x1f, 0x0000 },
2632
2633                 /* Channel estimation fine tune */
2634                 { 0x1f, 0x0001 },
2635                 { 0x0b, 0x6c20 },
2636                 { 0x07, 0x2872 },
2637                 { 0x1c, 0xefff },
2638                 { 0x1f, 0x0003 },
2639                 { 0x14, 0x6420 },
2640                 { 0x1f, 0x0000 },
2641
2642                 /* Update PFM & 10M TX idle timer */
2643                 { 0x1f, 0x0007 },
2644                 { 0x1e, 0x002f },
2645                 { 0x15, 0x1919 },
2646                 { 0x1f, 0x0000 },
2647
2648                 { 0x1f, 0x0007 },
2649                 { 0x1e, 0x00ac },
2650                 { 0x18, 0x0006 },
2651                 { 0x1f, 0x0000 }
2652         };
2653
2654         rtl_apply_firmware(tp);
2655
2656         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2657
2658         /* DCO enable for 10M IDLE Power */
2659         rtl_writephy(tp, 0x1f, 0x0007);
2660         rtl_writephy(tp, 0x1e, 0x0023);
2661         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2662         rtl_writephy(tp, 0x1f, 0x0000);
2663
2664         /* For impedance matching */
2665         rtl_writephy(tp, 0x1f, 0x0002);
2666         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2667         rtl_writephy(tp, 0x1f, 0x0000);
2668
2669         /* PHY auto speed down */
2670         rtl_writephy(tp, 0x1f, 0x0007);
2671         rtl_writephy(tp, 0x1e, 0x002d);
2672         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2673         rtl_writephy(tp, 0x1f, 0x0000);
2674         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2675
2676         rtl_writephy(tp, 0x1f, 0x0005);
2677         rtl_writephy(tp, 0x05, 0x8b86);
2678         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2679         rtl_writephy(tp, 0x1f, 0x0000);
2680
2681         rtl_writephy(tp, 0x1f, 0x0005);
2682         rtl_writephy(tp, 0x05, 0x8b85);
2683         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2684         rtl_writephy(tp, 0x1f, 0x0007);
2685         rtl_writephy(tp, 0x1e, 0x0020);
2686         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2687         rtl_writephy(tp, 0x1f, 0x0006);
2688         rtl_writephy(tp, 0x00, 0x5a00);
2689         rtl_writephy(tp, 0x1f, 0x0000);
2690         rtl_writephy(tp, 0x0d, 0x0007);
2691         rtl_writephy(tp, 0x0e, 0x003c);
2692         rtl_writephy(tp, 0x0d, 0x4007);
2693         rtl_writephy(tp, 0x0e, 0x0000);
2694         rtl_writephy(tp, 0x0d, 0x0000);
2695 }
2696
2697 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2698 {
2699         static const struct phy_reg phy_reg_init[] = {
2700                 { 0x1f, 0x0003 },
2701                 { 0x08, 0x441d },
2702                 { 0x01, 0x9100 },
2703                 { 0x1f, 0x0000 }
2704         };
2705
2706         rtl_writephy(tp, 0x1f, 0x0000);
2707         rtl_patchphy(tp, 0x11, 1 << 12);
2708         rtl_patchphy(tp, 0x19, 1 << 13);
2709         rtl_patchphy(tp, 0x10, 1 << 15);
2710
2711         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2712 }
2713
2714 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2715 {
2716         static const struct phy_reg phy_reg_init[] = {
2717                 { 0x1f, 0x0005 },
2718                 { 0x1a, 0x0000 },
2719                 { 0x1f, 0x0000 },
2720
2721                 { 0x1f, 0x0004 },
2722                 { 0x1c, 0x0000 },
2723                 { 0x1f, 0x0000 },
2724
2725                 { 0x1f, 0x0001 },
2726                 { 0x15, 0x7701 },
2727                 { 0x1f, 0x0000 }
2728         };
2729
2730         /* Disable ALDPS before ram code */
2731         rtl_writephy(tp, 0x1f, 0x0000);
2732         rtl_writephy(tp, 0x18, 0x0310);
2733         msleep(100);
2734
2735         rtl_apply_firmware(tp);
2736
2737         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2738 }
2739
2740 static void rtl_hw_phy_config(struct net_device *dev)
2741 {
2742         struct rtl8169_private *tp = netdev_priv(dev);
2743
2744         rtl8169_print_mac_version(tp);
2745
2746         switch (tp->mac_version) {
2747         case RTL_GIGA_MAC_VER_01:
2748                 break;
2749         case RTL_GIGA_MAC_VER_02:
2750         case RTL_GIGA_MAC_VER_03:
2751                 rtl8169s_hw_phy_config(tp);
2752                 break;
2753         case RTL_GIGA_MAC_VER_04:
2754                 rtl8169sb_hw_phy_config(tp);
2755                 break;
2756         case RTL_GIGA_MAC_VER_05:
2757                 rtl8169scd_hw_phy_config(tp);
2758                 break;
2759         case RTL_GIGA_MAC_VER_06:
2760                 rtl8169sce_hw_phy_config(tp);
2761                 break;
2762         case RTL_GIGA_MAC_VER_07:
2763         case RTL_GIGA_MAC_VER_08:
2764         case RTL_GIGA_MAC_VER_09:
2765                 rtl8102e_hw_phy_config(tp);
2766                 break;
2767         case RTL_GIGA_MAC_VER_11:
2768                 rtl8168bb_hw_phy_config(tp);
2769                 break;
2770         case RTL_GIGA_MAC_VER_12:
2771                 rtl8168bef_hw_phy_config(tp);
2772                 break;
2773         case RTL_GIGA_MAC_VER_17:
2774                 rtl8168bef_hw_phy_config(tp);
2775                 break;
2776         case RTL_GIGA_MAC_VER_18:
2777                 rtl8168cp_1_hw_phy_config(tp);
2778                 break;
2779         case RTL_GIGA_MAC_VER_19:
2780                 rtl8168c_1_hw_phy_config(tp);
2781                 break;
2782         case RTL_GIGA_MAC_VER_20:
2783                 rtl8168c_2_hw_phy_config(tp);
2784                 break;
2785         case RTL_GIGA_MAC_VER_21:
2786                 rtl8168c_3_hw_phy_config(tp);
2787                 break;
2788         case RTL_GIGA_MAC_VER_22:
2789                 rtl8168c_4_hw_phy_config(tp);
2790                 break;
2791         case RTL_GIGA_MAC_VER_23:
2792         case RTL_GIGA_MAC_VER_24:
2793                 rtl8168cp_2_hw_phy_config(tp);
2794                 break;
2795         case RTL_GIGA_MAC_VER_25:
2796                 rtl8168d_1_hw_phy_config(tp);
2797                 break;
2798         case RTL_GIGA_MAC_VER_26:
2799                 rtl8168d_2_hw_phy_config(tp);
2800                 break;
2801         case RTL_GIGA_MAC_VER_27:
2802                 rtl8168d_3_hw_phy_config(tp);
2803                 break;
2804         case RTL_GIGA_MAC_VER_28:
2805                 rtl8168d_4_hw_phy_config(tp);
2806                 break;
2807         case RTL_GIGA_MAC_VER_29:
2808         case RTL_GIGA_MAC_VER_30:
2809                 rtl8105e_hw_phy_config(tp);
2810                 break;
2811         case RTL_GIGA_MAC_VER_31:
2812                 /* None. */
2813                 break;
2814         case RTL_GIGA_MAC_VER_32:
2815         case RTL_GIGA_MAC_VER_33:
2816                 rtl8168e_hw_phy_config(tp);
2817                 break;
2818
2819         default:
2820                 break;
2821         }
2822 }
2823
2824 static void rtl8169_phy_timer(unsigned long __opaque)
2825 {
2826         struct net_device *dev = (struct net_device *)__opaque;
2827         struct rtl8169_private *tp = netdev_priv(dev);
2828         struct timer_list *timer = &tp->timer;
2829         void __iomem *ioaddr = tp->mmio_addr;
2830         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2831
2832         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2833
2834         spin_lock_irq(&tp->lock);
2835
2836         if (tp->phy_reset_pending(tp)) {
2837                 /*
2838                  * A busy loop could burn quite a few cycles on nowadays CPU.
2839                  * Let's delay the execution of the timer for a few ticks.
2840                  */
2841                 timeout = HZ/10;
2842                 goto out_mod_timer;
2843         }
2844
2845         if (tp->link_ok(ioaddr))
2846                 goto out_unlock;
2847
2848         netif_warn(tp, link, dev, "PHY reset until link up\n");
2849
2850         tp->phy_reset_enable(tp);
2851
2852 out_mod_timer:
2853         mod_timer(timer, jiffies + timeout);
2854 out_unlock:
2855         spin_unlock_irq(&tp->lock);
2856 }
2857
2858 #ifdef CONFIG_NET_POLL_CONTROLLER
2859 /*
2860  * Polling 'interrupt' - used by things like netconsole to send skbs
2861  * without having to re-enable interrupts. It's not called while
2862  * the interrupt routine is executing.
2863  */
2864 static void rtl8169_netpoll(struct net_device *dev)
2865 {
2866         struct rtl8169_private *tp = netdev_priv(dev);
2867         struct pci_dev *pdev = tp->pci_dev;
2868
2869         disable_irq(pdev->irq);
2870         rtl8169_interrupt(pdev->irq, dev);
2871         enable_irq(pdev->irq);
2872 }
2873 #endif
2874
2875 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2876                                   void __iomem *ioaddr)
2877 {
2878         iounmap(ioaddr);
2879         pci_release_regions(pdev);
2880         pci_clear_mwi(pdev);
2881         pci_disable_device(pdev);
2882         free_netdev(dev);
2883 }
2884
2885 static void rtl8169_phy_reset(struct net_device *dev,
2886                               struct rtl8169_private *tp)
2887 {
2888         unsigned int i;
2889
2890         tp->phy_reset_enable(tp);
2891         for (i = 0; i < 100; i++) {
2892                 if (!tp->phy_reset_pending(tp))
2893                         return;
2894                 msleep(1);
2895         }
2896         netif_err(tp, link, dev, "PHY reset failed\n");
2897 }
2898
2899 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2900 {
2901         void __iomem *ioaddr = tp->mmio_addr;
2902
2903         rtl_hw_phy_config(dev);
2904
2905         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2906                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2907                 RTL_W8(0x82, 0x01);
2908         }
2909
2910         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2911
2912         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2913                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2914
2915         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2916                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2917                 RTL_W8(0x82, 0x01);
2918                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2919                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2920         }
2921
2922         rtl8169_phy_reset(dev, tp);
2923
2924         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2925                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2926                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2927                           (tp->mii.supports_gmii ?
2928                            ADVERTISED_1000baseT_Half |
2929                            ADVERTISED_1000baseT_Full : 0));
2930
2931         if (RTL_R8(PHYstatus) & TBI_Enable)
2932                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2933 }
2934
2935 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2936 {
2937         void __iomem *ioaddr = tp->mmio_addr;
2938         u32 high;
2939         u32 low;
2940
2941         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2942         high = addr[4] | (addr[5] << 8);
2943
2944         spin_lock_irq(&tp->lock);
2945
2946         RTL_W8(Cfg9346, Cfg9346_Unlock);
2947
2948         RTL_W32(MAC4, high);
2949         RTL_R32(MAC4);
2950
2951         RTL_W32(MAC0, low);
2952         RTL_R32(MAC0);
2953
2954         RTL_W8(Cfg9346, Cfg9346_Lock);
2955
2956         spin_unlock_irq(&tp->lock);
2957 }
2958
2959 static int rtl_set_mac_address(struct net_device *dev, void *p)
2960 {
2961         struct rtl8169_private *tp = netdev_priv(dev);
2962         struct sockaddr *addr = p;
2963
2964         if (!is_valid_ether_addr(addr->sa_data))
2965                 return -EADDRNOTAVAIL;
2966
2967         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2968
2969         rtl_rar_set(tp, dev->dev_addr);
2970
2971         return 0;
2972 }
2973
2974 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2975 {
2976         struct rtl8169_private *tp = netdev_priv(dev);
2977         struct mii_ioctl_data *data = if_mii(ifr);
2978
2979         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2980 }
2981
2982 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2983                           struct mii_ioctl_data *data, int cmd)
2984 {
2985         switch (cmd) {
2986         case SIOCGMIIPHY:
2987                 data->phy_id = 32; /* Internal PHY */
2988                 return 0;
2989
2990         case SIOCGMIIREG:
2991                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2992                 return 0;
2993
2994         case SIOCSMIIREG:
2995                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2996                 return 0;
2997         }
2998         return -EOPNOTSUPP;
2999 }
3000
3001 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3002 {
3003         return -EOPNOTSUPP;
3004 }
3005
3006 static const struct rtl_cfg_info {
3007         void (*hw_start)(struct net_device *);
3008         unsigned int region;
3009         unsigned int align;
3010         u16 intr_event;
3011         u16 napi_event;
3012         unsigned features;
3013         u8 default_ver;
3014 } rtl_cfg_infos [] = {
3015         [RTL_CFG_0] = {
3016                 .hw_start       = rtl_hw_start_8169,
3017                 .region         = 1,
3018                 .align          = 0,
3019                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3020                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3021                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3022                 .features       = RTL_FEATURE_GMII,
3023                 .default_ver    = RTL_GIGA_MAC_VER_01,
3024         },
3025         [RTL_CFG_1] = {
3026                 .hw_start       = rtl_hw_start_8168,
3027                 .region         = 2,
3028                 .align          = 8,
3029                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3030                                   TxErr | TxOK | RxOK | RxErr,
3031                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3032                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3033                 .default_ver    = RTL_GIGA_MAC_VER_11,
3034         },
3035         [RTL_CFG_2] = {
3036                 .hw_start       = rtl_hw_start_8101,
3037                 .region         = 2,
3038                 .align          = 8,
3039                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3040                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3041                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3042                 .features       = RTL_FEATURE_MSI,
3043                 .default_ver    = RTL_GIGA_MAC_VER_13,
3044         }
3045 };
3046
3047 /* Cfg9346_Unlock assumed. */
3048 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3049                             const struct rtl_cfg_info *cfg)
3050 {
3051         unsigned msi = 0;
3052         u8 cfg2;
3053
3054         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3055         if (cfg->features & RTL_FEATURE_MSI) {
3056                 if (pci_enable_msi(pdev)) {
3057                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3058                 } else {
3059                         cfg2 |= MSIEnable;
3060                         msi = RTL_FEATURE_MSI;
3061                 }
3062         }
3063         RTL_W8(Config2, cfg2);
3064         return msi;
3065 }
3066
3067 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3068 {
3069         if (tp->features & RTL_FEATURE_MSI) {
3070                 pci_disable_msi(pdev);
3071                 tp->features &= ~RTL_FEATURE_MSI;
3072         }
3073 }
3074
3075 static const struct net_device_ops rtl8169_netdev_ops = {
3076         .ndo_open               = rtl8169_open,
3077         .ndo_stop               = rtl8169_close,
3078         .ndo_get_stats          = rtl8169_get_stats,
3079         .ndo_start_xmit         = rtl8169_start_xmit,
3080         .ndo_tx_timeout         = rtl8169_tx_timeout,
3081         .ndo_validate_addr      = eth_validate_addr,
3082         .ndo_change_mtu         = rtl8169_change_mtu,
3083         .ndo_fix_features       = rtl8169_fix_features,
3084         .ndo_set_features       = rtl8169_set_features,
3085         .ndo_set_mac_address    = rtl_set_mac_address,
3086         .ndo_do_ioctl           = rtl8169_ioctl,
3087         .ndo_set_multicast_list = rtl_set_rx_mode,
3088 #ifdef CONFIG_NET_POLL_CONTROLLER
3089         .ndo_poll_controller    = rtl8169_netpoll,
3090 #endif
3091
3092 };
3093
3094 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3095 {
3096         struct mdio_ops *ops = &tp->mdio_ops;
3097
3098         switch (tp->mac_version) {
3099         case RTL_GIGA_MAC_VER_27:
3100                 ops->write      = r8168dp_1_mdio_write;
3101                 ops->read       = r8168dp_1_mdio_read;
3102                 break;
3103         case RTL_GIGA_MAC_VER_28:
3104         case RTL_GIGA_MAC_VER_31:
3105                 ops->write      = r8168dp_2_mdio_write;
3106                 ops->read       = r8168dp_2_mdio_read;
3107                 break;
3108         default:
3109                 ops->write      = r8169_mdio_write;
3110                 ops->read       = r8169_mdio_read;
3111                 break;
3112         }
3113 }
3114
3115 static void r810x_phy_power_down(struct rtl8169_private *tp)
3116 {
3117         rtl_writephy(tp, 0x1f, 0x0000);
3118         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3119 }
3120
3121 static void r810x_phy_power_up(struct rtl8169_private *tp)
3122 {
3123         rtl_writephy(tp, 0x1f, 0x0000);
3124         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3125 }
3126
3127 static void r810x_pll_power_down(struct rtl8169_private *tp)
3128 {
3129         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3130                 rtl_writephy(tp, 0x1f, 0x0000);
3131                 rtl_writephy(tp, MII_BMCR, 0x0000);
3132                 return;
3133         }
3134
3135         r810x_phy_power_down(tp);
3136 }
3137
3138 static void r810x_pll_power_up(struct rtl8169_private *tp)
3139 {
3140         r810x_phy_power_up(tp);
3141 }
3142
3143 static void r8168_phy_power_up(struct rtl8169_private *tp)
3144 {
3145         rtl_writephy(tp, 0x1f, 0x0000);
3146         switch (tp->mac_version) {
3147         case RTL_GIGA_MAC_VER_11:
3148         case RTL_GIGA_MAC_VER_12:
3149         case RTL_GIGA_MAC_VER_17:
3150         case RTL_GIGA_MAC_VER_18:
3151         case RTL_GIGA_MAC_VER_19:
3152         case RTL_GIGA_MAC_VER_20:
3153         case RTL_GIGA_MAC_VER_21:
3154         case RTL_GIGA_MAC_VER_22:
3155         case RTL_GIGA_MAC_VER_23:
3156         case RTL_GIGA_MAC_VER_24:
3157         case RTL_GIGA_MAC_VER_25:
3158         case RTL_GIGA_MAC_VER_26:
3159         case RTL_GIGA_MAC_VER_27:
3160         case RTL_GIGA_MAC_VER_28:
3161         case RTL_GIGA_MAC_VER_31:
3162                 rtl_writephy(tp, 0x0e, 0x0000);
3163                 break;
3164         default:
3165                 break;
3166         }
3167         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3168 }
3169
3170 static void r8168_phy_power_down(struct rtl8169_private *tp)
3171 {
3172         rtl_writephy(tp, 0x1f, 0x0000);
3173         switch (tp->mac_version) {
3174         case RTL_GIGA_MAC_VER_32:
3175         case RTL_GIGA_MAC_VER_33:
3176                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3177                 break;
3178
3179         case RTL_GIGA_MAC_VER_11:
3180         case RTL_GIGA_MAC_VER_12:
3181         case RTL_GIGA_MAC_VER_17:
3182         case RTL_GIGA_MAC_VER_18:
3183         case RTL_GIGA_MAC_VER_19:
3184         case RTL_GIGA_MAC_VER_20:
3185         case RTL_GIGA_MAC_VER_21:
3186         case RTL_GIGA_MAC_VER_22:
3187         case RTL_GIGA_MAC_VER_23:
3188         case RTL_GIGA_MAC_VER_24:
3189         case RTL_GIGA_MAC_VER_25:
3190         case RTL_GIGA_MAC_VER_26:
3191         case RTL_GIGA_MAC_VER_27:
3192         case RTL_GIGA_MAC_VER_28:
3193         case RTL_GIGA_MAC_VER_31:
3194                 rtl_writephy(tp, 0x0e, 0x0200);
3195         default:
3196                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3197                 break;
3198         }
3199 }
3200
3201 static void r8168_pll_power_down(struct rtl8169_private *tp)
3202 {
3203         void __iomem *ioaddr = tp->mmio_addr;
3204
3205         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3206              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3207              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3208             r8168dp_check_dash(tp)) {
3209                 return;
3210         }
3211
3212         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3213              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3214             (RTL_R16(CPlusCmd) & ASF)) {
3215                 return;
3216         }
3217
3218         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3219             tp->mac_version == RTL_GIGA_MAC_VER_33)
3220                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3221
3222         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3223                 rtl_writephy(tp, 0x1f, 0x0000);
3224                 rtl_writephy(tp, MII_BMCR, 0x0000);
3225
3226                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3227                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3228                 return;
3229         }
3230
3231         r8168_phy_power_down(tp);
3232
3233         switch (tp->mac_version) {
3234         case RTL_GIGA_MAC_VER_25:
3235         case RTL_GIGA_MAC_VER_26:
3236         case RTL_GIGA_MAC_VER_27:
3237         case RTL_GIGA_MAC_VER_28:
3238         case RTL_GIGA_MAC_VER_31:
3239         case RTL_GIGA_MAC_VER_32:
3240         case RTL_GIGA_MAC_VER_33:
3241                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3242                 break;
3243         }
3244 }
3245
3246 static void r8168_pll_power_up(struct rtl8169_private *tp)
3247 {
3248         void __iomem *ioaddr = tp->mmio_addr;
3249
3250         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3251              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3252              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3253             r8168dp_check_dash(tp)) {
3254                 return;
3255         }
3256
3257         switch (tp->mac_version) {
3258         case RTL_GIGA_MAC_VER_25:
3259         case RTL_GIGA_MAC_VER_26:
3260         case RTL_GIGA_MAC_VER_27:
3261         case RTL_GIGA_MAC_VER_28:
3262         case RTL_GIGA_MAC_VER_31:
3263         case RTL_GIGA_MAC_VER_32:
3264         case RTL_GIGA_MAC_VER_33:
3265                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3266                 break;
3267         }
3268
3269         r8168_phy_power_up(tp);
3270 }
3271
3272 static void rtl_pll_power_op(struct rtl8169_private *tp,
3273                              void (*op)(struct rtl8169_private *))
3274 {
3275         if (op)
3276                 op(tp);
3277 }
3278
3279 static void rtl_pll_power_down(struct rtl8169_private *tp)
3280 {
3281         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3282 }
3283
3284 static void rtl_pll_power_up(struct rtl8169_private *tp)
3285 {
3286         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3287 }
3288
3289 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3290 {
3291         struct pll_power_ops *ops = &tp->pll_power_ops;
3292
3293         switch (tp->mac_version) {
3294         case RTL_GIGA_MAC_VER_07:
3295         case RTL_GIGA_MAC_VER_08:
3296         case RTL_GIGA_MAC_VER_09:
3297         case RTL_GIGA_MAC_VER_10:
3298         case RTL_GIGA_MAC_VER_16:
3299         case RTL_GIGA_MAC_VER_29:
3300         case RTL_GIGA_MAC_VER_30:
3301                 ops->down       = r810x_pll_power_down;
3302                 ops->up         = r810x_pll_power_up;
3303                 break;
3304
3305         case RTL_GIGA_MAC_VER_11:
3306         case RTL_GIGA_MAC_VER_12:
3307         case RTL_GIGA_MAC_VER_17:
3308         case RTL_GIGA_MAC_VER_18:
3309         case RTL_GIGA_MAC_VER_19:
3310         case RTL_GIGA_MAC_VER_20:
3311         case RTL_GIGA_MAC_VER_21:
3312         case RTL_GIGA_MAC_VER_22:
3313         case RTL_GIGA_MAC_VER_23:
3314         case RTL_GIGA_MAC_VER_24:
3315         case RTL_GIGA_MAC_VER_25:
3316         case RTL_GIGA_MAC_VER_26:
3317         case RTL_GIGA_MAC_VER_27:
3318         case RTL_GIGA_MAC_VER_28:
3319         case RTL_GIGA_MAC_VER_31:
3320         case RTL_GIGA_MAC_VER_32:
3321         case RTL_GIGA_MAC_VER_33:
3322                 ops->down       = r8168_pll_power_down;
3323                 ops->up         = r8168_pll_power_up;
3324                 break;
3325
3326         default:
3327                 ops->down       = NULL;
3328                 ops->up         = NULL;
3329                 break;
3330         }
3331 }
3332
3333 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3334 {
3335         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3336 }
3337
3338 static void rtl_hw_reset(struct rtl8169_private *tp)
3339 {
3340         void __iomem *ioaddr = tp->mmio_addr;
3341         int i;
3342
3343         /* Soft reset the chip. */
3344         RTL_W8(ChipCmd, CmdReset);
3345
3346         /* Check that the chip has finished the reset. */
3347         for (i = 0; i < 100; i++) {
3348                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3349                         break;
3350                 udelay(100);
3351         }
3352
3353         rtl8169_init_ring_indexes(tp);
3354 }
3355
3356 static int __devinit
3357 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3358 {
3359         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3360         const unsigned int region = cfg->region;
3361         struct rtl8169_private *tp;
3362         struct mii_if_info *mii;
3363         struct net_device *dev;
3364         void __iomem *ioaddr;
3365         int chipset, i;
3366         int rc;
3367
3368         if (netif_msg_drv(&debug)) {
3369                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3370                        MODULENAME, RTL8169_VERSION);
3371         }
3372
3373         dev = alloc_etherdev(sizeof (*tp));
3374         if (!dev) {
3375                 if (netif_msg_drv(&debug))
3376                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3377                 rc = -ENOMEM;
3378                 goto out;
3379         }
3380
3381         SET_NETDEV_DEV(dev, &pdev->dev);
3382         dev->netdev_ops = &rtl8169_netdev_ops;
3383         tp = netdev_priv(dev);
3384         tp->dev = dev;
3385         tp->pci_dev = pdev;
3386         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3387
3388         mii = &tp->mii;
3389         mii->dev = dev;
3390         mii->mdio_read = rtl_mdio_read;
3391         mii->mdio_write = rtl_mdio_write;
3392         mii->phy_id_mask = 0x1f;
3393         mii->reg_num_mask = 0x1f;
3394         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3395
3396         /* disable ASPM completely as that cause random device stop working
3397          * problems as well as full system hangs for some PCIe devices users */
3398         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3399                                      PCIE_LINK_STATE_CLKPM);
3400
3401         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3402         rc = pci_enable_device(pdev);
3403         if (rc < 0) {
3404                 netif_err(tp, probe, dev, "enable failure\n");
3405                 goto err_out_free_dev_1;
3406         }
3407
3408         if (pci_set_mwi(pdev) < 0)
3409                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3410
3411         /* make sure PCI base addr 1 is MMIO */
3412         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3413                 netif_err(tp, probe, dev,
3414                           "region #%d not an MMIO resource, aborting\n",
3415                           region);
3416                 rc = -ENODEV;
3417                 goto err_out_mwi_2;
3418         }
3419
3420         /* check for weird/broken PCI region reporting */
3421         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3422                 netif_err(tp, probe, dev,
3423                           "Invalid PCI region size(s), aborting\n");
3424                 rc = -ENODEV;
3425                 goto err_out_mwi_2;
3426         }
3427
3428         rc = pci_request_regions(pdev, MODULENAME);
3429         if (rc < 0) {
3430                 netif_err(tp, probe, dev, "could not request regions\n");
3431                 goto err_out_mwi_2;
3432         }
3433
3434         tp->cp_cmd = RxChkSum;
3435
3436         if ((sizeof(dma_addr_t) > 4) &&
3437             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3438                 tp->cp_cmd |= PCIDAC;
3439                 dev->features |= NETIF_F_HIGHDMA;
3440         } else {
3441                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3442                 if (rc < 0) {
3443                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3444                         goto err_out_free_res_3;
3445                 }
3446         }
3447
3448         /* ioremap MMIO region */
3449         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3450         if (!ioaddr) {
3451                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3452                 rc = -EIO;
3453                 goto err_out_free_res_3;
3454         }
3455         tp->mmio_addr = ioaddr;
3456
3457         if (!pci_is_pcie(pdev))
3458                 netif_info(tp, probe, dev, "not PCI Express\n");
3459
3460         RTL_W16(IntrMask, 0x0000);
3461
3462         rtl_hw_reset(tp);
3463
3464         RTL_W16(IntrStatus, 0xffff);
3465
3466         pci_set_master(pdev);
3467
3468         /* Identify chip attached to board */
3469         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3470
3471         /*
3472          * Pretend we are using VLANs; This bypasses a nasty bug where
3473          * Interrupts stop flowing on high load on 8110SCd controllers.
3474          */
3475         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3476                 tp->cp_cmd |= RxVlan;
3477
3478         rtl_init_mdio_ops(tp);
3479         rtl_init_pll_power_ops(tp);
3480
3481         rtl8169_print_mac_version(tp);
3482
3483         chipset = tp->mac_version;
3484         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3485
3486         RTL_W8(Cfg9346, Cfg9346_Unlock);
3487         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3488         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3489         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3490                 tp->features |= RTL_FEATURE_WOL;
3491         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3492                 tp->features |= RTL_FEATURE_WOL;
3493         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3494         RTL_W8(Cfg9346, Cfg9346_Lock);
3495
3496         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3497             (RTL_R8(PHYstatus) & TBI_Enable)) {
3498                 tp->set_speed = rtl8169_set_speed_tbi;
3499                 tp->get_settings = rtl8169_gset_tbi;
3500                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3501                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3502                 tp->link_ok = rtl8169_tbi_link_ok;
3503                 tp->do_ioctl = rtl_tbi_ioctl;
3504         } else {
3505                 tp->set_speed = rtl8169_set_speed_xmii;
3506                 tp->get_settings = rtl8169_gset_xmii;
3507                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3508                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3509                 tp->link_ok = rtl8169_xmii_link_ok;
3510                 tp->do_ioctl = rtl_xmii_ioctl;
3511         }
3512
3513         spin_lock_init(&tp->lock);
3514
3515         /* Get MAC address */
3516         for (i = 0; i < MAC_ADDR_LEN; i++)
3517                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3518         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3519
3520         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3521         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3522         dev->irq = pdev->irq;
3523         dev->base_addr = (unsigned long) ioaddr;
3524
3525         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3526
3527         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3528          * properly for all devices */
3529         dev->features |= NETIF_F_RXCSUM |
3530                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3531
3532         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3533                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3534         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3535                 NETIF_F_HIGHDMA;
3536
3537         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3538                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3539                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3540
3541         tp->intr_mask = 0xffff;
3542         tp->hw_start = cfg->hw_start;
3543         tp->intr_event = cfg->intr_event;
3544         tp->napi_event = cfg->napi_event;
3545
3546         init_timer(&tp->timer);
3547         tp->timer.data = (unsigned long) dev;
3548         tp->timer.function = rtl8169_phy_timer;
3549
3550         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3551
3552         rc = register_netdev(dev);
3553         if (rc < 0)
3554                 goto err_out_msi_4;
3555
3556         pci_set_drvdata(pdev, dev);
3557
3558         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3559                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3560                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3561
3562         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3563             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3564             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3565                 rtl8168_driver_start(tp);
3566         }
3567
3568         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3569
3570         if (pci_dev_run_wake(pdev))
3571                 pm_runtime_put_noidle(&pdev->dev);
3572
3573         netif_carrier_off(dev);
3574
3575 out:
3576         return rc;
3577
3578 err_out_msi_4:
3579         rtl_disable_msi(pdev, tp);
3580         iounmap(ioaddr);
3581 err_out_free_res_3:
3582         pci_release_regions(pdev);
3583 err_out_mwi_2:
3584         pci_clear_mwi(pdev);
3585         pci_disable_device(pdev);
3586 err_out_free_dev_1:
3587         free_netdev(dev);
3588         goto out;
3589 }
3590
3591 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3592 {
3593         struct net_device *dev = pci_get_drvdata(pdev);
3594         struct rtl8169_private *tp = netdev_priv(dev);
3595
3596         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3597             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3598             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3599                 rtl8168_driver_stop(tp);
3600         }
3601
3602         cancel_delayed_work_sync(&tp->task);
3603
3604         unregister_netdev(dev);
3605
3606         rtl_release_firmware(tp);
3607
3608         if (pci_dev_run_wake(pdev))
3609                 pm_runtime_get_noresume(&pdev->dev);
3610
3611         /* restore original MAC address */
3612         rtl_rar_set(tp, dev->perm_addr);
3613
3614         rtl_disable_msi(pdev, tp);
3615         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3616         pci_set_drvdata(pdev, NULL);
3617 }
3618
3619 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3620 {
3621         struct rtl_fw *rtl_fw;
3622         const char *name;
3623         int rc = -ENOMEM;
3624
3625         name = rtl_lookup_firmware_name(tp);
3626         if (!name)
3627                 goto out_no_firmware;
3628
3629         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3630         if (!rtl_fw)
3631                 goto err_warn;
3632
3633         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3634         if (rc < 0)
3635                 goto err_free;
3636
3637         rc = rtl_check_firmware(tp, rtl_fw);
3638         if (rc < 0)
3639                 goto err_release_firmware;
3640
3641         tp->rtl_fw = rtl_fw;
3642 out:
3643         return;
3644
3645 err_release_firmware:
3646         release_firmware(rtl_fw->fw);
3647 err_free:
3648         kfree(rtl_fw);
3649 err_warn:
3650         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3651                    name, rc);
3652 out_no_firmware:
3653         tp->rtl_fw = NULL;
3654         goto out;
3655 }
3656
3657 static void rtl_request_firmware(struct rtl8169_private *tp)
3658 {
3659         if (IS_ERR(tp->rtl_fw))
3660                 rtl_request_uncached_firmware(tp);
3661 }
3662
3663 static int rtl8169_open(struct net_device *dev)
3664 {
3665         struct rtl8169_private *tp = netdev_priv(dev);
3666         void __iomem *ioaddr = tp->mmio_addr;
3667         struct pci_dev *pdev = tp->pci_dev;
3668         int retval = -ENOMEM;
3669
3670         pm_runtime_get_sync(&pdev->dev);
3671
3672         /*
3673          * Rx and Tx desscriptors needs 256 bytes alignment.
3674          * dma_alloc_coherent provides more.
3675          */
3676         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3677                                              &tp->TxPhyAddr, GFP_KERNEL);
3678         if (!tp->TxDescArray)
3679                 goto err_pm_runtime_put;
3680
3681         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3682                                              &tp->RxPhyAddr, GFP_KERNEL);
3683         if (!tp->RxDescArray)
3684                 goto err_free_tx_0;
3685
3686         retval = rtl8169_init_ring(dev);
3687         if (retval < 0)
3688                 goto err_free_rx_1;
3689
3690         INIT_DELAYED_WORK(&tp->task, NULL);
3691
3692         smp_mb();
3693
3694         rtl_request_firmware(tp);
3695
3696         retval = request_irq(dev->irq, rtl8169_interrupt,
3697                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3698                              dev->name, dev);
3699         if (retval < 0)
3700                 goto err_release_fw_2;
3701
3702         napi_enable(&tp->napi);
3703
3704         rtl8169_init_phy(dev, tp);
3705
3706         rtl8169_set_features(dev, dev->features);
3707
3708         rtl_pll_power_up(tp);
3709
3710         rtl_hw_start(dev);
3711
3712         tp->saved_wolopts = 0;
3713         pm_runtime_put_noidle(&pdev->dev);
3714
3715         rtl8169_check_link_status(dev, tp, ioaddr);
3716 out:
3717         return retval;
3718
3719 err_release_fw_2:
3720         rtl_release_firmware(tp);
3721         rtl8169_rx_clear(tp);
3722 err_free_rx_1:
3723         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3724                           tp->RxPhyAddr);
3725         tp->RxDescArray = NULL;
3726 err_free_tx_0:
3727         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3728                           tp->TxPhyAddr);
3729         tp->TxDescArray = NULL;
3730 err_pm_runtime_put:
3731         pm_runtime_put_noidle(&pdev->dev);
3732         goto out;
3733 }
3734
3735 static void rtl_rx_close(struct rtl8169_private *tp)
3736 {
3737         void __iomem *ioaddr = tp->mmio_addr;
3738         u32 rxcfg = RTL_R32(RxConfig);
3739
3740         rxcfg &= ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast |
3741                    AcceptMyPhys | AcceptAllPhys);
3742         RTL_W32(RxConfig, rxcfg);
3743 }
3744
3745 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3746 {
3747         void __iomem *ioaddr = tp->mmio_addr;
3748
3749         /* Disable interrupts */
3750         rtl8169_irq_mask_and_ack(ioaddr);
3751
3752         rtl_rx_close(tp);
3753
3754         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3755             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3756             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3757                 while (RTL_R8(TxPoll) & NPQ)
3758                         udelay(20);
3759         } else {
3760                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3761                 udelay(100);
3762         }
3763
3764         rtl_hw_reset(tp);
3765 }
3766
3767 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3768 {
3769         void __iomem *ioaddr = tp->mmio_addr;
3770         u32 cfg = rtl8169_rx_config;
3771
3772         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3773         RTL_W32(RxConfig, cfg);
3774
3775         /* Set DMA burst size and Interframe Gap Time */
3776         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3777                 (InterFrameGap << TxInterFrameGapShift));
3778 }
3779
3780 static void rtl_hw_start(struct net_device *dev)
3781 {
3782         struct rtl8169_private *tp = netdev_priv(dev);
3783
3784         tp->hw_start(dev);
3785
3786         netif_start_queue(dev);
3787 }
3788
3789 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3790                                          void __iomem *ioaddr)
3791 {
3792         /*
3793          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3794          * register to be written before TxDescAddrLow to work.
3795          * Switching from MMIO to I/O access fixes the issue as well.
3796          */
3797         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3798         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3799         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3800         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3801 }
3802
3803 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3804 {
3805         u16 cmd;
3806
3807         cmd = RTL_R16(CPlusCmd);
3808         RTL_W16(CPlusCmd, cmd);
3809         return cmd;
3810 }
3811
3812 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3813 {
3814         /* Low hurts. Let's disable the filtering. */
3815         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3816 }
3817
3818 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3819 {
3820         static const struct rtl_cfg2_info {
3821                 u32 mac_version;
3822                 u32 clk;
3823                 u32 val;
3824         } cfg2_info [] = {
3825                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3826                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3827                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3828                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3829         };
3830         const struct rtl_cfg2_info *p = cfg2_info;
3831         unsigned int i;
3832         u32 clk;
3833
3834         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3835         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3836                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3837                         RTL_W32(0x7c, p->val);
3838                         break;
3839                 }
3840         }
3841 }
3842
3843 static void rtl_hw_start_8169(struct net_device *dev)
3844 {
3845         struct rtl8169_private *tp = netdev_priv(dev);
3846         void __iomem *ioaddr = tp->mmio_addr;
3847         struct pci_dev *pdev = tp->pci_dev;
3848
3849         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3850                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3851                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3852         }
3853
3854         RTL_W8(Cfg9346, Cfg9346_Unlock);
3855         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3856             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3857             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3858             tp->mac_version == RTL_GIGA_MAC_VER_04)
3859                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3860
3861         RTL_W8(EarlyTxThres, NoEarlyTx);
3862
3863         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3864
3865         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3866             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3867             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3868             tp->mac_version == RTL_GIGA_MAC_VER_04)
3869                 rtl_set_rx_tx_config_registers(tp);
3870
3871         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3872
3873         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3874             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3875                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3876                         "Bit-3 and bit-14 MUST be 1\n");
3877                 tp->cp_cmd |= (1 << 14);
3878         }
3879
3880         RTL_W16(CPlusCmd, tp->cp_cmd);
3881
3882         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3883
3884         /*
3885          * Undocumented corner. Supposedly:
3886          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3887          */
3888         RTL_W16(IntrMitigate, 0x0000);
3889
3890         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3891
3892         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3893             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3894             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3895             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3896                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3897                 rtl_set_rx_tx_config_registers(tp);
3898         }
3899
3900         RTL_W8(Cfg9346, Cfg9346_Lock);
3901
3902         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3903         RTL_R8(IntrMask);
3904
3905         RTL_W32(RxMissed, 0);
3906
3907         rtl_set_rx_mode(dev);
3908
3909         /* no early-rx interrupts */
3910         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3911
3912         /* Enable all known interrupts by setting the interrupt mask. */
3913         RTL_W16(IntrMask, tp->intr_event);
3914 }
3915
3916 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3917 {
3918         int cap = pci_pcie_cap(pdev);
3919
3920         if (cap) {
3921                 u16 ctl;
3922
3923                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3924                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3925                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3926         }
3927 }
3928
3929 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3930 {
3931         u32 csi;
3932
3933         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3934         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3935 }
3936
3937 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3938 {
3939         rtl_csi_access_enable(ioaddr, 0x17000000);
3940 }
3941
3942 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3943 {
3944         rtl_csi_access_enable(ioaddr, 0x27000000);
3945 }
3946
3947 struct ephy_info {
3948         unsigned int offset;
3949         u16 mask;
3950         u16 bits;
3951 };
3952
3953 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3954 {
3955         u16 w;
3956
3957         while (len-- > 0) {
3958                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3959                 rtl_ephy_write(ioaddr, e->offset, w);
3960                 e++;
3961         }
3962 }
3963
3964 static void rtl_disable_clock_request(struct pci_dev *pdev)
3965 {
3966         int cap = pci_pcie_cap(pdev);
3967
3968         if (cap) {
3969                 u16 ctl;
3970
3971                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3972                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3973                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3974         }
3975 }
3976
3977 static void rtl_enable_clock_request(struct pci_dev *pdev)
3978 {
3979         int cap = pci_pcie_cap(pdev);
3980
3981         if (cap) {
3982                 u16 ctl;
3983
3984                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3985                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3986                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3987         }
3988 }
3989
3990 #define R8168_CPCMD_QUIRK_MASK (\
3991         EnableBist | \
3992         Mac_dbgo_oe | \
3993         Force_half_dup | \
3994         Force_rxflow_en | \
3995         Force_txflow_en | \
3996         Cxpl_dbg_sel | \
3997         ASF | \
3998         PktCntrDisable | \
3999         Mac_dbgo_sel)
4000
4001 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4002 {
4003         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4004
4005         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4006
4007         rtl_tx_performance_tweak(pdev,
4008                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4009 }
4010
4011 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4012 {
4013         rtl_hw_start_8168bb(ioaddr, pdev);
4014
4015         RTL_W8(MaxTxPacketSize, TxPacketMax);
4016
4017         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4018 }
4019
4020 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4021 {
4022         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4023
4024         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4025
4026         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4027
4028         rtl_disable_clock_request(pdev);
4029
4030         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4031 }
4032
4033 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4034 {
4035         static const struct ephy_info e_info_8168cp[] = {
4036                 { 0x01, 0,      0x0001 },
4037                 { 0x02, 0x0800, 0x1000 },
4038                 { 0x03, 0,      0x0042 },
4039                 { 0x06, 0x0080, 0x0000 },
4040                 { 0x07, 0,      0x2000 }
4041         };
4042
4043         rtl_csi_access_enable_2(ioaddr);
4044
4045         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4046
4047         __rtl_hw_start_8168cp(ioaddr, pdev);
4048 }
4049
4050 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4051 {
4052         rtl_csi_access_enable_2(ioaddr);
4053
4054         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4055
4056         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4057
4058         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4059 }
4060
4061 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4062 {
4063         rtl_csi_access_enable_2(ioaddr);
4064
4065         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4066
4067         /* Magic. */
4068         RTL_W8(DBG_REG, 0x20);
4069
4070         RTL_W8(MaxTxPacketSize, TxPacketMax);
4071
4072         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4073
4074         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4075 }
4076
4077 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4078 {
4079         static const struct ephy_info e_info_8168c_1[] = {
4080                 { 0x02, 0x0800, 0x1000 },
4081                 { 0x03, 0,      0x0002 },
4082                 { 0x06, 0x0080, 0x0000 }
4083         };
4084
4085         rtl_csi_access_enable_2(ioaddr);
4086
4087         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4088
4089         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4090
4091         __rtl_hw_start_8168cp(ioaddr, pdev);
4092 }
4093
4094 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4095 {
4096         static const struct ephy_info e_info_8168c_2[] = {
4097                 { 0x01, 0,      0x0001 },
4098                 { 0x03, 0x0400, 0x0220 }
4099         };
4100
4101         rtl_csi_access_enable_2(ioaddr);
4102
4103         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4104
4105         __rtl_hw_start_8168cp(ioaddr, pdev);
4106 }
4107
4108 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4109 {
4110         rtl_hw_start_8168c_2(ioaddr, pdev);
4111 }
4112
4113 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4114 {
4115         rtl_csi_access_enable_2(ioaddr);
4116
4117         __rtl_hw_start_8168cp(ioaddr, pdev);
4118 }
4119
4120 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4121 {
4122         rtl_csi_access_enable_2(ioaddr);
4123
4124         rtl_disable_clock_request(pdev);
4125
4126         RTL_W8(MaxTxPacketSize, TxPacketMax);
4127
4128         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4129
4130         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4131 }
4132
4133 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4134 {
4135         rtl_csi_access_enable_1(ioaddr);
4136
4137         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4138
4139         RTL_W8(MaxTxPacketSize, TxPacketMax);
4140
4141         rtl_disable_clock_request(pdev);
4142 }
4143
4144 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4145 {
4146         static const struct ephy_info e_info_8168d_4[] = {
4147                 { 0x0b, ~0,     0x48 },
4148                 { 0x19, 0x20,   0x50 },
4149                 { 0x0c, ~0,     0x20 }
4150         };
4151         int i;
4152
4153         rtl_csi_access_enable_1(ioaddr);
4154
4155         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4156
4157         RTL_W8(MaxTxPacketSize, TxPacketMax);
4158
4159         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4160                 const struct ephy_info *e = e_info_8168d_4 + i;
4161                 u16 w;
4162
4163                 w = rtl_ephy_read(ioaddr, e->offset);
4164                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4165         }
4166
4167         rtl_enable_clock_request(pdev);
4168 }
4169
4170 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4171 {
4172         static const struct ephy_info e_info_8168e[] = {
4173                 { 0x00, 0x0200, 0x0100 },
4174                 { 0x00, 0x0000, 0x0004 },
4175                 { 0x06, 0x0002, 0x0001 },
4176                 { 0x06, 0x0000, 0x0030 },
4177                 { 0x07, 0x0000, 0x2000 },
4178                 { 0x00, 0x0000, 0x0020 },
4179                 { 0x03, 0x5800, 0x2000 },
4180                 { 0x03, 0x0000, 0x0001 },
4181                 { 0x01, 0x0800, 0x1000 },
4182                 { 0x07, 0x0000, 0x4000 },
4183                 { 0x1e, 0x0000, 0x2000 },
4184                 { 0x19, 0xffff, 0xfe6c },
4185                 { 0x0a, 0x0000, 0x0040 }
4186         };
4187
4188         rtl_csi_access_enable_2(ioaddr);
4189
4190         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4191
4192         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4193
4194         RTL_W8(MaxTxPacketSize, TxPacketMax);
4195
4196         rtl_disable_clock_request(pdev);
4197
4198         /* Reset tx FIFO pointer */
4199         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4200         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4201
4202         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4203 }
4204
4205 static void rtl_hw_start_8168(struct net_device *dev)
4206 {
4207         struct rtl8169_private *tp = netdev_priv(dev);
4208         void __iomem *ioaddr = tp->mmio_addr;
4209         struct pci_dev *pdev = tp->pci_dev;
4210
4211         RTL_W8(Cfg9346, Cfg9346_Unlock);
4212
4213         RTL_W8(MaxTxPacketSize, TxPacketMax);
4214
4215         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4216
4217         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4218
4219         RTL_W16(CPlusCmd, tp->cp_cmd);
4220
4221         RTL_W16(IntrMitigate, 0x5151);
4222
4223         /* Work around for RxFIFO overflow. */
4224         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4225             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4226                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4227                 tp->intr_event &= ~RxOverflow;
4228         }
4229
4230         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4231
4232         rtl_set_rx_mode(dev);
4233
4234         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4235                 (InterFrameGap << TxInterFrameGapShift));
4236
4237         RTL_R8(IntrMask);
4238
4239         switch (tp->mac_version) {
4240         case RTL_GIGA_MAC_VER_11:
4241                 rtl_hw_start_8168bb(ioaddr, pdev);
4242                 break;
4243
4244         case RTL_GIGA_MAC_VER_12:
4245         case RTL_GIGA_MAC_VER_17:
4246                 rtl_hw_start_8168bef(ioaddr, pdev);
4247                 break;
4248
4249         case RTL_GIGA_MAC_VER_18:
4250                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4251                 break;
4252
4253         case RTL_GIGA_MAC_VER_19:
4254                 rtl_hw_start_8168c_1(ioaddr, pdev);
4255                 break;
4256
4257         case RTL_GIGA_MAC_VER_20:
4258                 rtl_hw_start_8168c_2(ioaddr, pdev);
4259                 break;
4260
4261         case RTL_GIGA_MAC_VER_21:
4262                 rtl_hw_start_8168c_3(ioaddr, pdev);
4263                 break;
4264
4265         case RTL_GIGA_MAC_VER_22:
4266                 rtl_hw_start_8168c_4(ioaddr, pdev);
4267                 break;
4268
4269         case RTL_GIGA_MAC_VER_23:
4270                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4271                 break;
4272
4273         case RTL_GIGA_MAC_VER_24:
4274                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4275                 break;
4276
4277         case RTL_GIGA_MAC_VER_25:
4278         case RTL_GIGA_MAC_VER_26:
4279         case RTL_GIGA_MAC_VER_27:
4280                 rtl_hw_start_8168d(ioaddr, pdev);
4281                 break;
4282
4283         case RTL_GIGA_MAC_VER_28:
4284                 rtl_hw_start_8168d_4(ioaddr, pdev);
4285                 break;
4286
4287         case RTL_GIGA_MAC_VER_31:
4288                 rtl_hw_start_8168dp(ioaddr, pdev);
4289                 break;
4290
4291         case RTL_GIGA_MAC_VER_32:
4292         case RTL_GIGA_MAC_VER_33:
4293                 rtl_hw_start_8168e(ioaddr, pdev);
4294                 break;
4295
4296         default:
4297                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4298                         dev->name, tp->mac_version);
4299                 break;
4300         }
4301
4302         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4303
4304         RTL_W8(Cfg9346, Cfg9346_Lock);
4305
4306         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4307
4308         RTL_W16(IntrMask, tp->intr_event);
4309 }
4310
4311 #define R810X_CPCMD_QUIRK_MASK (\
4312         EnableBist | \
4313         Mac_dbgo_oe | \
4314         Force_half_dup | \
4315         Force_rxflow_en | \
4316         Force_txflow_en | \
4317         Cxpl_dbg_sel | \
4318         ASF | \
4319         PktCntrDisable | \
4320         Mac_dbgo_sel)
4321
4322 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4323 {
4324         static const struct ephy_info e_info_8102e_1[] = {
4325                 { 0x01, 0, 0x6e65 },
4326                 { 0x02, 0, 0x091f },
4327                 { 0x03, 0, 0xc2f9 },
4328                 { 0x06, 0, 0xafb5 },
4329                 { 0x07, 0, 0x0e00 },
4330                 { 0x19, 0, 0xec80 },
4331                 { 0x01, 0, 0x2e65 },
4332                 { 0x01, 0, 0x6e65 }
4333         };
4334         u8 cfg1;
4335
4336         rtl_csi_access_enable_2(ioaddr);
4337
4338         RTL_W8(DBG_REG, FIX_NAK_1);
4339
4340         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4341
4342         RTL_W8(Config1,
4343                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4344         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4345
4346         cfg1 = RTL_R8(Config1);
4347         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4348                 RTL_W8(Config1, cfg1 & ~LEDS0);
4349
4350         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4351 }
4352
4353 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4354 {
4355         rtl_csi_access_enable_2(ioaddr);
4356
4357         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4358
4359         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4360         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4361 }
4362
4363 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4364 {
4365         rtl_hw_start_8102e_2(ioaddr, pdev);
4366
4367         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4368 }
4369
4370 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4371 {
4372         static const struct ephy_info e_info_8105e_1[] = {
4373                 { 0x07, 0, 0x4000 },
4374                 { 0x19, 0, 0x0200 },
4375                 { 0x19, 0, 0x0020 },
4376                 { 0x1e, 0, 0x2000 },
4377                 { 0x03, 0, 0x0001 },
4378                 { 0x19, 0, 0x0100 },
4379                 { 0x19, 0, 0x0004 },
4380                 { 0x0a, 0, 0x0020 }
4381         };
4382
4383         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4384         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4385
4386         /* Disable Early Tally Counter */
4387         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4388
4389         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4390         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4391
4392         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4393 }
4394
4395 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4396 {
4397         rtl_hw_start_8105e_1(ioaddr, pdev);
4398         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4399 }
4400
4401 static void rtl_hw_start_8101(struct net_device *dev)
4402 {
4403         struct rtl8169_private *tp = netdev_priv(dev);
4404         void __iomem *ioaddr = tp->mmio_addr;
4405         struct pci_dev *pdev = tp->pci_dev;
4406
4407         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4408             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4409                 int cap = pci_pcie_cap(pdev);
4410
4411                 if (cap) {
4412                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4413                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4414                 }
4415         }
4416
4417         RTL_W8(Cfg9346, Cfg9346_Unlock);
4418
4419         switch (tp->mac_version) {
4420         case RTL_GIGA_MAC_VER_07:
4421                 rtl_hw_start_8102e_1(ioaddr, pdev);
4422                 break;
4423
4424         case RTL_GIGA_MAC_VER_08:
4425                 rtl_hw_start_8102e_3(ioaddr, pdev);
4426                 break;
4427
4428         case RTL_GIGA_MAC_VER_09:
4429                 rtl_hw_start_8102e_2(ioaddr, pdev);
4430                 break;
4431
4432         case RTL_GIGA_MAC_VER_29:
4433                 rtl_hw_start_8105e_1(ioaddr, pdev);
4434                 break;
4435         case RTL_GIGA_MAC_VER_30:
4436                 rtl_hw_start_8105e_2(ioaddr, pdev);
4437                 break;
4438         }
4439
4440         RTL_W8(Cfg9346, Cfg9346_Lock);
4441
4442         RTL_W8(MaxTxPacketSize, TxPacketMax);
4443
4444         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4445
4446         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4447         RTL_W16(CPlusCmd, tp->cp_cmd);
4448
4449         RTL_W16(IntrMitigate, 0x0000);
4450
4451         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4452
4453         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4454         rtl_set_rx_tx_config_registers(tp);
4455
4456         RTL_R8(IntrMask);
4457
4458         rtl_set_rx_mode(dev);
4459
4460         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4461
4462         RTL_W16(IntrMask, tp->intr_event);
4463 }
4464
4465 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4466 {
4467         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4468                 return -EINVAL;
4469
4470         dev->mtu = new_mtu;
4471         netdev_update_features(dev);
4472
4473         return 0;
4474 }
4475
4476 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4477 {
4478         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4479         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4480 }
4481
4482 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4483                                      void **data_buff, struct RxDesc *desc)
4484 {
4485         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4486                          DMA_FROM_DEVICE);
4487
4488         kfree(*data_buff);
4489         *data_buff = NULL;
4490         rtl8169_make_unusable_by_asic(desc);
4491 }
4492
4493 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4494 {
4495         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4496
4497         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4498 }
4499
4500 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4501                                        u32 rx_buf_sz)
4502 {
4503         desc->addr = cpu_to_le64(mapping);
4504         wmb();
4505         rtl8169_mark_to_asic(desc, rx_buf_sz);
4506 }
4507
4508 static inline void *rtl8169_align(void *data)
4509 {
4510         return (void *)ALIGN((long)data, 16);
4511 }
4512
4513 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4514                                              struct RxDesc *desc)
4515 {
4516         void *data;
4517         dma_addr_t mapping;
4518         struct device *d = &tp->pci_dev->dev;
4519         struct net_device *dev = tp->dev;
4520         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4521
4522         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4523         if (!data)
4524                 return NULL;
4525
4526         if (rtl8169_align(data) != data) {
4527                 kfree(data);
4528                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4529                 if (!data)
4530                         return NULL;
4531         }
4532
4533         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4534                                  DMA_FROM_DEVICE);
4535         if (unlikely(dma_mapping_error(d, mapping))) {
4536                 if (net_ratelimit())
4537                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4538                 goto err_out;
4539         }
4540
4541         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4542         return data;
4543
4544 err_out:
4545         kfree(data);
4546         return NULL;
4547 }
4548
4549 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4550 {
4551         unsigned int i;
4552
4553         for (i = 0; i < NUM_RX_DESC; i++) {
4554                 if (tp->Rx_databuff[i]) {
4555                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4556                                             tp->RxDescArray + i);
4557                 }
4558         }
4559 }
4560
4561 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4562 {
4563         desc->opts1 |= cpu_to_le32(RingEnd);
4564 }
4565
4566 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4567 {
4568         unsigned int i;
4569
4570         for (i = 0; i < NUM_RX_DESC; i++) {
4571                 void *data;
4572
4573                 if (tp->Rx_databuff[i])
4574                         continue;
4575
4576                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4577                 if (!data) {
4578                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4579                         goto err_out;
4580                 }
4581                 tp->Rx_databuff[i] = data;
4582         }
4583
4584         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4585         return 0;
4586
4587 err_out:
4588         rtl8169_rx_clear(tp);
4589         return -ENOMEM;
4590 }
4591
4592 static int rtl8169_init_ring(struct net_device *dev)
4593 {
4594         struct rtl8169_private *tp = netdev_priv(dev);
4595
4596         rtl8169_init_ring_indexes(tp);
4597
4598         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4599         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4600
4601         return rtl8169_rx_fill(tp);
4602 }
4603
4604 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4605                                  struct TxDesc *desc)
4606 {
4607         unsigned int len = tx_skb->len;
4608
4609         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4610
4611         desc->opts1 = 0x00;
4612         desc->opts2 = 0x00;
4613         desc->addr = 0x00;
4614         tx_skb->len = 0;
4615 }
4616
4617 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4618                                    unsigned int n)
4619 {
4620         unsigned int i;
4621
4622         for (i = 0; i < n; i++) {
4623                 unsigned int entry = (start + i) % NUM_TX_DESC;
4624                 struct ring_info *tx_skb = tp->tx_skb + entry;
4625                 unsigned int len = tx_skb->len;
4626
4627                 if (len) {
4628                         struct sk_buff *skb = tx_skb->skb;
4629
4630                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4631                                              tp->TxDescArray + entry);
4632                         if (skb) {
4633                                 tp->dev->stats.tx_dropped++;
4634                                 dev_kfree_skb(skb);
4635                                 tx_skb->skb = NULL;
4636                         }
4637                 }
4638         }
4639 }
4640
4641 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4642 {
4643         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4644         tp->cur_tx = tp->dirty_tx = 0;
4645 }
4646
4647 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4648 {
4649         struct rtl8169_private *tp = netdev_priv(dev);
4650
4651         PREPARE_DELAYED_WORK(&tp->task, task);
4652         schedule_delayed_work(&tp->task, 4);
4653 }
4654
4655 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4656 {
4657         struct rtl8169_private *tp = netdev_priv(dev);
4658         void __iomem *ioaddr = tp->mmio_addr;
4659
4660         synchronize_irq(dev->irq);
4661
4662         /* Wait for any pending NAPI task to complete */
4663         napi_disable(&tp->napi);
4664
4665         rtl8169_irq_mask_and_ack(ioaddr);
4666
4667         tp->intr_mask = 0xffff;
4668         RTL_W16(IntrMask, tp->intr_event);
4669         napi_enable(&tp->napi);
4670 }
4671
4672 static void rtl8169_reinit_task(struct work_struct *work)
4673 {
4674         struct rtl8169_private *tp =
4675                 container_of(work, struct rtl8169_private, task.work);
4676         struct net_device *dev = tp->dev;
4677         int ret;
4678
4679         rtnl_lock();
4680
4681         if (!netif_running(dev))
4682                 goto out_unlock;
4683
4684         rtl8169_wait_for_quiescence(dev);
4685         rtl8169_close(dev);
4686
4687         ret = rtl8169_open(dev);
4688         if (unlikely(ret < 0)) {
4689                 if (net_ratelimit())
4690                         netif_err(tp, drv, dev,
4691                                   "reinit failure (status = %d). Rescheduling\n",
4692                                   ret);
4693                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4694         }
4695
4696 out_unlock:
4697         rtnl_unlock();
4698 }
4699
4700 static void rtl8169_reset_task(struct work_struct *work)
4701 {
4702         struct rtl8169_private *tp =
4703                 container_of(work, struct rtl8169_private, task.work);
4704         struct net_device *dev = tp->dev;
4705         int i;
4706
4707         rtnl_lock();
4708
4709         if (!netif_running(dev))
4710                 goto out_unlock;
4711
4712         rtl8169_wait_for_quiescence(dev);
4713
4714         for (i = 0; i < NUM_RX_DESC; i++)
4715                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4716
4717         rtl8169_tx_clear(tp);
4718
4719         rtl8169_hw_reset(tp);
4720         rtl_hw_start(dev);
4721         netif_wake_queue(dev);
4722         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4723
4724 out_unlock:
4725         rtnl_unlock();
4726 }
4727
4728 static void rtl8169_tx_timeout(struct net_device *dev)
4729 {
4730         struct rtl8169_private *tp = netdev_priv(dev);
4731
4732         rtl8169_hw_reset(tp);
4733
4734         /* Let's wait a bit while any (async) irq lands on */
4735         rtl8169_schedule_work(dev, rtl8169_reset_task);
4736 }
4737
4738 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4739                               u32 *opts)
4740 {
4741         struct skb_shared_info *info = skb_shinfo(skb);
4742         unsigned int cur_frag, entry;
4743         struct TxDesc * uninitialized_var(txd);
4744         struct device *d = &tp->pci_dev->dev;
4745
4746         entry = tp->cur_tx;
4747         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4748                 skb_frag_t *frag = info->frags + cur_frag;
4749                 dma_addr_t mapping;
4750                 u32 status, len;
4751                 void *addr;
4752
4753                 entry = (entry + 1) % NUM_TX_DESC;
4754
4755                 txd = tp->TxDescArray + entry;
4756                 len = frag->size;
4757                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4758                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4759                 if (unlikely(dma_mapping_error(d, mapping))) {
4760                         if (net_ratelimit())
4761                                 netif_err(tp, drv, tp->dev,
4762                                           "Failed to map TX fragments DMA!\n");
4763                         goto err_out;
4764                 }
4765
4766                 /* Anti gcc 2.95.3 bugware (sic) */
4767                 status = opts[0] | len |
4768                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4769
4770                 txd->opts1 = cpu_to_le32(status);
4771                 txd->opts2 = cpu_to_le32(opts[1]);
4772                 txd->addr = cpu_to_le64(mapping);
4773
4774                 tp->tx_skb[entry].len = len;
4775         }
4776
4777         if (cur_frag) {
4778                 tp->tx_skb[entry].skb = skb;
4779                 txd->opts1 |= cpu_to_le32(LastFrag);
4780         }
4781
4782         return cur_frag;
4783
4784 err_out:
4785         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4786         return -EIO;
4787 }
4788
4789 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4790                                     struct sk_buff *skb, u32 *opts)
4791 {
4792         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4793         u32 mss = skb_shinfo(skb)->gso_size;
4794         int offset = info->opts_offset;
4795
4796         if (mss) {
4797                 opts[0] |= TD_LSO;
4798                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4799         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4800                 const struct iphdr *ip = ip_hdr(skb);
4801
4802                 if (ip->protocol == IPPROTO_TCP)
4803                         opts[offset] |= info->checksum.tcp;
4804                 else if (ip->protocol == IPPROTO_UDP)
4805                         opts[offset] |= info->checksum.udp;
4806                 else
4807                         WARN_ON_ONCE(1);
4808         }
4809 }
4810
4811 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4812                                       struct net_device *dev)
4813 {
4814         struct rtl8169_private *tp = netdev_priv(dev);
4815         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4816         struct TxDesc *txd = tp->TxDescArray + entry;
4817         void __iomem *ioaddr = tp->mmio_addr;
4818         struct device *d = &tp->pci_dev->dev;
4819         dma_addr_t mapping;
4820         u32 status, len;
4821         u32 opts[2];
4822         int frags;
4823
4824         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4825                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4826                 goto err_stop_0;
4827         }
4828
4829         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4830                 goto err_stop_0;
4831
4832         len = skb_headlen(skb);
4833         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4834         if (unlikely(dma_mapping_error(d, mapping))) {
4835                 if (net_ratelimit())
4836                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4837                 goto err_dma_0;
4838         }
4839
4840         tp->tx_skb[entry].len = len;
4841         txd->addr = cpu_to_le64(mapping);
4842
4843         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4844         opts[0] = DescOwn;
4845
4846         rtl8169_tso_csum(tp, skb, opts);
4847
4848         frags = rtl8169_xmit_frags(tp, skb, opts);
4849         if (frags < 0)
4850                 goto err_dma_1;
4851         else if (frags)
4852                 opts[0] |= FirstFrag;
4853         else {
4854                 opts[0] |= FirstFrag | LastFrag;
4855                 tp->tx_skb[entry].skb = skb;
4856         }
4857
4858         txd->opts2 = cpu_to_le32(opts[1]);
4859
4860         wmb();
4861
4862         /* Anti gcc 2.95.3 bugware (sic) */
4863         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4864         txd->opts1 = cpu_to_le32(status);
4865
4866         tp->cur_tx += frags + 1;
4867
4868         wmb();
4869
4870         RTL_W8(TxPoll, NPQ);
4871
4872         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4873                 netif_stop_queue(dev);
4874                 smp_rmb();
4875                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4876                         netif_wake_queue(dev);
4877         }
4878
4879         return NETDEV_TX_OK;
4880
4881 err_dma_1:
4882         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4883 err_dma_0:
4884         dev_kfree_skb(skb);
4885         dev->stats.tx_dropped++;
4886         return NETDEV_TX_OK;
4887
4888 err_stop_0:
4889         netif_stop_queue(dev);
4890         dev->stats.tx_dropped++;
4891         return NETDEV_TX_BUSY;
4892 }
4893
4894 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4895 {
4896         struct rtl8169_private *tp = netdev_priv(dev);
4897         struct pci_dev *pdev = tp->pci_dev;
4898         u16 pci_status, pci_cmd;
4899
4900         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4901         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4902
4903         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4904                   pci_cmd, pci_status);
4905
4906         /*
4907          * The recovery sequence below admits a very elaborated explanation:
4908          * - it seems to work;
4909          * - I did not see what else could be done;
4910          * - it makes iop3xx happy.
4911          *
4912          * Feel free to adjust to your needs.
4913          */
4914         if (pdev->broken_parity_status)
4915                 pci_cmd &= ~PCI_COMMAND_PARITY;
4916         else
4917                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4918
4919         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4920
4921         pci_write_config_word(pdev, PCI_STATUS,
4922                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4923                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4924                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4925
4926         /* The infamous DAC f*ckup only happens at boot time */
4927         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4928                 void __iomem *ioaddr = tp->mmio_addr;
4929
4930                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4931                 tp->cp_cmd &= ~PCIDAC;
4932                 RTL_W16(CPlusCmd, tp->cp_cmd);
4933                 dev->features &= ~NETIF_F_HIGHDMA;
4934         }
4935
4936         rtl8169_hw_reset(tp);
4937
4938         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4939 }
4940
4941 static void rtl8169_tx_interrupt(struct net_device *dev,
4942                                  struct rtl8169_private *tp,
4943                                  void __iomem *ioaddr)
4944 {
4945         unsigned int dirty_tx, tx_left;
4946
4947         dirty_tx = tp->dirty_tx;
4948         smp_rmb();
4949         tx_left = tp->cur_tx - dirty_tx;
4950
4951         while (tx_left > 0) {
4952                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4953                 struct ring_info *tx_skb = tp->tx_skb + entry;
4954                 u32 status;
4955
4956                 rmb();
4957                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4958                 if (status & DescOwn)
4959                         break;
4960
4961                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4962                                      tp->TxDescArray + entry);
4963                 if (status & LastFrag) {
4964                         dev->stats.tx_packets++;
4965                         dev->stats.tx_bytes += tx_skb->skb->len;
4966                         dev_kfree_skb(tx_skb->skb);
4967                         tx_skb->skb = NULL;
4968                 }
4969                 dirty_tx++;
4970                 tx_left--;
4971         }
4972
4973         if (tp->dirty_tx != dirty_tx) {
4974                 tp->dirty_tx = dirty_tx;
4975                 smp_wmb();
4976                 if (netif_queue_stopped(dev) &&
4977                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4978                         netif_wake_queue(dev);
4979                 }
4980                 /*
4981                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4982                  * too close. Let's kick an extra TxPoll request when a burst
4983                  * of start_xmit activity is detected (if it is not detected,
4984                  * it is slow enough). -- FR
4985                  */
4986                 smp_rmb();
4987                 if (tp->cur_tx != dirty_tx)
4988                         RTL_W8(TxPoll, NPQ);
4989         }
4990 }
4991
4992 static inline int rtl8169_fragmented_frame(u32 status)
4993 {
4994         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4995 }
4996
4997 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4998 {
4999         u32 status = opts1 & RxProtoMask;
5000
5001         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5002             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5003                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5004         else
5005                 skb_checksum_none_assert(skb);
5006 }
5007
5008 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5009                                            struct rtl8169_private *tp,
5010                                            int pkt_size,
5011                                            dma_addr_t addr)
5012 {
5013         struct sk_buff *skb;
5014         struct device *d = &tp->pci_dev->dev;
5015
5016         data = rtl8169_align(data);
5017         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5018         prefetch(data);
5019         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5020         if (skb)
5021                 memcpy(skb->data, data, pkt_size);
5022         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5023
5024         return skb;
5025 }
5026
5027 static int rtl8169_rx_interrupt(struct net_device *dev,
5028                                 struct rtl8169_private *tp,
5029                                 void __iomem *ioaddr, u32 budget)
5030 {
5031         unsigned int cur_rx, rx_left;
5032         unsigned int count;
5033
5034         cur_rx = tp->cur_rx;
5035         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5036         rx_left = min(rx_left, budget);
5037
5038         for (; rx_left > 0; rx_left--, cur_rx++) {
5039                 unsigned int entry = cur_rx % NUM_RX_DESC;
5040                 struct RxDesc *desc = tp->RxDescArray + entry;
5041                 u32 status;
5042
5043                 rmb();
5044                 status = le32_to_cpu(desc->opts1);
5045
5046                 if (status & DescOwn)
5047                         break;
5048                 if (unlikely(status & RxRES)) {
5049                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5050                                    status);
5051                         dev->stats.rx_errors++;
5052                         if (status & (RxRWT | RxRUNT))
5053                                 dev->stats.rx_length_errors++;
5054                         if (status & RxCRC)
5055                                 dev->stats.rx_crc_errors++;
5056                         if (status & RxFOVF) {
5057                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5058                                 dev->stats.rx_fifo_errors++;
5059                         }
5060                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5061                 } else {
5062                         struct sk_buff *skb;
5063                         dma_addr_t addr = le64_to_cpu(desc->addr);
5064                         int pkt_size = (status & 0x00001FFF) - 4;
5065
5066                         /*
5067                          * The driver does not support incoming fragmented
5068                          * frames. They are seen as a symptom of over-mtu
5069                          * sized frames.
5070                          */
5071                         if (unlikely(rtl8169_fragmented_frame(status))) {
5072                                 dev->stats.rx_dropped++;
5073                                 dev->stats.rx_length_errors++;
5074                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5075                                 continue;
5076                         }
5077
5078                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5079                                                   tp, pkt_size, addr);
5080                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5081                         if (!skb) {
5082                                 dev->stats.rx_dropped++;
5083                                 continue;
5084                         }
5085
5086                         rtl8169_rx_csum(skb, status);
5087                         skb_put(skb, pkt_size);
5088                         skb->protocol = eth_type_trans(skb, dev);
5089
5090                         rtl8169_rx_vlan_tag(desc, skb);
5091
5092                         napi_gro_receive(&tp->napi, skb);
5093
5094                         dev->stats.rx_bytes += pkt_size;
5095                         dev->stats.rx_packets++;
5096                 }
5097
5098                 /* Work around for AMD plateform. */
5099                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5100                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5101                         desc->opts2 = 0;
5102                         cur_rx++;
5103                 }
5104         }
5105
5106         count = cur_rx - tp->cur_rx;
5107         tp->cur_rx = cur_rx;
5108
5109         tp->dirty_rx += count;
5110
5111         return count;
5112 }
5113
5114 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5115 {
5116         struct net_device *dev = dev_instance;
5117         struct rtl8169_private *tp = netdev_priv(dev);
5118         void __iomem *ioaddr = tp->mmio_addr;
5119         int handled = 0;
5120         int status;
5121
5122         /* loop handling interrupts until we have no new ones or
5123          * we hit a invalid/hotplug case.
5124          */
5125         status = RTL_R16(IntrStatus);
5126         while (status && status != 0xffff) {
5127                 handled = 1;
5128
5129                 /* Handle all of the error cases first. These will reset
5130                  * the chip, so just exit the loop.
5131                  */
5132                 if (unlikely(!netif_running(dev))) {
5133                         rtl8169_hw_reset(tp);
5134                         break;
5135                 }
5136
5137                 if (unlikely(status & RxFIFOOver)) {
5138                         switch (tp->mac_version) {
5139                         /* Work around for rx fifo overflow */
5140                         case RTL_GIGA_MAC_VER_11:
5141                         case RTL_GIGA_MAC_VER_22:
5142                         case RTL_GIGA_MAC_VER_26:
5143                                 netif_stop_queue(dev);
5144                                 rtl8169_tx_timeout(dev);
5145                                 goto done;
5146                         /* Testers needed. */
5147                         case RTL_GIGA_MAC_VER_17:
5148                         case RTL_GIGA_MAC_VER_19:
5149                         case RTL_GIGA_MAC_VER_20:
5150                         case RTL_GIGA_MAC_VER_21:
5151                         case RTL_GIGA_MAC_VER_23:
5152                         case RTL_GIGA_MAC_VER_24:
5153                         case RTL_GIGA_MAC_VER_27:
5154                         case RTL_GIGA_MAC_VER_28:
5155                         case RTL_GIGA_MAC_VER_31:
5156                         /* Experimental science. Pktgen proof. */
5157                         case RTL_GIGA_MAC_VER_12:
5158                         case RTL_GIGA_MAC_VER_25:
5159                                 if (status == RxFIFOOver)
5160                                         goto done;
5161                                 break;
5162                         default:
5163                                 break;
5164                         }
5165                 }
5166
5167                 if (unlikely(status & SYSErr)) {
5168                         rtl8169_pcierr_interrupt(dev);
5169                         break;
5170                 }
5171
5172                 if (status & LinkChg)
5173                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5174
5175                 /* We need to see the lastest version of tp->intr_mask to
5176                  * avoid ignoring an MSI interrupt and having to wait for
5177                  * another event which may never come.
5178                  */
5179                 smp_rmb();
5180                 if (status & tp->intr_mask & tp->napi_event) {
5181                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5182                         tp->intr_mask = ~tp->napi_event;
5183
5184                         if (likely(napi_schedule_prep(&tp->napi)))
5185                                 __napi_schedule(&tp->napi);
5186                         else
5187                                 netif_info(tp, intr, dev,
5188                                            "interrupt %04x in poll\n", status);
5189                 }
5190
5191                 /* We only get a new MSI interrupt when all active irq
5192                  * sources on the chip have been acknowledged. So, ack
5193                  * everything we've seen and check if new sources have become
5194                  * active to avoid blocking all interrupts from the chip.
5195                  */
5196                 RTL_W16(IntrStatus,
5197                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5198                 status = RTL_R16(IntrStatus);
5199         }
5200 done:
5201         return IRQ_RETVAL(handled);
5202 }
5203
5204 static int rtl8169_poll(struct napi_struct *napi, int budget)
5205 {
5206         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5207         struct net_device *dev = tp->dev;
5208         void __iomem *ioaddr = tp->mmio_addr;
5209         int work_done;
5210
5211         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5212         rtl8169_tx_interrupt(dev, tp, ioaddr);
5213
5214         if (work_done < budget) {
5215                 napi_complete(napi);
5216
5217                 /* We need for force the visibility of tp->intr_mask
5218                  * for other CPUs, as we can loose an MSI interrupt
5219                  * and potentially wait for a retransmit timeout if we don't.
5220                  * The posted write to IntrMask is safe, as it will
5221                  * eventually make it to the chip and we won't loose anything
5222                  * until it does.
5223                  */
5224                 tp->intr_mask = 0xffff;
5225                 wmb();
5226                 RTL_W16(IntrMask, tp->intr_event);
5227         }
5228
5229         return work_done;
5230 }
5231
5232 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5233 {
5234         struct rtl8169_private *tp = netdev_priv(dev);
5235
5236         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5237                 return;
5238
5239         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5240         RTL_W32(RxMissed, 0);
5241 }
5242
5243 static void rtl8169_down(struct net_device *dev)
5244 {
5245         struct rtl8169_private *tp = netdev_priv(dev);
5246         void __iomem *ioaddr = tp->mmio_addr;
5247
5248         del_timer_sync(&tp->timer);
5249
5250         netif_stop_queue(dev);
5251
5252         napi_disable(&tp->napi);
5253
5254         spin_lock_irq(&tp->lock);
5255
5256         rtl8169_hw_reset(tp);
5257         /*
5258          * At this point device interrupts can not be enabled in any function,
5259          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5260          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5261          */
5262         rtl8169_rx_missed(dev, ioaddr);
5263
5264         spin_unlock_irq(&tp->lock);
5265
5266         synchronize_irq(dev->irq);
5267
5268         /* Give a racing hard_start_xmit a few cycles to complete. */
5269         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5270
5271         rtl8169_tx_clear(tp);
5272
5273         rtl8169_rx_clear(tp);
5274
5275         rtl_pll_power_down(tp);
5276 }
5277
5278 static int rtl8169_close(struct net_device *dev)
5279 {
5280         struct rtl8169_private *tp = netdev_priv(dev);
5281         struct pci_dev *pdev = tp->pci_dev;
5282
5283         pm_runtime_get_sync(&pdev->dev);
5284
5285         /* Update counters before going down */
5286         rtl8169_update_counters(dev);
5287
5288         rtl8169_down(dev);
5289
5290         free_irq(dev->irq, dev);
5291
5292         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5293                           tp->RxPhyAddr);
5294         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5295                           tp->TxPhyAddr);
5296         tp->TxDescArray = NULL;
5297         tp->RxDescArray = NULL;
5298
5299         pm_runtime_put_sync(&pdev->dev);
5300
5301         return 0;
5302 }
5303
5304 static void rtl_set_rx_mode(struct net_device *dev)
5305 {
5306         struct rtl8169_private *tp = netdev_priv(dev);
5307         void __iomem *ioaddr = tp->mmio_addr;
5308         unsigned long flags;
5309         u32 mc_filter[2];       /* Multicast hash filter */
5310         int rx_mode;
5311         u32 tmp = 0;
5312
5313         if (dev->flags & IFF_PROMISC) {
5314                 /* Unconditionally log net taps. */
5315                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5316                 rx_mode =
5317                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5318                     AcceptAllPhys;
5319                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5320         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5321                    (dev->flags & IFF_ALLMULTI)) {
5322                 /* Too many to filter perfectly -- accept all multicasts. */
5323                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5324                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5325         } else {
5326                 struct netdev_hw_addr *ha;
5327
5328                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5329                 mc_filter[1] = mc_filter[0] = 0;
5330                 netdev_for_each_mc_addr(ha, dev) {
5331                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5332                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5333                         rx_mode |= AcceptMulticast;
5334                 }
5335         }
5336
5337         spin_lock_irqsave(&tp->lock, flags);
5338
5339         tmp = rtl8169_rx_config | rx_mode |
5340               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5341
5342         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5343                 u32 data = mc_filter[0];
5344
5345                 mc_filter[0] = swab32(mc_filter[1]);
5346                 mc_filter[1] = swab32(data);
5347         }
5348
5349         RTL_W32(MAR0 + 4, mc_filter[1]);
5350         RTL_W32(MAR0 + 0, mc_filter[0]);
5351
5352         RTL_W32(RxConfig, tmp);
5353
5354         spin_unlock_irqrestore(&tp->lock, flags);
5355 }
5356
5357 /**
5358  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5359  *  @dev: The Ethernet Device to get statistics for
5360  *
5361  *  Get TX/RX statistics for rtl8169
5362  */
5363 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5364 {
5365         struct rtl8169_private *tp = netdev_priv(dev);
5366         void __iomem *ioaddr = tp->mmio_addr;
5367         unsigned long flags;
5368
5369         if (netif_running(dev)) {
5370                 spin_lock_irqsave(&tp->lock, flags);
5371                 rtl8169_rx_missed(dev, ioaddr);
5372                 spin_unlock_irqrestore(&tp->lock, flags);
5373         }
5374
5375         return &dev->stats;
5376 }
5377
5378 static void rtl8169_net_suspend(struct net_device *dev)
5379 {
5380         struct rtl8169_private *tp = netdev_priv(dev);
5381
5382         if (!netif_running(dev))
5383                 return;
5384
5385         rtl_pll_power_down(tp);
5386
5387         netif_device_detach(dev);
5388         netif_stop_queue(dev);
5389 }
5390
5391 #ifdef CONFIG_PM
5392
5393 static int rtl8169_suspend(struct device *device)
5394 {
5395         struct pci_dev *pdev = to_pci_dev(device);
5396         struct net_device *dev = pci_get_drvdata(pdev);
5397
5398         rtl8169_net_suspend(dev);
5399
5400         return 0;
5401 }
5402
5403 static void __rtl8169_resume(struct net_device *dev)
5404 {
5405         struct rtl8169_private *tp = netdev_priv(dev);
5406
5407         netif_device_attach(dev);
5408
5409         rtl_pll_power_up(tp);
5410
5411         rtl8169_schedule_work(dev, rtl8169_reset_task);
5412 }
5413
5414 static int rtl8169_resume(struct device *device)
5415 {
5416         struct pci_dev *pdev = to_pci_dev(device);
5417         struct net_device *dev = pci_get_drvdata(pdev);
5418         struct rtl8169_private *tp = netdev_priv(dev);
5419
5420         rtl8169_init_phy(dev, tp);
5421
5422         if (netif_running(dev))
5423                 __rtl8169_resume(dev);
5424
5425         return 0;
5426 }
5427
5428 static int rtl8169_runtime_suspend(struct device *device)
5429 {
5430         struct pci_dev *pdev = to_pci_dev(device);
5431         struct net_device *dev = pci_get_drvdata(pdev);
5432         struct rtl8169_private *tp = netdev_priv(dev);
5433
5434         if (!tp->TxDescArray)
5435                 return 0;
5436
5437         spin_lock_irq(&tp->lock);
5438         tp->saved_wolopts = __rtl8169_get_wol(tp);
5439         __rtl8169_set_wol(tp, WAKE_ANY);
5440         spin_unlock_irq(&tp->lock);
5441
5442         rtl8169_net_suspend(dev);
5443
5444         return 0;
5445 }
5446
5447 static int rtl8169_runtime_resume(struct device *device)
5448 {
5449         struct pci_dev *pdev = to_pci_dev(device);
5450         struct net_device *dev = pci_get_drvdata(pdev);
5451         struct rtl8169_private *tp = netdev_priv(dev);
5452
5453         if (!tp->TxDescArray)
5454                 return 0;
5455
5456         spin_lock_irq(&tp->lock);
5457         __rtl8169_set_wol(tp, tp->saved_wolopts);
5458         tp->saved_wolopts = 0;
5459         spin_unlock_irq(&tp->lock);
5460
5461         rtl8169_init_phy(dev, tp);
5462
5463         __rtl8169_resume(dev);
5464
5465         return 0;
5466 }
5467
5468 static int rtl8169_runtime_idle(struct device *device)
5469 {
5470         struct pci_dev *pdev = to_pci_dev(device);
5471         struct net_device *dev = pci_get_drvdata(pdev);
5472         struct rtl8169_private *tp = netdev_priv(dev);
5473
5474         return tp->TxDescArray ? -EBUSY : 0;
5475 }
5476
5477 static const struct dev_pm_ops rtl8169_pm_ops = {
5478         .suspend                = rtl8169_suspend,
5479         .resume                 = rtl8169_resume,
5480         .freeze                 = rtl8169_suspend,
5481         .thaw                   = rtl8169_resume,
5482         .poweroff               = rtl8169_suspend,
5483         .restore                = rtl8169_resume,
5484         .runtime_suspend        = rtl8169_runtime_suspend,
5485         .runtime_resume         = rtl8169_runtime_resume,
5486         .runtime_idle           = rtl8169_runtime_idle,
5487 };
5488
5489 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5490
5491 #else /* !CONFIG_PM */
5492
5493 #define RTL8169_PM_OPS  NULL
5494
5495 #endif /* !CONFIG_PM */
5496
5497 static void rtl_shutdown(struct pci_dev *pdev)
5498 {
5499         struct net_device *dev = pci_get_drvdata(pdev);
5500         struct rtl8169_private *tp = netdev_priv(dev);
5501         void __iomem *ioaddr = tp->mmio_addr;
5502
5503         rtl8169_net_suspend(dev);
5504
5505         /* Restore original MAC address */
5506         rtl_rar_set(tp, dev->perm_addr);
5507
5508         spin_lock_irq(&tp->lock);
5509
5510         rtl8169_hw_reset(tp);
5511
5512         spin_unlock_irq(&tp->lock);
5513
5514         if (system_state == SYSTEM_POWER_OFF) {
5515                 /* WoL fails with some 8168 when the receiver is disabled. */
5516                 if (tp->features & RTL_FEATURE_WOL) {
5517                         pci_clear_master(pdev);
5518
5519                         RTL_W8(ChipCmd, CmdRxEnb);
5520                         /* PCI commit */
5521                         RTL_R8(ChipCmd);
5522                 }
5523
5524                 pci_wake_from_d3(pdev, true);
5525                 pci_set_power_state(pdev, PCI_D3hot);
5526         }
5527 }
5528
5529 static struct pci_driver rtl8169_pci_driver = {
5530         .name           = MODULENAME,
5531         .id_table       = rtl8169_pci_tbl,
5532         .probe          = rtl8169_init_one,
5533         .remove         = __devexit_p(rtl8169_remove_one),
5534         .shutdown       = rtl_shutdown,
5535         .driver.pm      = RTL8169_PM_OPS,
5536 };
5537
5538 static int __init rtl8169_init_module(void)
5539 {
5540         return pci_register_driver(&rtl8169_pci_driver);
5541 }
5542
5543 static void __exit rtl8169_cleanup_module(void)
5544 {
5545         pci_unregister_driver(&rtl8169_pci_driver);
5546 }
5547
5548 module_init(rtl8169_init_module);
5549 module_exit(rtl8169_cleanup_module);