drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  45
  46 #ifdef RTL8169_DEBUG
  47 #define assert(expr) \
  48         if (!(expr)) {                                  \
  49                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  50                 #expr,__FILE__,__func__,__LINE__);              \
  51         }
  52 #define dprintk(fmt, args...) \
  53         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  54 #else
  55 #define assert(expr) do {} while (0)
  56 #define dprintk(fmt, args...)   do {} while (0)
  57 #endif /* RTL8169_DEBUG */
  58
  59 #define R8169_MSG_DEFAULT \
  60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62 #define TX_BUFFS_AVAIL(tp) \
  63         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  64
  65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  66    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  67 static const int multicast_filter_limit = 32;
  68
  69 /* MAC address length */
  70 #define MAC_ADDR_LEN    6
  71
  72 #define MAX_READ_REQUEST_SHIFT  12
  73 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  74 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  75 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  76 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  77 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  78
  79 #define R8169_REGS_SIZE         256
  80 #define R8169_NAPI_WEIGHT       64
  81 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  82 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  83 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  84 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  85 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  86
  87 #define RTL8169_TX_TIMEOUT      (6*HZ)
  88 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  89
  90 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  91 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  92 #define RTL_EEPROM_SIG_ADDR     0x0000
  93
  94 /* write/read MMIO register */
  95 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  96 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  97 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  98 #define RTL_R8(reg)             readb (ioaddr + (reg))
  99 #define RTL_R16(reg)            readw (ioaddr + (reg))
 100 #define RTL_R32(reg)            readl (ioaddr + (reg))
 101
 102 enum mac_version {
 103         RTL_GIGA_MAC_VER_01 = 0,
 104         RTL_GIGA_MAC_VER_02,
 105         RTL_GIGA_MAC_VER_03,
 106         RTL_GIGA_MAC_VER_04,
 107         RTL_GIGA_MAC_VER_05,
 108         RTL_GIGA_MAC_VER_06,
 109         RTL_GIGA_MAC_VER_07,
 110         RTL_GIGA_MAC_VER_08,
 111         RTL_GIGA_MAC_VER_09,
 112         RTL_GIGA_MAC_VER_10,
 113         RTL_GIGA_MAC_VER_11,
 114         RTL_GIGA_MAC_VER_12,
 115         RTL_GIGA_MAC_VER_13,
 116         RTL_GIGA_MAC_VER_14,
 117         RTL_GIGA_MAC_VER_15,
 118         RTL_GIGA_MAC_VER_16,
 119         RTL_GIGA_MAC_VER_17,
 120         RTL_GIGA_MAC_VER_18,
 121         RTL_GIGA_MAC_VER_19,
 122         RTL_GIGA_MAC_VER_20,
 123         RTL_GIGA_MAC_VER_21,
 124         RTL_GIGA_MAC_VER_22,
 125         RTL_GIGA_MAC_VER_23,
 126         RTL_GIGA_MAC_VER_24,
 127         RTL_GIGA_MAC_VER_25,
 128         RTL_GIGA_MAC_VER_26,
 129         RTL_GIGA_MAC_VER_27,
 130         RTL_GIGA_MAC_VER_28,
 131         RTL_GIGA_MAC_VER_29,
 132         RTL_GIGA_MAC_VER_30,
 133         RTL_GIGA_MAC_VER_31,
 134         RTL_GIGA_MAC_VER_32,
 135         RTL_GIGA_MAC_VER_33,
 136         RTL_GIGA_MAC_NONE   = 0xff,
 137 };
 138
 139 enum rtl_tx_desc_version {
 140         RTL_TD_0        = 0,
 141         RTL_TD_1        = 1,
 142 };
 143
 144 #define _R(NAME,TD,FW) \
 145         { .name = NAME, .txd_version = TD, .fw_name = FW }
 146
 147 static const struct {
 148         const char *name;
 149         enum rtl_tx_desc_version txd_version;
 150         const char *fw_name;
 151 } rtl_chip_infos[] = {
 152         /* PCI devices. */
 153         [RTL_GIGA_MAC_VER_01] =
 154                 _R("RTL8169",           RTL_TD_0, NULL),
 155         [RTL_GIGA_MAC_VER_02] =
 156                 _R("RTL8169s",          RTL_TD_0, NULL),
 157         [RTL_GIGA_MAC_VER_03] =
 158                 _R("RTL8110s",          RTL_TD_0, NULL),
 159         [RTL_GIGA_MAC_VER_04] =
 160                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
 161         [RTL_GIGA_MAC_VER_05] =
 162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 163         [RTL_GIGA_MAC_VER_06] =
 164                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 165         /* PCI-E devices. */
 166         [RTL_GIGA_MAC_VER_07] =
 167                 _R("RTL8102e",          RTL_TD_1, NULL),
 168         [RTL_GIGA_MAC_VER_08] =
 169                 _R("RTL8102e",          RTL_TD_1, NULL),
 170         [RTL_GIGA_MAC_VER_09] =
 171                 _R("RTL8102e",          RTL_TD_1, NULL),
 172         [RTL_GIGA_MAC_VER_10] =
 173                 _R("RTL8101e",          RTL_TD_0, NULL),
 174         [RTL_GIGA_MAC_VER_11] =
 175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 176         [RTL_GIGA_MAC_VER_12] =
 177                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 178         [RTL_GIGA_MAC_VER_13] =
 179                 _R("RTL8101e",          RTL_TD_0, NULL),
 180         [RTL_GIGA_MAC_VER_14] =
 181                 _R("RTL8100e",          RTL_TD_0, NULL),
 182         [RTL_GIGA_MAC_VER_15] =
 183                 _R("RTL8100e",          RTL_TD_0, NULL),
 184         [RTL_GIGA_MAC_VER_16] =
 185                 _R("RTL8101e",          RTL_TD_0, NULL),
 186         [RTL_GIGA_MAC_VER_17] =
 187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 188         [RTL_GIGA_MAC_VER_18] =
 189                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 190         [RTL_GIGA_MAC_VER_19] =
 191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 192         [RTL_GIGA_MAC_VER_20] =
 193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 194         [RTL_GIGA_MAC_VER_21] =
 195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 196         [RTL_GIGA_MAC_VER_22] =
 197                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 198         [RTL_GIGA_MAC_VER_23] =
 199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 200         [RTL_GIGA_MAC_VER_24] =
 201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 202         [RTL_GIGA_MAC_VER_25] =
 203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
 204         [RTL_GIGA_MAC_VER_26] =
 205                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
 206         [RTL_GIGA_MAC_VER_27] =
 207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 208         [RTL_GIGA_MAC_VER_28] =
 209                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 210         [RTL_GIGA_MAC_VER_29] =
 211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 212         [RTL_GIGA_MAC_VER_30] =
 213                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 214         [RTL_GIGA_MAC_VER_31] =
 215                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 216         [RTL_GIGA_MAC_VER_32] =
 217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
 218         [RTL_GIGA_MAC_VER_33] =
 219                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2)
 220 };
 221 #undef _R
 222
 223 enum cfg_version {
 224         RTL_CFG_0 = 0x00,
 225         RTL_CFG_1,
 226         RTL_CFG_2
 227 };
 228
 229 static void rtl_hw_start_8169(struct net_device *);
 230 static void rtl_hw_start_8168(struct net_device *);
 231 static void rtl_hw_start_8101(struct net_device *);
 232
 233 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 234         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 235         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 238         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 239         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 240         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 241         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 242         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 243                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 244         { 0x0001,                               0x8168,
 245                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 246         {0,},
 247 };
 248
 249 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 250
 251 static int rx_buf_sz = 16383;
 252 static int use_dac;
 253 static struct {
 254         u32 msg_enable;
 255 } debug = { -1 };
 256
 257 enum rtl_registers {
 258         MAC0            = 0,    /* Ethernet hardware address. */
 259         MAC4            = 4,
 260         MAR0            = 8,    /* Multicast filter. */
 261         CounterAddrLow          = 0x10,
 262         CounterAddrHigh         = 0x14,
 263         TxDescStartAddrLow      = 0x20,
 264         TxDescStartAddrHigh     = 0x24,
 265         TxHDescStartAddrLow     = 0x28,
 266         TxHDescStartAddrHigh    = 0x2c,
 267         FLASH           = 0x30,
 268         ERSR            = 0x36,
 269         ChipCmd         = 0x37,
 270         TxPoll          = 0x38,
 271         IntrMask        = 0x3c,
 272         IntrStatus      = 0x3e,
 273         TxConfig        = 0x40,
 274         RxConfig        = 0x44,
 275
 276 #define RTL_RX_CONFIG_MASK              0xff7e1880u
 277
 278         RxMissed        = 0x4c,
 279         Cfg9346         = 0x50,
 280         Config0         = 0x51,
 281         Config1         = 0x52,
 282         Config2         = 0x53,
 283         Config3         = 0x54,
 284         Config4         = 0x55,
 285         Config5         = 0x56,
 286         MultiIntr       = 0x5c,
 287         PHYAR           = 0x60,
 288         PHYstatus       = 0x6c,
 289         RxMaxSize       = 0xda,
 290         CPlusCmd        = 0xe0,
 291         IntrMitigate    = 0xe2,
 292         RxDescAddrLow   = 0xe4,
 293         RxDescAddrHigh  = 0xe8,
 294         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 295
 296 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 297
 298         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 299
 300 #define TxPacketMax     (8064 >> 7)
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         FuncForceEvent  = 0xfc,
 306 };
 307
 308 enum rtl8110_registers {
 309         TBICSR                  = 0x64,
 310         TBI_ANAR                = 0x68,
 311         TBI_LPAR                = 0x6a,
 312 };
 313
 314 enum rtl8168_8101_registers {
 315         CSIDR                   = 0x64,
 316         CSIAR                   = 0x68,
 317 #define CSIAR_FLAG                      0x80000000
 318 #define CSIAR_WRITE_CMD                 0x80000000
 319 #define CSIAR_BYTE_ENABLE               0x0f
 320 #define CSIAR_BYTE_ENABLE_SHIFT         12
 321 #define CSIAR_ADDR_MASK                 0x0fff
 322         PMCH                    = 0x6f,
 323         EPHYAR                  = 0x80,
 324 #define EPHYAR_FLAG                     0x80000000
 325 #define EPHYAR_WRITE_CMD                0x80000000
 326 #define EPHYAR_REG_MASK                 0x1f
 327 #define EPHYAR_REG_SHIFT                16
 328 #define EPHYAR_DATA_MASK                0xffff
 329         DLLPR                   = 0xd0,
 330 #define PM_SWITCH                       (1 << 6)
 331         DBG_REG                 = 0xd1,
 332 #define FIX_NAK_1                       (1 << 4)
 333 #define FIX_NAK_2                       (1 << 3)
 334         TWSI                    = 0xd2,
 335         MCU                     = 0xd3,
 336 #define EN_NDP                          (1 << 3)
 337 #define EN_OOB_RESET                    (1 << 2)
 338         EFUSEAR                 = 0xdc,
 339 #define EFUSEAR_FLAG                    0x80000000
 340 #define EFUSEAR_WRITE_CMD               0x80000000
 341 #define EFUSEAR_READ_CMD                0x00000000
 342 #define EFUSEAR_REG_MASK                0x03ff
 343 #define EFUSEAR_REG_SHIFT               8
 344 #define EFUSEAR_DATA_MASK               0xff
 345 };
 346
 347 enum rtl8168_registers {
 348         ERIDR                   = 0x70,
 349         ERIAR                   = 0x74,
 350 #define ERIAR_FLAG                      0x80000000
 351 #define ERIAR_WRITE_CMD                 0x80000000
 352 #define ERIAR_READ_CMD                  0x00000000
 353 #define ERIAR_ADDR_BYTE_ALIGN           4
 354 #define ERIAR_EXGMAC                    0
 355 #define ERIAR_MSIX                      1
 356 #define ERIAR_ASF                       2
 357 #define ERIAR_TYPE_SHIFT                16
 358 #define ERIAR_BYTEEN                    0x0f
 359 #define ERIAR_BYTEEN_SHIFT              12
 360         EPHY_RXER_NUM           = 0x7c,
 361         OCPDR                   = 0xb0, /* OCP GPHY access */
 362 #define OCPDR_WRITE_CMD                 0x80000000
 363 #define OCPDR_READ_CMD                  0x00000000
 364 #define OCPDR_REG_MASK                  0x7f
 365 #define OCPDR_GPHY_REG_SHIFT            16
 366 #define OCPDR_DATA_MASK                 0xffff
 367         OCPAR                   = 0xb4,
 368 #define OCPAR_FLAG                      0x80000000
 369 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 370 #define OCPAR_GPHY_READ_CMD             0x0000f060
 371         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 372         MISC                    = 0xf0, /* 8168e only. */
 373 #define TXPLA_RST                       (1 << 29)
 374 };
 375
 376 enum rtl_register_content {
 377         /* InterruptStatusBits */
 378         SYSErr          = 0x8000,
 379         PCSTimeout      = 0x4000,
 380         SWInt           = 0x0100,
 381         TxDescUnavail   = 0x0080,
 382         RxFIFOOver      = 0x0040,
 383         LinkChg         = 0x0020,
 384         RxOverflow      = 0x0010,
 385         TxErr           = 0x0008,
 386         TxOK            = 0x0004,
 387         RxErr           = 0x0002,
 388         RxOK            = 0x0001,
 389
 390         /* RxStatusDesc */
 391         RxFOVF  = (1 << 23),
 392         RxRWT   = (1 << 22),
 393         RxRES   = (1 << 21),
 394         RxRUNT  = (1 << 20),
 395         RxCRC   = (1 << 19),
 396
 397         /* ChipCmdBits */
 398         CmdReset        = 0x10,
 399         CmdRxEnb        = 0x08,
 400         CmdTxEnb        = 0x04,
 401         RxBufEmpty      = 0x01,
 402
 403         /* TXPoll register p.5 */
 404         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 405         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 406         FSWInt          = 0x01,         /* Forced software interrupt */
 407
 408         /* Cfg9346Bits */
 409         Cfg9346_Lock    = 0x00,
 410         Cfg9346_Unlock  = 0xc0,
 411
 412         /* rx_mode_bits */
 413         AcceptErr       = 0x20,
 414         AcceptRunt      = 0x10,
 415         AcceptBroadcast = 0x08,
 416         AcceptMulticast = 0x04,
 417         AcceptMyPhys    = 0x02,
 418         AcceptAllPhys   = 0x01,
 419
 420         /* RxConfigBits */
 421         RxCfgFIFOShift  = 13,
 422         RxCfgDMAShift   =  8,
 423
 424         /* TxConfigBits */
 425         TxInterFrameGapShift = 24,
 426         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 427
 428         /* Config1 register p.24 */
 429         LEDS1           = (1 << 7),
 430         LEDS0           = (1 << 6),
 431         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 432         Speed_down      = (1 << 4),
 433         MEMMAP          = (1 << 3),
 434         IOMAP           = (1 << 2),
 435         VPD             = (1 << 1),
 436         PMEnable        = (1 << 0),     /* Power Management Enable */
 437
 438         /* Config2 register p. 25 */
 439         PCI_Clock_66MHz = 0x01,
 440         PCI_Clock_33MHz = 0x00,
 441
 442         /* Config3 register p.25 */
 443         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 444         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 445         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 446
 447         /* Config5 register p.27 */
 448         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 449         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 450         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 451         Spi_en          = (1 << 3),
 452         LanWake         = (1 << 1),     /* LanWake enable/disable */
 453         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 454
 455         /* TBICSR p.28 */
 456         TBIReset        = 0x80000000,
 457         TBILoopback     = 0x40000000,
 458         TBINwEnable     = 0x20000000,
 459         TBINwRestart    = 0x10000000,
 460         TBILinkOk       = 0x02000000,
 461         TBINwComplete   = 0x01000000,
 462
 463         /* CPlusCmd p.31 */
 464         EnableBist      = (1 << 15),    // 8168 8101
 465         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 466         Normal_mode     = (1 << 13),    // unused
 467         Force_half_dup  = (1 << 12),    // 8168 8101
 468         Force_rxflow_en = (1 << 11),    // 8168 8101
 469         Force_txflow_en = (1 << 10),    // 8168 8101
 470         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 471         ASF             = (1 << 8),     // 8168 8101
 472         PktCntrDisable  = (1 << 7),     // 8168 8101
 473         Mac_dbgo_sel    = 0x001c,       // 8168
 474         RxVlan          = (1 << 6),
 475         RxChkSum        = (1 << 5),
 476         PCIDAC          = (1 << 4),
 477         PCIMulRW        = (1 << 3),
 478         INTT_0          = 0x0000,       // 8168
 479         INTT_1          = 0x0001,       // 8168
 480         INTT_2          = 0x0002,       // 8168
 481         INTT_3          = 0x0003,       // 8168
 482
 483         /* rtl8169_PHYstatus */
 484         TBI_Enable      = 0x80,
 485         TxFlowCtrl      = 0x40,
 486         RxFlowCtrl      = 0x20,
 487         _1000bpsF       = 0x10,
 488         _100bps         = 0x08,
 489         _10bps          = 0x04,
 490         LinkStatus      = 0x02,
 491         FullDup         = 0x01,
 492
 493         /* _TBICSRBit */
 494         TBILinkOK       = 0x02000000,
 495
 496         /* DumpCounterCommand */
 497         CounterDump     = 0x8,
 498 };
 499
 500 enum rtl_desc_bit {
 501         /* First doubleword. */
 502         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 503         RingEnd         = (1 << 30), /* End of descriptor ring */
 504         FirstFrag       = (1 << 29), /* First segment of a packet */
 505         LastFrag        = (1 << 28), /* Final segment of a packet */
 506 };
 507
 508 /* Generic case. */
 509 enum rtl_tx_desc_bit {
 510         /* First doubleword. */
 511         TD_LSO          = (1 << 27),            /* Large Send Offload */
 512 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 513
 514         /* Second doubleword. */
 515         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 516 };
 517
 518 /* 8169, 8168b and 810x except 8102e. */
 519 enum rtl_tx_desc_bit_0 {
 520         /* First doubleword. */
 521 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 522         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 523         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 524         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 525 };
 526
 527 /* 8102e, 8168c and beyond. */
 528 enum rtl_tx_desc_bit_1 {
 529         /* Second doubleword. */
 530 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 531         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 532         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 533         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 534 };
 535
 536 static const struct rtl_tx_desc_info {
 537         struct {
 538                 u32 udp;
 539                 u32 tcp;
 540         } checksum;
 541         u16 mss_shift;
 542         u16 opts_offset;
 543 } tx_desc_info [] = {
 544         [RTL_TD_0] = {
 545                 .checksum = {
 546                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 547                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 548                 },
 549                 .mss_shift      = TD0_MSS_SHIFT,
 550                 .opts_offset    = 0
 551         },
 552         [RTL_TD_1] = {
 553                 .checksum = {
 554                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 555                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 556                 },
 557                 .mss_shift      = TD1_MSS_SHIFT,
 558                 .opts_offset    = 1
 559         }
 560 };
 561
 562 enum rtl_rx_desc_bit {
 563         /* Rx private */
 564         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 565         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 566
 567 #define RxProtoUDP      (PID1)
 568 #define RxProtoTCP      (PID0)
 569 #define RxProtoIP       (PID1 | PID0)
 570 #define RxProtoMask     RxProtoIP
 571
 572         IPFail          = (1 << 16), /* IP checksum failed */
 573         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 574         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 575         RxVlanTag       = (1 << 16), /* VLAN tag available */
 576 };
 577
 578 #define RsvdMask        0x3fffc000
 579
 580 struct TxDesc {
 581         __le32 opts1;
 582         __le32 opts2;
 583         __le64 addr;
 584 };
 585
 586 struct RxDesc {
 587         __le32 opts1;
 588         __le32 opts2;
 589         __le64 addr;
 590 };
 591
 592 struct ring_info {
 593         struct sk_buff  *skb;
 594         u32             len;
 595         u8              __pad[sizeof(void *) - sizeof(u32)];
 596 };
 597
 598 enum features {
 599         RTL_FEATURE_WOL         = (1 << 0),
 600         RTL_FEATURE_MSI         = (1 << 1),
 601         RTL_FEATURE_GMII        = (1 << 2),
 602 };
 603
 604 struct rtl8169_counters {
 605         __le64  tx_packets;
 606         __le64  rx_packets;
 607         __le64  tx_errors;
 608         __le32  rx_errors;
 609         __le16  rx_missed;
 610         __le16  align_errors;
 611         __le32  tx_one_collision;
 612         __le32  tx_multi_collision;
 613         __le64  rx_unicast;
 614         __le64  rx_broadcast;
 615         __le32  rx_multicast;
 616         __le16  tx_aborted;
 617         __le16  tx_underun;
 618 };
 619
 620 struct rtl8169_private {
 621         void __iomem *mmio_addr;        /* memory map physical address */
 622         struct pci_dev *pci_dev;
 623         struct net_device *dev;
 624         struct napi_struct napi;
 625         spinlock_t lock;
 626         u32 msg_enable;
 627         u16 txd_version;
 628         u16 mac_version;
 629         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 630         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 631         u32 dirty_rx;
 632         u32 dirty_tx;
 633         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 634         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 635         dma_addr_t TxPhyAddr;
 636         dma_addr_t RxPhyAddr;
 637         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 638         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 639         struct timer_list timer;
 640         u16 cp_cmd;
 641         u16 intr_event;
 642         u16 napi_event;
 643         u16 intr_mask;
 644
 645         struct mdio_ops {
 646                 void (*write)(void __iomem *, int, int);
 647                 int (*read)(void __iomem *, int);
 648         } mdio_ops;
 649
 650         struct pll_power_ops {
 651                 void (*down)(struct rtl8169_private *);
 652                 void (*up)(struct rtl8169_private *);
 653         } pll_power_ops;
 654
 655         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 656         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 657         void (*phy_reset_enable)(struct rtl8169_private *tp);
 658         void (*hw_start)(struct net_device *);
 659         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 660         unsigned int (*link_ok)(void __iomem *);
 661         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 662         int pcie_cap;
 663         struct delayed_work task;
 664         unsigned features;
 665
 666         struct mii_if_info mii;
 667         struct rtl8169_counters counters;
 668         u32 saved_wolopts;
 669
 670         struct rtl_fw {
 671                 const struct firmware *fw;
 672
 673 #define RTL_VER_SIZE            32
 674
 675                 char version[RTL_VER_SIZE];
 676
 677                 struct rtl_fw_phy_action {
 678                         __le32 *code;
 679                         size_t size;
 680                 } phy_action;
 681         } *rtl_fw;
 682 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
 683 };
 684
 685 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 686 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 687 module_param(use_dac, int, 0);
 688 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 689 module_param_named(debug, debug.msg_enable, int, 0);
 690 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 691 MODULE_LICENSE("GPL");
 692 MODULE_VERSION(RTL8169_VERSION);
 693 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 694 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 695 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 696 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 697 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 698
 699 static int rtl8169_open(struct net_device *dev);
 700 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 701                                       struct net_device *dev);
 702 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 703 static int rtl8169_init_ring(struct net_device *dev);
 704 static void rtl_hw_start(struct net_device *dev);
 705 static int rtl8169_close(struct net_device *dev);
 706 static void rtl_set_rx_mode(struct net_device *dev);
 707 static void rtl8169_tx_timeout(struct net_device *dev);
 708 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 709 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 710                                 void __iomem *, u32 budget);
 711 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 712 static void rtl8169_down(struct net_device *dev);
 713 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 714 static int rtl8169_poll(struct napi_struct *napi, int budget);
 715
 716 static const unsigned int rtl8169_rx_config =
 717         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 718
 719 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 720 {
 721         void __iomem *ioaddr = tp->mmio_addr;
 722         int i;
 723
 724         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 725         for (i = 0; i < 20; i++) {
 726                 udelay(100);
 727                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 728                         break;
 729         }
 730         return RTL_R32(OCPDR);
 731 }
 732
 733 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 734 {
 735         void __iomem *ioaddr = tp->mmio_addr;
 736         int i;
 737
 738         RTL_W32(OCPDR, data);
 739         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 740         for (i = 0; i < 20; i++) {
 741                 udelay(100);
 742                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 743                         break;
 744         }
 745 }
 746
 747 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 748 {
 749         void __iomem *ioaddr = tp->mmio_addr;
 750         int i;
 751
 752         RTL_W8(ERIDR, cmd);
 753         RTL_W32(ERIAR, 0x800010e8);
 754         msleep(2);
 755         for (i = 0; i < 5; i++) {
 756                 udelay(100);
 757                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
 758                         break;
 759         }
 760
 761         ocp_write(tp, 0x1, 0x30, 0x00000001);
 762 }
 763
 764 #define OOB_CMD_RESET           0x00
 765 #define OOB_CMD_DRIVER_START    0x05
 766 #define OOB_CMD_DRIVER_STOP     0x06
 767
 768 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 769 {
 770         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 771 }
 772
 773 static void rtl8168_driver_start(struct rtl8169_private *tp)
 774 {
 775         u16 reg;
 776         int i;
 777
 778         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 779
 780         reg = rtl8168_get_ocp_reg(tp);
 781
 782         for (i = 0; i < 10; i++) {
 783                 msleep(10);
 784                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 785                         break;
 786         }
 787 }
 788
 789 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 790 {
 791         u16 reg;
 792         int i;
 793
 794         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 795
 796         reg = rtl8168_get_ocp_reg(tp);
 797
 798         for (i = 0; i < 10; i++) {
 799                 msleep(10);
 800                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 801                         break;
 802         }
 803 }
 804
 805 static int r8168dp_check_dash(struct rtl8169_private *tp)
 806 {
 807         u16 reg = rtl8168_get_ocp_reg(tp);
 808
 809         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 810 }
 811
 812 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 813 {
 814         int i;
 815
 816         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 817
 818         for (i = 20; i > 0; i--) {
 819                 /*
 820                  * Check if the RTL8169 has completed writing to the specified
 821                  * MII register.
 822                  */
 823                 if (!(RTL_R32(PHYAR) & 0x80000000))
 824                         break;
 825                 udelay(25);
 826         }
 827         /*
 828          * According to hardware specs a 20us delay is required after write
 829          * complete indication, but before sending next command.
 830          */
 831         udelay(20);
 832 }
 833
 834 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 835 {
 836         int i, value = -1;
 837
 838         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 839
 840         for (i = 20; i > 0; i--) {
 841                 /*
 842                  * Check if the RTL8169 has completed retrieving data from
 843                  * the specified MII register.
 844                  */
 845                 if (RTL_R32(PHYAR) & 0x80000000) {
 846                         value = RTL_R32(PHYAR) & 0xffff;
 847                         break;
 848                 }
 849                 udelay(25);
 850         }
 851         /*
 852          * According to hardware specs a 20us delay is required after read
 853          * complete indication, but before sending next command.
 854          */
 855         udelay(20);
 856
 857         return value;
 858 }
 859
 860 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 861 {
 862         int i;
 863
 864         RTL_W32(OCPDR, data |
 865                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 866         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 867         RTL_W32(EPHY_RXER_NUM, 0);
 868
 869         for (i = 0; i < 100; i++) {
 870                 mdelay(1);
 871                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 872                         break;
 873         }
 874 }
 875
 876 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 877 {
 878         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 879                 (value & OCPDR_DATA_MASK));
 880 }
 881
 882 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 883 {
 884         int i;
 885
 886         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 887
 888         mdelay(1);
 889         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 890         RTL_W32(EPHY_RXER_NUM, 0);
 891
 892         for (i = 0; i < 100; i++) {
 893                 mdelay(1);
 894                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 895                         break;
 896         }
 897
 898         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 899 }
 900
 901 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 902
 903 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 904 {
 905         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 906 }
 907
 908 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 909 {
 910         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 911 }
 912
 913 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 914 {
 915         r8168dp_2_mdio_start(ioaddr);
 916
 917         r8169_mdio_write(ioaddr, reg_addr, value);
 918
 919         r8168dp_2_mdio_stop(ioaddr);
 920 }
 921
 922 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 923 {
 924         int value;
 925
 926         r8168dp_2_mdio_start(ioaddr);
 927
 928         value = r8169_mdio_read(ioaddr, reg_addr);
 929
 930         r8168dp_2_mdio_stop(ioaddr);
 931
 932         return value;
 933 }
 934
 935 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 936 {
 937         tp->mdio_ops.write(tp->mmio_addr, location, val);
 938 }
 939
 940 static int rtl_readphy(struct rtl8169_private *tp, int location)
 941 {
 942         return tp->mdio_ops.read(tp->mmio_addr, location);
 943 }
 944
 945 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 946 {
 947         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 948 }
 949
 950 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 951 {
 952         int val;
 953
 954         val = rtl_readphy(tp, reg_addr);
 955         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 956 }
 957
 958 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 959                            int val)
 960 {
 961         struct rtl8169_private *tp = netdev_priv(dev);
 962
 963         rtl_writephy(tp, location, val);
 964 }
 965
 966 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 967 {
 968         struct rtl8169_private *tp = netdev_priv(dev);
 969
 970         return rtl_readphy(tp, location);
 971 }
 972
 973 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 974 {
 975         unsigned int i;
 976
 977         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 978                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 979
 980         for (i = 0; i < 100; i++) {
 981                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 982                         break;
 983                 udelay(10);
 984         }
 985 }
 986
 987 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 988 {
 989         u16 value = 0xffff;
 990         unsigned int i;
 991
 992         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 993
 994         for (i = 0; i < 100; i++) {
 995                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 996                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 997                         break;
 998                 }
 999                 udelay(10);
1000         }
1001
1002         return value;
1003 }
1004
1005 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1006 {
1007         unsigned int i;
1008
1009         RTL_W32(CSIDR, value);
1010         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1011                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1012
1013         for (i = 0; i < 100; i++) {
1014                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1015                         break;
1016                 udelay(10);
1017         }
1018 }
1019
1020 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1021 {
1022         u32 value = ~0x00;
1023         unsigned int i;
1024
1025         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1026                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1027
1028         for (i = 0; i < 100; i++) {
1029                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1030                         value = RTL_R32(CSIDR);
1031                         break;
1032                 }
1033                 udelay(10);
1034         }
1035
1036         return value;
1037 }
1038
1039 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1040 {
1041         u8 value = 0xff;
1042         unsigned int i;
1043
1044         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1045
1046         for (i = 0; i < 300; i++) {
1047                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1048                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1049                         break;
1050                 }
1051                 udelay(100);
1052         }
1053
1054         return value;
1055 }
1056
1057 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1058 {
1059         RTL_W16(IntrMask, 0x0000);
1060
1061         RTL_W16(IntrStatus, 0xffff);
1062 }
1063
1064 static void rtl8169_asic_down(void __iomem *ioaddr)
1065 {
1066         RTL_W8(ChipCmd, 0x00);
1067         rtl8169_irq_mask_and_ack(ioaddr);
1068         RTL_R16(CPlusCmd);
1069 }
1070
1071 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1072 {
1073         void __iomem *ioaddr = tp->mmio_addr;
1074
1075         return RTL_R32(TBICSR) & TBIReset;
1076 }
1077
1078 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1079 {
1080         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1081 }
1082
1083 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1084 {
1085         return RTL_R32(TBICSR) & TBILinkOk;
1086 }
1087
1088 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1089 {
1090         return RTL_R8(PHYstatus) & LinkStatus;
1091 }
1092
1093 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1094 {
1095         void __iomem *ioaddr = tp->mmio_addr;
1096
1097         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1098 }
1099
1100 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1101 {
1102         unsigned int val;
1103
1104         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1105         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1106 }
1107
1108 static void __rtl8169_check_link_status(struct net_device *dev,
1109                                         struct rtl8169_private *tp,
1110                                         void __iomem *ioaddr, bool pm)
1111 {
1112         unsigned long flags;
1113
1114         spin_lock_irqsave(&tp->lock, flags);
1115         if (tp->link_ok(ioaddr)) {
1116                 /* This is to cancel a scheduled suspend if there's one. */
1117                 if (pm)
1118                         pm_request_resume(&tp->pci_dev->dev);
1119                 netif_carrier_on(dev);
1120                 if (net_ratelimit())
1121                         netif_info(tp, ifup, dev, "link up\n");
1122         } else {
1123                 netif_carrier_off(dev);
1124                 netif_info(tp, ifdown, dev, "link down\n");
1125                 if (pm)
1126                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1127         }
1128         spin_unlock_irqrestore(&tp->lock, flags);
1129 }
1130
1131 static void rtl8169_check_link_status(struct net_device *dev,
1132                                       struct rtl8169_private *tp,
1133                                       void __iomem *ioaddr)
1134 {
1135         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1136 }
1137
1138 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1139
1140 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1141 {
1142         void __iomem *ioaddr = tp->mmio_addr;
1143         u8 options;
1144         u32 wolopts = 0;
1145
1146         options = RTL_R8(Config1);
1147         if (!(options & PMEnable))
1148                 return 0;
1149
1150         options = RTL_R8(Config3);
1151         if (options & LinkUp)
1152                 wolopts |= WAKE_PHY;
1153         if (options & MagicPacket)
1154                 wolopts |= WAKE_MAGIC;
1155
1156         options = RTL_R8(Config5);
1157         if (options & UWF)
1158                 wolopts |= WAKE_UCAST;
1159         if (options & BWF)
1160                 wolopts |= WAKE_BCAST;
1161         if (options & MWF)
1162                 wolopts |= WAKE_MCAST;
1163
1164         return wolopts;
1165 }
1166
1167 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1168 {
1169         struct rtl8169_private *tp = netdev_priv(dev);
1170
1171         spin_lock_irq(&tp->lock);
1172
1173         wol->supported = WAKE_ANY;
1174         wol->wolopts = __rtl8169_get_wol(tp);
1175
1176         spin_unlock_irq(&tp->lock);
1177 }
1178
1179 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1180 {
1181         void __iomem *ioaddr = tp->mmio_addr;
1182         unsigned int i;
1183         static const struct {
1184                 u32 opt;
1185                 u16 reg;
1186                 u8  mask;
1187         } cfg[] = {
1188                 { WAKE_ANY,   Config1, PMEnable },
1189                 { WAKE_PHY,   Config3, LinkUp },
1190                 { WAKE_MAGIC, Config3, MagicPacket },
1191                 { WAKE_UCAST, Config5, UWF },
1192                 { WAKE_BCAST, Config5, BWF },
1193                 { WAKE_MCAST, Config5, MWF },
1194                 { WAKE_ANY,   Config5, LanWake }
1195         };
1196
1197         RTL_W8(Cfg9346, Cfg9346_Unlock);
1198
1199         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1200                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1201                 if (wolopts & cfg[i].opt)
1202                         options |= cfg[i].mask;
1203                 RTL_W8(cfg[i].reg, options);
1204         }
1205
1206         RTL_W8(Cfg9346, Cfg9346_Lock);
1207 }
1208
1209 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1210 {
1211         struct rtl8169_private *tp = netdev_priv(dev);
1212
1213         spin_lock_irq(&tp->lock);
1214
1215         if (wol->wolopts)
1216                 tp->features |= RTL_FEATURE_WOL;
1217         else
1218                 tp->features &= ~RTL_FEATURE_WOL;
1219         __rtl8169_set_wol(tp, wol->wolopts);
1220         spin_unlock_irq(&tp->lock);
1221
1222         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1223
1224         return 0;
1225 }
1226
1227 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1228 {
1229         return rtl_chip_infos[tp->mac_version].fw_name;
1230 }
1231
1232 static void rtl8169_get_drvinfo(struct net_device *dev,
1233                                 struct ethtool_drvinfo *info)
1234 {
1235         struct rtl8169_private *tp = netdev_priv(dev);
1236         struct rtl_fw *rtl_fw = tp->rtl_fw;
1237
1238         strcpy(info->driver, MODULENAME);
1239         strcpy(info->version, RTL8169_VERSION);
1240         strcpy(info->bus_info, pci_name(tp->pci_dev));
1241         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1242         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1243                rtl_fw->version);
1244 }
1245
1246 static int rtl8169_get_regs_len(struct net_device *dev)
1247 {
1248         return R8169_REGS_SIZE;
1249 }
1250
1251 static int rtl8169_set_speed_tbi(struct net_device *dev,
1252                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1253 {
1254         struct rtl8169_private *tp = netdev_priv(dev);
1255         void __iomem *ioaddr = tp->mmio_addr;
1256         int ret = 0;
1257         u32 reg;
1258
1259         reg = RTL_R32(TBICSR);
1260         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1261             (duplex == DUPLEX_FULL)) {
1262                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1263         } else if (autoneg == AUTONEG_ENABLE)
1264                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1265         else {
1266                 netif_warn(tp, link, dev,
1267                            "incorrect speed setting refused in TBI mode\n");
1268                 ret = -EOPNOTSUPP;
1269         }
1270
1271         return ret;
1272 }
1273
1274 static int rtl8169_set_speed_xmii(struct net_device *dev,
1275                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1276 {
1277         struct rtl8169_private *tp = netdev_priv(dev);
1278         int giga_ctrl, bmcr;
1279         int rc = -EINVAL;
1280
1281         rtl_writephy(tp, 0x1f, 0x0000);
1282
1283         if (autoneg == AUTONEG_ENABLE) {
1284                 int auto_nego;
1285
1286                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1287                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1288                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1289
1290                 if (adv & ADVERTISED_10baseT_Half)
1291                         auto_nego |= ADVERTISE_10HALF;
1292                 if (adv & ADVERTISED_10baseT_Full)
1293                         auto_nego |= ADVERTISE_10FULL;
1294                 if (adv & ADVERTISED_100baseT_Half)
1295                         auto_nego |= ADVERTISE_100HALF;
1296                 if (adv & ADVERTISED_100baseT_Full)
1297                         auto_nego |= ADVERTISE_100FULL;
1298
1299                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1300
1301                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1302                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1303
1304                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1305                 if (tp->mii.supports_gmii) {
1306                         if (adv & ADVERTISED_1000baseT_Half)
1307                                 giga_ctrl |= ADVERTISE_1000HALF;
1308                         if (adv & ADVERTISED_1000baseT_Full)
1309                                 giga_ctrl |= ADVERTISE_1000FULL;
1310                 } else if (adv & (ADVERTISED_1000baseT_Half |
1311                                   ADVERTISED_1000baseT_Full)) {
1312                         netif_info(tp, link, dev,
1313                                    "PHY does not support 1000Mbps\n");
1314                         goto out;
1315                 }
1316
1317                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1318
1319                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1320                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1321         } else {
1322                 giga_ctrl = 0;
1323
1324                 if (speed == SPEED_10)
1325                         bmcr = 0;
1326                 else if (speed == SPEED_100)
1327                         bmcr = BMCR_SPEED100;
1328                 else
1329                         goto out;
1330
1331                 if (duplex == DUPLEX_FULL)
1332                         bmcr |= BMCR_FULLDPLX;
1333         }
1334
1335         rtl_writephy(tp, MII_BMCR, bmcr);
1336
1337         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1338             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1339                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1340                         rtl_writephy(tp, 0x17, 0x2138);
1341                         rtl_writephy(tp, 0x0e, 0x0260);
1342                 } else {
1343                         rtl_writephy(tp, 0x17, 0x2108);
1344                         rtl_writephy(tp, 0x0e, 0x0000);
1345                 }
1346         }
1347
1348         rc = 0;
1349 out:
1350         return rc;
1351 }
1352
1353 static int rtl8169_set_speed(struct net_device *dev,
1354                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1355 {
1356         struct rtl8169_private *tp = netdev_priv(dev);
1357         int ret;
1358
1359         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1360         if (ret < 0)
1361                 goto out;
1362
1363         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1364             (advertising & ADVERTISED_1000baseT_Full)) {
1365                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1366         }
1367 out:
1368         return ret;
1369 }
1370
1371 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1372 {
1373         struct rtl8169_private *tp = netdev_priv(dev);
1374         unsigned long flags;
1375         int ret;
1376
1377         del_timer_sync(&tp->timer);
1378
1379         spin_lock_irqsave(&tp->lock, flags);
1380         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1381                                 cmd->duplex, cmd->advertising);
1382         spin_unlock_irqrestore(&tp->lock, flags);
1383
1384         return ret;
1385 }
1386
1387 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1388 {
1389         if (dev->mtu > TD_MSS_MAX)
1390                 features &= ~NETIF_F_ALL_TSO;
1391
1392         return features;
1393 }
1394
1395 static int rtl8169_set_features(struct net_device *dev, u32 features)
1396 {
1397         struct rtl8169_private *tp = netdev_priv(dev);
1398         void __iomem *ioaddr = tp->mmio_addr;
1399         unsigned long flags;
1400
1401         spin_lock_irqsave(&tp->lock, flags);
1402
1403         if (features & NETIF_F_RXCSUM)
1404                 tp->cp_cmd |= RxChkSum;
1405         else
1406                 tp->cp_cmd &= ~RxChkSum;
1407
1408         if (dev->features & NETIF_F_HW_VLAN_RX)
1409                 tp->cp_cmd |= RxVlan;
1410         else
1411                 tp->cp_cmd &= ~RxVlan;
1412
1413         RTL_W16(CPlusCmd, tp->cp_cmd);
1414         RTL_R16(CPlusCmd);
1415
1416         spin_unlock_irqrestore(&tp->lock, flags);
1417
1418         return 0;
1419 }
1420
1421 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1422                                       struct sk_buff *skb)
1423 {
1424         return (vlan_tx_tag_present(skb)) ?
1425                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1426 }
1427
1428 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1429 {
1430         u32 opts2 = le32_to_cpu(desc->opts2);
1431
1432         if (opts2 & RxVlanTag)
1433                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1434
1435         desc->opts2 = 0;
1436 }
1437
1438 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1439 {
1440         struct rtl8169_private *tp = netdev_priv(dev);
1441         void __iomem *ioaddr = tp->mmio_addr;
1442         u32 status;
1443
1444         cmd->supported =
1445                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1446         cmd->port = PORT_FIBRE;
1447         cmd->transceiver = XCVR_INTERNAL;
1448
1449         status = RTL_R32(TBICSR);
1450         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1451         cmd->autoneg = !!(status & TBINwEnable);
1452
1453         ethtool_cmd_speed_set(cmd, SPEED_1000);
1454         cmd->duplex = DUPLEX_FULL; /* Always set */
1455
1456         return 0;
1457 }
1458
1459 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1460 {
1461         struct rtl8169_private *tp = netdev_priv(dev);
1462
1463         return mii_ethtool_gset(&tp->mii, cmd);
1464 }
1465
1466 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1467 {
1468         struct rtl8169_private *tp = netdev_priv(dev);
1469         unsigned long flags;
1470         int rc;
1471
1472         spin_lock_irqsave(&tp->lock, flags);
1473
1474         rc = tp->get_settings(dev, cmd);
1475
1476         spin_unlock_irqrestore(&tp->lock, flags);
1477         return rc;
1478 }
1479
1480 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1481                              void *p)
1482 {
1483         struct rtl8169_private *tp = netdev_priv(dev);
1484         unsigned long flags;
1485
1486         if (regs->len > R8169_REGS_SIZE)
1487                 regs->len = R8169_REGS_SIZE;
1488
1489         spin_lock_irqsave(&tp->lock, flags);
1490         memcpy_fromio(p, tp->mmio_addr, regs->len);
1491         spin_unlock_irqrestore(&tp->lock, flags);
1492 }
1493
1494 static u32 rtl8169_get_msglevel(struct net_device *dev)
1495 {
1496         struct rtl8169_private *tp = netdev_priv(dev);
1497
1498         return tp->msg_enable;
1499 }
1500
1501 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1502 {
1503         struct rtl8169_private *tp = netdev_priv(dev);
1504
1505         tp->msg_enable = value;
1506 }
1507
1508 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1509         "tx_packets",
1510         "rx_packets",
1511         "tx_errors",
1512         "rx_errors",
1513         "rx_missed",
1514         "align_errors",
1515         "tx_single_collisions",
1516         "tx_multi_collisions",
1517         "unicast",
1518         "broadcast",
1519         "multicast",
1520         "tx_aborted",
1521         "tx_underrun",
1522 };
1523
1524 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1525 {
1526         switch (sset) {
1527         case ETH_SS_STATS:
1528                 return ARRAY_SIZE(rtl8169_gstrings);
1529         default:
1530                 return -EOPNOTSUPP;
1531         }
1532 }
1533
1534 static void rtl8169_update_counters(struct net_device *dev)
1535 {
1536         struct rtl8169_private *tp = netdev_priv(dev);
1537         void __iomem *ioaddr = tp->mmio_addr;
1538         struct device *d = &tp->pci_dev->dev;
1539         struct rtl8169_counters *counters;
1540         dma_addr_t paddr;
1541         u32 cmd;
1542         int wait = 1000;
1543
1544         /*
1545          * Some chips are unable to dump tally counters when the receiver
1546          * is disabled.
1547          */
1548         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1549                 return;
1550
1551         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1552         if (!counters)
1553                 return;
1554
1555         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1556         cmd = (u64)paddr & DMA_BIT_MASK(32);
1557         RTL_W32(CounterAddrLow, cmd);
1558         RTL_W32(CounterAddrLow, cmd | CounterDump);
1559
1560         while (wait--) {
1561                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1562                         memcpy(&tp->counters, counters, sizeof(*counters));
1563                         break;
1564                 }
1565                 udelay(10);
1566         }
1567
1568         RTL_W32(CounterAddrLow, 0);
1569         RTL_W32(CounterAddrHigh, 0);
1570
1571         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1572 }
1573
1574 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1575                                       struct ethtool_stats *stats, u64 *data)
1576 {
1577         struct rtl8169_private *tp = netdev_priv(dev);
1578
1579         ASSERT_RTNL();
1580
1581         rtl8169_update_counters(dev);
1582
1583         data[0] = le64_to_cpu(tp->counters.tx_packets);
1584         data[1] = le64_to_cpu(tp->counters.rx_packets);
1585         data[2] = le64_to_cpu(tp->counters.tx_errors);
1586         data[3] = le32_to_cpu(tp->counters.rx_errors);
1587         data[4] = le16_to_cpu(tp->counters.rx_missed);
1588         data[5] = le16_to_cpu(tp->counters.align_errors);
1589         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1590         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1591         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1592         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1593         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1594         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1595         data[12] = le16_to_cpu(tp->counters.tx_underun);
1596 }
1597
1598 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1599 {
1600         switch(stringset) {
1601         case ETH_SS_STATS:
1602                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1603                 break;
1604         }
1605 }
1606
1607 static const struct ethtool_ops rtl8169_ethtool_ops = {
1608         .get_drvinfo            = rtl8169_get_drvinfo,
1609         .get_regs_len           = rtl8169_get_regs_len,
1610         .get_link               = ethtool_op_get_link,
1611         .get_settings           = rtl8169_get_settings,
1612         .set_settings           = rtl8169_set_settings,
1613         .get_msglevel           = rtl8169_get_msglevel,
1614         .set_msglevel           = rtl8169_set_msglevel,
1615         .get_regs               = rtl8169_get_regs,
1616         .get_wol                = rtl8169_get_wol,
1617         .set_wol                = rtl8169_set_wol,
1618         .get_strings            = rtl8169_get_strings,
1619         .get_sset_count         = rtl8169_get_sset_count,
1620         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1621 };
1622
1623 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1624                                     struct net_device *dev, u8 default_version)
1625 {
1626         void __iomem *ioaddr = tp->mmio_addr;
1627         /*
1628          * The driver currently handles the 8168Bf and the 8168Be identically
1629          * but they can be identified more specifically through the test below
1630          * if needed:
1631          *
1632          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1633          *
1634          * Same thing for the 8101Eb and the 8101Ec:
1635          *
1636          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1637          */
1638         static const struct {
1639                 u32 mask;
1640                 u32 val;
1641                 int mac_version;
1642         } mac_info[] = {
1643                 /* 8168E family. */
1644                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1645                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1646                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1647
1648                 /* 8168D family. */
1649                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1650                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1651                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1652
1653                 /* 8168DP family. */
1654                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1655                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1656                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1657
1658                 /* 8168C family. */
1659                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1660                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1661                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1662                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1663                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1664                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1665                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1666                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1667                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1668
1669                 /* 8168B family. */
1670                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1671                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1672                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1673                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1674
1675                 /* 8101 family. */
1676                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1677                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1678                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1679                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1680                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1681                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1682                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1683                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1684                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1685                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1686                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1687                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1688                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1689                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1690                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1691                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1692                 /* FIXME: where did these entries come from ? -- FR */
1693                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1694                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1695
1696                 /* 8110 family. */
1697                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1698                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1699                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1700                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1701                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1702                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1703
1704                 /* Catch-all */
1705                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1706         }, *p = mac_info;
1707         u32 reg;
1708
1709         reg = RTL_R32(TxConfig);
1710         while ((reg & p->mask) != p->val)
1711                 p++;
1712         tp->mac_version = p->mac_version;
1713
1714         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1715                 netif_notice(tp, probe, dev,
1716                              "unknown MAC, using family default\n");
1717                 tp->mac_version = default_version;
1718         }
1719 }
1720
1721 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1722 {
1723         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1724 }
1725
1726 struct phy_reg {
1727         u16 reg;
1728         u16 val;
1729 };
1730
1731 static void rtl_writephy_batch(struct rtl8169_private *tp,
1732                                const struct phy_reg *regs, int len)
1733 {
1734         while (len-- > 0) {
1735                 rtl_writephy(tp, regs->reg, regs->val);
1736                 regs++;
1737         }
1738 }
1739
1740 #define PHY_READ                0x00000000
1741 #define PHY_DATA_OR             0x10000000
1742 #define PHY_DATA_AND            0x20000000
1743 #define PHY_BJMPN               0x30000000
1744 #define PHY_READ_EFUSE          0x40000000
1745 #define PHY_READ_MAC_BYTE       0x50000000
1746 #define PHY_WRITE_MAC_BYTE      0x60000000
1747 #define PHY_CLEAR_READCOUNT     0x70000000
1748 #define PHY_WRITE               0x80000000
1749 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1750 #define PHY_COMP_EQ_SKIPN       0xa0000000
1751 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1752 #define PHY_WRITE_PREVIOUS      0xc0000000
1753 #define PHY_SKIPN               0xd0000000
1754 #define PHY_DELAY_MS            0xe0000000
1755 #define PHY_WRITE_ERI_WORD      0xf0000000
1756
1757 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1758
1759 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1760 {
1761         const struct firmware *fw = rtl_fw->fw;
1762         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1763         char *version = rtl_fw->version;
1764         bool rc = false;
1765
1766         if (fw->size < FW_OPCODE_SIZE)
1767                 goto out;
1768         else {
1769                 if (fw->size % FW_OPCODE_SIZE)
1770                         goto out;
1771
1772                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1773
1774                 pa->code = (__le32 *)fw->data;
1775                 pa->size = fw->size / FW_OPCODE_SIZE;
1776         }
1777         version[RTL_VER_SIZE - 1] = 0;
1778
1779         rc = true;
1780 out:
1781         return rc;
1782 }
1783
1784 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1785 {
1786         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1787         struct net_device *dev = tp->dev;
1788         u32 predata, count;
1789         size_t index;
1790
1791         if (!rtl_fw_format_ok(tp, rtl_fw)) {
1792                 netif_err(tp, probe, dev, "invalid firwmare\n");
1793                 return;
1794         }
1795
1796         for (index = 0; index < pa->size; index++) {
1797                 u32 action = le32_to_cpu(pa->code[index]);
1798                 u32 regno = (action & 0x0fff0000) >> 16;
1799
1800                 switch(action & 0xf0000000) {
1801                 case PHY_READ:
1802                 case PHY_DATA_OR:
1803                 case PHY_DATA_AND:
1804                 case PHY_READ_EFUSE:
1805                 case PHY_CLEAR_READCOUNT:
1806                 case PHY_WRITE:
1807                 case PHY_WRITE_PREVIOUS:
1808                 case PHY_DELAY_MS:
1809                         break;
1810
1811                 case PHY_BJMPN:
1812                         if (regno > index) {
1813                                 netif_err(tp, probe, tp->dev,
1814                                           "Out of range of firmware\n");
1815                                 return;
1816                         }
1817                         break;
1818                 case PHY_READCOUNT_EQ_SKIP:
1819                         if (index + 2 >= pa->size) {
1820                                 netif_err(tp, probe, tp->dev,
1821                                           "Out of range of firmware\n");
1822                                 return;
1823                         }
1824                         break;
1825                 case PHY_COMP_EQ_SKIPN:
1826                 case PHY_COMP_NEQ_SKIPN:
1827                 case PHY_SKIPN:
1828                         if (index + 1 + regno >= pa->size) {
1829                                 netif_err(tp, probe, tp->dev,
1830                                           "Out of range of firmware\n");
1831                                 return;
1832                         }
1833                         break;
1834
1835                 case PHY_READ_MAC_BYTE:
1836                 case PHY_WRITE_MAC_BYTE:
1837                 case PHY_WRITE_ERI_WORD:
1838                 default:
1839                         netif_err(tp, probe, tp->dev,
1840                                   "Invalid action 0x%08x\n", action);
1841                         return;
1842                 }
1843         }
1844
1845         predata = 0;
1846         count = 0;
1847
1848         for (index = 0; index < pa->size; ) {
1849                 u32 action = le32_to_cpu(pa->code[index]);
1850                 u32 data = action & 0x0000ffff;
1851                 u32 regno = (action & 0x0fff0000) >> 16;
1852
1853                 if (!action)
1854                         break;
1855
1856                 switch(action & 0xf0000000) {
1857                 case PHY_READ:
1858                         predata = rtl_readphy(tp, regno);
1859                         count++;
1860                         index++;
1861                         break;
1862                 case PHY_DATA_OR:
1863                         predata |= data;
1864                         index++;
1865                         break;
1866                 case PHY_DATA_AND:
1867                         predata &= data;
1868                         index++;
1869                         break;
1870                 case PHY_BJMPN:
1871                         index -= regno;
1872                         break;
1873                 case PHY_READ_EFUSE:
1874                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1875                         index++;
1876                         break;
1877                 case PHY_CLEAR_READCOUNT:
1878                         count = 0;
1879                         index++;
1880                         break;
1881                 case PHY_WRITE:
1882                         rtl_writephy(tp, regno, data);
1883                         index++;
1884                         break;
1885                 case PHY_READCOUNT_EQ_SKIP:
1886                         index += (count == data) ? 2 : 1;
1887                         break;
1888                 case PHY_COMP_EQ_SKIPN:
1889                         if (predata == data)
1890                                 index += regno;
1891                         index++;
1892                         break;
1893                 case PHY_COMP_NEQ_SKIPN:
1894                         if (predata != data)
1895                                 index += regno;
1896                         index++;
1897                         break;
1898                 case PHY_WRITE_PREVIOUS:
1899                         rtl_writephy(tp, regno, predata);
1900                         index++;
1901                         break;
1902                 case PHY_SKIPN:
1903                         index += regno + 1;
1904                         break;
1905                 case PHY_DELAY_MS:
1906                         mdelay(data);
1907                         index++;
1908                         break;
1909
1910                 case PHY_READ_MAC_BYTE:
1911                 case PHY_WRITE_MAC_BYTE:
1912                 case PHY_WRITE_ERI_WORD:
1913                 default:
1914                         BUG();
1915                 }
1916         }
1917 }
1918
1919 static void rtl_release_firmware(struct rtl8169_private *tp)
1920 {
1921         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
1922                 release_firmware(tp->rtl_fw->fw);
1923                 kfree(tp->rtl_fw);
1924         }
1925         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
1926 }
1927
1928 static void rtl_apply_firmware(struct rtl8169_private *tp)
1929 {
1930         struct rtl_fw *rtl_fw = tp->rtl_fw;
1931
1932         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1933         if (!IS_ERR_OR_NULL(rtl_fw))
1934                 rtl_phy_write_fw(tp, rtl_fw);
1935 }
1936
1937 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1938 {
1939         if (rtl_readphy(tp, reg) != val)
1940                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1941         else
1942                 rtl_apply_firmware(tp);
1943 }
1944
1945 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1946 {
1947         static const struct phy_reg phy_reg_init[] = {
1948                 { 0x1f, 0x0001 },
1949                 { 0x06, 0x006e },
1950                 { 0x08, 0x0708 },
1951                 { 0x15, 0x4000 },
1952                 { 0x18, 0x65c7 },
1953
1954                 { 0x1f, 0x0001 },
1955                 { 0x03, 0x00a1 },
1956                 { 0x02, 0x0008 },
1957                 { 0x01, 0x0120 },
1958                 { 0x00, 0x1000 },
1959                 { 0x04, 0x0800 },
1960                 { 0x04, 0x0000 },
1961
1962                 { 0x03, 0xff41 },
1963                 { 0x02, 0xdf60 },
1964                 { 0x01, 0x0140 },
1965                 { 0x00, 0x0077 },
1966                 { 0x04, 0x7800 },
1967                 { 0x04, 0x7000 },
1968
1969                 { 0x03, 0x802f },
1970                 { 0x02, 0x4f02 },
1971                 { 0x01, 0x0409 },
1972                 { 0x00, 0xf0f9 },
1973                 { 0x04, 0x9800 },
1974                 { 0x04, 0x9000 },
1975
1976                 { 0x03, 0xdf01 },
1977                 { 0x02, 0xdf20 },
1978                 { 0x01, 0xff95 },
1979                 { 0x00, 0xba00 },
1980                 { 0x04, 0xa800 },
1981                 { 0x04, 0xa000 },
1982
1983                 { 0x03, 0xff41 },
1984                 { 0x02, 0xdf20 },
1985                 { 0x01, 0x0140 },
1986                 { 0x00, 0x00bb },
1987                 { 0x04, 0xb800 },
1988                 { 0x04, 0xb000 },
1989
1990                 { 0x03, 0xdf41 },
1991                 { 0x02, 0xdc60 },
1992                 { 0x01, 0x6340 },
1993                 { 0x00, 0x007d },
1994                 { 0x04, 0xd800 },
1995                 { 0x04, 0xd000 },
1996
1997                 { 0x03, 0xdf01 },
1998                 { 0x02, 0xdf20 },
1999                 { 0x01, 0x100a },
2000                 { 0x00, 0xa0ff },
2001                 { 0x04, 0xf800 },
2002                 { 0x04, 0xf000 },
2003
2004                 { 0x1f, 0x0000 },
2005                 { 0x0b, 0x0000 },
2006                 { 0x00, 0x9200 }
2007         };
2008
2009         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2010 }
2011
2012 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2013 {
2014         static const struct phy_reg phy_reg_init[] = {
2015                 { 0x1f, 0x0002 },
2016                 { 0x01, 0x90d0 },
2017                 { 0x1f, 0x0000 }
2018         };
2019
2020         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2021 }
2022
2023 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2024 {
2025         struct pci_dev *pdev = tp->pci_dev;
2026         u16 vendor_id, device_id;
2027
2028         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2029         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2030
2031         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2032                 return;
2033
2034         rtl_writephy(tp, 0x1f, 0x0001);
2035         rtl_writephy(tp, 0x10, 0xf01b);
2036         rtl_writephy(tp, 0x1f, 0x0000);
2037 }
2038
2039 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2040 {
2041         static const struct phy_reg phy_reg_init[] = {
2042                 { 0x1f, 0x0001 },
2043                 { 0x04, 0x0000 },
2044                 { 0x03, 0x00a1 },
2045                 { 0x02, 0x0008 },
2046                 { 0x01, 0x0120 },
2047                 { 0x00, 0x1000 },
2048                 { 0x04, 0x0800 },
2049                 { 0x04, 0x9000 },
2050                 { 0x03, 0x802f },
2051                 { 0x02, 0x4f02 },
2052                 { 0x01, 0x0409 },
2053                 { 0x00, 0xf099 },
2054                 { 0x04, 0x9800 },
2055                 { 0x04, 0xa000 },
2056                 { 0x03, 0xdf01 },
2057                 { 0x02, 0xdf20 },
2058                 { 0x01, 0xff95 },
2059                 { 0x00, 0xba00 },
2060                 { 0x04, 0xa800 },
2061                 { 0x04, 0xf000 },
2062                 { 0x03, 0xdf01 },
2063                 { 0x02, 0xdf20 },
2064                 { 0x01, 0x101a },
2065                 { 0x00, 0xa0ff },
2066                 { 0x04, 0xf800 },
2067                 { 0x04, 0x0000 },
2068                 { 0x1f, 0x0000 },
2069
2070                 { 0x1f, 0x0001 },
2071                 { 0x10, 0xf41b },
2072                 { 0x14, 0xfb54 },
2073                 { 0x18, 0xf5c7 },
2074                 { 0x1f, 0x0000 },
2075
2076                 { 0x1f, 0x0001 },
2077                 { 0x17, 0x0cc0 },
2078                 { 0x1f, 0x0000 }
2079         };
2080
2081         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2082
2083         rtl8169scd_hw_phy_config_quirk(tp);
2084 }
2085
2086 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2087 {
2088         static const struct phy_reg phy_reg_init[] = {
2089                 { 0x1f, 0x0001 },
2090                 { 0x04, 0x0000 },
2091                 { 0x03, 0x00a1 },
2092                 { 0x02, 0x0008 },
2093                 { 0x01, 0x0120 },
2094                 { 0x00, 0x1000 },
2095                 { 0x04, 0x0800 },
2096                 { 0x04, 0x9000 },
2097                 { 0x03, 0x802f },
2098                 { 0x02, 0x4f02 },
2099                 { 0x01, 0x0409 },
2100                 { 0x00, 0xf099 },
2101                 { 0x04, 0x9800 },
2102                 { 0x04, 0xa000 },
2103                 { 0x03, 0xdf01 },
2104                 { 0x02, 0xdf20 },
2105                 { 0x01, 0xff95 },
2106                 { 0x00, 0xba00 },
2107                 { 0x04, 0xa800 },
2108                 { 0x04, 0xf000 },
2109                 { 0x03, 0xdf01 },
2110                 { 0x02, 0xdf20 },
2111                 { 0x01, 0x101a },
2112                 { 0x00, 0xa0ff },
2113                 { 0x04, 0xf800 },
2114                 { 0x04, 0x0000 },
2115                 { 0x1f, 0x0000 },
2116
2117                 { 0x1f, 0x0001 },
2118                 { 0x0b, 0x8480 },
2119                 { 0x1f, 0x0000 },
2120
2121                 { 0x1f, 0x0001 },
2122                 { 0x18, 0x67c7 },
2123                 { 0x04, 0x2000 },
2124                 { 0x03, 0x002f },
2125                 { 0x02, 0x4360 },
2126                 { 0x01, 0x0109 },
2127                 { 0x00, 0x3022 },
2128                 { 0x04, 0x2800 },
2129                 { 0x1f, 0x0000 },
2130
2131                 { 0x1f, 0x0001 },
2132                 { 0x17, 0x0cc0 },
2133                 { 0x1f, 0x0000 }
2134         };
2135
2136         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2137 }
2138
2139 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2140 {
2141         static const struct phy_reg phy_reg_init[] = {
2142                 { 0x10, 0xf41b },
2143                 { 0x1f, 0x0000 }
2144         };
2145
2146         rtl_writephy(tp, 0x1f, 0x0001);
2147         rtl_patchphy(tp, 0x16, 1 << 0);
2148
2149         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2150 }
2151
2152 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2153 {
2154         static const struct phy_reg phy_reg_init[] = {
2155                 { 0x1f, 0x0001 },
2156                 { 0x10, 0xf41b },
2157                 { 0x1f, 0x0000 }
2158         };
2159
2160         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2161 }
2162
2163 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2164 {
2165         static const struct phy_reg phy_reg_init[] = {
2166                 { 0x1f, 0x0000 },
2167                 { 0x1d, 0x0f00 },
2168                 { 0x1f, 0x0002 },
2169                 { 0x0c, 0x1ec8 },
2170                 { 0x1f, 0x0000 }
2171         };
2172
2173         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2174 }
2175
2176 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2177 {
2178         static const struct phy_reg phy_reg_init[] = {
2179                 { 0x1f, 0x0001 },
2180                 { 0x1d, 0x3d98 },
2181                 { 0x1f, 0x0000 }
2182         };
2183
2184         rtl_writephy(tp, 0x1f, 0x0000);
2185         rtl_patchphy(tp, 0x14, 1 << 5);
2186         rtl_patchphy(tp, 0x0d, 1 << 5);
2187
2188         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2189 }
2190
2191 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2192 {
2193         static const struct phy_reg phy_reg_init[] = {
2194                 { 0x1f, 0x0001 },
2195                 { 0x12, 0x2300 },
2196                 { 0x1f, 0x0002 },
2197                 { 0x00, 0x88d4 },
2198                 { 0x01, 0x82b1 },
2199                 { 0x03, 0x7002 },
2200                 { 0x08, 0x9e30 },
2201                 { 0x09, 0x01f0 },
2202                 { 0x0a, 0x5500 },
2203                 { 0x0c, 0x00c8 },
2204                 { 0x1f, 0x0003 },
2205                 { 0x12, 0xc096 },
2206                 { 0x16, 0x000a },
2207                 { 0x1f, 0x0000 },
2208                 { 0x1f, 0x0000 },
2209                 { 0x09, 0x2000 },
2210                 { 0x09, 0x0000 }
2211         };
2212
2213         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2214
2215         rtl_patchphy(tp, 0x14, 1 << 5);
2216         rtl_patchphy(tp, 0x0d, 1 << 5);
2217         rtl_writephy(tp, 0x1f, 0x0000);
2218 }
2219
2220 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2221 {
2222         static const struct phy_reg phy_reg_init[] = {
2223                 { 0x1f, 0x0001 },
2224                 { 0x12, 0x2300 },
2225                 { 0x03, 0x802f },
2226                 { 0x02, 0x4f02 },
2227                 { 0x01, 0x0409 },
2228                 { 0x00, 0xf099 },
2229                 { 0x04, 0x9800 },
2230                 { 0x04, 0x9000 },
2231                 { 0x1d, 0x3d98 },
2232                 { 0x1f, 0x0002 },
2233                 { 0x0c, 0x7eb8 },
2234                 { 0x06, 0x0761 },
2235                 { 0x1f, 0x0003 },
2236                 { 0x16, 0x0f0a },
2237                 { 0x1f, 0x0000 }
2238         };
2239
2240         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2241
2242         rtl_patchphy(tp, 0x16, 1 << 0);
2243         rtl_patchphy(tp, 0x14, 1 << 5);
2244         rtl_patchphy(tp, 0x0d, 1 << 5);
2245         rtl_writephy(tp, 0x1f, 0x0000);
2246 }
2247
2248 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2249 {
2250         static const struct phy_reg phy_reg_init[] = {
2251                 { 0x1f, 0x0001 },
2252                 { 0x12, 0x2300 },
2253                 { 0x1d, 0x3d98 },
2254                 { 0x1f, 0x0002 },
2255                 { 0x0c, 0x7eb8 },
2256                 { 0x06, 0x5461 },
2257                 { 0x1f, 0x0003 },
2258                 { 0x16, 0x0f0a },
2259                 { 0x1f, 0x0000 }
2260         };
2261
2262         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2263
2264         rtl_patchphy(tp, 0x16, 1 << 0);
2265         rtl_patchphy(tp, 0x14, 1 << 5);
2266         rtl_patchphy(tp, 0x0d, 1 << 5);
2267         rtl_writephy(tp, 0x1f, 0x0000);
2268 }
2269
2270 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2271 {
2272         rtl8168c_3_hw_phy_config(tp);
2273 }
2274
2275 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2276 {
2277         static const struct phy_reg phy_reg_init_0[] = {
2278                 /* Channel Estimation */
2279                 { 0x1f, 0x0001 },
2280                 { 0x06, 0x4064 },
2281                 { 0x07, 0x2863 },
2282                 { 0x08, 0x059c },
2283                 { 0x09, 0x26b4 },
2284                 { 0x0a, 0x6a19 },
2285                 { 0x0b, 0xdcc8 },
2286                 { 0x10, 0xf06d },
2287                 { 0x14, 0x7f68 },
2288                 { 0x18, 0x7fd9 },
2289                 { 0x1c, 0xf0ff },
2290                 { 0x1d, 0x3d9c },
2291                 { 0x1f, 0x0003 },
2292                 { 0x12, 0xf49f },
2293                 { 0x13, 0x070b },
2294                 { 0x1a, 0x05ad },
2295                 { 0x14, 0x94c0 },
2296
2297                 /*
2298                  * Tx Error Issue
2299                  * Enhance line driver power
2300                  */
2301                 { 0x1f, 0x0002 },
2302                 { 0x06, 0x5561 },
2303                 { 0x1f, 0x0005 },
2304                 { 0x05, 0x8332 },
2305                 { 0x06, 0x5561 },
2306
2307                 /*
2308                  * Can not link to 1Gbps with bad cable
2309                  * Decrease SNR threshold form 21.07dB to 19.04dB
2310                  */
2311                 { 0x1f, 0x0001 },
2312                 { 0x17, 0x0cc0 },
2313
2314                 { 0x1f, 0x0000 },
2315                 { 0x0d, 0xf880 }
2316         };
2317         void __iomem *ioaddr = tp->mmio_addr;
2318
2319         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2320
2321         /*
2322          * Rx Error Issue
2323          * Fine Tune Switching regulator parameter
2324          */
2325         rtl_writephy(tp, 0x1f, 0x0002);
2326         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2327         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2328
2329         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2330                 static const struct phy_reg phy_reg_init[] = {
2331                         { 0x1f, 0x0002 },
2332                         { 0x05, 0x669a },
2333                         { 0x1f, 0x0005 },
2334                         { 0x05, 0x8330 },
2335                         { 0x06, 0x669a },
2336                         { 0x1f, 0x0002 }
2337                 };
2338                 int val;
2339
2340                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2341
2342                 val = rtl_readphy(tp, 0x0d);
2343
2344                 if ((val & 0x00ff) != 0x006c) {
2345                         static const u32 set[] = {
2346                                 0x0065, 0x0066, 0x0067, 0x0068,
2347                                 0x0069, 0x006a, 0x006b, 0x006c
2348                         };
2349                         int i;
2350
2351                         rtl_writephy(tp, 0x1f, 0x0002);
2352
2353                         val &= 0xff00;
2354                         for (i = 0; i < ARRAY_SIZE(set); i++)
2355                                 rtl_writephy(tp, 0x0d, val | set[i]);
2356                 }
2357         } else {
2358                 static const struct phy_reg phy_reg_init[] = {
2359                         { 0x1f, 0x0002 },
2360                         { 0x05, 0x6662 },
2361                         { 0x1f, 0x0005 },
2362                         { 0x05, 0x8330 },
2363                         { 0x06, 0x6662 }
2364                 };
2365
2366                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2367         }
2368
2369         /* RSET couple improve */
2370         rtl_writephy(tp, 0x1f, 0x0002);
2371         rtl_patchphy(tp, 0x0d, 0x0300);
2372         rtl_patchphy(tp, 0x0f, 0x0010);
2373
2374         /* Fine tune PLL performance */
2375         rtl_writephy(tp, 0x1f, 0x0002);
2376         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2377         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2378
2379         rtl_writephy(tp, 0x1f, 0x0005);
2380         rtl_writephy(tp, 0x05, 0x001b);
2381
2382         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2383
2384         rtl_writephy(tp, 0x1f, 0x0000);
2385 }
2386
2387 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2388 {
2389         static const struct phy_reg phy_reg_init_0[] = {
2390                 /* Channel Estimation */
2391                 { 0x1f, 0x0001 },
2392                 { 0x06, 0x4064 },
2393                 { 0x07, 0x2863 },
2394                 { 0x08, 0x059c },
2395                 { 0x09, 0x26b4 },
2396                 { 0x0a, 0x6a19 },
2397                 { 0x0b, 0xdcc8 },
2398                 { 0x10, 0xf06d },
2399                 { 0x14, 0x7f68 },
2400                 { 0x18, 0x7fd9 },
2401                 { 0x1c, 0xf0ff },
2402                 { 0x1d, 0x3d9c },
2403                 { 0x1f, 0x0003 },
2404                 { 0x12, 0xf49f },
2405                 { 0x13, 0x070b },
2406                 { 0x1a, 0x05ad },
2407                 { 0x14, 0x94c0 },
2408
2409                 /*
2410                  * Tx Error Issue
2411                  * Enhance line driver power
2412                  */
2413                 { 0x1f, 0x0002 },
2414                 { 0x06, 0x5561 },
2415                 { 0x1f, 0x0005 },
2416                 { 0x05, 0x8332 },
2417                 { 0x06, 0x5561 },
2418
2419                 /*
2420                  * Can not link to 1Gbps with bad cable
2421                  * Decrease SNR threshold form 21.07dB to 19.04dB
2422                  */
2423                 { 0x1f, 0x0001 },
2424                 { 0x17, 0x0cc0 },
2425
2426                 { 0x1f, 0x0000 },
2427                 { 0x0d, 0xf880 }
2428         };
2429         void __iomem *ioaddr = tp->mmio_addr;
2430
2431         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2432
2433         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2434                 static const struct phy_reg phy_reg_init[] = {
2435                         { 0x1f, 0x0002 },
2436                         { 0x05, 0x669a },
2437                         { 0x1f, 0x0005 },
2438                         { 0x05, 0x8330 },
2439                         { 0x06, 0x669a },
2440
2441                         { 0x1f, 0x0002 }
2442                 };
2443                 int val;
2444
2445                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2446
2447                 val = rtl_readphy(tp, 0x0d);
2448                 if ((val & 0x00ff) != 0x006c) {
2449                         static const u32 set[] = {
2450                                 0x0065, 0x0066, 0x0067, 0x0068,
2451                                 0x0069, 0x006a, 0x006b, 0x006c
2452                         };
2453                         int i;
2454
2455                         rtl_writephy(tp, 0x1f, 0x0002);
2456
2457                         val &= 0xff00;
2458                         for (i = 0; i < ARRAY_SIZE(set); i++)
2459                                 rtl_writephy(tp, 0x0d, val | set[i]);
2460                 }
2461         } else {
2462                 static const struct phy_reg phy_reg_init[] = {
2463                         { 0x1f, 0x0002 },
2464                         { 0x05, 0x2642 },
2465                         { 0x1f, 0x0005 },
2466                         { 0x05, 0x8330 },
2467                         { 0x06, 0x2642 }
2468                 };
2469
2470                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2471         }
2472
2473         /* Fine tune PLL performance */
2474         rtl_writephy(tp, 0x1f, 0x0002);
2475         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2476         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2477
2478         /* Switching regulator Slew rate */
2479         rtl_writephy(tp, 0x1f, 0x0002);
2480         rtl_patchphy(tp, 0x0f, 0x0017);
2481
2482         rtl_writephy(tp, 0x1f, 0x0005);
2483         rtl_writephy(tp, 0x05, 0x001b);
2484
2485         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2486
2487         rtl_writephy(tp, 0x1f, 0x0000);
2488 }
2489
2490 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2491 {
2492         static const struct phy_reg phy_reg_init[] = {
2493                 { 0x1f, 0x0002 },
2494                 { 0x10, 0x0008 },
2495                 { 0x0d, 0x006c },
2496
2497                 { 0x1f, 0x0000 },
2498                 { 0x0d, 0xf880 },
2499
2500                 { 0x1f, 0x0001 },
2501                 { 0x17, 0x0cc0 },
2502
2503                 { 0x1f, 0x0001 },
2504                 { 0x0b, 0xa4d8 },
2505                 { 0x09, 0x281c },
2506                 { 0x07, 0x2883 },
2507                 { 0x0a, 0x6b35 },
2508                 { 0x1d, 0x3da4 },
2509                 { 0x1c, 0xeffd },
2510                 { 0x14, 0x7f52 },
2511                 { 0x18, 0x7fc6 },
2512                 { 0x08, 0x0601 },
2513                 { 0x06, 0x4063 },
2514                 { 0x10, 0xf074 },
2515                 { 0x1f, 0x0003 },
2516                 { 0x13, 0x0789 },
2517                 { 0x12, 0xf4bd },
2518                 { 0x1a, 0x04fd },
2519                 { 0x14, 0x84b0 },
2520                 { 0x1f, 0x0000 },
2521                 { 0x00, 0x9200 },
2522
2523                 { 0x1f, 0x0005 },
2524                 { 0x01, 0x0340 },
2525                 { 0x1f, 0x0001 },
2526                 { 0x04, 0x4000 },
2527                 { 0x03, 0x1d21 },
2528                 { 0x02, 0x0c32 },
2529                 { 0x01, 0x0200 },
2530                 { 0x00, 0x5554 },
2531                 { 0x04, 0x4800 },
2532                 { 0x04, 0x4000 },
2533                 { 0x04, 0xf000 },
2534                 { 0x03, 0xdf01 },
2535                 { 0x02, 0xdf20 },
2536                 { 0x01, 0x101a },
2537                 { 0x00, 0xa0ff },
2538                 { 0x04, 0xf800 },
2539                 { 0x04, 0xf000 },
2540                 { 0x1f, 0x0000 },
2541
2542                 { 0x1f, 0x0007 },
2543                 { 0x1e, 0x0023 },
2544                 { 0x16, 0x0000 },
2545                 { 0x1f, 0x0000 }
2546         };
2547
2548         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2549 }
2550
2551 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2552 {
2553         static const struct phy_reg phy_reg_init[] = {
2554                 { 0x1f, 0x0001 },
2555                 { 0x17, 0x0cc0 },
2556
2557                 { 0x1f, 0x0007 },
2558                 { 0x1e, 0x002d },
2559                 { 0x18, 0x0040 },
2560                 { 0x1f, 0x0000 }
2561         };
2562
2563         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2564         rtl_patchphy(tp, 0x0d, 1 << 5);
2565 }
2566
2567 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2568 {
2569         static const struct phy_reg phy_reg_init[] = {
2570                 /* Enable Delay cap */
2571                 { 0x1f, 0x0005 },
2572                 { 0x05, 0x8b80 },
2573                 { 0x06, 0xc896 },
2574                 { 0x1f, 0x0000 },
2575
2576                 /* Channel estimation fine tune */
2577                 { 0x1f, 0x0001 },
2578                 { 0x0b, 0x6c20 },
2579                 { 0x07, 0x2872 },
2580                 { 0x1c, 0xefff },
2581                 { 0x1f, 0x0003 },
2582                 { 0x14, 0x6420 },
2583                 { 0x1f, 0x0000 },
2584
2585                 /* Update PFM & 10M TX idle timer */
2586                 { 0x1f, 0x0007 },
2587                 { 0x1e, 0x002f },
2588                 { 0x15, 0x1919 },
2589                 { 0x1f, 0x0000 },
2590
2591                 { 0x1f, 0x0007 },
2592                 { 0x1e, 0x00ac },
2593                 { 0x18, 0x0006 },
2594                 { 0x1f, 0x0000 }
2595         };
2596
2597         rtl_apply_firmware(tp);
2598
2599         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2600
2601         /* DCO enable for 10M IDLE Power */
2602         rtl_writephy(tp, 0x1f, 0x0007);
2603         rtl_writephy(tp, 0x1e, 0x0023);
2604         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2605         rtl_writephy(tp, 0x1f, 0x0000);
2606
2607         /* For impedance matching */
2608         rtl_writephy(tp, 0x1f, 0x0002);
2609         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2610         rtl_writephy(tp, 0x1f, 0x0000);
2611
2612         /* PHY auto speed down */
2613         rtl_writephy(tp, 0x1f, 0x0007);
2614         rtl_writephy(tp, 0x1e, 0x002d);
2615         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2616         rtl_writephy(tp, 0x1f, 0x0000);
2617         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2618
2619         rtl_writephy(tp, 0x1f, 0x0005);
2620         rtl_writephy(tp, 0x05, 0x8b86);
2621         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2622         rtl_writephy(tp, 0x1f, 0x0000);
2623
2624         rtl_writephy(tp, 0x1f, 0x0005);
2625         rtl_writephy(tp, 0x05, 0x8b85);
2626         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2627         rtl_writephy(tp, 0x1f, 0x0007);
2628         rtl_writephy(tp, 0x1e, 0x0020);
2629         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2630         rtl_writephy(tp, 0x1f, 0x0006);
2631         rtl_writephy(tp, 0x00, 0x5a00);
2632         rtl_writephy(tp, 0x1f, 0x0000);
2633         rtl_writephy(tp, 0x0d, 0x0007);
2634         rtl_writephy(tp, 0x0e, 0x003c);
2635         rtl_writephy(tp, 0x0d, 0x4007);
2636         rtl_writephy(tp, 0x0e, 0x0000);
2637         rtl_writephy(tp, 0x0d, 0x0000);
2638 }
2639
2640 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2641 {
2642         static const struct phy_reg phy_reg_init[] = {
2643                 { 0x1f, 0x0003 },
2644                 { 0x08, 0x441d },
2645                 { 0x01, 0x9100 },
2646                 { 0x1f, 0x0000 }
2647         };
2648
2649         rtl_writephy(tp, 0x1f, 0x0000);
2650         rtl_patchphy(tp, 0x11, 1 << 12);
2651         rtl_patchphy(tp, 0x19, 1 << 13);
2652         rtl_patchphy(tp, 0x10, 1 << 15);
2653
2654         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2655 }
2656
2657 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2658 {
2659         static const struct phy_reg phy_reg_init[] = {
2660                 { 0x1f, 0x0005 },
2661                 { 0x1a, 0x0000 },
2662                 { 0x1f, 0x0000 },
2663
2664                 { 0x1f, 0x0004 },
2665                 { 0x1c, 0x0000 },
2666                 { 0x1f, 0x0000 },
2667
2668                 { 0x1f, 0x0001 },
2669                 { 0x15, 0x7701 },
2670                 { 0x1f, 0x0000 }
2671         };
2672
2673         /* Disable ALDPS before ram code */
2674         rtl_writephy(tp, 0x1f, 0x0000);
2675         rtl_writephy(tp, 0x18, 0x0310);
2676         msleep(100);
2677
2678         rtl_apply_firmware(tp);
2679
2680         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2681 }
2682
2683 static void rtl_hw_phy_config(struct net_device *dev)
2684 {
2685         struct rtl8169_private *tp = netdev_priv(dev);
2686
2687         rtl8169_print_mac_version(tp);
2688
2689         switch (tp->mac_version) {
2690         case RTL_GIGA_MAC_VER_01:
2691                 break;
2692         case RTL_GIGA_MAC_VER_02:
2693         case RTL_GIGA_MAC_VER_03:
2694                 rtl8169s_hw_phy_config(tp);
2695                 break;
2696         case RTL_GIGA_MAC_VER_04:
2697                 rtl8169sb_hw_phy_config(tp);
2698                 break;
2699         case RTL_GIGA_MAC_VER_05:
2700                 rtl8169scd_hw_phy_config(tp);
2701                 break;
2702         case RTL_GIGA_MAC_VER_06:
2703                 rtl8169sce_hw_phy_config(tp);
2704                 break;
2705         case RTL_GIGA_MAC_VER_07:
2706         case RTL_GIGA_MAC_VER_08:
2707         case RTL_GIGA_MAC_VER_09:
2708                 rtl8102e_hw_phy_config(tp);
2709                 break;
2710         case RTL_GIGA_MAC_VER_11:
2711                 rtl8168bb_hw_phy_config(tp);
2712                 break;
2713         case RTL_GIGA_MAC_VER_12:
2714                 rtl8168bef_hw_phy_config(tp);
2715                 break;
2716         case RTL_GIGA_MAC_VER_17:
2717                 rtl8168bef_hw_phy_config(tp);
2718                 break;
2719         case RTL_GIGA_MAC_VER_18:
2720                 rtl8168cp_1_hw_phy_config(tp);
2721                 break;
2722         case RTL_GIGA_MAC_VER_19:
2723                 rtl8168c_1_hw_phy_config(tp);
2724                 break;
2725         case RTL_GIGA_MAC_VER_20:
2726                 rtl8168c_2_hw_phy_config(tp);
2727                 break;
2728         case RTL_GIGA_MAC_VER_21:
2729                 rtl8168c_3_hw_phy_config(tp);
2730                 break;
2731         case RTL_GIGA_MAC_VER_22:
2732                 rtl8168c_4_hw_phy_config(tp);
2733                 break;
2734         case RTL_GIGA_MAC_VER_23:
2735         case RTL_GIGA_MAC_VER_24:
2736                 rtl8168cp_2_hw_phy_config(tp);
2737                 break;
2738         case RTL_GIGA_MAC_VER_25:
2739                 rtl8168d_1_hw_phy_config(tp);
2740                 break;
2741         case RTL_GIGA_MAC_VER_26:
2742                 rtl8168d_2_hw_phy_config(tp);
2743                 break;
2744         case RTL_GIGA_MAC_VER_27:
2745                 rtl8168d_3_hw_phy_config(tp);
2746                 break;
2747         case RTL_GIGA_MAC_VER_28:
2748                 rtl8168d_4_hw_phy_config(tp);
2749                 break;
2750         case RTL_GIGA_MAC_VER_29:
2751         case RTL_GIGA_MAC_VER_30:
2752                 rtl8105e_hw_phy_config(tp);
2753                 break;
2754         case RTL_GIGA_MAC_VER_31:
2755                 /* None. */
2756                 break;
2757         case RTL_GIGA_MAC_VER_32:
2758         case RTL_GIGA_MAC_VER_33:
2759                 rtl8168e_hw_phy_config(tp);
2760                 break;
2761
2762         default:
2763                 break;
2764         }
2765 }
2766
2767 static void rtl8169_phy_timer(unsigned long __opaque)
2768 {
2769         struct net_device *dev = (struct net_device *)__opaque;
2770         struct rtl8169_private *tp = netdev_priv(dev);
2771         struct timer_list *timer = &tp->timer;
2772         void __iomem *ioaddr = tp->mmio_addr;
2773         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2774
2775         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2776
2777         spin_lock_irq(&tp->lock);
2778
2779         if (tp->phy_reset_pending(tp)) {
2780                 /*
2781                  * A busy loop could burn quite a few cycles on nowadays CPU.
2782                  * Let's delay the execution of the timer for a few ticks.
2783                  */
2784                 timeout = HZ/10;
2785                 goto out_mod_timer;
2786         }
2787
2788         if (tp->link_ok(ioaddr))
2789                 goto out_unlock;
2790
2791         netif_warn(tp, link, dev, "PHY reset until link up\n");
2792
2793         tp->phy_reset_enable(tp);
2794
2795 out_mod_timer:
2796         mod_timer(timer, jiffies + timeout);
2797 out_unlock:
2798         spin_unlock_irq(&tp->lock);
2799 }
2800
2801 #ifdef CONFIG_NET_POLL_CONTROLLER
2802 /*
2803  * Polling 'interrupt' - used by things like netconsole to send skbs
2804  * without having to re-enable interrupts. It's not called while
2805  * the interrupt routine is executing.
2806  */
2807 static void rtl8169_netpoll(struct net_device *dev)
2808 {
2809         struct rtl8169_private *tp = netdev_priv(dev);
2810         struct pci_dev *pdev = tp->pci_dev;
2811
2812         disable_irq(pdev->irq);
2813         rtl8169_interrupt(pdev->irq, dev);
2814         enable_irq(pdev->irq);
2815 }
2816 #endif
2817
2818 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2819                                   void __iomem *ioaddr)
2820 {
2821         iounmap(ioaddr);
2822         pci_release_regions(pdev);
2823         pci_clear_mwi(pdev);
2824         pci_disable_device(pdev);
2825         free_netdev(dev);
2826 }
2827
2828 static void rtl8169_phy_reset(struct net_device *dev,
2829                               struct rtl8169_private *tp)
2830 {
2831         unsigned int i;
2832
2833         tp->phy_reset_enable(tp);
2834         for (i = 0; i < 100; i++) {
2835                 if (!tp->phy_reset_pending(tp))
2836                         return;
2837                 msleep(1);
2838         }
2839         netif_err(tp, link, dev, "PHY reset failed\n");
2840 }
2841
2842 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2843 {
2844         void __iomem *ioaddr = tp->mmio_addr;
2845
2846         rtl_hw_phy_config(dev);
2847
2848         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2849                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2850                 RTL_W8(0x82, 0x01);
2851         }
2852
2853         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2854
2855         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2856                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2857
2858         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2859                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2860                 RTL_W8(0x82, 0x01);
2861                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2862                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2863         }
2864
2865         rtl8169_phy_reset(dev, tp);
2866
2867         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2868                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2869                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2870                           (tp->mii.supports_gmii ?
2871                            ADVERTISED_1000baseT_Half |
2872                            ADVERTISED_1000baseT_Full : 0));
2873
2874         if (RTL_R8(PHYstatus) & TBI_Enable)
2875                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2876 }
2877
2878 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2879 {
2880         void __iomem *ioaddr = tp->mmio_addr;
2881         u32 high;
2882         u32 low;
2883
2884         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2885         high = addr[4] | (addr[5] << 8);
2886
2887         spin_lock_irq(&tp->lock);
2888
2889         RTL_W8(Cfg9346, Cfg9346_Unlock);
2890
2891         RTL_W32(MAC4, high);
2892         RTL_R32(MAC4);
2893
2894         RTL_W32(MAC0, low);
2895         RTL_R32(MAC0);
2896
2897         RTL_W8(Cfg9346, Cfg9346_Lock);
2898
2899         spin_unlock_irq(&tp->lock);
2900 }
2901
2902 static int rtl_set_mac_address(struct net_device *dev, void *p)
2903 {
2904         struct rtl8169_private *tp = netdev_priv(dev);
2905         struct sockaddr *addr = p;
2906
2907         if (!is_valid_ether_addr(addr->sa_data))
2908                 return -EADDRNOTAVAIL;
2909
2910         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2911
2912         rtl_rar_set(tp, dev->dev_addr);
2913
2914         return 0;
2915 }
2916
2917 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2918 {
2919         struct rtl8169_private *tp = netdev_priv(dev);
2920         struct mii_ioctl_data *data = if_mii(ifr);
2921
2922         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2923 }
2924
2925 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2926                           struct mii_ioctl_data *data, int cmd)
2927 {
2928         switch (cmd) {
2929         case SIOCGMIIPHY:
2930                 data->phy_id = 32; /* Internal PHY */
2931                 return 0;
2932
2933         case SIOCGMIIREG:
2934                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2935                 return 0;
2936
2937         case SIOCSMIIREG:
2938                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2939                 return 0;
2940         }
2941         return -EOPNOTSUPP;
2942 }
2943
2944 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2945 {
2946         return -EOPNOTSUPP;
2947 }
2948
2949 static const struct rtl_cfg_info {
2950         void (*hw_start)(struct net_device *);
2951         unsigned int region;
2952         unsigned int align;
2953         u16 intr_event;
2954         u16 napi_event;
2955         unsigned features;
2956         u8 default_ver;
2957 } rtl_cfg_infos [] = {
2958         [RTL_CFG_0] = {
2959                 .hw_start       = rtl_hw_start_8169,
2960                 .region         = 1,
2961                 .align          = 0,
2962                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2963                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2964                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2965                 .features       = RTL_FEATURE_GMII,
2966                 .default_ver    = RTL_GIGA_MAC_VER_01,
2967         },
2968         [RTL_CFG_1] = {
2969                 .hw_start       = rtl_hw_start_8168,
2970                 .region         = 2,
2971                 .align          = 8,
2972                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2973                                   TxErr | TxOK | RxOK | RxErr,
2974                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2975                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2976                 .default_ver    = RTL_GIGA_MAC_VER_11,
2977         },
2978         [RTL_CFG_2] = {
2979                 .hw_start       = rtl_hw_start_8101,
2980                 .region         = 2,
2981                 .align          = 8,
2982                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2983                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2984                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2985                 .features       = RTL_FEATURE_MSI,
2986                 .default_ver    = RTL_GIGA_MAC_VER_13,
2987         }
2988 };
2989
2990 /* Cfg9346_Unlock assumed. */
2991 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2992                             const struct rtl_cfg_info *cfg)
2993 {
2994         unsigned msi = 0;
2995         u8 cfg2;
2996
2997         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2998         if (cfg->features & RTL_FEATURE_MSI) {
2999                 if (pci_enable_msi(pdev)) {
3000                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3001                 } else {
3002                         cfg2 |= MSIEnable;
3003                         msi = RTL_FEATURE_MSI;
3004                 }
3005         }
3006         RTL_W8(Config2, cfg2);
3007         return msi;
3008 }
3009
3010 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3011 {
3012         if (tp->features & RTL_FEATURE_MSI) {
3013                 pci_disable_msi(pdev);
3014                 tp->features &= ~RTL_FEATURE_MSI;
3015         }
3016 }
3017
3018 static const struct net_device_ops rtl8169_netdev_ops = {
3019         .ndo_open               = rtl8169_open,
3020         .ndo_stop               = rtl8169_close,
3021         .ndo_get_stats          = rtl8169_get_stats,
3022         .ndo_start_xmit         = rtl8169_start_xmit,
3023         .ndo_tx_timeout         = rtl8169_tx_timeout,
3024         .ndo_validate_addr      = eth_validate_addr,
3025         .ndo_change_mtu         = rtl8169_change_mtu,
3026         .ndo_fix_features       = rtl8169_fix_features,
3027         .ndo_set_features       = rtl8169_set_features,
3028         .ndo_set_mac_address    = rtl_set_mac_address,
3029         .ndo_do_ioctl           = rtl8169_ioctl,
3030         .ndo_set_multicast_list = rtl_set_rx_mode,
3031 #ifdef CONFIG_NET_POLL_CONTROLLER
3032         .ndo_poll_controller    = rtl8169_netpoll,
3033 #endif
3034
3035 };
3036
3037 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3038 {
3039         struct mdio_ops *ops = &tp->mdio_ops;
3040
3041         switch (tp->mac_version) {
3042         case RTL_GIGA_MAC_VER_27:
3043                 ops->write      = r8168dp_1_mdio_write;
3044                 ops->read       = r8168dp_1_mdio_read;
3045                 break;
3046         case RTL_GIGA_MAC_VER_28:
3047         case RTL_GIGA_MAC_VER_31:
3048                 ops->write      = r8168dp_2_mdio_write;
3049                 ops->read       = r8168dp_2_mdio_read;
3050                 break;
3051         default:
3052                 ops->write      = r8169_mdio_write;
3053                 ops->read       = r8169_mdio_read;
3054                 break;
3055         }
3056 }
3057
3058 static void r810x_phy_power_down(struct rtl8169_private *tp)
3059 {
3060         rtl_writephy(tp, 0x1f, 0x0000);
3061         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3062 }
3063
3064 static void r810x_phy_power_up(struct rtl8169_private *tp)
3065 {
3066         rtl_writephy(tp, 0x1f, 0x0000);
3067         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3068 }
3069
3070 static void r810x_pll_power_down(struct rtl8169_private *tp)
3071 {
3072         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3073                 rtl_writephy(tp, 0x1f, 0x0000);
3074                 rtl_writephy(tp, MII_BMCR, 0x0000);
3075                 return;
3076         }
3077
3078         r810x_phy_power_down(tp);
3079 }
3080
3081 static void r810x_pll_power_up(struct rtl8169_private *tp)
3082 {
3083         r810x_phy_power_up(tp);
3084 }
3085
3086 static void r8168_phy_power_up(struct rtl8169_private *tp)
3087 {
3088         rtl_writephy(tp, 0x1f, 0x0000);
3089         switch (tp->mac_version) {
3090         case RTL_GIGA_MAC_VER_11:
3091         case RTL_GIGA_MAC_VER_12:
3092         case RTL_GIGA_MAC_VER_17:
3093         case RTL_GIGA_MAC_VER_18:
3094         case RTL_GIGA_MAC_VER_19:
3095         case RTL_GIGA_MAC_VER_20:
3096         case RTL_GIGA_MAC_VER_21:
3097         case RTL_GIGA_MAC_VER_22:
3098         case RTL_GIGA_MAC_VER_23:
3099         case RTL_GIGA_MAC_VER_24:
3100         case RTL_GIGA_MAC_VER_25:
3101         case RTL_GIGA_MAC_VER_26:
3102         case RTL_GIGA_MAC_VER_27:
3103         case RTL_GIGA_MAC_VER_28:
3104         case RTL_GIGA_MAC_VER_31:
3105                 rtl_writephy(tp, 0x0e, 0x0000);
3106                 break;
3107         default:
3108                 break;
3109         }
3110         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3111 }
3112
3113 static void r8168_phy_power_down(struct rtl8169_private *tp)
3114 {
3115         rtl_writephy(tp, 0x1f, 0x0000);
3116         switch (tp->mac_version) {
3117         case RTL_GIGA_MAC_VER_32:
3118         case RTL_GIGA_MAC_VER_33:
3119                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3120                 break;
3121
3122         case RTL_GIGA_MAC_VER_11:
3123         case RTL_GIGA_MAC_VER_12:
3124         case RTL_GIGA_MAC_VER_17:
3125         case RTL_GIGA_MAC_VER_18:
3126         case RTL_GIGA_MAC_VER_19:
3127         case RTL_GIGA_MAC_VER_20:
3128         case RTL_GIGA_MAC_VER_21:
3129         case RTL_GIGA_MAC_VER_22:
3130         case RTL_GIGA_MAC_VER_23:
3131         case RTL_GIGA_MAC_VER_24:
3132         case RTL_GIGA_MAC_VER_25:
3133         case RTL_GIGA_MAC_VER_26:
3134         case RTL_GIGA_MAC_VER_27:
3135         case RTL_GIGA_MAC_VER_28:
3136         case RTL_GIGA_MAC_VER_31:
3137                 rtl_writephy(tp, 0x0e, 0x0200);
3138         default:
3139                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3140                 break;
3141         }
3142 }
3143
3144 static void r8168_pll_power_down(struct rtl8169_private *tp)
3145 {
3146         void __iomem *ioaddr = tp->mmio_addr;
3147
3148         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3149              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3150              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3151             r8168dp_check_dash(tp)) {
3152                 return;
3153         }
3154
3155         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3156              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3157             (RTL_R16(CPlusCmd) & ASF)) {
3158                 return;
3159         }
3160
3161         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3162             tp->mac_version == RTL_GIGA_MAC_VER_33)
3163                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3164
3165         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3166                 rtl_writephy(tp, 0x1f, 0x0000);
3167                 rtl_writephy(tp, MII_BMCR, 0x0000);
3168
3169                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3170                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3171                 return;
3172         }
3173
3174         r8168_phy_power_down(tp);
3175
3176         switch (tp->mac_version) {
3177         case RTL_GIGA_MAC_VER_25:
3178         case RTL_GIGA_MAC_VER_26:
3179         case RTL_GIGA_MAC_VER_27:
3180         case RTL_GIGA_MAC_VER_28:
3181         case RTL_GIGA_MAC_VER_31:
3182         case RTL_GIGA_MAC_VER_32:
3183         case RTL_GIGA_MAC_VER_33:
3184                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3185                 break;
3186         }
3187 }
3188
3189 static void r8168_pll_power_up(struct rtl8169_private *tp)
3190 {
3191         void __iomem *ioaddr = tp->mmio_addr;
3192
3193         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3194              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3195              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3196             r8168dp_check_dash(tp)) {
3197                 return;
3198         }
3199
3200         switch (tp->mac_version) {
3201         case RTL_GIGA_MAC_VER_25:
3202         case RTL_GIGA_MAC_VER_26:
3203         case RTL_GIGA_MAC_VER_27:
3204         case RTL_GIGA_MAC_VER_28:
3205         case RTL_GIGA_MAC_VER_31:
3206         case RTL_GIGA_MAC_VER_32:
3207         case RTL_GIGA_MAC_VER_33:
3208                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3209                 break;
3210         }
3211
3212         r8168_phy_power_up(tp);
3213 }
3214
3215 static void rtl_pll_power_op(struct rtl8169_private *tp,
3216                              void (*op)(struct rtl8169_private *))
3217 {
3218         if (op)
3219                 op(tp);
3220 }
3221
3222 static void rtl_pll_power_down(struct rtl8169_private *tp)
3223 {
3224         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3225 }
3226
3227 static void rtl_pll_power_up(struct rtl8169_private *tp)
3228 {
3229         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3230 }
3231
3232 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3233 {
3234         struct pll_power_ops *ops = &tp->pll_power_ops;
3235
3236         switch (tp->mac_version) {
3237         case RTL_GIGA_MAC_VER_07:
3238         case RTL_GIGA_MAC_VER_08:
3239         case RTL_GIGA_MAC_VER_09:
3240         case RTL_GIGA_MAC_VER_10:
3241         case RTL_GIGA_MAC_VER_16:
3242         case RTL_GIGA_MAC_VER_29:
3243         case RTL_GIGA_MAC_VER_30:
3244                 ops->down       = r810x_pll_power_down;
3245                 ops->up         = r810x_pll_power_up;
3246                 break;
3247
3248         case RTL_GIGA_MAC_VER_11:
3249         case RTL_GIGA_MAC_VER_12:
3250         case RTL_GIGA_MAC_VER_17:
3251         case RTL_GIGA_MAC_VER_18:
3252         case RTL_GIGA_MAC_VER_19:
3253         case RTL_GIGA_MAC_VER_20:
3254         case RTL_GIGA_MAC_VER_21:
3255         case RTL_GIGA_MAC_VER_22:
3256         case RTL_GIGA_MAC_VER_23:
3257         case RTL_GIGA_MAC_VER_24:
3258         case RTL_GIGA_MAC_VER_25:
3259         case RTL_GIGA_MAC_VER_26:
3260         case RTL_GIGA_MAC_VER_27:
3261         case RTL_GIGA_MAC_VER_28:
3262         case RTL_GIGA_MAC_VER_31:
3263         case RTL_GIGA_MAC_VER_32:
3264         case RTL_GIGA_MAC_VER_33:
3265                 ops->down       = r8168_pll_power_down;
3266                 ops->up         = r8168_pll_power_up;
3267                 break;
3268
3269         default:
3270                 ops->down       = NULL;
3271                 ops->up         = NULL;
3272                 break;
3273         }
3274 }
3275
3276 static void rtl_hw_reset(struct rtl8169_private *tp)
3277 {
3278         void __iomem *ioaddr = tp->mmio_addr;
3279         int i;
3280
3281         /* Soft reset the chip. */
3282         RTL_W8(ChipCmd, CmdReset);
3283
3284         /* Check that the chip has finished the reset. */
3285         for (i = 0; i < 100; i++) {
3286                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3287                         break;
3288                 msleep_interruptible(1);
3289         }
3290 }
3291
3292 static int __devinit
3293 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3294 {
3295         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3296         const unsigned int region = cfg->region;
3297         struct rtl8169_private *tp;
3298         struct mii_if_info *mii;
3299         struct net_device *dev;
3300         void __iomem *ioaddr;
3301         int chipset, i;
3302         int rc;
3303
3304         if (netif_msg_drv(&debug)) {
3305                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3306                        MODULENAME, RTL8169_VERSION);
3307         }
3308
3309         dev = alloc_etherdev(sizeof (*tp));
3310         if (!dev) {
3311                 if (netif_msg_drv(&debug))
3312                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3313                 rc = -ENOMEM;
3314                 goto out;
3315         }
3316
3317         SET_NETDEV_DEV(dev, &pdev->dev);
3318         dev->netdev_ops = &rtl8169_netdev_ops;
3319         tp = netdev_priv(dev);
3320         tp->dev = dev;
3321         tp->pci_dev = pdev;
3322         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3323
3324         mii = &tp->mii;
3325         mii->dev = dev;
3326         mii->mdio_read = rtl_mdio_read;
3327         mii->mdio_write = rtl_mdio_write;
3328         mii->phy_id_mask = 0x1f;
3329         mii->reg_num_mask = 0x1f;
3330         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3331
3332         /* disable ASPM completely as that cause random device stop working
3333          * problems as well as full system hangs for some PCIe devices users */
3334         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3335                                      PCIE_LINK_STATE_CLKPM);
3336
3337         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3338         rc = pci_enable_device(pdev);
3339         if (rc < 0) {
3340                 netif_err(tp, probe, dev, "enable failure\n");
3341                 goto err_out_free_dev_1;
3342         }
3343
3344         if (pci_set_mwi(pdev) < 0)
3345                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3346
3347         /* make sure PCI base addr 1 is MMIO */
3348         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3349                 netif_err(tp, probe, dev,
3350                           "region #%d not an MMIO resource, aborting\n",
3351                           region);
3352                 rc = -ENODEV;
3353                 goto err_out_mwi_2;
3354         }
3355
3356         /* check for weird/broken PCI region reporting */
3357         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3358                 netif_err(tp, probe, dev,
3359                           "Invalid PCI region size(s), aborting\n");
3360                 rc = -ENODEV;
3361                 goto err_out_mwi_2;
3362         }
3363
3364         rc = pci_request_regions(pdev, MODULENAME);
3365         if (rc < 0) {
3366                 netif_err(tp, probe, dev, "could not request regions\n");
3367                 goto err_out_mwi_2;
3368         }
3369
3370         tp->cp_cmd = RxChkSum;
3371
3372         if ((sizeof(dma_addr_t) > 4) &&
3373             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3374                 tp->cp_cmd |= PCIDAC;
3375                 dev->features |= NETIF_F_HIGHDMA;
3376         } else {
3377                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3378                 if (rc < 0) {
3379                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3380                         goto err_out_free_res_3;
3381                 }
3382         }
3383
3384         /* ioremap MMIO region */
3385         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3386         if (!ioaddr) {
3387                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3388                 rc = -EIO;
3389                 goto err_out_free_res_3;
3390         }
3391         tp->mmio_addr = ioaddr;
3392
3393         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3394         if (!tp->pcie_cap)
3395                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3396
3397         RTL_W16(IntrMask, 0x0000);
3398
3399         rtl_hw_reset(tp);
3400
3401         RTL_W16(IntrStatus, 0xffff);
3402
3403         pci_set_master(pdev);
3404
3405         /* Identify chip attached to board */
3406         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3407
3408         /*
3409          * Pretend we are using VLANs; This bypasses a nasty bug where
3410          * Interrupts stop flowing on high load on 8110SCd controllers.
3411          */
3412         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3413                 tp->cp_cmd |= RxVlan;
3414
3415         rtl_init_mdio_ops(tp);
3416         rtl_init_pll_power_ops(tp);
3417
3418         rtl8169_print_mac_version(tp);
3419
3420         chipset = tp->mac_version;
3421         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3422
3423         RTL_W8(Cfg9346, Cfg9346_Unlock);
3424         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3425         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3426         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3427                 tp->features |= RTL_FEATURE_WOL;
3428         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3429                 tp->features |= RTL_FEATURE_WOL;
3430         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3431         RTL_W8(Cfg9346, Cfg9346_Lock);
3432
3433         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3434             (RTL_R8(PHYstatus) & TBI_Enable)) {
3435                 tp->set_speed = rtl8169_set_speed_tbi;
3436                 tp->get_settings = rtl8169_gset_tbi;
3437                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3438                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3439                 tp->link_ok = rtl8169_tbi_link_ok;
3440                 tp->do_ioctl = rtl_tbi_ioctl;
3441         } else {
3442                 tp->set_speed = rtl8169_set_speed_xmii;
3443                 tp->get_settings = rtl8169_gset_xmii;
3444                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3445                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3446                 tp->link_ok = rtl8169_xmii_link_ok;
3447                 tp->do_ioctl = rtl_xmii_ioctl;
3448         }
3449
3450         spin_lock_init(&tp->lock);
3451
3452         /* Get MAC address */
3453         for (i = 0; i < MAC_ADDR_LEN; i++)
3454                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3455         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3456
3457         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3458         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3459         dev->irq = pdev->irq;
3460         dev->base_addr = (unsigned long) ioaddr;
3461
3462         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3463
3464         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3465          * properly for all devices */
3466         dev->features |= NETIF_F_RXCSUM |
3467                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3468
3469         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3470                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3471         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3472                 NETIF_F_HIGHDMA;
3473
3474         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3475                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3476                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3477
3478         tp->intr_mask = 0xffff;
3479         tp->hw_start = cfg->hw_start;
3480         tp->intr_event = cfg->intr_event;
3481         tp->napi_event = cfg->napi_event;
3482
3483         init_timer(&tp->timer);
3484         tp->timer.data = (unsigned long) dev;
3485         tp->timer.function = rtl8169_phy_timer;
3486
3487         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3488
3489         rc = register_netdev(dev);
3490         if (rc < 0)
3491                 goto err_out_msi_4;
3492
3493         pci_set_drvdata(pdev, dev);
3494
3495         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3496                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3497                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3498
3499         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3500             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3501             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3502                 rtl8168_driver_start(tp);
3503         }
3504
3505         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3506
3507         if (pci_dev_run_wake(pdev))
3508                 pm_runtime_put_noidle(&pdev->dev);
3509
3510         netif_carrier_off(dev);
3511
3512 out:
3513         return rc;
3514
3515 err_out_msi_4:
3516         rtl_disable_msi(pdev, tp);
3517         iounmap(ioaddr);
3518 err_out_free_res_3:
3519         pci_release_regions(pdev);
3520 err_out_mwi_2:
3521         pci_clear_mwi(pdev);
3522         pci_disable_device(pdev);
3523 err_out_free_dev_1:
3524         free_netdev(dev);
3525         goto out;
3526 }
3527
3528 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3529 {
3530         struct net_device *dev = pci_get_drvdata(pdev);
3531         struct rtl8169_private *tp = netdev_priv(dev);
3532
3533         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3534             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3535             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3536                 rtl8168_driver_stop(tp);
3537         }
3538
3539         cancel_delayed_work_sync(&tp->task);
3540
3541         unregister_netdev(dev);
3542
3543         rtl_release_firmware(tp);
3544
3545         if (pci_dev_run_wake(pdev))
3546                 pm_runtime_get_noresume(&pdev->dev);
3547
3548         /* restore original MAC address */
3549         rtl_rar_set(tp, dev->perm_addr);
3550
3551         rtl_disable_msi(pdev, tp);
3552         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3553         pci_set_drvdata(pdev, NULL);
3554 }
3555
3556 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3557 {
3558         struct rtl_fw *rtl_fw;
3559         const char *name;
3560         int rc = -ENOMEM;
3561
3562         name = rtl_lookup_firmware_name(tp);
3563         if (!name)
3564                 goto out_no_firmware;
3565
3566         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3567         if (!rtl_fw)
3568                 goto err_warn;
3569
3570         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3571         if (rc < 0)
3572                 goto err_free;
3573
3574         tp->rtl_fw = rtl_fw;
3575 out:
3576         return;
3577
3578 err_free:
3579         kfree(rtl_fw);
3580 err_warn:
3581         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3582                    name, rc);
3583 out_no_firmware:
3584         tp->rtl_fw = NULL;
3585         goto out;
3586 }
3587
3588 static void rtl_request_firmware(struct rtl8169_private *tp)
3589 {
3590         if (IS_ERR(tp->rtl_fw))
3591                 rtl_request_uncached_firmware(tp);
3592 }
3593
3594 static int rtl8169_open(struct net_device *dev)
3595 {
3596         struct rtl8169_private *tp = netdev_priv(dev);
3597         void __iomem *ioaddr = tp->mmio_addr;
3598         struct pci_dev *pdev = tp->pci_dev;
3599         int retval = -ENOMEM;
3600
3601         pm_runtime_get_sync(&pdev->dev);
3602
3603         /*
3604          * Rx and Tx desscriptors needs 256 bytes alignment.
3605          * dma_alloc_coherent provides more.
3606          */
3607         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3608                                              &tp->TxPhyAddr, GFP_KERNEL);
3609         if (!tp->TxDescArray)
3610                 goto err_pm_runtime_put;
3611
3612         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3613                                              &tp->RxPhyAddr, GFP_KERNEL);
3614         if (!tp->RxDescArray)
3615                 goto err_free_tx_0;
3616
3617         retval = rtl8169_init_ring(dev);
3618         if (retval < 0)
3619                 goto err_free_rx_1;
3620
3621         INIT_DELAYED_WORK(&tp->task, NULL);
3622
3623         smp_mb();
3624
3625         rtl_request_firmware(tp);
3626
3627         retval = request_irq(dev->irq, rtl8169_interrupt,
3628                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3629                              dev->name, dev);
3630         if (retval < 0)
3631                 goto err_release_fw_2;
3632
3633         napi_enable(&tp->napi);
3634
3635         rtl8169_init_phy(dev, tp);
3636
3637         rtl8169_set_features(dev, dev->features);
3638
3639         rtl_pll_power_up(tp);
3640
3641         rtl_hw_start(dev);
3642
3643         tp->saved_wolopts = 0;
3644         pm_runtime_put_noidle(&pdev->dev);
3645
3646         rtl8169_check_link_status(dev, tp, ioaddr);
3647 out:
3648         return retval;
3649
3650 err_release_fw_2:
3651         rtl_release_firmware(tp);
3652         rtl8169_rx_clear(tp);
3653 err_free_rx_1:
3654         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3655                           tp->RxPhyAddr);
3656         tp->RxDescArray = NULL;
3657 err_free_tx_0:
3658         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3659                           tp->TxPhyAddr);
3660         tp->TxDescArray = NULL;
3661 err_pm_runtime_put:
3662         pm_runtime_put_noidle(&pdev->dev);
3663         goto out;
3664 }
3665
3666 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3667 {
3668         void __iomem *ioaddr = tp->mmio_addr;
3669
3670         /* Disable interrupts */
3671         rtl8169_irq_mask_and_ack(ioaddr);
3672
3673         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3674             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3675             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3676                 while (RTL_R8(TxPoll) & NPQ)
3677                         udelay(20);
3678
3679         }
3680
3681         /* Reset the chipset */
3682         RTL_W8(ChipCmd, CmdReset);
3683
3684         /* PCI commit */
3685         RTL_R8(ChipCmd);
3686 }
3687
3688 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3689 {
3690         void __iomem *ioaddr = tp->mmio_addr;
3691         u32 cfg = rtl8169_rx_config;
3692
3693         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3694         RTL_W32(RxConfig, cfg);
3695
3696         /* Set DMA burst size and Interframe Gap Time */
3697         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3698                 (InterFrameGap << TxInterFrameGapShift));
3699 }
3700
3701 static void rtl_hw_start(struct net_device *dev)
3702 {
3703         struct rtl8169_private *tp = netdev_priv(dev);
3704
3705         rtl_hw_reset(tp);
3706
3707         tp->hw_start(dev);
3708
3709         netif_start_queue(dev);
3710 }
3711
3712 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3713                                          void __iomem *ioaddr)
3714 {
3715         /*
3716          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3717          * register to be written before TxDescAddrLow to work.
3718          * Switching from MMIO to I/O access fixes the issue as well.
3719          */
3720         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3721         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3722         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3723         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3724 }
3725
3726 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3727 {
3728         u16 cmd;
3729
3730         cmd = RTL_R16(CPlusCmd);
3731         RTL_W16(CPlusCmd, cmd);
3732         return cmd;
3733 }
3734
3735 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3736 {
3737         /* Low hurts. Let's disable the filtering. */
3738         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3739 }
3740
3741 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3742 {
3743         static const struct {
3744                 u32 mac_version;
3745                 u32 clk;
3746                 u32 val;
3747         } cfg2_info [] = {
3748                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3749                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3750                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3751                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3752         }, *p = cfg2_info;
3753         unsigned int i;
3754         u32 clk;
3755
3756         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3757         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3758                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3759                         RTL_W32(0x7c, p->val);
3760                         break;
3761                 }
3762         }
3763 }
3764
3765 static void rtl_hw_start_8169(struct net_device *dev)
3766 {
3767         struct rtl8169_private *tp = netdev_priv(dev);
3768         void __iomem *ioaddr = tp->mmio_addr;
3769         struct pci_dev *pdev = tp->pci_dev;
3770
3771         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3772                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3773                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3774         }
3775
3776         RTL_W8(Cfg9346, Cfg9346_Unlock);
3777         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3778             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3779             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3780             tp->mac_version == RTL_GIGA_MAC_VER_04)
3781                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3782
3783         RTL_W8(EarlyTxThres, NoEarlyTx);
3784
3785         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3786
3787         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3788             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3789             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3790             tp->mac_version == RTL_GIGA_MAC_VER_04)
3791                 rtl_set_rx_tx_config_registers(tp);
3792
3793         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3794
3795         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3796             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3797                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3798                         "Bit-3 and bit-14 MUST be 1\n");
3799                 tp->cp_cmd |= (1 << 14);
3800         }
3801
3802         RTL_W16(CPlusCmd, tp->cp_cmd);
3803
3804         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3805
3806         /*
3807          * Undocumented corner. Supposedly:
3808          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3809          */
3810         RTL_W16(IntrMitigate, 0x0000);
3811
3812         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3813
3814         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3815             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3816             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3817             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3818                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3819                 rtl_set_rx_tx_config_registers(tp);
3820         }
3821
3822         RTL_W8(Cfg9346, Cfg9346_Lock);
3823
3824         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3825         RTL_R8(IntrMask);
3826
3827         RTL_W32(RxMissed, 0);
3828
3829         rtl_set_rx_mode(dev);
3830
3831         /* no early-rx interrupts */
3832         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3833
3834         /* Enable all known interrupts by setting the interrupt mask. */
3835         RTL_W16(IntrMask, tp->intr_event);
3836 }
3837
3838 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3839 {
3840         struct net_device *dev = pci_get_drvdata(pdev);
3841         struct rtl8169_private *tp = netdev_priv(dev);
3842         int cap = tp->pcie_cap;
3843
3844         if (cap) {
3845                 u16 ctl;
3846
3847                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3848                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3849                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3850         }
3851 }
3852
3853 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3854 {
3855         u32 csi;
3856
3857         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3858         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3859 }
3860
3861 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3862 {
3863         rtl_csi_access_enable(ioaddr, 0x17000000);
3864 }
3865
3866 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3867 {
3868         rtl_csi_access_enable(ioaddr, 0x27000000);
3869 }
3870
3871 struct ephy_info {
3872         unsigned int offset;
3873         u16 mask;
3874         u16 bits;
3875 };
3876
3877 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3878 {
3879         u16 w;
3880
3881         while (len-- > 0) {
3882                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3883                 rtl_ephy_write(ioaddr, e->offset, w);
3884                 e++;
3885         }
3886 }
3887
3888 static void rtl_disable_clock_request(struct pci_dev *pdev)
3889 {
3890         struct net_device *dev = pci_get_drvdata(pdev);
3891         struct rtl8169_private *tp = netdev_priv(dev);
3892         int cap = tp->pcie_cap;
3893
3894         if (cap) {
3895                 u16 ctl;
3896
3897                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3898                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3899                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3900         }
3901 }
3902
3903 static void rtl_enable_clock_request(struct pci_dev *pdev)
3904 {
3905         struct net_device *dev = pci_get_drvdata(pdev);
3906         struct rtl8169_private *tp = netdev_priv(dev);
3907         int cap = tp->pcie_cap;
3908
3909         if (cap) {
3910                 u16 ctl;
3911
3912                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3913                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3914                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3915         }
3916 }
3917
3918 #define R8168_CPCMD_QUIRK_MASK (\
3919         EnableBist | \
3920         Mac_dbgo_oe | \
3921         Force_half_dup | \
3922         Force_rxflow_en | \
3923         Force_txflow_en | \
3924         Cxpl_dbg_sel | \
3925         ASF | \
3926         PktCntrDisable | \
3927         Mac_dbgo_sel)
3928
3929 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3930 {
3931         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3932
3933         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3934
3935         rtl_tx_performance_tweak(pdev,
3936                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3937 }
3938
3939 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3940 {
3941         rtl_hw_start_8168bb(ioaddr, pdev);
3942
3943         RTL_W8(MaxTxPacketSize, TxPacketMax);
3944
3945         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3946 }
3947
3948 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3949 {
3950         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3951
3952         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3953
3954         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3955
3956         rtl_disable_clock_request(pdev);
3957
3958         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3959 }
3960
3961 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3962 {
3963         static const struct ephy_info e_info_8168cp[] = {
3964                 { 0x01, 0,      0x0001 },
3965                 { 0x02, 0x0800, 0x1000 },
3966                 { 0x03, 0,      0x0042 },
3967                 { 0x06, 0x0080, 0x0000 },
3968                 { 0x07, 0,      0x2000 }
3969         };
3970
3971         rtl_csi_access_enable_2(ioaddr);
3972
3973         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3974
3975         __rtl_hw_start_8168cp(ioaddr, pdev);
3976 }
3977
3978 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3979 {
3980         rtl_csi_access_enable_2(ioaddr);
3981
3982         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3983
3984         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3985
3986         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3987 }
3988
3989 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3990 {
3991         rtl_csi_access_enable_2(ioaddr);
3992
3993         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3994
3995         /* Magic. */
3996         RTL_W8(DBG_REG, 0x20);
3997
3998         RTL_W8(MaxTxPacketSize, TxPacketMax);
3999
4000         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4001
4002         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4003 }
4004
4005 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4006 {
4007         static const struct ephy_info e_info_8168c_1[] = {
4008                 { 0x02, 0x0800, 0x1000 },
4009                 { 0x03, 0,      0x0002 },
4010                 { 0x06, 0x0080, 0x0000 }
4011         };
4012
4013         rtl_csi_access_enable_2(ioaddr);
4014
4015         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4016
4017         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4018
4019         __rtl_hw_start_8168cp(ioaddr, pdev);
4020 }
4021
4022 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4023 {
4024         static const struct ephy_info e_info_8168c_2[] = {
4025                 { 0x01, 0,      0x0001 },
4026                 { 0x03, 0x0400, 0x0220 }
4027         };
4028
4029         rtl_csi_access_enable_2(ioaddr);
4030
4031         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4032
4033         __rtl_hw_start_8168cp(ioaddr, pdev);
4034 }
4035
4036 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4037 {
4038         rtl_hw_start_8168c_2(ioaddr, pdev);
4039 }
4040
4041 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4042 {
4043         rtl_csi_access_enable_2(ioaddr);
4044
4045         __rtl_hw_start_8168cp(ioaddr, pdev);
4046 }
4047
4048 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4049 {
4050         rtl_csi_access_enable_2(ioaddr);
4051
4052         rtl_disable_clock_request(pdev);
4053
4054         RTL_W8(MaxTxPacketSize, TxPacketMax);
4055
4056         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4057
4058         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4059 }
4060
4061 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4062 {
4063         rtl_csi_access_enable_1(ioaddr);
4064
4065         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4066
4067         RTL_W8(MaxTxPacketSize, TxPacketMax);
4068
4069         rtl_disable_clock_request(pdev);
4070 }
4071
4072 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4073 {
4074         static const struct ephy_info e_info_8168d_4[] = {
4075                 { 0x0b, ~0,     0x48 },
4076                 { 0x19, 0x20,   0x50 },
4077                 { 0x0c, ~0,     0x20 }
4078         };
4079         int i;
4080
4081         rtl_csi_access_enable_1(ioaddr);
4082
4083         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4084
4085         RTL_W8(MaxTxPacketSize, TxPacketMax);
4086
4087         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4088                 const struct ephy_info *e = e_info_8168d_4 + i;
4089                 u16 w;
4090
4091                 w = rtl_ephy_read(ioaddr, e->offset);
4092                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4093         }
4094
4095         rtl_enable_clock_request(pdev);
4096 }
4097
4098 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4099 {
4100         static const struct ephy_info e_info_8168e[] = {
4101                 { 0x00, 0x0200, 0x0100 },
4102                 { 0x00, 0x0000, 0x0004 },
4103                 { 0x06, 0x0002, 0x0001 },
4104                 { 0x06, 0x0000, 0x0030 },
4105                 { 0x07, 0x0000, 0x2000 },
4106                 { 0x00, 0x0000, 0x0020 },
4107                 { 0x03, 0x5800, 0x2000 },
4108                 { 0x03, 0x0000, 0x0001 },
4109                 { 0x01, 0x0800, 0x1000 },
4110                 { 0x07, 0x0000, 0x4000 },
4111                 { 0x1e, 0x0000, 0x2000 },
4112                 { 0x19, 0xffff, 0xfe6c },
4113                 { 0x0a, 0x0000, 0x0040 }
4114         };
4115
4116         rtl_csi_access_enable_2(ioaddr);
4117
4118         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4119
4120         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4121
4122         RTL_W8(MaxTxPacketSize, TxPacketMax);
4123
4124         rtl_disable_clock_request(pdev);
4125
4126         /* Reset tx FIFO pointer */
4127         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4128         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4129
4130         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4131 }
4132
4133 static void rtl_hw_start_8168(struct net_device *dev)
4134 {
4135         struct rtl8169_private *tp = netdev_priv(dev);
4136         void __iomem *ioaddr = tp->mmio_addr;
4137         struct pci_dev *pdev = tp->pci_dev;
4138
4139         RTL_W8(Cfg9346, Cfg9346_Unlock);
4140
4141         RTL_W8(MaxTxPacketSize, TxPacketMax);
4142
4143         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4144
4145         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4146
4147         RTL_W16(CPlusCmd, tp->cp_cmd);
4148
4149         RTL_W16(IntrMitigate, 0x5151);
4150
4151         /* Work around for RxFIFO overflow. */
4152         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4153             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4154                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4155                 tp->intr_event &= ~RxOverflow;
4156         }
4157
4158         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4159
4160         rtl_set_rx_mode(dev);
4161
4162         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4163                 (InterFrameGap << TxInterFrameGapShift));
4164
4165         RTL_R8(IntrMask);
4166
4167         switch (tp->mac_version) {
4168         case RTL_GIGA_MAC_VER_11:
4169                 rtl_hw_start_8168bb(ioaddr, pdev);
4170                 break;
4171
4172         case RTL_GIGA_MAC_VER_12:
4173         case RTL_GIGA_MAC_VER_17:
4174                 rtl_hw_start_8168bef(ioaddr, pdev);
4175                 break;
4176
4177         case RTL_GIGA_MAC_VER_18:
4178                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4179                 break;
4180
4181         case RTL_GIGA_MAC_VER_19:
4182                 rtl_hw_start_8168c_1(ioaddr, pdev);
4183                 break;
4184
4185         case RTL_GIGA_MAC_VER_20:
4186                 rtl_hw_start_8168c_2(ioaddr, pdev);
4187                 break;
4188
4189         case RTL_GIGA_MAC_VER_21:
4190                 rtl_hw_start_8168c_3(ioaddr, pdev);
4191                 break;
4192
4193         case RTL_GIGA_MAC_VER_22:
4194                 rtl_hw_start_8168c_4(ioaddr, pdev);
4195                 break;
4196
4197         case RTL_GIGA_MAC_VER_23:
4198                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4199                 break;
4200
4201         case RTL_GIGA_MAC_VER_24:
4202                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4203                 break;
4204
4205         case RTL_GIGA_MAC_VER_25:
4206         case RTL_GIGA_MAC_VER_26:
4207         case RTL_GIGA_MAC_VER_27:
4208                 rtl_hw_start_8168d(ioaddr, pdev);
4209                 break;
4210
4211         case RTL_GIGA_MAC_VER_28:
4212                 rtl_hw_start_8168d_4(ioaddr, pdev);
4213                 break;
4214
4215         case RTL_GIGA_MAC_VER_31:
4216                 rtl_hw_start_8168dp(ioaddr, pdev);
4217                 break;
4218
4219         case RTL_GIGA_MAC_VER_32:
4220         case RTL_GIGA_MAC_VER_33:
4221                 rtl_hw_start_8168e(ioaddr, pdev);
4222                 break;
4223
4224         default:
4225                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4226                         dev->name, tp->mac_version);
4227                 break;
4228         }
4229
4230         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4231
4232         RTL_W8(Cfg9346, Cfg9346_Lock);
4233
4234         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4235
4236         RTL_W16(IntrMask, tp->intr_event);
4237 }
4238
4239 #define R810X_CPCMD_QUIRK_MASK (\
4240         EnableBist | \
4241         Mac_dbgo_oe | \
4242         Force_half_dup | \
4243         Force_rxflow_en | \
4244         Force_txflow_en | \
4245         Cxpl_dbg_sel | \
4246         ASF | \
4247         PktCntrDisable | \
4248         Mac_dbgo_sel)
4249
4250 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4251 {
4252         static const struct ephy_info e_info_8102e_1[] = {
4253                 { 0x01, 0, 0x6e65 },
4254                 { 0x02, 0, 0x091f },
4255                 { 0x03, 0, 0xc2f9 },
4256                 { 0x06, 0, 0xafb5 },
4257                 { 0x07, 0, 0x0e00 },
4258                 { 0x19, 0, 0xec80 },
4259                 { 0x01, 0, 0x2e65 },
4260                 { 0x01, 0, 0x6e65 }
4261         };
4262         u8 cfg1;
4263
4264         rtl_csi_access_enable_2(ioaddr);
4265
4266         RTL_W8(DBG_REG, FIX_NAK_1);
4267
4268         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4269
4270         RTL_W8(Config1,
4271                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4272         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4273
4274         cfg1 = RTL_R8(Config1);
4275         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4276                 RTL_W8(Config1, cfg1 & ~LEDS0);
4277
4278         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4279 }
4280
4281 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4282 {
4283         rtl_csi_access_enable_2(ioaddr);
4284
4285         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4286
4287         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4288         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4289 }
4290
4291 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4292 {
4293         rtl_hw_start_8102e_2(ioaddr, pdev);
4294
4295         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4296 }
4297
4298 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4299 {
4300         static const struct ephy_info e_info_8105e_1[] = {
4301                 { 0x07, 0, 0x4000 },
4302                 { 0x19, 0, 0x0200 },
4303                 { 0x19, 0, 0x0020 },
4304                 { 0x1e, 0, 0x2000 },
4305                 { 0x03, 0, 0x0001 },
4306                 { 0x19, 0, 0x0100 },
4307                 { 0x19, 0, 0x0004 },
4308                 { 0x0a, 0, 0x0020 }
4309         };
4310
4311         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4312         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4313
4314         /* Disable Early Tally Counter */
4315         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4316
4317         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4318         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4319
4320         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4321 }
4322
4323 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4324 {
4325         rtl_hw_start_8105e_1(ioaddr, pdev);
4326         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4327 }
4328
4329 static void rtl_hw_start_8101(struct net_device *dev)
4330 {
4331         struct rtl8169_private *tp = netdev_priv(dev);
4332         void __iomem *ioaddr = tp->mmio_addr;
4333         struct pci_dev *pdev = tp->pci_dev;
4334
4335         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4336             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4337                 int cap = tp->pcie_cap;
4338
4339                 if (cap) {
4340                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4341                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4342                 }
4343         }
4344
4345         RTL_W8(Cfg9346, Cfg9346_Unlock);
4346
4347         switch (tp->mac_version) {
4348         case RTL_GIGA_MAC_VER_07:
4349                 rtl_hw_start_8102e_1(ioaddr, pdev);
4350                 break;
4351
4352         case RTL_GIGA_MAC_VER_08:
4353                 rtl_hw_start_8102e_3(ioaddr, pdev);
4354                 break;
4355
4356         case RTL_GIGA_MAC_VER_09:
4357                 rtl_hw_start_8102e_2(ioaddr, pdev);
4358                 break;
4359
4360         case RTL_GIGA_MAC_VER_29:
4361                 rtl_hw_start_8105e_1(ioaddr, pdev);
4362                 break;
4363         case RTL_GIGA_MAC_VER_30:
4364                 rtl_hw_start_8105e_2(ioaddr, pdev);
4365                 break;
4366         }
4367
4368         RTL_W8(Cfg9346, Cfg9346_Lock);
4369
4370         RTL_W8(MaxTxPacketSize, TxPacketMax);
4371
4372         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4373
4374         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4375         RTL_W16(CPlusCmd, tp->cp_cmd);
4376
4377         RTL_W16(IntrMitigate, 0x0000);
4378
4379         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4380
4381         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4382         rtl_set_rx_tx_config_registers(tp);
4383
4384         RTL_R8(IntrMask);
4385
4386         rtl_set_rx_mode(dev);
4387
4388         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4389
4390         RTL_W16(IntrMask, tp->intr_event);
4391 }
4392
4393 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4394 {
4395         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4396                 return -EINVAL;
4397
4398         dev->mtu = new_mtu;
4399         netdev_update_features(dev);
4400
4401         return 0;
4402 }
4403
4404 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4405 {
4406         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4407         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4408 }
4409
4410 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4411                                      void **data_buff, struct RxDesc *desc)
4412 {
4413         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4414                          DMA_FROM_DEVICE);
4415
4416         kfree(*data_buff);
4417         *data_buff = NULL;
4418         rtl8169_make_unusable_by_asic(desc);
4419 }
4420
4421 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4422 {
4423         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4424
4425         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4426 }
4427
4428 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4429                                        u32 rx_buf_sz)
4430 {
4431         desc->addr = cpu_to_le64(mapping);
4432         wmb();
4433         rtl8169_mark_to_asic(desc, rx_buf_sz);
4434 }
4435
4436 static inline void *rtl8169_align(void *data)
4437 {
4438         return (void *)ALIGN((long)data, 16);
4439 }
4440
4441 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4442                                              struct RxDesc *desc)
4443 {
4444         void *data;
4445         dma_addr_t mapping;
4446         struct device *d = &tp->pci_dev->dev;
4447         struct net_device *dev = tp->dev;
4448         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4449
4450         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4451         if (!data)
4452                 return NULL;
4453
4454         if (rtl8169_align(data) != data) {
4455                 kfree(data);
4456                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4457                 if (!data)
4458                         return NULL;
4459         }
4460
4461         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4462                                  DMA_FROM_DEVICE);
4463         if (unlikely(dma_mapping_error(d, mapping))) {
4464                 if (net_ratelimit())
4465                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4466                 goto err_out;
4467         }
4468
4469         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4470         return data;
4471
4472 err_out:
4473         kfree(data);
4474         return NULL;
4475 }
4476
4477 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4478 {
4479         unsigned int i;
4480
4481         for (i = 0; i < NUM_RX_DESC; i++) {
4482                 if (tp->Rx_databuff[i]) {
4483                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4484                                             tp->RxDescArray + i);
4485                 }
4486         }
4487 }
4488
4489 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4490 {
4491         desc->opts1 |= cpu_to_le32(RingEnd);
4492 }
4493
4494 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4495 {
4496         unsigned int i;
4497
4498         for (i = 0; i < NUM_RX_DESC; i++) {
4499                 void *data;
4500
4501                 if (tp->Rx_databuff[i])
4502                         continue;
4503
4504                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4505                 if (!data) {
4506                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4507                         goto err_out;
4508                 }
4509                 tp->Rx_databuff[i] = data;
4510         }
4511
4512         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4513         return 0;
4514
4515 err_out:
4516         rtl8169_rx_clear(tp);
4517         return -ENOMEM;
4518 }
4519
4520 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4521 {
4522         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4523 }
4524
4525 static int rtl8169_init_ring(struct net_device *dev)
4526 {
4527         struct rtl8169_private *tp = netdev_priv(dev);
4528
4529         rtl8169_init_ring_indexes(tp);
4530
4531         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4532         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4533
4534         return rtl8169_rx_fill(tp);
4535 }
4536
4537 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4538                                  struct TxDesc *desc)
4539 {
4540         unsigned int len = tx_skb->len;
4541
4542         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4543
4544         desc->opts1 = 0x00;
4545         desc->opts2 = 0x00;
4546         desc->addr = 0x00;
4547         tx_skb->len = 0;
4548 }
4549
4550 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4551                                    unsigned int n)
4552 {
4553         unsigned int i;
4554
4555         for (i = 0; i < n; i++) {
4556                 unsigned int entry = (start + i) % NUM_TX_DESC;
4557                 struct ring_info *tx_skb = tp->tx_skb + entry;
4558                 unsigned int len = tx_skb->len;
4559
4560                 if (len) {
4561                         struct sk_buff *skb = tx_skb->skb;
4562
4563                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4564                                              tp->TxDescArray + entry);
4565                         if (skb) {
4566                                 tp->dev->stats.tx_dropped++;
4567                                 dev_kfree_skb(skb);
4568                                 tx_skb->skb = NULL;
4569                         }
4570                 }
4571         }
4572 }
4573
4574 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4575 {
4576         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4577         tp->cur_tx = tp->dirty_tx = 0;
4578 }
4579
4580 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4581 {
4582         struct rtl8169_private *tp = netdev_priv(dev);
4583
4584         PREPARE_DELAYED_WORK(&tp->task, task);
4585         schedule_delayed_work(&tp->task, 4);
4586 }
4587
4588 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4589 {
4590         struct rtl8169_private *tp = netdev_priv(dev);
4591         void __iomem *ioaddr = tp->mmio_addr;
4592
4593         synchronize_irq(dev->irq);
4594
4595         /* Wait for any pending NAPI task to complete */
4596         napi_disable(&tp->napi);
4597
4598         rtl8169_irq_mask_and_ack(ioaddr);
4599
4600         tp->intr_mask = 0xffff;
4601         RTL_W16(IntrMask, tp->intr_event);
4602         napi_enable(&tp->napi);
4603 }
4604
4605 static void rtl8169_reinit_task(struct work_struct *work)
4606 {
4607         struct rtl8169_private *tp =
4608                 container_of(work, struct rtl8169_private, task.work);
4609         struct net_device *dev = tp->dev;
4610         int ret;
4611
4612         rtnl_lock();
4613
4614         if (!netif_running(dev))
4615                 goto out_unlock;
4616
4617         rtl8169_wait_for_quiescence(dev);
4618         rtl8169_close(dev);
4619
4620         ret = rtl8169_open(dev);
4621         if (unlikely(ret < 0)) {
4622                 if (net_ratelimit())
4623                         netif_err(tp, drv, dev,
4624                                   "reinit failure (status = %d). Rescheduling\n",
4625                                   ret);
4626                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4627         }
4628
4629 out_unlock:
4630         rtnl_unlock();
4631 }
4632
4633 static void rtl8169_reset_task(struct work_struct *work)
4634 {
4635         struct rtl8169_private *tp =
4636                 container_of(work, struct rtl8169_private, task.work);
4637         struct net_device *dev = tp->dev;
4638         int i;
4639
4640         rtnl_lock();
4641
4642         if (!netif_running(dev))
4643                 goto out_unlock;
4644
4645         rtl8169_wait_for_quiescence(dev);
4646
4647         for (i = 0; i < NUM_RX_DESC; i++)
4648                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4649
4650         rtl8169_tx_clear(tp);
4651
4652         rtl8169_init_ring_indexes(tp);
4653         rtl_hw_start(dev);
4654         netif_wake_queue(dev);
4655         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4656
4657 out_unlock:
4658         rtnl_unlock();
4659 }
4660
4661 static void rtl8169_tx_timeout(struct net_device *dev)
4662 {
4663         struct rtl8169_private *tp = netdev_priv(dev);
4664
4665         rtl8169_hw_reset(tp);
4666
4667         /* Let's wait a bit while any (async) irq lands on */
4668         rtl8169_schedule_work(dev, rtl8169_reset_task);
4669 }
4670
4671 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4672                               u32 *opts)
4673 {
4674         struct skb_shared_info *info = skb_shinfo(skb);
4675         unsigned int cur_frag, entry;
4676         struct TxDesc * uninitialized_var(txd);
4677         struct device *d = &tp->pci_dev->dev;
4678
4679         entry = tp->cur_tx;
4680         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4681                 skb_frag_t *frag = info->frags + cur_frag;
4682                 dma_addr_t mapping;
4683                 u32 status, len;
4684                 void *addr;
4685
4686                 entry = (entry + 1) % NUM_TX_DESC;
4687
4688                 txd = tp->TxDescArray + entry;
4689                 len = frag->size;
4690                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4691                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4692                 if (unlikely(dma_mapping_error(d, mapping))) {
4693                         if (net_ratelimit())
4694                                 netif_err(tp, drv, tp->dev,
4695                                           "Failed to map TX fragments DMA!\n");
4696                         goto err_out;
4697                 }
4698
4699                 /* Anti gcc 2.95.3 bugware (sic) */
4700                 status = opts[0] | len |
4701                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4702
4703                 txd->opts1 = cpu_to_le32(status);
4704                 txd->opts2 = cpu_to_le32(opts[1]);
4705                 txd->addr = cpu_to_le64(mapping);
4706
4707                 tp->tx_skb[entry].len = len;
4708         }
4709
4710         if (cur_frag) {
4711                 tp->tx_skb[entry].skb = skb;
4712                 txd->opts1 |= cpu_to_le32(LastFrag);
4713         }
4714
4715         return cur_frag;
4716
4717 err_out:
4718         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4719         return -EIO;
4720 }
4721
4722 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4723                                     struct sk_buff *skb, u32 *opts)
4724 {
4725         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4726         u32 mss = skb_shinfo(skb)->gso_size;
4727         int offset = info->opts_offset;
4728
4729         if (mss) {
4730                 opts[0] |= TD_LSO;
4731                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4732         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4733                 const struct iphdr *ip = ip_hdr(skb);
4734
4735                 if (ip->protocol == IPPROTO_TCP)
4736                         opts[offset] |= info->checksum.tcp;
4737                 else if (ip->protocol == IPPROTO_UDP)
4738                         opts[offset] |= info->checksum.udp;
4739                 else
4740                         WARN_ON_ONCE(1);
4741         }
4742 }
4743
4744 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4745                                       struct net_device *dev)
4746 {
4747         struct rtl8169_private *tp = netdev_priv(dev);
4748         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4749         struct TxDesc *txd = tp->TxDescArray + entry;
4750         void __iomem *ioaddr = tp->mmio_addr;
4751         struct device *d = &tp->pci_dev->dev;
4752         dma_addr_t mapping;
4753         u32 status, len;
4754         u32 opts[2];
4755         int frags;
4756
4757         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4758                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4759                 goto err_stop_0;
4760         }
4761
4762         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4763                 goto err_stop_0;
4764
4765         len = skb_headlen(skb);
4766         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4767         if (unlikely(dma_mapping_error(d, mapping))) {
4768                 if (net_ratelimit())
4769                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4770                 goto err_dma_0;
4771         }
4772
4773         tp->tx_skb[entry].len = len;
4774         txd->addr = cpu_to_le64(mapping);
4775
4776         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4777         opts[0] = DescOwn;
4778
4779         rtl8169_tso_csum(tp, skb, opts);
4780
4781         frags = rtl8169_xmit_frags(tp, skb, opts);
4782         if (frags < 0)
4783                 goto err_dma_1;
4784         else if (frags)
4785                 opts[0] |= FirstFrag;
4786         else {
4787                 opts[0] |= FirstFrag | LastFrag;
4788                 tp->tx_skb[entry].skb = skb;
4789         }
4790
4791         txd->opts2 = cpu_to_le32(opts[1]);
4792
4793         wmb();
4794
4795         /* Anti gcc 2.95.3 bugware (sic) */
4796         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4797         txd->opts1 = cpu_to_le32(status);
4798
4799         tp->cur_tx += frags + 1;
4800
4801         wmb();
4802
4803         RTL_W8(TxPoll, NPQ);
4804
4805         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4806                 netif_stop_queue(dev);
4807                 smp_rmb();
4808                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4809                         netif_wake_queue(dev);
4810         }
4811
4812         return NETDEV_TX_OK;
4813
4814 err_dma_1:
4815         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4816 err_dma_0:
4817         dev_kfree_skb(skb);
4818         dev->stats.tx_dropped++;
4819         return NETDEV_TX_OK;
4820
4821 err_stop_0:
4822         netif_stop_queue(dev);
4823         dev->stats.tx_dropped++;
4824         return NETDEV_TX_BUSY;
4825 }
4826
4827 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4828 {
4829         struct rtl8169_private *tp = netdev_priv(dev);
4830         struct pci_dev *pdev = tp->pci_dev;
4831         u16 pci_status, pci_cmd;
4832
4833         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4834         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4835
4836         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4837                   pci_cmd, pci_status);
4838
4839         /*
4840          * The recovery sequence below admits a very elaborated explanation:
4841          * - it seems to work;
4842          * - I did not see what else could be done;
4843          * - it makes iop3xx happy.
4844          *
4845          * Feel free to adjust to your needs.
4846          */
4847         if (pdev->broken_parity_status)
4848                 pci_cmd &= ~PCI_COMMAND_PARITY;
4849         else
4850                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4851
4852         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4853
4854         pci_write_config_word(pdev, PCI_STATUS,
4855                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4856                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4857                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4858
4859         /* The infamous DAC f*ckup only happens at boot time */
4860         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4861                 void __iomem *ioaddr = tp->mmio_addr;
4862
4863                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4864                 tp->cp_cmd &= ~PCIDAC;
4865                 RTL_W16(CPlusCmd, tp->cp_cmd);
4866                 dev->features &= ~NETIF_F_HIGHDMA;
4867         }
4868
4869         rtl8169_hw_reset(tp);
4870
4871         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4872 }
4873
4874 static void rtl8169_tx_interrupt(struct net_device *dev,
4875                                  struct rtl8169_private *tp,
4876                                  void __iomem *ioaddr)
4877 {
4878         unsigned int dirty_tx, tx_left;
4879
4880         dirty_tx = tp->dirty_tx;
4881         smp_rmb();
4882         tx_left = tp->cur_tx - dirty_tx;
4883
4884         while (tx_left > 0) {
4885                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4886                 struct ring_info *tx_skb = tp->tx_skb + entry;
4887                 u32 status;
4888
4889                 rmb();
4890                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4891                 if (status & DescOwn)
4892                         break;
4893
4894                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4895                                      tp->TxDescArray + entry);
4896                 if (status & LastFrag) {
4897                         dev->stats.tx_packets++;
4898                         dev->stats.tx_bytes += tx_skb->skb->len;
4899                         dev_kfree_skb(tx_skb->skb);
4900                         tx_skb->skb = NULL;
4901                 }
4902                 dirty_tx++;
4903                 tx_left--;
4904         }
4905
4906         if (tp->dirty_tx != dirty_tx) {
4907                 tp->dirty_tx = dirty_tx;
4908                 smp_wmb();
4909                 if (netif_queue_stopped(dev) &&
4910                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4911                         netif_wake_queue(dev);
4912                 }
4913                 /*
4914                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4915                  * too close. Let's kick an extra TxPoll request when a burst
4916                  * of start_xmit activity is detected (if it is not detected,
4917                  * it is slow enough). -- FR
4918                  */
4919                 smp_rmb();
4920                 if (tp->cur_tx != dirty_tx)
4921                         RTL_W8(TxPoll, NPQ);
4922         }
4923 }
4924
4925 static inline int rtl8169_fragmented_frame(u32 status)
4926 {
4927         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4928 }
4929
4930 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4931 {
4932         u32 status = opts1 & RxProtoMask;
4933
4934         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4935             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4936                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4937         else
4938                 skb_checksum_none_assert(skb);
4939 }
4940
4941 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4942                                            struct rtl8169_private *tp,
4943                                            int pkt_size,
4944                                            dma_addr_t addr)
4945 {
4946         struct sk_buff *skb;
4947         struct device *d = &tp->pci_dev->dev;
4948
4949         data = rtl8169_align(data);
4950         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4951         prefetch(data);
4952         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4953         if (skb)
4954                 memcpy(skb->data, data, pkt_size);
4955         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4956
4957         return skb;
4958 }
4959
4960 static int rtl8169_rx_interrupt(struct net_device *dev,
4961                                 struct rtl8169_private *tp,
4962                                 void __iomem *ioaddr, u32 budget)
4963 {
4964         unsigned int cur_rx, rx_left;
4965         unsigned int count;
4966
4967         cur_rx = tp->cur_rx;
4968         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4969         rx_left = min(rx_left, budget);
4970
4971         for (; rx_left > 0; rx_left--, cur_rx++) {
4972                 unsigned int entry = cur_rx % NUM_RX_DESC;
4973                 struct RxDesc *desc = tp->RxDescArray + entry;
4974                 u32 status;
4975
4976                 rmb();
4977                 status = le32_to_cpu(desc->opts1);
4978
4979                 if (status & DescOwn)
4980                         break;
4981                 if (unlikely(status & RxRES)) {
4982                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4983                                    status);
4984                         dev->stats.rx_errors++;
4985                         if (status & (RxRWT | RxRUNT))
4986                                 dev->stats.rx_length_errors++;
4987                         if (status & RxCRC)
4988                                 dev->stats.rx_crc_errors++;
4989                         if (status & RxFOVF) {
4990                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4991                                 dev->stats.rx_fifo_errors++;
4992                         }
4993                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4994                 } else {
4995                         struct sk_buff *skb;
4996                         dma_addr_t addr = le64_to_cpu(desc->addr);
4997                         int pkt_size = (status & 0x00001FFF) - 4;
4998
4999                         /*
5000                          * The driver does not support incoming fragmented
5001                          * frames. They are seen as a symptom of over-mtu
5002                          * sized frames.
5003                          */
5004                         if (unlikely(rtl8169_fragmented_frame(status))) {
5005                                 dev->stats.rx_dropped++;
5006                                 dev->stats.rx_length_errors++;
5007                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5008                                 continue;
5009                         }
5010
5011                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5012                                                   tp, pkt_size, addr);
5013                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5014                         if (!skb) {
5015                                 dev->stats.rx_dropped++;
5016                                 continue;
5017                         }
5018
5019                         rtl8169_rx_csum(skb, status);
5020                         skb_put(skb, pkt_size);
5021                         skb->protocol = eth_type_trans(skb, dev);
5022
5023                         rtl8169_rx_vlan_tag(desc, skb);
5024
5025                         napi_gro_receive(&tp->napi, skb);
5026
5027                         dev->stats.rx_bytes += pkt_size;
5028                         dev->stats.rx_packets++;
5029                 }
5030
5031                 /* Work around for AMD plateform. */
5032                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5033                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5034                         desc->opts2 = 0;
5035                         cur_rx++;
5036                 }
5037         }
5038
5039         count = cur_rx - tp->cur_rx;
5040         tp->cur_rx = cur_rx;
5041
5042         tp->dirty_rx += count;
5043
5044         return count;
5045 }
5046
5047 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5048 {
5049         struct net_device *dev = dev_instance;
5050         struct rtl8169_private *tp = netdev_priv(dev);
5051         void __iomem *ioaddr = tp->mmio_addr;
5052         int handled = 0;
5053         int status;
5054
5055         /* loop handling interrupts until we have no new ones or
5056          * we hit a invalid/hotplug case.
5057          */
5058         status = RTL_R16(IntrStatus);
5059         while (status && status != 0xffff) {
5060                 handled = 1;
5061
5062                 /* Handle all of the error cases first. These will reset
5063                  * the chip, so just exit the loop.
5064                  */
5065                 if (unlikely(!netif_running(dev))) {
5066                         rtl8169_asic_down(ioaddr);
5067                         break;
5068                 }
5069
5070                 if (unlikely(status & RxFIFOOver)) {
5071                         switch (tp->mac_version) {
5072                         /* Work around for rx fifo overflow */
5073                         case RTL_GIGA_MAC_VER_11:
5074                         case RTL_GIGA_MAC_VER_22:
5075                         case RTL_GIGA_MAC_VER_26:
5076                                 netif_stop_queue(dev);
5077                                 rtl8169_tx_timeout(dev);
5078                                 goto done;
5079                         /* Testers needed. */
5080                         case RTL_GIGA_MAC_VER_17:
5081                         case RTL_GIGA_MAC_VER_19:
5082                         case RTL_GIGA_MAC_VER_20:
5083                         case RTL_GIGA_MAC_VER_21:
5084                         case RTL_GIGA_MAC_VER_23:
5085                         case RTL_GIGA_MAC_VER_24:
5086                         case RTL_GIGA_MAC_VER_27:
5087                         case RTL_GIGA_MAC_VER_28:
5088                         case RTL_GIGA_MAC_VER_31:
5089                         /* Experimental science. Pktgen proof. */
5090                         case RTL_GIGA_MAC_VER_12:
5091                         case RTL_GIGA_MAC_VER_25:
5092                                 if (status == RxFIFOOver)
5093                                         goto done;
5094                                 break;
5095                         default:
5096                                 break;
5097                         }
5098                 }
5099
5100                 if (unlikely(status & SYSErr)) {
5101                         rtl8169_pcierr_interrupt(dev);
5102                         break;
5103                 }
5104
5105                 if (status & LinkChg)
5106                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5107
5108                 /* We need to see the lastest version of tp->intr_mask to
5109                  * avoid ignoring an MSI interrupt and having to wait for
5110                  * another event which may never come.
5111                  */
5112                 smp_rmb();
5113                 if (status & tp->intr_mask & tp->napi_event) {
5114                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5115                         tp->intr_mask = ~tp->napi_event;
5116
5117                         if (likely(napi_schedule_prep(&tp->napi)))
5118                                 __napi_schedule(&tp->napi);
5119                         else
5120                                 netif_info(tp, intr, dev,
5121                                            "interrupt %04x in poll\n", status);
5122                 }
5123
5124                 /* We only get a new MSI interrupt when all active irq
5125                  * sources on the chip have been acknowledged. So, ack
5126                  * everything we've seen and check if new sources have become
5127                  * active to avoid blocking all interrupts from the chip.
5128                  */
5129                 RTL_W16(IntrStatus,
5130                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5131                 status = RTL_R16(IntrStatus);
5132         }
5133 done:
5134         return IRQ_RETVAL(handled);
5135 }
5136
5137 static int rtl8169_poll(struct napi_struct *napi, int budget)
5138 {
5139         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5140         struct net_device *dev = tp->dev;
5141         void __iomem *ioaddr = tp->mmio_addr;
5142         int work_done;
5143
5144         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5145         rtl8169_tx_interrupt(dev, tp, ioaddr);
5146
5147         if (work_done < budget) {
5148                 napi_complete(napi);
5149
5150                 /* We need for force the visibility of tp->intr_mask
5151                  * for other CPUs, as we can loose an MSI interrupt
5152                  * and potentially wait for a retransmit timeout if we don't.
5153                  * The posted write to IntrMask is safe, as it will
5154                  * eventually make it to the chip and we won't loose anything
5155                  * until it does.
5156                  */
5157                 tp->intr_mask = 0xffff;
5158                 wmb();
5159                 RTL_W16(IntrMask, tp->intr_event);
5160         }
5161
5162         return work_done;
5163 }
5164
5165 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5166 {
5167         struct rtl8169_private *tp = netdev_priv(dev);
5168
5169         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5170                 return;
5171
5172         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5173         RTL_W32(RxMissed, 0);
5174 }
5175
5176 static void rtl8169_down(struct net_device *dev)
5177 {
5178         struct rtl8169_private *tp = netdev_priv(dev);
5179         void __iomem *ioaddr = tp->mmio_addr;
5180
5181         del_timer_sync(&tp->timer);
5182
5183         netif_stop_queue(dev);
5184
5185         napi_disable(&tp->napi);
5186
5187         spin_lock_irq(&tp->lock);
5188
5189         rtl8169_asic_down(ioaddr);
5190         /*
5191          * At this point device interrupts can not be enabled in any function,
5192          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5193          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5194          */
5195         rtl8169_rx_missed(dev, ioaddr);
5196
5197         spin_unlock_irq(&tp->lock);
5198
5199         synchronize_irq(dev->irq);
5200
5201         /* Give a racing hard_start_xmit a few cycles to complete. */
5202         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5203
5204         rtl8169_tx_clear(tp);
5205
5206         rtl8169_rx_clear(tp);
5207
5208         rtl_pll_power_down(tp);
5209 }
5210
5211 static int rtl8169_close(struct net_device *dev)
5212 {
5213         struct rtl8169_private *tp = netdev_priv(dev);
5214         struct pci_dev *pdev = tp->pci_dev;
5215
5216         pm_runtime_get_sync(&pdev->dev);
5217
5218         /* Update counters before going down */
5219         rtl8169_update_counters(dev);
5220
5221         rtl8169_down(dev);
5222
5223         free_irq(dev->irq, dev);
5224
5225         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5226                           tp->RxPhyAddr);
5227         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5228                           tp->TxPhyAddr);
5229         tp->TxDescArray = NULL;
5230         tp->RxDescArray = NULL;
5231
5232         pm_runtime_put_sync(&pdev->dev);
5233
5234         return 0;
5235 }
5236
5237 static void rtl_set_rx_mode(struct net_device *dev)
5238 {
5239         struct rtl8169_private *tp = netdev_priv(dev);
5240         void __iomem *ioaddr = tp->mmio_addr;
5241         unsigned long flags;
5242         u32 mc_filter[2];       /* Multicast hash filter */
5243         int rx_mode;
5244         u32 tmp = 0;
5245
5246         if (dev->flags & IFF_PROMISC) {
5247                 /* Unconditionally log net taps. */
5248                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5249                 rx_mode =
5250                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5251                     AcceptAllPhys;
5252                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5253         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5254                    (dev->flags & IFF_ALLMULTI)) {
5255                 /* Too many to filter perfectly -- accept all multicasts. */
5256                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5257                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5258         } else {
5259                 struct netdev_hw_addr *ha;
5260
5261                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5262                 mc_filter[1] = mc_filter[0] = 0;
5263                 netdev_for_each_mc_addr(ha, dev) {
5264                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5265                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5266                         rx_mode |= AcceptMulticast;
5267                 }
5268         }
5269
5270         spin_lock_irqsave(&tp->lock, flags);
5271
5272         tmp = rtl8169_rx_config | rx_mode |
5273               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5274
5275         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5276                 u32 data = mc_filter[0];
5277
5278                 mc_filter[0] = swab32(mc_filter[1]);
5279                 mc_filter[1] = swab32(data);
5280         }
5281
5282         RTL_W32(MAR0 + 4, mc_filter[1]);
5283         RTL_W32(MAR0 + 0, mc_filter[0]);
5284
5285         RTL_W32(RxConfig, tmp);
5286
5287         spin_unlock_irqrestore(&tp->lock, flags);
5288 }
5289
5290 /**
5291  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5292  *  @dev: The Ethernet Device to get statistics for
5293  *
5294  *  Get TX/RX statistics for rtl8169
5295  */
5296 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5297 {
5298         struct rtl8169_private *tp = netdev_priv(dev);
5299         void __iomem *ioaddr = tp->mmio_addr;
5300         unsigned long flags;
5301
5302         if (netif_running(dev)) {
5303                 spin_lock_irqsave(&tp->lock, flags);
5304                 rtl8169_rx_missed(dev, ioaddr);
5305                 spin_unlock_irqrestore(&tp->lock, flags);
5306         }
5307
5308         return &dev->stats;
5309 }
5310
5311 static void rtl8169_net_suspend(struct net_device *dev)
5312 {
5313         struct rtl8169_private *tp = netdev_priv(dev);
5314
5315         if (!netif_running(dev))
5316                 return;
5317
5318         rtl_pll_power_down(tp);
5319
5320         netif_device_detach(dev);
5321         netif_stop_queue(dev);
5322 }
5323
5324 #ifdef CONFIG_PM
5325
5326 static int rtl8169_suspend(struct device *device)
5327 {
5328         struct pci_dev *pdev = to_pci_dev(device);
5329         struct net_device *dev = pci_get_drvdata(pdev);
5330
5331         rtl8169_net_suspend(dev);
5332
5333         return 0;
5334 }
5335
5336 static void __rtl8169_resume(struct net_device *dev)
5337 {
5338         struct rtl8169_private *tp = netdev_priv(dev);
5339
5340         netif_device_attach(dev);
5341
5342         rtl_pll_power_up(tp);
5343
5344         rtl8169_schedule_work(dev, rtl8169_reset_task);
5345 }
5346
5347 static int rtl8169_resume(struct device *device)
5348 {
5349         struct pci_dev *pdev = to_pci_dev(device);
5350         struct net_device *dev = pci_get_drvdata(pdev);
5351         struct rtl8169_private *tp = netdev_priv(dev);
5352
5353         rtl8169_init_phy(dev, tp);
5354
5355         if (netif_running(dev))
5356                 __rtl8169_resume(dev);
5357
5358         return 0;
5359 }
5360
5361 static int rtl8169_runtime_suspend(struct device *device)
5362 {
5363         struct pci_dev *pdev = to_pci_dev(device);
5364         struct net_device *dev = pci_get_drvdata(pdev);
5365         struct rtl8169_private *tp = netdev_priv(dev);
5366
5367         if (!tp->TxDescArray)
5368                 return 0;
5369
5370         spin_lock_irq(&tp->lock);
5371         tp->saved_wolopts = __rtl8169_get_wol(tp);
5372         __rtl8169_set_wol(tp, WAKE_ANY);
5373         spin_unlock_irq(&tp->lock);
5374
5375         rtl8169_net_suspend(dev);
5376
5377         return 0;
5378 }
5379
5380 static int rtl8169_runtime_resume(struct device *device)
5381 {
5382         struct pci_dev *pdev = to_pci_dev(device);
5383         struct net_device *dev = pci_get_drvdata(pdev);
5384         struct rtl8169_private *tp = netdev_priv(dev);
5385
5386         if (!tp->TxDescArray)
5387                 return 0;
5388
5389         spin_lock_irq(&tp->lock);
5390         __rtl8169_set_wol(tp, tp->saved_wolopts);
5391         tp->saved_wolopts = 0;
5392         spin_unlock_irq(&tp->lock);
5393
5394         rtl8169_init_phy(dev, tp);
5395
5396         __rtl8169_resume(dev);
5397
5398         return 0;
5399 }
5400
5401 static int rtl8169_runtime_idle(struct device *device)
5402 {
5403         struct pci_dev *pdev = to_pci_dev(device);
5404         struct net_device *dev = pci_get_drvdata(pdev);
5405         struct rtl8169_private *tp = netdev_priv(dev);
5406
5407         return tp->TxDescArray ? -EBUSY : 0;
5408 }
5409
5410 static const struct dev_pm_ops rtl8169_pm_ops = {
5411         .suspend                = rtl8169_suspend,
5412         .resume                 = rtl8169_resume,
5413         .freeze                 = rtl8169_suspend,
5414         .thaw                   = rtl8169_resume,
5415         .poweroff               = rtl8169_suspend,
5416         .restore                = rtl8169_resume,
5417         .runtime_suspend        = rtl8169_runtime_suspend,
5418         .runtime_resume         = rtl8169_runtime_resume,
5419         .runtime_idle           = rtl8169_runtime_idle,
5420 };
5421
5422 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5423
5424 #else /* !CONFIG_PM */
5425
5426 #define RTL8169_PM_OPS  NULL
5427
5428 #endif /* !CONFIG_PM */
5429
5430 static void rtl_shutdown(struct pci_dev *pdev)
5431 {
5432         struct net_device *dev = pci_get_drvdata(pdev);
5433         struct rtl8169_private *tp = netdev_priv(dev);
5434         void __iomem *ioaddr = tp->mmio_addr;
5435
5436         rtl8169_net_suspend(dev);
5437
5438         /* Restore original MAC address */
5439         rtl_rar_set(tp, dev->perm_addr);
5440
5441         spin_lock_irq(&tp->lock);
5442
5443         rtl8169_asic_down(ioaddr);
5444
5445         spin_unlock_irq(&tp->lock);
5446
5447         if (system_state == SYSTEM_POWER_OFF) {
5448                 /* WoL fails with some 8168 when the receiver is disabled. */
5449                 if (tp->features & RTL_FEATURE_WOL) {
5450                         pci_clear_master(pdev);
5451
5452                         RTL_W8(ChipCmd, CmdRxEnb);
5453                         /* PCI commit */
5454                         RTL_R8(ChipCmd);
5455                 }
5456
5457                 pci_wake_from_d3(pdev, true);
5458                 pci_set_power_state(pdev, PCI_D3hot);
5459         }
5460 }
5461
5462 static struct pci_driver rtl8169_pci_driver = {
5463         .name           = MODULENAME,
5464         .id_table       = rtl8169_pci_tbl,
5465         .probe          = rtl8169_init_one,
5466         .remove         = __devexit_p(rtl8169_remove_one),
5467         .shutdown       = rtl_shutdown,
5468         .driver.pm      = RTL8169_PM_OPS,
5469 };
5470
5471 static int __init rtl8169_init_module(void)
5472 {
5473         return pci_register_driver(&rtl8169_pci_driver);
5474 }
5475
5476 static void __exit rtl8169_cleanup_module(void)
5477 {
5478         pci_unregister_driver(&rtl8169_pci_driver);
5479 }
5480
5481 module_init(rtl8169_init_module);
5482 module_exit(rtl8169_cleanup_module);