2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
28 /* Version Information */
29 #define DRIVER_VERSION "v1.06.1 (2014/10/01)"
30 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
31 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
32 #define MODULENAME "r8152"
34 #define R8152_PHY_ID 32
36 #define PLA_IDR 0xc000
37 #define PLA_RCR 0xc010
38 #define PLA_RMS 0xc016
39 #define PLA_RXFIFO_CTRL0 0xc0a0
40 #define PLA_RXFIFO_CTRL1 0xc0a4
41 #define PLA_RXFIFO_CTRL2 0xc0a8
42 #define PLA_FMC 0xc0b4
43 #define PLA_CFG_WOL 0xc0b6
44 #define PLA_TEREDO_CFG 0xc0bc
45 #define PLA_MAR 0xcd00
46 #define PLA_BACKUP 0xd000
47 #define PAL_BDC_CR 0xd1a0
48 #define PLA_TEREDO_TIMER 0xd2cc
49 #define PLA_REALWOW_TIMER 0xd2e8
50 #define PLA_LEDSEL 0xdd90
51 #define PLA_LED_FEATURE 0xdd92
52 #define PLA_PHYAR 0xde00
53 #define PLA_BOOT_CTRL 0xe004
54 #define PLA_GPHY_INTR_IMR 0xe022
55 #define PLA_EEE_CR 0xe040
56 #define PLA_EEEP_CR 0xe080
57 #define PLA_MAC_PWR_CTRL 0xe0c0
58 #define PLA_MAC_PWR_CTRL2 0xe0ca
59 #define PLA_MAC_PWR_CTRL3 0xe0cc
60 #define PLA_MAC_PWR_CTRL4 0xe0ce
61 #define PLA_WDT6_CTRL 0xe428
62 #define PLA_TCR0 0xe610
63 #define PLA_TCR1 0xe612
64 #define PLA_MTPS 0xe615
65 #define PLA_TXFIFO_CTRL 0xe618
66 #define PLA_RSTTALLY 0xe800
68 #define PLA_CRWECR 0xe81c
69 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
70 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
71 #define PLA_CONFIG5 0xe822
72 #define PLA_PHY_PWR 0xe84c
73 #define PLA_OOB_CTRL 0xe84f
74 #define PLA_CPCR 0xe854
75 #define PLA_MISC_0 0xe858
76 #define PLA_MISC_1 0xe85a
77 #define PLA_OCP_GPHY_BASE 0xe86c
78 #define PLA_TALLYCNT 0xe890
79 #define PLA_SFF_STS_7 0xe8de
80 #define PLA_PHYSTATUS 0xe908
81 #define PLA_BP_BA 0xfc26
82 #define PLA_BP_0 0xfc28
83 #define PLA_BP_1 0xfc2a
84 #define PLA_BP_2 0xfc2c
85 #define PLA_BP_3 0xfc2e
86 #define PLA_BP_4 0xfc30
87 #define PLA_BP_5 0xfc32
88 #define PLA_BP_6 0xfc34
89 #define PLA_BP_7 0xfc36
90 #define PLA_BP_EN 0xfc38
92 #define USB_U2P3_CTRL 0xb460
93 #define USB_DEV_STAT 0xb808
94 #define USB_USB_CTRL 0xd406
95 #define USB_PHY_CTRL 0xd408
96 #define USB_TX_AGG 0xd40a
97 #define USB_RX_BUF_TH 0xd40c
98 #define USB_USB_TIMER 0xd428
99 #define USB_RX_EARLY_AGG 0xd42c
100 #define USB_PM_CTRL_STATUS 0xd432
101 #define USB_TX_DMA 0xd434
102 #define USB_TOLERANCE 0xd490
103 #define USB_LPM_CTRL 0xd41a
104 #define USB_UPS_CTRL 0xd800
105 #define USB_MISC_0 0xd81a
106 #define USB_POWER_CUT 0xd80a
107 #define USB_AFE_CTRL2 0xd824
108 #define USB_WDT11_CTRL 0xe43c
109 #define USB_BP_BA 0xfc26
110 #define USB_BP_0 0xfc28
111 #define USB_BP_1 0xfc2a
112 #define USB_BP_2 0xfc2c
113 #define USB_BP_3 0xfc2e
114 #define USB_BP_4 0xfc30
115 #define USB_BP_5 0xfc32
116 #define USB_BP_6 0xfc34
117 #define USB_BP_7 0xfc36
118 #define USB_BP_EN 0xfc38
121 #define OCP_ALDPS_CONFIG 0x2010
122 #define OCP_EEE_CONFIG1 0x2080
123 #define OCP_EEE_CONFIG2 0x2092
124 #define OCP_EEE_CONFIG3 0x2094
125 #define OCP_BASE_MII 0xa400
126 #define OCP_EEE_AR 0xa41a
127 #define OCP_EEE_DATA 0xa41c
128 #define OCP_PHY_STATUS 0xa420
129 #define OCP_POWER_CFG 0xa430
130 #define OCP_EEE_CFG 0xa432
131 #define OCP_SRAM_ADDR 0xa436
132 #define OCP_SRAM_DATA 0xa438
133 #define OCP_DOWN_SPEED 0xa442
134 #define OCP_EEE_ABLE 0xa5c4
135 #define OCP_EEE_ADV 0xa5d0
136 #define OCP_EEE_LPABLE 0xa5d2
137 #define OCP_ADC_CFG 0xbc06
140 #define SRAM_LPF_CFG 0x8012
141 #define SRAM_10M_AMP1 0x8080
142 #define SRAM_10M_AMP2 0x8082
143 #define SRAM_IMPEDANCE 0x8084
146 #define RCR_AAP 0x00000001
147 #define RCR_APM 0x00000002
148 #define RCR_AM 0x00000004
149 #define RCR_AB 0x00000008
150 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
152 /* PLA_RXFIFO_CTRL0 */
153 #define RXFIFO_THR1_NORMAL 0x00080002
154 #define RXFIFO_THR1_OOB 0x01800003
156 /* PLA_RXFIFO_CTRL1 */
157 #define RXFIFO_THR2_FULL 0x00000060
158 #define RXFIFO_THR2_HIGH 0x00000038
159 #define RXFIFO_THR2_OOB 0x0000004a
160 #define RXFIFO_THR2_NORMAL 0x00a0
162 /* PLA_RXFIFO_CTRL2 */
163 #define RXFIFO_THR3_FULL 0x00000078
164 #define RXFIFO_THR3_HIGH 0x00000048
165 #define RXFIFO_THR3_OOB 0x0000005a
166 #define RXFIFO_THR3_NORMAL 0x0110
168 /* PLA_TXFIFO_CTRL */
169 #define TXFIFO_THR_NORMAL 0x00400008
170 #define TXFIFO_THR_NORMAL2 0x01000008
173 #define FMC_FCR_MCU_EN 0x0001
176 #define EEEP_CR_EEEP_TX 0x0002
179 #define WDT6_SET_MODE 0x0010
182 #define TCR0_TX_EMPTY 0x0800
183 #define TCR0_AUTO_FIFO 0x0080
186 #define VERSION_MASK 0x7cf0
189 #define MTPS_JUMBO (12 * 1024 / 64)
190 #define MTPS_DEFAULT (6 * 1024 / 64)
193 #define TALLY_RESET 0x0001
201 #define CRWECR_NORAML 0x00
202 #define CRWECR_CONFIG 0xc0
205 #define NOW_IS_OOB 0x80
206 #define TXFIFO_EMPTY 0x20
207 #define RXFIFO_EMPTY 0x10
208 #define LINK_LIST_READY 0x02
209 #define DIS_MCU_CLROOB 0x01
210 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
213 #define RXDY_GATED_EN 0x0008
216 #define RE_INIT_LL 0x8000
217 #define MCU_BORW_EN 0x4000
220 #define CPCR_RX_VLAN 0x0040
223 #define MAGIC_EN 0x0001
226 #define TEREDO_SEL 0x8000
227 #define TEREDO_WAKE_MASK 0x7f00
228 #define TEREDO_RS_EVENT_MASK 0x00fe
229 #define OOB_TEREDO_EN 0x0001
232 #define ALDPS_PROXY_MODE 0x0001
235 #define LINK_ON_WAKE_EN 0x0010
236 #define LINK_OFF_WAKE_EN 0x0008
239 #define BWF_EN 0x0040
240 #define MWF_EN 0x0020
241 #define UWF_EN 0x0010
242 #define LAN_WAKE_EN 0x0002
244 /* PLA_LED_FEATURE */
245 #define LED_MODE_MASK 0x0700
248 #define TX_10M_IDLE_EN 0x0080
249 #define PFM_PWM_SWITCH 0x0040
251 /* PLA_MAC_PWR_CTRL */
252 #define D3_CLK_GATED_EN 0x00004000
253 #define MCU_CLK_RATIO 0x07010f07
254 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
255 #define ALDPS_SPDWN_RATIO 0x0f87
257 /* PLA_MAC_PWR_CTRL2 */
258 #define EEE_SPDWN_RATIO 0x8007
260 /* PLA_MAC_PWR_CTRL3 */
261 #define PKT_AVAIL_SPDWN_EN 0x0100
262 #define SUSPEND_SPDWN_EN 0x0004
263 #define U1U2_SPDWN_EN 0x0002
264 #define L1_SPDWN_EN 0x0001
266 /* PLA_MAC_PWR_CTRL4 */
267 #define PWRSAVE_SPDWN_EN 0x1000
268 #define RXDV_SPDWN_EN 0x0800
269 #define TX10MIDLE_EN 0x0100
270 #define TP100_SPDWN_EN 0x0020
271 #define TP500_SPDWN_EN 0x0010
272 #define TP1000_SPDWN_EN 0x0008
273 #define EEE_SPDWN_EN 0x0001
275 /* PLA_GPHY_INTR_IMR */
276 #define GPHY_STS_MSK 0x0001
277 #define SPEED_DOWN_MSK 0x0002
278 #define SPDWN_RXDV_MSK 0x0004
279 #define SPDWN_LINKCHG_MSK 0x0008
282 #define PHYAR_FLAG 0x80000000
285 #define EEE_RX_EN 0x0001
286 #define EEE_TX_EN 0x0002
289 #define AUTOLOAD_DONE 0x0002
292 #define STAT_SPEED_MASK 0x0006
293 #define STAT_SPEED_HIGH 0x0000
294 #define STAT_SPEED_FULL 0x0002
297 #define TX_AGG_MAX_THRESHOLD 0x03
300 #define RX_THR_SUPPER 0x0c350180
301 #define RX_THR_HIGH 0x7a120180
302 #define RX_THR_SLOW 0xffff0180
305 #define TEST_MODE_DISABLE 0x00000001
306 #define TX_SIZE_ADJUST1 0x00000100
309 #define POWER_CUT 0x0100
311 /* USB_PM_CTRL_STATUS */
312 #define RESUME_INDICATE 0x0001
315 #define RX_AGG_DISABLE 0x0010
318 #define U2P3_ENABLE 0x0001
321 #define PWR_EN 0x0001
322 #define PHASE2_EN 0x0008
325 #define PCUT_STATUS 0x0001
327 /* USB_RX_EARLY_AGG */
328 #define EARLY_AGG_SUPPER 0x0e832981
329 #define EARLY_AGG_HIGH 0x0e837a12
330 #define EARLY_AGG_SLOW 0x0e83ffff
333 #define TIMER11_EN 0x0001
336 #define LPM_TIMER_MASK 0x0c
337 #define LPM_TIMER_500MS 0x04 /* 500 ms */
338 #define LPM_TIMER_500US 0x0c /* 500 us */
341 #define SEN_VAL_MASK 0xf800
342 #define SEN_VAL_NORMAL 0xa000
343 #define SEL_RXIDLE 0x0100
345 /* OCP_ALDPS_CONFIG */
346 #define ENPWRSAVE 0x8000
347 #define ENPDNPS 0x0200
348 #define LINKENA 0x0100
349 #define DIS_SDSAVE 0x0010
352 #define PHY_STAT_MASK 0x0007
353 #define PHY_STAT_LAN_ON 3
354 #define PHY_STAT_PWRDN 5
357 #define EEE_CLKDIV_EN 0x8000
358 #define EN_ALDPS 0x0004
359 #define EN_10M_PLLOFF 0x0001
361 /* OCP_EEE_CONFIG1 */
362 #define RG_TXLPI_MSK_HFDUP 0x8000
363 #define RG_MATCLR_EN 0x4000
364 #define EEE_10_CAP 0x2000
365 #define EEE_NWAY_EN 0x1000
366 #define TX_QUIET_EN 0x0200
367 #define RX_QUIET_EN 0x0100
368 #define sd_rise_time_mask 0x0070
369 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
370 #define RG_RXLPI_MSK_HFDUP 0x0008
371 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
373 /* OCP_EEE_CONFIG2 */
374 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
375 #define RG_DACQUIET_EN 0x0400
376 #define RG_LDVQUIET_EN 0x0200
377 #define RG_CKRSEL 0x0020
378 #define RG_EEEPRG_EN 0x0010
380 /* OCP_EEE_CONFIG3 */
381 #define fast_snr_mask 0xff80
382 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
383 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
384 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
387 /* bit[15:14] function */
388 #define FUN_ADDR 0x0000
389 #define FUN_DATA 0x4000
390 /* bit[4:0] device addr */
393 #define CTAP_SHORT_EN 0x0040
394 #define EEE10_EN 0x0010
397 #define EN_10M_BGOFF 0x0080
400 #define CKADSEL_L 0x0100
401 #define ADC_EN 0x0080
402 #define EN_EMI_L 0x0040
405 #define LPF_AUTO_TUNE 0x8000
408 #define GDAC_IB_UPALL 0x0008
411 #define AMP_DN 0x0200
414 #define RX_DRIVING_MASK 0x6000
416 enum rtl_register_content {
424 #define RTL8152_MAX_TX 4
425 #define RTL8152_MAX_RX 10
431 #define INTR_LINK 0x0004
433 #define RTL8152_REQT_READ 0xc0
434 #define RTL8152_REQT_WRITE 0x40
435 #define RTL8152_REQ_GET_REGS 0x05
436 #define RTL8152_REQ_SET_REGS 0x05
438 #define BYTE_EN_DWORD 0xff
439 #define BYTE_EN_WORD 0x33
440 #define BYTE_EN_BYTE 0x11
441 #define BYTE_EN_SIX_BYTES 0x3f
442 #define BYTE_EN_START_MASK 0x0f
443 #define BYTE_EN_END_MASK 0xf0
445 #define RTL8153_MAX_PACKET 9216 /* 9K */
446 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
447 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
448 #define RTL8153_RMS RTL8153_MAX_PACKET
449 #define RTL8152_TX_TIMEOUT (5 * HZ)
462 /* Define these values to match your device */
463 #define VENDOR_ID_REALTEK 0x0bda
464 #define PRODUCT_ID_RTL8152 0x8152
465 #define PRODUCT_ID_RTL8153 0x8153
467 #define VENDOR_ID_SAMSUNG 0x04e8
468 #define PRODUCT_ID_SAMSUNG 0xa101
470 #define MCU_TYPE_PLA 0x0100
471 #define MCU_TYPE_USB 0x0000
473 #define REALTEK_USB_DEVICE(vend, prod) \
474 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
476 struct tally_counter {
483 __le32 tx_one_collision;
484 __le32 tx_multi_collision;
494 #define RX_LEN_MASK 0x7fff
497 #define RD_UDP_CS (1 << 23)
498 #define RD_TCP_CS (1 << 22)
499 #define RD_IPV6_CS (1 << 20)
500 #define RD_IPV4_CS (1 << 19)
503 #define IPF (1 << 23) /* IP checksum fail */
504 #define UDPF (1 << 22) /* UDP checksum fail */
505 #define TCPF (1 << 21) /* TCP checksum fail */
506 #define RX_VLAN_TAG (1 << 16)
515 #define TX_FS (1 << 31) /* First segment of a packet */
516 #define TX_LS (1 << 30) /* Final segment of a packet */
517 #define GTSENDV4 (1 << 28)
518 #define GTSENDV6 (1 << 27)
519 #define GTTCPHO_SHIFT 18
520 #define GTTCPHO_MAX 0x7fU
521 #define TX_LEN_MAX 0x3ffffU
524 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
525 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
526 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
527 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
529 #define MSS_MAX 0x7ffU
530 #define TCPHO_SHIFT 17
531 #define TCPHO_MAX 0x7ffU
532 #define TX_VLAN_TAG (1 << 16)
538 struct list_head list;
540 struct r8152 *context;
546 struct list_head list;
548 struct r8152 *context;
557 struct usb_device *udev;
558 struct tasklet_struct tl;
559 struct usb_interface *intf;
560 struct net_device *netdev;
561 struct urb *intr_urb;
562 struct tx_agg tx_info[RTL8152_MAX_TX];
563 struct rx_agg rx_info[RTL8152_MAX_RX];
564 struct list_head rx_done, tx_free;
565 struct sk_buff_head tx_queue;
566 spinlock_t rx_lock, tx_lock;
567 struct delayed_work schedule;
568 struct mii_if_info mii;
571 void (*init)(struct r8152 *);
572 int (*enable)(struct r8152 *);
573 void (*disable)(struct r8152 *);
574 void (*up)(struct r8152 *);
575 void (*down)(struct r8152 *);
576 void (*unload)(struct r8152 *);
577 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
578 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
607 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
608 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
610 static const int multicast_filter_limit = 32;
611 static unsigned int agg_buf_sz = 16384;
613 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
614 VLAN_ETH_HLEN - VLAN_HLEN)
617 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
622 tmp = kmalloc(size, GFP_KERNEL);
626 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
627 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
628 value, index, tmp, size, 500);
630 memcpy(data, tmp, size);
637 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
642 tmp = kmemdup(data, size, GFP_KERNEL);
646 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
647 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
648 value, index, tmp, size, 500);
655 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
656 void *data, u16 type)
661 if (test_bit(RTL8152_UNPLUG, &tp->flags))
664 /* both size and indix must be 4 bytes align */
665 if ((size & 3) || !size || (index & 3) || !data)
668 if ((u32)index + (u32)size > 0xffff)
673 ret = get_registers(tp, index, type, limit, data);
681 ret = get_registers(tp, index, type, size, data);
695 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
696 u16 size, void *data, u16 type)
699 u16 byteen_start, byteen_end, byen;
702 if (test_bit(RTL8152_UNPLUG, &tp->flags))
705 /* both size and indix must be 4 bytes align */
706 if ((size & 3) || !size || (index & 3) || !data)
709 if ((u32)index + (u32)size > 0xffff)
712 byteen_start = byteen & BYTE_EN_START_MASK;
713 byteen_end = byteen & BYTE_EN_END_MASK;
715 byen = byteen_start | (byteen_start << 4);
716 ret = set_registers(tp, index, type | byen, 4, data);
729 ret = set_registers(tp, index,
730 type | BYTE_EN_DWORD,
739 ret = set_registers(tp, index,
740 type | BYTE_EN_DWORD,
752 byen = byteen_end | (byteen_end >> 4);
753 ret = set_registers(tp, index, type | byen, 4, data);
763 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
765 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
769 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
771 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
775 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
777 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
781 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
783 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
786 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
790 generic_ocp_read(tp, index, sizeof(data), &data, type);
792 return __le32_to_cpu(data);
795 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
797 __le32 tmp = __cpu_to_le32(data);
799 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
802 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
806 u8 shift = index & 2;
810 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
812 data = __le32_to_cpu(tmp);
813 data >>= (shift * 8);
819 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
823 u16 byen = BYTE_EN_WORD;
824 u8 shift = index & 2;
830 mask <<= (shift * 8);
831 data <<= (shift * 8);
835 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
837 data |= __le32_to_cpu(tmp) & ~mask;
838 tmp = __cpu_to_le32(data);
840 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
843 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
847 u8 shift = index & 3;
851 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
853 data = __le32_to_cpu(tmp);
854 data >>= (shift * 8);
860 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
864 u16 byen = BYTE_EN_BYTE;
865 u8 shift = index & 3;
871 mask <<= (shift * 8);
872 data <<= (shift * 8);
876 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
878 data |= __le32_to_cpu(tmp) & ~mask;
879 tmp = __cpu_to_le32(data);
881 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
884 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
886 u16 ocp_base, ocp_index;
888 ocp_base = addr & 0xf000;
889 if (ocp_base != tp->ocp_base) {
890 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
891 tp->ocp_base = ocp_base;
894 ocp_index = (addr & 0x0fff) | 0xb000;
895 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
898 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
900 u16 ocp_base, ocp_index;
902 ocp_base = addr & 0xf000;
903 if (ocp_base != tp->ocp_base) {
904 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
905 tp->ocp_base = ocp_base;
908 ocp_index = (addr & 0x0fff) | 0xb000;
909 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
912 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
914 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
917 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
919 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
922 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
924 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
925 ocp_reg_write(tp, OCP_SRAM_DATA, data);
928 static u16 sram_read(struct r8152 *tp, u16 addr)
930 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
931 return ocp_reg_read(tp, OCP_SRAM_DATA);
934 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
936 struct r8152 *tp = netdev_priv(netdev);
939 if (test_bit(RTL8152_UNPLUG, &tp->flags))
942 if (phy_id != R8152_PHY_ID)
945 ret = r8152_mdio_read(tp, reg);
951 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
953 struct r8152 *tp = netdev_priv(netdev);
955 if (test_bit(RTL8152_UNPLUG, &tp->flags))
958 if (phy_id != R8152_PHY_ID)
961 r8152_mdio_write(tp, reg, val);
965 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
967 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
969 struct r8152 *tp = netdev_priv(netdev);
970 struct sockaddr *addr = p;
971 int ret = -EADDRNOTAVAIL;
973 if (!is_valid_ether_addr(addr->sa_data))
976 ret = usb_autopm_get_interface(tp->intf);
980 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
982 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
983 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
984 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
986 usb_autopm_put_interface(tp->intf);
991 static int set_ethernet_addr(struct r8152 *tp)
993 struct net_device *dev = tp->netdev;
997 if (tp->version == RTL_VER_01)
998 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1000 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1003 netif_err(tp, probe, dev, "Get ether addr fail\n");
1004 } else if (!is_valid_ether_addr(sa.sa_data)) {
1005 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1007 eth_hw_addr_random(dev);
1008 ether_addr_copy(sa.sa_data, dev->dev_addr);
1009 ret = rtl8152_set_mac_address(dev, &sa);
1010 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1013 if (tp->version == RTL_VER_01)
1014 ether_addr_copy(dev->dev_addr, sa.sa_data);
1016 ret = rtl8152_set_mac_address(dev, &sa);
1022 static void read_bulk_callback(struct urb *urb)
1024 struct net_device *netdev;
1025 int status = urb->status;
1038 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1041 if (!test_bit(WORK_ENABLE, &tp->flags))
1044 netdev = tp->netdev;
1046 /* When link down, the driver would cancel all bulks. */
1047 /* This avoid the re-submitting bulk */
1048 if (!netif_carrier_ok(netdev))
1051 usb_mark_last_busy(tp->udev);
1055 if (urb->actual_length < ETH_ZLEN)
1058 spin_lock(&tp->rx_lock);
1059 list_add_tail(&agg->list, &tp->rx_done);
1060 spin_unlock(&tp->rx_lock);
1061 tasklet_schedule(&tp->tl);
1064 set_bit(RTL8152_UNPLUG, &tp->flags);
1065 netif_device_detach(tp->netdev);
1068 return; /* the urb is in unlink state */
1070 if (net_ratelimit())
1071 netdev_warn(netdev, "maybe reset is needed?\n");
1074 if (net_ratelimit())
1075 netdev_warn(netdev, "Rx status %d\n", status);
1079 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1080 if (result == -ENODEV) {
1081 netif_device_detach(tp->netdev);
1082 } else if (result) {
1083 spin_lock(&tp->rx_lock);
1084 list_add_tail(&agg->list, &tp->rx_done);
1085 spin_unlock(&tp->rx_lock);
1086 tasklet_schedule(&tp->tl);
1090 static void write_bulk_callback(struct urb *urb)
1092 struct net_device_stats *stats;
1093 struct net_device *netdev;
1096 int status = urb->status;
1106 netdev = tp->netdev;
1107 stats = &netdev->stats;
1109 if (net_ratelimit())
1110 netdev_warn(netdev, "Tx status %d\n", status);
1111 stats->tx_errors += agg->skb_num;
1113 stats->tx_packets += agg->skb_num;
1114 stats->tx_bytes += agg->skb_len;
1117 spin_lock(&tp->tx_lock);
1118 list_add_tail(&agg->list, &tp->tx_free);
1119 spin_unlock(&tp->tx_lock);
1121 usb_autopm_put_interface_async(tp->intf);
1123 if (!netif_carrier_ok(netdev))
1126 if (!test_bit(WORK_ENABLE, &tp->flags))
1129 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1132 if (!skb_queue_empty(&tp->tx_queue))
1133 tasklet_schedule(&tp->tl);
1136 static void intr_callback(struct urb *urb)
1140 int status = urb->status;
1147 if (!test_bit(WORK_ENABLE, &tp->flags))
1150 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1154 case 0: /* success */
1156 case -ECONNRESET: /* unlink */
1158 netif_device_detach(tp->netdev);
1162 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1164 /* -EPIPE: should clear the halt */
1166 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1170 d = urb->transfer_buffer;
1171 if (INTR_LINK & __le16_to_cpu(d[0])) {
1172 if (!(tp->speed & LINK_STATUS)) {
1173 set_bit(RTL8152_LINK_CHG, &tp->flags);
1174 schedule_delayed_work(&tp->schedule, 0);
1177 if (tp->speed & LINK_STATUS) {
1178 set_bit(RTL8152_LINK_CHG, &tp->flags);
1179 schedule_delayed_work(&tp->schedule, 0);
1184 res = usb_submit_urb(urb, GFP_ATOMIC);
1186 netif_device_detach(tp->netdev);
1188 netif_err(tp, intr, tp->netdev,
1189 "can't resubmit intr, status %d\n", res);
1192 static inline void *rx_agg_align(void *data)
1194 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1197 static inline void *tx_agg_align(void *data)
1199 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1202 static void free_all_mem(struct r8152 *tp)
1206 for (i = 0; i < RTL8152_MAX_RX; i++) {
1207 usb_free_urb(tp->rx_info[i].urb);
1208 tp->rx_info[i].urb = NULL;
1210 kfree(tp->rx_info[i].buffer);
1211 tp->rx_info[i].buffer = NULL;
1212 tp->rx_info[i].head = NULL;
1215 for (i = 0; i < RTL8152_MAX_TX; i++) {
1216 usb_free_urb(tp->tx_info[i].urb);
1217 tp->tx_info[i].urb = NULL;
1219 kfree(tp->tx_info[i].buffer);
1220 tp->tx_info[i].buffer = NULL;
1221 tp->tx_info[i].head = NULL;
1224 usb_free_urb(tp->intr_urb);
1225 tp->intr_urb = NULL;
1227 kfree(tp->intr_buff);
1228 tp->intr_buff = NULL;
1231 static int alloc_all_mem(struct r8152 *tp)
1233 struct net_device *netdev = tp->netdev;
1234 struct usb_interface *intf = tp->intf;
1235 struct usb_host_interface *alt = intf->cur_altsetting;
1236 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1241 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1243 spin_lock_init(&tp->rx_lock);
1244 spin_lock_init(&tp->tx_lock);
1245 INIT_LIST_HEAD(&tp->rx_done);
1246 INIT_LIST_HEAD(&tp->tx_free);
1247 skb_queue_head_init(&tp->tx_queue);
1249 for (i = 0; i < RTL8152_MAX_RX; i++) {
1250 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1254 if (buf != rx_agg_align(buf)) {
1256 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1262 urb = usb_alloc_urb(0, GFP_KERNEL);
1268 INIT_LIST_HEAD(&tp->rx_info[i].list);
1269 tp->rx_info[i].context = tp;
1270 tp->rx_info[i].urb = urb;
1271 tp->rx_info[i].buffer = buf;
1272 tp->rx_info[i].head = rx_agg_align(buf);
1275 for (i = 0; i < RTL8152_MAX_TX; i++) {
1276 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1280 if (buf != tx_agg_align(buf)) {
1282 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1288 urb = usb_alloc_urb(0, GFP_KERNEL);
1294 INIT_LIST_HEAD(&tp->tx_info[i].list);
1295 tp->tx_info[i].context = tp;
1296 tp->tx_info[i].urb = urb;
1297 tp->tx_info[i].buffer = buf;
1298 tp->tx_info[i].head = tx_agg_align(buf);
1300 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1303 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1307 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1311 tp->intr_interval = (int)ep_intr->desc.bInterval;
1312 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1313 tp->intr_buff, INTBUFSIZE, intr_callback,
1314 tp, tp->intr_interval);
1323 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1325 struct tx_agg *agg = NULL;
1326 unsigned long flags;
1328 if (list_empty(&tp->tx_free))
1331 spin_lock_irqsave(&tp->tx_lock, flags);
1332 if (!list_empty(&tp->tx_free)) {
1333 struct list_head *cursor;
1335 cursor = tp->tx_free.next;
1336 list_del_init(cursor);
1337 agg = list_entry(cursor, struct tx_agg, list);
1339 spin_unlock_irqrestore(&tp->tx_lock, flags);
1344 static inline __be16 get_protocol(struct sk_buff *skb)
1348 if (skb->protocol == htons(ETH_P_8021Q))
1349 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1351 protocol = skb->protocol;
1356 /* r8152_csum_workaround()
1357 * The hw limites the value the transport offset. When the offset is out of the
1358 * range, calculate the checksum by sw.
1360 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1361 struct sk_buff_head *list)
1363 if (skb_shinfo(skb)->gso_size) {
1364 netdev_features_t features = tp->netdev->features;
1365 struct sk_buff_head seg_list;
1366 struct sk_buff *segs, *nskb;
1368 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1369 segs = skb_gso_segment(skb, features);
1370 if (IS_ERR(segs) || !segs)
1373 __skb_queue_head_init(&seg_list);
1379 __skb_queue_tail(&seg_list, nskb);
1382 skb_queue_splice(&seg_list, list);
1384 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1385 if (skb_checksum_help(skb) < 0)
1388 __skb_queue_head(list, skb);
1390 struct net_device_stats *stats;
1393 stats = &tp->netdev->stats;
1394 stats->tx_dropped++;
1399 /* msdn_giant_send_check()
1400 * According to the document of microsoft, the TCP Pseudo Header excludes the
1401 * packet length for IPv6 TCP large packets.
1403 static int msdn_giant_send_check(struct sk_buff *skb)
1405 const struct ipv6hdr *ipv6h;
1409 ret = skb_cow_head(skb, 0);
1413 ipv6h = ipv6_hdr(skb);
1417 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1422 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1424 if (vlan_tx_tag_present(skb)) {
1427 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1428 desc->opts2 |= cpu_to_le32(opts2);
1432 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1434 u32 opts2 = le32_to_cpu(desc->opts2);
1436 if (opts2 & RX_VLAN_TAG)
1437 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1438 swab16(opts2 & 0xffff));
1441 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1442 struct sk_buff *skb, u32 len, u32 transport_offset)
1444 u32 mss = skb_shinfo(skb)->gso_size;
1445 u32 opts1, opts2 = 0;
1446 int ret = TX_CSUM_SUCCESS;
1448 WARN_ON_ONCE(len > TX_LEN_MAX);
1450 opts1 = len | TX_FS | TX_LS;
1453 if (transport_offset > GTTCPHO_MAX) {
1454 netif_warn(tp, tx_err, tp->netdev,
1455 "Invalid transport offset 0x%x for TSO\n",
1461 switch (get_protocol(skb)) {
1462 case htons(ETH_P_IP):
1466 case htons(ETH_P_IPV6):
1467 if (msdn_giant_send_check(skb)) {
1479 opts1 |= transport_offset << GTTCPHO_SHIFT;
1480 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1481 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1484 if (transport_offset > TCPHO_MAX) {
1485 netif_warn(tp, tx_err, tp->netdev,
1486 "Invalid transport offset 0x%x\n",
1492 switch (get_protocol(skb)) {
1493 case htons(ETH_P_IP):
1495 ip_protocol = ip_hdr(skb)->protocol;
1498 case htons(ETH_P_IPV6):
1500 ip_protocol = ipv6_hdr(skb)->nexthdr;
1504 ip_protocol = IPPROTO_RAW;
1508 if (ip_protocol == IPPROTO_TCP)
1510 else if (ip_protocol == IPPROTO_UDP)
1515 opts2 |= transport_offset << TCPHO_SHIFT;
1518 desc->opts2 = cpu_to_le32(opts2);
1519 desc->opts1 = cpu_to_le32(opts1);
1525 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1527 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1531 __skb_queue_head_init(&skb_head);
1532 spin_lock(&tx_queue->lock);
1533 skb_queue_splice_init(tx_queue, &skb_head);
1534 spin_unlock(&tx_queue->lock);
1536 tx_data = agg->head;
1539 remain = agg_buf_sz;
1541 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1542 struct tx_desc *tx_desc;
1543 struct sk_buff *skb;
1547 skb = __skb_dequeue(&skb_head);
1551 len = skb->len + sizeof(*tx_desc);
1554 __skb_queue_head(&skb_head, skb);
1558 tx_data = tx_agg_align(tx_data);
1559 tx_desc = (struct tx_desc *)tx_data;
1561 offset = (u32)skb_transport_offset(skb);
1563 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1564 r8152_csum_workaround(tp, skb, &skb_head);
1568 rtl_tx_vlan_tag(tx_desc, skb);
1570 tx_data += sizeof(*tx_desc);
1573 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1574 struct net_device_stats *stats = &tp->netdev->stats;
1576 stats->tx_dropped++;
1577 dev_kfree_skb_any(skb);
1578 tx_data -= sizeof(*tx_desc);
1583 agg->skb_len += len;
1586 dev_kfree_skb_any(skb);
1588 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1591 if (!skb_queue_empty(&skb_head)) {
1592 spin_lock(&tx_queue->lock);
1593 skb_queue_splice(&skb_head, tx_queue);
1594 spin_unlock(&tx_queue->lock);
1597 netif_tx_lock(tp->netdev);
1599 if (netif_queue_stopped(tp->netdev) &&
1600 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1601 netif_wake_queue(tp->netdev);
1603 netif_tx_unlock(tp->netdev);
1605 ret = usb_autopm_get_interface_async(tp->intf);
1609 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1610 agg->head, (int)(tx_data - (u8 *)agg->head),
1611 (usb_complete_t)write_bulk_callback, agg);
1613 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1615 usb_autopm_put_interface_async(tp->intf);
1621 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1623 u8 checksum = CHECKSUM_NONE;
1626 if (tp->version == RTL_VER_01)
1629 opts2 = le32_to_cpu(rx_desc->opts2);
1630 opts3 = le32_to_cpu(rx_desc->opts3);
1632 if (opts2 & RD_IPV4_CS) {
1634 checksum = CHECKSUM_NONE;
1635 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1636 checksum = CHECKSUM_NONE;
1637 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1638 checksum = CHECKSUM_NONE;
1640 checksum = CHECKSUM_UNNECESSARY;
1641 } else if (RD_IPV6_CS) {
1642 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1643 checksum = CHECKSUM_UNNECESSARY;
1644 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1645 checksum = CHECKSUM_UNNECESSARY;
1652 static void rx_bottom(struct r8152 *tp)
1654 unsigned long flags;
1655 struct list_head *cursor, *next, rx_queue;
1657 if (list_empty(&tp->rx_done))
1660 INIT_LIST_HEAD(&rx_queue);
1661 spin_lock_irqsave(&tp->rx_lock, flags);
1662 list_splice_init(&tp->rx_done, &rx_queue);
1663 spin_unlock_irqrestore(&tp->rx_lock, flags);
1665 list_for_each_safe(cursor, next, &rx_queue) {
1666 struct rx_desc *rx_desc;
1673 list_del_init(cursor);
1675 agg = list_entry(cursor, struct rx_agg, list);
1677 if (urb->actual_length < ETH_ZLEN)
1680 rx_desc = agg->head;
1681 rx_data = agg->head;
1682 len_used += sizeof(struct rx_desc);
1684 while (urb->actual_length > len_used) {
1685 struct net_device *netdev = tp->netdev;
1686 struct net_device_stats *stats = &netdev->stats;
1687 unsigned int pkt_len;
1688 struct sk_buff *skb;
1690 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1691 if (pkt_len < ETH_ZLEN)
1694 len_used += pkt_len;
1695 if (urb->actual_length < len_used)
1698 pkt_len -= CRC_SIZE;
1699 rx_data += sizeof(struct rx_desc);
1701 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1703 stats->rx_dropped++;
1707 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1708 memcpy(skb->data, rx_data, pkt_len);
1709 skb_put(skb, pkt_len);
1710 skb->protocol = eth_type_trans(skb, netdev);
1711 rtl_rx_vlan_tag(rx_desc, skb);
1712 netif_receive_skb(skb);
1713 stats->rx_packets++;
1714 stats->rx_bytes += pkt_len;
1717 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1718 rx_desc = (struct rx_desc *)rx_data;
1719 len_used = (int)(rx_data - (u8 *)agg->head);
1720 len_used += sizeof(struct rx_desc);
1724 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1725 if (ret && ret != -ENODEV) {
1726 spin_lock_irqsave(&tp->rx_lock, flags);
1727 list_add_tail(&agg->list, &tp->rx_done);
1728 spin_unlock_irqrestore(&tp->rx_lock, flags);
1729 tasklet_schedule(&tp->tl);
1734 static void tx_bottom(struct r8152 *tp)
1741 if (skb_queue_empty(&tp->tx_queue))
1744 agg = r8152_get_tx_agg(tp);
1748 res = r8152_tx_agg_fill(tp, agg);
1750 struct net_device *netdev = tp->netdev;
1752 if (res == -ENODEV) {
1753 netif_device_detach(netdev);
1755 struct net_device_stats *stats = &netdev->stats;
1756 unsigned long flags;
1758 netif_warn(tp, tx_err, netdev,
1759 "failed tx_urb %d\n", res);
1760 stats->tx_dropped += agg->skb_num;
1762 spin_lock_irqsave(&tp->tx_lock, flags);
1763 list_add_tail(&agg->list, &tp->tx_free);
1764 spin_unlock_irqrestore(&tp->tx_lock, flags);
1770 static void bottom_half(unsigned long data)
1774 tp = (struct r8152 *)data;
1776 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1779 if (!test_bit(WORK_ENABLE, &tp->flags))
1782 /* When link down, the driver would cancel all bulks. */
1783 /* This avoid the re-submitting bulk */
1784 if (!netif_carrier_ok(tp->netdev))
1792 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1794 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1795 agg->head, agg_buf_sz,
1796 (usb_complete_t)read_bulk_callback, agg);
1798 return usb_submit_urb(agg->urb, mem_flags);
1801 static void rtl_drop_queued_tx(struct r8152 *tp)
1803 struct net_device_stats *stats = &tp->netdev->stats;
1804 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1805 struct sk_buff *skb;
1807 if (skb_queue_empty(tx_queue))
1810 __skb_queue_head_init(&skb_head);
1811 spin_lock_bh(&tx_queue->lock);
1812 skb_queue_splice_init(tx_queue, &skb_head);
1813 spin_unlock_bh(&tx_queue->lock);
1815 while ((skb = __skb_dequeue(&skb_head))) {
1817 stats->tx_dropped++;
1821 static void rtl8152_tx_timeout(struct net_device *netdev)
1823 struct r8152 *tp = netdev_priv(netdev);
1826 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1827 for (i = 0; i < RTL8152_MAX_TX; i++)
1828 usb_unlink_urb(tp->tx_info[i].urb);
1831 static void rtl8152_set_rx_mode(struct net_device *netdev)
1833 struct r8152 *tp = netdev_priv(netdev);
1835 if (tp->speed & LINK_STATUS) {
1836 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1837 schedule_delayed_work(&tp->schedule, 0);
1841 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1843 struct r8152 *tp = netdev_priv(netdev);
1844 u32 mc_filter[2]; /* Multicast hash filter */
1848 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1849 netif_stop_queue(netdev);
1850 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1851 ocp_data &= ~RCR_ACPT_ALL;
1852 ocp_data |= RCR_AB | RCR_APM;
1854 if (netdev->flags & IFF_PROMISC) {
1855 /* Unconditionally log net taps. */
1856 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1857 ocp_data |= RCR_AM | RCR_AAP;
1858 mc_filter[1] = 0xffffffff;
1859 mc_filter[0] = 0xffffffff;
1860 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1861 (netdev->flags & IFF_ALLMULTI)) {
1862 /* Too many to filter perfectly -- accept all multicasts. */
1864 mc_filter[1] = 0xffffffff;
1865 mc_filter[0] = 0xffffffff;
1867 struct netdev_hw_addr *ha;
1871 netdev_for_each_mc_addr(ha, netdev) {
1872 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1874 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1879 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1880 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1882 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1883 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1884 netif_wake_queue(netdev);
1887 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1888 struct net_device *netdev)
1890 struct r8152 *tp = netdev_priv(netdev);
1892 skb_tx_timestamp(skb);
1894 skb_queue_tail(&tp->tx_queue, skb);
1896 if (!list_empty(&tp->tx_free)) {
1897 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1898 set_bit(SCHEDULE_TASKLET, &tp->flags);
1899 schedule_delayed_work(&tp->schedule, 0);
1901 usb_mark_last_busy(tp->udev);
1902 tasklet_schedule(&tp->tl);
1904 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1905 netif_stop_queue(netdev);
1908 return NETDEV_TX_OK;
1911 static void r8152b_reset_packet_filter(struct r8152 *tp)
1915 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1916 ocp_data &= ~FMC_FCR_MCU_EN;
1917 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1918 ocp_data |= FMC_FCR_MCU_EN;
1919 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1922 static void rtl8152_nic_reset(struct r8152 *tp)
1926 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1928 for (i = 0; i < 1000; i++) {
1929 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1931 usleep_range(100, 400);
1935 static void set_tx_qlen(struct r8152 *tp)
1937 struct net_device *netdev = tp->netdev;
1939 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1940 sizeof(struct tx_desc));
1943 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1945 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1948 static void rtl_set_eee_plus(struct r8152 *tp)
1953 speed = rtl8152_get_speed(tp);
1954 if (speed & _10bps) {
1955 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1956 ocp_data |= EEEP_CR_EEEP_TX;
1957 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1959 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1960 ocp_data &= ~EEEP_CR_EEEP_TX;
1961 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1965 static void rxdy_gated_en(struct r8152 *tp, bool enable)
1969 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1971 ocp_data |= RXDY_GATED_EN;
1973 ocp_data &= ~RXDY_GATED_EN;
1974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1977 static int rtl_start_rx(struct r8152 *tp)
1981 INIT_LIST_HEAD(&tp->rx_done);
1982 for (i = 0; i < RTL8152_MAX_RX; i++) {
1983 INIT_LIST_HEAD(&tp->rx_info[i].list);
1984 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1992 static int rtl_stop_rx(struct r8152 *tp)
1996 for (i = 0; i < RTL8152_MAX_RX; i++)
1997 usb_kill_urb(tp->rx_info[i].urb);
2002 static int rtl_enable(struct r8152 *tp)
2006 r8152b_reset_packet_filter(tp);
2008 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2009 ocp_data |= CR_RE | CR_TE;
2010 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2012 rxdy_gated_en(tp, false);
2014 return rtl_start_rx(tp);
2017 static int rtl8152_enable(struct r8152 *tp)
2019 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2023 rtl_set_eee_plus(tp);
2025 return rtl_enable(tp);
2028 static void r8153_set_rx_agg(struct r8152 *tp)
2032 speed = rtl8152_get_speed(tp);
2033 if (speed & _1000bps) {
2034 if (tp->udev->speed == USB_SPEED_SUPER) {
2035 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2037 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2040 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2042 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2046 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2047 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2052 static int rtl8153_enable(struct r8152 *tp)
2054 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2058 rtl_set_eee_plus(tp);
2059 r8153_set_rx_agg(tp);
2061 return rtl_enable(tp);
2064 static void rtl_disable(struct r8152 *tp)
2069 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2070 rtl_drop_queued_tx(tp);
2074 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2075 ocp_data &= ~RCR_ACPT_ALL;
2076 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2078 rtl_drop_queued_tx(tp);
2080 for (i = 0; i < RTL8152_MAX_TX; i++)
2081 usb_kill_urb(tp->tx_info[i].urb);
2083 rxdy_gated_en(tp, true);
2085 for (i = 0; i < 1000; i++) {
2086 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2087 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2089 usleep_range(1000, 2000);
2092 for (i = 0; i < 1000; i++) {
2093 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2095 usleep_range(1000, 2000);
2100 rtl8152_nic_reset(tp);
2103 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2107 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2109 ocp_data |= POWER_CUT;
2111 ocp_data &= ~POWER_CUT;
2112 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2114 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2115 ocp_data &= ~RESUME_INDICATE;
2116 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2119 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2123 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2125 ocp_data |= CPCR_RX_VLAN;
2127 ocp_data &= ~CPCR_RX_VLAN;
2128 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2131 static int rtl8152_set_features(struct net_device *dev,
2132 netdev_features_t features)
2134 netdev_features_t changed = features ^ dev->features;
2135 struct r8152 *tp = netdev_priv(dev);
2138 ret = usb_autopm_get_interface(tp->intf);
2142 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2143 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2144 rtl_rx_vlan_en(tp, true);
2146 rtl_rx_vlan_en(tp, false);
2149 usb_autopm_put_interface(tp->intf);
2155 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2157 static u32 __rtl_get_wol(struct r8152 *tp)
2162 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2163 if (!(ocp_data & LAN_WAKE_EN))
2166 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2167 if (ocp_data & LINK_ON_WAKE_EN)
2168 wolopts |= WAKE_PHY;
2170 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2171 if (ocp_data & UWF_EN)
2172 wolopts |= WAKE_UCAST;
2173 if (ocp_data & BWF_EN)
2174 wolopts |= WAKE_BCAST;
2175 if (ocp_data & MWF_EN)
2176 wolopts |= WAKE_MCAST;
2178 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2179 if (ocp_data & MAGIC_EN)
2180 wolopts |= WAKE_MAGIC;
2185 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2189 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2191 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2192 ocp_data &= ~LINK_ON_WAKE_EN;
2193 if (wolopts & WAKE_PHY)
2194 ocp_data |= LINK_ON_WAKE_EN;
2195 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2197 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2198 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2199 if (wolopts & WAKE_UCAST)
2201 if (wolopts & WAKE_BCAST)
2203 if (wolopts & WAKE_MCAST)
2205 if (wolopts & WAKE_ANY)
2206 ocp_data |= LAN_WAKE_EN;
2207 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2209 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2211 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2212 ocp_data &= ~MAGIC_EN;
2213 if (wolopts & WAKE_MAGIC)
2214 ocp_data |= MAGIC_EN;
2215 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2217 if (wolopts & WAKE_ANY)
2218 device_set_wakeup_enable(&tp->udev->dev, true);
2220 device_set_wakeup_enable(&tp->udev->dev, false);
2223 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2228 __rtl_set_wol(tp, WAKE_ANY);
2230 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2232 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2233 ocp_data |= LINK_OFF_WAKE_EN;
2234 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2236 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2238 __rtl_set_wol(tp, tp->saved_wolopts);
2242 static void rtl_phy_reset(struct r8152 *tp)
2247 clear_bit(PHY_RESET, &tp->flags);
2249 data = r8152_mdio_read(tp, MII_BMCR);
2251 /* don't reset again before the previous one complete */
2252 if (data & BMCR_RESET)
2256 r8152_mdio_write(tp, MII_BMCR, data);
2258 for (i = 0; i < 50; i++) {
2260 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2265 static void r8153_teredo_off(struct r8152 *tp)
2269 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2270 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2271 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2273 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2274 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2275 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2278 static void r8152b_disable_aldps(struct r8152 *tp)
2280 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2284 static inline void r8152b_enable_aldps(struct r8152 *tp)
2286 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2287 LINKENA | DIS_SDSAVE);
2290 static void rtl8152_disable(struct r8152 *tp)
2292 r8152b_disable_aldps(tp);
2294 r8152b_enable_aldps(tp);
2297 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2301 data = r8152_mdio_read(tp, MII_BMCR);
2302 if (data & BMCR_PDOWN) {
2303 data &= ~BMCR_PDOWN;
2304 r8152_mdio_write(tp, MII_BMCR, data);
2307 set_bit(PHY_RESET, &tp->flags);
2310 static void r8152b_exit_oob(struct r8152 *tp)
2315 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2316 ocp_data &= ~RCR_ACPT_ALL;
2317 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2319 rxdy_gated_en(tp, true);
2320 r8153_teredo_off(tp);
2321 r8152b_hw_phy_cfg(tp);
2323 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2324 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2326 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2327 ocp_data &= ~NOW_IS_OOB;
2328 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2330 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2331 ocp_data &= ~MCU_BORW_EN;
2332 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2334 for (i = 0; i < 1000; i++) {
2335 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2336 if (ocp_data & LINK_LIST_READY)
2338 usleep_range(1000, 2000);
2341 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2342 ocp_data |= RE_INIT_LL;
2343 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2345 for (i = 0; i < 1000; i++) {
2346 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2347 if (ocp_data & LINK_LIST_READY)
2349 usleep_range(1000, 2000);
2352 rtl8152_nic_reset(tp);
2354 /* rx share fifo credit full threshold */
2355 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2357 if (tp->udev->speed == USB_SPEED_FULL ||
2358 tp->udev->speed == USB_SPEED_LOW) {
2359 /* rx share fifo credit near full threshold */
2360 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2362 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2365 /* rx share fifo credit near full threshold */
2366 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2368 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2372 /* TX share fifo free credit full threshold */
2373 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2375 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2376 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2377 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2378 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2380 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2382 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2384 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2385 ocp_data |= TCR0_AUTO_FIFO;
2386 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2389 static void r8152b_enter_oob(struct r8152 *tp)
2394 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2395 ocp_data &= ~NOW_IS_OOB;
2396 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2398 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2399 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2400 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2404 for (i = 0; i < 1000; i++) {
2405 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2406 if (ocp_data & LINK_LIST_READY)
2408 usleep_range(1000, 2000);
2411 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2412 ocp_data |= RE_INIT_LL;
2413 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2415 for (i = 0; i < 1000; i++) {
2416 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2417 if (ocp_data & LINK_LIST_READY)
2419 usleep_range(1000, 2000);
2422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2424 rtl_rx_vlan_en(tp, true);
2426 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2427 ocp_data |= ALDPS_PROXY_MODE;
2428 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2430 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2431 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2432 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2434 rxdy_gated_en(tp, false);
2436 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2437 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2438 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2441 static void r8153_hw_phy_cfg(struct r8152 *tp)
2446 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2447 data = r8152_mdio_read(tp, MII_BMCR);
2448 if (data & BMCR_PDOWN) {
2449 data &= ~BMCR_PDOWN;
2450 r8152_mdio_write(tp, MII_BMCR, data);
2453 if (tp->version == RTL_VER_03) {
2454 data = ocp_reg_read(tp, OCP_EEE_CFG);
2455 data &= ~CTAP_SHORT_EN;
2456 ocp_reg_write(tp, OCP_EEE_CFG, data);
2459 data = ocp_reg_read(tp, OCP_POWER_CFG);
2460 data |= EEE_CLKDIV_EN;
2461 ocp_reg_write(tp, OCP_POWER_CFG, data);
2463 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2464 data |= EN_10M_BGOFF;
2465 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2466 data = ocp_reg_read(tp, OCP_POWER_CFG);
2467 data |= EN_10M_PLLOFF;
2468 ocp_reg_write(tp, OCP_POWER_CFG, data);
2469 data = sram_read(tp, SRAM_IMPEDANCE);
2470 data &= ~RX_DRIVING_MASK;
2471 sram_write(tp, SRAM_IMPEDANCE, data);
2473 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2474 ocp_data |= PFM_PWM_SWITCH;
2475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2477 data = sram_read(tp, SRAM_LPF_CFG);
2478 data |= LPF_AUTO_TUNE;
2479 sram_write(tp, SRAM_LPF_CFG, data);
2481 data = sram_read(tp, SRAM_10M_AMP1);
2482 data |= GDAC_IB_UPALL;
2483 sram_write(tp, SRAM_10M_AMP1, data);
2484 data = sram_read(tp, SRAM_10M_AMP2);
2486 sram_write(tp, SRAM_10M_AMP2, data);
2488 set_bit(PHY_RESET, &tp->flags);
2491 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2496 memset(u1u2, 0xff, sizeof(u1u2));
2498 memset(u1u2, 0x00, sizeof(u1u2));
2500 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2503 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2507 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2509 ocp_data |= U2P3_ENABLE;
2511 ocp_data &= ~U2P3_ENABLE;
2512 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2515 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2519 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2521 ocp_data |= PWR_EN | PHASE2_EN;
2523 ocp_data &= ~(PWR_EN | PHASE2_EN);
2524 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2526 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2527 ocp_data &= ~PCUT_STATUS;
2528 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2531 static void r8153_first_init(struct r8152 *tp)
2536 rxdy_gated_en(tp, true);
2537 r8153_teredo_off(tp);
2539 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2540 ocp_data &= ~RCR_ACPT_ALL;
2541 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2543 r8153_hw_phy_cfg(tp);
2545 rtl8152_nic_reset(tp);
2547 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2548 ocp_data &= ~NOW_IS_OOB;
2549 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2551 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2552 ocp_data &= ~MCU_BORW_EN;
2553 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2555 for (i = 0; i < 1000; i++) {
2556 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2557 if (ocp_data & LINK_LIST_READY)
2559 usleep_range(1000, 2000);
2562 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2563 ocp_data |= RE_INIT_LL;
2564 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2566 for (i = 0; i < 1000; i++) {
2567 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2568 if (ocp_data & LINK_LIST_READY)
2570 usleep_range(1000, 2000);
2573 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2575 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2576 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2578 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2579 ocp_data |= TCR0_AUTO_FIFO;
2580 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2582 rtl8152_nic_reset(tp);
2584 /* rx share fifo credit full threshold */
2585 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2586 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2587 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2588 /* TX share fifo free credit full threshold */
2589 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2591 /* rx aggregation */
2592 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2593 ocp_data &= ~RX_AGG_DISABLE;
2594 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2597 static void r8153_enter_oob(struct r8152 *tp)
2602 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2603 ocp_data &= ~NOW_IS_OOB;
2604 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2608 for (i = 0; i < 1000; i++) {
2609 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2610 if (ocp_data & LINK_LIST_READY)
2612 usleep_range(1000, 2000);
2615 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2616 ocp_data |= RE_INIT_LL;
2617 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2619 for (i = 0; i < 1000; i++) {
2620 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2621 if (ocp_data & LINK_LIST_READY)
2623 usleep_range(1000, 2000);
2626 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2628 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2629 ocp_data &= ~TEREDO_WAKE_MASK;
2630 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2632 rtl_rx_vlan_en(tp, true);
2634 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2635 ocp_data |= ALDPS_PROXY_MODE;
2636 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2638 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2639 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2640 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2642 rxdy_gated_en(tp, false);
2644 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2645 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2646 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2649 static void r8153_disable_aldps(struct r8152 *tp)
2653 data = ocp_reg_read(tp, OCP_POWER_CFG);
2655 ocp_reg_write(tp, OCP_POWER_CFG, data);
2659 static void r8153_enable_aldps(struct r8152 *tp)
2663 data = ocp_reg_read(tp, OCP_POWER_CFG);
2665 ocp_reg_write(tp, OCP_POWER_CFG, data);
2668 static void rtl8153_disable(struct r8152 *tp)
2670 r8153_disable_aldps(tp);
2672 r8153_enable_aldps(tp);
2675 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2677 u16 bmcr, anar, gbcr;
2680 cancel_delayed_work_sync(&tp->schedule);
2681 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2682 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2683 ADVERTISE_100HALF | ADVERTISE_100FULL);
2684 if (tp->mii.supports_gmii) {
2685 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2686 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2691 if (autoneg == AUTONEG_DISABLE) {
2692 if (speed == SPEED_10) {
2694 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2695 } else if (speed == SPEED_100) {
2696 bmcr = BMCR_SPEED100;
2697 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2698 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2699 bmcr = BMCR_SPEED1000;
2700 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2706 if (duplex == DUPLEX_FULL)
2707 bmcr |= BMCR_FULLDPLX;
2709 if (speed == SPEED_10) {
2710 if (duplex == DUPLEX_FULL)
2711 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2713 anar |= ADVERTISE_10HALF;
2714 } else if (speed == SPEED_100) {
2715 if (duplex == DUPLEX_FULL) {
2716 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2717 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2719 anar |= ADVERTISE_10HALF;
2720 anar |= ADVERTISE_100HALF;
2722 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2723 if (duplex == DUPLEX_FULL) {
2724 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2725 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2726 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2728 anar |= ADVERTISE_10HALF;
2729 anar |= ADVERTISE_100HALF;
2730 gbcr |= ADVERTISE_1000HALF;
2737 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2740 if (test_bit(PHY_RESET, &tp->flags))
2743 if (tp->mii.supports_gmii)
2744 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2746 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2747 r8152_mdio_write(tp, MII_BMCR, bmcr);
2749 if (test_bit(PHY_RESET, &tp->flags)) {
2752 clear_bit(PHY_RESET, &tp->flags);
2753 for (i = 0; i < 50; i++) {
2755 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2765 static void rtl8152_up(struct r8152 *tp)
2767 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2770 r8152b_disable_aldps(tp);
2771 r8152b_exit_oob(tp);
2772 r8152b_enable_aldps(tp);
2775 static void rtl8152_down(struct r8152 *tp)
2777 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2778 rtl_drop_queued_tx(tp);
2782 r8152_power_cut_en(tp, false);
2783 r8152b_disable_aldps(tp);
2784 r8152b_enter_oob(tp);
2785 r8152b_enable_aldps(tp);
2788 static void rtl8153_up(struct r8152 *tp)
2790 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2793 r8153_disable_aldps(tp);
2794 r8153_first_init(tp);
2795 r8153_enable_aldps(tp);
2798 static void rtl8153_down(struct r8152 *tp)
2800 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2801 rtl_drop_queued_tx(tp);
2805 r8153_u1u2en(tp, false);
2806 r8153_power_cut_en(tp, false);
2807 r8153_disable_aldps(tp);
2808 r8153_enter_oob(tp);
2809 r8153_enable_aldps(tp);
2812 static void set_carrier(struct r8152 *tp)
2814 struct net_device *netdev = tp->netdev;
2817 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2818 speed = rtl8152_get_speed(tp);
2820 if (speed & LINK_STATUS) {
2821 if (!(tp->speed & LINK_STATUS)) {
2822 tp->rtl_ops.enable(tp);
2823 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2824 netif_carrier_on(netdev);
2827 if (tp->speed & LINK_STATUS) {
2828 netif_carrier_off(netdev);
2829 tasklet_disable(&tp->tl);
2830 tp->rtl_ops.disable(tp);
2831 tasklet_enable(&tp->tl);
2837 static void rtl_work_func_t(struct work_struct *work)
2839 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2841 if (usb_autopm_get_interface(tp->intf) < 0)
2844 if (!test_bit(WORK_ENABLE, &tp->flags))
2847 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2850 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2853 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2854 _rtl8152_set_rx_mode(tp->netdev);
2856 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2857 (tp->speed & LINK_STATUS)) {
2858 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2859 tasklet_schedule(&tp->tl);
2862 if (test_bit(PHY_RESET, &tp->flags))
2866 usb_autopm_put_interface(tp->intf);
2869 static int rtl8152_open(struct net_device *netdev)
2871 struct r8152 *tp = netdev_priv(netdev);
2874 res = alloc_all_mem(tp);
2878 res = usb_autopm_get_interface(tp->intf);
2884 /* The WORK_ENABLE may be set when autoresume occurs */
2885 if (test_bit(WORK_ENABLE, &tp->flags)) {
2886 clear_bit(WORK_ENABLE, &tp->flags);
2887 usb_kill_urb(tp->intr_urb);
2888 cancel_delayed_work_sync(&tp->schedule);
2889 if (tp->speed & LINK_STATUS)
2890 tp->rtl_ops.disable(tp);
2895 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2896 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2899 netif_carrier_off(netdev);
2900 netif_start_queue(netdev);
2901 set_bit(WORK_ENABLE, &tp->flags);
2903 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2906 netif_device_detach(tp->netdev);
2907 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2912 usb_autopm_put_interface(tp->intf);
2918 static int rtl8152_close(struct net_device *netdev)
2920 struct r8152 *tp = netdev_priv(netdev);
2923 clear_bit(WORK_ENABLE, &tp->flags);
2924 usb_kill_urb(tp->intr_urb);
2925 cancel_delayed_work_sync(&tp->schedule);
2926 netif_stop_queue(netdev);
2928 res = usb_autopm_get_interface(tp->intf);
2930 rtl_drop_queued_tx(tp);
2932 /* The autosuspend may have been enabled and wouldn't
2933 * be disable when autoresume occurs, because the
2934 * netif_running() would be false.
2936 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2937 rtl_runtime_suspend_enable(tp, false);
2938 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2941 tasklet_disable(&tp->tl);
2942 tp->rtl_ops.down(tp);
2943 tasklet_enable(&tp->tl);
2944 usb_autopm_put_interface(tp->intf);
2952 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2954 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2955 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2956 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2959 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2963 r8152_mmd_indirect(tp, dev, reg);
2964 data = ocp_reg_read(tp, OCP_EEE_DATA);
2965 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2970 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2972 r8152_mmd_indirect(tp, dev, reg);
2973 ocp_reg_write(tp, OCP_EEE_DATA, data);
2974 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2977 static void r8152_eee_en(struct r8152 *tp, bool enable)
2979 u16 config1, config2, config3;
2982 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2983 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2984 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2985 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2988 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2989 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2990 config1 |= sd_rise_time(1);
2991 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2992 config3 |= fast_snr(42);
2994 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2995 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2997 config1 |= sd_rise_time(7);
2998 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2999 config3 |= fast_snr(511);
3002 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3003 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3004 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3005 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3008 static void r8152b_enable_eee(struct r8152 *tp)
3010 r8152_eee_en(tp, true);
3011 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3014 static void r8153_eee_en(struct r8152 *tp, bool enable)
3019 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3020 config = ocp_reg_read(tp, OCP_EEE_CFG);
3023 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3026 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3027 config &= ~EEE10_EN;
3030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3031 ocp_reg_write(tp, OCP_EEE_CFG, config);
3034 static void r8153_enable_eee(struct r8152 *tp)
3036 r8153_eee_en(tp, true);
3037 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3040 static void r8152b_enable_fc(struct r8152 *tp)
3044 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3045 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3046 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3049 static void rtl_tally_reset(struct r8152 *tp)
3053 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3054 ocp_data |= TALLY_RESET;
3055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3058 static void r8152b_init(struct r8152 *tp)
3062 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3065 r8152b_disable_aldps(tp);
3067 if (tp->version == RTL_VER_01) {
3068 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3069 ocp_data &= ~LED_MODE_MASK;
3070 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3073 r8152_power_cut_en(tp, false);
3075 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3076 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3077 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3078 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3079 ocp_data &= ~MCU_CLK_RATIO_MASK;
3080 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3081 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3082 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3083 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3084 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3086 r8152b_enable_eee(tp);
3087 r8152b_enable_aldps(tp);
3088 r8152b_enable_fc(tp);
3089 rtl_tally_reset(tp);
3091 /* enable rx aggregation */
3092 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3093 ocp_data &= ~RX_AGG_DISABLE;
3094 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3097 static void r8153_init(struct r8152 *tp)
3102 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3105 r8153_disable_aldps(tp);
3106 r8153_u1u2en(tp, false);
3108 for (i = 0; i < 500; i++) {
3109 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3115 for (i = 0; i < 500; i++) {
3116 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3117 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3122 r8153_u2p3en(tp, false);
3124 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3125 ocp_data &= ~TIMER11_EN;
3126 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3128 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3129 ocp_data &= ~LED_MODE_MASK;
3130 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3132 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3133 ocp_data &= ~LPM_TIMER_MASK;
3134 if (tp->udev->speed == USB_SPEED_SUPER)
3135 ocp_data |= LPM_TIMER_500US;
3137 ocp_data |= LPM_TIMER_500MS;
3138 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3140 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3141 ocp_data &= ~SEN_VAL_MASK;
3142 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3143 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3145 r8153_power_cut_en(tp, false);
3146 r8153_u1u2en(tp, true);
3148 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3149 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3150 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3151 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3152 U1U2_SPDWN_EN | L1_SPDWN_EN);
3153 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3154 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3155 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3158 r8153_enable_eee(tp);
3159 r8153_enable_aldps(tp);
3160 r8152b_enable_fc(tp);
3161 rtl_tally_reset(tp);
3164 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3166 struct r8152 *tp = usb_get_intfdata(intf);
3168 if (PMSG_IS_AUTO(message))
3169 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3171 netif_device_detach(tp->netdev);
3173 if (netif_running(tp->netdev)) {
3174 clear_bit(WORK_ENABLE, &tp->flags);
3175 usb_kill_urb(tp->intr_urb);
3176 cancel_delayed_work_sync(&tp->schedule);
3177 tasklet_disable(&tp->tl);
3178 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3180 rtl_runtime_suspend_enable(tp, true);
3182 tp->rtl_ops.down(tp);
3184 tasklet_enable(&tp->tl);
3190 static int rtl8152_resume(struct usb_interface *intf)
3192 struct r8152 *tp = usb_get_intfdata(intf);
3194 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3195 tp->rtl_ops.init(tp);
3196 netif_device_attach(tp->netdev);
3199 if (netif_running(tp->netdev)) {
3200 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3201 rtl_runtime_suspend_enable(tp, false);
3202 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3203 set_bit(WORK_ENABLE, &tp->flags);
3204 if (tp->speed & LINK_STATUS)
3208 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3209 tp->mii.supports_gmii ?
3210 SPEED_1000 : SPEED_100,
3213 netif_carrier_off(tp->netdev);
3214 set_bit(WORK_ENABLE, &tp->flags);
3216 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3222 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3224 struct r8152 *tp = netdev_priv(dev);
3226 if (usb_autopm_get_interface(tp->intf) < 0)
3229 wol->supported = WAKE_ANY;
3230 wol->wolopts = __rtl_get_wol(tp);
3232 usb_autopm_put_interface(tp->intf);
3235 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3237 struct r8152 *tp = netdev_priv(dev);
3240 ret = usb_autopm_get_interface(tp->intf);
3244 __rtl_set_wol(tp, wol->wolopts);
3245 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3247 usb_autopm_put_interface(tp->intf);
3253 static u32 rtl8152_get_msglevel(struct net_device *dev)
3255 struct r8152 *tp = netdev_priv(dev);
3257 return tp->msg_enable;
3260 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3262 struct r8152 *tp = netdev_priv(dev);
3264 tp->msg_enable = value;
3267 static void rtl8152_get_drvinfo(struct net_device *netdev,
3268 struct ethtool_drvinfo *info)
3270 struct r8152 *tp = netdev_priv(netdev);
3272 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3273 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3274 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3278 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3280 struct r8152 *tp = netdev_priv(netdev);
3283 if (!tp->mii.mdio_read)
3286 ret = usb_autopm_get_interface(tp->intf);
3290 ret = mii_ethtool_gset(&tp->mii, cmd);
3292 usb_autopm_put_interface(tp->intf);
3298 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3300 struct r8152 *tp = netdev_priv(dev);
3303 ret = usb_autopm_get_interface(tp->intf);
3307 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3309 usb_autopm_put_interface(tp->intf);
3315 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3322 "tx_single_collisions",
3323 "tx_multi_collisions",
3331 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3335 return ARRAY_SIZE(rtl8152_gstrings);
3341 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3342 struct ethtool_stats *stats, u64 *data)
3344 struct r8152 *tp = netdev_priv(dev);
3345 struct tally_counter tally;
3347 if (usb_autopm_get_interface(tp->intf) < 0)
3350 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3352 usb_autopm_put_interface(tp->intf);
3354 data[0] = le64_to_cpu(tally.tx_packets);
3355 data[1] = le64_to_cpu(tally.rx_packets);
3356 data[2] = le64_to_cpu(tally.tx_errors);
3357 data[3] = le32_to_cpu(tally.rx_errors);
3358 data[4] = le16_to_cpu(tally.rx_missed);
3359 data[5] = le16_to_cpu(tally.align_errors);
3360 data[6] = le32_to_cpu(tally.tx_one_collision);
3361 data[7] = le32_to_cpu(tally.tx_multi_collision);
3362 data[8] = le64_to_cpu(tally.rx_unicast);
3363 data[9] = le64_to_cpu(tally.rx_broadcast);
3364 data[10] = le32_to_cpu(tally.rx_multicast);
3365 data[11] = le16_to_cpu(tally.tx_aborted);
3366 data[12] = le16_to_cpu(tally.tx_underun);
3369 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3371 switch (stringset) {
3373 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3378 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3380 u32 ocp_data, lp, adv, supported = 0;
3383 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3384 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3386 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3387 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3389 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3390 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3392 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3393 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3395 eee->eee_enabled = !!ocp_data;
3396 eee->eee_active = !!(supported & adv & lp);
3397 eee->supported = supported;
3398 eee->advertised = adv;
3399 eee->lp_advertised = lp;
3404 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3406 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3408 r8152_eee_en(tp, eee->eee_enabled);
3410 if (!eee->eee_enabled)
3413 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3418 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3420 u32 ocp_data, lp, adv, supported = 0;
3423 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3424 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3426 val = ocp_reg_read(tp, OCP_EEE_ADV);
3427 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3429 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3430 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3432 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3433 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3435 eee->eee_enabled = !!ocp_data;
3436 eee->eee_active = !!(supported & adv & lp);
3437 eee->supported = supported;
3438 eee->advertised = adv;
3439 eee->lp_advertised = lp;
3444 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3446 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3448 r8153_eee_en(tp, eee->eee_enabled);
3450 if (!eee->eee_enabled)
3453 ocp_reg_write(tp, OCP_EEE_ADV, val);
3459 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3461 struct r8152 *tp = netdev_priv(net);
3464 ret = usb_autopm_get_interface(tp->intf);
3468 ret = tp->rtl_ops.eee_get(tp, edata);
3470 usb_autopm_put_interface(tp->intf);
3477 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3479 struct r8152 *tp = netdev_priv(net);
3482 ret = usb_autopm_get_interface(tp->intf);
3486 ret = tp->rtl_ops.eee_set(tp, edata);
3488 ret = mii_nway_restart(&tp->mii);
3490 usb_autopm_put_interface(tp->intf);
3496 static struct ethtool_ops ops = {
3497 .get_drvinfo = rtl8152_get_drvinfo,
3498 .get_settings = rtl8152_get_settings,
3499 .set_settings = rtl8152_set_settings,
3500 .get_link = ethtool_op_get_link,
3501 .get_msglevel = rtl8152_get_msglevel,
3502 .set_msglevel = rtl8152_set_msglevel,
3503 .get_wol = rtl8152_get_wol,
3504 .set_wol = rtl8152_set_wol,
3505 .get_strings = rtl8152_get_strings,
3506 .get_sset_count = rtl8152_get_sset_count,
3507 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3508 .get_eee = rtl_ethtool_get_eee,
3509 .set_eee = rtl_ethtool_set_eee,
3512 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3514 struct r8152 *tp = netdev_priv(netdev);
3515 struct mii_ioctl_data *data = if_mii(rq);
3518 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3521 res = usb_autopm_get_interface(tp->intf);
3527 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3531 data->val_out = r8152_mdio_read(tp, data->reg_num);
3535 if (!capable(CAP_NET_ADMIN)) {
3539 r8152_mdio_write(tp, data->reg_num, data->val_in);
3546 usb_autopm_put_interface(tp->intf);
3552 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3554 struct r8152 *tp = netdev_priv(dev);
3556 switch (tp->version) {
3559 return eth_change_mtu(dev, new_mtu);
3564 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3572 static const struct net_device_ops rtl8152_netdev_ops = {
3573 .ndo_open = rtl8152_open,
3574 .ndo_stop = rtl8152_close,
3575 .ndo_do_ioctl = rtl8152_ioctl,
3576 .ndo_start_xmit = rtl8152_start_xmit,
3577 .ndo_tx_timeout = rtl8152_tx_timeout,
3578 .ndo_set_features = rtl8152_set_features,
3579 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3580 .ndo_set_mac_address = rtl8152_set_mac_address,
3581 .ndo_change_mtu = rtl8152_change_mtu,
3582 .ndo_validate_addr = eth_validate_addr,
3585 static void r8152b_get_version(struct r8152 *tp)
3590 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3591 version = (u16)(ocp_data & VERSION_MASK);
3595 tp->version = RTL_VER_01;
3598 tp->version = RTL_VER_02;
3601 tp->version = RTL_VER_03;
3602 tp->mii.supports_gmii = 1;
3605 tp->version = RTL_VER_04;
3606 tp->mii.supports_gmii = 1;
3609 tp->version = RTL_VER_05;
3610 tp->mii.supports_gmii = 1;
3613 netif_info(tp, probe, tp->netdev,
3614 "Unknown version 0x%04x\n", version);
3619 static void rtl8152_unload(struct r8152 *tp)
3621 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3624 if (tp->version != RTL_VER_01)
3625 r8152_power_cut_en(tp, true);
3628 static void rtl8153_unload(struct r8152 *tp)
3630 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3633 r8153_power_cut_en(tp, false);
3636 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
3638 struct rtl_ops *ops = &tp->rtl_ops;
3641 switch (id->idVendor) {
3642 case VENDOR_ID_REALTEK:
3643 switch (id->idProduct) {
3644 case PRODUCT_ID_RTL8152:
3645 ops->init = r8152b_init;
3646 ops->enable = rtl8152_enable;
3647 ops->disable = rtl8152_disable;
3648 ops->up = rtl8152_up;
3649 ops->down = rtl8152_down;
3650 ops->unload = rtl8152_unload;
3651 ops->eee_get = r8152_get_eee;
3652 ops->eee_set = r8152_set_eee;
3655 case PRODUCT_ID_RTL8153:
3656 ops->init = r8153_init;
3657 ops->enable = rtl8153_enable;
3658 ops->disable = rtl8153_disable;
3659 ops->up = rtl8153_up;
3660 ops->down = rtl8153_down;
3661 ops->unload = rtl8153_unload;
3662 ops->eee_get = r8153_get_eee;
3663 ops->eee_set = r8153_set_eee;
3671 case VENDOR_ID_SAMSUNG:
3672 switch (id->idProduct) {
3673 case PRODUCT_ID_SAMSUNG:
3674 ops->init = r8153_init;
3675 ops->enable = rtl8153_enable;
3676 ops->disable = rtl8153_disable;
3677 ops->up = rtl8153_up;
3678 ops->down = rtl8153_down;
3679 ops->unload = rtl8153_unload;
3680 ops->eee_get = r8153_get_eee;
3681 ops->eee_set = r8153_set_eee;
3694 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3699 static int rtl8152_probe(struct usb_interface *intf,
3700 const struct usb_device_id *id)
3702 struct usb_device *udev = interface_to_usbdev(intf);
3704 struct net_device *netdev;
3707 if (udev->actconfig->desc.bConfigurationValue != 1) {
3708 usb_driver_set_configuration(udev, 1);
3712 usb_reset_device(udev);
3713 netdev = alloc_etherdev(sizeof(struct r8152));
3715 dev_err(&intf->dev, "Out of memory\n");
3719 SET_NETDEV_DEV(netdev, &intf->dev);
3720 tp = netdev_priv(netdev);
3721 tp->msg_enable = 0x7FFF;
3724 tp->netdev = netdev;
3727 ret = rtl_ops_init(tp, id);
3731 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3732 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3734 netdev->netdev_ops = &rtl8152_netdev_ops;
3735 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3737 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3738 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3739 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3740 NETIF_F_HW_VLAN_CTAG_TX;
3741 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3742 NETIF_F_TSO | NETIF_F_FRAGLIST |
3743 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3744 NETIF_F_HW_VLAN_CTAG_RX |
3745 NETIF_F_HW_VLAN_CTAG_TX;
3746 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3747 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3748 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3750 netdev->ethtool_ops = &ops;
3751 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3753 tp->mii.dev = netdev;
3754 tp->mii.mdio_read = read_mii_word;
3755 tp->mii.mdio_write = write_mii_word;
3756 tp->mii.phy_id_mask = 0x3f;
3757 tp->mii.reg_num_mask = 0x1f;
3758 tp->mii.phy_id = R8152_PHY_ID;
3759 tp->mii.supports_gmii = 0;
3761 intf->needs_remote_wakeup = 1;
3763 r8152b_get_version(tp);
3764 tp->rtl_ops.init(tp);
3765 set_ethernet_addr(tp);
3767 usb_set_intfdata(intf, tp);
3769 ret = register_netdev(netdev);
3771 netif_err(tp, probe, netdev, "couldn't register the device\n");
3775 tp->saved_wolopts = __rtl_get_wol(tp);
3776 if (tp->saved_wolopts)
3777 device_set_wakeup_enable(&udev->dev, true);
3779 device_set_wakeup_enable(&udev->dev, false);
3781 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3786 usb_set_intfdata(intf, NULL);
3788 free_netdev(netdev);
3792 static void rtl8152_disconnect(struct usb_interface *intf)
3794 struct r8152 *tp = usb_get_intfdata(intf);
3796 usb_set_intfdata(intf, NULL);
3798 struct usb_device *udev = tp->udev;
3800 if (udev->state == USB_STATE_NOTATTACHED)
3801 set_bit(RTL8152_UNPLUG, &tp->flags);
3803 tasklet_kill(&tp->tl);
3804 unregister_netdev(tp->netdev);
3805 tp->rtl_ops.unload(tp);
3806 free_netdev(tp->netdev);
3810 /* table of devices that work with this driver */
3811 static struct usb_device_id rtl8152_table[] = {
3812 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3813 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3814 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3818 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3820 static struct usb_driver rtl8152_driver = {
3822 .id_table = rtl8152_table,
3823 .probe = rtl8152_probe,
3824 .disconnect = rtl8152_disconnect,
3825 .suspend = rtl8152_suspend,
3826 .resume = rtl8152_resume,
3827 .reset_resume = rtl8152_resume,
3828 .supports_autosuspend = 1,
3829 .disable_hub_initiated_lpm = 1,
3832 module_usb_driver(rtl8152_driver);
3834 MODULE_AUTHOR(DRIVER_AUTHOR);
3835 MODULE_DESCRIPTION(DRIVER_DESC);
3836 MODULE_LICENSE("GPL");