r8152: restore hw settings
[cascardo/linux.git] / drivers / net / usb / r8152.c
1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28
29 /* Version Information */
30 #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
31 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
32 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
33 #define MODULENAME "r8152"
34
35 #define R8152_PHY_ID            32
36
37 #define PLA_IDR                 0xc000
38 #define PLA_RCR                 0xc010
39 #define PLA_RMS                 0xc016
40 #define PLA_RXFIFO_CTRL0        0xc0a0
41 #define PLA_RXFIFO_CTRL1        0xc0a4
42 #define PLA_RXFIFO_CTRL2        0xc0a8
43 #define PLA_DMY_REG0            0xc0b0
44 #define PLA_FMC                 0xc0b4
45 #define PLA_CFG_WOL             0xc0b6
46 #define PLA_TEREDO_CFG          0xc0bc
47 #define PLA_MAR                 0xcd00
48 #define PLA_BACKUP              0xd000
49 #define PAL_BDC_CR              0xd1a0
50 #define PLA_TEREDO_TIMER        0xd2cc
51 #define PLA_REALWOW_TIMER       0xd2e8
52 #define PLA_LEDSEL              0xdd90
53 #define PLA_LED_FEATURE         0xdd92
54 #define PLA_PHYAR               0xde00
55 #define PLA_BOOT_CTRL           0xe004
56 #define PLA_GPHY_INTR_IMR       0xe022
57 #define PLA_EEE_CR              0xe040
58 #define PLA_EEEP_CR             0xe080
59 #define PLA_MAC_PWR_CTRL        0xe0c0
60 #define PLA_MAC_PWR_CTRL2       0xe0ca
61 #define PLA_MAC_PWR_CTRL3       0xe0cc
62 #define PLA_MAC_PWR_CTRL4       0xe0ce
63 #define PLA_WDT6_CTRL           0xe428
64 #define PLA_TCR0                0xe610
65 #define PLA_TCR1                0xe612
66 #define PLA_MTPS                0xe615
67 #define PLA_TXFIFO_CTRL         0xe618
68 #define PLA_RSTTALLY            0xe800
69 #define PLA_CR                  0xe813
70 #define PLA_CRWECR              0xe81c
71 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
72 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
73 #define PLA_CONFIG5             0xe822
74 #define PLA_PHY_PWR             0xe84c
75 #define PLA_OOB_CTRL            0xe84f
76 #define PLA_CPCR                0xe854
77 #define PLA_MISC_0              0xe858
78 #define PLA_MISC_1              0xe85a
79 #define PLA_OCP_GPHY_BASE       0xe86c
80 #define PLA_TALLYCNT            0xe890
81 #define PLA_SFF_STS_7           0xe8de
82 #define PLA_PHYSTATUS           0xe908
83 #define PLA_BP_BA               0xfc26
84 #define PLA_BP_0                0xfc28
85 #define PLA_BP_1                0xfc2a
86 #define PLA_BP_2                0xfc2c
87 #define PLA_BP_3                0xfc2e
88 #define PLA_BP_4                0xfc30
89 #define PLA_BP_5                0xfc32
90 #define PLA_BP_6                0xfc34
91 #define PLA_BP_7                0xfc36
92 #define PLA_BP_EN               0xfc38
93
94 #define USB_USB2PHY             0xb41e
95 #define USB_SSPHYLINK2          0xb428
96 #define USB_U2P3_CTRL           0xb460
97 #define USB_CSR_DUMMY1          0xb464
98 #define USB_CSR_DUMMY2          0xb466
99 #define USB_DEV_STAT            0xb808
100 #define USB_CONNECT_TIMER       0xcbf8
101 #define USB_BURST_SIZE          0xcfc0
102 #define USB_USB_CTRL            0xd406
103 #define USB_PHY_CTRL            0xd408
104 #define USB_TX_AGG              0xd40a
105 #define USB_RX_BUF_TH           0xd40c
106 #define USB_USB_TIMER           0xd428
107 #define USB_RX_EARLY_AGG        0xd42c
108 #define USB_PM_CTRL_STATUS      0xd432
109 #define USB_TX_DMA              0xd434
110 #define USB_TOLERANCE           0xd490
111 #define USB_LPM_CTRL            0xd41a
112 #define USB_UPS_CTRL            0xd800
113 #define USB_MISC_0              0xd81a
114 #define USB_POWER_CUT           0xd80a
115 #define USB_AFE_CTRL2           0xd824
116 #define USB_WDT11_CTRL          0xe43c
117 #define USB_BP_BA               0xfc26
118 #define USB_BP_0                0xfc28
119 #define USB_BP_1                0xfc2a
120 #define USB_BP_2                0xfc2c
121 #define USB_BP_3                0xfc2e
122 #define USB_BP_4                0xfc30
123 #define USB_BP_5                0xfc32
124 #define USB_BP_6                0xfc34
125 #define USB_BP_7                0xfc36
126 #define USB_BP_EN               0xfc38
127
128 /* OCP Registers */
129 #define OCP_ALDPS_CONFIG        0x2010
130 #define OCP_EEE_CONFIG1         0x2080
131 #define OCP_EEE_CONFIG2         0x2092
132 #define OCP_EEE_CONFIG3         0x2094
133 #define OCP_BASE_MII            0xa400
134 #define OCP_EEE_AR              0xa41a
135 #define OCP_EEE_DATA            0xa41c
136 #define OCP_PHY_STATUS          0xa420
137 #define OCP_POWER_CFG           0xa430
138 #define OCP_EEE_CFG             0xa432
139 #define OCP_SRAM_ADDR           0xa436
140 #define OCP_SRAM_DATA           0xa438
141 #define OCP_DOWN_SPEED          0xa442
142 #define OCP_EEE_ABLE            0xa5c4
143 #define OCP_EEE_ADV             0xa5d0
144 #define OCP_EEE_LPABLE          0xa5d2
145 #define OCP_ADC_CFG             0xbc06
146
147 /* SRAM Register */
148 #define SRAM_LPF_CFG            0x8012
149 #define SRAM_10M_AMP1           0x8080
150 #define SRAM_10M_AMP2           0x8082
151 #define SRAM_IMPEDANCE          0x8084
152
153 /* PLA_RCR */
154 #define RCR_AAP                 0x00000001
155 #define RCR_APM                 0x00000002
156 #define RCR_AM                  0x00000004
157 #define RCR_AB                  0x00000008
158 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
159
160 /* PLA_RXFIFO_CTRL0 */
161 #define RXFIFO_THR1_NORMAL      0x00080002
162 #define RXFIFO_THR1_OOB         0x01800003
163
164 /* PLA_RXFIFO_CTRL1 */
165 #define RXFIFO_THR2_FULL        0x00000060
166 #define RXFIFO_THR2_HIGH        0x00000038
167 #define RXFIFO_THR2_OOB         0x0000004a
168 #define RXFIFO_THR2_NORMAL      0x00a0
169
170 /* PLA_RXFIFO_CTRL2 */
171 #define RXFIFO_THR3_FULL        0x00000078
172 #define RXFIFO_THR3_HIGH        0x00000048
173 #define RXFIFO_THR3_OOB         0x0000005a
174 #define RXFIFO_THR3_NORMAL      0x0110
175
176 /* PLA_TXFIFO_CTRL */
177 #define TXFIFO_THR_NORMAL       0x00400008
178 #define TXFIFO_THR_NORMAL2      0x01000008
179
180 /* PLA_DMY_REG0 */
181 #define ECM_ALDPS               0x0002
182
183 /* PLA_FMC */
184 #define FMC_FCR_MCU_EN          0x0001
185
186 /* PLA_EEEP_CR */
187 #define EEEP_CR_EEEP_TX         0x0002
188
189 /* PLA_WDT6_CTRL */
190 #define WDT6_SET_MODE           0x0010
191
192 /* PLA_TCR0 */
193 #define TCR0_TX_EMPTY           0x0800
194 #define TCR0_AUTO_FIFO          0x0080
195
196 /* PLA_TCR1 */
197 #define VERSION_MASK            0x7cf0
198
199 /* PLA_MTPS */
200 #define MTPS_JUMBO              (12 * 1024 / 64)
201 #define MTPS_DEFAULT            (6 * 1024 / 64)
202
203 /* PLA_RSTTALLY */
204 #define TALLY_RESET             0x0001
205
206 /* PLA_CR */
207 #define CR_RST                  0x10
208 #define CR_RE                   0x08
209 #define CR_TE                   0x04
210
211 /* PLA_CRWECR */
212 #define CRWECR_NORAML           0x00
213 #define CRWECR_CONFIG           0xc0
214
215 /* PLA_OOB_CTRL */
216 #define NOW_IS_OOB              0x80
217 #define TXFIFO_EMPTY            0x20
218 #define RXFIFO_EMPTY            0x10
219 #define LINK_LIST_READY         0x02
220 #define DIS_MCU_CLROOB          0x01
221 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
222
223 /* PLA_MISC_1 */
224 #define RXDY_GATED_EN           0x0008
225
226 /* PLA_SFF_STS_7 */
227 #define RE_INIT_LL              0x8000
228 #define MCU_BORW_EN             0x4000
229
230 /* PLA_CPCR */
231 #define CPCR_RX_VLAN            0x0040
232
233 /* PLA_CFG_WOL */
234 #define MAGIC_EN                0x0001
235
236 /* PLA_TEREDO_CFG */
237 #define TEREDO_SEL              0x8000
238 #define TEREDO_WAKE_MASK        0x7f00
239 #define TEREDO_RS_EVENT_MASK    0x00fe
240 #define OOB_TEREDO_EN           0x0001
241
242 /* PAL_BDC_CR */
243 #define ALDPS_PROXY_MODE        0x0001
244
245 /* PLA_CONFIG34 */
246 #define LINK_ON_WAKE_EN         0x0010
247 #define LINK_OFF_WAKE_EN        0x0008
248
249 /* PLA_CONFIG5 */
250 #define BWF_EN                  0x0040
251 #define MWF_EN                  0x0020
252 #define UWF_EN                  0x0010
253 #define LAN_WAKE_EN             0x0002
254
255 /* PLA_LED_FEATURE */
256 #define LED_MODE_MASK           0x0700
257
258 /* PLA_PHY_PWR */
259 #define TX_10M_IDLE_EN          0x0080
260 #define PFM_PWM_SWITCH          0x0040
261
262 /* PLA_MAC_PWR_CTRL */
263 #define D3_CLK_GATED_EN         0x00004000
264 #define MCU_CLK_RATIO           0x07010f07
265 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
266 #define ALDPS_SPDWN_RATIO       0x0f87
267
268 /* PLA_MAC_PWR_CTRL2 */
269 #define EEE_SPDWN_RATIO         0x8007
270
271 /* PLA_MAC_PWR_CTRL3 */
272 #define PKT_AVAIL_SPDWN_EN      0x0100
273 #define SUSPEND_SPDWN_EN        0x0004
274 #define U1U2_SPDWN_EN           0x0002
275 #define L1_SPDWN_EN             0x0001
276
277 /* PLA_MAC_PWR_CTRL4 */
278 #define PWRSAVE_SPDWN_EN        0x1000
279 #define RXDV_SPDWN_EN           0x0800
280 #define TX10MIDLE_EN            0x0100
281 #define TP100_SPDWN_EN          0x0020
282 #define TP500_SPDWN_EN          0x0010
283 #define TP1000_SPDWN_EN         0x0008
284 #define EEE_SPDWN_EN            0x0001
285
286 /* PLA_GPHY_INTR_IMR */
287 #define GPHY_STS_MSK            0x0001
288 #define SPEED_DOWN_MSK          0x0002
289 #define SPDWN_RXDV_MSK          0x0004
290 #define SPDWN_LINKCHG_MSK       0x0008
291
292 /* PLA_PHYAR */
293 #define PHYAR_FLAG              0x80000000
294
295 /* PLA_EEE_CR */
296 #define EEE_RX_EN               0x0001
297 #define EEE_TX_EN               0x0002
298
299 /* PLA_BOOT_CTRL */
300 #define AUTOLOAD_DONE           0x0002
301
302 /* USB_USB2PHY */
303 #define USB2PHY_SUSPEND         0x0001
304 #define USB2PHY_L1              0x0002
305
306 /* USB_SSPHYLINK2 */
307 #define pwd_dn_scale_mask       0x3ffe
308 #define pwd_dn_scale(x)         ((x) << 1)
309
310 /* USB_CSR_DUMMY1 */
311 #define DYNAMIC_BURST           0x0001
312
313 /* USB_CSR_DUMMY2 */
314 #define EP4_FULL_FC             0x0001
315
316 /* USB_DEV_STAT */
317 #define STAT_SPEED_MASK         0x0006
318 #define STAT_SPEED_HIGH         0x0000
319 #define STAT_SPEED_FULL         0x0002
320
321 /* USB_TX_AGG */
322 #define TX_AGG_MAX_THRESHOLD    0x03
323
324 /* USB_RX_BUF_TH */
325 #define RX_THR_SUPPER           0x0c350180
326 #define RX_THR_HIGH             0x7a120180
327 #define RX_THR_SLOW             0xffff0180
328
329 /* USB_TX_DMA */
330 #define TEST_MODE_DISABLE       0x00000001
331 #define TX_SIZE_ADJUST1         0x00000100
332
333 /* USB_UPS_CTRL */
334 #define POWER_CUT               0x0100
335
336 /* USB_PM_CTRL_STATUS */
337 #define RESUME_INDICATE         0x0001
338
339 /* USB_USB_CTRL */
340 #define RX_AGG_DISABLE          0x0010
341
342 /* USB_U2P3_CTRL */
343 #define U2P3_ENABLE             0x0001
344
345 /* USB_POWER_CUT */
346 #define PWR_EN                  0x0001
347 #define PHASE2_EN               0x0008
348
349 /* USB_MISC_0 */
350 #define PCUT_STATUS             0x0001
351
352 /* USB_RX_EARLY_AGG */
353 #define EARLY_AGG_SUPPER        0x0e832981
354 #define EARLY_AGG_HIGH          0x0e837a12
355 #define EARLY_AGG_SLOW          0x0e83ffff
356
357 /* USB_WDT11_CTRL */
358 #define TIMER11_EN              0x0001
359
360 /* USB_LPM_CTRL */
361 /* bit 4 ~ 5: fifo empty boundary */
362 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
363 /* bit 2 ~ 3: LMP timer */
364 #define LPM_TIMER_MASK          0x0c
365 #define LPM_TIMER_500MS         0x04    /* 500 ms */
366 #define LPM_TIMER_500US         0x0c    /* 500 us */
367 #define ROK_EXIT_LPM            0x02
368
369 /* USB_AFE_CTRL2 */
370 #define SEN_VAL_MASK            0xf800
371 #define SEN_VAL_NORMAL          0xa000
372 #define SEL_RXIDLE              0x0100
373
374 /* OCP_ALDPS_CONFIG */
375 #define ENPWRSAVE               0x8000
376 #define ENPDNPS                 0x0200
377 #define LINKENA                 0x0100
378 #define DIS_SDSAVE              0x0010
379
380 /* OCP_PHY_STATUS */
381 #define PHY_STAT_MASK           0x0007
382 #define PHY_STAT_LAN_ON         3
383 #define PHY_STAT_PWRDN          5
384
385 /* OCP_POWER_CFG */
386 #define EEE_CLKDIV_EN           0x8000
387 #define EN_ALDPS                0x0004
388 #define EN_10M_PLLOFF           0x0001
389
390 /* OCP_EEE_CONFIG1 */
391 #define RG_TXLPI_MSK_HFDUP      0x8000
392 #define RG_MATCLR_EN            0x4000
393 #define EEE_10_CAP              0x2000
394 #define EEE_NWAY_EN             0x1000
395 #define TX_QUIET_EN             0x0200
396 #define RX_QUIET_EN             0x0100
397 #define sd_rise_time_mask       0x0070
398 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
399 #define RG_RXLPI_MSK_HFDUP      0x0008
400 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
401
402 /* OCP_EEE_CONFIG2 */
403 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
404 #define RG_DACQUIET_EN          0x0400
405 #define RG_LDVQUIET_EN          0x0200
406 #define RG_CKRSEL               0x0020
407 #define RG_EEEPRG_EN            0x0010
408
409 /* OCP_EEE_CONFIG3 */
410 #define fast_snr_mask           0xff80
411 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
412 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
413 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
414
415 /* OCP_EEE_AR */
416 /* bit[15:14] function */
417 #define FUN_ADDR                0x0000
418 #define FUN_DATA                0x4000
419 /* bit[4:0] device addr */
420
421 /* OCP_EEE_CFG */
422 #define CTAP_SHORT_EN           0x0040
423 #define EEE10_EN                0x0010
424
425 /* OCP_DOWN_SPEED */
426 #define EN_10M_BGOFF            0x0080
427
428 /* OCP_ADC_CFG */
429 #define CKADSEL_L               0x0100
430 #define ADC_EN                  0x0080
431 #define EN_EMI_L                0x0040
432
433 /* SRAM_LPF_CFG */
434 #define LPF_AUTO_TUNE           0x8000
435
436 /* SRAM_10M_AMP1 */
437 #define GDAC_IB_UPALL           0x0008
438
439 /* SRAM_10M_AMP2 */
440 #define AMP_DN                  0x0200
441
442 /* SRAM_IMPEDANCE */
443 #define RX_DRIVING_MASK         0x6000
444
445 enum rtl_register_content {
446         _1000bps        = 0x10,
447         _100bps         = 0x08,
448         _10bps          = 0x04,
449         LINK_STATUS     = 0x02,
450         FULL_DUP        = 0x01,
451 };
452
453 #define RTL8152_MAX_TX          4
454 #define RTL8152_MAX_RX          10
455 #define INTBUFSIZE              2
456 #define CRC_SIZE                4
457 #define TX_ALIGN                4
458 #define RX_ALIGN                8
459
460 #define INTR_LINK               0x0004
461
462 #define RTL8152_REQT_READ       0xc0
463 #define RTL8152_REQT_WRITE      0x40
464 #define RTL8152_REQ_GET_REGS    0x05
465 #define RTL8152_REQ_SET_REGS    0x05
466
467 #define BYTE_EN_DWORD           0xff
468 #define BYTE_EN_WORD            0x33
469 #define BYTE_EN_BYTE            0x11
470 #define BYTE_EN_SIX_BYTES       0x3f
471 #define BYTE_EN_START_MASK      0x0f
472 #define BYTE_EN_END_MASK        0xf0
473
474 #define RTL8153_MAX_PACKET      9216 /* 9K */
475 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
476 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
477 #define RTL8153_RMS             RTL8153_MAX_PACKET
478 #define RTL8152_TX_TIMEOUT      (5 * HZ)
479 #define RTL8152_NAPI_WEIGHT     64
480
481 /* rtl8152 flags */
482 enum rtl8152_flags {
483         RTL8152_UNPLUG = 0,
484         RTL8152_SET_RX_MODE,
485         WORK_ENABLE,
486         RTL8152_LINK_CHG,
487         SELECTIVE_SUSPEND,
488         PHY_RESET,
489         SCHEDULE_NAPI,
490 };
491
492 /* Define these values to match your device */
493 #define VENDOR_ID_REALTEK               0x0bda
494 #define VENDOR_ID_SAMSUNG               0x04e8
495
496 #define MCU_TYPE_PLA                    0x0100
497 #define MCU_TYPE_USB                    0x0000
498
499 struct tally_counter {
500         __le64  tx_packets;
501         __le64  rx_packets;
502         __le64  tx_errors;
503         __le32  rx_errors;
504         __le16  rx_missed;
505         __le16  align_errors;
506         __le32  tx_one_collision;
507         __le32  tx_multi_collision;
508         __le64  rx_unicast;
509         __le64  rx_broadcast;
510         __le32  rx_multicast;
511         __le16  tx_aborted;
512         __le16  tx_underrun;
513 };
514
515 struct rx_desc {
516         __le32 opts1;
517 #define RX_LEN_MASK                     0x7fff
518
519         __le32 opts2;
520 #define RD_UDP_CS                       BIT(23)
521 #define RD_TCP_CS                       BIT(22)
522 #define RD_IPV6_CS                      BIT(20)
523 #define RD_IPV4_CS                      BIT(19)
524
525         __le32 opts3;
526 #define IPF                             BIT(23) /* IP checksum fail */
527 #define UDPF                            BIT(22) /* UDP checksum fail */
528 #define TCPF                            BIT(21) /* TCP checksum fail */
529 #define RX_VLAN_TAG                     BIT(16)
530
531         __le32 opts4;
532         __le32 opts5;
533         __le32 opts6;
534 };
535
536 struct tx_desc {
537         __le32 opts1;
538 #define TX_FS                   BIT(31) /* First segment of a packet */
539 #define TX_LS                   BIT(30) /* Final segment of a packet */
540 #define GTSENDV4                BIT(28)
541 #define GTSENDV6                BIT(27)
542 #define GTTCPHO_SHIFT           18
543 #define GTTCPHO_MAX             0x7fU
544 #define TX_LEN_MAX              0x3ffffU
545
546         __le32 opts2;
547 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
548 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
549 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
550 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
551 #define MSS_SHIFT               17
552 #define MSS_MAX                 0x7ffU
553 #define TCPHO_SHIFT             17
554 #define TCPHO_MAX               0x7ffU
555 #define TX_VLAN_TAG             BIT(16)
556 };
557
558 struct r8152;
559
560 struct rx_agg {
561         struct list_head list;
562         struct urb *urb;
563         struct r8152 *context;
564         void *buffer;
565         void *head;
566 };
567
568 struct tx_agg {
569         struct list_head list;
570         struct urb *urb;
571         struct r8152 *context;
572         void *buffer;
573         void *head;
574         u32 skb_num;
575         u32 skb_len;
576 };
577
578 struct r8152 {
579         unsigned long flags;
580         struct usb_device *udev;
581         struct napi_struct napi;
582         struct usb_interface *intf;
583         struct net_device *netdev;
584         struct urb *intr_urb;
585         struct tx_agg tx_info[RTL8152_MAX_TX];
586         struct rx_agg rx_info[RTL8152_MAX_RX];
587         struct list_head rx_done, tx_free;
588         struct sk_buff_head tx_queue, rx_queue;
589         spinlock_t rx_lock, tx_lock;
590         struct delayed_work schedule;
591         struct mii_if_info mii;
592         struct mutex control;   /* use for hw setting */
593
594         struct rtl_ops {
595                 void (*init)(struct r8152 *);
596                 int (*enable)(struct r8152 *);
597                 void (*disable)(struct r8152 *);
598                 void (*up)(struct r8152 *);
599                 void (*down)(struct r8152 *);
600                 void (*unload)(struct r8152 *);
601                 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
602                 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
603         } rtl_ops;
604
605         int intr_interval;
606         u32 saved_wolopts;
607         u32 msg_enable;
608         u32 tx_qlen;
609         u16 ocp_base;
610         u8 *intr_buff;
611         u8 version;
612 };
613
614 enum rtl_version {
615         RTL_VER_UNKNOWN = 0,
616         RTL_VER_01,
617         RTL_VER_02,
618         RTL_VER_03,
619         RTL_VER_04,
620         RTL_VER_05,
621         RTL_VER_MAX
622 };
623
624 enum tx_csum_stat {
625         TX_CSUM_SUCCESS = 0,
626         TX_CSUM_TSO,
627         TX_CSUM_NONE
628 };
629
630 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
631  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
632  */
633 static const int multicast_filter_limit = 32;
634 static unsigned int agg_buf_sz = 16384;
635
636 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
637                                  VLAN_ETH_HLEN - VLAN_HLEN)
638
639 static
640 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
641 {
642         int ret;
643         void *tmp;
644
645         tmp = kmalloc(size, GFP_KERNEL);
646         if (!tmp)
647                 return -ENOMEM;
648
649         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
650                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
651                               value, index, tmp, size, 500);
652
653         memcpy(data, tmp, size);
654         kfree(tmp);
655
656         return ret;
657 }
658
659 static
660 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
661 {
662         int ret;
663         void *tmp;
664
665         tmp = kmemdup(data, size, GFP_KERNEL);
666         if (!tmp)
667                 return -ENOMEM;
668
669         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
670                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
671                               value, index, tmp, size, 500);
672
673         kfree(tmp);
674
675         return ret;
676 }
677
678 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
679                             void *data, u16 type)
680 {
681         u16 limit = 64;
682         int ret = 0;
683
684         if (test_bit(RTL8152_UNPLUG, &tp->flags))
685                 return -ENODEV;
686
687         /* both size and indix must be 4 bytes align */
688         if ((size & 3) || !size || (index & 3) || !data)
689                 return -EPERM;
690
691         if ((u32)index + (u32)size > 0xffff)
692                 return -EPERM;
693
694         while (size) {
695                 if (size > limit) {
696                         ret = get_registers(tp, index, type, limit, data);
697                         if (ret < 0)
698                                 break;
699
700                         index += limit;
701                         data += limit;
702                         size -= limit;
703                 } else {
704                         ret = get_registers(tp, index, type, size, data);
705                         if (ret < 0)
706                                 break;
707
708                         index += size;
709                         data += size;
710                         size = 0;
711                         break;
712                 }
713         }
714
715         if (ret == -ENODEV)
716                 set_bit(RTL8152_UNPLUG, &tp->flags);
717
718         return ret;
719 }
720
721 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
722                              u16 size, void *data, u16 type)
723 {
724         int ret;
725         u16 byteen_start, byteen_end, byen;
726         u16 limit = 512;
727
728         if (test_bit(RTL8152_UNPLUG, &tp->flags))
729                 return -ENODEV;
730
731         /* both size and indix must be 4 bytes align */
732         if ((size & 3) || !size || (index & 3) || !data)
733                 return -EPERM;
734
735         if ((u32)index + (u32)size > 0xffff)
736                 return -EPERM;
737
738         byteen_start = byteen & BYTE_EN_START_MASK;
739         byteen_end = byteen & BYTE_EN_END_MASK;
740
741         byen = byteen_start | (byteen_start << 4);
742         ret = set_registers(tp, index, type | byen, 4, data);
743         if (ret < 0)
744                 goto error1;
745
746         index += 4;
747         data += 4;
748         size -= 4;
749
750         if (size) {
751                 size -= 4;
752
753                 while (size) {
754                         if (size > limit) {
755                                 ret = set_registers(tp, index,
756                                                     type | BYTE_EN_DWORD,
757                                                     limit, data);
758                                 if (ret < 0)
759                                         goto error1;
760
761                                 index += limit;
762                                 data += limit;
763                                 size -= limit;
764                         } else {
765                                 ret = set_registers(tp, index,
766                                                     type | BYTE_EN_DWORD,
767                                                     size, data);
768                                 if (ret < 0)
769                                         goto error1;
770
771                                 index += size;
772                                 data += size;
773                                 size = 0;
774                                 break;
775                         }
776                 }
777
778                 byen = byteen_end | (byteen_end >> 4);
779                 ret = set_registers(tp, index, type | byen, 4, data);
780                 if (ret < 0)
781                         goto error1;
782         }
783
784 error1:
785         if (ret == -ENODEV)
786                 set_bit(RTL8152_UNPLUG, &tp->flags);
787
788         return ret;
789 }
790
791 static inline
792 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
793 {
794         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
795 }
796
797 static inline
798 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
799 {
800         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
801 }
802
803 static inline
804 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
805 {
806         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
807 }
808
809 static inline
810 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
811 {
812         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
813 }
814
815 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
816 {
817         __le32 data;
818
819         generic_ocp_read(tp, index, sizeof(data), &data, type);
820
821         return __le32_to_cpu(data);
822 }
823
824 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
825 {
826         __le32 tmp = __cpu_to_le32(data);
827
828         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
829 }
830
831 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
832 {
833         u32 data;
834         __le32 tmp;
835         u8 shift = index & 2;
836
837         index &= ~3;
838
839         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
840
841         data = __le32_to_cpu(tmp);
842         data >>= (shift * 8);
843         data &= 0xffff;
844
845         return (u16)data;
846 }
847
848 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
849 {
850         u32 mask = 0xffff;
851         __le32 tmp;
852         u16 byen = BYTE_EN_WORD;
853         u8 shift = index & 2;
854
855         data &= mask;
856
857         if (index & 2) {
858                 byen <<= shift;
859                 mask <<= (shift * 8);
860                 data <<= (shift * 8);
861                 index &= ~3;
862         }
863
864         tmp = __cpu_to_le32(data);
865
866         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
867 }
868
869 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
870 {
871         u32 data;
872         __le32 tmp;
873         u8 shift = index & 3;
874
875         index &= ~3;
876
877         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
878
879         data = __le32_to_cpu(tmp);
880         data >>= (shift * 8);
881         data &= 0xff;
882
883         return (u8)data;
884 }
885
886 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
887 {
888         u32 mask = 0xff;
889         __le32 tmp;
890         u16 byen = BYTE_EN_BYTE;
891         u8 shift = index & 3;
892
893         data &= mask;
894
895         if (index & 3) {
896                 byen <<= shift;
897                 mask <<= (shift * 8);
898                 data <<= (shift * 8);
899                 index &= ~3;
900         }
901
902         tmp = __cpu_to_le32(data);
903
904         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
905 }
906
907 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
908 {
909         u16 ocp_base, ocp_index;
910
911         ocp_base = addr & 0xf000;
912         if (ocp_base != tp->ocp_base) {
913                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
914                 tp->ocp_base = ocp_base;
915         }
916
917         ocp_index = (addr & 0x0fff) | 0xb000;
918         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
919 }
920
921 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
922 {
923         u16 ocp_base, ocp_index;
924
925         ocp_base = addr & 0xf000;
926         if (ocp_base != tp->ocp_base) {
927                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
928                 tp->ocp_base = ocp_base;
929         }
930
931         ocp_index = (addr & 0x0fff) | 0xb000;
932         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
933 }
934
935 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
936 {
937         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
938 }
939
940 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
941 {
942         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
943 }
944
945 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
946 {
947         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
948         ocp_reg_write(tp, OCP_SRAM_DATA, data);
949 }
950
951 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
952 {
953         struct r8152 *tp = netdev_priv(netdev);
954         int ret;
955
956         if (test_bit(RTL8152_UNPLUG, &tp->flags))
957                 return -ENODEV;
958
959         if (phy_id != R8152_PHY_ID)
960                 return -EINVAL;
961
962         ret = r8152_mdio_read(tp, reg);
963
964         return ret;
965 }
966
967 static
968 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
969 {
970         struct r8152 *tp = netdev_priv(netdev);
971
972         if (test_bit(RTL8152_UNPLUG, &tp->flags))
973                 return;
974
975         if (phy_id != R8152_PHY_ID)
976                 return;
977
978         r8152_mdio_write(tp, reg, val);
979 }
980
981 static int
982 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
983
984 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
985 {
986         struct r8152 *tp = netdev_priv(netdev);
987         struct sockaddr *addr = p;
988         int ret = -EADDRNOTAVAIL;
989
990         if (!is_valid_ether_addr(addr->sa_data))
991                 goto out1;
992
993         ret = usb_autopm_get_interface(tp->intf);
994         if (ret < 0)
995                 goto out1;
996
997         mutex_lock(&tp->control);
998
999         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1000
1001         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1002         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1003         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1004
1005         mutex_unlock(&tp->control);
1006
1007         usb_autopm_put_interface(tp->intf);
1008 out1:
1009         return ret;
1010 }
1011
1012 static int set_ethernet_addr(struct r8152 *tp)
1013 {
1014         struct net_device *dev = tp->netdev;
1015         struct sockaddr sa;
1016         int ret;
1017
1018         if (tp->version == RTL_VER_01)
1019                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1020         else
1021                 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1022
1023         if (ret < 0) {
1024                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1025         } else if (!is_valid_ether_addr(sa.sa_data)) {
1026                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1027                           sa.sa_data);
1028                 eth_hw_addr_random(dev);
1029                 ether_addr_copy(sa.sa_data, dev->dev_addr);
1030                 ret = rtl8152_set_mac_address(dev, &sa);
1031                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1032                            sa.sa_data);
1033         } else {
1034                 if (tp->version == RTL_VER_01)
1035                         ether_addr_copy(dev->dev_addr, sa.sa_data);
1036                 else
1037                         ret = rtl8152_set_mac_address(dev, &sa);
1038         }
1039
1040         return ret;
1041 }
1042
1043 static void read_bulk_callback(struct urb *urb)
1044 {
1045         struct net_device *netdev;
1046         int status = urb->status;
1047         struct rx_agg *agg;
1048         struct r8152 *tp;
1049
1050         agg = urb->context;
1051         if (!agg)
1052                 return;
1053
1054         tp = agg->context;
1055         if (!tp)
1056                 return;
1057
1058         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1059                 return;
1060
1061         if (!test_bit(WORK_ENABLE, &tp->flags))
1062                 return;
1063
1064         netdev = tp->netdev;
1065
1066         /* When link down, the driver would cancel all bulks. */
1067         /* This avoid the re-submitting bulk */
1068         if (!netif_carrier_ok(netdev))
1069                 return;
1070
1071         usb_mark_last_busy(tp->udev);
1072
1073         switch (status) {
1074         case 0:
1075                 if (urb->actual_length < ETH_ZLEN)
1076                         break;
1077
1078                 spin_lock(&tp->rx_lock);
1079                 list_add_tail(&agg->list, &tp->rx_done);
1080                 spin_unlock(&tp->rx_lock);
1081                 napi_schedule(&tp->napi);
1082                 return;
1083         case -ESHUTDOWN:
1084                 set_bit(RTL8152_UNPLUG, &tp->flags);
1085                 netif_device_detach(tp->netdev);
1086                 return;
1087         case -ENOENT:
1088                 return; /* the urb is in unlink state */
1089         case -ETIME:
1090                 if (net_ratelimit())
1091                         netdev_warn(netdev, "maybe reset is needed?\n");
1092                 break;
1093         default:
1094                 if (net_ratelimit())
1095                         netdev_warn(netdev, "Rx status %d\n", status);
1096                 break;
1097         }
1098
1099         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1100 }
1101
1102 static void write_bulk_callback(struct urb *urb)
1103 {
1104         struct net_device_stats *stats;
1105         struct net_device *netdev;
1106         struct tx_agg *agg;
1107         struct r8152 *tp;
1108         int status = urb->status;
1109
1110         agg = urb->context;
1111         if (!agg)
1112                 return;
1113
1114         tp = agg->context;
1115         if (!tp)
1116                 return;
1117
1118         netdev = tp->netdev;
1119         stats = &netdev->stats;
1120         if (status) {
1121                 if (net_ratelimit())
1122                         netdev_warn(netdev, "Tx status %d\n", status);
1123                 stats->tx_errors += agg->skb_num;
1124         } else {
1125                 stats->tx_packets += agg->skb_num;
1126                 stats->tx_bytes += agg->skb_len;
1127         }
1128
1129         spin_lock(&tp->tx_lock);
1130         list_add_tail(&agg->list, &tp->tx_free);
1131         spin_unlock(&tp->tx_lock);
1132
1133         usb_autopm_put_interface_async(tp->intf);
1134
1135         if (!netif_carrier_ok(netdev))
1136                 return;
1137
1138         if (!test_bit(WORK_ENABLE, &tp->flags))
1139                 return;
1140
1141         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1142                 return;
1143
1144         if (!skb_queue_empty(&tp->tx_queue))
1145                 napi_schedule(&tp->napi);
1146 }
1147
1148 static void intr_callback(struct urb *urb)
1149 {
1150         struct r8152 *tp;
1151         __le16 *d;
1152         int status = urb->status;
1153         int res;
1154
1155         tp = urb->context;
1156         if (!tp)
1157                 return;
1158
1159         if (!test_bit(WORK_ENABLE, &tp->flags))
1160                 return;
1161
1162         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1163                 return;
1164
1165         switch (status) {
1166         case 0:                 /* success */
1167                 break;
1168         case -ECONNRESET:       /* unlink */
1169         case -ESHUTDOWN:
1170                 netif_device_detach(tp->netdev);
1171         case -ENOENT:
1172         case -EPROTO:
1173                 netif_info(tp, intr, tp->netdev,
1174                            "Stop submitting intr, status %d\n", status);
1175                 return;
1176         case -EOVERFLOW:
1177                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1178                 goto resubmit;
1179         /* -EPIPE:  should clear the halt */
1180         default:
1181                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1182                 goto resubmit;
1183         }
1184
1185         d = urb->transfer_buffer;
1186         if (INTR_LINK & __le16_to_cpu(d[0])) {
1187                 if (!netif_carrier_ok(tp->netdev)) {
1188                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1189                         schedule_delayed_work(&tp->schedule, 0);
1190                 }
1191         } else {
1192                 if (netif_carrier_ok(tp->netdev)) {
1193                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1194                         schedule_delayed_work(&tp->schedule, 0);
1195                 }
1196         }
1197
1198 resubmit:
1199         res = usb_submit_urb(urb, GFP_ATOMIC);
1200         if (res == -ENODEV) {
1201                 set_bit(RTL8152_UNPLUG, &tp->flags);
1202                 netif_device_detach(tp->netdev);
1203         } else if (res) {
1204                 netif_err(tp, intr, tp->netdev,
1205                           "can't resubmit intr, status %d\n", res);
1206         }
1207 }
1208
1209 static inline void *rx_agg_align(void *data)
1210 {
1211         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1212 }
1213
1214 static inline void *tx_agg_align(void *data)
1215 {
1216         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1217 }
1218
1219 static void free_all_mem(struct r8152 *tp)
1220 {
1221         int i;
1222
1223         for (i = 0; i < RTL8152_MAX_RX; i++) {
1224                 usb_free_urb(tp->rx_info[i].urb);
1225                 tp->rx_info[i].urb = NULL;
1226
1227                 kfree(tp->rx_info[i].buffer);
1228                 tp->rx_info[i].buffer = NULL;
1229                 tp->rx_info[i].head = NULL;
1230         }
1231
1232         for (i = 0; i < RTL8152_MAX_TX; i++) {
1233                 usb_free_urb(tp->tx_info[i].urb);
1234                 tp->tx_info[i].urb = NULL;
1235
1236                 kfree(tp->tx_info[i].buffer);
1237                 tp->tx_info[i].buffer = NULL;
1238                 tp->tx_info[i].head = NULL;
1239         }
1240
1241         usb_free_urb(tp->intr_urb);
1242         tp->intr_urb = NULL;
1243
1244         kfree(tp->intr_buff);
1245         tp->intr_buff = NULL;
1246 }
1247
1248 static int alloc_all_mem(struct r8152 *tp)
1249 {
1250         struct net_device *netdev = tp->netdev;
1251         struct usb_interface *intf = tp->intf;
1252         struct usb_host_interface *alt = intf->cur_altsetting;
1253         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1254         struct urb *urb;
1255         int node, i;
1256         u8 *buf;
1257
1258         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1259
1260         spin_lock_init(&tp->rx_lock);
1261         spin_lock_init(&tp->tx_lock);
1262         INIT_LIST_HEAD(&tp->tx_free);
1263         skb_queue_head_init(&tp->tx_queue);
1264         skb_queue_head_init(&tp->rx_queue);
1265
1266         for (i = 0; i < RTL8152_MAX_RX; i++) {
1267                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1268                 if (!buf)
1269                         goto err1;
1270
1271                 if (buf != rx_agg_align(buf)) {
1272                         kfree(buf);
1273                         buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1274                                            node);
1275                         if (!buf)
1276                                 goto err1;
1277                 }
1278
1279                 urb = usb_alloc_urb(0, GFP_KERNEL);
1280                 if (!urb) {
1281                         kfree(buf);
1282                         goto err1;
1283                 }
1284
1285                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1286                 tp->rx_info[i].context = tp;
1287                 tp->rx_info[i].urb = urb;
1288                 tp->rx_info[i].buffer = buf;
1289                 tp->rx_info[i].head = rx_agg_align(buf);
1290         }
1291
1292         for (i = 0; i < RTL8152_MAX_TX; i++) {
1293                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1294                 if (!buf)
1295                         goto err1;
1296
1297                 if (buf != tx_agg_align(buf)) {
1298                         kfree(buf);
1299                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1300                                            node);
1301                         if (!buf)
1302                                 goto err1;
1303                 }
1304
1305                 urb = usb_alloc_urb(0, GFP_KERNEL);
1306                 if (!urb) {
1307                         kfree(buf);
1308                         goto err1;
1309                 }
1310
1311                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1312                 tp->tx_info[i].context = tp;
1313                 tp->tx_info[i].urb = urb;
1314                 tp->tx_info[i].buffer = buf;
1315                 tp->tx_info[i].head = tx_agg_align(buf);
1316
1317                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1318         }
1319
1320         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1321         if (!tp->intr_urb)
1322                 goto err1;
1323
1324         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1325         if (!tp->intr_buff)
1326                 goto err1;
1327
1328         tp->intr_interval = (int)ep_intr->desc.bInterval;
1329         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1330                          tp->intr_buff, INTBUFSIZE, intr_callback,
1331                          tp, tp->intr_interval);
1332
1333         return 0;
1334
1335 err1:
1336         free_all_mem(tp);
1337         return -ENOMEM;
1338 }
1339
1340 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1341 {
1342         struct tx_agg *agg = NULL;
1343         unsigned long flags;
1344
1345         if (list_empty(&tp->tx_free))
1346                 return NULL;
1347
1348         spin_lock_irqsave(&tp->tx_lock, flags);
1349         if (!list_empty(&tp->tx_free)) {
1350                 struct list_head *cursor;
1351
1352                 cursor = tp->tx_free.next;
1353                 list_del_init(cursor);
1354                 agg = list_entry(cursor, struct tx_agg, list);
1355         }
1356         spin_unlock_irqrestore(&tp->tx_lock, flags);
1357
1358         return agg;
1359 }
1360
1361 /* r8152_csum_workaround()
1362  * The hw limites the value the transport offset. When the offset is out of the
1363  * range, calculate the checksum by sw.
1364  */
1365 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1366                                   struct sk_buff_head *list)
1367 {
1368         if (skb_shinfo(skb)->gso_size) {
1369                 netdev_features_t features = tp->netdev->features;
1370                 struct sk_buff_head seg_list;
1371                 struct sk_buff *segs, *nskb;
1372
1373                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1374                 segs = skb_gso_segment(skb, features);
1375                 if (IS_ERR(segs) || !segs)
1376                         goto drop;
1377
1378                 __skb_queue_head_init(&seg_list);
1379
1380                 do {
1381                         nskb = segs;
1382                         segs = segs->next;
1383                         nskb->next = NULL;
1384                         __skb_queue_tail(&seg_list, nskb);
1385                 } while (segs);
1386
1387                 skb_queue_splice(&seg_list, list);
1388                 dev_kfree_skb(skb);
1389         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1390                 if (skb_checksum_help(skb) < 0)
1391                         goto drop;
1392
1393                 __skb_queue_head(list, skb);
1394         } else {
1395                 struct net_device_stats *stats;
1396
1397 drop:
1398                 stats = &tp->netdev->stats;
1399                 stats->tx_dropped++;
1400                 dev_kfree_skb(skb);
1401         }
1402 }
1403
1404 /* msdn_giant_send_check()
1405  * According to the document of microsoft, the TCP Pseudo Header excludes the
1406  * packet length for IPv6 TCP large packets.
1407  */
1408 static int msdn_giant_send_check(struct sk_buff *skb)
1409 {
1410         const struct ipv6hdr *ipv6h;
1411         struct tcphdr *th;
1412         int ret;
1413
1414         ret = skb_cow_head(skb, 0);
1415         if (ret)
1416                 return ret;
1417
1418         ipv6h = ipv6_hdr(skb);
1419         th = tcp_hdr(skb);
1420
1421         th->check = 0;
1422         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1423
1424         return ret;
1425 }
1426
1427 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1428 {
1429         if (skb_vlan_tag_present(skb)) {
1430                 u32 opts2;
1431
1432                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1433                 desc->opts2 |= cpu_to_le32(opts2);
1434         }
1435 }
1436
1437 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1438 {
1439         u32 opts2 = le32_to_cpu(desc->opts2);
1440
1441         if (opts2 & RX_VLAN_TAG)
1442                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1443                                        swab16(opts2 & 0xffff));
1444 }
1445
1446 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1447                          struct sk_buff *skb, u32 len, u32 transport_offset)
1448 {
1449         u32 mss = skb_shinfo(skb)->gso_size;
1450         u32 opts1, opts2 = 0;
1451         int ret = TX_CSUM_SUCCESS;
1452
1453         WARN_ON_ONCE(len > TX_LEN_MAX);
1454
1455         opts1 = len | TX_FS | TX_LS;
1456
1457         if (mss) {
1458                 if (transport_offset > GTTCPHO_MAX) {
1459                         netif_warn(tp, tx_err, tp->netdev,
1460                                    "Invalid transport offset 0x%x for TSO\n",
1461                                    transport_offset);
1462                         ret = TX_CSUM_TSO;
1463                         goto unavailable;
1464                 }
1465
1466                 switch (vlan_get_protocol(skb)) {
1467                 case htons(ETH_P_IP):
1468                         opts1 |= GTSENDV4;
1469                         break;
1470
1471                 case htons(ETH_P_IPV6):
1472                         if (msdn_giant_send_check(skb)) {
1473                                 ret = TX_CSUM_TSO;
1474                                 goto unavailable;
1475                         }
1476                         opts1 |= GTSENDV6;
1477                         break;
1478
1479                 default:
1480                         WARN_ON_ONCE(1);
1481                         break;
1482                 }
1483
1484                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1485                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1486         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1487                 u8 ip_protocol;
1488
1489                 if (transport_offset > TCPHO_MAX) {
1490                         netif_warn(tp, tx_err, tp->netdev,
1491                                    "Invalid transport offset 0x%x\n",
1492                                    transport_offset);
1493                         ret = TX_CSUM_NONE;
1494                         goto unavailable;
1495                 }
1496
1497                 switch (vlan_get_protocol(skb)) {
1498                 case htons(ETH_P_IP):
1499                         opts2 |= IPV4_CS;
1500                         ip_protocol = ip_hdr(skb)->protocol;
1501                         break;
1502
1503                 case htons(ETH_P_IPV6):
1504                         opts2 |= IPV6_CS;
1505                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1506                         break;
1507
1508                 default:
1509                         ip_protocol = IPPROTO_RAW;
1510                         break;
1511                 }
1512
1513                 if (ip_protocol == IPPROTO_TCP)
1514                         opts2 |= TCP_CS;
1515                 else if (ip_protocol == IPPROTO_UDP)
1516                         opts2 |= UDP_CS;
1517                 else
1518                         WARN_ON_ONCE(1);
1519
1520                 opts2 |= transport_offset << TCPHO_SHIFT;
1521         }
1522
1523         desc->opts2 = cpu_to_le32(opts2);
1524         desc->opts1 = cpu_to_le32(opts1);
1525
1526 unavailable:
1527         return ret;
1528 }
1529
1530 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1531 {
1532         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1533         int remain, ret;
1534         u8 *tx_data;
1535
1536         __skb_queue_head_init(&skb_head);
1537         spin_lock(&tx_queue->lock);
1538         skb_queue_splice_init(tx_queue, &skb_head);
1539         spin_unlock(&tx_queue->lock);
1540
1541         tx_data = agg->head;
1542         agg->skb_num = 0;
1543         agg->skb_len = 0;
1544         remain = agg_buf_sz;
1545
1546         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1547                 struct tx_desc *tx_desc;
1548                 struct sk_buff *skb;
1549                 unsigned int len;
1550                 u32 offset;
1551
1552                 skb = __skb_dequeue(&skb_head);
1553                 if (!skb)
1554                         break;
1555
1556                 len = skb->len + sizeof(*tx_desc);
1557
1558                 if (len > remain) {
1559                         __skb_queue_head(&skb_head, skb);
1560                         break;
1561                 }
1562
1563                 tx_data = tx_agg_align(tx_data);
1564                 tx_desc = (struct tx_desc *)tx_data;
1565
1566                 offset = (u32)skb_transport_offset(skb);
1567
1568                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1569                         r8152_csum_workaround(tp, skb, &skb_head);
1570                         continue;
1571                 }
1572
1573                 rtl_tx_vlan_tag(tx_desc, skb);
1574
1575                 tx_data += sizeof(*tx_desc);
1576
1577                 len = skb->len;
1578                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1579                         struct net_device_stats *stats = &tp->netdev->stats;
1580
1581                         stats->tx_dropped++;
1582                         dev_kfree_skb_any(skb);
1583                         tx_data -= sizeof(*tx_desc);
1584                         continue;
1585                 }
1586
1587                 tx_data += len;
1588                 agg->skb_len += len;
1589                 agg->skb_num++;
1590
1591                 dev_kfree_skb_any(skb);
1592
1593                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1594         }
1595
1596         if (!skb_queue_empty(&skb_head)) {
1597                 spin_lock(&tx_queue->lock);
1598                 skb_queue_splice(&skb_head, tx_queue);
1599                 spin_unlock(&tx_queue->lock);
1600         }
1601
1602         netif_tx_lock(tp->netdev);
1603
1604         if (netif_queue_stopped(tp->netdev) &&
1605             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1606                 netif_wake_queue(tp->netdev);
1607
1608         netif_tx_unlock(tp->netdev);
1609
1610         ret = usb_autopm_get_interface_async(tp->intf);
1611         if (ret < 0)
1612                 goto out_tx_fill;
1613
1614         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1615                           agg->head, (int)(tx_data - (u8 *)agg->head),
1616                           (usb_complete_t)write_bulk_callback, agg);
1617
1618         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1619         if (ret < 0)
1620                 usb_autopm_put_interface_async(tp->intf);
1621
1622 out_tx_fill:
1623         return ret;
1624 }
1625
1626 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1627 {
1628         u8 checksum = CHECKSUM_NONE;
1629         u32 opts2, opts3;
1630
1631         if (tp->version == RTL_VER_01)
1632                 goto return_result;
1633
1634         opts2 = le32_to_cpu(rx_desc->opts2);
1635         opts3 = le32_to_cpu(rx_desc->opts3);
1636
1637         if (opts2 & RD_IPV4_CS) {
1638                 if (opts3 & IPF)
1639                         checksum = CHECKSUM_NONE;
1640                 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1641                         checksum = CHECKSUM_NONE;
1642                 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1643                         checksum = CHECKSUM_NONE;
1644                 else
1645                         checksum = CHECKSUM_UNNECESSARY;
1646         } else if (RD_IPV6_CS) {
1647                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1648                         checksum = CHECKSUM_UNNECESSARY;
1649                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1650                         checksum = CHECKSUM_UNNECESSARY;
1651         }
1652
1653 return_result:
1654         return checksum;
1655 }
1656
1657 static int rx_bottom(struct r8152 *tp, int budget)
1658 {
1659         unsigned long flags;
1660         struct list_head *cursor, *next, rx_queue;
1661         int ret = 0, work_done = 0;
1662
1663         if (!skb_queue_empty(&tp->rx_queue)) {
1664                 while (work_done < budget) {
1665                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1666                         struct net_device *netdev = tp->netdev;
1667                         struct net_device_stats *stats = &netdev->stats;
1668                         unsigned int pkt_len;
1669
1670                         if (!skb)
1671                                 break;
1672
1673                         pkt_len = skb->len;
1674                         napi_gro_receive(&tp->napi, skb);
1675                         work_done++;
1676                         stats->rx_packets++;
1677                         stats->rx_bytes += pkt_len;
1678                 }
1679         }
1680
1681         if (list_empty(&tp->rx_done))
1682                 goto out1;
1683
1684         INIT_LIST_HEAD(&rx_queue);
1685         spin_lock_irqsave(&tp->rx_lock, flags);
1686         list_splice_init(&tp->rx_done, &rx_queue);
1687         spin_unlock_irqrestore(&tp->rx_lock, flags);
1688
1689         list_for_each_safe(cursor, next, &rx_queue) {
1690                 struct rx_desc *rx_desc;
1691                 struct rx_agg *agg;
1692                 int len_used = 0;
1693                 struct urb *urb;
1694                 u8 *rx_data;
1695
1696                 list_del_init(cursor);
1697
1698                 agg = list_entry(cursor, struct rx_agg, list);
1699                 urb = agg->urb;
1700                 if (urb->actual_length < ETH_ZLEN)
1701                         goto submit;
1702
1703                 rx_desc = agg->head;
1704                 rx_data = agg->head;
1705                 len_used += sizeof(struct rx_desc);
1706
1707                 while (urb->actual_length > len_used) {
1708                         struct net_device *netdev = tp->netdev;
1709                         struct net_device_stats *stats = &netdev->stats;
1710                         unsigned int pkt_len;
1711                         struct sk_buff *skb;
1712
1713                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1714                         if (pkt_len < ETH_ZLEN)
1715                                 break;
1716
1717                         len_used += pkt_len;
1718                         if (urb->actual_length < len_used)
1719                                 break;
1720
1721                         pkt_len -= CRC_SIZE;
1722                         rx_data += sizeof(struct rx_desc);
1723
1724                         skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1725                         if (!skb) {
1726                                 stats->rx_dropped++;
1727                                 goto find_next_rx;
1728                         }
1729
1730                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1731                         memcpy(skb->data, rx_data, pkt_len);
1732                         skb_put(skb, pkt_len);
1733                         skb->protocol = eth_type_trans(skb, netdev);
1734                         rtl_rx_vlan_tag(rx_desc, skb);
1735                         if (work_done < budget) {
1736                                 napi_gro_receive(&tp->napi, skb);
1737                                 work_done++;
1738                                 stats->rx_packets++;
1739                                 stats->rx_bytes += pkt_len;
1740                         } else {
1741                                 __skb_queue_tail(&tp->rx_queue, skb);
1742                         }
1743
1744 find_next_rx:
1745                         rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1746                         rx_desc = (struct rx_desc *)rx_data;
1747                         len_used = (int)(rx_data - (u8 *)agg->head);
1748                         len_used += sizeof(struct rx_desc);
1749                 }
1750
1751 submit:
1752                 if (!ret) {
1753                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1754                 } else {
1755                         urb->actual_length = 0;
1756                         list_add_tail(&agg->list, next);
1757                 }
1758         }
1759
1760         if (!list_empty(&rx_queue)) {
1761                 spin_lock_irqsave(&tp->rx_lock, flags);
1762                 list_splice_tail(&rx_queue, &tp->rx_done);
1763                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1764         }
1765
1766 out1:
1767         return work_done;
1768 }
1769
1770 static void tx_bottom(struct r8152 *tp)
1771 {
1772         int res;
1773
1774         do {
1775                 struct tx_agg *agg;
1776
1777                 if (skb_queue_empty(&tp->tx_queue))
1778                         break;
1779
1780                 agg = r8152_get_tx_agg(tp);
1781                 if (!agg)
1782                         break;
1783
1784                 res = r8152_tx_agg_fill(tp, agg);
1785                 if (res) {
1786                         struct net_device *netdev = tp->netdev;
1787
1788                         if (res == -ENODEV) {
1789                                 set_bit(RTL8152_UNPLUG, &tp->flags);
1790                                 netif_device_detach(netdev);
1791                         } else {
1792                                 struct net_device_stats *stats = &netdev->stats;
1793                                 unsigned long flags;
1794
1795                                 netif_warn(tp, tx_err, netdev,
1796                                            "failed tx_urb %d\n", res);
1797                                 stats->tx_dropped += agg->skb_num;
1798
1799                                 spin_lock_irqsave(&tp->tx_lock, flags);
1800                                 list_add_tail(&agg->list, &tp->tx_free);
1801                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
1802                         }
1803                 }
1804         } while (res == 0);
1805 }
1806
1807 static void bottom_half(struct r8152 *tp)
1808 {
1809         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1810                 return;
1811
1812         if (!test_bit(WORK_ENABLE, &tp->flags))
1813                 return;
1814
1815         /* When link down, the driver would cancel all bulks. */
1816         /* This avoid the re-submitting bulk */
1817         if (!netif_carrier_ok(tp->netdev))
1818                 return;
1819
1820         clear_bit(SCHEDULE_NAPI, &tp->flags);
1821
1822         tx_bottom(tp);
1823 }
1824
1825 static int r8152_poll(struct napi_struct *napi, int budget)
1826 {
1827         struct r8152 *tp = container_of(napi, struct r8152, napi);
1828         int work_done;
1829
1830         work_done = rx_bottom(tp, budget);
1831         bottom_half(tp);
1832
1833         if (work_done < budget) {
1834                 napi_complete(napi);
1835                 if (!list_empty(&tp->rx_done))
1836                         napi_schedule(napi);
1837         }
1838
1839         return work_done;
1840 }
1841
1842 static
1843 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1844 {
1845         int ret;
1846
1847         /* The rx would be stopped, so skip submitting */
1848         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1849             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1850                 return 0;
1851
1852         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1853                           agg->head, agg_buf_sz,
1854                           (usb_complete_t)read_bulk_callback, agg);
1855
1856         ret = usb_submit_urb(agg->urb, mem_flags);
1857         if (ret == -ENODEV) {
1858                 set_bit(RTL8152_UNPLUG, &tp->flags);
1859                 netif_device_detach(tp->netdev);
1860         } else if (ret) {
1861                 struct urb *urb = agg->urb;
1862                 unsigned long flags;
1863
1864                 urb->actual_length = 0;
1865                 spin_lock_irqsave(&tp->rx_lock, flags);
1866                 list_add_tail(&agg->list, &tp->rx_done);
1867                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1868
1869                 netif_err(tp, rx_err, tp->netdev,
1870                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1871
1872                 napi_schedule(&tp->napi);
1873         }
1874
1875         return ret;
1876 }
1877
1878 static void rtl_drop_queued_tx(struct r8152 *tp)
1879 {
1880         struct net_device_stats *stats = &tp->netdev->stats;
1881         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1882         struct sk_buff *skb;
1883
1884         if (skb_queue_empty(tx_queue))
1885                 return;
1886
1887         __skb_queue_head_init(&skb_head);
1888         spin_lock_bh(&tx_queue->lock);
1889         skb_queue_splice_init(tx_queue, &skb_head);
1890         spin_unlock_bh(&tx_queue->lock);
1891
1892         while ((skb = __skb_dequeue(&skb_head))) {
1893                 dev_kfree_skb(skb);
1894                 stats->tx_dropped++;
1895         }
1896 }
1897
1898 static void rtl8152_tx_timeout(struct net_device *netdev)
1899 {
1900         struct r8152 *tp = netdev_priv(netdev);
1901         int i;
1902
1903         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1904         for (i = 0; i < RTL8152_MAX_TX; i++)
1905                 usb_unlink_urb(tp->tx_info[i].urb);
1906 }
1907
1908 static void rtl8152_set_rx_mode(struct net_device *netdev)
1909 {
1910         struct r8152 *tp = netdev_priv(netdev);
1911
1912         if (netif_carrier_ok(netdev)) {
1913                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1914                 schedule_delayed_work(&tp->schedule, 0);
1915         }
1916 }
1917
1918 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1919 {
1920         struct r8152 *tp = netdev_priv(netdev);
1921         u32 mc_filter[2];       /* Multicast hash filter */
1922         __le32 tmp[2];
1923         u32 ocp_data;
1924
1925         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1926         netif_stop_queue(netdev);
1927         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1928         ocp_data &= ~RCR_ACPT_ALL;
1929         ocp_data |= RCR_AB | RCR_APM;
1930
1931         if (netdev->flags & IFF_PROMISC) {
1932                 /* Unconditionally log net taps. */
1933                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1934                 ocp_data |= RCR_AM | RCR_AAP;
1935                 mc_filter[1] = 0xffffffff;
1936                 mc_filter[0] = 0xffffffff;
1937         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1938                    (netdev->flags & IFF_ALLMULTI)) {
1939                 /* Too many to filter perfectly -- accept all multicasts. */
1940                 ocp_data |= RCR_AM;
1941                 mc_filter[1] = 0xffffffff;
1942                 mc_filter[0] = 0xffffffff;
1943         } else {
1944                 struct netdev_hw_addr *ha;
1945
1946                 mc_filter[1] = 0;
1947                 mc_filter[0] = 0;
1948                 netdev_for_each_mc_addr(ha, netdev) {
1949                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1950
1951                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1952                         ocp_data |= RCR_AM;
1953                 }
1954         }
1955
1956         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1957         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1958
1959         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1960         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1961         netif_wake_queue(netdev);
1962 }
1963
1964 static netdev_features_t
1965 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1966                        netdev_features_t features)
1967 {
1968         u32 mss = skb_shinfo(skb)->gso_size;
1969         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1970         int offset = skb_transport_offset(skb);
1971
1972         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
1973                 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
1974         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1975                 features &= ~NETIF_F_GSO_MASK;
1976
1977         return features;
1978 }
1979
1980 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1981                                       struct net_device *netdev)
1982 {
1983         struct r8152 *tp = netdev_priv(netdev);
1984
1985         skb_tx_timestamp(skb);
1986
1987         skb_queue_tail(&tp->tx_queue, skb);
1988
1989         if (!list_empty(&tp->tx_free)) {
1990                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1991                         set_bit(SCHEDULE_NAPI, &tp->flags);
1992                         schedule_delayed_work(&tp->schedule, 0);
1993                 } else {
1994                         usb_mark_last_busy(tp->udev);
1995                         napi_schedule(&tp->napi);
1996                 }
1997         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1998                 netif_stop_queue(netdev);
1999         }
2000
2001         return NETDEV_TX_OK;
2002 }
2003
2004 static void r8152b_reset_packet_filter(struct r8152 *tp)
2005 {
2006         u32     ocp_data;
2007
2008         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2009         ocp_data &= ~FMC_FCR_MCU_EN;
2010         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2011         ocp_data |= FMC_FCR_MCU_EN;
2012         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2013 }
2014
2015 static void rtl8152_nic_reset(struct r8152 *tp)
2016 {
2017         int     i;
2018
2019         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2020
2021         for (i = 0; i < 1000; i++) {
2022                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2023                         break;
2024                 usleep_range(100, 400);
2025         }
2026 }
2027
2028 static void set_tx_qlen(struct r8152 *tp)
2029 {
2030         struct net_device *netdev = tp->netdev;
2031
2032         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2033                                     sizeof(struct tx_desc));
2034 }
2035
2036 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2037 {
2038         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2039 }
2040
2041 static void rtl_set_eee_plus(struct r8152 *tp)
2042 {
2043         u32 ocp_data;
2044         u8 speed;
2045
2046         speed = rtl8152_get_speed(tp);
2047         if (speed & _10bps) {
2048                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2049                 ocp_data |= EEEP_CR_EEEP_TX;
2050                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2051         } else {
2052                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2053                 ocp_data &= ~EEEP_CR_EEEP_TX;
2054                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2055         }
2056 }
2057
2058 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2059 {
2060         u32 ocp_data;
2061
2062         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2063         if (enable)
2064                 ocp_data |= RXDY_GATED_EN;
2065         else
2066                 ocp_data &= ~RXDY_GATED_EN;
2067         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2068 }
2069
2070 static int rtl_start_rx(struct r8152 *tp)
2071 {
2072         int i, ret = 0;
2073
2074         napi_disable(&tp->napi);
2075         INIT_LIST_HEAD(&tp->rx_done);
2076         for (i = 0; i < RTL8152_MAX_RX; i++) {
2077                 INIT_LIST_HEAD(&tp->rx_info[i].list);
2078                 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2079                 if (ret)
2080                         break;
2081         }
2082         napi_enable(&tp->napi);
2083
2084         if (ret && ++i < RTL8152_MAX_RX) {
2085                 struct list_head rx_queue;
2086                 unsigned long flags;
2087
2088                 INIT_LIST_HEAD(&rx_queue);
2089
2090                 do {
2091                         struct rx_agg *agg = &tp->rx_info[i++];
2092                         struct urb *urb = agg->urb;
2093
2094                         urb->actual_length = 0;
2095                         list_add_tail(&agg->list, &rx_queue);
2096                 } while (i < RTL8152_MAX_RX);
2097
2098                 spin_lock_irqsave(&tp->rx_lock, flags);
2099                 list_splice_tail(&rx_queue, &tp->rx_done);
2100                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2101         }
2102
2103         return ret;
2104 }
2105
2106 static int rtl_stop_rx(struct r8152 *tp)
2107 {
2108         int i;
2109
2110         for (i = 0; i < RTL8152_MAX_RX; i++)
2111                 usb_kill_urb(tp->rx_info[i].urb);
2112
2113         while (!skb_queue_empty(&tp->rx_queue))
2114                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2115
2116         return 0;
2117 }
2118
2119 static int rtl_enable(struct r8152 *tp)
2120 {
2121         u32 ocp_data;
2122
2123         r8152b_reset_packet_filter(tp);
2124
2125         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2126         ocp_data |= CR_RE | CR_TE;
2127         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2128
2129         rxdy_gated_en(tp, false);
2130
2131         return 0;
2132 }
2133
2134 static int rtl8152_enable(struct r8152 *tp)
2135 {
2136         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2137                 return -ENODEV;
2138
2139         set_tx_qlen(tp);
2140         rtl_set_eee_plus(tp);
2141
2142         return rtl_enable(tp);
2143 }
2144
2145 static void r8153_set_rx_agg(struct r8152 *tp)
2146 {
2147         u8 speed;
2148
2149         speed = rtl8152_get_speed(tp);
2150         if (speed & _1000bps) {
2151                 if (tp->udev->speed == USB_SPEED_SUPER) {
2152                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2153                                         RX_THR_SUPPER);
2154                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2155                                         EARLY_AGG_SUPPER);
2156                 } else {
2157                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2158                                         RX_THR_HIGH);
2159                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2160                                         EARLY_AGG_HIGH);
2161                 }
2162         } else {
2163                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2164                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2165                                 EARLY_AGG_SLOW);
2166         }
2167 }
2168
2169 static int rtl8153_enable(struct r8152 *tp)
2170 {
2171         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2172                 return -ENODEV;
2173
2174         set_tx_qlen(tp);
2175         rtl_set_eee_plus(tp);
2176         r8153_set_rx_agg(tp);
2177
2178         return rtl_enable(tp);
2179 }
2180
2181 static void rtl_disable(struct r8152 *tp)
2182 {
2183         u32 ocp_data;
2184         int i;
2185
2186         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2187                 rtl_drop_queued_tx(tp);
2188                 return;
2189         }
2190
2191         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2192         ocp_data &= ~RCR_ACPT_ALL;
2193         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2194
2195         rtl_drop_queued_tx(tp);
2196
2197         for (i = 0; i < RTL8152_MAX_TX; i++)
2198                 usb_kill_urb(tp->tx_info[i].urb);
2199
2200         rxdy_gated_en(tp, true);
2201
2202         for (i = 0; i < 1000; i++) {
2203                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2204                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2205                         break;
2206                 usleep_range(1000, 2000);
2207         }
2208
2209         for (i = 0; i < 1000; i++) {
2210                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2211                         break;
2212                 usleep_range(1000, 2000);
2213         }
2214
2215         rtl_stop_rx(tp);
2216
2217         rtl8152_nic_reset(tp);
2218 }
2219
2220 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2221 {
2222         u32 ocp_data;
2223
2224         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2225         if (enable)
2226                 ocp_data |= POWER_CUT;
2227         else
2228                 ocp_data &= ~POWER_CUT;
2229         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2230
2231         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2232         ocp_data &= ~RESUME_INDICATE;
2233         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2234 }
2235
2236 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2237 {
2238         u32 ocp_data;
2239
2240         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2241         if (enable)
2242                 ocp_data |= CPCR_RX_VLAN;
2243         else
2244                 ocp_data &= ~CPCR_RX_VLAN;
2245         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2246 }
2247
2248 static int rtl8152_set_features(struct net_device *dev,
2249                                 netdev_features_t features)
2250 {
2251         netdev_features_t changed = features ^ dev->features;
2252         struct r8152 *tp = netdev_priv(dev);
2253         int ret;
2254
2255         ret = usb_autopm_get_interface(tp->intf);
2256         if (ret < 0)
2257                 goto out;
2258
2259         mutex_lock(&tp->control);
2260
2261         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2262                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2263                         rtl_rx_vlan_en(tp, true);
2264                 else
2265                         rtl_rx_vlan_en(tp, false);
2266         }
2267
2268         mutex_unlock(&tp->control);
2269
2270         usb_autopm_put_interface(tp->intf);
2271
2272 out:
2273         return ret;
2274 }
2275
2276 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2277
2278 static u32 __rtl_get_wol(struct r8152 *tp)
2279 {
2280         u32 ocp_data;
2281         u32 wolopts = 0;
2282
2283         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2284         if (!(ocp_data & LAN_WAKE_EN))
2285                 return 0;
2286
2287         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2288         if (ocp_data & LINK_ON_WAKE_EN)
2289                 wolopts |= WAKE_PHY;
2290
2291         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2292         if (ocp_data & UWF_EN)
2293                 wolopts |= WAKE_UCAST;
2294         if (ocp_data & BWF_EN)
2295                 wolopts |= WAKE_BCAST;
2296         if (ocp_data & MWF_EN)
2297                 wolopts |= WAKE_MCAST;
2298
2299         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2300         if (ocp_data & MAGIC_EN)
2301                 wolopts |= WAKE_MAGIC;
2302
2303         return wolopts;
2304 }
2305
2306 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2307 {
2308         u32 ocp_data;
2309
2310         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2311
2312         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2313         ocp_data &= ~LINK_ON_WAKE_EN;
2314         if (wolopts & WAKE_PHY)
2315                 ocp_data |= LINK_ON_WAKE_EN;
2316         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2317
2318         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2319         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2320         if (wolopts & WAKE_UCAST)
2321                 ocp_data |= UWF_EN;
2322         if (wolopts & WAKE_BCAST)
2323                 ocp_data |= BWF_EN;
2324         if (wolopts & WAKE_MCAST)
2325                 ocp_data |= MWF_EN;
2326         if (wolopts & WAKE_ANY)
2327                 ocp_data |= LAN_WAKE_EN;
2328         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2329
2330         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2331
2332         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2333         ocp_data &= ~MAGIC_EN;
2334         if (wolopts & WAKE_MAGIC)
2335                 ocp_data |= MAGIC_EN;
2336         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2337
2338         if (wolopts & WAKE_ANY)
2339                 device_set_wakeup_enable(&tp->udev->dev, true);
2340         else
2341                 device_set_wakeup_enable(&tp->udev->dev, false);
2342 }
2343
2344 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2345 {
2346         if (enable) {
2347                 u32 ocp_data;
2348
2349                 __rtl_set_wol(tp, WAKE_ANY);
2350
2351                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2352
2353                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2354                 ocp_data |= LINK_OFF_WAKE_EN;
2355                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2356
2357                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2358         } else {
2359                 __rtl_set_wol(tp, tp->saved_wolopts);
2360         }
2361 }
2362
2363 static void rtl_phy_reset(struct r8152 *tp)
2364 {
2365         u16 data;
2366         int i;
2367
2368         clear_bit(PHY_RESET, &tp->flags);
2369
2370         data = r8152_mdio_read(tp, MII_BMCR);
2371
2372         /* don't reset again before the previous one complete */
2373         if (data & BMCR_RESET)
2374                 return;
2375
2376         data |= BMCR_RESET;
2377         r8152_mdio_write(tp, MII_BMCR, data);
2378
2379         for (i = 0; i < 50; i++) {
2380                 msleep(20);
2381                 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2382                         break;
2383         }
2384 }
2385
2386 static void r8153_teredo_off(struct r8152 *tp)
2387 {
2388         u32 ocp_data;
2389
2390         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2391         ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2392         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2393
2394         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2395         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2396         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2397 }
2398
2399 static void r8152b_disable_aldps(struct r8152 *tp)
2400 {
2401         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2402         msleep(20);
2403 }
2404
2405 static inline void r8152b_enable_aldps(struct r8152 *tp)
2406 {
2407         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2408                                             LINKENA | DIS_SDSAVE);
2409 }
2410
2411 static void rtl8152_disable(struct r8152 *tp)
2412 {
2413         r8152b_disable_aldps(tp);
2414         rtl_disable(tp);
2415         r8152b_enable_aldps(tp);
2416 }
2417
2418 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2419 {
2420         u16 data;
2421
2422         data = r8152_mdio_read(tp, MII_BMCR);
2423         if (data & BMCR_PDOWN) {
2424                 data &= ~BMCR_PDOWN;
2425                 r8152_mdio_write(tp, MII_BMCR, data);
2426         }
2427
2428         set_bit(PHY_RESET, &tp->flags);
2429 }
2430
2431 static void r8152b_exit_oob(struct r8152 *tp)
2432 {
2433         u32 ocp_data;
2434         int i;
2435
2436         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2437         ocp_data &= ~RCR_ACPT_ALL;
2438         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2439
2440         rxdy_gated_en(tp, true);
2441         r8153_teredo_off(tp);
2442         r8152b_hw_phy_cfg(tp);
2443
2444         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2445         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2446
2447         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2448         ocp_data &= ~NOW_IS_OOB;
2449         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2450
2451         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2452         ocp_data &= ~MCU_BORW_EN;
2453         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2454
2455         for (i = 0; i < 1000; i++) {
2456                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2457                 if (ocp_data & LINK_LIST_READY)
2458                         break;
2459                 usleep_range(1000, 2000);
2460         }
2461
2462         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2463         ocp_data |= RE_INIT_LL;
2464         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2465
2466         for (i = 0; i < 1000; i++) {
2467                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2468                 if (ocp_data & LINK_LIST_READY)
2469                         break;
2470                 usleep_range(1000, 2000);
2471         }
2472
2473         rtl8152_nic_reset(tp);
2474
2475         /* rx share fifo credit full threshold */
2476         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2477
2478         if (tp->udev->speed == USB_SPEED_FULL ||
2479             tp->udev->speed == USB_SPEED_LOW) {
2480                 /* rx share fifo credit near full threshold */
2481                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2482                                 RXFIFO_THR2_FULL);
2483                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2484                                 RXFIFO_THR3_FULL);
2485         } else {
2486                 /* rx share fifo credit near full threshold */
2487                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2488                                 RXFIFO_THR2_HIGH);
2489                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2490                                 RXFIFO_THR3_HIGH);
2491         }
2492
2493         /* TX share fifo free credit full threshold */
2494         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2495
2496         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2497         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2498         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2499                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2500
2501         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2502
2503         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2504
2505         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2506         ocp_data |= TCR0_AUTO_FIFO;
2507         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2508 }
2509
2510 static void r8152b_enter_oob(struct r8152 *tp)
2511 {
2512         u32 ocp_data;
2513         int i;
2514
2515         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2516         ocp_data &= ~NOW_IS_OOB;
2517         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2518
2519         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2520         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2521         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2522
2523         rtl_disable(tp);
2524
2525         for (i = 0; i < 1000; i++) {
2526                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2527                 if (ocp_data & LINK_LIST_READY)
2528                         break;
2529                 usleep_range(1000, 2000);
2530         }
2531
2532         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2533         ocp_data |= RE_INIT_LL;
2534         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2535
2536         for (i = 0; i < 1000; i++) {
2537                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2538                 if (ocp_data & LINK_LIST_READY)
2539                         break;
2540                 usleep_range(1000, 2000);
2541         }
2542
2543         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2544
2545         rtl_rx_vlan_en(tp, true);
2546
2547         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2548         ocp_data |= ALDPS_PROXY_MODE;
2549         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2550
2551         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2552         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2553         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2554
2555         rxdy_gated_en(tp, false);
2556
2557         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2558         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2559         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2560 }
2561
2562 static void r8153_hw_phy_cfg(struct r8152 *tp)
2563 {
2564         u32 ocp_data;
2565         u16 data;
2566
2567         ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2568         data = r8152_mdio_read(tp, MII_BMCR);
2569         if (data & BMCR_PDOWN) {
2570                 data &= ~BMCR_PDOWN;
2571                 r8152_mdio_write(tp, MII_BMCR, data);
2572         }
2573
2574         if (tp->version == RTL_VER_03) {
2575                 data = ocp_reg_read(tp, OCP_EEE_CFG);
2576                 data &= ~CTAP_SHORT_EN;
2577                 ocp_reg_write(tp, OCP_EEE_CFG, data);
2578         }
2579
2580         data = ocp_reg_read(tp, OCP_POWER_CFG);
2581         data |= EEE_CLKDIV_EN;
2582         ocp_reg_write(tp, OCP_POWER_CFG, data);
2583
2584         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2585         data |= EN_10M_BGOFF;
2586         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2587         data = ocp_reg_read(tp, OCP_POWER_CFG);
2588         data |= EN_10M_PLLOFF;
2589         ocp_reg_write(tp, OCP_POWER_CFG, data);
2590         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
2591
2592         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2593         ocp_data |= PFM_PWM_SWITCH;
2594         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2595
2596         /* Enable LPF corner auto tune */
2597         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
2598
2599         /* Adjust 10M Amplitude */
2600         sram_write(tp, SRAM_10M_AMP1, 0x00af);
2601         sram_write(tp, SRAM_10M_AMP2, 0x0208);
2602
2603         set_bit(PHY_RESET, &tp->flags);
2604 }
2605
2606 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2607 {
2608         u8 u1u2[8];
2609
2610         if (enable)
2611                 memset(u1u2, 0xff, sizeof(u1u2));
2612         else
2613                 memset(u1u2, 0x00, sizeof(u1u2));
2614
2615         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2616 }
2617
2618 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2619 {
2620         u32 ocp_data;
2621
2622         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2623         if (enable)
2624                 ocp_data |= U2P3_ENABLE;
2625         else
2626                 ocp_data &= ~U2P3_ENABLE;
2627         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2628 }
2629
2630 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2631 {
2632         u32 ocp_data;
2633
2634         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2635         if (enable)
2636                 ocp_data |= PWR_EN | PHASE2_EN;
2637         else
2638                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2639         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2640
2641         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2642         ocp_data &= ~PCUT_STATUS;
2643         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2644 }
2645
2646 static void r8153_first_init(struct r8152 *tp)
2647 {
2648         u32 ocp_data;
2649         int i;
2650
2651         rxdy_gated_en(tp, true);
2652         r8153_teredo_off(tp);
2653
2654         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2655         ocp_data &= ~RCR_ACPT_ALL;
2656         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2657
2658         r8153_hw_phy_cfg(tp);
2659
2660         rtl8152_nic_reset(tp);
2661
2662         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2663         ocp_data &= ~NOW_IS_OOB;
2664         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2665
2666         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2667         ocp_data &= ~MCU_BORW_EN;
2668         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2669
2670         for (i = 0; i < 1000; i++) {
2671                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2672                 if (ocp_data & LINK_LIST_READY)
2673                         break;
2674                 usleep_range(1000, 2000);
2675         }
2676
2677         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2678         ocp_data |= RE_INIT_LL;
2679         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2680
2681         for (i = 0; i < 1000; i++) {
2682                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2683                 if (ocp_data & LINK_LIST_READY)
2684                         break;
2685                 usleep_range(1000, 2000);
2686         }
2687
2688         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2689
2690         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2691         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2692
2693         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2694         ocp_data |= TCR0_AUTO_FIFO;
2695         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2696
2697         rtl8152_nic_reset(tp);
2698
2699         /* rx share fifo credit full threshold */
2700         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2701         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2702         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2703         /* TX share fifo free credit full threshold */
2704         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2705
2706         /* rx aggregation */
2707         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2708         ocp_data &= ~RX_AGG_DISABLE;
2709         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2710 }
2711
2712 static void r8153_enter_oob(struct r8152 *tp)
2713 {
2714         u32 ocp_data;
2715         int i;
2716
2717         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2718         ocp_data &= ~NOW_IS_OOB;
2719         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2720
2721         rtl_disable(tp);
2722
2723         for (i = 0; i < 1000; i++) {
2724                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2725                 if (ocp_data & LINK_LIST_READY)
2726                         break;
2727                 usleep_range(1000, 2000);
2728         }
2729
2730         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2731         ocp_data |= RE_INIT_LL;
2732         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2733
2734         for (i = 0; i < 1000; i++) {
2735                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2736                 if (ocp_data & LINK_LIST_READY)
2737                         break;
2738                 usleep_range(1000, 2000);
2739         }
2740
2741         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2742
2743         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2744         ocp_data &= ~TEREDO_WAKE_MASK;
2745         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2746
2747         rtl_rx_vlan_en(tp, true);
2748
2749         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2750         ocp_data |= ALDPS_PROXY_MODE;
2751         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2752
2753         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2754         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2755         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2756
2757         rxdy_gated_en(tp, false);
2758
2759         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2760         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2761         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2762 }
2763
2764 static void r8153_disable_aldps(struct r8152 *tp)
2765 {
2766         u16 data;
2767
2768         data = ocp_reg_read(tp, OCP_POWER_CFG);
2769         data &= ~EN_ALDPS;
2770         ocp_reg_write(tp, OCP_POWER_CFG, data);
2771         msleep(20);
2772 }
2773
2774 static void r8153_enable_aldps(struct r8152 *tp)
2775 {
2776         u16 data;
2777
2778         data = ocp_reg_read(tp, OCP_POWER_CFG);
2779         data |= EN_ALDPS;
2780         ocp_reg_write(tp, OCP_POWER_CFG, data);
2781 }
2782
2783 static void rtl8153_disable(struct r8152 *tp)
2784 {
2785         r8153_disable_aldps(tp);
2786         rtl_disable(tp);
2787         r8153_enable_aldps(tp);
2788 }
2789
2790 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2791 {
2792         u16 bmcr, anar, gbcr;
2793         int ret = 0;
2794
2795         cancel_delayed_work_sync(&tp->schedule);
2796         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2797         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2798                   ADVERTISE_100HALF | ADVERTISE_100FULL);
2799         if (tp->mii.supports_gmii) {
2800                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2801                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2802         } else {
2803                 gbcr = 0;
2804         }
2805
2806         if (autoneg == AUTONEG_DISABLE) {
2807                 if (speed == SPEED_10) {
2808                         bmcr = 0;
2809                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2810                 } else if (speed == SPEED_100) {
2811                         bmcr = BMCR_SPEED100;
2812                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2813                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2814                         bmcr = BMCR_SPEED1000;
2815                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2816                 } else {
2817                         ret = -EINVAL;
2818                         goto out;
2819                 }
2820
2821                 if (duplex == DUPLEX_FULL)
2822                         bmcr |= BMCR_FULLDPLX;
2823         } else {
2824                 if (speed == SPEED_10) {
2825                         if (duplex == DUPLEX_FULL)
2826                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2827                         else
2828                                 anar |= ADVERTISE_10HALF;
2829                 } else if (speed == SPEED_100) {
2830                         if (duplex == DUPLEX_FULL) {
2831                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2832                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2833                         } else {
2834                                 anar |= ADVERTISE_10HALF;
2835                                 anar |= ADVERTISE_100HALF;
2836                         }
2837                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2838                         if (duplex == DUPLEX_FULL) {
2839                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2840                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2841                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2842                         } else {
2843                                 anar |= ADVERTISE_10HALF;
2844                                 anar |= ADVERTISE_100HALF;
2845                                 gbcr |= ADVERTISE_1000HALF;
2846                         }
2847                 } else {
2848                         ret = -EINVAL;
2849                         goto out;
2850                 }
2851
2852                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2853         }
2854
2855         if (test_bit(PHY_RESET, &tp->flags))
2856                 bmcr |= BMCR_RESET;
2857
2858         if (tp->mii.supports_gmii)
2859                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2860
2861         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2862         r8152_mdio_write(tp, MII_BMCR, bmcr);
2863
2864         if (test_bit(PHY_RESET, &tp->flags)) {
2865                 int i;
2866
2867                 clear_bit(PHY_RESET, &tp->flags);
2868                 for (i = 0; i < 50; i++) {
2869                         msleep(20);
2870                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2871                                 break;
2872                 }
2873         }
2874
2875 out:
2876
2877         return ret;
2878 }
2879
2880 static void rtl8152_up(struct r8152 *tp)
2881 {
2882         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2883                 return;
2884
2885         r8152b_disable_aldps(tp);
2886         r8152b_exit_oob(tp);
2887         r8152b_enable_aldps(tp);
2888 }
2889
2890 static void rtl8152_down(struct r8152 *tp)
2891 {
2892         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2893                 rtl_drop_queued_tx(tp);
2894                 return;
2895         }
2896
2897         r8152_power_cut_en(tp, false);
2898         r8152b_disable_aldps(tp);
2899         r8152b_enter_oob(tp);
2900         r8152b_enable_aldps(tp);
2901 }
2902
2903 static void rtl8153_up(struct r8152 *tp)
2904 {
2905         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2906                 return;
2907
2908         r8153_disable_aldps(tp);
2909         r8153_first_init(tp);
2910         r8153_enable_aldps(tp);
2911 }
2912
2913 static void rtl8153_down(struct r8152 *tp)
2914 {
2915         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2916                 rtl_drop_queued_tx(tp);
2917                 return;
2918         }
2919
2920         r8153_u1u2en(tp, false);
2921         r8153_power_cut_en(tp, false);
2922         r8153_disable_aldps(tp);
2923         r8153_enter_oob(tp);
2924         r8153_enable_aldps(tp);
2925 }
2926
2927 static void set_carrier(struct r8152 *tp)
2928 {
2929         struct net_device *netdev = tp->netdev;
2930         u8 speed;
2931
2932         clear_bit(RTL8152_LINK_CHG, &tp->flags);
2933         speed = rtl8152_get_speed(tp);
2934
2935         if (speed & LINK_STATUS) {
2936                 if (!netif_carrier_ok(netdev)) {
2937                         tp->rtl_ops.enable(tp);
2938                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2939                         netif_carrier_on(netdev);
2940                         rtl_start_rx(tp);
2941                 }
2942         } else {
2943                 if (netif_carrier_ok(netdev)) {
2944                         netif_carrier_off(netdev);
2945                         napi_disable(&tp->napi);
2946                         tp->rtl_ops.disable(tp);
2947                         napi_enable(&tp->napi);
2948                 }
2949         }
2950 }
2951
2952 static void rtl_work_func_t(struct work_struct *work)
2953 {
2954         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2955
2956         /* If the device is unplugged or !netif_running(), the workqueue
2957          * doesn't need to wake the device, and could return directly.
2958          */
2959         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2960                 return;
2961
2962         if (usb_autopm_get_interface(tp->intf) < 0)
2963                 return;
2964
2965         if (!test_bit(WORK_ENABLE, &tp->flags))
2966                 goto out1;
2967
2968         if (!mutex_trylock(&tp->control)) {
2969                 schedule_delayed_work(&tp->schedule, 0);
2970                 goto out1;
2971         }
2972
2973         if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2974                 set_carrier(tp);
2975
2976         if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2977                 _rtl8152_set_rx_mode(tp->netdev);
2978
2979         /* don't schedule napi before linking */
2980         if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
2981             netif_carrier_ok(tp->netdev)) {
2982                 clear_bit(SCHEDULE_NAPI, &tp->flags);
2983                 napi_schedule(&tp->napi);
2984         }
2985
2986         if (test_bit(PHY_RESET, &tp->flags))
2987                 rtl_phy_reset(tp);
2988
2989         mutex_unlock(&tp->control);
2990
2991 out1:
2992         usb_autopm_put_interface(tp->intf);
2993 }
2994
2995 static int rtl8152_open(struct net_device *netdev)
2996 {
2997         struct r8152 *tp = netdev_priv(netdev);
2998         int res = 0;
2999
3000         res = alloc_all_mem(tp);
3001         if (res)
3002                 goto out;
3003
3004         netif_carrier_off(netdev);
3005
3006         res = usb_autopm_get_interface(tp->intf);
3007         if (res < 0) {
3008                 free_all_mem(tp);
3009                 goto out;
3010         }
3011
3012         mutex_lock(&tp->control);
3013
3014         /* The WORK_ENABLE may be set when autoresume occurs */
3015         if (test_bit(WORK_ENABLE, &tp->flags)) {
3016                 clear_bit(WORK_ENABLE, &tp->flags);
3017                 usb_kill_urb(tp->intr_urb);
3018                 cancel_delayed_work_sync(&tp->schedule);
3019
3020                 /* disable the tx/rx, if the workqueue has enabled them. */
3021                 if (netif_carrier_ok(netdev))
3022                         tp->rtl_ops.disable(tp);
3023         }
3024
3025         tp->rtl_ops.up(tp);
3026
3027         rtl8152_set_speed(tp, AUTONEG_ENABLE,
3028                           tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3029                           DUPLEX_FULL);
3030         netif_carrier_off(netdev);
3031         netif_start_queue(netdev);
3032         set_bit(WORK_ENABLE, &tp->flags);
3033
3034         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3035         if (res) {
3036                 if (res == -ENODEV)
3037                         netif_device_detach(tp->netdev);
3038                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3039                            res);
3040                 free_all_mem(tp);
3041         } else {
3042                 napi_enable(&tp->napi);
3043         }
3044
3045         mutex_unlock(&tp->control);
3046
3047         usb_autopm_put_interface(tp->intf);
3048
3049 out:
3050         return res;
3051 }
3052
3053 static int rtl8152_close(struct net_device *netdev)
3054 {
3055         struct r8152 *tp = netdev_priv(netdev);
3056         int res = 0;
3057
3058         napi_disable(&tp->napi);
3059         clear_bit(WORK_ENABLE, &tp->flags);
3060         usb_kill_urb(tp->intr_urb);
3061         cancel_delayed_work_sync(&tp->schedule);
3062         netif_stop_queue(netdev);
3063
3064         res = usb_autopm_get_interface(tp->intf);
3065         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3066                 rtl_drop_queued_tx(tp);
3067                 rtl_stop_rx(tp);
3068         } else {
3069                 mutex_lock(&tp->control);
3070
3071                 /* The autosuspend may have been enabled and wouldn't
3072                  * be disable when autoresume occurs, because the
3073                  * netif_running() would be false.
3074                  */
3075                 rtl_runtime_suspend_enable(tp, false);
3076
3077                 tp->rtl_ops.down(tp);
3078
3079                 mutex_unlock(&tp->control);
3080
3081                 usb_autopm_put_interface(tp->intf);
3082         }
3083
3084         free_all_mem(tp);
3085
3086         return res;
3087 }
3088
3089 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3090 {
3091         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3092         ocp_reg_write(tp, OCP_EEE_DATA, reg);
3093         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3094 }
3095
3096 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3097 {
3098         u16 data;
3099
3100         r8152_mmd_indirect(tp, dev, reg);
3101         data = ocp_reg_read(tp, OCP_EEE_DATA);
3102         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3103
3104         return data;
3105 }
3106
3107 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3108 {
3109         r8152_mmd_indirect(tp, dev, reg);
3110         ocp_reg_write(tp, OCP_EEE_DATA, data);
3111         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3112 }
3113
3114 static void r8152_eee_en(struct r8152 *tp, bool enable)
3115 {
3116         u16 config1, config2, config3;
3117         u32 ocp_data;
3118
3119         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3120         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3121         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3122         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3123
3124         if (enable) {
3125                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3126                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3127                 config1 |= sd_rise_time(1);
3128                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3129                 config3 |= fast_snr(42);
3130         } else {
3131                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3132                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3133                              RX_QUIET_EN);
3134                 config1 |= sd_rise_time(7);
3135                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3136                 config3 |= fast_snr(511);
3137         }
3138
3139         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3140         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3141         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3142         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3143 }
3144
3145 static void r8152b_enable_eee(struct r8152 *tp)
3146 {
3147         r8152_eee_en(tp, true);
3148         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3149 }
3150
3151 static void r8153_eee_en(struct r8152 *tp, bool enable)
3152 {
3153         u32 ocp_data;
3154         u16 config;
3155
3156         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3157         config = ocp_reg_read(tp, OCP_EEE_CFG);
3158
3159         if (enable) {
3160                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3161                 config |= EEE10_EN;
3162         } else {
3163                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3164                 config &= ~EEE10_EN;
3165         }
3166
3167         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3168         ocp_reg_write(tp, OCP_EEE_CFG, config);
3169 }
3170
3171 static void r8153_enable_eee(struct r8152 *tp)
3172 {
3173         r8153_eee_en(tp, true);
3174         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3175 }
3176
3177 static void r8152b_enable_fc(struct r8152 *tp)
3178 {
3179         u16 anar;
3180
3181         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3182         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3183         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3184 }
3185
3186 static void rtl_tally_reset(struct r8152 *tp)
3187 {
3188         u32 ocp_data;
3189
3190         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3191         ocp_data |= TALLY_RESET;
3192         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3193 }
3194
3195 static void r8152b_init(struct r8152 *tp)
3196 {
3197         u32 ocp_data;
3198
3199         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3200                 return;
3201
3202         r8152b_disable_aldps(tp);
3203
3204         if (tp->version == RTL_VER_01) {
3205                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3206                 ocp_data &= ~LED_MODE_MASK;
3207                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3208         }
3209
3210         r8152_power_cut_en(tp, false);
3211
3212         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3213         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3214         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3215         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3216         ocp_data &= ~MCU_CLK_RATIO_MASK;
3217         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3218         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3219         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3220                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3221         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3222
3223         r8152b_enable_eee(tp);
3224         r8152b_enable_aldps(tp);
3225         r8152b_enable_fc(tp);
3226         rtl_tally_reset(tp);
3227
3228         /* enable rx aggregation */
3229         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3230         ocp_data &= ~RX_AGG_DISABLE;
3231         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3232 }
3233
3234 static void r8153_init(struct r8152 *tp)
3235 {
3236         u32 ocp_data;
3237         int i;
3238
3239         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3240                 return;
3241
3242         r8153_disable_aldps(tp);
3243         r8153_u1u2en(tp, false);
3244
3245         for (i = 0; i < 500; i++) {
3246                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3247                     AUTOLOAD_DONE)
3248                         break;
3249                 msleep(20);
3250         }
3251
3252         for (i = 0; i < 500; i++) {
3253                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3254                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3255                         break;
3256                 msleep(20);
3257         }
3258
3259         r8153_u2p3en(tp, false);
3260
3261         if (tp->version == RTL_VER_04) {
3262                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3263                 ocp_data &= ~pwd_dn_scale_mask;
3264                 ocp_data |= pwd_dn_scale(96);
3265                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3266
3267                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3268                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3269                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3270         } else if (tp->version == RTL_VER_05) {
3271                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3272                 ocp_data &= ~ECM_ALDPS;
3273                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3274
3275                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3276                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3277                         ocp_data &= ~DYNAMIC_BURST;
3278                 else
3279                         ocp_data |= DYNAMIC_BURST;
3280                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3281         }
3282
3283         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3284         ocp_data |= EP4_FULL_FC;
3285         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3286
3287         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3288         ocp_data &= ~TIMER11_EN;
3289         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3290
3291         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3292         ocp_data &= ~LED_MODE_MASK;
3293         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3294
3295         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
3296         if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
3297                 ocp_data |= LPM_TIMER_500MS;
3298         else
3299                 ocp_data |= LPM_TIMER_500US;
3300         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3301
3302         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3303         ocp_data &= ~SEN_VAL_MASK;
3304         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3305         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3306
3307         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3308
3309         r8153_power_cut_en(tp, false);
3310         r8153_u1u2en(tp, true);
3311
3312         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3313         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3314         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3315                        PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3316                        U1U2_SPDWN_EN | L1_SPDWN_EN);
3317         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3318                        PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3319                        TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3320                        EEE_SPDWN_EN);
3321
3322         r8153_enable_eee(tp);
3323         r8153_enable_aldps(tp);
3324         r8152b_enable_fc(tp);
3325         rtl_tally_reset(tp);
3326 }
3327
3328 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3329 {
3330         struct r8152 *tp = usb_get_intfdata(intf);
3331         struct net_device *netdev = tp->netdev;
3332         int ret = 0;
3333
3334         mutex_lock(&tp->control);
3335
3336         if (PMSG_IS_AUTO(message)) {
3337                 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3338                         ret = -EBUSY;
3339                         goto out1;
3340                 }
3341
3342                 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3343         } else {
3344                 netif_device_detach(netdev);
3345         }
3346
3347         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3348                 clear_bit(WORK_ENABLE, &tp->flags);
3349                 usb_kill_urb(tp->intr_urb);
3350                 napi_disable(&tp->napi);
3351                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3352                         rtl_stop_rx(tp);
3353                         rtl_runtime_suspend_enable(tp, true);
3354                 } else {
3355                         cancel_delayed_work_sync(&tp->schedule);
3356                         tp->rtl_ops.down(tp);
3357                 }
3358                 napi_enable(&tp->napi);
3359         }
3360 out1:
3361         mutex_unlock(&tp->control);
3362
3363         return ret;
3364 }
3365
3366 static int rtl8152_resume(struct usb_interface *intf)
3367 {
3368         struct r8152 *tp = usb_get_intfdata(intf);
3369
3370         mutex_lock(&tp->control);
3371
3372         if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3373                 tp->rtl_ops.init(tp);
3374                 netif_device_attach(tp->netdev);
3375         }
3376
3377         if (netif_running(tp->netdev)) {
3378                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3379                         rtl_runtime_suspend_enable(tp, false);
3380                         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3381                         set_bit(WORK_ENABLE, &tp->flags);
3382                         if (netif_carrier_ok(tp->netdev))
3383                                 rtl_start_rx(tp);
3384                 } else {
3385                         tp->rtl_ops.up(tp);
3386                         rtl8152_set_speed(tp, AUTONEG_ENABLE,
3387                                           tp->mii.supports_gmii ?
3388                                           SPEED_1000 : SPEED_100,
3389                                           DUPLEX_FULL);
3390                         netif_carrier_off(tp->netdev);
3391                         set_bit(WORK_ENABLE, &tp->flags);
3392                 }
3393                 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3394         } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3395                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3396         }
3397
3398         mutex_unlock(&tp->control);
3399
3400         return 0;
3401 }
3402
3403 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3404 {
3405         struct r8152 *tp = netdev_priv(dev);
3406
3407         if (usb_autopm_get_interface(tp->intf) < 0)
3408                 return;
3409
3410         mutex_lock(&tp->control);
3411
3412         wol->supported = WAKE_ANY;
3413         wol->wolopts = __rtl_get_wol(tp);
3414
3415         mutex_unlock(&tp->control);
3416
3417         usb_autopm_put_interface(tp->intf);
3418 }
3419
3420 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3421 {
3422         struct r8152 *tp = netdev_priv(dev);
3423         int ret;
3424
3425         ret = usb_autopm_get_interface(tp->intf);
3426         if (ret < 0)
3427                 goto out_set_wol;
3428
3429         mutex_lock(&tp->control);
3430
3431         __rtl_set_wol(tp, wol->wolopts);
3432         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3433
3434         mutex_unlock(&tp->control);
3435
3436         usb_autopm_put_interface(tp->intf);
3437
3438 out_set_wol:
3439         return ret;
3440 }
3441
3442 static u32 rtl8152_get_msglevel(struct net_device *dev)
3443 {
3444         struct r8152 *tp = netdev_priv(dev);
3445
3446         return tp->msg_enable;
3447 }
3448
3449 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3450 {
3451         struct r8152 *tp = netdev_priv(dev);
3452
3453         tp->msg_enable = value;
3454 }
3455
3456 static void rtl8152_get_drvinfo(struct net_device *netdev,
3457                                 struct ethtool_drvinfo *info)
3458 {
3459         struct r8152 *tp = netdev_priv(netdev);
3460
3461         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3462         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3463         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3464 }
3465
3466 static
3467 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3468 {
3469         struct r8152 *tp = netdev_priv(netdev);
3470         int ret;
3471
3472         if (!tp->mii.mdio_read)
3473                 return -EOPNOTSUPP;
3474
3475         ret = usb_autopm_get_interface(tp->intf);
3476         if (ret < 0)
3477                 goto out;
3478
3479         mutex_lock(&tp->control);
3480
3481         ret = mii_ethtool_gset(&tp->mii, cmd);
3482
3483         mutex_unlock(&tp->control);
3484
3485         usb_autopm_put_interface(tp->intf);
3486
3487 out:
3488         return ret;
3489 }
3490
3491 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3492 {
3493         struct r8152 *tp = netdev_priv(dev);
3494         int ret;
3495
3496         ret = usb_autopm_get_interface(tp->intf);
3497         if (ret < 0)
3498                 goto out;
3499
3500         mutex_lock(&tp->control);
3501
3502         ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3503
3504         mutex_unlock(&tp->control);
3505
3506         usb_autopm_put_interface(tp->intf);
3507
3508 out:
3509         return ret;
3510 }
3511
3512 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3513         "tx_packets",
3514         "rx_packets",
3515         "tx_errors",
3516         "rx_errors",
3517         "rx_missed",
3518         "align_errors",
3519         "tx_single_collisions",
3520         "tx_multi_collisions",
3521         "rx_unicast",
3522         "rx_broadcast",
3523         "rx_multicast",
3524         "tx_aborted",
3525         "tx_underrun",
3526 };
3527
3528 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3529 {
3530         switch (sset) {
3531         case ETH_SS_STATS:
3532                 return ARRAY_SIZE(rtl8152_gstrings);
3533         default:
3534                 return -EOPNOTSUPP;
3535         }
3536 }
3537
3538 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3539                                       struct ethtool_stats *stats, u64 *data)
3540 {
3541         struct r8152 *tp = netdev_priv(dev);
3542         struct tally_counter tally;
3543
3544         if (usb_autopm_get_interface(tp->intf) < 0)
3545                 return;
3546
3547         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3548
3549         usb_autopm_put_interface(tp->intf);
3550
3551         data[0] = le64_to_cpu(tally.tx_packets);
3552         data[1] = le64_to_cpu(tally.rx_packets);
3553         data[2] = le64_to_cpu(tally.tx_errors);
3554         data[3] = le32_to_cpu(tally.rx_errors);
3555         data[4] = le16_to_cpu(tally.rx_missed);
3556         data[5] = le16_to_cpu(tally.align_errors);
3557         data[6] = le32_to_cpu(tally.tx_one_collision);
3558         data[7] = le32_to_cpu(tally.tx_multi_collision);
3559         data[8] = le64_to_cpu(tally.rx_unicast);
3560         data[9] = le64_to_cpu(tally.rx_broadcast);
3561         data[10] = le32_to_cpu(tally.rx_multicast);
3562         data[11] = le16_to_cpu(tally.tx_aborted);
3563         data[12] = le16_to_cpu(tally.tx_underrun);
3564 }
3565
3566 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3567 {
3568         switch (stringset) {
3569         case ETH_SS_STATS:
3570                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3571                 break;
3572         }
3573 }
3574
3575 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3576 {
3577         u32 ocp_data, lp, adv, supported = 0;
3578         u16 val;
3579
3580         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3581         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3582
3583         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3584         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3585
3586         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3587         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3588
3589         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3590         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3591
3592         eee->eee_enabled = !!ocp_data;
3593         eee->eee_active = !!(supported & adv & lp);
3594         eee->supported = supported;
3595         eee->advertised = adv;
3596         eee->lp_advertised = lp;
3597
3598         return 0;
3599 }
3600
3601 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3602 {
3603         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3604
3605         r8152_eee_en(tp, eee->eee_enabled);
3606
3607         if (!eee->eee_enabled)
3608                 val = 0;
3609
3610         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3611
3612         return 0;
3613 }
3614
3615 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3616 {
3617         u32 ocp_data, lp, adv, supported = 0;
3618         u16 val;
3619
3620         val = ocp_reg_read(tp, OCP_EEE_ABLE);
3621         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3622
3623         val = ocp_reg_read(tp, OCP_EEE_ADV);
3624         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3625
3626         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3627         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3628
3629         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3630         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3631
3632         eee->eee_enabled = !!ocp_data;
3633         eee->eee_active = !!(supported & adv & lp);
3634         eee->supported = supported;
3635         eee->advertised = adv;
3636         eee->lp_advertised = lp;
3637
3638         return 0;
3639 }
3640
3641 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3642 {
3643         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3644
3645         r8153_eee_en(tp, eee->eee_enabled);
3646
3647         if (!eee->eee_enabled)
3648                 val = 0;
3649
3650         ocp_reg_write(tp, OCP_EEE_ADV, val);
3651
3652         return 0;
3653 }
3654
3655 static int
3656 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3657 {
3658         struct r8152 *tp = netdev_priv(net);
3659         int ret;
3660
3661         ret = usb_autopm_get_interface(tp->intf);
3662         if (ret < 0)
3663                 goto out;
3664
3665         mutex_lock(&tp->control);
3666
3667         ret = tp->rtl_ops.eee_get(tp, edata);
3668
3669         mutex_unlock(&tp->control);
3670
3671         usb_autopm_put_interface(tp->intf);
3672
3673 out:
3674         return ret;
3675 }
3676
3677 static int
3678 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3679 {
3680         struct r8152 *tp = netdev_priv(net);
3681         int ret;
3682
3683         ret = usb_autopm_get_interface(tp->intf);
3684         if (ret < 0)
3685                 goto out;
3686
3687         mutex_lock(&tp->control);
3688
3689         ret = tp->rtl_ops.eee_set(tp, edata);
3690         if (!ret)
3691                 ret = mii_nway_restart(&tp->mii);
3692
3693         mutex_unlock(&tp->control);
3694
3695         usb_autopm_put_interface(tp->intf);
3696
3697 out:
3698         return ret;
3699 }
3700
3701 static int rtl8152_nway_reset(struct net_device *dev)
3702 {
3703         struct r8152 *tp = netdev_priv(dev);
3704         int ret;
3705
3706         ret = usb_autopm_get_interface(tp->intf);
3707         if (ret < 0)
3708                 goto out;
3709
3710         mutex_lock(&tp->control);
3711
3712         ret = mii_nway_restart(&tp->mii);
3713
3714         mutex_unlock(&tp->control);
3715
3716         usb_autopm_put_interface(tp->intf);
3717
3718 out:
3719         return ret;
3720 }
3721
3722 static struct ethtool_ops ops = {
3723         .get_drvinfo = rtl8152_get_drvinfo,
3724         .get_settings = rtl8152_get_settings,
3725         .set_settings = rtl8152_set_settings,
3726         .get_link = ethtool_op_get_link,
3727         .nway_reset = rtl8152_nway_reset,
3728         .get_msglevel = rtl8152_get_msglevel,
3729         .set_msglevel = rtl8152_set_msglevel,
3730         .get_wol = rtl8152_get_wol,
3731         .set_wol = rtl8152_set_wol,
3732         .get_strings = rtl8152_get_strings,
3733         .get_sset_count = rtl8152_get_sset_count,
3734         .get_ethtool_stats = rtl8152_get_ethtool_stats,
3735         .get_eee = rtl_ethtool_get_eee,
3736         .set_eee = rtl_ethtool_set_eee,
3737 };
3738
3739 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3740 {
3741         struct r8152 *tp = netdev_priv(netdev);
3742         struct mii_ioctl_data *data = if_mii(rq);
3743         int res;
3744
3745         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3746                 return -ENODEV;
3747
3748         res = usb_autopm_get_interface(tp->intf);
3749         if (res < 0)
3750                 goto out;
3751
3752         switch (cmd) {
3753         case SIOCGMIIPHY:
3754                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3755                 break;
3756
3757         case SIOCGMIIREG:
3758                 mutex_lock(&tp->control);
3759                 data->val_out = r8152_mdio_read(tp, data->reg_num);
3760                 mutex_unlock(&tp->control);
3761                 break;
3762
3763         case SIOCSMIIREG:
3764                 if (!capable(CAP_NET_ADMIN)) {
3765                         res = -EPERM;
3766                         break;
3767                 }
3768                 mutex_lock(&tp->control);
3769                 r8152_mdio_write(tp, data->reg_num, data->val_in);
3770                 mutex_unlock(&tp->control);
3771                 break;
3772
3773         default:
3774                 res = -EOPNOTSUPP;
3775         }
3776
3777         usb_autopm_put_interface(tp->intf);
3778
3779 out:
3780         return res;
3781 }
3782
3783 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3784 {
3785         struct r8152 *tp = netdev_priv(dev);
3786
3787         switch (tp->version) {
3788         case RTL_VER_01:
3789         case RTL_VER_02:
3790                 return eth_change_mtu(dev, new_mtu);
3791         default:
3792                 break;
3793         }
3794
3795         if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3796                 return -EINVAL;
3797
3798         dev->mtu = new_mtu;
3799
3800         return 0;
3801 }
3802
3803 static const struct net_device_ops rtl8152_netdev_ops = {
3804         .ndo_open               = rtl8152_open,
3805         .ndo_stop               = rtl8152_close,
3806         .ndo_do_ioctl           = rtl8152_ioctl,
3807         .ndo_start_xmit         = rtl8152_start_xmit,
3808         .ndo_tx_timeout         = rtl8152_tx_timeout,
3809         .ndo_set_features       = rtl8152_set_features,
3810         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
3811         .ndo_set_mac_address    = rtl8152_set_mac_address,
3812         .ndo_change_mtu         = rtl8152_change_mtu,
3813         .ndo_validate_addr      = eth_validate_addr,
3814         .ndo_features_check     = rtl8152_features_check,
3815 };
3816
3817 static void r8152b_get_version(struct r8152 *tp)
3818 {
3819         u32     ocp_data;
3820         u16     version;
3821
3822         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3823         version = (u16)(ocp_data & VERSION_MASK);
3824
3825         switch (version) {
3826         case 0x4c00:
3827                 tp->version = RTL_VER_01;
3828                 break;
3829         case 0x4c10:
3830                 tp->version = RTL_VER_02;
3831                 break;
3832         case 0x5c00:
3833                 tp->version = RTL_VER_03;
3834                 tp->mii.supports_gmii = 1;
3835                 break;
3836         case 0x5c10:
3837                 tp->version = RTL_VER_04;
3838                 tp->mii.supports_gmii = 1;
3839                 break;
3840         case 0x5c20:
3841                 tp->version = RTL_VER_05;
3842                 tp->mii.supports_gmii = 1;
3843                 break;
3844         default:
3845                 netif_info(tp, probe, tp->netdev,
3846                            "Unknown version 0x%04x\n", version);
3847                 break;
3848         }
3849 }
3850
3851 static void rtl8152_unload(struct r8152 *tp)
3852 {
3853         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3854                 return;
3855
3856         if (tp->version != RTL_VER_01)
3857                 r8152_power_cut_en(tp, true);
3858 }
3859
3860 static void rtl8153_unload(struct r8152 *tp)
3861 {
3862         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3863                 return;
3864
3865         r8153_power_cut_en(tp, false);
3866 }
3867
3868 static int rtl_ops_init(struct r8152 *tp)
3869 {
3870         struct rtl_ops *ops = &tp->rtl_ops;
3871         int ret = 0;
3872
3873         switch (tp->version) {
3874         case RTL_VER_01:
3875         case RTL_VER_02:
3876                 ops->init               = r8152b_init;
3877                 ops->enable             = rtl8152_enable;
3878                 ops->disable            = rtl8152_disable;
3879                 ops->up                 = rtl8152_up;
3880                 ops->down               = rtl8152_down;
3881                 ops->unload             = rtl8152_unload;
3882                 ops->eee_get            = r8152_get_eee;
3883                 ops->eee_set            = r8152_set_eee;
3884                 break;
3885
3886         case RTL_VER_03:
3887         case RTL_VER_04:
3888         case RTL_VER_05:
3889                 ops->init               = r8153_init;
3890                 ops->enable             = rtl8153_enable;
3891                 ops->disable            = rtl8153_disable;
3892                 ops->up                 = rtl8153_up;
3893                 ops->down               = rtl8153_down;
3894                 ops->unload             = rtl8153_unload;
3895                 ops->eee_get            = r8153_get_eee;
3896                 ops->eee_set            = r8153_set_eee;
3897                 break;
3898
3899         default:
3900                 ret = -ENODEV;
3901                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3902                 break;
3903         }
3904
3905         return ret;
3906 }
3907
3908 static int rtl8152_probe(struct usb_interface *intf,
3909                          const struct usb_device_id *id)
3910 {
3911         struct usb_device *udev = interface_to_usbdev(intf);
3912         struct r8152 *tp;
3913         struct net_device *netdev;
3914         int ret;
3915
3916         if (udev->actconfig->desc.bConfigurationValue != 1) {
3917                 usb_driver_set_configuration(udev, 1);
3918                 return -ENODEV;
3919         }
3920
3921         usb_reset_device(udev);
3922         netdev = alloc_etherdev(sizeof(struct r8152));
3923         if (!netdev) {
3924                 dev_err(&intf->dev, "Out of memory\n");
3925                 return -ENOMEM;
3926         }
3927
3928         SET_NETDEV_DEV(netdev, &intf->dev);
3929         tp = netdev_priv(netdev);
3930         tp->msg_enable = 0x7FFF;
3931
3932         tp->udev = udev;
3933         tp->netdev = netdev;
3934         tp->intf = intf;
3935
3936         r8152b_get_version(tp);
3937         ret = rtl_ops_init(tp);
3938         if (ret)
3939                 goto out;
3940
3941         mutex_init(&tp->control);
3942         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3943
3944         netdev->netdev_ops = &rtl8152_netdev_ops;
3945         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3946
3947         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3948                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3949                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3950                             NETIF_F_HW_VLAN_CTAG_TX;
3951         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3952                               NETIF_F_TSO | NETIF_F_FRAGLIST |
3953                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3954                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
3955         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3956                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3957                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3958
3959         netdev->ethtool_ops = &ops;
3960         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3961
3962         tp->mii.dev = netdev;
3963         tp->mii.mdio_read = read_mii_word;
3964         tp->mii.mdio_write = write_mii_word;
3965         tp->mii.phy_id_mask = 0x3f;
3966         tp->mii.reg_num_mask = 0x1f;
3967         tp->mii.phy_id = R8152_PHY_ID;
3968
3969         intf->needs_remote_wakeup = 1;
3970
3971         tp->rtl_ops.init(tp);
3972         set_ethernet_addr(tp);
3973
3974         usb_set_intfdata(intf, tp);
3975         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
3976
3977         ret = register_netdev(netdev);
3978         if (ret != 0) {
3979                 netif_err(tp, probe, netdev, "couldn't register the device\n");
3980                 goto out1;
3981         }
3982
3983         tp->saved_wolopts = __rtl_get_wol(tp);
3984         if (tp->saved_wolopts)
3985                 device_set_wakeup_enable(&udev->dev, true);
3986         else
3987                 device_set_wakeup_enable(&udev->dev, false);
3988
3989         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3990
3991         return 0;
3992
3993 out1:
3994         netif_napi_del(&tp->napi);
3995         usb_set_intfdata(intf, NULL);
3996 out:
3997         free_netdev(netdev);
3998         return ret;
3999 }
4000
4001 static void rtl8152_disconnect(struct usb_interface *intf)
4002 {
4003         struct r8152 *tp = usb_get_intfdata(intf);
4004
4005         usb_set_intfdata(intf, NULL);
4006         if (tp) {
4007                 struct usb_device *udev = tp->udev;
4008
4009                 if (udev->state == USB_STATE_NOTATTACHED)
4010                         set_bit(RTL8152_UNPLUG, &tp->flags);
4011
4012                 netif_napi_del(&tp->napi);
4013                 unregister_netdev(tp->netdev);
4014                 tp->rtl_ops.unload(tp);
4015                 free_netdev(tp->netdev);
4016         }
4017 }
4018
4019 #define REALTEK_USB_DEVICE(vend, prod)  \
4020         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4021                        USB_DEVICE_ID_MATCH_INT_CLASS, \
4022         .idVendor = (vend), \
4023         .idProduct = (prod), \
4024         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4025 }, \
4026 { \
4027         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4028                        USB_DEVICE_ID_MATCH_DEVICE, \
4029         .idVendor = (vend), \
4030         .idProduct = (prod), \
4031         .bInterfaceClass = USB_CLASS_COMM, \
4032         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4033         .bInterfaceProtocol = USB_CDC_PROTO_NONE
4034
4035 /* table of devices that work with this driver */
4036 static struct usb_device_id rtl8152_table[] = {
4037         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4038         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4039         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
4040         {}
4041 };
4042
4043 MODULE_DEVICE_TABLE(usb, rtl8152_table);
4044
4045 static struct usb_driver rtl8152_driver = {
4046         .name =         MODULENAME,
4047         .id_table =     rtl8152_table,
4048         .probe =        rtl8152_probe,
4049         .disconnect =   rtl8152_disconnect,
4050         .suspend =      rtl8152_suspend,
4051         .resume =       rtl8152_resume,
4052         .reset_resume = rtl8152_resume,
4053         .supports_autosuspend = 1,
4054         .disable_hub_initiated_lpm = 1,
4055 };
4056
4057 module_usb_driver(rtl8152_driver);
4058
4059 MODULE_AUTHOR(DRIVER_AUTHOR);
4060 MODULE_DESCRIPTION(DRIVER_DESC);
4061 MODULE_LICENSE("GPL");