r8152: support the new RTL8153 chip
[cascardo/linux.git] / drivers / net / usb / r8152.c
1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28
29 /* Version Information */
30 #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
31 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
32 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
33 #define MODULENAME "r8152"
34
35 #define R8152_PHY_ID            32
36
37 #define PLA_IDR                 0xc000
38 #define PLA_RCR                 0xc010
39 #define PLA_RMS                 0xc016
40 #define PLA_RXFIFO_CTRL0        0xc0a0
41 #define PLA_RXFIFO_CTRL1        0xc0a4
42 #define PLA_RXFIFO_CTRL2        0xc0a8
43 #define PLA_DMY_REG0            0xc0b0
44 #define PLA_FMC                 0xc0b4
45 #define PLA_CFG_WOL             0xc0b6
46 #define PLA_TEREDO_CFG          0xc0bc
47 #define PLA_MAR                 0xcd00
48 #define PLA_BACKUP              0xd000
49 #define PAL_BDC_CR              0xd1a0
50 #define PLA_TEREDO_TIMER        0xd2cc
51 #define PLA_REALWOW_TIMER       0xd2e8
52 #define PLA_LEDSEL              0xdd90
53 #define PLA_LED_FEATURE         0xdd92
54 #define PLA_PHYAR               0xde00
55 #define PLA_BOOT_CTRL           0xe004
56 #define PLA_GPHY_INTR_IMR       0xe022
57 #define PLA_EEE_CR              0xe040
58 #define PLA_EEEP_CR             0xe080
59 #define PLA_MAC_PWR_CTRL        0xe0c0
60 #define PLA_MAC_PWR_CTRL2       0xe0ca
61 #define PLA_MAC_PWR_CTRL3       0xe0cc
62 #define PLA_MAC_PWR_CTRL4       0xe0ce
63 #define PLA_WDT6_CTRL           0xe428
64 #define PLA_TCR0                0xe610
65 #define PLA_TCR1                0xe612
66 #define PLA_MTPS                0xe615
67 #define PLA_TXFIFO_CTRL         0xe618
68 #define PLA_RSTTALLY            0xe800
69 #define PLA_CR                  0xe813
70 #define PLA_CRWECR              0xe81c
71 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
72 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
73 #define PLA_CONFIG5             0xe822
74 #define PLA_PHY_PWR             0xe84c
75 #define PLA_OOB_CTRL            0xe84f
76 #define PLA_CPCR                0xe854
77 #define PLA_MISC_0              0xe858
78 #define PLA_MISC_1              0xe85a
79 #define PLA_OCP_GPHY_BASE       0xe86c
80 #define PLA_TALLYCNT            0xe890
81 #define PLA_SFF_STS_7           0xe8de
82 #define PLA_PHYSTATUS           0xe908
83 #define PLA_BP_BA               0xfc26
84 #define PLA_BP_0                0xfc28
85 #define PLA_BP_1                0xfc2a
86 #define PLA_BP_2                0xfc2c
87 #define PLA_BP_3                0xfc2e
88 #define PLA_BP_4                0xfc30
89 #define PLA_BP_5                0xfc32
90 #define PLA_BP_6                0xfc34
91 #define PLA_BP_7                0xfc36
92 #define PLA_BP_EN               0xfc38
93
94 #define USB_USB2PHY             0xb41e
95 #define USB_SSPHYLINK2          0xb428
96 #define USB_U2P3_CTRL           0xb460
97 #define USB_CSR_DUMMY1          0xb464
98 #define USB_CSR_DUMMY2          0xb466
99 #define USB_DEV_STAT            0xb808
100 #define USB_CONNECT_TIMER       0xcbf8
101 #define USB_BURST_SIZE          0xcfc0
102 #define USB_USB_CTRL            0xd406
103 #define USB_PHY_CTRL            0xd408
104 #define USB_TX_AGG              0xd40a
105 #define USB_RX_BUF_TH           0xd40c
106 #define USB_USB_TIMER           0xd428
107 #define USB_RX_EARLY_TIMEOUT    0xd42c
108 #define USB_RX_EARLY_SIZE       0xd42e
109 #define USB_PM_CTRL_STATUS      0xd432
110 #define USB_TX_DMA              0xd434
111 #define USB_TOLERANCE           0xd490
112 #define USB_LPM_CTRL            0xd41a
113 #define USB_UPS_CTRL            0xd800
114 #define USB_MISC_0              0xd81a
115 #define USB_POWER_CUT           0xd80a
116 #define USB_AFE_CTRL2           0xd824
117 #define USB_WDT11_CTRL          0xe43c
118 #define USB_BP_BA               0xfc26
119 #define USB_BP_0                0xfc28
120 #define USB_BP_1                0xfc2a
121 #define USB_BP_2                0xfc2c
122 #define USB_BP_3                0xfc2e
123 #define USB_BP_4                0xfc30
124 #define USB_BP_5                0xfc32
125 #define USB_BP_6                0xfc34
126 #define USB_BP_7                0xfc36
127 #define USB_BP_EN               0xfc38
128
129 /* OCP Registers */
130 #define OCP_ALDPS_CONFIG        0x2010
131 #define OCP_EEE_CONFIG1         0x2080
132 #define OCP_EEE_CONFIG2         0x2092
133 #define OCP_EEE_CONFIG3         0x2094
134 #define OCP_BASE_MII            0xa400
135 #define OCP_EEE_AR              0xa41a
136 #define OCP_EEE_DATA            0xa41c
137 #define OCP_PHY_STATUS          0xa420
138 #define OCP_POWER_CFG           0xa430
139 #define OCP_EEE_CFG             0xa432
140 #define OCP_SRAM_ADDR           0xa436
141 #define OCP_SRAM_DATA           0xa438
142 #define OCP_DOWN_SPEED          0xa442
143 #define OCP_EEE_ABLE            0xa5c4
144 #define OCP_EEE_ADV             0xa5d0
145 #define OCP_EEE_LPABLE          0xa5d2
146 #define OCP_ADC_CFG             0xbc06
147
148 /* SRAM Register */
149 #define SRAM_LPF_CFG            0x8012
150 #define SRAM_10M_AMP1           0x8080
151 #define SRAM_10M_AMP2           0x8082
152 #define SRAM_IMPEDANCE          0x8084
153
154 /* PLA_RCR */
155 #define RCR_AAP                 0x00000001
156 #define RCR_APM                 0x00000002
157 #define RCR_AM                  0x00000004
158 #define RCR_AB                  0x00000008
159 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
160
161 /* PLA_RXFIFO_CTRL0 */
162 #define RXFIFO_THR1_NORMAL      0x00080002
163 #define RXFIFO_THR1_OOB         0x01800003
164
165 /* PLA_RXFIFO_CTRL1 */
166 #define RXFIFO_THR2_FULL        0x00000060
167 #define RXFIFO_THR2_HIGH        0x00000038
168 #define RXFIFO_THR2_OOB         0x0000004a
169 #define RXFIFO_THR2_NORMAL      0x00a0
170
171 /* PLA_RXFIFO_CTRL2 */
172 #define RXFIFO_THR3_FULL        0x00000078
173 #define RXFIFO_THR3_HIGH        0x00000048
174 #define RXFIFO_THR3_OOB         0x0000005a
175 #define RXFIFO_THR3_NORMAL      0x0110
176
177 /* PLA_TXFIFO_CTRL */
178 #define TXFIFO_THR_NORMAL       0x00400008
179 #define TXFIFO_THR_NORMAL2      0x01000008
180
181 /* PLA_DMY_REG0 */
182 #define ECM_ALDPS               0x0002
183
184 /* PLA_FMC */
185 #define FMC_FCR_MCU_EN          0x0001
186
187 /* PLA_EEEP_CR */
188 #define EEEP_CR_EEEP_TX         0x0002
189
190 /* PLA_WDT6_CTRL */
191 #define WDT6_SET_MODE           0x0010
192
193 /* PLA_TCR0 */
194 #define TCR0_TX_EMPTY           0x0800
195 #define TCR0_AUTO_FIFO          0x0080
196
197 /* PLA_TCR1 */
198 #define VERSION_MASK            0x7cf0
199
200 /* PLA_MTPS */
201 #define MTPS_JUMBO              (12 * 1024 / 64)
202 #define MTPS_DEFAULT            (6 * 1024 / 64)
203
204 /* PLA_RSTTALLY */
205 #define TALLY_RESET             0x0001
206
207 /* PLA_CR */
208 #define CR_RST                  0x10
209 #define CR_RE                   0x08
210 #define CR_TE                   0x04
211
212 /* PLA_CRWECR */
213 #define CRWECR_NORAML           0x00
214 #define CRWECR_CONFIG           0xc0
215
216 /* PLA_OOB_CTRL */
217 #define NOW_IS_OOB              0x80
218 #define TXFIFO_EMPTY            0x20
219 #define RXFIFO_EMPTY            0x10
220 #define LINK_LIST_READY         0x02
221 #define DIS_MCU_CLROOB          0x01
222 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
223
224 /* PLA_MISC_1 */
225 #define RXDY_GATED_EN           0x0008
226
227 /* PLA_SFF_STS_7 */
228 #define RE_INIT_LL              0x8000
229 #define MCU_BORW_EN             0x4000
230
231 /* PLA_CPCR */
232 #define CPCR_RX_VLAN            0x0040
233
234 /* PLA_CFG_WOL */
235 #define MAGIC_EN                0x0001
236
237 /* PLA_TEREDO_CFG */
238 #define TEREDO_SEL              0x8000
239 #define TEREDO_WAKE_MASK        0x7f00
240 #define TEREDO_RS_EVENT_MASK    0x00fe
241 #define OOB_TEREDO_EN           0x0001
242
243 /* PAL_BDC_CR */
244 #define ALDPS_PROXY_MODE        0x0001
245
246 /* PLA_CONFIG34 */
247 #define LINK_ON_WAKE_EN         0x0010
248 #define LINK_OFF_WAKE_EN        0x0008
249
250 /* PLA_CONFIG5 */
251 #define BWF_EN                  0x0040
252 #define MWF_EN                  0x0020
253 #define UWF_EN                  0x0010
254 #define LAN_WAKE_EN             0x0002
255
256 /* PLA_LED_FEATURE */
257 #define LED_MODE_MASK           0x0700
258
259 /* PLA_PHY_PWR */
260 #define TX_10M_IDLE_EN          0x0080
261 #define PFM_PWM_SWITCH          0x0040
262
263 /* PLA_MAC_PWR_CTRL */
264 #define D3_CLK_GATED_EN         0x00004000
265 #define MCU_CLK_RATIO           0x07010f07
266 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
267 #define ALDPS_SPDWN_RATIO       0x0f87
268
269 /* PLA_MAC_PWR_CTRL2 */
270 #define EEE_SPDWN_RATIO         0x8007
271
272 /* PLA_MAC_PWR_CTRL3 */
273 #define PKT_AVAIL_SPDWN_EN      0x0100
274 #define SUSPEND_SPDWN_EN        0x0004
275 #define U1U2_SPDWN_EN           0x0002
276 #define L1_SPDWN_EN             0x0001
277
278 /* PLA_MAC_PWR_CTRL4 */
279 #define PWRSAVE_SPDWN_EN        0x1000
280 #define RXDV_SPDWN_EN           0x0800
281 #define TX10MIDLE_EN            0x0100
282 #define TP100_SPDWN_EN          0x0020
283 #define TP500_SPDWN_EN          0x0010
284 #define TP1000_SPDWN_EN         0x0008
285 #define EEE_SPDWN_EN            0x0001
286
287 /* PLA_GPHY_INTR_IMR */
288 #define GPHY_STS_MSK            0x0001
289 #define SPEED_DOWN_MSK          0x0002
290 #define SPDWN_RXDV_MSK          0x0004
291 #define SPDWN_LINKCHG_MSK       0x0008
292
293 /* PLA_PHYAR */
294 #define PHYAR_FLAG              0x80000000
295
296 /* PLA_EEE_CR */
297 #define EEE_RX_EN               0x0001
298 #define EEE_TX_EN               0x0002
299
300 /* PLA_BOOT_CTRL */
301 #define AUTOLOAD_DONE           0x0002
302
303 /* USB_USB2PHY */
304 #define USB2PHY_SUSPEND         0x0001
305 #define USB2PHY_L1              0x0002
306
307 /* USB_SSPHYLINK2 */
308 #define pwd_dn_scale_mask       0x3ffe
309 #define pwd_dn_scale(x)         ((x) << 1)
310
311 /* USB_CSR_DUMMY1 */
312 #define DYNAMIC_BURST           0x0001
313
314 /* USB_CSR_DUMMY2 */
315 #define EP4_FULL_FC             0x0001
316
317 /* USB_DEV_STAT */
318 #define STAT_SPEED_MASK         0x0006
319 #define STAT_SPEED_HIGH         0x0000
320 #define STAT_SPEED_FULL         0x0002
321
322 /* USB_TX_AGG */
323 #define TX_AGG_MAX_THRESHOLD    0x03
324
325 /* USB_RX_BUF_TH */
326 #define RX_THR_SUPPER           0x0c350180
327 #define RX_THR_HIGH             0x7a120180
328 #define RX_THR_SLOW             0xffff0180
329
330 /* USB_TX_DMA */
331 #define TEST_MODE_DISABLE       0x00000001
332 #define TX_SIZE_ADJUST1         0x00000100
333
334 /* USB_UPS_CTRL */
335 #define POWER_CUT               0x0100
336
337 /* USB_PM_CTRL_STATUS */
338 #define RESUME_INDICATE         0x0001
339
340 /* USB_USB_CTRL */
341 #define RX_AGG_DISABLE          0x0010
342
343 /* USB_U2P3_CTRL */
344 #define U2P3_ENABLE             0x0001
345
346 /* USB_POWER_CUT */
347 #define PWR_EN                  0x0001
348 #define PHASE2_EN               0x0008
349
350 /* USB_MISC_0 */
351 #define PCUT_STATUS             0x0001
352
353 /* USB_RX_EARLY_TIMEOUT */
354 #define COALESCE_SUPER           85000U
355 #define COALESCE_HIGH           250000U
356 #define COALESCE_SLOW           524280U
357
358 /* USB_WDT11_CTRL */
359 #define TIMER11_EN              0x0001
360
361 /* USB_LPM_CTRL */
362 /* bit 4 ~ 5: fifo empty boundary */
363 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
364 /* bit 2 ~ 3: LMP timer */
365 #define LPM_TIMER_MASK          0x0c
366 #define LPM_TIMER_500MS         0x04    /* 500 ms */
367 #define LPM_TIMER_500US         0x0c    /* 500 us */
368 #define ROK_EXIT_LPM            0x02
369
370 /* USB_AFE_CTRL2 */
371 #define SEN_VAL_MASK            0xf800
372 #define SEN_VAL_NORMAL          0xa000
373 #define SEL_RXIDLE              0x0100
374
375 /* OCP_ALDPS_CONFIG */
376 #define ENPWRSAVE               0x8000
377 #define ENPDNPS                 0x0200
378 #define LINKENA                 0x0100
379 #define DIS_SDSAVE              0x0010
380
381 /* OCP_PHY_STATUS */
382 #define PHY_STAT_MASK           0x0007
383 #define PHY_STAT_LAN_ON         3
384 #define PHY_STAT_PWRDN          5
385
386 /* OCP_POWER_CFG */
387 #define EEE_CLKDIV_EN           0x8000
388 #define EN_ALDPS                0x0004
389 #define EN_10M_PLLOFF           0x0001
390
391 /* OCP_EEE_CONFIG1 */
392 #define RG_TXLPI_MSK_HFDUP      0x8000
393 #define RG_MATCLR_EN            0x4000
394 #define EEE_10_CAP              0x2000
395 #define EEE_NWAY_EN             0x1000
396 #define TX_QUIET_EN             0x0200
397 #define RX_QUIET_EN             0x0100
398 #define sd_rise_time_mask       0x0070
399 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
400 #define RG_RXLPI_MSK_HFDUP      0x0008
401 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
402
403 /* OCP_EEE_CONFIG2 */
404 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
405 #define RG_DACQUIET_EN          0x0400
406 #define RG_LDVQUIET_EN          0x0200
407 #define RG_CKRSEL               0x0020
408 #define RG_EEEPRG_EN            0x0010
409
410 /* OCP_EEE_CONFIG3 */
411 #define fast_snr_mask           0xff80
412 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
413 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
414 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
415
416 /* OCP_EEE_AR */
417 /* bit[15:14] function */
418 #define FUN_ADDR                0x0000
419 #define FUN_DATA                0x4000
420 /* bit[4:0] device addr */
421
422 /* OCP_EEE_CFG */
423 #define CTAP_SHORT_EN           0x0040
424 #define EEE10_EN                0x0010
425
426 /* OCP_DOWN_SPEED */
427 #define EN_10M_BGOFF            0x0080
428
429 /* OCP_ADC_CFG */
430 #define CKADSEL_L               0x0100
431 #define ADC_EN                  0x0080
432 #define EN_EMI_L                0x0040
433
434 /* SRAM_LPF_CFG */
435 #define LPF_AUTO_TUNE           0x8000
436
437 /* SRAM_10M_AMP1 */
438 #define GDAC_IB_UPALL           0x0008
439
440 /* SRAM_10M_AMP2 */
441 #define AMP_DN                  0x0200
442
443 /* SRAM_IMPEDANCE */
444 #define RX_DRIVING_MASK         0x6000
445
446 enum rtl_register_content {
447         _1000bps        = 0x10,
448         _100bps         = 0x08,
449         _10bps          = 0x04,
450         LINK_STATUS     = 0x02,
451         FULL_DUP        = 0x01,
452 };
453
454 #define RTL8152_MAX_TX          4
455 #define RTL8152_MAX_RX          10
456 #define INTBUFSIZE              2
457 #define CRC_SIZE                4
458 #define TX_ALIGN                4
459 #define RX_ALIGN                8
460
461 #define INTR_LINK               0x0004
462
463 #define RTL8152_REQT_READ       0xc0
464 #define RTL8152_REQT_WRITE      0x40
465 #define RTL8152_REQ_GET_REGS    0x05
466 #define RTL8152_REQ_SET_REGS    0x05
467
468 #define BYTE_EN_DWORD           0xff
469 #define BYTE_EN_WORD            0x33
470 #define BYTE_EN_BYTE            0x11
471 #define BYTE_EN_SIX_BYTES       0x3f
472 #define BYTE_EN_START_MASK      0x0f
473 #define BYTE_EN_END_MASK        0xf0
474
475 #define RTL8153_MAX_PACKET      9216 /* 9K */
476 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
477 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
478 #define RTL8153_RMS             RTL8153_MAX_PACKET
479 #define RTL8152_TX_TIMEOUT      (5 * HZ)
480 #define RTL8152_NAPI_WEIGHT     64
481
482 /* rtl8152 flags */
483 enum rtl8152_flags {
484         RTL8152_UNPLUG = 0,
485         RTL8152_SET_RX_MODE,
486         WORK_ENABLE,
487         RTL8152_LINK_CHG,
488         SELECTIVE_SUSPEND,
489         PHY_RESET,
490         SCHEDULE_NAPI,
491 };
492
493 /* Define these values to match your device */
494 #define VENDOR_ID_REALTEK               0x0bda
495 #define VENDOR_ID_SAMSUNG               0x04e8
496 #define VENDOR_ID_LENOVO                0x17ef
497 #define VENDOR_ID_NVIDIA                0x0955
498
499 #define MCU_TYPE_PLA                    0x0100
500 #define MCU_TYPE_USB                    0x0000
501
502 struct tally_counter {
503         __le64  tx_packets;
504         __le64  rx_packets;
505         __le64  tx_errors;
506         __le32  rx_errors;
507         __le16  rx_missed;
508         __le16  align_errors;
509         __le32  tx_one_collision;
510         __le32  tx_multi_collision;
511         __le64  rx_unicast;
512         __le64  rx_broadcast;
513         __le32  rx_multicast;
514         __le16  tx_aborted;
515         __le16  tx_underrun;
516 };
517
518 struct rx_desc {
519         __le32 opts1;
520 #define RX_LEN_MASK                     0x7fff
521
522         __le32 opts2;
523 #define RD_UDP_CS                       BIT(23)
524 #define RD_TCP_CS                       BIT(22)
525 #define RD_IPV6_CS                      BIT(20)
526 #define RD_IPV4_CS                      BIT(19)
527
528         __le32 opts3;
529 #define IPF                             BIT(23) /* IP checksum fail */
530 #define UDPF                            BIT(22) /* UDP checksum fail */
531 #define TCPF                            BIT(21) /* TCP checksum fail */
532 #define RX_VLAN_TAG                     BIT(16)
533
534         __le32 opts4;
535         __le32 opts5;
536         __le32 opts6;
537 };
538
539 struct tx_desc {
540         __le32 opts1;
541 #define TX_FS                   BIT(31) /* First segment of a packet */
542 #define TX_LS                   BIT(30) /* Final segment of a packet */
543 #define GTSENDV4                BIT(28)
544 #define GTSENDV6                BIT(27)
545 #define GTTCPHO_SHIFT           18
546 #define GTTCPHO_MAX             0x7fU
547 #define TX_LEN_MAX              0x3ffffU
548
549         __le32 opts2;
550 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
551 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
552 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
553 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
554 #define MSS_SHIFT               17
555 #define MSS_MAX                 0x7ffU
556 #define TCPHO_SHIFT             17
557 #define TCPHO_MAX               0x7ffU
558 #define TX_VLAN_TAG             BIT(16)
559 };
560
561 struct r8152;
562
563 struct rx_agg {
564         struct list_head list;
565         struct urb *urb;
566         struct r8152 *context;
567         void *buffer;
568         void *head;
569 };
570
571 struct tx_agg {
572         struct list_head list;
573         struct urb *urb;
574         struct r8152 *context;
575         void *buffer;
576         void *head;
577         u32 skb_num;
578         u32 skb_len;
579 };
580
581 struct r8152 {
582         unsigned long flags;
583         struct usb_device *udev;
584         struct napi_struct napi;
585         struct usb_interface *intf;
586         struct net_device *netdev;
587         struct urb *intr_urb;
588         struct tx_agg tx_info[RTL8152_MAX_TX];
589         struct rx_agg rx_info[RTL8152_MAX_RX];
590         struct list_head rx_done, tx_free;
591         struct sk_buff_head tx_queue, rx_queue;
592         spinlock_t rx_lock, tx_lock;
593         struct delayed_work schedule;
594         struct mii_if_info mii;
595         struct mutex control;   /* use for hw setting */
596
597         struct rtl_ops {
598                 void (*init)(struct r8152 *);
599                 int (*enable)(struct r8152 *);
600                 void (*disable)(struct r8152 *);
601                 void (*up)(struct r8152 *);
602                 void (*down)(struct r8152 *);
603                 void (*unload)(struct r8152 *);
604                 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
605                 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
606         } rtl_ops;
607
608         int intr_interval;
609         u32 saved_wolopts;
610         u32 msg_enable;
611         u32 tx_qlen;
612         u32 coalesce;
613         u16 ocp_base;
614         u8 *intr_buff;
615         u8 version;
616 };
617
618 enum rtl_version {
619         RTL_VER_UNKNOWN = 0,
620         RTL_VER_01,
621         RTL_VER_02,
622         RTL_VER_03,
623         RTL_VER_04,
624         RTL_VER_05,
625         RTL_VER_06,
626         RTL_VER_MAX
627 };
628
629 enum tx_csum_stat {
630         TX_CSUM_SUCCESS = 0,
631         TX_CSUM_TSO,
632         TX_CSUM_NONE
633 };
634
635 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
636  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
637  */
638 static const int multicast_filter_limit = 32;
639 static unsigned int agg_buf_sz = 16384;
640
641 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
642                                  VLAN_ETH_HLEN - VLAN_HLEN)
643
644 static
645 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
646 {
647         int ret;
648         void *tmp;
649
650         tmp = kmalloc(size, GFP_KERNEL);
651         if (!tmp)
652                 return -ENOMEM;
653
654         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
655                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
656                               value, index, tmp, size, 500);
657
658         memcpy(data, tmp, size);
659         kfree(tmp);
660
661         return ret;
662 }
663
664 static
665 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
666 {
667         int ret;
668         void *tmp;
669
670         tmp = kmemdup(data, size, GFP_KERNEL);
671         if (!tmp)
672                 return -ENOMEM;
673
674         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
675                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
676                               value, index, tmp, size, 500);
677
678         kfree(tmp);
679
680         return ret;
681 }
682
683 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
684                             void *data, u16 type)
685 {
686         u16 limit = 64;
687         int ret = 0;
688
689         if (test_bit(RTL8152_UNPLUG, &tp->flags))
690                 return -ENODEV;
691
692         /* both size and indix must be 4 bytes align */
693         if ((size & 3) || !size || (index & 3) || !data)
694                 return -EPERM;
695
696         if ((u32)index + (u32)size > 0xffff)
697                 return -EPERM;
698
699         while (size) {
700                 if (size > limit) {
701                         ret = get_registers(tp, index, type, limit, data);
702                         if (ret < 0)
703                                 break;
704
705                         index += limit;
706                         data += limit;
707                         size -= limit;
708                 } else {
709                         ret = get_registers(tp, index, type, size, data);
710                         if (ret < 0)
711                                 break;
712
713                         index += size;
714                         data += size;
715                         size = 0;
716                         break;
717                 }
718         }
719
720         if (ret == -ENODEV)
721                 set_bit(RTL8152_UNPLUG, &tp->flags);
722
723         return ret;
724 }
725
726 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
727                              u16 size, void *data, u16 type)
728 {
729         int ret;
730         u16 byteen_start, byteen_end, byen;
731         u16 limit = 512;
732
733         if (test_bit(RTL8152_UNPLUG, &tp->flags))
734                 return -ENODEV;
735
736         /* both size and indix must be 4 bytes align */
737         if ((size & 3) || !size || (index & 3) || !data)
738                 return -EPERM;
739
740         if ((u32)index + (u32)size > 0xffff)
741                 return -EPERM;
742
743         byteen_start = byteen & BYTE_EN_START_MASK;
744         byteen_end = byteen & BYTE_EN_END_MASK;
745
746         byen = byteen_start | (byteen_start << 4);
747         ret = set_registers(tp, index, type | byen, 4, data);
748         if (ret < 0)
749                 goto error1;
750
751         index += 4;
752         data += 4;
753         size -= 4;
754
755         if (size) {
756                 size -= 4;
757
758                 while (size) {
759                         if (size > limit) {
760                                 ret = set_registers(tp, index,
761                                                     type | BYTE_EN_DWORD,
762                                                     limit, data);
763                                 if (ret < 0)
764                                         goto error1;
765
766                                 index += limit;
767                                 data += limit;
768                                 size -= limit;
769                         } else {
770                                 ret = set_registers(tp, index,
771                                                     type | BYTE_EN_DWORD,
772                                                     size, data);
773                                 if (ret < 0)
774                                         goto error1;
775
776                                 index += size;
777                                 data += size;
778                                 size = 0;
779                                 break;
780                         }
781                 }
782
783                 byen = byteen_end | (byteen_end >> 4);
784                 ret = set_registers(tp, index, type | byen, 4, data);
785                 if (ret < 0)
786                         goto error1;
787         }
788
789 error1:
790         if (ret == -ENODEV)
791                 set_bit(RTL8152_UNPLUG, &tp->flags);
792
793         return ret;
794 }
795
796 static inline
797 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
798 {
799         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
800 }
801
802 static inline
803 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
804 {
805         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
806 }
807
808 static inline
809 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
810 {
811         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
812 }
813
814 static inline
815 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
816 {
817         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
818 }
819
820 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
821 {
822         __le32 data;
823
824         generic_ocp_read(tp, index, sizeof(data), &data, type);
825
826         return __le32_to_cpu(data);
827 }
828
829 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
830 {
831         __le32 tmp = __cpu_to_le32(data);
832
833         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
834 }
835
836 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
837 {
838         u32 data;
839         __le32 tmp;
840         u8 shift = index & 2;
841
842         index &= ~3;
843
844         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
845
846         data = __le32_to_cpu(tmp);
847         data >>= (shift * 8);
848         data &= 0xffff;
849
850         return (u16)data;
851 }
852
853 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
854 {
855         u32 mask = 0xffff;
856         __le32 tmp;
857         u16 byen = BYTE_EN_WORD;
858         u8 shift = index & 2;
859
860         data &= mask;
861
862         if (index & 2) {
863                 byen <<= shift;
864                 mask <<= (shift * 8);
865                 data <<= (shift * 8);
866                 index &= ~3;
867         }
868
869         tmp = __cpu_to_le32(data);
870
871         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
872 }
873
874 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
875 {
876         u32 data;
877         __le32 tmp;
878         u8 shift = index & 3;
879
880         index &= ~3;
881
882         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
883
884         data = __le32_to_cpu(tmp);
885         data >>= (shift * 8);
886         data &= 0xff;
887
888         return (u8)data;
889 }
890
891 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
892 {
893         u32 mask = 0xff;
894         __le32 tmp;
895         u16 byen = BYTE_EN_BYTE;
896         u8 shift = index & 3;
897
898         data &= mask;
899
900         if (index & 3) {
901                 byen <<= shift;
902                 mask <<= (shift * 8);
903                 data <<= (shift * 8);
904                 index &= ~3;
905         }
906
907         tmp = __cpu_to_le32(data);
908
909         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
910 }
911
912 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
913 {
914         u16 ocp_base, ocp_index;
915
916         ocp_base = addr & 0xf000;
917         if (ocp_base != tp->ocp_base) {
918                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
919                 tp->ocp_base = ocp_base;
920         }
921
922         ocp_index = (addr & 0x0fff) | 0xb000;
923         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
924 }
925
926 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
927 {
928         u16 ocp_base, ocp_index;
929
930         ocp_base = addr & 0xf000;
931         if (ocp_base != tp->ocp_base) {
932                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
933                 tp->ocp_base = ocp_base;
934         }
935
936         ocp_index = (addr & 0x0fff) | 0xb000;
937         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
938 }
939
940 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
941 {
942         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
943 }
944
945 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
946 {
947         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
948 }
949
950 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
951 {
952         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
953         ocp_reg_write(tp, OCP_SRAM_DATA, data);
954 }
955
956 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
957 {
958         struct r8152 *tp = netdev_priv(netdev);
959         int ret;
960
961         if (test_bit(RTL8152_UNPLUG, &tp->flags))
962                 return -ENODEV;
963
964         if (phy_id != R8152_PHY_ID)
965                 return -EINVAL;
966
967         ret = r8152_mdio_read(tp, reg);
968
969         return ret;
970 }
971
972 static
973 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
974 {
975         struct r8152 *tp = netdev_priv(netdev);
976
977         if (test_bit(RTL8152_UNPLUG, &tp->flags))
978                 return;
979
980         if (phy_id != R8152_PHY_ID)
981                 return;
982
983         r8152_mdio_write(tp, reg, val);
984 }
985
986 static int
987 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
988
989 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
990 {
991         struct r8152 *tp = netdev_priv(netdev);
992         struct sockaddr *addr = p;
993         int ret = -EADDRNOTAVAIL;
994
995         if (!is_valid_ether_addr(addr->sa_data))
996                 goto out1;
997
998         ret = usb_autopm_get_interface(tp->intf);
999         if (ret < 0)
1000                 goto out1;
1001
1002         mutex_lock(&tp->control);
1003
1004         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1005
1006         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1007         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1008         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1009
1010         mutex_unlock(&tp->control);
1011
1012         usb_autopm_put_interface(tp->intf);
1013 out1:
1014         return ret;
1015 }
1016
1017 static int set_ethernet_addr(struct r8152 *tp)
1018 {
1019         struct net_device *dev = tp->netdev;
1020         struct sockaddr sa;
1021         int ret;
1022
1023         if (tp->version == RTL_VER_01)
1024                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1025         else
1026                 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1027
1028         if (ret < 0) {
1029                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1030         } else if (!is_valid_ether_addr(sa.sa_data)) {
1031                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1032                           sa.sa_data);
1033                 eth_hw_addr_random(dev);
1034                 ether_addr_copy(sa.sa_data, dev->dev_addr);
1035                 ret = rtl8152_set_mac_address(dev, &sa);
1036                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1037                            sa.sa_data);
1038         } else {
1039                 if (tp->version == RTL_VER_01)
1040                         ether_addr_copy(dev->dev_addr, sa.sa_data);
1041                 else
1042                         ret = rtl8152_set_mac_address(dev, &sa);
1043         }
1044
1045         return ret;
1046 }
1047
1048 static void read_bulk_callback(struct urb *urb)
1049 {
1050         struct net_device *netdev;
1051         int status = urb->status;
1052         struct rx_agg *agg;
1053         struct r8152 *tp;
1054
1055         agg = urb->context;
1056         if (!agg)
1057                 return;
1058
1059         tp = agg->context;
1060         if (!tp)
1061                 return;
1062
1063         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1064                 return;
1065
1066         if (!test_bit(WORK_ENABLE, &tp->flags))
1067                 return;
1068
1069         netdev = tp->netdev;
1070
1071         /* When link down, the driver would cancel all bulks. */
1072         /* This avoid the re-submitting bulk */
1073         if (!netif_carrier_ok(netdev))
1074                 return;
1075
1076         usb_mark_last_busy(tp->udev);
1077
1078         switch (status) {
1079         case 0:
1080                 if (urb->actual_length < ETH_ZLEN)
1081                         break;
1082
1083                 spin_lock(&tp->rx_lock);
1084                 list_add_tail(&agg->list, &tp->rx_done);
1085                 spin_unlock(&tp->rx_lock);
1086                 napi_schedule(&tp->napi);
1087                 return;
1088         case -ESHUTDOWN:
1089                 set_bit(RTL8152_UNPLUG, &tp->flags);
1090                 netif_device_detach(tp->netdev);
1091                 return;
1092         case -ENOENT:
1093                 return; /* the urb is in unlink state */
1094         case -ETIME:
1095                 if (net_ratelimit())
1096                         netdev_warn(netdev, "maybe reset is needed?\n");
1097                 break;
1098         default:
1099                 if (net_ratelimit())
1100                         netdev_warn(netdev, "Rx status %d\n", status);
1101                 break;
1102         }
1103
1104         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1105 }
1106
1107 static void write_bulk_callback(struct urb *urb)
1108 {
1109         struct net_device_stats *stats;
1110         struct net_device *netdev;
1111         struct tx_agg *agg;
1112         struct r8152 *tp;
1113         int status = urb->status;
1114
1115         agg = urb->context;
1116         if (!agg)
1117                 return;
1118
1119         tp = agg->context;
1120         if (!tp)
1121                 return;
1122
1123         netdev = tp->netdev;
1124         stats = &netdev->stats;
1125         if (status) {
1126                 if (net_ratelimit())
1127                         netdev_warn(netdev, "Tx status %d\n", status);
1128                 stats->tx_errors += agg->skb_num;
1129         } else {
1130                 stats->tx_packets += agg->skb_num;
1131                 stats->tx_bytes += agg->skb_len;
1132         }
1133
1134         spin_lock(&tp->tx_lock);
1135         list_add_tail(&agg->list, &tp->tx_free);
1136         spin_unlock(&tp->tx_lock);
1137
1138         usb_autopm_put_interface_async(tp->intf);
1139
1140         if (!netif_carrier_ok(netdev))
1141                 return;
1142
1143         if (!test_bit(WORK_ENABLE, &tp->flags))
1144                 return;
1145
1146         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1147                 return;
1148
1149         if (!skb_queue_empty(&tp->tx_queue))
1150                 napi_schedule(&tp->napi);
1151 }
1152
1153 static void intr_callback(struct urb *urb)
1154 {
1155         struct r8152 *tp;
1156         __le16 *d;
1157         int status = urb->status;
1158         int res;
1159
1160         tp = urb->context;
1161         if (!tp)
1162                 return;
1163
1164         if (!test_bit(WORK_ENABLE, &tp->flags))
1165                 return;
1166
1167         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1168                 return;
1169
1170         switch (status) {
1171         case 0:                 /* success */
1172                 break;
1173         case -ECONNRESET:       /* unlink */
1174         case -ESHUTDOWN:
1175                 netif_device_detach(tp->netdev);
1176         case -ENOENT:
1177         case -EPROTO:
1178                 netif_info(tp, intr, tp->netdev,
1179                            "Stop submitting intr, status %d\n", status);
1180                 return;
1181         case -EOVERFLOW:
1182                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1183                 goto resubmit;
1184         /* -EPIPE:  should clear the halt */
1185         default:
1186                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1187                 goto resubmit;
1188         }
1189
1190         d = urb->transfer_buffer;
1191         if (INTR_LINK & __le16_to_cpu(d[0])) {
1192                 if (!netif_carrier_ok(tp->netdev)) {
1193                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1194                         schedule_delayed_work(&tp->schedule, 0);
1195                 }
1196         } else {
1197                 if (netif_carrier_ok(tp->netdev)) {
1198                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1199                         schedule_delayed_work(&tp->schedule, 0);
1200                 }
1201         }
1202
1203 resubmit:
1204         res = usb_submit_urb(urb, GFP_ATOMIC);
1205         if (res == -ENODEV) {
1206                 set_bit(RTL8152_UNPLUG, &tp->flags);
1207                 netif_device_detach(tp->netdev);
1208         } else if (res) {
1209                 netif_err(tp, intr, tp->netdev,
1210                           "can't resubmit intr, status %d\n", res);
1211         }
1212 }
1213
1214 static inline void *rx_agg_align(void *data)
1215 {
1216         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1217 }
1218
1219 static inline void *tx_agg_align(void *data)
1220 {
1221         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1222 }
1223
1224 static void free_all_mem(struct r8152 *tp)
1225 {
1226         int i;
1227
1228         for (i = 0; i < RTL8152_MAX_RX; i++) {
1229                 usb_free_urb(tp->rx_info[i].urb);
1230                 tp->rx_info[i].urb = NULL;
1231
1232                 kfree(tp->rx_info[i].buffer);
1233                 tp->rx_info[i].buffer = NULL;
1234                 tp->rx_info[i].head = NULL;
1235         }
1236
1237         for (i = 0; i < RTL8152_MAX_TX; i++) {
1238                 usb_free_urb(tp->tx_info[i].urb);
1239                 tp->tx_info[i].urb = NULL;
1240
1241                 kfree(tp->tx_info[i].buffer);
1242                 tp->tx_info[i].buffer = NULL;
1243                 tp->tx_info[i].head = NULL;
1244         }
1245
1246         usb_free_urb(tp->intr_urb);
1247         tp->intr_urb = NULL;
1248
1249         kfree(tp->intr_buff);
1250         tp->intr_buff = NULL;
1251 }
1252
1253 static int alloc_all_mem(struct r8152 *tp)
1254 {
1255         struct net_device *netdev = tp->netdev;
1256         struct usb_interface *intf = tp->intf;
1257         struct usb_host_interface *alt = intf->cur_altsetting;
1258         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1259         struct urb *urb;
1260         int node, i;
1261         u8 *buf;
1262
1263         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1264
1265         spin_lock_init(&tp->rx_lock);
1266         spin_lock_init(&tp->tx_lock);
1267         INIT_LIST_HEAD(&tp->tx_free);
1268         skb_queue_head_init(&tp->tx_queue);
1269         skb_queue_head_init(&tp->rx_queue);
1270
1271         for (i = 0; i < RTL8152_MAX_RX; i++) {
1272                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1273                 if (!buf)
1274                         goto err1;
1275
1276                 if (buf != rx_agg_align(buf)) {
1277                         kfree(buf);
1278                         buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1279                                            node);
1280                         if (!buf)
1281                                 goto err1;
1282                 }
1283
1284                 urb = usb_alloc_urb(0, GFP_KERNEL);
1285                 if (!urb) {
1286                         kfree(buf);
1287                         goto err1;
1288                 }
1289
1290                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1291                 tp->rx_info[i].context = tp;
1292                 tp->rx_info[i].urb = urb;
1293                 tp->rx_info[i].buffer = buf;
1294                 tp->rx_info[i].head = rx_agg_align(buf);
1295         }
1296
1297         for (i = 0; i < RTL8152_MAX_TX; i++) {
1298                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1299                 if (!buf)
1300                         goto err1;
1301
1302                 if (buf != tx_agg_align(buf)) {
1303                         kfree(buf);
1304                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1305                                            node);
1306                         if (!buf)
1307                                 goto err1;
1308                 }
1309
1310                 urb = usb_alloc_urb(0, GFP_KERNEL);
1311                 if (!urb) {
1312                         kfree(buf);
1313                         goto err1;
1314                 }
1315
1316                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1317                 tp->tx_info[i].context = tp;
1318                 tp->tx_info[i].urb = urb;
1319                 tp->tx_info[i].buffer = buf;
1320                 tp->tx_info[i].head = tx_agg_align(buf);
1321
1322                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1323         }
1324
1325         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1326         if (!tp->intr_urb)
1327                 goto err1;
1328
1329         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1330         if (!tp->intr_buff)
1331                 goto err1;
1332
1333         tp->intr_interval = (int)ep_intr->desc.bInterval;
1334         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1335                          tp->intr_buff, INTBUFSIZE, intr_callback,
1336                          tp, tp->intr_interval);
1337
1338         return 0;
1339
1340 err1:
1341         free_all_mem(tp);
1342         return -ENOMEM;
1343 }
1344
1345 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1346 {
1347         struct tx_agg *agg = NULL;
1348         unsigned long flags;
1349
1350         if (list_empty(&tp->tx_free))
1351                 return NULL;
1352
1353         spin_lock_irqsave(&tp->tx_lock, flags);
1354         if (!list_empty(&tp->tx_free)) {
1355                 struct list_head *cursor;
1356
1357                 cursor = tp->tx_free.next;
1358                 list_del_init(cursor);
1359                 agg = list_entry(cursor, struct tx_agg, list);
1360         }
1361         spin_unlock_irqrestore(&tp->tx_lock, flags);
1362
1363         return agg;
1364 }
1365
1366 /* r8152_csum_workaround()
1367  * The hw limites the value the transport offset. When the offset is out of the
1368  * range, calculate the checksum by sw.
1369  */
1370 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1371                                   struct sk_buff_head *list)
1372 {
1373         if (skb_shinfo(skb)->gso_size) {
1374                 netdev_features_t features = tp->netdev->features;
1375                 struct sk_buff_head seg_list;
1376                 struct sk_buff *segs, *nskb;
1377
1378                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1379                 segs = skb_gso_segment(skb, features);
1380                 if (IS_ERR(segs) || !segs)
1381                         goto drop;
1382
1383                 __skb_queue_head_init(&seg_list);
1384
1385                 do {
1386                         nskb = segs;
1387                         segs = segs->next;
1388                         nskb->next = NULL;
1389                         __skb_queue_tail(&seg_list, nskb);
1390                 } while (segs);
1391
1392                 skb_queue_splice(&seg_list, list);
1393                 dev_kfree_skb(skb);
1394         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1395                 if (skb_checksum_help(skb) < 0)
1396                         goto drop;
1397
1398                 __skb_queue_head(list, skb);
1399         } else {
1400                 struct net_device_stats *stats;
1401
1402 drop:
1403                 stats = &tp->netdev->stats;
1404                 stats->tx_dropped++;
1405                 dev_kfree_skb(skb);
1406         }
1407 }
1408
1409 /* msdn_giant_send_check()
1410  * According to the document of microsoft, the TCP Pseudo Header excludes the
1411  * packet length for IPv6 TCP large packets.
1412  */
1413 static int msdn_giant_send_check(struct sk_buff *skb)
1414 {
1415         const struct ipv6hdr *ipv6h;
1416         struct tcphdr *th;
1417         int ret;
1418
1419         ret = skb_cow_head(skb, 0);
1420         if (ret)
1421                 return ret;
1422
1423         ipv6h = ipv6_hdr(skb);
1424         th = tcp_hdr(skb);
1425
1426         th->check = 0;
1427         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1428
1429         return ret;
1430 }
1431
1432 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1433 {
1434         if (skb_vlan_tag_present(skb)) {
1435                 u32 opts2;
1436
1437                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1438                 desc->opts2 |= cpu_to_le32(opts2);
1439         }
1440 }
1441
1442 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1443 {
1444         u32 opts2 = le32_to_cpu(desc->opts2);
1445
1446         if (opts2 & RX_VLAN_TAG)
1447                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1448                                        swab16(opts2 & 0xffff));
1449 }
1450
1451 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1452                          struct sk_buff *skb, u32 len, u32 transport_offset)
1453 {
1454         u32 mss = skb_shinfo(skb)->gso_size;
1455         u32 opts1, opts2 = 0;
1456         int ret = TX_CSUM_SUCCESS;
1457
1458         WARN_ON_ONCE(len > TX_LEN_MAX);
1459
1460         opts1 = len | TX_FS | TX_LS;
1461
1462         if (mss) {
1463                 if (transport_offset > GTTCPHO_MAX) {
1464                         netif_warn(tp, tx_err, tp->netdev,
1465                                    "Invalid transport offset 0x%x for TSO\n",
1466                                    transport_offset);
1467                         ret = TX_CSUM_TSO;
1468                         goto unavailable;
1469                 }
1470
1471                 switch (vlan_get_protocol(skb)) {
1472                 case htons(ETH_P_IP):
1473                         opts1 |= GTSENDV4;
1474                         break;
1475
1476                 case htons(ETH_P_IPV6):
1477                         if (msdn_giant_send_check(skb)) {
1478                                 ret = TX_CSUM_TSO;
1479                                 goto unavailable;
1480                         }
1481                         opts1 |= GTSENDV6;
1482                         break;
1483
1484                 default:
1485                         WARN_ON_ONCE(1);
1486                         break;
1487                 }
1488
1489                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1490                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1491         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1492                 u8 ip_protocol;
1493
1494                 if (transport_offset > TCPHO_MAX) {
1495                         netif_warn(tp, tx_err, tp->netdev,
1496                                    "Invalid transport offset 0x%x\n",
1497                                    transport_offset);
1498                         ret = TX_CSUM_NONE;
1499                         goto unavailable;
1500                 }
1501
1502                 switch (vlan_get_protocol(skb)) {
1503                 case htons(ETH_P_IP):
1504                         opts2 |= IPV4_CS;
1505                         ip_protocol = ip_hdr(skb)->protocol;
1506                         break;
1507
1508                 case htons(ETH_P_IPV6):
1509                         opts2 |= IPV6_CS;
1510                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1511                         break;
1512
1513                 default:
1514                         ip_protocol = IPPROTO_RAW;
1515                         break;
1516                 }
1517
1518                 if (ip_protocol == IPPROTO_TCP)
1519                         opts2 |= TCP_CS;
1520                 else if (ip_protocol == IPPROTO_UDP)
1521                         opts2 |= UDP_CS;
1522                 else
1523                         WARN_ON_ONCE(1);
1524
1525                 opts2 |= transport_offset << TCPHO_SHIFT;
1526         }
1527
1528         desc->opts2 = cpu_to_le32(opts2);
1529         desc->opts1 = cpu_to_le32(opts1);
1530
1531 unavailable:
1532         return ret;
1533 }
1534
1535 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1536 {
1537         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1538         int remain, ret;
1539         u8 *tx_data;
1540
1541         __skb_queue_head_init(&skb_head);
1542         spin_lock(&tx_queue->lock);
1543         skb_queue_splice_init(tx_queue, &skb_head);
1544         spin_unlock(&tx_queue->lock);
1545
1546         tx_data = agg->head;
1547         agg->skb_num = 0;
1548         agg->skb_len = 0;
1549         remain = agg_buf_sz;
1550
1551         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1552                 struct tx_desc *tx_desc;
1553                 struct sk_buff *skb;
1554                 unsigned int len;
1555                 u32 offset;
1556
1557                 skb = __skb_dequeue(&skb_head);
1558                 if (!skb)
1559                         break;
1560
1561                 len = skb->len + sizeof(*tx_desc);
1562
1563                 if (len > remain) {
1564                         __skb_queue_head(&skb_head, skb);
1565                         break;
1566                 }
1567
1568                 tx_data = tx_agg_align(tx_data);
1569                 tx_desc = (struct tx_desc *)tx_data;
1570
1571                 offset = (u32)skb_transport_offset(skb);
1572
1573                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1574                         r8152_csum_workaround(tp, skb, &skb_head);
1575                         continue;
1576                 }
1577
1578                 rtl_tx_vlan_tag(tx_desc, skb);
1579
1580                 tx_data += sizeof(*tx_desc);
1581
1582                 len = skb->len;
1583                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1584                         struct net_device_stats *stats = &tp->netdev->stats;
1585
1586                         stats->tx_dropped++;
1587                         dev_kfree_skb_any(skb);
1588                         tx_data -= sizeof(*tx_desc);
1589                         continue;
1590                 }
1591
1592                 tx_data += len;
1593                 agg->skb_len += len;
1594                 agg->skb_num++;
1595
1596                 dev_kfree_skb_any(skb);
1597
1598                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1599         }
1600
1601         if (!skb_queue_empty(&skb_head)) {
1602                 spin_lock(&tx_queue->lock);
1603                 skb_queue_splice(&skb_head, tx_queue);
1604                 spin_unlock(&tx_queue->lock);
1605         }
1606
1607         netif_tx_lock(tp->netdev);
1608
1609         if (netif_queue_stopped(tp->netdev) &&
1610             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1611                 netif_wake_queue(tp->netdev);
1612
1613         netif_tx_unlock(tp->netdev);
1614
1615         ret = usb_autopm_get_interface_async(tp->intf);
1616         if (ret < 0)
1617                 goto out_tx_fill;
1618
1619         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1620                           agg->head, (int)(tx_data - (u8 *)agg->head),
1621                           (usb_complete_t)write_bulk_callback, agg);
1622
1623         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1624         if (ret < 0)
1625                 usb_autopm_put_interface_async(tp->intf);
1626
1627 out_tx_fill:
1628         return ret;
1629 }
1630
1631 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1632 {
1633         u8 checksum = CHECKSUM_NONE;
1634         u32 opts2, opts3;
1635
1636         if (tp->version == RTL_VER_01)
1637                 goto return_result;
1638
1639         opts2 = le32_to_cpu(rx_desc->opts2);
1640         opts3 = le32_to_cpu(rx_desc->opts3);
1641
1642         if (opts2 & RD_IPV4_CS) {
1643                 if (opts3 & IPF)
1644                         checksum = CHECKSUM_NONE;
1645                 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1646                         checksum = CHECKSUM_NONE;
1647                 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1648                         checksum = CHECKSUM_NONE;
1649                 else
1650                         checksum = CHECKSUM_UNNECESSARY;
1651         } else if (RD_IPV6_CS) {
1652                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1653                         checksum = CHECKSUM_UNNECESSARY;
1654                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1655                         checksum = CHECKSUM_UNNECESSARY;
1656         }
1657
1658 return_result:
1659         return checksum;
1660 }
1661
1662 static int rx_bottom(struct r8152 *tp, int budget)
1663 {
1664         unsigned long flags;
1665         struct list_head *cursor, *next, rx_queue;
1666         int ret = 0, work_done = 0;
1667
1668         if (!skb_queue_empty(&tp->rx_queue)) {
1669                 while (work_done < budget) {
1670                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1671                         struct net_device *netdev = tp->netdev;
1672                         struct net_device_stats *stats = &netdev->stats;
1673                         unsigned int pkt_len;
1674
1675                         if (!skb)
1676                                 break;
1677
1678                         pkt_len = skb->len;
1679                         napi_gro_receive(&tp->napi, skb);
1680                         work_done++;
1681                         stats->rx_packets++;
1682                         stats->rx_bytes += pkt_len;
1683                 }
1684         }
1685
1686         if (list_empty(&tp->rx_done))
1687                 goto out1;
1688
1689         INIT_LIST_HEAD(&rx_queue);
1690         spin_lock_irqsave(&tp->rx_lock, flags);
1691         list_splice_init(&tp->rx_done, &rx_queue);
1692         spin_unlock_irqrestore(&tp->rx_lock, flags);
1693
1694         list_for_each_safe(cursor, next, &rx_queue) {
1695                 struct rx_desc *rx_desc;
1696                 struct rx_agg *agg;
1697                 int len_used = 0;
1698                 struct urb *urb;
1699                 u8 *rx_data;
1700
1701                 list_del_init(cursor);
1702
1703                 agg = list_entry(cursor, struct rx_agg, list);
1704                 urb = agg->urb;
1705                 if (urb->actual_length < ETH_ZLEN)
1706                         goto submit;
1707
1708                 rx_desc = agg->head;
1709                 rx_data = agg->head;
1710                 len_used += sizeof(struct rx_desc);
1711
1712                 while (urb->actual_length > len_used) {
1713                         struct net_device *netdev = tp->netdev;
1714                         struct net_device_stats *stats = &netdev->stats;
1715                         unsigned int pkt_len;
1716                         struct sk_buff *skb;
1717
1718                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1719                         if (pkt_len < ETH_ZLEN)
1720                                 break;
1721
1722                         len_used += pkt_len;
1723                         if (urb->actual_length < len_used)
1724                                 break;
1725
1726                         pkt_len -= CRC_SIZE;
1727                         rx_data += sizeof(struct rx_desc);
1728
1729                         skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1730                         if (!skb) {
1731                                 stats->rx_dropped++;
1732                                 goto find_next_rx;
1733                         }
1734
1735                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1736                         memcpy(skb->data, rx_data, pkt_len);
1737                         skb_put(skb, pkt_len);
1738                         skb->protocol = eth_type_trans(skb, netdev);
1739                         rtl_rx_vlan_tag(rx_desc, skb);
1740                         if (work_done < budget) {
1741                                 napi_gro_receive(&tp->napi, skb);
1742                                 work_done++;
1743                                 stats->rx_packets++;
1744                                 stats->rx_bytes += pkt_len;
1745                         } else {
1746                                 __skb_queue_tail(&tp->rx_queue, skb);
1747                         }
1748
1749 find_next_rx:
1750                         rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1751                         rx_desc = (struct rx_desc *)rx_data;
1752                         len_used = (int)(rx_data - (u8 *)agg->head);
1753                         len_used += sizeof(struct rx_desc);
1754                 }
1755
1756 submit:
1757                 if (!ret) {
1758                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1759                 } else {
1760                         urb->actual_length = 0;
1761                         list_add_tail(&agg->list, next);
1762                 }
1763         }
1764
1765         if (!list_empty(&rx_queue)) {
1766                 spin_lock_irqsave(&tp->rx_lock, flags);
1767                 list_splice_tail(&rx_queue, &tp->rx_done);
1768                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1769         }
1770
1771 out1:
1772         return work_done;
1773 }
1774
1775 static void tx_bottom(struct r8152 *tp)
1776 {
1777         int res;
1778
1779         do {
1780                 struct tx_agg *agg;
1781
1782                 if (skb_queue_empty(&tp->tx_queue))
1783                         break;
1784
1785                 agg = r8152_get_tx_agg(tp);
1786                 if (!agg)
1787                         break;
1788
1789                 res = r8152_tx_agg_fill(tp, agg);
1790                 if (res) {
1791                         struct net_device *netdev = tp->netdev;
1792
1793                         if (res == -ENODEV) {
1794                                 set_bit(RTL8152_UNPLUG, &tp->flags);
1795                                 netif_device_detach(netdev);
1796                         } else {
1797                                 struct net_device_stats *stats = &netdev->stats;
1798                                 unsigned long flags;
1799
1800                                 netif_warn(tp, tx_err, netdev,
1801                                            "failed tx_urb %d\n", res);
1802                                 stats->tx_dropped += agg->skb_num;
1803
1804                                 spin_lock_irqsave(&tp->tx_lock, flags);
1805                                 list_add_tail(&agg->list, &tp->tx_free);
1806                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
1807                         }
1808                 }
1809         } while (res == 0);
1810 }
1811
1812 static void bottom_half(struct r8152 *tp)
1813 {
1814         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1815                 return;
1816
1817         if (!test_bit(WORK_ENABLE, &tp->flags))
1818                 return;
1819
1820         /* When link down, the driver would cancel all bulks. */
1821         /* This avoid the re-submitting bulk */
1822         if (!netif_carrier_ok(tp->netdev))
1823                 return;
1824
1825         clear_bit(SCHEDULE_NAPI, &tp->flags);
1826
1827         tx_bottom(tp);
1828 }
1829
1830 static int r8152_poll(struct napi_struct *napi, int budget)
1831 {
1832         struct r8152 *tp = container_of(napi, struct r8152, napi);
1833         int work_done;
1834
1835         work_done = rx_bottom(tp, budget);
1836         bottom_half(tp);
1837
1838         if (work_done < budget) {
1839                 napi_complete(napi);
1840                 if (!list_empty(&tp->rx_done))
1841                         napi_schedule(napi);
1842         }
1843
1844         return work_done;
1845 }
1846
1847 static
1848 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1849 {
1850         int ret;
1851
1852         /* The rx would be stopped, so skip submitting */
1853         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1854             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1855                 return 0;
1856
1857         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1858                           agg->head, agg_buf_sz,
1859                           (usb_complete_t)read_bulk_callback, agg);
1860
1861         ret = usb_submit_urb(agg->urb, mem_flags);
1862         if (ret == -ENODEV) {
1863                 set_bit(RTL8152_UNPLUG, &tp->flags);
1864                 netif_device_detach(tp->netdev);
1865         } else if (ret) {
1866                 struct urb *urb = agg->urb;
1867                 unsigned long flags;
1868
1869                 urb->actual_length = 0;
1870                 spin_lock_irqsave(&tp->rx_lock, flags);
1871                 list_add_tail(&agg->list, &tp->rx_done);
1872                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1873
1874                 netif_err(tp, rx_err, tp->netdev,
1875                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1876
1877                 napi_schedule(&tp->napi);
1878         }
1879
1880         return ret;
1881 }
1882
1883 static void rtl_drop_queued_tx(struct r8152 *tp)
1884 {
1885         struct net_device_stats *stats = &tp->netdev->stats;
1886         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1887         struct sk_buff *skb;
1888
1889         if (skb_queue_empty(tx_queue))
1890                 return;
1891
1892         __skb_queue_head_init(&skb_head);
1893         spin_lock_bh(&tx_queue->lock);
1894         skb_queue_splice_init(tx_queue, &skb_head);
1895         spin_unlock_bh(&tx_queue->lock);
1896
1897         while ((skb = __skb_dequeue(&skb_head))) {
1898                 dev_kfree_skb(skb);
1899                 stats->tx_dropped++;
1900         }
1901 }
1902
1903 static void rtl8152_tx_timeout(struct net_device *netdev)
1904 {
1905         struct r8152 *tp = netdev_priv(netdev);
1906         int i;
1907
1908         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1909         for (i = 0; i < RTL8152_MAX_TX; i++)
1910                 usb_unlink_urb(tp->tx_info[i].urb);
1911 }
1912
1913 static void rtl8152_set_rx_mode(struct net_device *netdev)
1914 {
1915         struct r8152 *tp = netdev_priv(netdev);
1916
1917         if (netif_carrier_ok(netdev)) {
1918                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1919                 schedule_delayed_work(&tp->schedule, 0);
1920         }
1921 }
1922
1923 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1924 {
1925         struct r8152 *tp = netdev_priv(netdev);
1926         u32 mc_filter[2];       /* Multicast hash filter */
1927         __le32 tmp[2];
1928         u32 ocp_data;
1929
1930         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1931         netif_stop_queue(netdev);
1932         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1933         ocp_data &= ~RCR_ACPT_ALL;
1934         ocp_data |= RCR_AB | RCR_APM;
1935
1936         if (netdev->flags & IFF_PROMISC) {
1937                 /* Unconditionally log net taps. */
1938                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1939                 ocp_data |= RCR_AM | RCR_AAP;
1940                 mc_filter[1] = 0xffffffff;
1941                 mc_filter[0] = 0xffffffff;
1942         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1943                    (netdev->flags & IFF_ALLMULTI)) {
1944                 /* Too many to filter perfectly -- accept all multicasts. */
1945                 ocp_data |= RCR_AM;
1946                 mc_filter[1] = 0xffffffff;
1947                 mc_filter[0] = 0xffffffff;
1948         } else {
1949                 struct netdev_hw_addr *ha;
1950
1951                 mc_filter[1] = 0;
1952                 mc_filter[0] = 0;
1953                 netdev_for_each_mc_addr(ha, netdev) {
1954                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1955
1956                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1957                         ocp_data |= RCR_AM;
1958                 }
1959         }
1960
1961         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1962         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1963
1964         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1965         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1966         netif_wake_queue(netdev);
1967 }
1968
1969 static netdev_features_t
1970 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1971                        netdev_features_t features)
1972 {
1973         u32 mss = skb_shinfo(skb)->gso_size;
1974         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1975         int offset = skb_transport_offset(skb);
1976
1977         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
1978                 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
1979         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1980                 features &= ~NETIF_F_GSO_MASK;
1981
1982         return features;
1983 }
1984
1985 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1986                                       struct net_device *netdev)
1987 {
1988         struct r8152 *tp = netdev_priv(netdev);
1989
1990         skb_tx_timestamp(skb);
1991
1992         skb_queue_tail(&tp->tx_queue, skb);
1993
1994         if (!list_empty(&tp->tx_free)) {
1995                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1996                         set_bit(SCHEDULE_NAPI, &tp->flags);
1997                         schedule_delayed_work(&tp->schedule, 0);
1998                 } else {
1999                         usb_mark_last_busy(tp->udev);
2000                         napi_schedule(&tp->napi);
2001                 }
2002         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2003                 netif_stop_queue(netdev);
2004         }
2005
2006         return NETDEV_TX_OK;
2007 }
2008
2009 static void r8152b_reset_packet_filter(struct r8152 *tp)
2010 {
2011         u32     ocp_data;
2012
2013         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2014         ocp_data &= ~FMC_FCR_MCU_EN;
2015         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2016         ocp_data |= FMC_FCR_MCU_EN;
2017         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2018 }
2019
2020 static void rtl8152_nic_reset(struct r8152 *tp)
2021 {
2022         int     i;
2023
2024         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2025
2026         for (i = 0; i < 1000; i++) {
2027                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2028                         break;
2029                 usleep_range(100, 400);
2030         }
2031 }
2032
2033 static void set_tx_qlen(struct r8152 *tp)
2034 {
2035         struct net_device *netdev = tp->netdev;
2036
2037         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2038                                     sizeof(struct tx_desc));
2039 }
2040
2041 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2042 {
2043         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2044 }
2045
2046 static void rtl_set_eee_plus(struct r8152 *tp)
2047 {
2048         u32 ocp_data;
2049         u8 speed;
2050
2051         speed = rtl8152_get_speed(tp);
2052         if (speed & _10bps) {
2053                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2054                 ocp_data |= EEEP_CR_EEEP_TX;
2055                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2056         } else {
2057                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2058                 ocp_data &= ~EEEP_CR_EEEP_TX;
2059                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2060         }
2061 }
2062
2063 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2064 {
2065         u32 ocp_data;
2066
2067         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2068         if (enable)
2069                 ocp_data |= RXDY_GATED_EN;
2070         else
2071                 ocp_data &= ~RXDY_GATED_EN;
2072         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2073 }
2074
2075 static int rtl_start_rx(struct r8152 *tp)
2076 {
2077         int i, ret = 0;
2078
2079         napi_disable(&tp->napi);
2080         INIT_LIST_HEAD(&tp->rx_done);
2081         for (i = 0; i < RTL8152_MAX_RX; i++) {
2082                 INIT_LIST_HEAD(&tp->rx_info[i].list);
2083                 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2084                 if (ret)
2085                         break;
2086         }
2087         napi_enable(&tp->napi);
2088
2089         if (ret && ++i < RTL8152_MAX_RX) {
2090                 struct list_head rx_queue;
2091                 unsigned long flags;
2092
2093                 INIT_LIST_HEAD(&rx_queue);
2094
2095                 do {
2096                         struct rx_agg *agg = &tp->rx_info[i++];
2097                         struct urb *urb = agg->urb;
2098
2099                         urb->actual_length = 0;
2100                         list_add_tail(&agg->list, &rx_queue);
2101                 } while (i < RTL8152_MAX_RX);
2102
2103                 spin_lock_irqsave(&tp->rx_lock, flags);
2104                 list_splice_tail(&rx_queue, &tp->rx_done);
2105                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2106         }
2107
2108         return ret;
2109 }
2110
2111 static int rtl_stop_rx(struct r8152 *tp)
2112 {
2113         int i;
2114
2115         for (i = 0; i < RTL8152_MAX_RX; i++)
2116                 usb_kill_urb(tp->rx_info[i].urb);
2117
2118         while (!skb_queue_empty(&tp->rx_queue))
2119                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2120
2121         return 0;
2122 }
2123
2124 static int rtl_enable(struct r8152 *tp)
2125 {
2126         u32 ocp_data;
2127
2128         r8152b_reset_packet_filter(tp);
2129
2130         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2131         ocp_data |= CR_RE | CR_TE;
2132         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2133
2134         rxdy_gated_en(tp, false);
2135
2136         return 0;
2137 }
2138
2139 static int rtl8152_enable(struct r8152 *tp)
2140 {
2141         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2142                 return -ENODEV;
2143
2144         set_tx_qlen(tp);
2145         rtl_set_eee_plus(tp);
2146
2147         return rtl_enable(tp);
2148 }
2149
2150 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2151 {
2152         u32 ocp_data = tp->coalesce / 8;
2153
2154         ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2155 }
2156
2157 static void r8153_set_rx_early_size(struct r8152 *tp)
2158 {
2159         u32 mtu = tp->netdev->mtu;
2160         u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
2161
2162         ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
2163 }
2164
2165 static int rtl8153_enable(struct r8152 *tp)
2166 {
2167         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2168                 return -ENODEV;
2169
2170         set_tx_qlen(tp);
2171         rtl_set_eee_plus(tp);
2172         r8153_set_rx_early_timeout(tp);
2173         r8153_set_rx_early_size(tp);
2174
2175         return rtl_enable(tp);
2176 }
2177
2178 static void rtl_disable(struct r8152 *tp)
2179 {
2180         u32 ocp_data;
2181         int i;
2182
2183         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2184                 rtl_drop_queued_tx(tp);
2185                 return;
2186         }
2187
2188         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2189         ocp_data &= ~RCR_ACPT_ALL;
2190         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2191
2192         rtl_drop_queued_tx(tp);
2193
2194         for (i = 0; i < RTL8152_MAX_TX; i++)
2195                 usb_kill_urb(tp->tx_info[i].urb);
2196
2197         rxdy_gated_en(tp, true);
2198
2199         for (i = 0; i < 1000; i++) {
2200                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2201                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2202                         break;
2203                 usleep_range(1000, 2000);
2204         }
2205
2206         for (i = 0; i < 1000; i++) {
2207                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2208                         break;
2209                 usleep_range(1000, 2000);
2210         }
2211
2212         rtl_stop_rx(tp);
2213
2214         rtl8152_nic_reset(tp);
2215 }
2216
2217 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2218 {
2219         u32 ocp_data;
2220
2221         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2222         if (enable)
2223                 ocp_data |= POWER_CUT;
2224         else
2225                 ocp_data &= ~POWER_CUT;
2226         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2227
2228         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2229         ocp_data &= ~RESUME_INDICATE;
2230         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2231 }
2232
2233 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2234 {
2235         u32 ocp_data;
2236
2237         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2238         if (enable)
2239                 ocp_data |= CPCR_RX_VLAN;
2240         else
2241                 ocp_data &= ~CPCR_RX_VLAN;
2242         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2243 }
2244
2245 static int rtl8152_set_features(struct net_device *dev,
2246                                 netdev_features_t features)
2247 {
2248         netdev_features_t changed = features ^ dev->features;
2249         struct r8152 *tp = netdev_priv(dev);
2250         int ret;
2251
2252         ret = usb_autopm_get_interface(tp->intf);
2253         if (ret < 0)
2254                 goto out;
2255
2256         mutex_lock(&tp->control);
2257
2258         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2259                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2260                         rtl_rx_vlan_en(tp, true);
2261                 else
2262                         rtl_rx_vlan_en(tp, false);
2263         }
2264
2265         mutex_unlock(&tp->control);
2266
2267         usb_autopm_put_interface(tp->intf);
2268
2269 out:
2270         return ret;
2271 }
2272
2273 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2274
2275 static u32 __rtl_get_wol(struct r8152 *tp)
2276 {
2277         u32 ocp_data;
2278         u32 wolopts = 0;
2279
2280         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2281         if (!(ocp_data & LAN_WAKE_EN))
2282                 return 0;
2283
2284         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2285         if (ocp_data & LINK_ON_WAKE_EN)
2286                 wolopts |= WAKE_PHY;
2287
2288         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2289         if (ocp_data & UWF_EN)
2290                 wolopts |= WAKE_UCAST;
2291         if (ocp_data & BWF_EN)
2292                 wolopts |= WAKE_BCAST;
2293         if (ocp_data & MWF_EN)
2294                 wolopts |= WAKE_MCAST;
2295
2296         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2297         if (ocp_data & MAGIC_EN)
2298                 wolopts |= WAKE_MAGIC;
2299
2300         return wolopts;
2301 }
2302
2303 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2304 {
2305         u32 ocp_data;
2306
2307         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2308
2309         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2310         ocp_data &= ~LINK_ON_WAKE_EN;
2311         if (wolopts & WAKE_PHY)
2312                 ocp_data |= LINK_ON_WAKE_EN;
2313         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2314
2315         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2316         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2317         if (wolopts & WAKE_UCAST)
2318                 ocp_data |= UWF_EN;
2319         if (wolopts & WAKE_BCAST)
2320                 ocp_data |= BWF_EN;
2321         if (wolopts & WAKE_MCAST)
2322                 ocp_data |= MWF_EN;
2323         if (wolopts & WAKE_ANY)
2324                 ocp_data |= LAN_WAKE_EN;
2325         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2326
2327         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2328
2329         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2330         ocp_data &= ~MAGIC_EN;
2331         if (wolopts & WAKE_MAGIC)
2332                 ocp_data |= MAGIC_EN;
2333         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2334
2335         if (wolopts & WAKE_ANY)
2336                 device_set_wakeup_enable(&tp->udev->dev, true);
2337         else
2338                 device_set_wakeup_enable(&tp->udev->dev, false);
2339 }
2340
2341 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2342 {
2343         if (enable) {
2344                 u32 ocp_data;
2345
2346                 __rtl_set_wol(tp, WAKE_ANY);
2347
2348                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2349
2350                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2351                 ocp_data |= LINK_OFF_WAKE_EN;
2352                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2353
2354                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2355         } else {
2356                 __rtl_set_wol(tp, tp->saved_wolopts);
2357         }
2358 }
2359
2360 static void rtl_phy_reset(struct r8152 *tp)
2361 {
2362         u16 data;
2363         int i;
2364
2365         clear_bit(PHY_RESET, &tp->flags);
2366
2367         data = r8152_mdio_read(tp, MII_BMCR);
2368
2369         /* don't reset again before the previous one complete */
2370         if (data & BMCR_RESET)
2371                 return;
2372
2373         data |= BMCR_RESET;
2374         r8152_mdio_write(tp, MII_BMCR, data);
2375
2376         for (i = 0; i < 50; i++) {
2377                 msleep(20);
2378                 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2379                         break;
2380         }
2381 }
2382
2383 static void r8153_teredo_off(struct r8152 *tp)
2384 {
2385         u32 ocp_data;
2386
2387         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2388         ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2389         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2390
2391         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2392         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2393         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2394 }
2395
2396 static void r8152b_disable_aldps(struct r8152 *tp)
2397 {
2398         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2399         msleep(20);
2400 }
2401
2402 static inline void r8152b_enable_aldps(struct r8152 *tp)
2403 {
2404         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2405                                             LINKENA | DIS_SDSAVE);
2406 }
2407
2408 static void rtl8152_disable(struct r8152 *tp)
2409 {
2410         r8152b_disable_aldps(tp);
2411         rtl_disable(tp);
2412         r8152b_enable_aldps(tp);
2413 }
2414
2415 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2416 {
2417         u16 data;
2418
2419         data = r8152_mdio_read(tp, MII_BMCR);
2420         if (data & BMCR_PDOWN) {
2421                 data &= ~BMCR_PDOWN;
2422                 r8152_mdio_write(tp, MII_BMCR, data);
2423         }
2424
2425         set_bit(PHY_RESET, &tp->flags);
2426 }
2427
2428 static void r8152b_exit_oob(struct r8152 *tp)
2429 {
2430         u32 ocp_data;
2431         int i;
2432
2433         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2434         ocp_data &= ~RCR_ACPT_ALL;
2435         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2436
2437         rxdy_gated_en(tp, true);
2438         r8153_teredo_off(tp);
2439         r8152b_hw_phy_cfg(tp);
2440
2441         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2442         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2443
2444         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2445         ocp_data &= ~NOW_IS_OOB;
2446         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2447
2448         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2449         ocp_data &= ~MCU_BORW_EN;
2450         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2451
2452         for (i = 0; i < 1000; i++) {
2453                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2454                 if (ocp_data & LINK_LIST_READY)
2455                         break;
2456                 usleep_range(1000, 2000);
2457         }
2458
2459         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2460         ocp_data |= RE_INIT_LL;
2461         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2462
2463         for (i = 0; i < 1000; i++) {
2464                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2465                 if (ocp_data & LINK_LIST_READY)
2466                         break;
2467                 usleep_range(1000, 2000);
2468         }
2469
2470         rtl8152_nic_reset(tp);
2471
2472         /* rx share fifo credit full threshold */
2473         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2474
2475         if (tp->udev->speed == USB_SPEED_FULL ||
2476             tp->udev->speed == USB_SPEED_LOW) {
2477                 /* rx share fifo credit near full threshold */
2478                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2479                                 RXFIFO_THR2_FULL);
2480                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2481                                 RXFIFO_THR3_FULL);
2482         } else {
2483                 /* rx share fifo credit near full threshold */
2484                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2485                                 RXFIFO_THR2_HIGH);
2486                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2487                                 RXFIFO_THR3_HIGH);
2488         }
2489
2490         /* TX share fifo free credit full threshold */
2491         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2492
2493         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2494         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2495         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2496                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2497
2498         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2499
2500         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2501
2502         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2503         ocp_data |= TCR0_AUTO_FIFO;
2504         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2505 }
2506
2507 static void r8152b_enter_oob(struct r8152 *tp)
2508 {
2509         u32 ocp_data;
2510         int i;
2511
2512         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2513         ocp_data &= ~NOW_IS_OOB;
2514         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2515
2516         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2517         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2518         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2519
2520         rtl_disable(tp);
2521
2522         for (i = 0; i < 1000; i++) {
2523                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2524                 if (ocp_data & LINK_LIST_READY)
2525                         break;
2526                 usleep_range(1000, 2000);
2527         }
2528
2529         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2530         ocp_data |= RE_INIT_LL;
2531         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2532
2533         for (i = 0; i < 1000; i++) {
2534                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2535                 if (ocp_data & LINK_LIST_READY)
2536                         break;
2537                 usleep_range(1000, 2000);
2538         }
2539
2540         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2541
2542         rtl_rx_vlan_en(tp, true);
2543
2544         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2545         ocp_data |= ALDPS_PROXY_MODE;
2546         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2547
2548         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2549         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2550         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2551
2552         rxdy_gated_en(tp, false);
2553
2554         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2555         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2556         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2557 }
2558
2559 static void r8153_hw_phy_cfg(struct r8152 *tp)
2560 {
2561         u32 ocp_data;
2562         u16 data;
2563
2564         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
2565             tp->version == RTL_VER_05)
2566                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2567
2568         data = r8152_mdio_read(tp, MII_BMCR);
2569         if (data & BMCR_PDOWN) {
2570                 data &= ~BMCR_PDOWN;
2571                 r8152_mdio_write(tp, MII_BMCR, data);
2572         }
2573
2574         if (tp->version == RTL_VER_03) {
2575                 data = ocp_reg_read(tp, OCP_EEE_CFG);
2576                 data &= ~CTAP_SHORT_EN;
2577                 ocp_reg_write(tp, OCP_EEE_CFG, data);
2578         }
2579
2580         data = ocp_reg_read(tp, OCP_POWER_CFG);
2581         data |= EEE_CLKDIV_EN;
2582         ocp_reg_write(tp, OCP_POWER_CFG, data);
2583
2584         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2585         data |= EN_10M_BGOFF;
2586         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2587         data = ocp_reg_read(tp, OCP_POWER_CFG);
2588         data |= EN_10M_PLLOFF;
2589         ocp_reg_write(tp, OCP_POWER_CFG, data);
2590         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
2591
2592         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2593         ocp_data |= PFM_PWM_SWITCH;
2594         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2595
2596         /* Enable LPF corner auto tune */
2597         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
2598
2599         /* Adjust 10M Amplitude */
2600         sram_write(tp, SRAM_10M_AMP1, 0x00af);
2601         sram_write(tp, SRAM_10M_AMP2, 0x0208);
2602
2603         set_bit(PHY_RESET, &tp->flags);
2604 }
2605
2606 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2607 {
2608         u8 u1u2[8];
2609
2610         if (enable)
2611                 memset(u1u2, 0xff, sizeof(u1u2));
2612         else
2613                 memset(u1u2, 0x00, sizeof(u1u2));
2614
2615         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2616 }
2617
2618 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2619 {
2620         u32 ocp_data;
2621
2622         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2623         if (enable)
2624                 ocp_data |= U2P3_ENABLE;
2625         else
2626                 ocp_data &= ~U2P3_ENABLE;
2627         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2628 }
2629
2630 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2631 {
2632         u32 ocp_data;
2633
2634         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2635         if (enable)
2636                 ocp_data |= PWR_EN | PHASE2_EN;
2637         else
2638                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2639         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2640
2641         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2642         ocp_data &= ~PCUT_STATUS;
2643         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2644 }
2645
2646 static void r8153_first_init(struct r8152 *tp)
2647 {
2648         u32 ocp_data;
2649         int i;
2650
2651         rxdy_gated_en(tp, true);
2652         r8153_teredo_off(tp);
2653
2654         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2655         ocp_data &= ~RCR_ACPT_ALL;
2656         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2657
2658         r8153_hw_phy_cfg(tp);
2659
2660         rtl8152_nic_reset(tp);
2661
2662         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2663         ocp_data &= ~NOW_IS_OOB;
2664         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2665
2666         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2667         ocp_data &= ~MCU_BORW_EN;
2668         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2669
2670         for (i = 0; i < 1000; i++) {
2671                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2672                 if (ocp_data & LINK_LIST_READY)
2673                         break;
2674                 usleep_range(1000, 2000);
2675         }
2676
2677         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2678         ocp_data |= RE_INIT_LL;
2679         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2680
2681         for (i = 0; i < 1000; i++) {
2682                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2683                 if (ocp_data & LINK_LIST_READY)
2684                         break;
2685                 usleep_range(1000, 2000);
2686         }
2687
2688         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2689
2690         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2691         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2692
2693         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2694         ocp_data |= TCR0_AUTO_FIFO;
2695         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2696
2697         rtl8152_nic_reset(tp);
2698
2699         /* rx share fifo credit full threshold */
2700         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2701         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2702         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2703         /* TX share fifo free credit full threshold */
2704         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2705
2706         /* rx aggregation */
2707         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2708         ocp_data &= ~RX_AGG_DISABLE;
2709         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2710 }
2711
2712 static void r8153_enter_oob(struct r8152 *tp)
2713 {
2714         u32 ocp_data;
2715         int i;
2716
2717         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2718         ocp_data &= ~NOW_IS_OOB;
2719         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2720
2721         rtl_disable(tp);
2722
2723         for (i = 0; i < 1000; i++) {
2724                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2725                 if (ocp_data & LINK_LIST_READY)
2726                         break;
2727                 usleep_range(1000, 2000);
2728         }
2729
2730         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2731         ocp_data |= RE_INIT_LL;
2732         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2733
2734         for (i = 0; i < 1000; i++) {
2735                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2736                 if (ocp_data & LINK_LIST_READY)
2737                         break;
2738                 usleep_range(1000, 2000);
2739         }
2740
2741         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2742
2743         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2744         ocp_data &= ~TEREDO_WAKE_MASK;
2745         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2746
2747         rtl_rx_vlan_en(tp, true);
2748
2749         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2750         ocp_data |= ALDPS_PROXY_MODE;
2751         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2752
2753         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2754         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2755         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2756
2757         rxdy_gated_en(tp, false);
2758
2759         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2760         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2761         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2762 }
2763
2764 static void r8153_disable_aldps(struct r8152 *tp)
2765 {
2766         u16 data;
2767
2768         data = ocp_reg_read(tp, OCP_POWER_CFG);
2769         data &= ~EN_ALDPS;
2770         ocp_reg_write(tp, OCP_POWER_CFG, data);
2771         msleep(20);
2772 }
2773
2774 static void r8153_enable_aldps(struct r8152 *tp)
2775 {
2776         u16 data;
2777
2778         data = ocp_reg_read(tp, OCP_POWER_CFG);
2779         data |= EN_ALDPS;
2780         ocp_reg_write(tp, OCP_POWER_CFG, data);
2781 }
2782
2783 static void rtl8153_disable(struct r8152 *tp)
2784 {
2785         r8153_disable_aldps(tp);
2786         rtl_disable(tp);
2787         r8153_enable_aldps(tp);
2788 }
2789
2790 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2791 {
2792         u16 bmcr, anar, gbcr;
2793         int ret = 0;
2794
2795         cancel_delayed_work_sync(&tp->schedule);
2796         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2797         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2798                   ADVERTISE_100HALF | ADVERTISE_100FULL);
2799         if (tp->mii.supports_gmii) {
2800                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2801                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2802         } else {
2803                 gbcr = 0;
2804         }
2805
2806         if (autoneg == AUTONEG_DISABLE) {
2807                 if (speed == SPEED_10) {
2808                         bmcr = 0;
2809                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2810                 } else if (speed == SPEED_100) {
2811                         bmcr = BMCR_SPEED100;
2812                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2813                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2814                         bmcr = BMCR_SPEED1000;
2815                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2816                 } else {
2817                         ret = -EINVAL;
2818                         goto out;
2819                 }
2820
2821                 if (duplex == DUPLEX_FULL)
2822                         bmcr |= BMCR_FULLDPLX;
2823         } else {
2824                 if (speed == SPEED_10) {
2825                         if (duplex == DUPLEX_FULL)
2826                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2827                         else
2828                                 anar |= ADVERTISE_10HALF;
2829                 } else if (speed == SPEED_100) {
2830                         if (duplex == DUPLEX_FULL) {
2831                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2832                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2833                         } else {
2834                                 anar |= ADVERTISE_10HALF;
2835                                 anar |= ADVERTISE_100HALF;
2836                         }
2837                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2838                         if (duplex == DUPLEX_FULL) {
2839                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2840                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2841                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2842                         } else {
2843                                 anar |= ADVERTISE_10HALF;
2844                                 anar |= ADVERTISE_100HALF;
2845                                 gbcr |= ADVERTISE_1000HALF;
2846                         }
2847                 } else {
2848                         ret = -EINVAL;
2849                         goto out;
2850                 }
2851
2852                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2853         }
2854
2855         if (test_bit(PHY_RESET, &tp->flags))
2856                 bmcr |= BMCR_RESET;
2857
2858         if (tp->mii.supports_gmii)
2859                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2860
2861         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2862         r8152_mdio_write(tp, MII_BMCR, bmcr);
2863
2864         if (test_bit(PHY_RESET, &tp->flags)) {
2865                 int i;
2866
2867                 clear_bit(PHY_RESET, &tp->flags);
2868                 for (i = 0; i < 50; i++) {
2869                         msleep(20);
2870                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2871                                 break;
2872                 }
2873         }
2874
2875 out:
2876
2877         return ret;
2878 }
2879
2880 static void rtl8152_up(struct r8152 *tp)
2881 {
2882         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2883                 return;
2884
2885         r8152b_disable_aldps(tp);
2886         r8152b_exit_oob(tp);
2887         r8152b_enable_aldps(tp);
2888 }
2889
2890 static void rtl8152_down(struct r8152 *tp)
2891 {
2892         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2893                 rtl_drop_queued_tx(tp);
2894                 return;
2895         }
2896
2897         r8152_power_cut_en(tp, false);
2898         r8152b_disable_aldps(tp);
2899         r8152b_enter_oob(tp);
2900         r8152b_enable_aldps(tp);
2901 }
2902
2903 static void rtl8153_up(struct r8152 *tp)
2904 {
2905         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2906                 return;
2907
2908         r8153_disable_aldps(tp);
2909         r8153_first_init(tp);
2910         r8153_enable_aldps(tp);
2911 }
2912
2913 static void rtl8153_down(struct r8152 *tp)
2914 {
2915         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2916                 rtl_drop_queued_tx(tp);
2917                 return;
2918         }
2919
2920         r8153_u1u2en(tp, false);
2921         r8153_power_cut_en(tp, false);
2922         r8153_disable_aldps(tp);
2923         r8153_enter_oob(tp);
2924         r8153_enable_aldps(tp);
2925 }
2926
2927 static void set_carrier(struct r8152 *tp)
2928 {
2929         struct net_device *netdev = tp->netdev;
2930         u8 speed;
2931
2932         clear_bit(RTL8152_LINK_CHG, &tp->flags);
2933         speed = rtl8152_get_speed(tp);
2934
2935         if (speed & LINK_STATUS) {
2936                 if (!netif_carrier_ok(netdev)) {
2937                         tp->rtl_ops.enable(tp);
2938                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2939                         netif_carrier_on(netdev);
2940                         rtl_start_rx(tp);
2941                 }
2942         } else {
2943                 if (netif_carrier_ok(netdev)) {
2944                         netif_carrier_off(netdev);
2945                         napi_disable(&tp->napi);
2946                         tp->rtl_ops.disable(tp);
2947                         napi_enable(&tp->napi);
2948                 }
2949         }
2950 }
2951
2952 static void rtl_work_func_t(struct work_struct *work)
2953 {
2954         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2955
2956         /* If the device is unplugged or !netif_running(), the workqueue
2957          * doesn't need to wake the device, and could return directly.
2958          */
2959         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2960                 return;
2961
2962         if (usb_autopm_get_interface(tp->intf) < 0)
2963                 return;
2964
2965         if (!test_bit(WORK_ENABLE, &tp->flags))
2966                 goto out1;
2967
2968         if (!mutex_trylock(&tp->control)) {
2969                 schedule_delayed_work(&tp->schedule, 0);
2970                 goto out1;
2971         }
2972
2973         if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2974                 set_carrier(tp);
2975
2976         if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2977                 _rtl8152_set_rx_mode(tp->netdev);
2978
2979         /* don't schedule napi before linking */
2980         if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
2981             netif_carrier_ok(tp->netdev)) {
2982                 clear_bit(SCHEDULE_NAPI, &tp->flags);
2983                 napi_schedule(&tp->napi);
2984         }
2985
2986         if (test_bit(PHY_RESET, &tp->flags))
2987                 rtl_phy_reset(tp);
2988
2989         mutex_unlock(&tp->control);
2990
2991 out1:
2992         usb_autopm_put_interface(tp->intf);
2993 }
2994
2995 static int rtl8152_open(struct net_device *netdev)
2996 {
2997         struct r8152 *tp = netdev_priv(netdev);
2998         int res = 0;
2999
3000         res = alloc_all_mem(tp);
3001         if (res)
3002                 goto out;
3003
3004         netif_carrier_off(netdev);
3005
3006         res = usb_autopm_get_interface(tp->intf);
3007         if (res < 0) {
3008                 free_all_mem(tp);
3009                 goto out;
3010         }
3011
3012         mutex_lock(&tp->control);
3013
3014         /* The WORK_ENABLE may be set when autoresume occurs */
3015         if (test_bit(WORK_ENABLE, &tp->flags)) {
3016                 clear_bit(WORK_ENABLE, &tp->flags);
3017                 usb_kill_urb(tp->intr_urb);
3018                 cancel_delayed_work_sync(&tp->schedule);
3019
3020                 /* disable the tx/rx, if the workqueue has enabled them. */
3021                 if (netif_carrier_ok(netdev))
3022                         tp->rtl_ops.disable(tp);
3023         }
3024
3025         tp->rtl_ops.up(tp);
3026
3027         rtl8152_set_speed(tp, AUTONEG_ENABLE,
3028                           tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3029                           DUPLEX_FULL);
3030         netif_carrier_off(netdev);
3031         netif_start_queue(netdev);
3032         set_bit(WORK_ENABLE, &tp->flags);
3033
3034         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3035         if (res) {
3036                 if (res == -ENODEV)
3037                         netif_device_detach(tp->netdev);
3038                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3039                            res);
3040                 free_all_mem(tp);
3041         } else {
3042                 napi_enable(&tp->napi);
3043         }
3044
3045         mutex_unlock(&tp->control);
3046
3047         usb_autopm_put_interface(tp->intf);
3048
3049 out:
3050         return res;
3051 }
3052
3053 static int rtl8152_close(struct net_device *netdev)
3054 {
3055         struct r8152 *tp = netdev_priv(netdev);
3056         int res = 0;
3057
3058         napi_disable(&tp->napi);
3059         clear_bit(WORK_ENABLE, &tp->flags);
3060         usb_kill_urb(tp->intr_urb);
3061         cancel_delayed_work_sync(&tp->schedule);
3062         netif_stop_queue(netdev);
3063
3064         res = usb_autopm_get_interface(tp->intf);
3065         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3066                 rtl_drop_queued_tx(tp);
3067                 rtl_stop_rx(tp);
3068         } else {
3069                 mutex_lock(&tp->control);
3070
3071                 /* The autosuspend may have been enabled and wouldn't
3072                  * be disable when autoresume occurs, because the
3073                  * netif_running() would be false.
3074                  */
3075                 rtl_runtime_suspend_enable(tp, false);
3076
3077                 tp->rtl_ops.down(tp);
3078
3079                 mutex_unlock(&tp->control);
3080
3081                 usb_autopm_put_interface(tp->intf);
3082         }
3083
3084         free_all_mem(tp);
3085
3086         return res;
3087 }
3088
3089 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3090 {
3091         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3092         ocp_reg_write(tp, OCP_EEE_DATA, reg);
3093         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3094 }
3095
3096 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3097 {
3098         u16 data;
3099
3100         r8152_mmd_indirect(tp, dev, reg);
3101         data = ocp_reg_read(tp, OCP_EEE_DATA);
3102         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3103
3104         return data;
3105 }
3106
3107 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3108 {
3109         r8152_mmd_indirect(tp, dev, reg);
3110         ocp_reg_write(tp, OCP_EEE_DATA, data);
3111         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3112 }
3113
3114 static void r8152_eee_en(struct r8152 *tp, bool enable)
3115 {
3116         u16 config1, config2, config3;
3117         u32 ocp_data;
3118
3119         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3120         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3121         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3122         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3123
3124         if (enable) {
3125                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3126                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3127                 config1 |= sd_rise_time(1);
3128                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3129                 config3 |= fast_snr(42);
3130         } else {
3131                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3132                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3133                              RX_QUIET_EN);
3134                 config1 |= sd_rise_time(7);
3135                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3136                 config3 |= fast_snr(511);
3137         }
3138
3139         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3140         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3141         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3142         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3143 }
3144
3145 static void r8152b_enable_eee(struct r8152 *tp)
3146 {
3147         r8152_eee_en(tp, true);
3148         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3149 }
3150
3151 static void r8153_eee_en(struct r8152 *tp, bool enable)
3152 {
3153         u32 ocp_data;
3154         u16 config;
3155
3156         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3157         config = ocp_reg_read(tp, OCP_EEE_CFG);
3158
3159         if (enable) {
3160                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3161                 config |= EEE10_EN;
3162         } else {
3163                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3164                 config &= ~EEE10_EN;
3165         }
3166
3167         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3168         ocp_reg_write(tp, OCP_EEE_CFG, config);
3169 }
3170
3171 static void r8153_enable_eee(struct r8152 *tp)
3172 {
3173         r8153_eee_en(tp, true);
3174         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3175 }
3176
3177 static void r8152b_enable_fc(struct r8152 *tp)
3178 {
3179         u16 anar;
3180
3181         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3182         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3183         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3184 }
3185
3186 static void rtl_tally_reset(struct r8152 *tp)
3187 {
3188         u32 ocp_data;
3189
3190         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3191         ocp_data |= TALLY_RESET;
3192         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3193 }
3194
3195 static void r8152b_init(struct r8152 *tp)
3196 {
3197         u32 ocp_data;
3198
3199         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3200                 return;
3201
3202         r8152b_disable_aldps(tp);
3203
3204         if (tp->version == RTL_VER_01) {
3205                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3206                 ocp_data &= ~LED_MODE_MASK;
3207                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3208         }
3209
3210         r8152_power_cut_en(tp, false);
3211
3212         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3213         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3214         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3215         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3216         ocp_data &= ~MCU_CLK_RATIO_MASK;
3217         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3218         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3219         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3220                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3221         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3222
3223         r8152b_enable_eee(tp);
3224         r8152b_enable_aldps(tp);
3225         r8152b_enable_fc(tp);
3226         rtl_tally_reset(tp);
3227
3228         /* enable rx aggregation */
3229         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3230         ocp_data &= ~RX_AGG_DISABLE;
3231         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3232 }
3233
3234 static void r8153_init(struct r8152 *tp)
3235 {
3236         u32 ocp_data;
3237         int i;
3238
3239         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3240                 return;
3241
3242         r8153_disable_aldps(tp);
3243         r8153_u1u2en(tp, false);
3244
3245         for (i = 0; i < 500; i++) {
3246                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3247                     AUTOLOAD_DONE)
3248                         break;
3249                 msleep(20);
3250         }
3251
3252         for (i = 0; i < 500; i++) {
3253                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3254                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3255                         break;
3256                 msleep(20);
3257         }
3258
3259         r8153_u2p3en(tp, false);
3260
3261         if (tp->version == RTL_VER_04) {
3262                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3263                 ocp_data &= ~pwd_dn_scale_mask;
3264                 ocp_data |= pwd_dn_scale(96);
3265                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3266
3267                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3268                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3269                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3270         } else if (tp->version == RTL_VER_05) {
3271                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3272                 ocp_data &= ~ECM_ALDPS;
3273                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3274
3275                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3276                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3277                         ocp_data &= ~DYNAMIC_BURST;
3278                 else
3279                         ocp_data |= DYNAMIC_BURST;
3280                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3281         } else if (tp->version == RTL_VER_06) {
3282                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3283                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3284                         ocp_data &= ~DYNAMIC_BURST;
3285                 else
3286                         ocp_data |= DYNAMIC_BURST;
3287                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3288         }
3289
3290         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3291         ocp_data |= EP4_FULL_FC;
3292         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3293
3294         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3295         ocp_data &= ~TIMER11_EN;
3296         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3297
3298         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3299         ocp_data &= ~LED_MODE_MASK;
3300         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3301
3302         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
3303         if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
3304                 ocp_data |= LPM_TIMER_500MS;
3305         else
3306                 ocp_data |= LPM_TIMER_500US;
3307         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3308
3309         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3310         ocp_data &= ~SEN_VAL_MASK;
3311         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3312         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3313
3314         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3315
3316         r8153_power_cut_en(tp, false);
3317         r8153_u1u2en(tp, true);
3318
3319         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3320         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3321         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3322                        PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3323                        U1U2_SPDWN_EN | L1_SPDWN_EN);
3324         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3325                        PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3326                        TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3327                        EEE_SPDWN_EN);
3328
3329         r8153_enable_eee(tp);
3330         r8153_enable_aldps(tp);
3331         r8152b_enable_fc(tp);
3332         rtl_tally_reset(tp);
3333 }
3334
3335 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3336 {
3337         struct r8152 *tp = usb_get_intfdata(intf);
3338         struct net_device *netdev = tp->netdev;
3339         int ret = 0;
3340
3341         mutex_lock(&tp->control);
3342
3343         if (PMSG_IS_AUTO(message)) {
3344                 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3345                         ret = -EBUSY;
3346                         goto out1;
3347                 }
3348
3349                 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3350         } else {
3351                 netif_device_detach(netdev);
3352         }
3353
3354         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3355                 clear_bit(WORK_ENABLE, &tp->flags);
3356                 usb_kill_urb(tp->intr_urb);
3357                 napi_disable(&tp->napi);
3358                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3359                         rtl_stop_rx(tp);
3360                         rtl_runtime_suspend_enable(tp, true);
3361                 } else {
3362                         cancel_delayed_work_sync(&tp->schedule);
3363                         tp->rtl_ops.down(tp);
3364                 }
3365                 napi_enable(&tp->napi);
3366         }
3367 out1:
3368         mutex_unlock(&tp->control);
3369
3370         return ret;
3371 }
3372
3373 static int rtl8152_resume(struct usb_interface *intf)
3374 {
3375         struct r8152 *tp = usb_get_intfdata(intf);
3376
3377         mutex_lock(&tp->control);
3378
3379         if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3380                 tp->rtl_ops.init(tp);
3381                 netif_device_attach(tp->netdev);
3382         }
3383
3384         if (netif_running(tp->netdev)) {
3385                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3386                         rtl_runtime_suspend_enable(tp, false);
3387                         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3388                         set_bit(WORK_ENABLE, &tp->flags);
3389                         if (netif_carrier_ok(tp->netdev))
3390                                 rtl_start_rx(tp);
3391                 } else {
3392                         tp->rtl_ops.up(tp);
3393                         rtl8152_set_speed(tp, AUTONEG_ENABLE,
3394                                           tp->mii.supports_gmii ?
3395                                           SPEED_1000 : SPEED_100,
3396                                           DUPLEX_FULL);
3397                         netif_carrier_off(tp->netdev);
3398                         set_bit(WORK_ENABLE, &tp->flags);
3399                 }
3400                 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3401         } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3402                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3403         }
3404
3405         mutex_unlock(&tp->control);
3406
3407         return 0;
3408 }
3409
3410 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3411 {
3412         struct r8152 *tp = netdev_priv(dev);
3413
3414         if (usb_autopm_get_interface(tp->intf) < 0)
3415                 return;
3416
3417         mutex_lock(&tp->control);
3418
3419         wol->supported = WAKE_ANY;
3420         wol->wolopts = __rtl_get_wol(tp);
3421
3422         mutex_unlock(&tp->control);
3423
3424         usb_autopm_put_interface(tp->intf);
3425 }
3426
3427 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3428 {
3429         struct r8152 *tp = netdev_priv(dev);
3430         int ret;
3431
3432         ret = usb_autopm_get_interface(tp->intf);
3433         if (ret < 0)
3434                 goto out_set_wol;
3435
3436         mutex_lock(&tp->control);
3437
3438         __rtl_set_wol(tp, wol->wolopts);
3439         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3440
3441         mutex_unlock(&tp->control);
3442
3443         usb_autopm_put_interface(tp->intf);
3444
3445 out_set_wol:
3446         return ret;
3447 }
3448
3449 static u32 rtl8152_get_msglevel(struct net_device *dev)
3450 {
3451         struct r8152 *tp = netdev_priv(dev);
3452
3453         return tp->msg_enable;
3454 }
3455
3456 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3457 {
3458         struct r8152 *tp = netdev_priv(dev);
3459
3460         tp->msg_enable = value;
3461 }
3462
3463 static void rtl8152_get_drvinfo(struct net_device *netdev,
3464                                 struct ethtool_drvinfo *info)
3465 {
3466         struct r8152 *tp = netdev_priv(netdev);
3467
3468         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3469         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3470         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3471 }
3472
3473 static
3474 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3475 {
3476         struct r8152 *tp = netdev_priv(netdev);
3477         int ret;
3478
3479         if (!tp->mii.mdio_read)
3480                 return -EOPNOTSUPP;
3481
3482         ret = usb_autopm_get_interface(tp->intf);
3483         if (ret < 0)
3484                 goto out;
3485
3486         mutex_lock(&tp->control);
3487
3488         ret = mii_ethtool_gset(&tp->mii, cmd);
3489
3490         mutex_unlock(&tp->control);
3491
3492         usb_autopm_put_interface(tp->intf);
3493
3494 out:
3495         return ret;
3496 }
3497
3498 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3499 {
3500         struct r8152 *tp = netdev_priv(dev);
3501         int ret;
3502
3503         ret = usb_autopm_get_interface(tp->intf);
3504         if (ret < 0)
3505                 goto out;
3506
3507         mutex_lock(&tp->control);
3508
3509         ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3510
3511         mutex_unlock(&tp->control);
3512
3513         usb_autopm_put_interface(tp->intf);
3514
3515 out:
3516         return ret;
3517 }
3518
3519 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3520         "tx_packets",
3521         "rx_packets",
3522         "tx_errors",
3523         "rx_errors",
3524         "rx_missed",
3525         "align_errors",
3526         "tx_single_collisions",
3527         "tx_multi_collisions",
3528         "rx_unicast",
3529         "rx_broadcast",
3530         "rx_multicast",
3531         "tx_aborted",
3532         "tx_underrun",
3533 };
3534
3535 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3536 {
3537         switch (sset) {
3538         case ETH_SS_STATS:
3539                 return ARRAY_SIZE(rtl8152_gstrings);
3540         default:
3541                 return -EOPNOTSUPP;
3542         }
3543 }
3544
3545 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3546                                       struct ethtool_stats *stats, u64 *data)
3547 {
3548         struct r8152 *tp = netdev_priv(dev);
3549         struct tally_counter tally;
3550
3551         if (usb_autopm_get_interface(tp->intf) < 0)
3552                 return;
3553
3554         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3555
3556         usb_autopm_put_interface(tp->intf);
3557
3558         data[0] = le64_to_cpu(tally.tx_packets);
3559         data[1] = le64_to_cpu(tally.rx_packets);
3560         data[2] = le64_to_cpu(tally.tx_errors);
3561         data[3] = le32_to_cpu(tally.rx_errors);
3562         data[4] = le16_to_cpu(tally.rx_missed);
3563         data[5] = le16_to_cpu(tally.align_errors);
3564         data[6] = le32_to_cpu(tally.tx_one_collision);
3565         data[7] = le32_to_cpu(tally.tx_multi_collision);
3566         data[8] = le64_to_cpu(tally.rx_unicast);
3567         data[9] = le64_to_cpu(tally.rx_broadcast);
3568         data[10] = le32_to_cpu(tally.rx_multicast);
3569         data[11] = le16_to_cpu(tally.tx_aborted);
3570         data[12] = le16_to_cpu(tally.tx_underrun);
3571 }
3572
3573 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3574 {
3575         switch (stringset) {
3576         case ETH_SS_STATS:
3577                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3578                 break;
3579         }
3580 }
3581
3582 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3583 {
3584         u32 ocp_data, lp, adv, supported = 0;
3585         u16 val;
3586
3587         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3588         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3589
3590         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3591         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3592
3593         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3594         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3595
3596         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3597         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3598
3599         eee->eee_enabled = !!ocp_data;
3600         eee->eee_active = !!(supported & adv & lp);
3601         eee->supported = supported;
3602         eee->advertised = adv;
3603         eee->lp_advertised = lp;
3604
3605         return 0;
3606 }
3607
3608 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3609 {
3610         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3611
3612         r8152_eee_en(tp, eee->eee_enabled);
3613
3614         if (!eee->eee_enabled)
3615                 val = 0;
3616
3617         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3618
3619         return 0;
3620 }
3621
3622 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3623 {
3624         u32 ocp_data, lp, adv, supported = 0;
3625         u16 val;
3626
3627         val = ocp_reg_read(tp, OCP_EEE_ABLE);
3628         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3629
3630         val = ocp_reg_read(tp, OCP_EEE_ADV);
3631         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3632
3633         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3634         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3635
3636         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3637         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3638
3639         eee->eee_enabled = !!ocp_data;
3640         eee->eee_active = !!(supported & adv & lp);
3641         eee->supported = supported;
3642         eee->advertised = adv;
3643         eee->lp_advertised = lp;
3644
3645         return 0;
3646 }
3647
3648 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3649 {
3650         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3651
3652         r8153_eee_en(tp, eee->eee_enabled);
3653
3654         if (!eee->eee_enabled)
3655                 val = 0;
3656
3657         ocp_reg_write(tp, OCP_EEE_ADV, val);
3658
3659         return 0;
3660 }
3661
3662 static int
3663 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3664 {
3665         struct r8152 *tp = netdev_priv(net);
3666         int ret;
3667
3668         ret = usb_autopm_get_interface(tp->intf);
3669         if (ret < 0)
3670                 goto out;
3671
3672         mutex_lock(&tp->control);
3673
3674         ret = tp->rtl_ops.eee_get(tp, edata);
3675
3676         mutex_unlock(&tp->control);
3677
3678         usb_autopm_put_interface(tp->intf);
3679
3680 out:
3681         return ret;
3682 }
3683
3684 static int
3685 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3686 {
3687         struct r8152 *tp = netdev_priv(net);
3688         int ret;
3689
3690         ret = usb_autopm_get_interface(tp->intf);
3691         if (ret < 0)
3692                 goto out;
3693
3694         mutex_lock(&tp->control);
3695
3696         ret = tp->rtl_ops.eee_set(tp, edata);
3697         if (!ret)
3698                 ret = mii_nway_restart(&tp->mii);
3699
3700         mutex_unlock(&tp->control);
3701
3702         usb_autopm_put_interface(tp->intf);
3703
3704 out:
3705         return ret;
3706 }
3707
3708 static int rtl8152_nway_reset(struct net_device *dev)
3709 {
3710         struct r8152 *tp = netdev_priv(dev);
3711         int ret;
3712
3713         ret = usb_autopm_get_interface(tp->intf);
3714         if (ret < 0)
3715                 goto out;
3716
3717         mutex_lock(&tp->control);
3718
3719         ret = mii_nway_restart(&tp->mii);
3720
3721         mutex_unlock(&tp->control);
3722
3723         usb_autopm_put_interface(tp->intf);
3724
3725 out:
3726         return ret;
3727 }
3728
3729 static int rtl8152_get_coalesce(struct net_device *netdev,
3730                                 struct ethtool_coalesce *coalesce)
3731 {
3732         struct r8152 *tp = netdev_priv(netdev);
3733
3734         switch (tp->version) {
3735         case RTL_VER_01:
3736         case RTL_VER_02:
3737                 return -EOPNOTSUPP;
3738         default:
3739                 break;
3740         }
3741
3742         coalesce->rx_coalesce_usecs = tp->coalesce;
3743
3744         return 0;
3745 }
3746
3747 static int rtl8152_set_coalesce(struct net_device *netdev,
3748                                 struct ethtool_coalesce *coalesce)
3749 {
3750         struct r8152 *tp = netdev_priv(netdev);
3751         int ret;
3752
3753         switch (tp->version) {
3754         case RTL_VER_01:
3755         case RTL_VER_02:
3756                 return -EOPNOTSUPP;
3757         default:
3758                 break;
3759         }
3760
3761         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
3762                 return -EINVAL;
3763
3764         ret = usb_autopm_get_interface(tp->intf);
3765         if (ret < 0)
3766                 return ret;
3767
3768         mutex_lock(&tp->control);
3769
3770         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
3771                 tp->coalesce = coalesce->rx_coalesce_usecs;
3772
3773                 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
3774                         r8153_set_rx_early_timeout(tp);
3775         }
3776
3777         mutex_unlock(&tp->control);
3778
3779         usb_autopm_put_interface(tp->intf);
3780
3781         return ret;
3782 }
3783
3784 static struct ethtool_ops ops = {
3785         .get_drvinfo = rtl8152_get_drvinfo,
3786         .get_settings = rtl8152_get_settings,
3787         .set_settings = rtl8152_set_settings,
3788         .get_link = ethtool_op_get_link,
3789         .nway_reset = rtl8152_nway_reset,
3790         .get_msglevel = rtl8152_get_msglevel,
3791         .set_msglevel = rtl8152_set_msglevel,
3792         .get_wol = rtl8152_get_wol,
3793         .set_wol = rtl8152_set_wol,
3794         .get_strings = rtl8152_get_strings,
3795         .get_sset_count = rtl8152_get_sset_count,
3796         .get_ethtool_stats = rtl8152_get_ethtool_stats,
3797         .get_coalesce = rtl8152_get_coalesce,
3798         .set_coalesce = rtl8152_set_coalesce,
3799         .get_eee = rtl_ethtool_get_eee,
3800         .set_eee = rtl_ethtool_set_eee,
3801 };
3802
3803 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3804 {
3805         struct r8152 *tp = netdev_priv(netdev);
3806         struct mii_ioctl_data *data = if_mii(rq);
3807         int res;
3808
3809         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3810                 return -ENODEV;
3811
3812         res = usb_autopm_get_interface(tp->intf);
3813         if (res < 0)
3814                 goto out;
3815
3816         switch (cmd) {
3817         case SIOCGMIIPHY:
3818                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3819                 break;
3820
3821         case SIOCGMIIREG:
3822                 mutex_lock(&tp->control);
3823                 data->val_out = r8152_mdio_read(tp, data->reg_num);
3824                 mutex_unlock(&tp->control);
3825                 break;
3826
3827         case SIOCSMIIREG:
3828                 if (!capable(CAP_NET_ADMIN)) {
3829                         res = -EPERM;
3830                         break;
3831                 }
3832                 mutex_lock(&tp->control);
3833                 r8152_mdio_write(tp, data->reg_num, data->val_in);
3834                 mutex_unlock(&tp->control);
3835                 break;
3836
3837         default:
3838                 res = -EOPNOTSUPP;
3839         }
3840
3841         usb_autopm_put_interface(tp->intf);
3842
3843 out:
3844         return res;
3845 }
3846
3847 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3848 {
3849         struct r8152 *tp = netdev_priv(dev);
3850         int ret;
3851
3852         switch (tp->version) {
3853         case RTL_VER_01:
3854         case RTL_VER_02:
3855                 return eth_change_mtu(dev, new_mtu);
3856         default:
3857                 break;
3858         }
3859
3860         if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3861                 return -EINVAL;
3862
3863         ret = usb_autopm_get_interface(tp->intf);
3864         if (ret < 0)
3865                 return ret;
3866
3867         mutex_lock(&tp->control);
3868
3869         dev->mtu = new_mtu;
3870
3871         if (netif_running(dev) && netif_carrier_ok(dev))
3872                 r8153_set_rx_early_size(tp);
3873
3874         mutex_unlock(&tp->control);
3875
3876         usb_autopm_put_interface(tp->intf);
3877
3878         return ret;
3879 }
3880
3881 static const struct net_device_ops rtl8152_netdev_ops = {
3882         .ndo_open               = rtl8152_open,
3883         .ndo_stop               = rtl8152_close,
3884         .ndo_do_ioctl           = rtl8152_ioctl,
3885         .ndo_start_xmit         = rtl8152_start_xmit,
3886         .ndo_tx_timeout         = rtl8152_tx_timeout,
3887         .ndo_set_features       = rtl8152_set_features,
3888         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
3889         .ndo_set_mac_address    = rtl8152_set_mac_address,
3890         .ndo_change_mtu         = rtl8152_change_mtu,
3891         .ndo_validate_addr      = eth_validate_addr,
3892         .ndo_features_check     = rtl8152_features_check,
3893 };
3894
3895 static void r8152b_get_version(struct r8152 *tp)
3896 {
3897         u32     ocp_data;
3898         u16     version;
3899
3900         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3901         version = (u16)(ocp_data & VERSION_MASK);
3902
3903         switch (version) {
3904         case 0x4c00:
3905                 tp->version = RTL_VER_01;
3906                 break;
3907         case 0x4c10:
3908                 tp->version = RTL_VER_02;
3909                 break;
3910         case 0x5c00:
3911                 tp->version = RTL_VER_03;
3912                 tp->mii.supports_gmii = 1;
3913                 break;
3914         case 0x5c10:
3915                 tp->version = RTL_VER_04;
3916                 tp->mii.supports_gmii = 1;
3917                 break;
3918         case 0x5c20:
3919                 tp->version = RTL_VER_05;
3920                 tp->mii.supports_gmii = 1;
3921                 break;
3922         case 0x5c30:
3923                 tp->version = RTL_VER_06;
3924                 tp->mii.supports_gmii = 1;
3925                 break;
3926         default:
3927                 netif_info(tp, probe, tp->netdev,
3928                            "Unknown version 0x%04x\n", version);
3929                 break;
3930         }
3931 }
3932
3933 static void rtl8152_unload(struct r8152 *tp)
3934 {
3935         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3936                 return;
3937
3938         if (tp->version != RTL_VER_01)
3939                 r8152_power_cut_en(tp, true);
3940 }
3941
3942 static void rtl8153_unload(struct r8152 *tp)
3943 {
3944         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3945                 return;
3946
3947         r8153_power_cut_en(tp, false);
3948 }
3949
3950 static int rtl_ops_init(struct r8152 *tp)
3951 {
3952         struct rtl_ops *ops = &tp->rtl_ops;
3953         int ret = 0;
3954
3955         switch (tp->version) {
3956         case RTL_VER_01:
3957         case RTL_VER_02:
3958                 ops->init               = r8152b_init;
3959                 ops->enable             = rtl8152_enable;
3960                 ops->disable            = rtl8152_disable;
3961                 ops->up                 = rtl8152_up;
3962                 ops->down               = rtl8152_down;
3963                 ops->unload             = rtl8152_unload;
3964                 ops->eee_get            = r8152_get_eee;
3965                 ops->eee_set            = r8152_set_eee;
3966                 break;
3967
3968         case RTL_VER_03:
3969         case RTL_VER_04:
3970         case RTL_VER_05:
3971         case RTL_VER_06:
3972                 ops->init               = r8153_init;
3973                 ops->enable             = rtl8153_enable;
3974                 ops->disable            = rtl8153_disable;
3975                 ops->up                 = rtl8153_up;
3976                 ops->down               = rtl8153_down;
3977                 ops->unload             = rtl8153_unload;
3978                 ops->eee_get            = r8153_get_eee;
3979                 ops->eee_set            = r8153_set_eee;
3980                 break;
3981
3982         default:
3983                 ret = -ENODEV;
3984                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3985                 break;
3986         }
3987
3988         return ret;
3989 }
3990
3991 static int rtl8152_probe(struct usb_interface *intf,
3992                          const struct usb_device_id *id)
3993 {
3994         struct usb_device *udev = interface_to_usbdev(intf);
3995         struct r8152 *tp;
3996         struct net_device *netdev;
3997         int ret;
3998
3999         if (udev->actconfig->desc.bConfigurationValue != 1) {
4000                 usb_driver_set_configuration(udev, 1);
4001                 return -ENODEV;
4002         }
4003
4004         usb_reset_device(udev);
4005         netdev = alloc_etherdev(sizeof(struct r8152));
4006         if (!netdev) {
4007                 dev_err(&intf->dev, "Out of memory\n");
4008                 return -ENOMEM;
4009         }
4010
4011         SET_NETDEV_DEV(netdev, &intf->dev);
4012         tp = netdev_priv(netdev);
4013         tp->msg_enable = 0x7FFF;
4014
4015         tp->udev = udev;
4016         tp->netdev = netdev;
4017         tp->intf = intf;
4018
4019         r8152b_get_version(tp);
4020         ret = rtl_ops_init(tp);
4021         if (ret)
4022                 goto out;
4023
4024         mutex_init(&tp->control);
4025         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
4026
4027         netdev->netdev_ops = &rtl8152_netdev_ops;
4028         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
4029
4030         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4031                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
4032                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4033                             NETIF_F_HW_VLAN_CTAG_TX;
4034         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4035                               NETIF_F_TSO | NETIF_F_FRAGLIST |
4036                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
4037                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
4038         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4039                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4040                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
4041
4042         netdev->ethtool_ops = &ops;
4043         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
4044
4045         tp->mii.dev = netdev;
4046         tp->mii.mdio_read = read_mii_word;
4047         tp->mii.mdio_write = write_mii_word;
4048         tp->mii.phy_id_mask = 0x3f;
4049         tp->mii.reg_num_mask = 0x1f;
4050         tp->mii.phy_id = R8152_PHY_ID;
4051
4052         switch (udev->speed) {
4053         case USB_SPEED_SUPER:
4054                 tp->coalesce = COALESCE_SUPER;
4055                 break;
4056         case USB_SPEED_HIGH:
4057                 tp->coalesce = COALESCE_HIGH;
4058                 break;
4059         default:
4060                 tp->coalesce = COALESCE_SLOW;
4061                 break;
4062         }
4063
4064         intf->needs_remote_wakeup = 1;
4065
4066         tp->rtl_ops.init(tp);
4067         set_ethernet_addr(tp);
4068
4069         usb_set_intfdata(intf, tp);
4070         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
4071
4072         ret = register_netdev(netdev);
4073         if (ret != 0) {
4074                 netif_err(tp, probe, netdev, "couldn't register the device\n");
4075                 goto out1;
4076         }
4077
4078         tp->saved_wolopts = __rtl_get_wol(tp);
4079         if (tp->saved_wolopts)
4080                 device_set_wakeup_enable(&udev->dev, true);
4081         else
4082                 device_set_wakeup_enable(&udev->dev, false);
4083
4084         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
4085
4086         return 0;
4087
4088 out1:
4089         netif_napi_del(&tp->napi);
4090         usb_set_intfdata(intf, NULL);
4091 out:
4092         free_netdev(netdev);
4093         return ret;
4094 }
4095
4096 static void rtl8152_disconnect(struct usb_interface *intf)
4097 {
4098         struct r8152 *tp = usb_get_intfdata(intf);
4099
4100         usb_set_intfdata(intf, NULL);
4101         if (tp) {
4102                 struct usb_device *udev = tp->udev;
4103
4104                 if (udev->state == USB_STATE_NOTATTACHED)
4105                         set_bit(RTL8152_UNPLUG, &tp->flags);
4106
4107                 netif_napi_del(&tp->napi);
4108                 unregister_netdev(tp->netdev);
4109                 tp->rtl_ops.unload(tp);
4110                 free_netdev(tp->netdev);
4111         }
4112 }
4113
4114 #define REALTEK_USB_DEVICE(vend, prod)  \
4115         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4116                        USB_DEVICE_ID_MATCH_INT_CLASS, \
4117         .idVendor = (vend), \
4118         .idProduct = (prod), \
4119         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4120 }, \
4121 { \
4122         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4123                        USB_DEVICE_ID_MATCH_DEVICE, \
4124         .idVendor = (vend), \
4125         .idProduct = (prod), \
4126         .bInterfaceClass = USB_CLASS_COMM, \
4127         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4128         .bInterfaceProtocol = USB_CDC_PROTO_NONE
4129
4130 /* table of devices that work with this driver */
4131 static struct usb_device_id rtl8152_table[] = {
4132         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4133         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4134         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
4135         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
4136         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
4137         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
4138         {}
4139 };
4140
4141 MODULE_DEVICE_TABLE(usb, rtl8152_table);
4142
4143 static struct usb_driver rtl8152_driver = {
4144         .name =         MODULENAME,
4145         .id_table =     rtl8152_table,
4146         .probe =        rtl8152_probe,
4147         .disconnect =   rtl8152_disconnect,
4148         .suspend =      rtl8152_suspend,
4149         .resume =       rtl8152_resume,
4150         .reset_resume = rtl8152_resume,
4151         .supports_autosuspend = 1,
4152         .disable_hub_initiated_lpm = 1,
4153 };
4154
4155 module_usb_driver(rtl8152_driver);
4156
4157 MODULE_AUTHOR(DRIVER_AUTHOR);
4158 MODULE_DESCRIPTION(DRIVER_DESC);
4159 MODULE_LICENSE("GPL");