2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
28 /* Version Information */
29 #define DRIVER_VERSION "v1.07.0 (2014/10/09)"
30 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
31 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
32 #define MODULENAME "r8152"
34 #define R8152_PHY_ID 32
36 #define PLA_IDR 0xc000
37 #define PLA_RCR 0xc010
38 #define PLA_RMS 0xc016
39 #define PLA_RXFIFO_CTRL0 0xc0a0
40 #define PLA_RXFIFO_CTRL1 0xc0a4
41 #define PLA_RXFIFO_CTRL2 0xc0a8
42 #define PLA_FMC 0xc0b4
43 #define PLA_CFG_WOL 0xc0b6
44 #define PLA_TEREDO_CFG 0xc0bc
45 #define PLA_MAR 0xcd00
46 #define PLA_BACKUP 0xd000
47 #define PAL_BDC_CR 0xd1a0
48 #define PLA_TEREDO_TIMER 0xd2cc
49 #define PLA_REALWOW_TIMER 0xd2e8
50 #define PLA_LEDSEL 0xdd90
51 #define PLA_LED_FEATURE 0xdd92
52 #define PLA_PHYAR 0xde00
53 #define PLA_BOOT_CTRL 0xe004
54 #define PLA_GPHY_INTR_IMR 0xe022
55 #define PLA_EEE_CR 0xe040
56 #define PLA_EEEP_CR 0xe080
57 #define PLA_MAC_PWR_CTRL 0xe0c0
58 #define PLA_MAC_PWR_CTRL2 0xe0ca
59 #define PLA_MAC_PWR_CTRL3 0xe0cc
60 #define PLA_MAC_PWR_CTRL4 0xe0ce
61 #define PLA_WDT6_CTRL 0xe428
62 #define PLA_TCR0 0xe610
63 #define PLA_TCR1 0xe612
64 #define PLA_MTPS 0xe615
65 #define PLA_TXFIFO_CTRL 0xe618
66 #define PLA_RSTTALLY 0xe800
68 #define PLA_CRWECR 0xe81c
69 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
70 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
71 #define PLA_CONFIG5 0xe822
72 #define PLA_PHY_PWR 0xe84c
73 #define PLA_OOB_CTRL 0xe84f
74 #define PLA_CPCR 0xe854
75 #define PLA_MISC_0 0xe858
76 #define PLA_MISC_1 0xe85a
77 #define PLA_OCP_GPHY_BASE 0xe86c
78 #define PLA_TALLYCNT 0xe890
79 #define PLA_SFF_STS_7 0xe8de
80 #define PLA_PHYSTATUS 0xe908
81 #define PLA_BP_BA 0xfc26
82 #define PLA_BP_0 0xfc28
83 #define PLA_BP_1 0xfc2a
84 #define PLA_BP_2 0xfc2c
85 #define PLA_BP_3 0xfc2e
86 #define PLA_BP_4 0xfc30
87 #define PLA_BP_5 0xfc32
88 #define PLA_BP_6 0xfc34
89 #define PLA_BP_7 0xfc36
90 #define PLA_BP_EN 0xfc38
92 #define USB_U2P3_CTRL 0xb460
93 #define USB_DEV_STAT 0xb808
94 #define USB_USB_CTRL 0xd406
95 #define USB_PHY_CTRL 0xd408
96 #define USB_TX_AGG 0xd40a
97 #define USB_RX_BUF_TH 0xd40c
98 #define USB_USB_TIMER 0xd428
99 #define USB_RX_EARLY_AGG 0xd42c
100 #define USB_PM_CTRL_STATUS 0xd432
101 #define USB_TX_DMA 0xd434
102 #define USB_TOLERANCE 0xd490
103 #define USB_LPM_CTRL 0xd41a
104 #define USB_UPS_CTRL 0xd800
105 #define USB_MISC_0 0xd81a
106 #define USB_POWER_CUT 0xd80a
107 #define USB_AFE_CTRL2 0xd824
108 #define USB_WDT11_CTRL 0xe43c
109 #define USB_BP_BA 0xfc26
110 #define USB_BP_0 0xfc28
111 #define USB_BP_1 0xfc2a
112 #define USB_BP_2 0xfc2c
113 #define USB_BP_3 0xfc2e
114 #define USB_BP_4 0xfc30
115 #define USB_BP_5 0xfc32
116 #define USB_BP_6 0xfc34
117 #define USB_BP_7 0xfc36
118 #define USB_BP_EN 0xfc38
121 #define OCP_ALDPS_CONFIG 0x2010
122 #define OCP_EEE_CONFIG1 0x2080
123 #define OCP_EEE_CONFIG2 0x2092
124 #define OCP_EEE_CONFIG3 0x2094
125 #define OCP_BASE_MII 0xa400
126 #define OCP_EEE_AR 0xa41a
127 #define OCP_EEE_DATA 0xa41c
128 #define OCP_PHY_STATUS 0xa420
129 #define OCP_POWER_CFG 0xa430
130 #define OCP_EEE_CFG 0xa432
131 #define OCP_SRAM_ADDR 0xa436
132 #define OCP_SRAM_DATA 0xa438
133 #define OCP_DOWN_SPEED 0xa442
134 #define OCP_EEE_ABLE 0xa5c4
135 #define OCP_EEE_ADV 0xa5d0
136 #define OCP_EEE_LPABLE 0xa5d2
137 #define OCP_ADC_CFG 0xbc06
140 #define SRAM_LPF_CFG 0x8012
141 #define SRAM_10M_AMP1 0x8080
142 #define SRAM_10M_AMP2 0x8082
143 #define SRAM_IMPEDANCE 0x8084
146 #define RCR_AAP 0x00000001
147 #define RCR_APM 0x00000002
148 #define RCR_AM 0x00000004
149 #define RCR_AB 0x00000008
150 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
152 /* PLA_RXFIFO_CTRL0 */
153 #define RXFIFO_THR1_NORMAL 0x00080002
154 #define RXFIFO_THR1_OOB 0x01800003
156 /* PLA_RXFIFO_CTRL1 */
157 #define RXFIFO_THR2_FULL 0x00000060
158 #define RXFIFO_THR2_HIGH 0x00000038
159 #define RXFIFO_THR2_OOB 0x0000004a
160 #define RXFIFO_THR2_NORMAL 0x00a0
162 /* PLA_RXFIFO_CTRL2 */
163 #define RXFIFO_THR3_FULL 0x00000078
164 #define RXFIFO_THR3_HIGH 0x00000048
165 #define RXFIFO_THR3_OOB 0x0000005a
166 #define RXFIFO_THR3_NORMAL 0x0110
168 /* PLA_TXFIFO_CTRL */
169 #define TXFIFO_THR_NORMAL 0x00400008
170 #define TXFIFO_THR_NORMAL2 0x01000008
173 #define FMC_FCR_MCU_EN 0x0001
176 #define EEEP_CR_EEEP_TX 0x0002
179 #define WDT6_SET_MODE 0x0010
182 #define TCR0_TX_EMPTY 0x0800
183 #define TCR0_AUTO_FIFO 0x0080
186 #define VERSION_MASK 0x7cf0
189 #define MTPS_JUMBO (12 * 1024 / 64)
190 #define MTPS_DEFAULT (6 * 1024 / 64)
193 #define TALLY_RESET 0x0001
201 #define CRWECR_NORAML 0x00
202 #define CRWECR_CONFIG 0xc0
205 #define NOW_IS_OOB 0x80
206 #define TXFIFO_EMPTY 0x20
207 #define RXFIFO_EMPTY 0x10
208 #define LINK_LIST_READY 0x02
209 #define DIS_MCU_CLROOB 0x01
210 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
213 #define RXDY_GATED_EN 0x0008
216 #define RE_INIT_LL 0x8000
217 #define MCU_BORW_EN 0x4000
220 #define CPCR_RX_VLAN 0x0040
223 #define MAGIC_EN 0x0001
226 #define TEREDO_SEL 0x8000
227 #define TEREDO_WAKE_MASK 0x7f00
228 #define TEREDO_RS_EVENT_MASK 0x00fe
229 #define OOB_TEREDO_EN 0x0001
232 #define ALDPS_PROXY_MODE 0x0001
235 #define LINK_ON_WAKE_EN 0x0010
236 #define LINK_OFF_WAKE_EN 0x0008
239 #define BWF_EN 0x0040
240 #define MWF_EN 0x0020
241 #define UWF_EN 0x0010
242 #define LAN_WAKE_EN 0x0002
244 /* PLA_LED_FEATURE */
245 #define LED_MODE_MASK 0x0700
248 #define TX_10M_IDLE_EN 0x0080
249 #define PFM_PWM_SWITCH 0x0040
251 /* PLA_MAC_PWR_CTRL */
252 #define D3_CLK_GATED_EN 0x00004000
253 #define MCU_CLK_RATIO 0x07010f07
254 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
255 #define ALDPS_SPDWN_RATIO 0x0f87
257 /* PLA_MAC_PWR_CTRL2 */
258 #define EEE_SPDWN_RATIO 0x8007
260 /* PLA_MAC_PWR_CTRL3 */
261 #define PKT_AVAIL_SPDWN_EN 0x0100
262 #define SUSPEND_SPDWN_EN 0x0004
263 #define U1U2_SPDWN_EN 0x0002
264 #define L1_SPDWN_EN 0x0001
266 /* PLA_MAC_PWR_CTRL4 */
267 #define PWRSAVE_SPDWN_EN 0x1000
268 #define RXDV_SPDWN_EN 0x0800
269 #define TX10MIDLE_EN 0x0100
270 #define TP100_SPDWN_EN 0x0020
271 #define TP500_SPDWN_EN 0x0010
272 #define TP1000_SPDWN_EN 0x0008
273 #define EEE_SPDWN_EN 0x0001
275 /* PLA_GPHY_INTR_IMR */
276 #define GPHY_STS_MSK 0x0001
277 #define SPEED_DOWN_MSK 0x0002
278 #define SPDWN_RXDV_MSK 0x0004
279 #define SPDWN_LINKCHG_MSK 0x0008
282 #define PHYAR_FLAG 0x80000000
285 #define EEE_RX_EN 0x0001
286 #define EEE_TX_EN 0x0002
289 #define AUTOLOAD_DONE 0x0002
292 #define STAT_SPEED_MASK 0x0006
293 #define STAT_SPEED_HIGH 0x0000
294 #define STAT_SPEED_FULL 0x0002
297 #define TX_AGG_MAX_THRESHOLD 0x03
300 #define RX_THR_SUPPER 0x0c350180
301 #define RX_THR_HIGH 0x7a120180
302 #define RX_THR_SLOW 0xffff0180
305 #define TEST_MODE_DISABLE 0x00000001
306 #define TX_SIZE_ADJUST1 0x00000100
309 #define POWER_CUT 0x0100
311 /* USB_PM_CTRL_STATUS */
312 #define RESUME_INDICATE 0x0001
315 #define RX_AGG_DISABLE 0x0010
318 #define U2P3_ENABLE 0x0001
321 #define PWR_EN 0x0001
322 #define PHASE2_EN 0x0008
325 #define PCUT_STATUS 0x0001
327 /* USB_RX_EARLY_AGG */
328 #define EARLY_AGG_SUPPER 0x0e832981
329 #define EARLY_AGG_HIGH 0x0e837a12
330 #define EARLY_AGG_SLOW 0x0e83ffff
333 #define TIMER11_EN 0x0001
336 #define LPM_TIMER_MASK 0x0c
337 #define LPM_TIMER_500MS 0x04 /* 500 ms */
338 #define LPM_TIMER_500US 0x0c /* 500 us */
341 #define SEN_VAL_MASK 0xf800
342 #define SEN_VAL_NORMAL 0xa000
343 #define SEL_RXIDLE 0x0100
345 /* OCP_ALDPS_CONFIG */
346 #define ENPWRSAVE 0x8000
347 #define ENPDNPS 0x0200
348 #define LINKENA 0x0100
349 #define DIS_SDSAVE 0x0010
352 #define PHY_STAT_MASK 0x0007
353 #define PHY_STAT_LAN_ON 3
354 #define PHY_STAT_PWRDN 5
357 #define EEE_CLKDIV_EN 0x8000
358 #define EN_ALDPS 0x0004
359 #define EN_10M_PLLOFF 0x0001
361 /* OCP_EEE_CONFIG1 */
362 #define RG_TXLPI_MSK_HFDUP 0x8000
363 #define RG_MATCLR_EN 0x4000
364 #define EEE_10_CAP 0x2000
365 #define EEE_NWAY_EN 0x1000
366 #define TX_QUIET_EN 0x0200
367 #define RX_QUIET_EN 0x0100
368 #define sd_rise_time_mask 0x0070
369 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
370 #define RG_RXLPI_MSK_HFDUP 0x0008
371 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
373 /* OCP_EEE_CONFIG2 */
374 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
375 #define RG_DACQUIET_EN 0x0400
376 #define RG_LDVQUIET_EN 0x0200
377 #define RG_CKRSEL 0x0020
378 #define RG_EEEPRG_EN 0x0010
380 /* OCP_EEE_CONFIG3 */
381 #define fast_snr_mask 0xff80
382 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
383 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
384 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
387 /* bit[15:14] function */
388 #define FUN_ADDR 0x0000
389 #define FUN_DATA 0x4000
390 /* bit[4:0] device addr */
393 #define CTAP_SHORT_EN 0x0040
394 #define EEE10_EN 0x0010
397 #define EN_10M_BGOFF 0x0080
400 #define CKADSEL_L 0x0100
401 #define ADC_EN 0x0080
402 #define EN_EMI_L 0x0040
405 #define LPF_AUTO_TUNE 0x8000
408 #define GDAC_IB_UPALL 0x0008
411 #define AMP_DN 0x0200
414 #define RX_DRIVING_MASK 0x6000
416 enum rtl_register_content {
424 #define RTL8152_MAX_TX 4
425 #define RTL8152_MAX_RX 10
431 #define INTR_LINK 0x0004
433 #define RTL8152_REQT_READ 0xc0
434 #define RTL8152_REQT_WRITE 0x40
435 #define RTL8152_REQ_GET_REGS 0x05
436 #define RTL8152_REQ_SET_REGS 0x05
438 #define BYTE_EN_DWORD 0xff
439 #define BYTE_EN_WORD 0x33
440 #define BYTE_EN_BYTE 0x11
441 #define BYTE_EN_SIX_BYTES 0x3f
442 #define BYTE_EN_START_MASK 0x0f
443 #define BYTE_EN_END_MASK 0xf0
445 #define RTL8153_MAX_PACKET 9216 /* 9K */
446 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
447 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
448 #define RTL8153_RMS RTL8153_MAX_PACKET
449 #define RTL8152_TX_TIMEOUT (5 * HZ)
462 /* Define these values to match your device */
463 #define VENDOR_ID_REALTEK 0x0bda
464 #define PRODUCT_ID_RTL8152 0x8152
465 #define PRODUCT_ID_RTL8153 0x8153
467 #define VENDOR_ID_SAMSUNG 0x04e8
468 #define PRODUCT_ID_SAMSUNG 0xa101
470 #define MCU_TYPE_PLA 0x0100
471 #define MCU_TYPE_USB 0x0000
473 #define REALTEK_USB_DEVICE(vend, prod) \
474 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
476 struct tally_counter {
483 __le32 tx_one_collision;
484 __le32 tx_multi_collision;
494 #define RX_LEN_MASK 0x7fff
497 #define RD_UDP_CS (1 << 23)
498 #define RD_TCP_CS (1 << 22)
499 #define RD_IPV6_CS (1 << 20)
500 #define RD_IPV4_CS (1 << 19)
503 #define IPF (1 << 23) /* IP checksum fail */
504 #define UDPF (1 << 22) /* UDP checksum fail */
505 #define TCPF (1 << 21) /* TCP checksum fail */
506 #define RX_VLAN_TAG (1 << 16)
515 #define TX_FS (1 << 31) /* First segment of a packet */
516 #define TX_LS (1 << 30) /* Final segment of a packet */
517 #define GTSENDV4 (1 << 28)
518 #define GTSENDV6 (1 << 27)
519 #define GTTCPHO_SHIFT 18
520 #define GTTCPHO_MAX 0x7fU
521 #define TX_LEN_MAX 0x3ffffU
524 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
525 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
526 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
527 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
529 #define MSS_MAX 0x7ffU
530 #define TCPHO_SHIFT 17
531 #define TCPHO_MAX 0x7ffU
532 #define TX_VLAN_TAG (1 << 16)
538 struct list_head list;
540 struct r8152 *context;
546 struct list_head list;
548 struct r8152 *context;
557 struct usb_device *udev;
558 struct tasklet_struct tl;
559 struct usb_interface *intf;
560 struct net_device *netdev;
561 struct urb *intr_urb;
562 struct tx_agg tx_info[RTL8152_MAX_TX];
563 struct rx_agg rx_info[RTL8152_MAX_RX];
564 struct list_head rx_done, tx_free;
565 struct sk_buff_head tx_queue;
566 spinlock_t rx_lock, tx_lock;
567 struct delayed_work schedule;
568 struct mii_if_info mii;
569 struct mutex control; /* use for hw setting */
572 void (*init)(struct r8152 *);
573 int (*enable)(struct r8152 *);
574 void (*disable)(struct r8152 *);
575 void (*up)(struct r8152 *);
576 void (*down)(struct r8152 *);
577 void (*unload)(struct r8152 *);
578 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
579 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
608 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
609 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
611 static const int multicast_filter_limit = 32;
612 static unsigned int agg_buf_sz = 16384;
614 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
615 VLAN_ETH_HLEN - VLAN_HLEN)
618 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
623 tmp = kmalloc(size, GFP_KERNEL);
627 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
628 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
629 value, index, tmp, size, 500);
631 memcpy(data, tmp, size);
638 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
643 tmp = kmemdup(data, size, GFP_KERNEL);
647 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
648 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
649 value, index, tmp, size, 500);
656 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
657 void *data, u16 type)
662 if (test_bit(RTL8152_UNPLUG, &tp->flags))
665 /* both size and indix must be 4 bytes align */
666 if ((size & 3) || !size || (index & 3) || !data)
669 if ((u32)index + (u32)size > 0xffff)
674 ret = get_registers(tp, index, type, limit, data);
682 ret = get_registers(tp, index, type, size, data);
694 set_bit(RTL8152_UNPLUG, &tp->flags);
699 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
700 u16 size, void *data, u16 type)
703 u16 byteen_start, byteen_end, byen;
706 if (test_bit(RTL8152_UNPLUG, &tp->flags))
709 /* both size and indix must be 4 bytes align */
710 if ((size & 3) || !size || (index & 3) || !data)
713 if ((u32)index + (u32)size > 0xffff)
716 byteen_start = byteen & BYTE_EN_START_MASK;
717 byteen_end = byteen & BYTE_EN_END_MASK;
719 byen = byteen_start | (byteen_start << 4);
720 ret = set_registers(tp, index, type | byen, 4, data);
733 ret = set_registers(tp, index,
734 type | BYTE_EN_DWORD,
743 ret = set_registers(tp, index,
744 type | BYTE_EN_DWORD,
756 byen = byteen_end | (byteen_end >> 4);
757 ret = set_registers(tp, index, type | byen, 4, data);
764 set_bit(RTL8152_UNPLUG, &tp->flags);
770 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
772 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
776 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
778 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
782 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
784 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
788 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
790 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
793 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
797 generic_ocp_read(tp, index, sizeof(data), &data, type);
799 return __le32_to_cpu(data);
802 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
804 __le32 tmp = __cpu_to_le32(data);
806 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
809 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
813 u8 shift = index & 2;
817 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
819 data = __le32_to_cpu(tmp);
820 data >>= (shift * 8);
826 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
830 u16 byen = BYTE_EN_WORD;
831 u8 shift = index & 2;
837 mask <<= (shift * 8);
838 data <<= (shift * 8);
842 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
844 data |= __le32_to_cpu(tmp) & ~mask;
845 tmp = __cpu_to_le32(data);
847 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
850 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
854 u8 shift = index & 3;
858 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
860 data = __le32_to_cpu(tmp);
861 data >>= (shift * 8);
867 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
871 u16 byen = BYTE_EN_BYTE;
872 u8 shift = index & 3;
878 mask <<= (shift * 8);
879 data <<= (shift * 8);
883 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
885 data |= __le32_to_cpu(tmp) & ~mask;
886 tmp = __cpu_to_le32(data);
888 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
891 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
893 u16 ocp_base, ocp_index;
895 ocp_base = addr & 0xf000;
896 if (ocp_base != tp->ocp_base) {
897 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
898 tp->ocp_base = ocp_base;
901 ocp_index = (addr & 0x0fff) | 0xb000;
902 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
905 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
907 u16 ocp_base, ocp_index;
909 ocp_base = addr & 0xf000;
910 if (ocp_base != tp->ocp_base) {
911 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
912 tp->ocp_base = ocp_base;
915 ocp_index = (addr & 0x0fff) | 0xb000;
916 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
919 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
921 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
924 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
926 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
929 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
931 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
932 ocp_reg_write(tp, OCP_SRAM_DATA, data);
935 static u16 sram_read(struct r8152 *tp, u16 addr)
937 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
938 return ocp_reg_read(tp, OCP_SRAM_DATA);
941 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
943 struct r8152 *tp = netdev_priv(netdev);
946 if (test_bit(RTL8152_UNPLUG, &tp->flags))
949 if (phy_id != R8152_PHY_ID)
952 ret = r8152_mdio_read(tp, reg);
958 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
960 struct r8152 *tp = netdev_priv(netdev);
962 if (test_bit(RTL8152_UNPLUG, &tp->flags))
965 if (phy_id != R8152_PHY_ID)
968 r8152_mdio_write(tp, reg, val);
972 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
974 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
976 struct r8152 *tp = netdev_priv(netdev);
977 struct sockaddr *addr = p;
978 int ret = -EADDRNOTAVAIL;
980 if (!is_valid_ether_addr(addr->sa_data))
983 ret = usb_autopm_get_interface(tp->intf);
987 mutex_lock(&tp->control);
989 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
991 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
992 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
993 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
995 mutex_unlock(&tp->control);
997 usb_autopm_put_interface(tp->intf);
1002 static int set_ethernet_addr(struct r8152 *tp)
1004 struct net_device *dev = tp->netdev;
1008 if (tp->version == RTL_VER_01)
1009 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1011 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1014 netif_err(tp, probe, dev, "Get ether addr fail\n");
1015 } else if (!is_valid_ether_addr(sa.sa_data)) {
1016 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1018 eth_hw_addr_random(dev);
1019 ether_addr_copy(sa.sa_data, dev->dev_addr);
1020 ret = rtl8152_set_mac_address(dev, &sa);
1021 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1024 if (tp->version == RTL_VER_01)
1025 ether_addr_copy(dev->dev_addr, sa.sa_data);
1027 ret = rtl8152_set_mac_address(dev, &sa);
1033 static void read_bulk_callback(struct urb *urb)
1035 struct net_device *netdev;
1036 int status = urb->status;
1049 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1052 if (!test_bit(WORK_ENABLE, &tp->flags))
1055 netdev = tp->netdev;
1057 /* When link down, the driver would cancel all bulks. */
1058 /* This avoid the re-submitting bulk */
1059 if (!netif_carrier_ok(netdev))
1062 usb_mark_last_busy(tp->udev);
1066 if (urb->actual_length < ETH_ZLEN)
1069 spin_lock(&tp->rx_lock);
1070 list_add_tail(&agg->list, &tp->rx_done);
1071 spin_unlock(&tp->rx_lock);
1072 tasklet_schedule(&tp->tl);
1075 set_bit(RTL8152_UNPLUG, &tp->flags);
1076 netif_device_detach(tp->netdev);
1079 return; /* the urb is in unlink state */
1081 if (net_ratelimit())
1082 netdev_warn(netdev, "maybe reset is needed?\n");
1085 if (net_ratelimit())
1086 netdev_warn(netdev, "Rx status %d\n", status);
1090 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1091 if (result == -ENODEV) {
1092 set_bit(RTL8152_UNPLUG, &tp->flags);
1093 netif_device_detach(tp->netdev);
1094 } else if (result) {
1095 spin_lock(&tp->rx_lock);
1096 list_add_tail(&agg->list, &tp->rx_done);
1097 spin_unlock(&tp->rx_lock);
1098 tasklet_schedule(&tp->tl);
1102 static void write_bulk_callback(struct urb *urb)
1104 struct net_device_stats *stats;
1105 struct net_device *netdev;
1108 int status = urb->status;
1118 netdev = tp->netdev;
1119 stats = &netdev->stats;
1121 if (net_ratelimit())
1122 netdev_warn(netdev, "Tx status %d\n", status);
1123 stats->tx_errors += agg->skb_num;
1125 stats->tx_packets += agg->skb_num;
1126 stats->tx_bytes += agg->skb_len;
1129 spin_lock(&tp->tx_lock);
1130 list_add_tail(&agg->list, &tp->tx_free);
1131 spin_unlock(&tp->tx_lock);
1133 usb_autopm_put_interface_async(tp->intf);
1135 if (!netif_carrier_ok(netdev))
1138 if (!test_bit(WORK_ENABLE, &tp->flags))
1141 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1144 if (!skb_queue_empty(&tp->tx_queue))
1145 tasklet_schedule(&tp->tl);
1148 static void intr_callback(struct urb *urb)
1152 int status = urb->status;
1159 if (!test_bit(WORK_ENABLE, &tp->flags))
1162 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1166 case 0: /* success */
1168 case -ECONNRESET: /* unlink */
1170 netif_device_detach(tp->netdev);
1173 netif_info(tp, intr, tp->netdev,
1174 "Stop submitting intr, status %d\n", status);
1177 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1179 /* -EPIPE: should clear the halt */
1181 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1185 d = urb->transfer_buffer;
1186 if (INTR_LINK & __le16_to_cpu(d[0])) {
1187 if (!(tp->speed & LINK_STATUS)) {
1188 set_bit(RTL8152_LINK_CHG, &tp->flags);
1189 schedule_delayed_work(&tp->schedule, 0);
1192 if (tp->speed & LINK_STATUS) {
1193 set_bit(RTL8152_LINK_CHG, &tp->flags);
1194 schedule_delayed_work(&tp->schedule, 0);
1199 res = usb_submit_urb(urb, GFP_ATOMIC);
1200 if (res == -ENODEV) {
1201 set_bit(RTL8152_UNPLUG, &tp->flags);
1202 netif_device_detach(tp->netdev);
1204 netif_err(tp, intr, tp->netdev,
1205 "can't resubmit intr, status %d\n", res);
1209 static inline void *rx_agg_align(void *data)
1211 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1214 static inline void *tx_agg_align(void *data)
1216 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1219 static void free_all_mem(struct r8152 *tp)
1223 for (i = 0; i < RTL8152_MAX_RX; i++) {
1224 usb_free_urb(tp->rx_info[i].urb);
1225 tp->rx_info[i].urb = NULL;
1227 kfree(tp->rx_info[i].buffer);
1228 tp->rx_info[i].buffer = NULL;
1229 tp->rx_info[i].head = NULL;
1232 for (i = 0; i < RTL8152_MAX_TX; i++) {
1233 usb_free_urb(tp->tx_info[i].urb);
1234 tp->tx_info[i].urb = NULL;
1236 kfree(tp->tx_info[i].buffer);
1237 tp->tx_info[i].buffer = NULL;
1238 tp->tx_info[i].head = NULL;
1241 usb_free_urb(tp->intr_urb);
1242 tp->intr_urb = NULL;
1244 kfree(tp->intr_buff);
1245 tp->intr_buff = NULL;
1248 static int alloc_all_mem(struct r8152 *tp)
1250 struct net_device *netdev = tp->netdev;
1251 struct usb_interface *intf = tp->intf;
1252 struct usb_host_interface *alt = intf->cur_altsetting;
1253 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1258 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1260 spin_lock_init(&tp->rx_lock);
1261 spin_lock_init(&tp->tx_lock);
1262 INIT_LIST_HEAD(&tp->rx_done);
1263 INIT_LIST_HEAD(&tp->tx_free);
1264 skb_queue_head_init(&tp->tx_queue);
1266 for (i = 0; i < RTL8152_MAX_RX; i++) {
1267 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1271 if (buf != rx_agg_align(buf)) {
1273 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1279 urb = usb_alloc_urb(0, GFP_KERNEL);
1285 INIT_LIST_HEAD(&tp->rx_info[i].list);
1286 tp->rx_info[i].context = tp;
1287 tp->rx_info[i].urb = urb;
1288 tp->rx_info[i].buffer = buf;
1289 tp->rx_info[i].head = rx_agg_align(buf);
1292 for (i = 0; i < RTL8152_MAX_TX; i++) {
1293 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1297 if (buf != tx_agg_align(buf)) {
1299 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1305 urb = usb_alloc_urb(0, GFP_KERNEL);
1311 INIT_LIST_HEAD(&tp->tx_info[i].list);
1312 tp->tx_info[i].context = tp;
1313 tp->tx_info[i].urb = urb;
1314 tp->tx_info[i].buffer = buf;
1315 tp->tx_info[i].head = tx_agg_align(buf);
1317 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1320 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1324 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1328 tp->intr_interval = (int)ep_intr->desc.bInterval;
1329 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1330 tp->intr_buff, INTBUFSIZE, intr_callback,
1331 tp, tp->intr_interval);
1340 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1342 struct tx_agg *agg = NULL;
1343 unsigned long flags;
1345 if (list_empty(&tp->tx_free))
1348 spin_lock_irqsave(&tp->tx_lock, flags);
1349 if (!list_empty(&tp->tx_free)) {
1350 struct list_head *cursor;
1352 cursor = tp->tx_free.next;
1353 list_del_init(cursor);
1354 agg = list_entry(cursor, struct tx_agg, list);
1356 spin_unlock_irqrestore(&tp->tx_lock, flags);
1361 static inline __be16 get_protocol(struct sk_buff *skb)
1365 if (skb->protocol == htons(ETH_P_8021Q))
1366 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1368 protocol = skb->protocol;
1373 /* r8152_csum_workaround()
1374 * The hw limites the value the transport offset. When the offset is out of the
1375 * range, calculate the checksum by sw.
1377 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1378 struct sk_buff_head *list)
1380 if (skb_shinfo(skb)->gso_size) {
1381 netdev_features_t features = tp->netdev->features;
1382 struct sk_buff_head seg_list;
1383 struct sk_buff *segs, *nskb;
1385 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1386 segs = skb_gso_segment(skb, features);
1387 if (IS_ERR(segs) || !segs)
1390 __skb_queue_head_init(&seg_list);
1396 __skb_queue_tail(&seg_list, nskb);
1399 skb_queue_splice(&seg_list, list);
1401 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1402 if (skb_checksum_help(skb) < 0)
1405 __skb_queue_head(list, skb);
1407 struct net_device_stats *stats;
1410 stats = &tp->netdev->stats;
1411 stats->tx_dropped++;
1416 /* msdn_giant_send_check()
1417 * According to the document of microsoft, the TCP Pseudo Header excludes the
1418 * packet length for IPv6 TCP large packets.
1420 static int msdn_giant_send_check(struct sk_buff *skb)
1422 const struct ipv6hdr *ipv6h;
1426 ret = skb_cow_head(skb, 0);
1430 ipv6h = ipv6_hdr(skb);
1434 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1439 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1441 if (vlan_tx_tag_present(skb)) {
1444 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1445 desc->opts2 |= cpu_to_le32(opts2);
1449 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1451 u32 opts2 = le32_to_cpu(desc->opts2);
1453 if (opts2 & RX_VLAN_TAG)
1454 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1455 swab16(opts2 & 0xffff));
1458 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1459 struct sk_buff *skb, u32 len, u32 transport_offset)
1461 u32 mss = skb_shinfo(skb)->gso_size;
1462 u32 opts1, opts2 = 0;
1463 int ret = TX_CSUM_SUCCESS;
1465 WARN_ON_ONCE(len > TX_LEN_MAX);
1467 opts1 = len | TX_FS | TX_LS;
1470 if (transport_offset > GTTCPHO_MAX) {
1471 netif_warn(tp, tx_err, tp->netdev,
1472 "Invalid transport offset 0x%x for TSO\n",
1478 switch (get_protocol(skb)) {
1479 case htons(ETH_P_IP):
1483 case htons(ETH_P_IPV6):
1484 if (msdn_giant_send_check(skb)) {
1496 opts1 |= transport_offset << GTTCPHO_SHIFT;
1497 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1498 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1501 if (transport_offset > TCPHO_MAX) {
1502 netif_warn(tp, tx_err, tp->netdev,
1503 "Invalid transport offset 0x%x\n",
1509 switch (get_protocol(skb)) {
1510 case htons(ETH_P_IP):
1512 ip_protocol = ip_hdr(skb)->protocol;
1515 case htons(ETH_P_IPV6):
1517 ip_protocol = ipv6_hdr(skb)->nexthdr;
1521 ip_protocol = IPPROTO_RAW;
1525 if (ip_protocol == IPPROTO_TCP)
1527 else if (ip_protocol == IPPROTO_UDP)
1532 opts2 |= transport_offset << TCPHO_SHIFT;
1535 desc->opts2 = cpu_to_le32(opts2);
1536 desc->opts1 = cpu_to_le32(opts1);
1542 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1544 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1548 __skb_queue_head_init(&skb_head);
1549 spin_lock(&tx_queue->lock);
1550 skb_queue_splice_init(tx_queue, &skb_head);
1551 spin_unlock(&tx_queue->lock);
1553 tx_data = agg->head;
1556 remain = agg_buf_sz;
1558 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1559 struct tx_desc *tx_desc;
1560 struct sk_buff *skb;
1564 skb = __skb_dequeue(&skb_head);
1568 len = skb->len + sizeof(*tx_desc);
1571 __skb_queue_head(&skb_head, skb);
1575 tx_data = tx_agg_align(tx_data);
1576 tx_desc = (struct tx_desc *)tx_data;
1578 offset = (u32)skb_transport_offset(skb);
1580 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1581 r8152_csum_workaround(tp, skb, &skb_head);
1585 rtl_tx_vlan_tag(tx_desc, skb);
1587 tx_data += sizeof(*tx_desc);
1590 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1591 struct net_device_stats *stats = &tp->netdev->stats;
1593 stats->tx_dropped++;
1594 dev_kfree_skb_any(skb);
1595 tx_data -= sizeof(*tx_desc);
1600 agg->skb_len += len;
1603 dev_kfree_skb_any(skb);
1605 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1608 if (!skb_queue_empty(&skb_head)) {
1609 spin_lock(&tx_queue->lock);
1610 skb_queue_splice(&skb_head, tx_queue);
1611 spin_unlock(&tx_queue->lock);
1614 netif_tx_lock(tp->netdev);
1616 if (netif_queue_stopped(tp->netdev) &&
1617 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1618 netif_wake_queue(tp->netdev);
1620 netif_tx_unlock(tp->netdev);
1622 ret = usb_autopm_get_interface_async(tp->intf);
1626 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1627 agg->head, (int)(tx_data - (u8 *)agg->head),
1628 (usb_complete_t)write_bulk_callback, agg);
1630 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1632 usb_autopm_put_interface_async(tp->intf);
1638 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1640 u8 checksum = CHECKSUM_NONE;
1643 if (tp->version == RTL_VER_01)
1646 opts2 = le32_to_cpu(rx_desc->opts2);
1647 opts3 = le32_to_cpu(rx_desc->opts3);
1649 if (opts2 & RD_IPV4_CS) {
1651 checksum = CHECKSUM_NONE;
1652 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1653 checksum = CHECKSUM_NONE;
1654 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1655 checksum = CHECKSUM_NONE;
1657 checksum = CHECKSUM_UNNECESSARY;
1658 } else if (RD_IPV6_CS) {
1659 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1660 checksum = CHECKSUM_UNNECESSARY;
1661 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1662 checksum = CHECKSUM_UNNECESSARY;
1669 static void rx_bottom(struct r8152 *tp)
1671 unsigned long flags;
1672 struct list_head *cursor, *next, rx_queue;
1674 if (list_empty(&tp->rx_done))
1677 INIT_LIST_HEAD(&rx_queue);
1678 spin_lock_irqsave(&tp->rx_lock, flags);
1679 list_splice_init(&tp->rx_done, &rx_queue);
1680 spin_unlock_irqrestore(&tp->rx_lock, flags);
1682 list_for_each_safe(cursor, next, &rx_queue) {
1683 struct rx_desc *rx_desc;
1690 list_del_init(cursor);
1692 agg = list_entry(cursor, struct rx_agg, list);
1694 if (urb->actual_length < ETH_ZLEN)
1697 rx_desc = agg->head;
1698 rx_data = agg->head;
1699 len_used += sizeof(struct rx_desc);
1701 while (urb->actual_length > len_used) {
1702 struct net_device *netdev = tp->netdev;
1703 struct net_device_stats *stats = &netdev->stats;
1704 unsigned int pkt_len;
1705 struct sk_buff *skb;
1707 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1708 if (pkt_len < ETH_ZLEN)
1711 len_used += pkt_len;
1712 if (urb->actual_length < len_used)
1715 pkt_len -= CRC_SIZE;
1716 rx_data += sizeof(struct rx_desc);
1718 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1720 stats->rx_dropped++;
1724 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1725 memcpy(skb->data, rx_data, pkt_len);
1726 skb_put(skb, pkt_len);
1727 skb->protocol = eth_type_trans(skb, netdev);
1728 rtl_rx_vlan_tag(rx_desc, skb);
1729 netif_receive_skb(skb);
1730 stats->rx_packets++;
1731 stats->rx_bytes += pkt_len;
1734 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1735 rx_desc = (struct rx_desc *)rx_data;
1736 len_used = (int)(rx_data - (u8 *)agg->head);
1737 len_used += sizeof(struct rx_desc);
1741 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1742 if (ret && ret != -ENODEV) {
1743 spin_lock_irqsave(&tp->rx_lock, flags);
1744 list_add_tail(&agg->list, &tp->rx_done);
1745 spin_unlock_irqrestore(&tp->rx_lock, flags);
1746 tasklet_schedule(&tp->tl);
1751 static void tx_bottom(struct r8152 *tp)
1758 if (skb_queue_empty(&tp->tx_queue))
1761 agg = r8152_get_tx_agg(tp);
1765 res = r8152_tx_agg_fill(tp, agg);
1767 struct net_device *netdev = tp->netdev;
1769 if (res == -ENODEV) {
1770 set_bit(RTL8152_UNPLUG, &tp->flags);
1771 netif_device_detach(netdev);
1773 struct net_device_stats *stats = &netdev->stats;
1774 unsigned long flags;
1776 netif_warn(tp, tx_err, netdev,
1777 "failed tx_urb %d\n", res);
1778 stats->tx_dropped += agg->skb_num;
1780 spin_lock_irqsave(&tp->tx_lock, flags);
1781 list_add_tail(&agg->list, &tp->tx_free);
1782 spin_unlock_irqrestore(&tp->tx_lock, flags);
1788 static void bottom_half(unsigned long data)
1792 tp = (struct r8152 *)data;
1794 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1797 if (!test_bit(WORK_ENABLE, &tp->flags))
1800 /* When link down, the driver would cancel all bulks. */
1801 /* This avoid the re-submitting bulk */
1802 if (!netif_carrier_ok(tp->netdev))
1810 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1812 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1813 agg->head, agg_buf_sz,
1814 (usb_complete_t)read_bulk_callback, agg);
1816 return usb_submit_urb(agg->urb, mem_flags);
1819 static void rtl_drop_queued_tx(struct r8152 *tp)
1821 struct net_device_stats *stats = &tp->netdev->stats;
1822 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1823 struct sk_buff *skb;
1825 if (skb_queue_empty(tx_queue))
1828 __skb_queue_head_init(&skb_head);
1829 spin_lock_bh(&tx_queue->lock);
1830 skb_queue_splice_init(tx_queue, &skb_head);
1831 spin_unlock_bh(&tx_queue->lock);
1833 while ((skb = __skb_dequeue(&skb_head))) {
1835 stats->tx_dropped++;
1839 static void rtl8152_tx_timeout(struct net_device *netdev)
1841 struct r8152 *tp = netdev_priv(netdev);
1844 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1845 for (i = 0; i < RTL8152_MAX_TX; i++)
1846 usb_unlink_urb(tp->tx_info[i].urb);
1849 static void rtl8152_set_rx_mode(struct net_device *netdev)
1851 struct r8152 *tp = netdev_priv(netdev);
1853 if (tp->speed & LINK_STATUS) {
1854 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1855 schedule_delayed_work(&tp->schedule, 0);
1859 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1861 struct r8152 *tp = netdev_priv(netdev);
1862 u32 mc_filter[2]; /* Multicast hash filter */
1866 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1867 netif_stop_queue(netdev);
1868 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1869 ocp_data &= ~RCR_ACPT_ALL;
1870 ocp_data |= RCR_AB | RCR_APM;
1872 if (netdev->flags & IFF_PROMISC) {
1873 /* Unconditionally log net taps. */
1874 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1875 ocp_data |= RCR_AM | RCR_AAP;
1876 mc_filter[1] = 0xffffffff;
1877 mc_filter[0] = 0xffffffff;
1878 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1879 (netdev->flags & IFF_ALLMULTI)) {
1880 /* Too many to filter perfectly -- accept all multicasts. */
1882 mc_filter[1] = 0xffffffff;
1883 mc_filter[0] = 0xffffffff;
1885 struct netdev_hw_addr *ha;
1889 netdev_for_each_mc_addr(ha, netdev) {
1890 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1892 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1897 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1898 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1900 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1901 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1902 netif_wake_queue(netdev);
1905 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1906 struct net_device *netdev)
1908 struct r8152 *tp = netdev_priv(netdev);
1910 skb_tx_timestamp(skb);
1912 skb_queue_tail(&tp->tx_queue, skb);
1914 if (!list_empty(&tp->tx_free)) {
1915 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1916 set_bit(SCHEDULE_TASKLET, &tp->flags);
1917 schedule_delayed_work(&tp->schedule, 0);
1919 usb_mark_last_busy(tp->udev);
1920 tasklet_schedule(&tp->tl);
1922 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1923 netif_stop_queue(netdev);
1926 return NETDEV_TX_OK;
1929 static void r8152b_reset_packet_filter(struct r8152 *tp)
1933 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1934 ocp_data &= ~FMC_FCR_MCU_EN;
1935 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1936 ocp_data |= FMC_FCR_MCU_EN;
1937 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1940 static void rtl8152_nic_reset(struct r8152 *tp)
1944 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1946 for (i = 0; i < 1000; i++) {
1947 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1949 usleep_range(100, 400);
1953 static void set_tx_qlen(struct r8152 *tp)
1955 struct net_device *netdev = tp->netdev;
1957 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1958 sizeof(struct tx_desc));
1961 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1963 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1966 static void rtl_set_eee_plus(struct r8152 *tp)
1971 speed = rtl8152_get_speed(tp);
1972 if (speed & _10bps) {
1973 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1974 ocp_data |= EEEP_CR_EEEP_TX;
1975 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1977 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1978 ocp_data &= ~EEEP_CR_EEEP_TX;
1979 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1983 static void rxdy_gated_en(struct r8152 *tp, bool enable)
1987 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1989 ocp_data |= RXDY_GATED_EN;
1991 ocp_data &= ~RXDY_GATED_EN;
1992 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1995 static int rtl_start_rx(struct r8152 *tp)
1999 INIT_LIST_HEAD(&tp->rx_done);
2000 for (i = 0; i < RTL8152_MAX_RX; i++) {
2001 INIT_LIST_HEAD(&tp->rx_info[i].list);
2002 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2010 static int rtl_stop_rx(struct r8152 *tp)
2014 for (i = 0; i < RTL8152_MAX_RX; i++)
2015 usb_kill_urb(tp->rx_info[i].urb);
2020 static int rtl_enable(struct r8152 *tp)
2024 r8152b_reset_packet_filter(tp);
2026 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2027 ocp_data |= CR_RE | CR_TE;
2028 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2030 rxdy_gated_en(tp, false);
2032 return rtl_start_rx(tp);
2035 static int rtl8152_enable(struct r8152 *tp)
2037 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2041 rtl_set_eee_plus(tp);
2043 return rtl_enable(tp);
2046 static void r8153_set_rx_agg(struct r8152 *tp)
2050 speed = rtl8152_get_speed(tp);
2051 if (speed & _1000bps) {
2052 if (tp->udev->speed == USB_SPEED_SUPER) {
2053 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2055 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2058 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2060 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2064 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2065 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2070 static int rtl8153_enable(struct r8152 *tp)
2072 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2076 rtl_set_eee_plus(tp);
2077 r8153_set_rx_agg(tp);
2079 return rtl_enable(tp);
2082 static void rtl_disable(struct r8152 *tp)
2087 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2088 rtl_drop_queued_tx(tp);
2092 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2093 ocp_data &= ~RCR_ACPT_ALL;
2094 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2096 rtl_drop_queued_tx(tp);
2098 for (i = 0; i < RTL8152_MAX_TX; i++)
2099 usb_kill_urb(tp->tx_info[i].urb);
2101 rxdy_gated_en(tp, true);
2103 for (i = 0; i < 1000; i++) {
2104 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2105 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2107 usleep_range(1000, 2000);
2110 for (i = 0; i < 1000; i++) {
2111 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2113 usleep_range(1000, 2000);
2118 rtl8152_nic_reset(tp);
2121 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2125 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2127 ocp_data |= POWER_CUT;
2129 ocp_data &= ~POWER_CUT;
2130 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2132 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2133 ocp_data &= ~RESUME_INDICATE;
2134 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2137 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2141 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2143 ocp_data |= CPCR_RX_VLAN;
2145 ocp_data &= ~CPCR_RX_VLAN;
2146 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2149 static int rtl8152_set_features(struct net_device *dev,
2150 netdev_features_t features)
2152 netdev_features_t changed = features ^ dev->features;
2153 struct r8152 *tp = netdev_priv(dev);
2156 ret = usb_autopm_get_interface(tp->intf);
2160 mutex_lock(&tp->control);
2162 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2163 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2164 rtl_rx_vlan_en(tp, true);
2166 rtl_rx_vlan_en(tp, false);
2169 mutex_unlock(&tp->control);
2171 usb_autopm_put_interface(tp->intf);
2177 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2179 static u32 __rtl_get_wol(struct r8152 *tp)
2184 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2185 if (!(ocp_data & LAN_WAKE_EN))
2188 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2189 if (ocp_data & LINK_ON_WAKE_EN)
2190 wolopts |= WAKE_PHY;
2192 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2193 if (ocp_data & UWF_EN)
2194 wolopts |= WAKE_UCAST;
2195 if (ocp_data & BWF_EN)
2196 wolopts |= WAKE_BCAST;
2197 if (ocp_data & MWF_EN)
2198 wolopts |= WAKE_MCAST;
2200 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2201 if (ocp_data & MAGIC_EN)
2202 wolopts |= WAKE_MAGIC;
2207 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2211 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2213 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2214 ocp_data &= ~LINK_ON_WAKE_EN;
2215 if (wolopts & WAKE_PHY)
2216 ocp_data |= LINK_ON_WAKE_EN;
2217 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2219 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2220 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2221 if (wolopts & WAKE_UCAST)
2223 if (wolopts & WAKE_BCAST)
2225 if (wolopts & WAKE_MCAST)
2227 if (wolopts & WAKE_ANY)
2228 ocp_data |= LAN_WAKE_EN;
2229 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2231 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2233 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2234 ocp_data &= ~MAGIC_EN;
2235 if (wolopts & WAKE_MAGIC)
2236 ocp_data |= MAGIC_EN;
2237 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2239 if (wolopts & WAKE_ANY)
2240 device_set_wakeup_enable(&tp->udev->dev, true);
2242 device_set_wakeup_enable(&tp->udev->dev, false);
2245 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2250 __rtl_set_wol(tp, WAKE_ANY);
2252 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2254 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2255 ocp_data |= LINK_OFF_WAKE_EN;
2256 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2258 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2260 __rtl_set_wol(tp, tp->saved_wolopts);
2264 static void rtl_phy_reset(struct r8152 *tp)
2269 clear_bit(PHY_RESET, &tp->flags);
2271 data = r8152_mdio_read(tp, MII_BMCR);
2273 /* don't reset again before the previous one complete */
2274 if (data & BMCR_RESET)
2278 r8152_mdio_write(tp, MII_BMCR, data);
2280 for (i = 0; i < 50; i++) {
2282 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2287 static void r8153_teredo_off(struct r8152 *tp)
2291 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2292 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2293 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2296 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2297 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2300 static void r8152b_disable_aldps(struct r8152 *tp)
2302 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2306 static inline void r8152b_enable_aldps(struct r8152 *tp)
2308 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2309 LINKENA | DIS_SDSAVE);
2312 static void rtl8152_disable(struct r8152 *tp)
2314 r8152b_disable_aldps(tp);
2316 r8152b_enable_aldps(tp);
2319 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2323 data = r8152_mdio_read(tp, MII_BMCR);
2324 if (data & BMCR_PDOWN) {
2325 data &= ~BMCR_PDOWN;
2326 r8152_mdio_write(tp, MII_BMCR, data);
2329 set_bit(PHY_RESET, &tp->flags);
2332 static void r8152b_exit_oob(struct r8152 *tp)
2337 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2338 ocp_data &= ~RCR_ACPT_ALL;
2339 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2341 rxdy_gated_en(tp, true);
2342 r8153_teredo_off(tp);
2343 r8152b_hw_phy_cfg(tp);
2345 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2346 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2348 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2349 ocp_data &= ~NOW_IS_OOB;
2350 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2352 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2353 ocp_data &= ~MCU_BORW_EN;
2354 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2356 for (i = 0; i < 1000; i++) {
2357 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2358 if (ocp_data & LINK_LIST_READY)
2360 usleep_range(1000, 2000);
2363 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2364 ocp_data |= RE_INIT_LL;
2365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2367 for (i = 0; i < 1000; i++) {
2368 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2369 if (ocp_data & LINK_LIST_READY)
2371 usleep_range(1000, 2000);
2374 rtl8152_nic_reset(tp);
2376 /* rx share fifo credit full threshold */
2377 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2379 if (tp->udev->speed == USB_SPEED_FULL ||
2380 tp->udev->speed == USB_SPEED_LOW) {
2381 /* rx share fifo credit near full threshold */
2382 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2384 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2387 /* rx share fifo credit near full threshold */
2388 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2390 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2394 /* TX share fifo free credit full threshold */
2395 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2397 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2398 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2399 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2400 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2402 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2404 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2406 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2407 ocp_data |= TCR0_AUTO_FIFO;
2408 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2411 static void r8152b_enter_oob(struct r8152 *tp)
2416 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2417 ocp_data &= ~NOW_IS_OOB;
2418 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2420 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2421 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2422 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2426 for (i = 0; i < 1000; i++) {
2427 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2428 if (ocp_data & LINK_LIST_READY)
2430 usleep_range(1000, 2000);
2433 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2434 ocp_data |= RE_INIT_LL;
2435 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2437 for (i = 0; i < 1000; i++) {
2438 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2439 if (ocp_data & LINK_LIST_READY)
2441 usleep_range(1000, 2000);
2444 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2446 rtl_rx_vlan_en(tp, true);
2448 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2449 ocp_data |= ALDPS_PROXY_MODE;
2450 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2452 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2453 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2454 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2456 rxdy_gated_en(tp, false);
2458 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2459 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2460 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2463 static void r8153_hw_phy_cfg(struct r8152 *tp)
2468 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2469 data = r8152_mdio_read(tp, MII_BMCR);
2470 if (data & BMCR_PDOWN) {
2471 data &= ~BMCR_PDOWN;
2472 r8152_mdio_write(tp, MII_BMCR, data);
2475 if (tp->version == RTL_VER_03) {
2476 data = ocp_reg_read(tp, OCP_EEE_CFG);
2477 data &= ~CTAP_SHORT_EN;
2478 ocp_reg_write(tp, OCP_EEE_CFG, data);
2481 data = ocp_reg_read(tp, OCP_POWER_CFG);
2482 data |= EEE_CLKDIV_EN;
2483 ocp_reg_write(tp, OCP_POWER_CFG, data);
2485 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2486 data |= EN_10M_BGOFF;
2487 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2488 data = ocp_reg_read(tp, OCP_POWER_CFG);
2489 data |= EN_10M_PLLOFF;
2490 ocp_reg_write(tp, OCP_POWER_CFG, data);
2491 data = sram_read(tp, SRAM_IMPEDANCE);
2492 data &= ~RX_DRIVING_MASK;
2493 sram_write(tp, SRAM_IMPEDANCE, data);
2495 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2496 ocp_data |= PFM_PWM_SWITCH;
2497 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2499 data = sram_read(tp, SRAM_LPF_CFG);
2500 data |= LPF_AUTO_TUNE;
2501 sram_write(tp, SRAM_LPF_CFG, data);
2503 data = sram_read(tp, SRAM_10M_AMP1);
2504 data |= GDAC_IB_UPALL;
2505 sram_write(tp, SRAM_10M_AMP1, data);
2506 data = sram_read(tp, SRAM_10M_AMP2);
2508 sram_write(tp, SRAM_10M_AMP2, data);
2510 set_bit(PHY_RESET, &tp->flags);
2513 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2518 memset(u1u2, 0xff, sizeof(u1u2));
2520 memset(u1u2, 0x00, sizeof(u1u2));
2522 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2525 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2529 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2531 ocp_data |= U2P3_ENABLE;
2533 ocp_data &= ~U2P3_ENABLE;
2534 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2537 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2541 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2543 ocp_data |= PWR_EN | PHASE2_EN;
2545 ocp_data &= ~(PWR_EN | PHASE2_EN);
2546 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2548 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2549 ocp_data &= ~PCUT_STATUS;
2550 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2553 static void r8153_first_init(struct r8152 *tp)
2558 rxdy_gated_en(tp, true);
2559 r8153_teredo_off(tp);
2561 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2562 ocp_data &= ~RCR_ACPT_ALL;
2563 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2565 r8153_hw_phy_cfg(tp);
2567 rtl8152_nic_reset(tp);
2569 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2570 ocp_data &= ~NOW_IS_OOB;
2571 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2573 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2574 ocp_data &= ~MCU_BORW_EN;
2575 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2577 for (i = 0; i < 1000; i++) {
2578 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2579 if (ocp_data & LINK_LIST_READY)
2581 usleep_range(1000, 2000);
2584 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2585 ocp_data |= RE_INIT_LL;
2586 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2588 for (i = 0; i < 1000; i++) {
2589 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2590 if (ocp_data & LINK_LIST_READY)
2592 usleep_range(1000, 2000);
2595 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2597 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2598 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2600 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2601 ocp_data |= TCR0_AUTO_FIFO;
2602 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2604 rtl8152_nic_reset(tp);
2606 /* rx share fifo credit full threshold */
2607 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2608 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2609 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2610 /* TX share fifo free credit full threshold */
2611 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2613 /* rx aggregation */
2614 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2615 ocp_data &= ~RX_AGG_DISABLE;
2616 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2619 static void r8153_enter_oob(struct r8152 *tp)
2624 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2625 ocp_data &= ~NOW_IS_OOB;
2626 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2630 for (i = 0; i < 1000; i++) {
2631 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2632 if (ocp_data & LINK_LIST_READY)
2634 usleep_range(1000, 2000);
2637 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2638 ocp_data |= RE_INIT_LL;
2639 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2641 for (i = 0; i < 1000; i++) {
2642 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2643 if (ocp_data & LINK_LIST_READY)
2645 usleep_range(1000, 2000);
2648 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2650 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2651 ocp_data &= ~TEREDO_WAKE_MASK;
2652 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2654 rtl_rx_vlan_en(tp, true);
2656 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2657 ocp_data |= ALDPS_PROXY_MODE;
2658 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2660 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2661 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2662 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2664 rxdy_gated_en(tp, false);
2666 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2667 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2668 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2671 static void r8153_disable_aldps(struct r8152 *tp)
2675 data = ocp_reg_read(tp, OCP_POWER_CFG);
2677 ocp_reg_write(tp, OCP_POWER_CFG, data);
2681 static void r8153_enable_aldps(struct r8152 *tp)
2685 data = ocp_reg_read(tp, OCP_POWER_CFG);
2687 ocp_reg_write(tp, OCP_POWER_CFG, data);
2690 static void rtl8153_disable(struct r8152 *tp)
2692 r8153_disable_aldps(tp);
2694 r8153_enable_aldps(tp);
2697 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2699 u16 bmcr, anar, gbcr;
2702 cancel_delayed_work_sync(&tp->schedule);
2703 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2704 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2705 ADVERTISE_100HALF | ADVERTISE_100FULL);
2706 if (tp->mii.supports_gmii) {
2707 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2708 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2713 if (autoneg == AUTONEG_DISABLE) {
2714 if (speed == SPEED_10) {
2716 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2717 } else if (speed == SPEED_100) {
2718 bmcr = BMCR_SPEED100;
2719 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2720 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2721 bmcr = BMCR_SPEED1000;
2722 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2728 if (duplex == DUPLEX_FULL)
2729 bmcr |= BMCR_FULLDPLX;
2731 if (speed == SPEED_10) {
2732 if (duplex == DUPLEX_FULL)
2733 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2735 anar |= ADVERTISE_10HALF;
2736 } else if (speed == SPEED_100) {
2737 if (duplex == DUPLEX_FULL) {
2738 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2739 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2741 anar |= ADVERTISE_10HALF;
2742 anar |= ADVERTISE_100HALF;
2744 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2745 if (duplex == DUPLEX_FULL) {
2746 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2747 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2748 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2750 anar |= ADVERTISE_10HALF;
2751 anar |= ADVERTISE_100HALF;
2752 gbcr |= ADVERTISE_1000HALF;
2759 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2762 if (test_bit(PHY_RESET, &tp->flags))
2765 if (tp->mii.supports_gmii)
2766 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2768 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2769 r8152_mdio_write(tp, MII_BMCR, bmcr);
2771 if (test_bit(PHY_RESET, &tp->flags)) {
2774 clear_bit(PHY_RESET, &tp->flags);
2775 for (i = 0; i < 50; i++) {
2777 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2787 static void rtl8152_up(struct r8152 *tp)
2789 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2792 r8152b_disable_aldps(tp);
2793 r8152b_exit_oob(tp);
2794 r8152b_enable_aldps(tp);
2797 static void rtl8152_down(struct r8152 *tp)
2799 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2800 rtl_drop_queued_tx(tp);
2804 r8152_power_cut_en(tp, false);
2805 r8152b_disable_aldps(tp);
2806 r8152b_enter_oob(tp);
2807 r8152b_enable_aldps(tp);
2810 static void rtl8153_up(struct r8152 *tp)
2812 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2815 r8153_disable_aldps(tp);
2816 r8153_first_init(tp);
2817 r8153_enable_aldps(tp);
2820 static void rtl8153_down(struct r8152 *tp)
2822 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2823 rtl_drop_queued_tx(tp);
2827 r8153_u1u2en(tp, false);
2828 r8153_power_cut_en(tp, false);
2829 r8153_disable_aldps(tp);
2830 r8153_enter_oob(tp);
2831 r8153_enable_aldps(tp);
2834 static void set_carrier(struct r8152 *tp)
2836 struct net_device *netdev = tp->netdev;
2839 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2840 speed = rtl8152_get_speed(tp);
2842 if (speed & LINK_STATUS) {
2843 if (!(tp->speed & LINK_STATUS)) {
2844 tp->rtl_ops.enable(tp);
2845 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2846 netif_carrier_on(netdev);
2849 if (tp->speed & LINK_STATUS) {
2850 netif_carrier_off(netdev);
2851 tasklet_disable(&tp->tl);
2852 tp->rtl_ops.disable(tp);
2853 tasklet_enable(&tp->tl);
2859 static void rtl_work_func_t(struct work_struct *work)
2861 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2863 if (usb_autopm_get_interface(tp->intf) < 0)
2866 if (!test_bit(WORK_ENABLE, &tp->flags))
2869 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2872 if (!mutex_trylock(&tp->control)) {
2873 schedule_delayed_work(&tp->schedule, 0);
2877 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2880 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2881 _rtl8152_set_rx_mode(tp->netdev);
2883 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2884 (tp->speed & LINK_STATUS)) {
2885 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2886 tasklet_schedule(&tp->tl);
2889 if (test_bit(PHY_RESET, &tp->flags))
2892 mutex_unlock(&tp->control);
2895 usb_autopm_put_interface(tp->intf);
2898 static int rtl8152_open(struct net_device *netdev)
2900 struct r8152 *tp = netdev_priv(netdev);
2903 res = alloc_all_mem(tp);
2907 /* set speed to 0 to avoid autoresume try to submit rx */
2910 res = usb_autopm_get_interface(tp->intf);
2916 mutex_lock(&tp->control);
2918 /* The WORK_ENABLE may be set when autoresume occurs */
2919 if (test_bit(WORK_ENABLE, &tp->flags)) {
2920 clear_bit(WORK_ENABLE, &tp->flags);
2921 usb_kill_urb(tp->intr_urb);
2922 cancel_delayed_work_sync(&tp->schedule);
2924 /* disable the tx/rx, if the workqueue has enabled them. */
2925 if (tp->speed & LINK_STATUS)
2926 tp->rtl_ops.disable(tp);
2931 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2932 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2935 netif_carrier_off(netdev);
2936 netif_start_queue(netdev);
2937 set_bit(WORK_ENABLE, &tp->flags);
2939 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2942 netif_device_detach(tp->netdev);
2943 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2947 tasklet_enable(&tp->tl);
2950 mutex_unlock(&tp->control);
2952 usb_autopm_put_interface(tp->intf);
2958 static int rtl8152_close(struct net_device *netdev)
2960 struct r8152 *tp = netdev_priv(netdev);
2963 tasklet_disable(&tp->tl);
2964 clear_bit(WORK_ENABLE, &tp->flags);
2965 usb_kill_urb(tp->intr_urb);
2966 cancel_delayed_work_sync(&tp->schedule);
2967 netif_stop_queue(netdev);
2969 res = usb_autopm_get_interface(tp->intf);
2971 rtl_drop_queued_tx(tp);
2973 mutex_lock(&tp->control);
2975 /* The autosuspend may have been enabled and wouldn't
2976 * be disable when autoresume occurs, because the
2977 * netif_running() would be false.
2979 rtl_runtime_suspend_enable(tp, false);
2981 tp->rtl_ops.down(tp);
2983 mutex_unlock(&tp->control);
2985 usb_autopm_put_interface(tp->intf);
2993 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2995 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2996 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2997 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3000 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3004 r8152_mmd_indirect(tp, dev, reg);
3005 data = ocp_reg_read(tp, OCP_EEE_DATA);
3006 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3011 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3013 r8152_mmd_indirect(tp, dev, reg);
3014 ocp_reg_write(tp, OCP_EEE_DATA, data);
3015 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3018 static void r8152_eee_en(struct r8152 *tp, bool enable)
3020 u16 config1, config2, config3;
3023 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3024 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3025 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3026 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3029 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3030 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3031 config1 |= sd_rise_time(1);
3032 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3033 config3 |= fast_snr(42);
3035 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3036 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3038 config1 |= sd_rise_time(7);
3039 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3040 config3 |= fast_snr(511);
3043 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3044 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3045 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3046 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3049 static void r8152b_enable_eee(struct r8152 *tp)
3051 r8152_eee_en(tp, true);
3052 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3055 static void r8153_eee_en(struct r8152 *tp, bool enable)
3060 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3061 config = ocp_reg_read(tp, OCP_EEE_CFG);
3064 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3067 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3068 config &= ~EEE10_EN;
3071 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3072 ocp_reg_write(tp, OCP_EEE_CFG, config);
3075 static void r8153_enable_eee(struct r8152 *tp)
3077 r8153_eee_en(tp, true);
3078 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3081 static void r8152b_enable_fc(struct r8152 *tp)
3085 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3086 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3087 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3090 static void rtl_tally_reset(struct r8152 *tp)
3094 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3095 ocp_data |= TALLY_RESET;
3096 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3099 static void r8152b_init(struct r8152 *tp)
3103 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3106 r8152b_disable_aldps(tp);
3108 if (tp->version == RTL_VER_01) {
3109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3110 ocp_data &= ~LED_MODE_MASK;
3111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3114 r8152_power_cut_en(tp, false);
3116 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3117 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3119 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3120 ocp_data &= ~MCU_CLK_RATIO_MASK;
3121 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3122 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3123 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3124 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3125 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3127 r8152b_enable_eee(tp);
3128 r8152b_enable_aldps(tp);
3129 r8152b_enable_fc(tp);
3130 rtl_tally_reset(tp);
3132 /* enable rx aggregation */
3133 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3134 ocp_data &= ~RX_AGG_DISABLE;
3135 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3138 static void r8153_init(struct r8152 *tp)
3143 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3146 r8153_disable_aldps(tp);
3147 r8153_u1u2en(tp, false);
3149 for (i = 0; i < 500; i++) {
3150 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3156 for (i = 0; i < 500; i++) {
3157 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3158 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3163 r8153_u2p3en(tp, false);
3165 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3166 ocp_data &= ~TIMER11_EN;
3167 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3169 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3170 ocp_data &= ~LED_MODE_MASK;
3171 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3173 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3174 ocp_data &= ~LPM_TIMER_MASK;
3175 if (tp->udev->speed == USB_SPEED_SUPER)
3176 ocp_data |= LPM_TIMER_500US;
3178 ocp_data |= LPM_TIMER_500MS;
3179 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3181 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3182 ocp_data &= ~SEN_VAL_MASK;
3183 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3184 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3186 r8153_power_cut_en(tp, false);
3187 r8153_u1u2en(tp, true);
3189 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3190 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3191 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3192 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3193 U1U2_SPDWN_EN | L1_SPDWN_EN);
3194 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3195 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3196 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3199 r8153_enable_eee(tp);
3200 r8153_enable_aldps(tp);
3201 r8152b_enable_fc(tp);
3202 rtl_tally_reset(tp);
3205 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3207 struct r8152 *tp = usb_get_intfdata(intf);
3208 struct net_device *netdev = tp->netdev;
3211 mutex_lock(&tp->control);
3213 if (PMSG_IS_AUTO(message)) {
3214 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3219 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3221 netif_device_detach(netdev);
3224 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3225 clear_bit(WORK_ENABLE, &tp->flags);
3226 usb_kill_urb(tp->intr_urb);
3227 tasklet_disable(&tp->tl);
3228 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3230 rtl_runtime_suspend_enable(tp, true);
3232 cancel_delayed_work_sync(&tp->schedule);
3233 tp->rtl_ops.down(tp);
3235 tasklet_enable(&tp->tl);
3238 mutex_unlock(&tp->control);
3243 static int rtl8152_resume(struct usb_interface *intf)
3245 struct r8152 *tp = usb_get_intfdata(intf);
3247 mutex_lock(&tp->control);
3249 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3250 tp->rtl_ops.init(tp);
3251 netif_device_attach(tp->netdev);
3254 if (netif_running(tp->netdev)) {
3255 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3256 rtl_runtime_suspend_enable(tp, false);
3257 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3258 set_bit(WORK_ENABLE, &tp->flags);
3259 if (tp->speed & LINK_STATUS)
3263 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3264 tp->mii.supports_gmii ?
3265 SPEED_1000 : SPEED_100,
3268 netif_carrier_off(tp->netdev);
3269 set_bit(WORK_ENABLE, &tp->flags);
3271 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3272 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3273 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3276 mutex_unlock(&tp->control);
3281 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3283 struct r8152 *tp = netdev_priv(dev);
3285 if (usb_autopm_get_interface(tp->intf) < 0)
3288 mutex_lock(&tp->control);
3290 wol->supported = WAKE_ANY;
3291 wol->wolopts = __rtl_get_wol(tp);
3293 mutex_unlock(&tp->control);
3295 usb_autopm_put_interface(tp->intf);
3298 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3300 struct r8152 *tp = netdev_priv(dev);
3303 ret = usb_autopm_get_interface(tp->intf);
3307 mutex_lock(&tp->control);
3309 __rtl_set_wol(tp, wol->wolopts);
3310 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3312 mutex_unlock(&tp->control);
3314 usb_autopm_put_interface(tp->intf);
3320 static u32 rtl8152_get_msglevel(struct net_device *dev)
3322 struct r8152 *tp = netdev_priv(dev);
3324 return tp->msg_enable;
3327 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3329 struct r8152 *tp = netdev_priv(dev);
3331 tp->msg_enable = value;
3334 static void rtl8152_get_drvinfo(struct net_device *netdev,
3335 struct ethtool_drvinfo *info)
3337 struct r8152 *tp = netdev_priv(netdev);
3339 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3340 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3341 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3345 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3347 struct r8152 *tp = netdev_priv(netdev);
3350 if (!tp->mii.mdio_read)
3353 ret = usb_autopm_get_interface(tp->intf);
3357 mutex_lock(&tp->control);
3359 ret = mii_ethtool_gset(&tp->mii, cmd);
3361 mutex_unlock(&tp->control);
3363 usb_autopm_put_interface(tp->intf);
3369 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3371 struct r8152 *tp = netdev_priv(dev);
3374 ret = usb_autopm_get_interface(tp->intf);
3378 mutex_lock(&tp->control);
3380 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3382 mutex_unlock(&tp->control);
3384 usb_autopm_put_interface(tp->intf);
3390 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3397 "tx_single_collisions",
3398 "tx_multi_collisions",
3406 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3410 return ARRAY_SIZE(rtl8152_gstrings);
3416 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3417 struct ethtool_stats *stats, u64 *data)
3419 struct r8152 *tp = netdev_priv(dev);
3420 struct tally_counter tally;
3422 if (usb_autopm_get_interface(tp->intf) < 0)
3425 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3427 usb_autopm_put_interface(tp->intf);
3429 data[0] = le64_to_cpu(tally.tx_packets);
3430 data[1] = le64_to_cpu(tally.rx_packets);
3431 data[2] = le64_to_cpu(tally.tx_errors);
3432 data[3] = le32_to_cpu(tally.rx_errors);
3433 data[4] = le16_to_cpu(tally.rx_missed);
3434 data[5] = le16_to_cpu(tally.align_errors);
3435 data[6] = le32_to_cpu(tally.tx_one_collision);
3436 data[7] = le32_to_cpu(tally.tx_multi_collision);
3437 data[8] = le64_to_cpu(tally.rx_unicast);
3438 data[9] = le64_to_cpu(tally.rx_broadcast);
3439 data[10] = le32_to_cpu(tally.rx_multicast);
3440 data[11] = le16_to_cpu(tally.tx_aborted);
3441 data[12] = le16_to_cpu(tally.tx_underrun);
3444 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3446 switch (stringset) {
3448 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3453 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3455 u32 ocp_data, lp, adv, supported = 0;
3458 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3459 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3461 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3462 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3464 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3465 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3467 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3468 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3470 eee->eee_enabled = !!ocp_data;
3471 eee->eee_active = !!(supported & adv & lp);
3472 eee->supported = supported;
3473 eee->advertised = adv;
3474 eee->lp_advertised = lp;
3479 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3481 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3483 r8152_eee_en(tp, eee->eee_enabled);
3485 if (!eee->eee_enabled)
3488 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3493 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3495 u32 ocp_data, lp, adv, supported = 0;
3498 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3499 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3501 val = ocp_reg_read(tp, OCP_EEE_ADV);
3502 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3504 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3505 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3507 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3508 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3510 eee->eee_enabled = !!ocp_data;
3511 eee->eee_active = !!(supported & adv & lp);
3512 eee->supported = supported;
3513 eee->advertised = adv;
3514 eee->lp_advertised = lp;
3519 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3521 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3523 r8153_eee_en(tp, eee->eee_enabled);
3525 if (!eee->eee_enabled)
3528 ocp_reg_write(tp, OCP_EEE_ADV, val);
3534 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3536 struct r8152 *tp = netdev_priv(net);
3539 ret = usb_autopm_get_interface(tp->intf);
3543 mutex_lock(&tp->control);
3545 ret = tp->rtl_ops.eee_get(tp, edata);
3547 mutex_unlock(&tp->control);
3549 usb_autopm_put_interface(tp->intf);
3556 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3558 struct r8152 *tp = netdev_priv(net);
3561 ret = usb_autopm_get_interface(tp->intf);
3565 mutex_lock(&tp->control);
3567 ret = tp->rtl_ops.eee_set(tp, edata);
3569 ret = mii_nway_restart(&tp->mii);
3571 mutex_unlock(&tp->control);
3573 usb_autopm_put_interface(tp->intf);
3579 static int rtl8152_nway_reset(struct net_device *dev)
3581 struct r8152 *tp = netdev_priv(dev);
3584 ret = usb_autopm_get_interface(tp->intf);
3588 mutex_lock(&tp->control);
3590 ret = mii_nway_restart(&tp->mii);
3592 mutex_unlock(&tp->control);
3594 usb_autopm_put_interface(tp->intf);
3600 static struct ethtool_ops ops = {
3601 .get_drvinfo = rtl8152_get_drvinfo,
3602 .get_settings = rtl8152_get_settings,
3603 .set_settings = rtl8152_set_settings,
3604 .get_link = ethtool_op_get_link,
3605 .nway_reset = rtl8152_nway_reset,
3606 .get_msglevel = rtl8152_get_msglevel,
3607 .set_msglevel = rtl8152_set_msglevel,
3608 .get_wol = rtl8152_get_wol,
3609 .set_wol = rtl8152_set_wol,
3610 .get_strings = rtl8152_get_strings,
3611 .get_sset_count = rtl8152_get_sset_count,
3612 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3613 .get_eee = rtl_ethtool_get_eee,
3614 .set_eee = rtl_ethtool_set_eee,
3617 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3619 struct r8152 *tp = netdev_priv(netdev);
3620 struct mii_ioctl_data *data = if_mii(rq);
3623 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3626 res = usb_autopm_get_interface(tp->intf);
3632 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3636 mutex_lock(&tp->control);
3637 data->val_out = r8152_mdio_read(tp, data->reg_num);
3638 mutex_unlock(&tp->control);
3642 if (!capable(CAP_NET_ADMIN)) {
3646 mutex_lock(&tp->control);
3647 r8152_mdio_write(tp, data->reg_num, data->val_in);
3648 mutex_unlock(&tp->control);
3655 usb_autopm_put_interface(tp->intf);
3661 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3663 struct r8152 *tp = netdev_priv(dev);
3665 switch (tp->version) {
3668 return eth_change_mtu(dev, new_mtu);
3673 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3681 static const struct net_device_ops rtl8152_netdev_ops = {
3682 .ndo_open = rtl8152_open,
3683 .ndo_stop = rtl8152_close,
3684 .ndo_do_ioctl = rtl8152_ioctl,
3685 .ndo_start_xmit = rtl8152_start_xmit,
3686 .ndo_tx_timeout = rtl8152_tx_timeout,
3687 .ndo_set_features = rtl8152_set_features,
3688 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3689 .ndo_set_mac_address = rtl8152_set_mac_address,
3690 .ndo_change_mtu = rtl8152_change_mtu,
3691 .ndo_validate_addr = eth_validate_addr,
3694 static void r8152b_get_version(struct r8152 *tp)
3699 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3700 version = (u16)(ocp_data & VERSION_MASK);
3704 tp->version = RTL_VER_01;
3707 tp->version = RTL_VER_02;
3710 tp->version = RTL_VER_03;
3711 tp->mii.supports_gmii = 1;
3714 tp->version = RTL_VER_04;
3715 tp->mii.supports_gmii = 1;
3718 tp->version = RTL_VER_05;
3719 tp->mii.supports_gmii = 1;
3722 netif_info(tp, probe, tp->netdev,
3723 "Unknown version 0x%04x\n", version);
3728 static void rtl8152_unload(struct r8152 *tp)
3730 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3733 if (tp->version != RTL_VER_01)
3734 r8152_power_cut_en(tp, true);
3737 static void rtl8153_unload(struct r8152 *tp)
3739 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3742 r8153_power_cut_en(tp, false);
3745 static int rtl_ops_init(struct r8152 *tp)
3747 struct rtl_ops *ops = &tp->rtl_ops;
3750 switch (tp->version) {
3753 ops->init = r8152b_init;
3754 ops->enable = rtl8152_enable;
3755 ops->disable = rtl8152_disable;
3756 ops->up = rtl8152_up;
3757 ops->down = rtl8152_down;
3758 ops->unload = rtl8152_unload;
3759 ops->eee_get = r8152_get_eee;
3760 ops->eee_set = r8152_set_eee;
3766 ops->init = r8153_init;
3767 ops->enable = rtl8153_enable;
3768 ops->disable = rtl8153_disable;
3769 ops->up = rtl8153_up;
3770 ops->down = rtl8153_down;
3771 ops->unload = rtl8153_unload;
3772 ops->eee_get = r8153_get_eee;
3773 ops->eee_set = r8153_set_eee;
3778 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3785 static int rtl8152_probe(struct usb_interface *intf,
3786 const struct usb_device_id *id)
3788 struct usb_device *udev = interface_to_usbdev(intf);
3790 struct net_device *netdev;
3793 if (udev->actconfig->desc.bConfigurationValue != 1) {
3794 usb_driver_set_configuration(udev, 1);
3798 usb_reset_device(udev);
3799 netdev = alloc_etherdev(sizeof(struct r8152));
3801 dev_err(&intf->dev, "Out of memory\n");
3805 SET_NETDEV_DEV(netdev, &intf->dev);
3806 tp = netdev_priv(netdev);
3807 tp->msg_enable = 0x7FFF;
3810 tp->netdev = netdev;
3813 r8152b_get_version(tp);
3814 ret = rtl_ops_init(tp);
3818 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3819 mutex_init(&tp->control);
3820 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3822 netdev->netdev_ops = &rtl8152_netdev_ops;
3823 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3825 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3826 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3827 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3828 NETIF_F_HW_VLAN_CTAG_TX;
3829 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3830 NETIF_F_TSO | NETIF_F_FRAGLIST |
3831 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3832 NETIF_F_HW_VLAN_CTAG_RX |
3833 NETIF_F_HW_VLAN_CTAG_TX;
3834 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3835 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3836 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3838 netdev->ethtool_ops = &ops;
3839 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3841 tp->mii.dev = netdev;
3842 tp->mii.mdio_read = read_mii_word;
3843 tp->mii.mdio_write = write_mii_word;
3844 tp->mii.phy_id_mask = 0x3f;
3845 tp->mii.reg_num_mask = 0x1f;
3846 tp->mii.phy_id = R8152_PHY_ID;
3848 intf->needs_remote_wakeup = 1;
3850 tp->rtl_ops.init(tp);
3851 set_ethernet_addr(tp);
3853 usb_set_intfdata(intf, tp);
3855 ret = register_netdev(netdev);
3857 netif_err(tp, probe, netdev, "couldn't register the device\n");
3861 tp->saved_wolopts = __rtl_get_wol(tp);
3862 if (tp->saved_wolopts)
3863 device_set_wakeup_enable(&udev->dev, true);
3865 device_set_wakeup_enable(&udev->dev, false);
3867 tasklet_disable(&tp->tl);
3869 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3874 usb_set_intfdata(intf, NULL);
3875 tasklet_kill(&tp->tl);
3877 free_netdev(netdev);
3881 static void rtl8152_disconnect(struct usb_interface *intf)
3883 struct r8152 *tp = usb_get_intfdata(intf);
3885 usb_set_intfdata(intf, NULL);
3887 struct usb_device *udev = tp->udev;
3889 if (udev->state == USB_STATE_NOTATTACHED)
3890 set_bit(RTL8152_UNPLUG, &tp->flags);
3892 tasklet_kill(&tp->tl);
3893 unregister_netdev(tp->netdev);
3894 tp->rtl_ops.unload(tp);
3895 free_netdev(tp->netdev);
3899 /* table of devices that work with this driver */
3900 static struct usb_device_id rtl8152_table[] = {
3901 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3902 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3903 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3907 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3909 static struct usb_driver rtl8152_driver = {
3911 .id_table = rtl8152_table,
3912 .probe = rtl8152_probe,
3913 .disconnect = rtl8152_disconnect,
3914 .suspend = rtl8152_suspend,
3915 .resume = rtl8152_resume,
3916 .reset_resume = rtl8152_resume,
3917 .supports_autosuspend = 1,
3918 .disable_hub_initiated_lpm = 1,
3921 module_usb_driver(rtl8152_driver);
3923 MODULE_AUTHOR(DRIVER_AUTHOR);
3924 MODULE_DESCRIPTION(DRIVER_DESC);
3925 MODULE_LICENSE("GPL");