2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
29 /* Version Information */
30 #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
31 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
32 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
33 #define MODULENAME "r8152"
35 #define R8152_PHY_ID 32
37 #define PLA_IDR 0xc000
38 #define PLA_RCR 0xc010
39 #define PLA_RMS 0xc016
40 #define PLA_RXFIFO_CTRL0 0xc0a0
41 #define PLA_RXFIFO_CTRL1 0xc0a4
42 #define PLA_RXFIFO_CTRL2 0xc0a8
43 #define PLA_FMC 0xc0b4
44 #define PLA_CFG_WOL 0xc0b6
45 #define PLA_TEREDO_CFG 0xc0bc
46 #define PLA_MAR 0xcd00
47 #define PLA_BACKUP 0xd000
48 #define PAL_BDC_CR 0xd1a0
49 #define PLA_TEREDO_TIMER 0xd2cc
50 #define PLA_REALWOW_TIMER 0xd2e8
51 #define PLA_LEDSEL 0xdd90
52 #define PLA_LED_FEATURE 0xdd92
53 #define PLA_PHYAR 0xde00
54 #define PLA_BOOT_CTRL 0xe004
55 #define PLA_GPHY_INTR_IMR 0xe022
56 #define PLA_EEE_CR 0xe040
57 #define PLA_EEEP_CR 0xe080
58 #define PLA_MAC_PWR_CTRL 0xe0c0
59 #define PLA_MAC_PWR_CTRL2 0xe0ca
60 #define PLA_MAC_PWR_CTRL3 0xe0cc
61 #define PLA_MAC_PWR_CTRL4 0xe0ce
62 #define PLA_WDT6_CTRL 0xe428
63 #define PLA_TCR0 0xe610
64 #define PLA_TCR1 0xe612
65 #define PLA_MTPS 0xe615
66 #define PLA_TXFIFO_CTRL 0xe618
67 #define PLA_RSTTALLY 0xe800
69 #define PLA_CRWECR 0xe81c
70 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
71 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
72 #define PLA_CONFIG5 0xe822
73 #define PLA_PHY_PWR 0xe84c
74 #define PLA_OOB_CTRL 0xe84f
75 #define PLA_CPCR 0xe854
76 #define PLA_MISC_0 0xe858
77 #define PLA_MISC_1 0xe85a
78 #define PLA_OCP_GPHY_BASE 0xe86c
79 #define PLA_TALLYCNT 0xe890
80 #define PLA_SFF_STS_7 0xe8de
81 #define PLA_PHYSTATUS 0xe908
82 #define PLA_BP_BA 0xfc26
83 #define PLA_BP_0 0xfc28
84 #define PLA_BP_1 0xfc2a
85 #define PLA_BP_2 0xfc2c
86 #define PLA_BP_3 0xfc2e
87 #define PLA_BP_4 0xfc30
88 #define PLA_BP_5 0xfc32
89 #define PLA_BP_6 0xfc34
90 #define PLA_BP_7 0xfc36
91 #define PLA_BP_EN 0xfc38
93 #define USB_U2P3_CTRL 0xb460
94 #define USB_DEV_STAT 0xb808
95 #define USB_USB_CTRL 0xd406
96 #define USB_PHY_CTRL 0xd408
97 #define USB_TX_AGG 0xd40a
98 #define USB_RX_BUF_TH 0xd40c
99 #define USB_USB_TIMER 0xd428
100 #define USB_RX_EARLY_AGG 0xd42c
101 #define USB_PM_CTRL_STATUS 0xd432
102 #define USB_TX_DMA 0xd434
103 #define USB_TOLERANCE 0xd490
104 #define USB_LPM_CTRL 0xd41a
105 #define USB_UPS_CTRL 0xd800
106 #define USB_MISC_0 0xd81a
107 #define USB_POWER_CUT 0xd80a
108 #define USB_AFE_CTRL2 0xd824
109 #define USB_WDT11_CTRL 0xe43c
110 #define USB_BP_BA 0xfc26
111 #define USB_BP_0 0xfc28
112 #define USB_BP_1 0xfc2a
113 #define USB_BP_2 0xfc2c
114 #define USB_BP_3 0xfc2e
115 #define USB_BP_4 0xfc30
116 #define USB_BP_5 0xfc32
117 #define USB_BP_6 0xfc34
118 #define USB_BP_7 0xfc36
119 #define USB_BP_EN 0xfc38
122 #define OCP_ALDPS_CONFIG 0x2010
123 #define OCP_EEE_CONFIG1 0x2080
124 #define OCP_EEE_CONFIG2 0x2092
125 #define OCP_EEE_CONFIG3 0x2094
126 #define OCP_BASE_MII 0xa400
127 #define OCP_EEE_AR 0xa41a
128 #define OCP_EEE_DATA 0xa41c
129 #define OCP_PHY_STATUS 0xa420
130 #define OCP_POWER_CFG 0xa430
131 #define OCP_EEE_CFG 0xa432
132 #define OCP_SRAM_ADDR 0xa436
133 #define OCP_SRAM_DATA 0xa438
134 #define OCP_DOWN_SPEED 0xa442
135 #define OCP_EEE_ABLE 0xa5c4
136 #define OCP_EEE_ADV 0xa5d0
137 #define OCP_EEE_LPABLE 0xa5d2
138 #define OCP_ADC_CFG 0xbc06
141 #define SRAM_LPF_CFG 0x8012
142 #define SRAM_10M_AMP1 0x8080
143 #define SRAM_10M_AMP2 0x8082
144 #define SRAM_IMPEDANCE 0x8084
147 #define RCR_AAP 0x00000001
148 #define RCR_APM 0x00000002
149 #define RCR_AM 0x00000004
150 #define RCR_AB 0x00000008
151 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
153 /* PLA_RXFIFO_CTRL0 */
154 #define RXFIFO_THR1_NORMAL 0x00080002
155 #define RXFIFO_THR1_OOB 0x01800003
157 /* PLA_RXFIFO_CTRL1 */
158 #define RXFIFO_THR2_FULL 0x00000060
159 #define RXFIFO_THR2_HIGH 0x00000038
160 #define RXFIFO_THR2_OOB 0x0000004a
161 #define RXFIFO_THR2_NORMAL 0x00a0
163 /* PLA_RXFIFO_CTRL2 */
164 #define RXFIFO_THR3_FULL 0x00000078
165 #define RXFIFO_THR3_HIGH 0x00000048
166 #define RXFIFO_THR3_OOB 0x0000005a
167 #define RXFIFO_THR3_NORMAL 0x0110
169 /* PLA_TXFIFO_CTRL */
170 #define TXFIFO_THR_NORMAL 0x00400008
171 #define TXFIFO_THR_NORMAL2 0x01000008
174 #define FMC_FCR_MCU_EN 0x0001
177 #define EEEP_CR_EEEP_TX 0x0002
180 #define WDT6_SET_MODE 0x0010
183 #define TCR0_TX_EMPTY 0x0800
184 #define TCR0_AUTO_FIFO 0x0080
187 #define VERSION_MASK 0x7cf0
190 #define MTPS_JUMBO (12 * 1024 / 64)
191 #define MTPS_DEFAULT (6 * 1024 / 64)
194 #define TALLY_RESET 0x0001
202 #define CRWECR_NORAML 0x00
203 #define CRWECR_CONFIG 0xc0
206 #define NOW_IS_OOB 0x80
207 #define TXFIFO_EMPTY 0x20
208 #define RXFIFO_EMPTY 0x10
209 #define LINK_LIST_READY 0x02
210 #define DIS_MCU_CLROOB 0x01
211 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
214 #define RXDY_GATED_EN 0x0008
217 #define RE_INIT_LL 0x8000
218 #define MCU_BORW_EN 0x4000
221 #define CPCR_RX_VLAN 0x0040
224 #define MAGIC_EN 0x0001
227 #define TEREDO_SEL 0x8000
228 #define TEREDO_WAKE_MASK 0x7f00
229 #define TEREDO_RS_EVENT_MASK 0x00fe
230 #define OOB_TEREDO_EN 0x0001
233 #define ALDPS_PROXY_MODE 0x0001
236 #define LINK_ON_WAKE_EN 0x0010
237 #define LINK_OFF_WAKE_EN 0x0008
240 #define BWF_EN 0x0040
241 #define MWF_EN 0x0020
242 #define UWF_EN 0x0010
243 #define LAN_WAKE_EN 0x0002
245 /* PLA_LED_FEATURE */
246 #define LED_MODE_MASK 0x0700
249 #define TX_10M_IDLE_EN 0x0080
250 #define PFM_PWM_SWITCH 0x0040
252 /* PLA_MAC_PWR_CTRL */
253 #define D3_CLK_GATED_EN 0x00004000
254 #define MCU_CLK_RATIO 0x07010f07
255 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
256 #define ALDPS_SPDWN_RATIO 0x0f87
258 /* PLA_MAC_PWR_CTRL2 */
259 #define EEE_SPDWN_RATIO 0x8007
261 /* PLA_MAC_PWR_CTRL3 */
262 #define PKT_AVAIL_SPDWN_EN 0x0100
263 #define SUSPEND_SPDWN_EN 0x0004
264 #define U1U2_SPDWN_EN 0x0002
265 #define L1_SPDWN_EN 0x0001
267 /* PLA_MAC_PWR_CTRL4 */
268 #define PWRSAVE_SPDWN_EN 0x1000
269 #define RXDV_SPDWN_EN 0x0800
270 #define TX10MIDLE_EN 0x0100
271 #define TP100_SPDWN_EN 0x0020
272 #define TP500_SPDWN_EN 0x0010
273 #define TP1000_SPDWN_EN 0x0008
274 #define EEE_SPDWN_EN 0x0001
276 /* PLA_GPHY_INTR_IMR */
277 #define GPHY_STS_MSK 0x0001
278 #define SPEED_DOWN_MSK 0x0002
279 #define SPDWN_RXDV_MSK 0x0004
280 #define SPDWN_LINKCHG_MSK 0x0008
283 #define PHYAR_FLAG 0x80000000
286 #define EEE_RX_EN 0x0001
287 #define EEE_TX_EN 0x0002
290 #define AUTOLOAD_DONE 0x0002
293 #define STAT_SPEED_MASK 0x0006
294 #define STAT_SPEED_HIGH 0x0000
295 #define STAT_SPEED_FULL 0x0002
298 #define TX_AGG_MAX_THRESHOLD 0x03
301 #define RX_THR_SUPPER 0x0c350180
302 #define RX_THR_HIGH 0x7a120180
303 #define RX_THR_SLOW 0xffff0180
306 #define TEST_MODE_DISABLE 0x00000001
307 #define TX_SIZE_ADJUST1 0x00000100
310 #define POWER_CUT 0x0100
312 /* USB_PM_CTRL_STATUS */
313 #define RESUME_INDICATE 0x0001
316 #define RX_AGG_DISABLE 0x0010
319 #define U2P3_ENABLE 0x0001
322 #define PWR_EN 0x0001
323 #define PHASE2_EN 0x0008
326 #define PCUT_STATUS 0x0001
328 /* USB_RX_EARLY_AGG */
329 #define EARLY_AGG_SUPPER 0x0e832981
330 #define EARLY_AGG_HIGH 0x0e837a12
331 #define EARLY_AGG_SLOW 0x0e83ffff
334 #define TIMER11_EN 0x0001
337 #define LPM_TIMER_MASK 0x0c
338 #define LPM_TIMER_500MS 0x04 /* 500 ms */
339 #define LPM_TIMER_500US 0x0c /* 500 us */
342 #define SEN_VAL_MASK 0xf800
343 #define SEN_VAL_NORMAL 0xa000
344 #define SEL_RXIDLE 0x0100
346 /* OCP_ALDPS_CONFIG */
347 #define ENPWRSAVE 0x8000
348 #define ENPDNPS 0x0200
349 #define LINKENA 0x0100
350 #define DIS_SDSAVE 0x0010
353 #define PHY_STAT_MASK 0x0007
354 #define PHY_STAT_LAN_ON 3
355 #define PHY_STAT_PWRDN 5
358 #define EEE_CLKDIV_EN 0x8000
359 #define EN_ALDPS 0x0004
360 #define EN_10M_PLLOFF 0x0001
362 /* OCP_EEE_CONFIG1 */
363 #define RG_TXLPI_MSK_HFDUP 0x8000
364 #define RG_MATCLR_EN 0x4000
365 #define EEE_10_CAP 0x2000
366 #define EEE_NWAY_EN 0x1000
367 #define TX_QUIET_EN 0x0200
368 #define RX_QUIET_EN 0x0100
369 #define sd_rise_time_mask 0x0070
370 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
371 #define RG_RXLPI_MSK_HFDUP 0x0008
372 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
374 /* OCP_EEE_CONFIG2 */
375 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
376 #define RG_DACQUIET_EN 0x0400
377 #define RG_LDVQUIET_EN 0x0200
378 #define RG_CKRSEL 0x0020
379 #define RG_EEEPRG_EN 0x0010
381 /* OCP_EEE_CONFIG3 */
382 #define fast_snr_mask 0xff80
383 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
384 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
385 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
388 /* bit[15:14] function */
389 #define FUN_ADDR 0x0000
390 #define FUN_DATA 0x4000
391 /* bit[4:0] device addr */
394 #define CTAP_SHORT_EN 0x0040
395 #define EEE10_EN 0x0010
398 #define EN_10M_BGOFF 0x0080
401 #define CKADSEL_L 0x0100
402 #define ADC_EN 0x0080
403 #define EN_EMI_L 0x0040
406 #define LPF_AUTO_TUNE 0x8000
409 #define GDAC_IB_UPALL 0x0008
412 #define AMP_DN 0x0200
415 #define RX_DRIVING_MASK 0x6000
417 enum rtl_register_content {
425 #define RTL8152_MAX_TX 4
426 #define RTL8152_MAX_RX 10
432 #define INTR_LINK 0x0004
434 #define RTL8152_REQT_READ 0xc0
435 #define RTL8152_REQT_WRITE 0x40
436 #define RTL8152_REQ_GET_REGS 0x05
437 #define RTL8152_REQ_SET_REGS 0x05
439 #define BYTE_EN_DWORD 0xff
440 #define BYTE_EN_WORD 0x33
441 #define BYTE_EN_BYTE 0x11
442 #define BYTE_EN_SIX_BYTES 0x3f
443 #define BYTE_EN_START_MASK 0x0f
444 #define BYTE_EN_END_MASK 0xf0
446 #define RTL8153_MAX_PACKET 9216 /* 9K */
447 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
448 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
449 #define RTL8153_RMS RTL8153_MAX_PACKET
450 #define RTL8152_TX_TIMEOUT (5 * HZ)
451 #define RTL8152_NAPI_WEIGHT 64
464 /* Define these values to match your device */
465 #define VENDOR_ID_REALTEK 0x0bda
466 #define VENDOR_ID_SAMSUNG 0x04e8
468 #define MCU_TYPE_PLA 0x0100
469 #define MCU_TYPE_USB 0x0000
471 struct tally_counter {
478 __le32 tx_one_collision;
479 __le32 tx_multi_collision;
489 #define RX_LEN_MASK 0x7fff
492 #define RD_UDP_CS BIT(23)
493 #define RD_TCP_CS BIT(22)
494 #define RD_IPV6_CS BIT(20)
495 #define RD_IPV4_CS BIT(19)
498 #define IPF BIT(23) /* IP checksum fail */
499 #define UDPF BIT(22) /* UDP checksum fail */
500 #define TCPF BIT(21) /* TCP checksum fail */
501 #define RX_VLAN_TAG BIT(16)
510 #define TX_FS BIT(31) /* First segment of a packet */
511 #define TX_LS BIT(30) /* Final segment of a packet */
512 #define GTSENDV4 BIT(28)
513 #define GTSENDV6 BIT(27)
514 #define GTTCPHO_SHIFT 18
515 #define GTTCPHO_MAX 0x7fU
516 #define TX_LEN_MAX 0x3ffffU
519 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
520 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
521 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
522 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
524 #define MSS_MAX 0x7ffU
525 #define TCPHO_SHIFT 17
526 #define TCPHO_MAX 0x7ffU
527 #define TX_VLAN_TAG BIT(16)
533 struct list_head list;
535 struct r8152 *context;
541 struct list_head list;
543 struct r8152 *context;
552 struct usb_device *udev;
553 struct napi_struct napi;
554 struct usb_interface *intf;
555 struct net_device *netdev;
556 struct urb *intr_urb;
557 struct tx_agg tx_info[RTL8152_MAX_TX];
558 struct rx_agg rx_info[RTL8152_MAX_RX];
559 struct list_head rx_done, tx_free;
560 struct sk_buff_head tx_queue, rx_queue;
561 spinlock_t rx_lock, tx_lock;
562 struct delayed_work schedule;
563 struct mii_if_info mii;
564 struct mutex control; /* use for hw setting */
567 void (*init)(struct r8152 *);
568 int (*enable)(struct r8152 *);
569 void (*disable)(struct r8152 *);
570 void (*up)(struct r8152 *);
571 void (*down)(struct r8152 *);
572 void (*unload)(struct r8152 *);
573 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
574 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
602 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
603 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
605 static const int multicast_filter_limit = 32;
606 static unsigned int agg_buf_sz = 16384;
608 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
609 VLAN_ETH_HLEN - VLAN_HLEN)
612 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
617 tmp = kmalloc(size, GFP_KERNEL);
621 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
622 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
623 value, index, tmp, size, 500);
625 memcpy(data, tmp, size);
632 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
637 tmp = kmemdup(data, size, GFP_KERNEL);
641 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
642 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
643 value, index, tmp, size, 500);
650 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
651 void *data, u16 type)
656 if (test_bit(RTL8152_UNPLUG, &tp->flags))
659 /* both size and indix must be 4 bytes align */
660 if ((size & 3) || !size || (index & 3) || !data)
663 if ((u32)index + (u32)size > 0xffff)
668 ret = get_registers(tp, index, type, limit, data);
676 ret = get_registers(tp, index, type, size, data);
688 set_bit(RTL8152_UNPLUG, &tp->flags);
693 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
694 u16 size, void *data, u16 type)
697 u16 byteen_start, byteen_end, byen;
700 if (test_bit(RTL8152_UNPLUG, &tp->flags))
703 /* both size and indix must be 4 bytes align */
704 if ((size & 3) || !size || (index & 3) || !data)
707 if ((u32)index + (u32)size > 0xffff)
710 byteen_start = byteen & BYTE_EN_START_MASK;
711 byteen_end = byteen & BYTE_EN_END_MASK;
713 byen = byteen_start | (byteen_start << 4);
714 ret = set_registers(tp, index, type | byen, 4, data);
727 ret = set_registers(tp, index,
728 type | BYTE_EN_DWORD,
737 ret = set_registers(tp, index,
738 type | BYTE_EN_DWORD,
750 byen = byteen_end | (byteen_end >> 4);
751 ret = set_registers(tp, index, type | byen, 4, data);
758 set_bit(RTL8152_UNPLUG, &tp->flags);
764 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
766 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
770 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
772 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
776 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
778 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
782 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
784 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
787 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
791 generic_ocp_read(tp, index, sizeof(data), &data, type);
793 return __le32_to_cpu(data);
796 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
798 __le32 tmp = __cpu_to_le32(data);
800 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
803 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
807 u8 shift = index & 2;
811 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
813 data = __le32_to_cpu(tmp);
814 data >>= (shift * 8);
820 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
824 u16 byen = BYTE_EN_WORD;
825 u8 shift = index & 2;
831 mask <<= (shift * 8);
832 data <<= (shift * 8);
836 tmp = __cpu_to_le32(data);
838 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
841 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
845 u8 shift = index & 3;
849 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
851 data = __le32_to_cpu(tmp);
852 data >>= (shift * 8);
858 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
862 u16 byen = BYTE_EN_BYTE;
863 u8 shift = index & 3;
869 mask <<= (shift * 8);
870 data <<= (shift * 8);
874 tmp = __cpu_to_le32(data);
876 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
879 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
881 u16 ocp_base, ocp_index;
883 ocp_base = addr & 0xf000;
884 if (ocp_base != tp->ocp_base) {
885 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
886 tp->ocp_base = ocp_base;
889 ocp_index = (addr & 0x0fff) | 0xb000;
890 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
893 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
895 u16 ocp_base, ocp_index;
897 ocp_base = addr & 0xf000;
898 if (ocp_base != tp->ocp_base) {
899 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
900 tp->ocp_base = ocp_base;
903 ocp_index = (addr & 0x0fff) | 0xb000;
904 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
907 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
909 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
912 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
914 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
917 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
919 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
920 ocp_reg_write(tp, OCP_SRAM_DATA, data);
923 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
925 struct r8152 *tp = netdev_priv(netdev);
928 if (test_bit(RTL8152_UNPLUG, &tp->flags))
931 if (phy_id != R8152_PHY_ID)
934 ret = r8152_mdio_read(tp, reg);
940 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
942 struct r8152 *tp = netdev_priv(netdev);
944 if (test_bit(RTL8152_UNPLUG, &tp->flags))
947 if (phy_id != R8152_PHY_ID)
950 r8152_mdio_write(tp, reg, val);
954 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
956 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
958 struct r8152 *tp = netdev_priv(netdev);
959 struct sockaddr *addr = p;
960 int ret = -EADDRNOTAVAIL;
962 if (!is_valid_ether_addr(addr->sa_data))
965 ret = usb_autopm_get_interface(tp->intf);
969 mutex_lock(&tp->control);
971 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
973 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
974 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
975 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
977 mutex_unlock(&tp->control);
979 usb_autopm_put_interface(tp->intf);
984 static int set_ethernet_addr(struct r8152 *tp)
986 struct net_device *dev = tp->netdev;
990 if (tp->version == RTL_VER_01)
991 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
993 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
996 netif_err(tp, probe, dev, "Get ether addr fail\n");
997 } else if (!is_valid_ether_addr(sa.sa_data)) {
998 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1000 eth_hw_addr_random(dev);
1001 ether_addr_copy(sa.sa_data, dev->dev_addr);
1002 ret = rtl8152_set_mac_address(dev, &sa);
1003 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1006 if (tp->version == RTL_VER_01)
1007 ether_addr_copy(dev->dev_addr, sa.sa_data);
1009 ret = rtl8152_set_mac_address(dev, &sa);
1015 static void read_bulk_callback(struct urb *urb)
1017 struct net_device *netdev;
1018 int status = urb->status;
1030 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1033 if (!test_bit(WORK_ENABLE, &tp->flags))
1036 netdev = tp->netdev;
1038 /* When link down, the driver would cancel all bulks. */
1039 /* This avoid the re-submitting bulk */
1040 if (!netif_carrier_ok(netdev))
1043 usb_mark_last_busy(tp->udev);
1047 if (urb->actual_length < ETH_ZLEN)
1050 spin_lock(&tp->rx_lock);
1051 list_add_tail(&agg->list, &tp->rx_done);
1052 spin_unlock(&tp->rx_lock);
1053 napi_schedule(&tp->napi);
1056 set_bit(RTL8152_UNPLUG, &tp->flags);
1057 netif_device_detach(tp->netdev);
1060 return; /* the urb is in unlink state */
1062 if (net_ratelimit())
1063 netdev_warn(netdev, "maybe reset is needed?\n");
1066 if (net_ratelimit())
1067 netdev_warn(netdev, "Rx status %d\n", status);
1071 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1074 static void write_bulk_callback(struct urb *urb)
1076 struct net_device_stats *stats;
1077 struct net_device *netdev;
1080 int status = urb->status;
1090 netdev = tp->netdev;
1091 stats = &netdev->stats;
1093 if (net_ratelimit())
1094 netdev_warn(netdev, "Tx status %d\n", status);
1095 stats->tx_errors += agg->skb_num;
1097 stats->tx_packets += agg->skb_num;
1098 stats->tx_bytes += agg->skb_len;
1101 spin_lock(&tp->tx_lock);
1102 list_add_tail(&agg->list, &tp->tx_free);
1103 spin_unlock(&tp->tx_lock);
1105 usb_autopm_put_interface_async(tp->intf);
1107 if (!netif_carrier_ok(netdev))
1110 if (!test_bit(WORK_ENABLE, &tp->flags))
1113 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1116 if (!skb_queue_empty(&tp->tx_queue))
1117 napi_schedule(&tp->napi);
1120 static void intr_callback(struct urb *urb)
1124 int status = urb->status;
1131 if (!test_bit(WORK_ENABLE, &tp->flags))
1134 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1138 case 0: /* success */
1140 case -ECONNRESET: /* unlink */
1142 netif_device_detach(tp->netdev);
1145 netif_info(tp, intr, tp->netdev,
1146 "Stop submitting intr, status %d\n", status);
1149 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1151 /* -EPIPE: should clear the halt */
1153 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1157 d = urb->transfer_buffer;
1158 if (INTR_LINK & __le16_to_cpu(d[0])) {
1159 if (!netif_carrier_ok(tp->netdev)) {
1160 set_bit(RTL8152_LINK_CHG, &tp->flags);
1161 schedule_delayed_work(&tp->schedule, 0);
1164 if (netif_carrier_ok(tp->netdev)) {
1165 set_bit(RTL8152_LINK_CHG, &tp->flags);
1166 schedule_delayed_work(&tp->schedule, 0);
1171 res = usb_submit_urb(urb, GFP_ATOMIC);
1172 if (res == -ENODEV) {
1173 set_bit(RTL8152_UNPLUG, &tp->flags);
1174 netif_device_detach(tp->netdev);
1176 netif_err(tp, intr, tp->netdev,
1177 "can't resubmit intr, status %d\n", res);
1181 static inline void *rx_agg_align(void *data)
1183 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1186 static inline void *tx_agg_align(void *data)
1188 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1191 static void free_all_mem(struct r8152 *tp)
1195 for (i = 0; i < RTL8152_MAX_RX; i++) {
1196 usb_free_urb(tp->rx_info[i].urb);
1197 tp->rx_info[i].urb = NULL;
1199 kfree(tp->rx_info[i].buffer);
1200 tp->rx_info[i].buffer = NULL;
1201 tp->rx_info[i].head = NULL;
1204 for (i = 0; i < RTL8152_MAX_TX; i++) {
1205 usb_free_urb(tp->tx_info[i].urb);
1206 tp->tx_info[i].urb = NULL;
1208 kfree(tp->tx_info[i].buffer);
1209 tp->tx_info[i].buffer = NULL;
1210 tp->tx_info[i].head = NULL;
1213 usb_free_urb(tp->intr_urb);
1214 tp->intr_urb = NULL;
1216 kfree(tp->intr_buff);
1217 tp->intr_buff = NULL;
1220 static int alloc_all_mem(struct r8152 *tp)
1222 struct net_device *netdev = tp->netdev;
1223 struct usb_interface *intf = tp->intf;
1224 struct usb_host_interface *alt = intf->cur_altsetting;
1225 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1230 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1232 spin_lock_init(&tp->rx_lock);
1233 spin_lock_init(&tp->tx_lock);
1234 INIT_LIST_HEAD(&tp->tx_free);
1235 skb_queue_head_init(&tp->tx_queue);
1236 skb_queue_head_init(&tp->rx_queue);
1238 for (i = 0; i < RTL8152_MAX_RX; i++) {
1239 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1243 if (buf != rx_agg_align(buf)) {
1245 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1251 urb = usb_alloc_urb(0, GFP_KERNEL);
1257 INIT_LIST_HEAD(&tp->rx_info[i].list);
1258 tp->rx_info[i].context = tp;
1259 tp->rx_info[i].urb = urb;
1260 tp->rx_info[i].buffer = buf;
1261 tp->rx_info[i].head = rx_agg_align(buf);
1264 for (i = 0; i < RTL8152_MAX_TX; i++) {
1265 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1269 if (buf != tx_agg_align(buf)) {
1271 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1277 urb = usb_alloc_urb(0, GFP_KERNEL);
1283 INIT_LIST_HEAD(&tp->tx_info[i].list);
1284 tp->tx_info[i].context = tp;
1285 tp->tx_info[i].urb = urb;
1286 tp->tx_info[i].buffer = buf;
1287 tp->tx_info[i].head = tx_agg_align(buf);
1289 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1292 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1296 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1300 tp->intr_interval = (int)ep_intr->desc.bInterval;
1301 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1302 tp->intr_buff, INTBUFSIZE, intr_callback,
1303 tp, tp->intr_interval);
1312 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1314 struct tx_agg *agg = NULL;
1315 unsigned long flags;
1317 if (list_empty(&tp->tx_free))
1320 spin_lock_irqsave(&tp->tx_lock, flags);
1321 if (!list_empty(&tp->tx_free)) {
1322 struct list_head *cursor;
1324 cursor = tp->tx_free.next;
1325 list_del_init(cursor);
1326 agg = list_entry(cursor, struct tx_agg, list);
1328 spin_unlock_irqrestore(&tp->tx_lock, flags);
1333 /* r8152_csum_workaround()
1334 * The hw limites the value the transport offset. When the offset is out of the
1335 * range, calculate the checksum by sw.
1337 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1338 struct sk_buff_head *list)
1340 if (skb_shinfo(skb)->gso_size) {
1341 netdev_features_t features = tp->netdev->features;
1342 struct sk_buff_head seg_list;
1343 struct sk_buff *segs, *nskb;
1345 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1346 segs = skb_gso_segment(skb, features);
1347 if (IS_ERR(segs) || !segs)
1350 __skb_queue_head_init(&seg_list);
1356 __skb_queue_tail(&seg_list, nskb);
1359 skb_queue_splice(&seg_list, list);
1361 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1362 if (skb_checksum_help(skb) < 0)
1365 __skb_queue_head(list, skb);
1367 struct net_device_stats *stats;
1370 stats = &tp->netdev->stats;
1371 stats->tx_dropped++;
1376 /* msdn_giant_send_check()
1377 * According to the document of microsoft, the TCP Pseudo Header excludes the
1378 * packet length for IPv6 TCP large packets.
1380 static int msdn_giant_send_check(struct sk_buff *skb)
1382 const struct ipv6hdr *ipv6h;
1386 ret = skb_cow_head(skb, 0);
1390 ipv6h = ipv6_hdr(skb);
1394 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1399 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1401 if (skb_vlan_tag_present(skb)) {
1404 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1405 desc->opts2 |= cpu_to_le32(opts2);
1409 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1411 u32 opts2 = le32_to_cpu(desc->opts2);
1413 if (opts2 & RX_VLAN_TAG)
1414 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1415 swab16(opts2 & 0xffff));
1418 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1419 struct sk_buff *skb, u32 len, u32 transport_offset)
1421 u32 mss = skb_shinfo(skb)->gso_size;
1422 u32 opts1, opts2 = 0;
1423 int ret = TX_CSUM_SUCCESS;
1425 WARN_ON_ONCE(len > TX_LEN_MAX);
1427 opts1 = len | TX_FS | TX_LS;
1430 if (transport_offset > GTTCPHO_MAX) {
1431 netif_warn(tp, tx_err, tp->netdev,
1432 "Invalid transport offset 0x%x for TSO\n",
1438 switch (vlan_get_protocol(skb)) {
1439 case htons(ETH_P_IP):
1443 case htons(ETH_P_IPV6):
1444 if (msdn_giant_send_check(skb)) {
1456 opts1 |= transport_offset << GTTCPHO_SHIFT;
1457 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1458 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1461 if (transport_offset > TCPHO_MAX) {
1462 netif_warn(tp, tx_err, tp->netdev,
1463 "Invalid transport offset 0x%x\n",
1469 switch (vlan_get_protocol(skb)) {
1470 case htons(ETH_P_IP):
1472 ip_protocol = ip_hdr(skb)->protocol;
1475 case htons(ETH_P_IPV6):
1477 ip_protocol = ipv6_hdr(skb)->nexthdr;
1481 ip_protocol = IPPROTO_RAW;
1485 if (ip_protocol == IPPROTO_TCP)
1487 else if (ip_protocol == IPPROTO_UDP)
1492 opts2 |= transport_offset << TCPHO_SHIFT;
1495 desc->opts2 = cpu_to_le32(opts2);
1496 desc->opts1 = cpu_to_le32(opts1);
1502 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1504 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1508 __skb_queue_head_init(&skb_head);
1509 spin_lock(&tx_queue->lock);
1510 skb_queue_splice_init(tx_queue, &skb_head);
1511 spin_unlock(&tx_queue->lock);
1513 tx_data = agg->head;
1516 remain = agg_buf_sz;
1518 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1519 struct tx_desc *tx_desc;
1520 struct sk_buff *skb;
1524 skb = __skb_dequeue(&skb_head);
1528 len = skb->len + sizeof(*tx_desc);
1531 __skb_queue_head(&skb_head, skb);
1535 tx_data = tx_agg_align(tx_data);
1536 tx_desc = (struct tx_desc *)tx_data;
1538 offset = (u32)skb_transport_offset(skb);
1540 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1541 r8152_csum_workaround(tp, skb, &skb_head);
1545 rtl_tx_vlan_tag(tx_desc, skb);
1547 tx_data += sizeof(*tx_desc);
1550 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1551 struct net_device_stats *stats = &tp->netdev->stats;
1553 stats->tx_dropped++;
1554 dev_kfree_skb_any(skb);
1555 tx_data -= sizeof(*tx_desc);
1560 agg->skb_len += len;
1563 dev_kfree_skb_any(skb);
1565 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1568 if (!skb_queue_empty(&skb_head)) {
1569 spin_lock(&tx_queue->lock);
1570 skb_queue_splice(&skb_head, tx_queue);
1571 spin_unlock(&tx_queue->lock);
1574 netif_tx_lock(tp->netdev);
1576 if (netif_queue_stopped(tp->netdev) &&
1577 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1578 netif_wake_queue(tp->netdev);
1580 netif_tx_unlock(tp->netdev);
1582 ret = usb_autopm_get_interface_async(tp->intf);
1586 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1587 agg->head, (int)(tx_data - (u8 *)agg->head),
1588 (usb_complete_t)write_bulk_callback, agg);
1590 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1592 usb_autopm_put_interface_async(tp->intf);
1598 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1600 u8 checksum = CHECKSUM_NONE;
1603 if (tp->version == RTL_VER_01)
1606 opts2 = le32_to_cpu(rx_desc->opts2);
1607 opts3 = le32_to_cpu(rx_desc->opts3);
1609 if (opts2 & RD_IPV4_CS) {
1611 checksum = CHECKSUM_NONE;
1612 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1613 checksum = CHECKSUM_NONE;
1614 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1615 checksum = CHECKSUM_NONE;
1617 checksum = CHECKSUM_UNNECESSARY;
1618 } else if (RD_IPV6_CS) {
1619 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1620 checksum = CHECKSUM_UNNECESSARY;
1621 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1622 checksum = CHECKSUM_UNNECESSARY;
1629 static int rx_bottom(struct r8152 *tp, int budget)
1631 unsigned long flags;
1632 struct list_head *cursor, *next, rx_queue;
1633 int ret = 0, work_done = 0;
1635 if (!skb_queue_empty(&tp->rx_queue)) {
1636 while (work_done < budget) {
1637 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1638 struct net_device *netdev = tp->netdev;
1639 struct net_device_stats *stats = &netdev->stats;
1640 unsigned int pkt_len;
1646 napi_gro_receive(&tp->napi, skb);
1648 stats->rx_packets++;
1649 stats->rx_bytes += pkt_len;
1653 if (list_empty(&tp->rx_done))
1656 INIT_LIST_HEAD(&rx_queue);
1657 spin_lock_irqsave(&tp->rx_lock, flags);
1658 list_splice_init(&tp->rx_done, &rx_queue);
1659 spin_unlock_irqrestore(&tp->rx_lock, flags);
1661 list_for_each_safe(cursor, next, &rx_queue) {
1662 struct rx_desc *rx_desc;
1668 list_del_init(cursor);
1670 agg = list_entry(cursor, struct rx_agg, list);
1672 if (urb->actual_length < ETH_ZLEN)
1675 rx_desc = agg->head;
1676 rx_data = agg->head;
1677 len_used += sizeof(struct rx_desc);
1679 while (urb->actual_length > len_used) {
1680 struct net_device *netdev = tp->netdev;
1681 struct net_device_stats *stats = &netdev->stats;
1682 unsigned int pkt_len;
1683 struct sk_buff *skb;
1685 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1686 if (pkt_len < ETH_ZLEN)
1689 len_used += pkt_len;
1690 if (urb->actual_length < len_used)
1693 pkt_len -= CRC_SIZE;
1694 rx_data += sizeof(struct rx_desc);
1696 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1698 stats->rx_dropped++;
1702 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1703 memcpy(skb->data, rx_data, pkt_len);
1704 skb_put(skb, pkt_len);
1705 skb->protocol = eth_type_trans(skb, netdev);
1706 rtl_rx_vlan_tag(rx_desc, skb);
1707 if (work_done < budget) {
1708 napi_gro_receive(&tp->napi, skb);
1710 stats->rx_packets++;
1711 stats->rx_bytes += pkt_len;
1713 __skb_queue_tail(&tp->rx_queue, skb);
1717 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1718 rx_desc = (struct rx_desc *)rx_data;
1719 len_used = (int)(rx_data - (u8 *)agg->head);
1720 len_used += sizeof(struct rx_desc);
1725 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1727 urb->actual_length = 0;
1728 list_add_tail(&agg->list, next);
1732 if (!list_empty(&rx_queue)) {
1733 spin_lock_irqsave(&tp->rx_lock, flags);
1734 list_splice_tail(&rx_queue, &tp->rx_done);
1735 spin_unlock_irqrestore(&tp->rx_lock, flags);
1742 static void tx_bottom(struct r8152 *tp)
1749 if (skb_queue_empty(&tp->tx_queue))
1752 agg = r8152_get_tx_agg(tp);
1756 res = r8152_tx_agg_fill(tp, agg);
1758 struct net_device *netdev = tp->netdev;
1760 if (res == -ENODEV) {
1761 set_bit(RTL8152_UNPLUG, &tp->flags);
1762 netif_device_detach(netdev);
1764 struct net_device_stats *stats = &netdev->stats;
1765 unsigned long flags;
1767 netif_warn(tp, tx_err, netdev,
1768 "failed tx_urb %d\n", res);
1769 stats->tx_dropped += agg->skb_num;
1771 spin_lock_irqsave(&tp->tx_lock, flags);
1772 list_add_tail(&agg->list, &tp->tx_free);
1773 spin_unlock_irqrestore(&tp->tx_lock, flags);
1779 static void bottom_half(struct r8152 *tp)
1781 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1784 if (!test_bit(WORK_ENABLE, &tp->flags))
1787 /* When link down, the driver would cancel all bulks. */
1788 /* This avoid the re-submitting bulk */
1789 if (!netif_carrier_ok(tp->netdev))
1792 clear_bit(SCHEDULE_NAPI, &tp->flags);
1797 static int r8152_poll(struct napi_struct *napi, int budget)
1799 struct r8152 *tp = container_of(napi, struct r8152, napi);
1802 work_done = rx_bottom(tp, budget);
1805 if (work_done < budget) {
1806 napi_complete(napi);
1807 if (!list_empty(&tp->rx_done))
1808 napi_schedule(napi);
1815 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1819 /* The rx would be stopped, so skip submitting */
1820 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1821 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1824 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1825 agg->head, agg_buf_sz,
1826 (usb_complete_t)read_bulk_callback, agg);
1828 ret = usb_submit_urb(agg->urb, mem_flags);
1829 if (ret == -ENODEV) {
1830 set_bit(RTL8152_UNPLUG, &tp->flags);
1831 netif_device_detach(tp->netdev);
1833 struct urb *urb = agg->urb;
1834 unsigned long flags;
1836 urb->actual_length = 0;
1837 spin_lock_irqsave(&tp->rx_lock, flags);
1838 list_add_tail(&agg->list, &tp->rx_done);
1839 spin_unlock_irqrestore(&tp->rx_lock, flags);
1841 netif_err(tp, rx_err, tp->netdev,
1842 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1844 napi_schedule(&tp->napi);
1850 static void rtl_drop_queued_tx(struct r8152 *tp)
1852 struct net_device_stats *stats = &tp->netdev->stats;
1853 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1854 struct sk_buff *skb;
1856 if (skb_queue_empty(tx_queue))
1859 __skb_queue_head_init(&skb_head);
1860 spin_lock_bh(&tx_queue->lock);
1861 skb_queue_splice_init(tx_queue, &skb_head);
1862 spin_unlock_bh(&tx_queue->lock);
1864 while ((skb = __skb_dequeue(&skb_head))) {
1866 stats->tx_dropped++;
1870 static void rtl8152_tx_timeout(struct net_device *netdev)
1872 struct r8152 *tp = netdev_priv(netdev);
1875 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1876 for (i = 0; i < RTL8152_MAX_TX; i++)
1877 usb_unlink_urb(tp->tx_info[i].urb);
1880 static void rtl8152_set_rx_mode(struct net_device *netdev)
1882 struct r8152 *tp = netdev_priv(netdev);
1884 if (netif_carrier_ok(netdev)) {
1885 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1886 schedule_delayed_work(&tp->schedule, 0);
1890 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1892 struct r8152 *tp = netdev_priv(netdev);
1893 u32 mc_filter[2]; /* Multicast hash filter */
1897 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1898 netif_stop_queue(netdev);
1899 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1900 ocp_data &= ~RCR_ACPT_ALL;
1901 ocp_data |= RCR_AB | RCR_APM;
1903 if (netdev->flags & IFF_PROMISC) {
1904 /* Unconditionally log net taps. */
1905 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1906 ocp_data |= RCR_AM | RCR_AAP;
1907 mc_filter[1] = 0xffffffff;
1908 mc_filter[0] = 0xffffffff;
1909 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1910 (netdev->flags & IFF_ALLMULTI)) {
1911 /* Too many to filter perfectly -- accept all multicasts. */
1913 mc_filter[1] = 0xffffffff;
1914 mc_filter[0] = 0xffffffff;
1916 struct netdev_hw_addr *ha;
1920 netdev_for_each_mc_addr(ha, netdev) {
1921 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1923 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1928 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1929 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1931 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1932 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1933 netif_wake_queue(netdev);
1936 static netdev_features_t
1937 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1938 netdev_features_t features)
1940 u32 mss = skb_shinfo(skb)->gso_size;
1941 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1942 int offset = skb_transport_offset(skb);
1944 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
1945 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
1946 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1947 features &= ~NETIF_F_GSO_MASK;
1952 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1953 struct net_device *netdev)
1955 struct r8152 *tp = netdev_priv(netdev);
1957 skb_tx_timestamp(skb);
1959 skb_queue_tail(&tp->tx_queue, skb);
1961 if (!list_empty(&tp->tx_free)) {
1962 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1963 set_bit(SCHEDULE_NAPI, &tp->flags);
1964 schedule_delayed_work(&tp->schedule, 0);
1966 usb_mark_last_busy(tp->udev);
1967 napi_schedule(&tp->napi);
1969 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1970 netif_stop_queue(netdev);
1973 return NETDEV_TX_OK;
1976 static void r8152b_reset_packet_filter(struct r8152 *tp)
1980 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1981 ocp_data &= ~FMC_FCR_MCU_EN;
1982 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1983 ocp_data |= FMC_FCR_MCU_EN;
1984 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1987 static void rtl8152_nic_reset(struct r8152 *tp)
1991 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1993 for (i = 0; i < 1000; i++) {
1994 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1996 usleep_range(100, 400);
2000 static void set_tx_qlen(struct r8152 *tp)
2002 struct net_device *netdev = tp->netdev;
2004 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2005 sizeof(struct tx_desc));
2008 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2010 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2013 static void rtl_set_eee_plus(struct r8152 *tp)
2018 speed = rtl8152_get_speed(tp);
2019 if (speed & _10bps) {
2020 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2021 ocp_data |= EEEP_CR_EEEP_TX;
2022 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2024 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2025 ocp_data &= ~EEEP_CR_EEEP_TX;
2026 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2030 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2034 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2036 ocp_data |= RXDY_GATED_EN;
2038 ocp_data &= ~RXDY_GATED_EN;
2039 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2042 static int rtl_start_rx(struct r8152 *tp)
2046 napi_disable(&tp->napi);
2047 INIT_LIST_HEAD(&tp->rx_done);
2048 for (i = 0; i < RTL8152_MAX_RX; i++) {
2049 INIT_LIST_HEAD(&tp->rx_info[i].list);
2050 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2054 napi_enable(&tp->napi);
2056 if (ret && ++i < RTL8152_MAX_RX) {
2057 struct list_head rx_queue;
2058 unsigned long flags;
2060 INIT_LIST_HEAD(&rx_queue);
2063 struct rx_agg *agg = &tp->rx_info[i++];
2064 struct urb *urb = agg->urb;
2066 urb->actual_length = 0;
2067 list_add_tail(&agg->list, &rx_queue);
2068 } while (i < RTL8152_MAX_RX);
2070 spin_lock_irqsave(&tp->rx_lock, flags);
2071 list_splice_tail(&rx_queue, &tp->rx_done);
2072 spin_unlock_irqrestore(&tp->rx_lock, flags);
2078 static int rtl_stop_rx(struct r8152 *tp)
2082 for (i = 0; i < RTL8152_MAX_RX; i++)
2083 usb_kill_urb(tp->rx_info[i].urb);
2085 while (!skb_queue_empty(&tp->rx_queue))
2086 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2091 static int rtl_enable(struct r8152 *tp)
2095 r8152b_reset_packet_filter(tp);
2097 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2098 ocp_data |= CR_RE | CR_TE;
2099 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2101 rxdy_gated_en(tp, false);
2106 static int rtl8152_enable(struct r8152 *tp)
2108 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2112 rtl_set_eee_plus(tp);
2114 return rtl_enable(tp);
2117 static void r8153_set_rx_agg(struct r8152 *tp)
2121 speed = rtl8152_get_speed(tp);
2122 if (speed & _1000bps) {
2123 if (tp->udev->speed == USB_SPEED_SUPER) {
2124 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2126 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2129 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2131 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2135 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2136 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2141 static int rtl8153_enable(struct r8152 *tp)
2143 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2147 rtl_set_eee_plus(tp);
2148 r8153_set_rx_agg(tp);
2150 return rtl_enable(tp);
2153 static void rtl_disable(struct r8152 *tp)
2158 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2159 rtl_drop_queued_tx(tp);
2163 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2164 ocp_data &= ~RCR_ACPT_ALL;
2165 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2167 rtl_drop_queued_tx(tp);
2169 for (i = 0; i < RTL8152_MAX_TX; i++)
2170 usb_kill_urb(tp->tx_info[i].urb);
2172 rxdy_gated_en(tp, true);
2174 for (i = 0; i < 1000; i++) {
2175 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2176 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2178 usleep_range(1000, 2000);
2181 for (i = 0; i < 1000; i++) {
2182 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2184 usleep_range(1000, 2000);
2189 rtl8152_nic_reset(tp);
2192 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2196 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2198 ocp_data |= POWER_CUT;
2200 ocp_data &= ~POWER_CUT;
2201 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2203 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2204 ocp_data &= ~RESUME_INDICATE;
2205 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2208 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2212 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2214 ocp_data |= CPCR_RX_VLAN;
2216 ocp_data &= ~CPCR_RX_VLAN;
2217 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2220 static int rtl8152_set_features(struct net_device *dev,
2221 netdev_features_t features)
2223 netdev_features_t changed = features ^ dev->features;
2224 struct r8152 *tp = netdev_priv(dev);
2227 ret = usb_autopm_get_interface(tp->intf);
2231 mutex_lock(&tp->control);
2233 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2234 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2235 rtl_rx_vlan_en(tp, true);
2237 rtl_rx_vlan_en(tp, false);
2240 mutex_unlock(&tp->control);
2242 usb_autopm_put_interface(tp->intf);
2248 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2250 static u32 __rtl_get_wol(struct r8152 *tp)
2255 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2256 if (!(ocp_data & LAN_WAKE_EN))
2259 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2260 if (ocp_data & LINK_ON_WAKE_EN)
2261 wolopts |= WAKE_PHY;
2263 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2264 if (ocp_data & UWF_EN)
2265 wolopts |= WAKE_UCAST;
2266 if (ocp_data & BWF_EN)
2267 wolopts |= WAKE_BCAST;
2268 if (ocp_data & MWF_EN)
2269 wolopts |= WAKE_MCAST;
2271 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2272 if (ocp_data & MAGIC_EN)
2273 wolopts |= WAKE_MAGIC;
2278 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2282 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2284 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2285 ocp_data &= ~LINK_ON_WAKE_EN;
2286 if (wolopts & WAKE_PHY)
2287 ocp_data |= LINK_ON_WAKE_EN;
2288 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2290 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2291 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2292 if (wolopts & WAKE_UCAST)
2294 if (wolopts & WAKE_BCAST)
2296 if (wolopts & WAKE_MCAST)
2298 if (wolopts & WAKE_ANY)
2299 ocp_data |= LAN_WAKE_EN;
2300 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2302 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2304 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2305 ocp_data &= ~MAGIC_EN;
2306 if (wolopts & WAKE_MAGIC)
2307 ocp_data |= MAGIC_EN;
2308 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2310 if (wolopts & WAKE_ANY)
2311 device_set_wakeup_enable(&tp->udev->dev, true);
2313 device_set_wakeup_enable(&tp->udev->dev, false);
2316 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2321 __rtl_set_wol(tp, WAKE_ANY);
2323 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2325 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2326 ocp_data |= LINK_OFF_WAKE_EN;
2327 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2329 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2331 __rtl_set_wol(tp, tp->saved_wolopts);
2335 static void rtl_phy_reset(struct r8152 *tp)
2340 clear_bit(PHY_RESET, &tp->flags);
2342 data = r8152_mdio_read(tp, MII_BMCR);
2344 /* don't reset again before the previous one complete */
2345 if (data & BMCR_RESET)
2349 r8152_mdio_write(tp, MII_BMCR, data);
2351 for (i = 0; i < 50; i++) {
2353 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2358 static void r8153_teredo_off(struct r8152 *tp)
2362 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2363 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2364 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2366 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2367 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2368 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2371 static void r8152b_disable_aldps(struct r8152 *tp)
2373 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2377 static inline void r8152b_enable_aldps(struct r8152 *tp)
2379 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2380 LINKENA | DIS_SDSAVE);
2383 static void rtl8152_disable(struct r8152 *tp)
2385 r8152b_disable_aldps(tp);
2387 r8152b_enable_aldps(tp);
2390 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2394 data = r8152_mdio_read(tp, MII_BMCR);
2395 if (data & BMCR_PDOWN) {
2396 data &= ~BMCR_PDOWN;
2397 r8152_mdio_write(tp, MII_BMCR, data);
2400 set_bit(PHY_RESET, &tp->flags);
2403 static void r8152b_exit_oob(struct r8152 *tp)
2408 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2409 ocp_data &= ~RCR_ACPT_ALL;
2410 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2412 rxdy_gated_en(tp, true);
2413 r8153_teredo_off(tp);
2414 r8152b_hw_phy_cfg(tp);
2416 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2417 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2419 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2420 ocp_data &= ~NOW_IS_OOB;
2421 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2423 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2424 ocp_data &= ~MCU_BORW_EN;
2425 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2427 for (i = 0; i < 1000; i++) {
2428 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2429 if (ocp_data & LINK_LIST_READY)
2431 usleep_range(1000, 2000);
2434 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2435 ocp_data |= RE_INIT_LL;
2436 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2438 for (i = 0; i < 1000; i++) {
2439 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2440 if (ocp_data & LINK_LIST_READY)
2442 usleep_range(1000, 2000);
2445 rtl8152_nic_reset(tp);
2447 /* rx share fifo credit full threshold */
2448 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2450 if (tp->udev->speed == USB_SPEED_FULL ||
2451 tp->udev->speed == USB_SPEED_LOW) {
2452 /* rx share fifo credit near full threshold */
2453 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2455 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2458 /* rx share fifo credit near full threshold */
2459 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2461 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2465 /* TX share fifo free credit full threshold */
2466 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2468 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2469 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2470 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2471 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2473 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2477 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2478 ocp_data |= TCR0_AUTO_FIFO;
2479 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2482 static void r8152b_enter_oob(struct r8152 *tp)
2487 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2488 ocp_data &= ~NOW_IS_OOB;
2489 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2491 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2492 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2493 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2497 for (i = 0; i < 1000; i++) {
2498 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2499 if (ocp_data & LINK_LIST_READY)
2501 usleep_range(1000, 2000);
2504 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2505 ocp_data |= RE_INIT_LL;
2506 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2508 for (i = 0; i < 1000; i++) {
2509 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2510 if (ocp_data & LINK_LIST_READY)
2512 usleep_range(1000, 2000);
2515 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2517 rtl_rx_vlan_en(tp, true);
2519 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2520 ocp_data |= ALDPS_PROXY_MODE;
2521 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2523 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2524 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2525 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2527 rxdy_gated_en(tp, false);
2529 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2530 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2531 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2534 static void r8153_hw_phy_cfg(struct r8152 *tp)
2539 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2540 data = r8152_mdio_read(tp, MII_BMCR);
2541 if (data & BMCR_PDOWN) {
2542 data &= ~BMCR_PDOWN;
2543 r8152_mdio_write(tp, MII_BMCR, data);
2546 if (tp->version == RTL_VER_03) {
2547 data = ocp_reg_read(tp, OCP_EEE_CFG);
2548 data &= ~CTAP_SHORT_EN;
2549 ocp_reg_write(tp, OCP_EEE_CFG, data);
2552 data = ocp_reg_read(tp, OCP_POWER_CFG);
2553 data |= EEE_CLKDIV_EN;
2554 ocp_reg_write(tp, OCP_POWER_CFG, data);
2556 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2557 data |= EN_10M_BGOFF;
2558 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2559 data = ocp_reg_read(tp, OCP_POWER_CFG);
2560 data |= EN_10M_PLLOFF;
2561 ocp_reg_write(tp, OCP_POWER_CFG, data);
2562 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
2564 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2565 ocp_data |= PFM_PWM_SWITCH;
2566 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2568 /* Enable LPF corner auto tune */
2569 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
2571 /* Adjust 10M Amplitude */
2572 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2573 sram_write(tp, SRAM_10M_AMP2, 0x0208);
2575 set_bit(PHY_RESET, &tp->flags);
2578 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2583 memset(u1u2, 0xff, sizeof(u1u2));
2585 memset(u1u2, 0x00, sizeof(u1u2));
2587 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2590 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2594 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2596 ocp_data |= U2P3_ENABLE;
2598 ocp_data &= ~U2P3_ENABLE;
2599 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2602 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2606 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2608 ocp_data |= PWR_EN | PHASE2_EN;
2610 ocp_data &= ~(PWR_EN | PHASE2_EN);
2611 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2613 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2614 ocp_data &= ~PCUT_STATUS;
2615 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2618 static void r8153_first_init(struct r8152 *tp)
2623 rxdy_gated_en(tp, true);
2624 r8153_teredo_off(tp);
2626 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2627 ocp_data &= ~RCR_ACPT_ALL;
2628 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2630 r8153_hw_phy_cfg(tp);
2632 rtl8152_nic_reset(tp);
2634 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2635 ocp_data &= ~NOW_IS_OOB;
2636 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2638 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2639 ocp_data &= ~MCU_BORW_EN;
2640 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2642 for (i = 0; i < 1000; i++) {
2643 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2644 if (ocp_data & LINK_LIST_READY)
2646 usleep_range(1000, 2000);
2649 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2650 ocp_data |= RE_INIT_LL;
2651 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2653 for (i = 0; i < 1000; i++) {
2654 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2655 if (ocp_data & LINK_LIST_READY)
2657 usleep_range(1000, 2000);
2660 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2662 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2663 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2665 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2666 ocp_data |= TCR0_AUTO_FIFO;
2667 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2669 rtl8152_nic_reset(tp);
2671 /* rx share fifo credit full threshold */
2672 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2673 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2674 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2675 /* TX share fifo free credit full threshold */
2676 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2678 /* rx aggregation */
2679 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2680 ocp_data &= ~RX_AGG_DISABLE;
2681 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2684 static void r8153_enter_oob(struct r8152 *tp)
2689 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2690 ocp_data &= ~NOW_IS_OOB;
2691 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2695 for (i = 0; i < 1000; i++) {
2696 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2697 if (ocp_data & LINK_LIST_READY)
2699 usleep_range(1000, 2000);
2702 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2703 ocp_data |= RE_INIT_LL;
2704 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2706 for (i = 0; i < 1000; i++) {
2707 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2708 if (ocp_data & LINK_LIST_READY)
2710 usleep_range(1000, 2000);
2713 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2715 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2716 ocp_data &= ~TEREDO_WAKE_MASK;
2717 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2719 rtl_rx_vlan_en(tp, true);
2721 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2722 ocp_data |= ALDPS_PROXY_MODE;
2723 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2725 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2726 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2727 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2729 rxdy_gated_en(tp, false);
2731 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2732 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2733 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2736 static void r8153_disable_aldps(struct r8152 *tp)
2740 data = ocp_reg_read(tp, OCP_POWER_CFG);
2742 ocp_reg_write(tp, OCP_POWER_CFG, data);
2746 static void r8153_enable_aldps(struct r8152 *tp)
2750 data = ocp_reg_read(tp, OCP_POWER_CFG);
2752 ocp_reg_write(tp, OCP_POWER_CFG, data);
2755 static void rtl8153_disable(struct r8152 *tp)
2757 r8153_disable_aldps(tp);
2759 r8153_enable_aldps(tp);
2762 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2764 u16 bmcr, anar, gbcr;
2767 cancel_delayed_work_sync(&tp->schedule);
2768 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2769 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2770 ADVERTISE_100HALF | ADVERTISE_100FULL);
2771 if (tp->mii.supports_gmii) {
2772 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2773 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2778 if (autoneg == AUTONEG_DISABLE) {
2779 if (speed == SPEED_10) {
2781 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2782 } else if (speed == SPEED_100) {
2783 bmcr = BMCR_SPEED100;
2784 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2785 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2786 bmcr = BMCR_SPEED1000;
2787 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2793 if (duplex == DUPLEX_FULL)
2794 bmcr |= BMCR_FULLDPLX;
2796 if (speed == SPEED_10) {
2797 if (duplex == DUPLEX_FULL)
2798 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2800 anar |= ADVERTISE_10HALF;
2801 } else if (speed == SPEED_100) {
2802 if (duplex == DUPLEX_FULL) {
2803 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2804 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2806 anar |= ADVERTISE_10HALF;
2807 anar |= ADVERTISE_100HALF;
2809 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2810 if (duplex == DUPLEX_FULL) {
2811 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2812 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2813 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2815 anar |= ADVERTISE_10HALF;
2816 anar |= ADVERTISE_100HALF;
2817 gbcr |= ADVERTISE_1000HALF;
2824 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2827 if (test_bit(PHY_RESET, &tp->flags))
2830 if (tp->mii.supports_gmii)
2831 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2833 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2834 r8152_mdio_write(tp, MII_BMCR, bmcr);
2836 if (test_bit(PHY_RESET, &tp->flags)) {
2839 clear_bit(PHY_RESET, &tp->flags);
2840 for (i = 0; i < 50; i++) {
2842 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2852 static void rtl8152_up(struct r8152 *tp)
2854 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2857 r8152b_disable_aldps(tp);
2858 r8152b_exit_oob(tp);
2859 r8152b_enable_aldps(tp);
2862 static void rtl8152_down(struct r8152 *tp)
2864 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2865 rtl_drop_queued_tx(tp);
2869 r8152_power_cut_en(tp, false);
2870 r8152b_disable_aldps(tp);
2871 r8152b_enter_oob(tp);
2872 r8152b_enable_aldps(tp);
2875 static void rtl8153_up(struct r8152 *tp)
2877 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2880 r8153_disable_aldps(tp);
2881 r8153_first_init(tp);
2882 r8153_enable_aldps(tp);
2885 static void rtl8153_down(struct r8152 *tp)
2887 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2888 rtl_drop_queued_tx(tp);
2892 r8153_u1u2en(tp, false);
2893 r8153_power_cut_en(tp, false);
2894 r8153_disable_aldps(tp);
2895 r8153_enter_oob(tp);
2896 r8153_enable_aldps(tp);
2899 static void set_carrier(struct r8152 *tp)
2901 struct net_device *netdev = tp->netdev;
2904 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2905 speed = rtl8152_get_speed(tp);
2907 if (speed & LINK_STATUS) {
2908 if (!netif_carrier_ok(netdev)) {
2909 tp->rtl_ops.enable(tp);
2910 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2911 netif_carrier_on(netdev);
2915 if (netif_carrier_ok(netdev)) {
2916 netif_carrier_off(netdev);
2917 napi_disable(&tp->napi);
2918 tp->rtl_ops.disable(tp);
2919 napi_enable(&tp->napi);
2924 static void rtl_work_func_t(struct work_struct *work)
2926 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2928 /* If the device is unplugged or !netif_running(), the workqueue
2929 * doesn't need to wake the device, and could return directly.
2931 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2934 if (usb_autopm_get_interface(tp->intf) < 0)
2937 if (!test_bit(WORK_ENABLE, &tp->flags))
2940 if (!mutex_trylock(&tp->control)) {
2941 schedule_delayed_work(&tp->schedule, 0);
2945 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2948 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2949 _rtl8152_set_rx_mode(tp->netdev);
2951 /* don't schedule napi before linking */
2952 if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
2953 netif_carrier_ok(tp->netdev)) {
2954 clear_bit(SCHEDULE_NAPI, &tp->flags);
2955 napi_schedule(&tp->napi);
2958 if (test_bit(PHY_RESET, &tp->flags))
2961 mutex_unlock(&tp->control);
2964 usb_autopm_put_interface(tp->intf);
2967 static int rtl8152_open(struct net_device *netdev)
2969 struct r8152 *tp = netdev_priv(netdev);
2972 res = alloc_all_mem(tp);
2976 netif_carrier_off(netdev);
2978 res = usb_autopm_get_interface(tp->intf);
2984 mutex_lock(&tp->control);
2986 /* The WORK_ENABLE may be set when autoresume occurs */
2987 if (test_bit(WORK_ENABLE, &tp->flags)) {
2988 clear_bit(WORK_ENABLE, &tp->flags);
2989 usb_kill_urb(tp->intr_urb);
2990 cancel_delayed_work_sync(&tp->schedule);
2992 /* disable the tx/rx, if the workqueue has enabled them. */
2993 if (netif_carrier_ok(netdev))
2994 tp->rtl_ops.disable(tp);
2999 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3000 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3002 netif_carrier_off(netdev);
3003 netif_start_queue(netdev);
3004 set_bit(WORK_ENABLE, &tp->flags);
3006 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3009 netif_device_detach(tp->netdev);
3010 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3014 napi_enable(&tp->napi);
3017 mutex_unlock(&tp->control);
3019 usb_autopm_put_interface(tp->intf);
3025 static int rtl8152_close(struct net_device *netdev)
3027 struct r8152 *tp = netdev_priv(netdev);
3030 napi_disable(&tp->napi);
3031 clear_bit(WORK_ENABLE, &tp->flags);
3032 usb_kill_urb(tp->intr_urb);
3033 cancel_delayed_work_sync(&tp->schedule);
3034 netif_stop_queue(netdev);
3036 res = usb_autopm_get_interface(tp->intf);
3037 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3038 rtl_drop_queued_tx(tp);
3041 mutex_lock(&tp->control);
3043 /* The autosuspend may have been enabled and wouldn't
3044 * be disable when autoresume occurs, because the
3045 * netif_running() would be false.
3047 rtl_runtime_suspend_enable(tp, false);
3049 tp->rtl_ops.down(tp);
3051 mutex_unlock(&tp->control);
3053 usb_autopm_put_interface(tp->intf);
3061 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3063 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3064 ocp_reg_write(tp, OCP_EEE_DATA, reg);
3065 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3068 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3072 r8152_mmd_indirect(tp, dev, reg);
3073 data = ocp_reg_read(tp, OCP_EEE_DATA);
3074 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3079 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3081 r8152_mmd_indirect(tp, dev, reg);
3082 ocp_reg_write(tp, OCP_EEE_DATA, data);
3083 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3086 static void r8152_eee_en(struct r8152 *tp, bool enable)
3088 u16 config1, config2, config3;
3091 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3092 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3093 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3094 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3097 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3098 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3099 config1 |= sd_rise_time(1);
3100 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3101 config3 |= fast_snr(42);
3103 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3104 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3106 config1 |= sd_rise_time(7);
3107 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3108 config3 |= fast_snr(511);
3111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3112 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3113 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3114 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3117 static void r8152b_enable_eee(struct r8152 *tp)
3119 r8152_eee_en(tp, true);
3120 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3123 static void r8153_eee_en(struct r8152 *tp, bool enable)
3128 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3129 config = ocp_reg_read(tp, OCP_EEE_CFG);
3132 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3135 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3136 config &= ~EEE10_EN;
3139 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3140 ocp_reg_write(tp, OCP_EEE_CFG, config);
3143 static void r8153_enable_eee(struct r8152 *tp)
3145 r8153_eee_en(tp, true);
3146 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3149 static void r8152b_enable_fc(struct r8152 *tp)
3153 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3154 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3155 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3158 static void rtl_tally_reset(struct r8152 *tp)
3162 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3163 ocp_data |= TALLY_RESET;
3164 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3167 static void r8152b_init(struct r8152 *tp)
3171 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3174 r8152b_disable_aldps(tp);
3176 if (tp->version == RTL_VER_01) {
3177 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3178 ocp_data &= ~LED_MODE_MASK;
3179 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3182 r8152_power_cut_en(tp, false);
3184 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3185 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3186 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3187 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3188 ocp_data &= ~MCU_CLK_RATIO_MASK;
3189 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3190 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3191 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3192 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3195 r8152b_enable_eee(tp);
3196 r8152b_enable_aldps(tp);
3197 r8152b_enable_fc(tp);
3198 rtl_tally_reset(tp);
3200 /* enable rx aggregation */
3201 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3202 ocp_data &= ~RX_AGG_DISABLE;
3203 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3206 static void r8153_init(struct r8152 *tp)
3211 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3214 r8153_disable_aldps(tp);
3215 r8153_u1u2en(tp, false);
3217 for (i = 0; i < 500; i++) {
3218 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3224 for (i = 0; i < 500; i++) {
3225 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3226 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3231 r8153_u2p3en(tp, false);
3233 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3234 ocp_data &= ~TIMER11_EN;
3235 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3237 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3238 ocp_data &= ~LED_MODE_MASK;
3239 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3241 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3242 ocp_data &= ~LPM_TIMER_MASK;
3243 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
3244 ocp_data |= LPM_TIMER_500MS;
3246 ocp_data |= LPM_TIMER_500US;
3247 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3249 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3250 ocp_data &= ~SEN_VAL_MASK;
3251 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3252 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3254 r8153_power_cut_en(tp, false);
3255 r8153_u1u2en(tp, true);
3257 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3258 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3259 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3260 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3261 U1U2_SPDWN_EN | L1_SPDWN_EN);
3262 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3263 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3264 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3267 r8153_enable_eee(tp);
3268 r8153_enable_aldps(tp);
3269 r8152b_enable_fc(tp);
3270 rtl_tally_reset(tp);
3273 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3275 struct r8152 *tp = usb_get_intfdata(intf);
3276 struct net_device *netdev = tp->netdev;
3279 mutex_lock(&tp->control);
3281 if (PMSG_IS_AUTO(message)) {
3282 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3287 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3289 netif_device_detach(netdev);
3292 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3293 clear_bit(WORK_ENABLE, &tp->flags);
3294 usb_kill_urb(tp->intr_urb);
3295 napi_disable(&tp->napi);
3296 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3298 rtl_runtime_suspend_enable(tp, true);
3300 cancel_delayed_work_sync(&tp->schedule);
3301 tp->rtl_ops.down(tp);
3303 napi_enable(&tp->napi);
3306 mutex_unlock(&tp->control);
3311 static int rtl8152_resume(struct usb_interface *intf)
3313 struct r8152 *tp = usb_get_intfdata(intf);
3315 mutex_lock(&tp->control);
3317 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3318 tp->rtl_ops.init(tp);
3319 netif_device_attach(tp->netdev);
3322 if (netif_running(tp->netdev)) {
3323 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3324 rtl_runtime_suspend_enable(tp, false);
3325 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3326 set_bit(WORK_ENABLE, &tp->flags);
3327 if (netif_carrier_ok(tp->netdev))
3331 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3332 tp->mii.supports_gmii ?
3333 SPEED_1000 : SPEED_100,
3335 netif_carrier_off(tp->netdev);
3336 set_bit(WORK_ENABLE, &tp->flags);
3338 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3339 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3340 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3343 mutex_unlock(&tp->control);
3348 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3350 struct r8152 *tp = netdev_priv(dev);
3352 if (usb_autopm_get_interface(tp->intf) < 0)
3355 mutex_lock(&tp->control);
3357 wol->supported = WAKE_ANY;
3358 wol->wolopts = __rtl_get_wol(tp);
3360 mutex_unlock(&tp->control);
3362 usb_autopm_put_interface(tp->intf);
3365 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3367 struct r8152 *tp = netdev_priv(dev);
3370 ret = usb_autopm_get_interface(tp->intf);
3374 mutex_lock(&tp->control);
3376 __rtl_set_wol(tp, wol->wolopts);
3377 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3379 mutex_unlock(&tp->control);
3381 usb_autopm_put_interface(tp->intf);
3387 static u32 rtl8152_get_msglevel(struct net_device *dev)
3389 struct r8152 *tp = netdev_priv(dev);
3391 return tp->msg_enable;
3394 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3396 struct r8152 *tp = netdev_priv(dev);
3398 tp->msg_enable = value;
3401 static void rtl8152_get_drvinfo(struct net_device *netdev,
3402 struct ethtool_drvinfo *info)
3404 struct r8152 *tp = netdev_priv(netdev);
3406 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3407 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3408 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3412 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3414 struct r8152 *tp = netdev_priv(netdev);
3417 if (!tp->mii.mdio_read)
3420 ret = usb_autopm_get_interface(tp->intf);
3424 mutex_lock(&tp->control);
3426 ret = mii_ethtool_gset(&tp->mii, cmd);
3428 mutex_unlock(&tp->control);
3430 usb_autopm_put_interface(tp->intf);
3436 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3438 struct r8152 *tp = netdev_priv(dev);
3441 ret = usb_autopm_get_interface(tp->intf);
3445 mutex_lock(&tp->control);
3447 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3449 mutex_unlock(&tp->control);
3451 usb_autopm_put_interface(tp->intf);
3457 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3464 "tx_single_collisions",
3465 "tx_multi_collisions",
3473 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3477 return ARRAY_SIZE(rtl8152_gstrings);
3483 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3484 struct ethtool_stats *stats, u64 *data)
3486 struct r8152 *tp = netdev_priv(dev);
3487 struct tally_counter tally;
3489 if (usb_autopm_get_interface(tp->intf) < 0)
3492 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3494 usb_autopm_put_interface(tp->intf);
3496 data[0] = le64_to_cpu(tally.tx_packets);
3497 data[1] = le64_to_cpu(tally.rx_packets);
3498 data[2] = le64_to_cpu(tally.tx_errors);
3499 data[3] = le32_to_cpu(tally.rx_errors);
3500 data[4] = le16_to_cpu(tally.rx_missed);
3501 data[5] = le16_to_cpu(tally.align_errors);
3502 data[6] = le32_to_cpu(tally.tx_one_collision);
3503 data[7] = le32_to_cpu(tally.tx_multi_collision);
3504 data[8] = le64_to_cpu(tally.rx_unicast);
3505 data[9] = le64_to_cpu(tally.rx_broadcast);
3506 data[10] = le32_to_cpu(tally.rx_multicast);
3507 data[11] = le16_to_cpu(tally.tx_aborted);
3508 data[12] = le16_to_cpu(tally.tx_underrun);
3511 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3513 switch (stringset) {
3515 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3520 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3522 u32 ocp_data, lp, adv, supported = 0;
3525 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3526 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3528 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3529 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3531 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3532 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3534 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3535 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3537 eee->eee_enabled = !!ocp_data;
3538 eee->eee_active = !!(supported & adv & lp);
3539 eee->supported = supported;
3540 eee->advertised = adv;
3541 eee->lp_advertised = lp;
3546 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3548 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3550 r8152_eee_en(tp, eee->eee_enabled);
3552 if (!eee->eee_enabled)
3555 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3560 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3562 u32 ocp_data, lp, adv, supported = 0;
3565 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3566 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3568 val = ocp_reg_read(tp, OCP_EEE_ADV);
3569 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3571 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3572 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3574 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3575 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3577 eee->eee_enabled = !!ocp_data;
3578 eee->eee_active = !!(supported & adv & lp);
3579 eee->supported = supported;
3580 eee->advertised = adv;
3581 eee->lp_advertised = lp;
3586 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3588 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3590 r8153_eee_en(tp, eee->eee_enabled);
3592 if (!eee->eee_enabled)
3595 ocp_reg_write(tp, OCP_EEE_ADV, val);
3601 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3603 struct r8152 *tp = netdev_priv(net);
3606 ret = usb_autopm_get_interface(tp->intf);
3610 mutex_lock(&tp->control);
3612 ret = tp->rtl_ops.eee_get(tp, edata);
3614 mutex_unlock(&tp->control);
3616 usb_autopm_put_interface(tp->intf);
3623 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3625 struct r8152 *tp = netdev_priv(net);
3628 ret = usb_autopm_get_interface(tp->intf);
3632 mutex_lock(&tp->control);
3634 ret = tp->rtl_ops.eee_set(tp, edata);
3636 ret = mii_nway_restart(&tp->mii);
3638 mutex_unlock(&tp->control);
3640 usb_autopm_put_interface(tp->intf);
3646 static int rtl8152_nway_reset(struct net_device *dev)
3648 struct r8152 *tp = netdev_priv(dev);
3651 ret = usb_autopm_get_interface(tp->intf);
3655 mutex_lock(&tp->control);
3657 ret = mii_nway_restart(&tp->mii);
3659 mutex_unlock(&tp->control);
3661 usb_autopm_put_interface(tp->intf);
3667 static struct ethtool_ops ops = {
3668 .get_drvinfo = rtl8152_get_drvinfo,
3669 .get_settings = rtl8152_get_settings,
3670 .set_settings = rtl8152_set_settings,
3671 .get_link = ethtool_op_get_link,
3672 .nway_reset = rtl8152_nway_reset,
3673 .get_msglevel = rtl8152_get_msglevel,
3674 .set_msglevel = rtl8152_set_msglevel,
3675 .get_wol = rtl8152_get_wol,
3676 .set_wol = rtl8152_set_wol,
3677 .get_strings = rtl8152_get_strings,
3678 .get_sset_count = rtl8152_get_sset_count,
3679 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3680 .get_eee = rtl_ethtool_get_eee,
3681 .set_eee = rtl_ethtool_set_eee,
3684 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3686 struct r8152 *tp = netdev_priv(netdev);
3687 struct mii_ioctl_data *data = if_mii(rq);
3690 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3693 res = usb_autopm_get_interface(tp->intf);
3699 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3703 mutex_lock(&tp->control);
3704 data->val_out = r8152_mdio_read(tp, data->reg_num);
3705 mutex_unlock(&tp->control);
3709 if (!capable(CAP_NET_ADMIN)) {
3713 mutex_lock(&tp->control);
3714 r8152_mdio_write(tp, data->reg_num, data->val_in);
3715 mutex_unlock(&tp->control);
3722 usb_autopm_put_interface(tp->intf);
3728 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3730 struct r8152 *tp = netdev_priv(dev);
3732 switch (tp->version) {
3735 return eth_change_mtu(dev, new_mtu);
3740 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3748 static const struct net_device_ops rtl8152_netdev_ops = {
3749 .ndo_open = rtl8152_open,
3750 .ndo_stop = rtl8152_close,
3751 .ndo_do_ioctl = rtl8152_ioctl,
3752 .ndo_start_xmit = rtl8152_start_xmit,
3753 .ndo_tx_timeout = rtl8152_tx_timeout,
3754 .ndo_set_features = rtl8152_set_features,
3755 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3756 .ndo_set_mac_address = rtl8152_set_mac_address,
3757 .ndo_change_mtu = rtl8152_change_mtu,
3758 .ndo_validate_addr = eth_validate_addr,
3759 .ndo_features_check = rtl8152_features_check,
3762 static void r8152b_get_version(struct r8152 *tp)
3767 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3768 version = (u16)(ocp_data & VERSION_MASK);
3772 tp->version = RTL_VER_01;
3775 tp->version = RTL_VER_02;
3778 tp->version = RTL_VER_03;
3779 tp->mii.supports_gmii = 1;
3782 tp->version = RTL_VER_04;
3783 tp->mii.supports_gmii = 1;
3786 tp->version = RTL_VER_05;
3787 tp->mii.supports_gmii = 1;
3790 netif_info(tp, probe, tp->netdev,
3791 "Unknown version 0x%04x\n", version);
3796 static void rtl8152_unload(struct r8152 *tp)
3798 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3801 if (tp->version != RTL_VER_01)
3802 r8152_power_cut_en(tp, true);
3805 static void rtl8153_unload(struct r8152 *tp)
3807 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3810 r8153_power_cut_en(tp, false);
3813 static int rtl_ops_init(struct r8152 *tp)
3815 struct rtl_ops *ops = &tp->rtl_ops;
3818 switch (tp->version) {
3821 ops->init = r8152b_init;
3822 ops->enable = rtl8152_enable;
3823 ops->disable = rtl8152_disable;
3824 ops->up = rtl8152_up;
3825 ops->down = rtl8152_down;
3826 ops->unload = rtl8152_unload;
3827 ops->eee_get = r8152_get_eee;
3828 ops->eee_set = r8152_set_eee;
3834 ops->init = r8153_init;
3835 ops->enable = rtl8153_enable;
3836 ops->disable = rtl8153_disable;
3837 ops->up = rtl8153_up;
3838 ops->down = rtl8153_down;
3839 ops->unload = rtl8153_unload;
3840 ops->eee_get = r8153_get_eee;
3841 ops->eee_set = r8153_set_eee;
3846 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3853 static int rtl8152_probe(struct usb_interface *intf,
3854 const struct usb_device_id *id)
3856 struct usb_device *udev = interface_to_usbdev(intf);
3858 struct net_device *netdev;
3861 if (udev->actconfig->desc.bConfigurationValue != 1) {
3862 usb_driver_set_configuration(udev, 1);
3866 usb_reset_device(udev);
3867 netdev = alloc_etherdev(sizeof(struct r8152));
3869 dev_err(&intf->dev, "Out of memory\n");
3873 SET_NETDEV_DEV(netdev, &intf->dev);
3874 tp = netdev_priv(netdev);
3875 tp->msg_enable = 0x7FFF;
3878 tp->netdev = netdev;
3881 r8152b_get_version(tp);
3882 ret = rtl_ops_init(tp);
3886 mutex_init(&tp->control);
3887 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3889 netdev->netdev_ops = &rtl8152_netdev_ops;
3890 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3892 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3893 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3894 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3895 NETIF_F_HW_VLAN_CTAG_TX;
3896 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3897 NETIF_F_TSO | NETIF_F_FRAGLIST |
3898 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3899 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
3900 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3901 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3902 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3904 netdev->ethtool_ops = &ops;
3905 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3907 tp->mii.dev = netdev;
3908 tp->mii.mdio_read = read_mii_word;
3909 tp->mii.mdio_write = write_mii_word;
3910 tp->mii.phy_id_mask = 0x3f;
3911 tp->mii.reg_num_mask = 0x1f;
3912 tp->mii.phy_id = R8152_PHY_ID;
3914 intf->needs_remote_wakeup = 1;
3916 tp->rtl_ops.init(tp);
3917 set_ethernet_addr(tp);
3919 usb_set_intfdata(intf, tp);
3920 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
3922 ret = register_netdev(netdev);
3924 netif_err(tp, probe, netdev, "couldn't register the device\n");
3928 tp->saved_wolopts = __rtl_get_wol(tp);
3929 if (tp->saved_wolopts)
3930 device_set_wakeup_enable(&udev->dev, true);
3932 device_set_wakeup_enable(&udev->dev, false);
3934 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3939 netif_napi_del(&tp->napi);
3940 usb_set_intfdata(intf, NULL);
3942 free_netdev(netdev);
3946 static void rtl8152_disconnect(struct usb_interface *intf)
3948 struct r8152 *tp = usb_get_intfdata(intf);
3950 usb_set_intfdata(intf, NULL);
3952 struct usb_device *udev = tp->udev;
3954 if (udev->state == USB_STATE_NOTATTACHED)
3955 set_bit(RTL8152_UNPLUG, &tp->flags);
3957 netif_napi_del(&tp->napi);
3958 unregister_netdev(tp->netdev);
3959 tp->rtl_ops.unload(tp);
3960 free_netdev(tp->netdev);
3964 #define REALTEK_USB_DEVICE(vend, prod) \
3965 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
3966 USB_DEVICE_ID_MATCH_INT_CLASS, \
3967 .idVendor = (vend), \
3968 .idProduct = (prod), \
3969 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
3972 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
3973 USB_DEVICE_ID_MATCH_DEVICE, \
3974 .idVendor = (vend), \
3975 .idProduct = (prod), \
3976 .bInterfaceClass = USB_CLASS_COMM, \
3977 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
3978 .bInterfaceProtocol = USB_CDC_PROTO_NONE
3980 /* table of devices that work with this driver */
3981 static struct usb_device_id rtl8152_table[] = {
3982 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
3983 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
3984 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
3988 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3990 static struct usb_driver rtl8152_driver = {
3992 .id_table = rtl8152_table,
3993 .probe = rtl8152_probe,
3994 .disconnect = rtl8152_disconnect,
3995 .suspend = rtl8152_suspend,
3996 .resume = rtl8152_resume,
3997 .reset_resume = rtl8152_resume,
3998 .supports_autosuspend = 1,
3999 .disable_hub_initiated_lpm = 1,
4002 module_usb_driver(rtl8152_driver);
4004 MODULE_AUTHOR(DRIVER_AUTHOR);
4005 MODULE_DESCRIPTION(DRIVER_DESC);
4006 MODULE_LICENSE("GPL");