2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
27 #include "targaddrs.h"
36 enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
42 enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
47 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
48 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
50 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
51 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
53 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
54 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
56 /* how long wait to wait for target to initialise, in ms */
57 #define ATH10K_PCI_TARGET_WAIT 3000
58 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
60 static const struct pci_device_id ath10k_pci_id_table[] = {
61 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
62 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
63 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
64 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
65 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
69 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
70 /* QCA988X pre 2.0 chips are not supported because they need some nasty
71 * hacks. ath10k doesn't have them and these devices crash horribly
74 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
78 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
79 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
80 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
84 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
85 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
86 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
88 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
90 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
91 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
94 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
95 static int ath10k_pci_cold_reset(struct ath10k *ar);
96 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
97 static int ath10k_pci_init_irq(struct ath10k *ar);
98 static int ath10k_pci_deinit_irq(struct ath10k *ar);
99 static int ath10k_pci_request_irq(struct ath10k *ar);
100 static void ath10k_pci_free_irq(struct ath10k *ar);
101 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
102 struct ath10k_ce_pipe *rx_pipe,
103 struct bmi_xfer *xfer);
104 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
105 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
106 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
107 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
108 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
109 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
110 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
112 static struct ce_attr host_ce_config_wlan[] = {
113 /* CE0: host->target HTC control and raw streams */
115 .flags = CE_ATTR_FLAGS,
119 .send_cb = ath10k_pci_htc_tx_cb,
122 /* CE1: target->host HTT + HTC control */
124 .flags = CE_ATTR_FLAGS,
127 .dest_nentries = 512,
128 .recv_cb = ath10k_pci_htt_htc_rx_cb,
131 /* CE2: target->host WMI */
133 .flags = CE_ATTR_FLAGS,
136 .dest_nentries = 128,
137 .recv_cb = ath10k_pci_htc_rx_cb,
140 /* CE3: host->target WMI */
142 .flags = CE_ATTR_FLAGS,
146 .send_cb = ath10k_pci_htc_tx_cb,
149 /* CE4: host->target HTT */
151 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
152 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
155 .send_cb = ath10k_pci_htt_tx_cb,
158 /* CE5: target->host HTT (HIF->HTT) */
160 .flags = CE_ATTR_FLAGS,
163 .dest_nentries = 512,
164 .recv_cb = ath10k_pci_htt_rx_cb,
167 /* CE6: target autonomous hif_memcpy */
169 .flags = CE_ATTR_FLAGS,
175 /* CE7: ce_diag, the Diagnostic Window */
177 .flags = CE_ATTR_FLAGS,
179 .src_sz_max = DIAG_TRANSFER_LIMIT,
183 /* CE8: target->host pktlog */
185 .flags = CE_ATTR_FLAGS,
188 .dest_nentries = 128,
189 .recv_cb = ath10k_pci_pktlog_rx_cb,
192 /* CE9 target autonomous qcache memcpy */
194 .flags = CE_ATTR_FLAGS,
200 /* CE10: target autonomous hif memcpy */
202 .flags = CE_ATTR_FLAGS,
208 /* CE11: target autonomous hif memcpy */
210 .flags = CE_ATTR_FLAGS,
217 /* Target firmware's Copy Engine configuration. */
218 static struct ce_pipe_config target_ce_config_wlan[] = {
219 /* CE0: host->target HTC control and raw streams */
221 .pipenum = __cpu_to_le32(0),
222 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
223 .nentries = __cpu_to_le32(32),
224 .nbytes_max = __cpu_to_le32(256),
225 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
226 .reserved = __cpu_to_le32(0),
229 /* CE1: target->host HTT + HTC control */
231 .pipenum = __cpu_to_le32(1),
232 .pipedir = __cpu_to_le32(PIPEDIR_IN),
233 .nentries = __cpu_to_le32(32),
234 .nbytes_max = __cpu_to_le32(2048),
235 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
236 .reserved = __cpu_to_le32(0),
239 /* CE2: target->host WMI */
241 .pipenum = __cpu_to_le32(2),
242 .pipedir = __cpu_to_le32(PIPEDIR_IN),
243 .nentries = __cpu_to_le32(64),
244 .nbytes_max = __cpu_to_le32(2048),
245 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
246 .reserved = __cpu_to_le32(0),
249 /* CE3: host->target WMI */
251 .pipenum = __cpu_to_le32(3),
252 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
253 .nentries = __cpu_to_le32(32),
254 .nbytes_max = __cpu_to_le32(2048),
255 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
256 .reserved = __cpu_to_le32(0),
259 /* CE4: host->target HTT */
261 .pipenum = __cpu_to_le32(4),
262 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
263 .nentries = __cpu_to_le32(256),
264 .nbytes_max = __cpu_to_le32(256),
265 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
266 .reserved = __cpu_to_le32(0),
269 /* NB: 50% of src nentries, since tx has 2 frags */
271 /* CE5: target->host HTT (HIF->HTT) */
273 .pipenum = __cpu_to_le32(5),
274 .pipedir = __cpu_to_le32(PIPEDIR_IN),
275 .nentries = __cpu_to_le32(32),
276 .nbytes_max = __cpu_to_le32(512),
277 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
278 .reserved = __cpu_to_le32(0),
281 /* CE6: Reserved for target autonomous hif_memcpy */
283 .pipenum = __cpu_to_le32(6),
284 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
285 .nentries = __cpu_to_le32(32),
286 .nbytes_max = __cpu_to_le32(4096),
287 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
288 .reserved = __cpu_to_le32(0),
291 /* CE7 used only by Host */
293 .pipenum = __cpu_to_le32(7),
294 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
295 .nentries = __cpu_to_le32(0),
296 .nbytes_max = __cpu_to_le32(0),
297 .flags = __cpu_to_le32(0),
298 .reserved = __cpu_to_le32(0),
301 /* CE8 target->host packtlog */
303 .pipenum = __cpu_to_le32(8),
304 .pipedir = __cpu_to_le32(PIPEDIR_IN),
305 .nentries = __cpu_to_le32(64),
306 .nbytes_max = __cpu_to_le32(2048),
307 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
308 .reserved = __cpu_to_le32(0),
311 /* CE9 target autonomous qcache memcpy */
313 .pipenum = __cpu_to_le32(9),
314 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
315 .nentries = __cpu_to_le32(32),
316 .nbytes_max = __cpu_to_le32(2048),
317 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
318 .reserved = __cpu_to_le32(0),
321 /* It not necessary to send target wlan configuration for CE10 & CE11
322 * as these CEs are not actively used in target.
327 * Map from service/endpoint to Copy Engine.
328 * This table is derived from the CE_PCI TABLE, above.
329 * It is passed to the Target at startup for use by firmware.
331 static struct service_to_pipe target_service_to_ce_map_wlan[] = {
333 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
334 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
338 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
339 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
343 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
344 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
348 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
349 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
353 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
354 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
358 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
359 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
363 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
364 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
368 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
369 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
373 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
374 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
378 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
379 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
383 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
384 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
388 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
389 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
393 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
394 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
398 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
399 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
403 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
404 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
408 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
409 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
413 /* (Additions here) */
422 static bool ath10k_pci_is_awake(struct ath10k *ar)
424 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
425 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
428 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
431 static void __ath10k_pci_wake(struct ath10k *ar)
433 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
435 lockdep_assert_held(&ar_pci->ps_lock);
437 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
438 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
440 iowrite32(PCIE_SOC_WAKE_V_MASK,
441 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
442 PCIE_SOC_WAKE_ADDRESS);
445 static void __ath10k_pci_sleep(struct ath10k *ar)
447 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
449 lockdep_assert_held(&ar_pci->ps_lock);
451 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
452 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
454 iowrite32(PCIE_SOC_WAKE_RESET,
455 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
456 PCIE_SOC_WAKE_ADDRESS);
457 ar_pci->ps_awake = false;
460 static int ath10k_pci_wake_wait(struct ath10k *ar)
465 while (tot_delay < PCIE_WAKE_TIMEOUT) {
466 if (ath10k_pci_is_awake(ar)) {
467 if (tot_delay > PCIE_WAKE_LATE_US)
468 ath10k_warn(ar, "device wakeup took %d ms which is unusally long, otherwise it works normally.\n",
474 tot_delay += curr_delay;
483 static int ath10k_pci_force_wake(struct ath10k *ar)
485 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
492 spin_lock_irqsave(&ar_pci->ps_lock, flags);
494 if (!ar_pci->ps_awake) {
495 iowrite32(PCIE_SOC_WAKE_V_MASK,
496 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
497 PCIE_SOC_WAKE_ADDRESS);
499 ret = ath10k_pci_wake_wait(ar);
501 ar_pci->ps_awake = true;
504 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
509 static void ath10k_pci_force_sleep(struct ath10k *ar)
511 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
514 spin_lock_irqsave(&ar_pci->ps_lock, flags);
516 iowrite32(PCIE_SOC_WAKE_RESET,
517 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
518 PCIE_SOC_WAKE_ADDRESS);
519 ar_pci->ps_awake = false;
521 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
524 static int ath10k_pci_wake(struct ath10k *ar)
526 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
530 if (ar_pci->pci_ps == 0)
533 spin_lock_irqsave(&ar_pci->ps_lock, flags);
535 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
536 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
538 /* This function can be called very frequently. To avoid excessive
539 * CPU stalls for MMIO reads use a cache var to hold the device state.
541 if (!ar_pci->ps_awake) {
542 __ath10k_pci_wake(ar);
544 ret = ath10k_pci_wake_wait(ar);
546 ar_pci->ps_awake = true;
550 ar_pci->ps_wake_refcount++;
551 WARN_ON(ar_pci->ps_wake_refcount == 0);
554 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
559 static void ath10k_pci_sleep(struct ath10k *ar)
561 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
564 if (ar_pci->pci_ps == 0)
567 spin_lock_irqsave(&ar_pci->ps_lock, flags);
569 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
570 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
572 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
575 ar_pci->ps_wake_refcount--;
577 mod_timer(&ar_pci->ps_timer, jiffies +
578 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
581 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
584 static void ath10k_pci_ps_timer(unsigned long ptr)
586 struct ath10k *ar = (void *)ptr;
587 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
590 spin_lock_irqsave(&ar_pci->ps_lock, flags);
592 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
593 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
595 if (ar_pci->ps_wake_refcount > 0)
598 __ath10k_pci_sleep(ar);
601 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
604 static void ath10k_pci_sleep_sync(struct ath10k *ar)
606 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
609 if (ar_pci->pci_ps == 0) {
610 ath10k_pci_force_sleep(ar);
614 del_timer_sync(&ar_pci->ps_timer);
616 spin_lock_irqsave(&ar_pci->ps_lock, flags);
617 WARN_ON(ar_pci->ps_wake_refcount > 0);
618 __ath10k_pci_sleep(ar);
619 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
622 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
624 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
627 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
628 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
629 offset, offset + sizeof(value), ar_pci->mem_len);
633 ret = ath10k_pci_wake(ar);
635 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
640 iowrite32(value, ar_pci->mem + offset);
641 ath10k_pci_sleep(ar);
644 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
646 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
650 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
651 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
652 offset, offset + sizeof(val), ar_pci->mem_len);
656 ret = ath10k_pci_wake(ar);
658 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
663 val = ioread32(ar_pci->mem + offset);
664 ath10k_pci_sleep(ar);
669 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
671 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
673 ar_pci->bus_ops->write32(ar, offset, value);
676 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
678 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
680 return ar_pci->bus_ops->read32(ar, offset);
683 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
685 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
688 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
690 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
693 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
695 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
698 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
700 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
703 bool ath10k_pci_irq_pending(struct ath10k *ar)
707 /* Check if the shared legacy irq is for us */
708 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
709 PCIE_INTR_CAUSE_ADDRESS);
710 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
716 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
718 /* IMPORTANT: INTR_CLR register has to be set after
719 * INTR_ENABLE is set to 0, otherwise interrupt can not be
721 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
723 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
724 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
726 /* IMPORTANT: this extra read transaction is required to
727 * flush the posted write buffer. */
728 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
729 PCIE_INTR_ENABLE_ADDRESS);
732 void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
734 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
735 PCIE_INTR_ENABLE_ADDRESS,
736 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
738 /* IMPORTANT: this extra read transaction is required to
739 * flush the posted write buffer. */
740 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
741 PCIE_INTR_ENABLE_ADDRESS);
744 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
746 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
748 if (ar_pci->num_msi_intrs > 1)
751 if (ar_pci->num_msi_intrs == 1)
757 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
759 struct ath10k *ar = pipe->hif_ce_state;
760 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
761 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
766 skb = dev_alloc_skb(pipe->buf_sz);
770 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
772 paddr = dma_map_single(ar->dev, skb->data,
773 skb->len + skb_tailroom(skb),
775 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
776 ath10k_warn(ar, "failed to dma map pci rx buf\n");
777 dev_kfree_skb_any(skb);
781 ATH10K_SKB_RXCB(skb)->paddr = paddr;
783 spin_lock_bh(&ar_pci->ce_lock);
784 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
785 spin_unlock_bh(&ar_pci->ce_lock);
787 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
789 dev_kfree_skb_any(skb);
796 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
798 struct ath10k *ar = pipe->hif_ce_state;
799 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
800 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
803 if (pipe->buf_sz == 0)
806 if (!ce_pipe->dest_ring)
809 spin_lock_bh(&ar_pci->ce_lock);
810 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
811 spin_unlock_bh(&ar_pci->ce_lock);
813 ret = __ath10k_pci_rx_post_buf(pipe);
817 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
818 mod_timer(&ar_pci->rx_post_retry, jiffies +
819 ATH10K_PCI_RX_POST_RETRY_MS);
825 void ath10k_pci_rx_post(struct ath10k *ar)
827 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
830 for (i = 0; i < CE_COUNT; i++)
831 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
834 void ath10k_pci_rx_replenish_retry(unsigned long ptr)
836 struct ath10k *ar = (void *)ptr;
838 ath10k_pci_rx_post(ar);
841 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
845 switch (ar->hw_rev) {
846 case ATH10K_HW_QCA988X:
847 case ATH10K_HW_QCA6174:
848 case ATH10K_HW_QCA9377:
849 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
853 case ATH10K_HW_QCA99X0:
854 case ATH10K_HW_QCA4019:
855 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
859 val |= 0x100000 | (addr & 0xfffff);
864 * Diagnostic read/write access is provided for startup/config/debug usage.
865 * Caller must guarantee proper alignment, when applicable, and single user
868 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
871 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
874 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
877 struct ath10k_ce_pipe *ce_diag;
878 /* Host buffer address in CE space */
880 dma_addr_t ce_data_base = 0;
881 void *data_buf = NULL;
884 spin_lock_bh(&ar_pci->ce_lock);
886 ce_diag = ar_pci->ce_diag;
889 * Allocate a temporary bounce buffer to hold caller's data
890 * to be DMA'ed from Target. This guarantees
891 * 1) 4-byte alignment
892 * 2) Buffer in DMA-able space
894 orig_nbytes = nbytes;
895 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
904 memset(data_buf, 0, orig_nbytes);
906 remaining_bytes = orig_nbytes;
907 ce_data = ce_data_base;
908 while (remaining_bytes) {
909 nbytes = min_t(unsigned int, remaining_bytes,
910 DIAG_TRANSFER_LIMIT);
912 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data);
916 /* Request CE to send from Target(!) address to Host buffer */
918 * The address supplied by the caller is in the
919 * Target CPU virtual address space.
921 * In order to use this address with the diagnostic CE,
922 * convert it from Target CPU virtual address space
923 * to CE address space
925 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
927 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
933 while (ath10k_ce_completed_send_next_nolock(ce_diag,
936 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
943 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
948 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
954 if (nbytes != completed_nbytes) {
959 if (buf != ce_data) {
964 remaining_bytes -= nbytes;
971 memcpy(data, data_buf, orig_nbytes);
973 ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n",
977 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
980 spin_unlock_bh(&ar_pci->ce_lock);
985 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
990 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
991 *value = __le32_to_cpu(val);
996 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
1002 host_addr = host_interest_item_address(src);
1004 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1006 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1011 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1013 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1021 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1022 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1024 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1025 const void *data, int nbytes)
1027 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1030 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
1033 struct ath10k_ce_pipe *ce_diag;
1034 void *data_buf = NULL;
1035 u32 ce_data; /* Host buffer address in CE space */
1036 dma_addr_t ce_data_base = 0;
1039 spin_lock_bh(&ar_pci->ce_lock);
1041 ce_diag = ar_pci->ce_diag;
1044 * Allocate a temporary bounce buffer to hold caller's data
1045 * to be DMA'ed to Target. This guarantees
1046 * 1) 4-byte alignment
1047 * 2) Buffer in DMA-able space
1049 orig_nbytes = nbytes;
1050 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1059 /* Copy caller's data to allocated DMA buf */
1060 memcpy(data_buf, data, orig_nbytes);
1063 * The address supplied by the caller is in the
1064 * Target CPU virtual address space.
1066 * In order to use this address with the diagnostic CE,
1068 * Target CPU virtual address space
1072 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1074 remaining_bytes = orig_nbytes;
1075 ce_data = ce_data_base;
1076 while (remaining_bytes) {
1077 /* FIXME: check cast */
1078 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1080 /* Set up to receive directly into Target(!) address */
1081 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, address);
1086 * Request CE to send caller-supplied data that
1087 * was copied to bounce buffer to Target(!) address.
1089 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
1095 while (ath10k_ce_completed_send_next_nolock(ce_diag,
1099 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1106 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
1108 &id, &flags) != 0) {
1111 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1117 if (nbytes != completed_nbytes) {
1122 if (buf != address) {
1127 remaining_bytes -= nbytes;
1134 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
1139 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1142 spin_unlock_bh(&ar_pci->ce_lock);
1147 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1149 __le32 val = __cpu_to_le32(value);
1151 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1154 /* Called by lower (CE) layer when a send to Target completes. */
1155 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1157 struct ath10k *ar = ce_state->ar;
1158 struct sk_buff_head list;
1159 struct sk_buff *skb;
1161 __skb_queue_head_init(&list);
1162 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1163 /* no need to call tx completion for NULL pointers */
1167 __skb_queue_tail(&list, skb);
1170 while ((skb = __skb_dequeue(&list)))
1171 ath10k_htc_tx_completion_handler(ar, skb);
1174 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1175 void (*callback)(struct ath10k *ar,
1176 struct sk_buff *skb))
1178 struct ath10k *ar = ce_state->ar;
1179 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1180 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1181 struct sk_buff *skb;
1182 struct sk_buff_head list;
1183 void *transfer_context;
1185 unsigned int nbytes, max_nbytes;
1186 unsigned int transfer_id;
1189 __skb_queue_head_init(&list);
1190 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1191 &ce_data, &nbytes, &transfer_id,
1193 skb = transfer_context;
1194 max_nbytes = skb->len + skb_tailroom(skb);
1195 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1196 max_nbytes, DMA_FROM_DEVICE);
1198 if (unlikely(max_nbytes < nbytes)) {
1199 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1200 nbytes, max_nbytes);
1201 dev_kfree_skb_any(skb);
1205 skb_put(skb, nbytes);
1206 __skb_queue_tail(&list, skb);
1209 while ((skb = __skb_dequeue(&list))) {
1210 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1211 ce_state->id, skb->len);
1212 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1213 skb->data, skb->len);
1218 ath10k_pci_rx_post_pipe(pipe_info);
1221 /* Called by lower (CE) layer when data is received from the Target. */
1222 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1224 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1227 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1229 /* CE4 polling needs to be done whenever CE pipe which transports
1230 * HTT Rx (target->host) is processed.
1232 ath10k_ce_per_engine_service(ce_state->ar, 4);
1234 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1237 /* Called by lower (CE) layer when data is received from the Target.
1238 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1240 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1242 ath10k_pci_process_rx_cb(ce_state,
1243 ath10k_htt_rx_pktlog_completion_handler);
1246 /* Called by lower (CE) layer when a send to HTT Target completes. */
1247 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1249 struct ath10k *ar = ce_state->ar;
1250 struct sk_buff *skb;
1252 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1253 /* no need to call tx completion for NULL pointers */
1257 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1258 skb->len, DMA_TO_DEVICE);
1259 ath10k_htt_hif_tx_complete(ar, skb);
1263 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1265 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1266 ath10k_htt_t2h_msg_handler(ar, skb);
1269 /* Called by lower (CE) layer when HTT data is received from the Target. */
1270 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1272 /* CE4 polling needs to be done whenever CE pipe which transports
1273 * HTT Rx (target->host) is processed.
1275 ath10k_ce_per_engine_service(ce_state->ar, 4);
1277 ath10k_pci_process_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1280 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1281 struct ath10k_hif_sg_item *items, int n_items)
1283 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1284 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1285 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1286 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1287 unsigned int nentries_mask;
1288 unsigned int sw_index;
1289 unsigned int write_index;
1292 spin_lock_bh(&ar_pci->ce_lock);
1294 nentries_mask = src_ring->nentries_mask;
1295 sw_index = src_ring->sw_index;
1296 write_index = src_ring->write_index;
1298 if (unlikely(CE_RING_DELTA(nentries_mask,
1299 write_index, sw_index - 1) < n_items)) {
1304 for (i = 0; i < n_items - 1; i++) {
1305 ath10k_dbg(ar, ATH10K_DBG_PCI,
1306 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1307 i, items[i].paddr, items[i].len, n_items);
1308 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1309 items[i].vaddr, items[i].len);
1311 err = ath10k_ce_send_nolock(ce_pipe,
1312 items[i].transfer_context,
1315 items[i].transfer_id,
1316 CE_SEND_FLAG_GATHER);
1321 /* `i` is equal to `n_items -1` after for() */
1323 ath10k_dbg(ar, ATH10K_DBG_PCI,
1324 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1325 i, items[i].paddr, items[i].len, n_items);
1326 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1327 items[i].vaddr, items[i].len);
1329 err = ath10k_ce_send_nolock(ce_pipe,
1330 items[i].transfer_context,
1333 items[i].transfer_id,
1338 spin_unlock_bh(&ar_pci->ce_lock);
1343 __ath10k_ce_send_revert(ce_pipe);
1345 spin_unlock_bh(&ar_pci->ce_lock);
1349 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1352 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1355 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1357 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1359 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1361 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1364 static void ath10k_pci_dump_registers(struct ath10k *ar,
1365 struct ath10k_fw_crash_data *crash_data)
1367 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1370 lockdep_assert_held(&ar->data_lock);
1372 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1374 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1376 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1380 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1382 ath10k_err(ar, "firmware register dump:\n");
1383 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1384 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1386 __le32_to_cpu(reg_dump_values[i]),
1387 __le32_to_cpu(reg_dump_values[i + 1]),
1388 __le32_to_cpu(reg_dump_values[i + 2]),
1389 __le32_to_cpu(reg_dump_values[i + 3]));
1394 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1395 crash_data->registers[i] = reg_dump_values[i];
1398 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1400 struct ath10k_fw_crash_data *crash_data;
1403 spin_lock_bh(&ar->data_lock);
1405 ar->stats.fw_crash_counter++;
1407 crash_data = ath10k_debug_get_new_fw_crash_data(ar);
1410 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid);
1412 scnprintf(uuid, sizeof(uuid), "n/a");
1414 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid);
1415 ath10k_print_driver_info(ar);
1416 ath10k_pci_dump_registers(ar, crash_data);
1418 spin_unlock_bh(&ar->data_lock);
1420 queue_work(ar->workqueue, &ar->restart_work);
1423 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1426 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1431 * Decide whether to actually poll for completions, or just
1432 * wait for a later chance.
1433 * If there seem to be plenty of resources left, then just wait
1434 * since checking involves reading a CE register, which is a
1435 * relatively expensive operation.
1437 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1440 * If at least 50% of the total resources are still available,
1441 * don't bother checking again yet.
1443 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1446 ath10k_ce_per_engine_service(ar, pipe);
1449 void ath10k_pci_kill_tasklet(struct ath10k *ar)
1451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1454 tasklet_kill(&ar_pci->intr_tq);
1455 tasklet_kill(&ar_pci->msi_fw_err);
1457 for (i = 0; i < CE_COUNT; i++)
1458 tasklet_kill(&ar_pci->pipe_info[i].intr);
1460 del_timer_sync(&ar_pci->rx_post_retry);
1463 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1464 u8 *ul_pipe, u8 *dl_pipe)
1466 const struct service_to_pipe *entry;
1467 bool ul_set = false, dl_set = false;
1470 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1472 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1473 entry = &target_service_to_ce_map_wlan[i];
1475 if (__le32_to_cpu(entry->service_id) != service_id)
1478 switch (__le32_to_cpu(entry->pipedir)) {
1483 *dl_pipe = __le32_to_cpu(entry->pipenum);
1488 *ul_pipe = __le32_to_cpu(entry->pipenum);
1494 *dl_pipe = __le32_to_cpu(entry->pipenum);
1495 *ul_pipe = __le32_to_cpu(entry->pipenum);
1502 if (WARN_ON(!ul_set || !dl_set))
1508 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1509 u8 *ul_pipe, u8 *dl_pipe)
1511 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1513 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1514 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1518 static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1522 switch (ar->hw_rev) {
1523 case ATH10K_HW_QCA988X:
1524 case ATH10K_HW_QCA6174:
1525 case ATH10K_HW_QCA9377:
1526 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1528 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1529 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1530 CORE_CTRL_ADDRESS, val);
1532 case ATH10K_HW_QCA99X0:
1533 case ATH10K_HW_QCA4019:
1534 /* TODO: Find appropriate register configuration for QCA99X0
1541 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1545 switch (ar->hw_rev) {
1546 case ATH10K_HW_QCA988X:
1547 case ATH10K_HW_QCA6174:
1548 case ATH10K_HW_QCA9377:
1549 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1551 val |= CORE_CTRL_PCIE_REG_31_MASK;
1552 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1553 CORE_CTRL_ADDRESS, val);
1555 case ATH10K_HW_QCA99X0:
1556 case ATH10K_HW_QCA4019:
1557 /* TODO: Find appropriate register configuration for QCA99X0
1558 * to unmask irq/MSI.
1564 static void ath10k_pci_irq_disable(struct ath10k *ar)
1566 ath10k_ce_disable_interrupts(ar);
1567 ath10k_pci_disable_and_clear_legacy_irq(ar);
1568 ath10k_pci_irq_msi_fw_mask(ar);
1571 static void ath10k_pci_irq_sync(struct ath10k *ar)
1573 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1576 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1577 synchronize_irq(ar_pci->pdev->irq + i);
1580 static void ath10k_pci_irq_enable(struct ath10k *ar)
1582 ath10k_ce_enable_interrupts(ar);
1583 ath10k_pci_enable_legacy_irq(ar);
1584 ath10k_pci_irq_msi_fw_unmask(ar);
1587 static int ath10k_pci_hif_start(struct ath10k *ar)
1589 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1591 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1593 ath10k_pci_irq_enable(ar);
1594 ath10k_pci_rx_post(ar);
1596 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1602 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1605 struct ath10k_ce_pipe *ce_pipe;
1606 struct ath10k_ce_ring *ce_ring;
1607 struct sk_buff *skb;
1610 ar = pci_pipe->hif_ce_state;
1611 ce_pipe = pci_pipe->ce_hdl;
1612 ce_ring = ce_pipe->dest_ring;
1617 if (!pci_pipe->buf_sz)
1620 for (i = 0; i < ce_ring->nentries; i++) {
1621 skb = ce_ring->per_transfer_context[i];
1625 ce_ring->per_transfer_context[i] = NULL;
1627 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1628 skb->len + skb_tailroom(skb),
1630 dev_kfree_skb_any(skb);
1634 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1637 struct ath10k_pci *ar_pci;
1638 struct ath10k_ce_pipe *ce_pipe;
1639 struct ath10k_ce_ring *ce_ring;
1640 struct sk_buff *skb;
1643 ar = pci_pipe->hif_ce_state;
1644 ar_pci = ath10k_pci_priv(ar);
1645 ce_pipe = pci_pipe->ce_hdl;
1646 ce_ring = ce_pipe->src_ring;
1651 if (!pci_pipe->buf_sz)
1654 for (i = 0; i < ce_ring->nentries; i++) {
1655 skb = ce_ring->per_transfer_context[i];
1659 ce_ring->per_transfer_context[i] = NULL;
1661 ath10k_htc_tx_completion_handler(ar, skb);
1666 * Cleanup residual buffers for device shutdown:
1667 * buffers that were enqueued for receive
1668 * buffers that were to be sent
1669 * Note: Buffers that had completed but which were
1670 * not yet processed are on a completion queue. They
1671 * are handled when the completion thread shuts down.
1673 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1675 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1678 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1679 struct ath10k_pci_pipe *pipe_info;
1681 pipe_info = &ar_pci->pipe_info[pipe_num];
1682 ath10k_pci_rx_pipe_cleanup(pipe_info);
1683 ath10k_pci_tx_pipe_cleanup(pipe_info);
1687 void ath10k_pci_ce_deinit(struct ath10k *ar)
1691 for (i = 0; i < CE_COUNT; i++)
1692 ath10k_ce_deinit_pipe(ar, i);
1695 void ath10k_pci_flush(struct ath10k *ar)
1697 ath10k_pci_kill_tasklet(ar);
1698 ath10k_pci_buffer_cleanup(ar);
1701 static void ath10k_pci_hif_stop(struct ath10k *ar)
1703 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1704 unsigned long flags;
1706 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1708 /* Most likely the device has HTT Rx ring configured. The only way to
1709 * prevent the device from accessing (and possible corrupting) host
1710 * memory is to reset the chip now.
1712 * There's also no known way of masking MSI interrupts on the device.
1713 * For ranged MSI the CE-related interrupts can be masked. However
1714 * regardless how many MSI interrupts are assigned the first one
1715 * is always used for firmware indications (crashes) and cannot be
1716 * masked. To prevent the device from asserting the interrupt reset it
1717 * before proceeding with cleanup.
1719 ath10k_pci_safe_chip_reset(ar);
1721 ath10k_pci_irq_disable(ar);
1722 ath10k_pci_irq_sync(ar);
1723 ath10k_pci_flush(ar);
1725 spin_lock_irqsave(&ar_pci->ps_lock, flags);
1726 WARN_ON(ar_pci->ps_wake_refcount > 0);
1727 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
1730 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1731 void *req, u32 req_len,
1732 void *resp, u32 *resp_len)
1734 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1735 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1736 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1737 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1738 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1739 dma_addr_t req_paddr = 0;
1740 dma_addr_t resp_paddr = 0;
1741 struct bmi_xfer xfer = {};
1742 void *treq, *tresp = NULL;
1747 if (resp && !resp_len)
1750 if (resp && resp_len && *resp_len == 0)
1753 treq = kmemdup(req, req_len, GFP_KERNEL);
1757 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1758 ret = dma_mapping_error(ar->dev, req_paddr);
1764 if (resp && resp_len) {
1765 tresp = kzalloc(*resp_len, GFP_KERNEL);
1771 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1773 ret = dma_mapping_error(ar->dev, resp_paddr);
1779 xfer.wait_for_resp = true;
1782 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1785 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1789 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1792 unsigned int unused_nbytes;
1793 unsigned int unused_id;
1795 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1796 &unused_nbytes, &unused_id);
1798 /* non-zero means we did not time out */
1806 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1807 dma_unmap_single(ar->dev, resp_paddr,
1808 *resp_len, DMA_FROM_DEVICE);
1811 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1813 if (ret == 0 && resp_len) {
1814 *resp_len = min(*resp_len, xfer.resp_len);
1815 memcpy(resp, tresp, xfer.resp_len);
1824 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1826 struct bmi_xfer *xfer;
1828 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
1831 xfer->tx_done = true;
1834 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1836 struct ath10k *ar = ce_state->ar;
1837 struct bmi_xfer *xfer;
1839 unsigned int nbytes;
1840 unsigned int transfer_id;
1843 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1844 &nbytes, &transfer_id, &flags))
1847 if (WARN_ON_ONCE(!xfer))
1850 if (!xfer->wait_for_resp) {
1851 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1855 xfer->resp_len = nbytes;
1856 xfer->rx_done = true;
1859 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1860 struct ath10k_ce_pipe *rx_pipe,
1861 struct bmi_xfer *xfer)
1863 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1865 while (time_before_eq(jiffies, timeout)) {
1866 ath10k_pci_bmi_send_done(tx_pipe);
1867 ath10k_pci_bmi_recv_data(rx_pipe);
1869 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp))
1879 * Send an interrupt to the device to wake up the Target CPU
1880 * so it has an opportunity to notice any changed state.
1882 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1886 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
1887 val = ath10k_pci_read32(ar, addr);
1888 val |= CORE_CTRL_CPU_INTR_MASK;
1889 ath10k_pci_write32(ar, addr, val);
1894 static int ath10k_pci_get_num_banks(struct ath10k *ar)
1896 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1898 switch (ar_pci->pdev->device) {
1899 case QCA988X_2_0_DEVICE_ID:
1900 case QCA99X0_2_0_DEVICE_ID:
1902 case QCA6164_2_1_DEVICE_ID:
1903 case QCA6174_2_1_DEVICE_ID:
1904 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
1905 case QCA6174_HW_1_0_CHIP_ID_REV:
1906 case QCA6174_HW_1_1_CHIP_ID_REV:
1907 case QCA6174_HW_2_1_CHIP_ID_REV:
1908 case QCA6174_HW_2_2_CHIP_ID_REV:
1910 case QCA6174_HW_1_3_CHIP_ID_REV:
1912 case QCA6174_HW_3_0_CHIP_ID_REV:
1913 case QCA6174_HW_3_1_CHIP_ID_REV:
1914 case QCA6174_HW_3_2_CHIP_ID_REV:
1918 case QCA9377_1_0_DEVICE_ID:
1922 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
1926 static int ath10k_bus_get_num_banks(struct ath10k *ar)
1928 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1930 return ar_pci->bus_ops->get_num_banks(ar);
1933 int ath10k_pci_init_config(struct ath10k *ar)
1935 u32 interconnect_targ_addr;
1936 u32 pcie_state_targ_addr = 0;
1937 u32 pipe_cfg_targ_addr = 0;
1938 u32 svc_to_pipe_map = 0;
1939 u32 pcie_config_flags = 0;
1941 u32 ealloc_targ_addr;
1943 u32 flag2_targ_addr;
1946 /* Download to Target the CE Config and the service-to-CE map */
1947 interconnect_targ_addr =
1948 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1950 /* Supply Target-side CE configuration */
1951 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
1952 &pcie_state_targ_addr);
1954 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
1958 if (pcie_state_targ_addr == 0) {
1960 ath10k_err(ar, "Invalid pcie state addr\n");
1964 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1965 offsetof(struct pcie_state,
1967 &pipe_cfg_targ_addr);
1969 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
1973 if (pipe_cfg_targ_addr == 0) {
1975 ath10k_err(ar, "Invalid pipe cfg addr\n");
1979 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1980 target_ce_config_wlan,
1981 sizeof(struct ce_pipe_config) *
1982 NUM_TARGET_CE_CONFIG_WLAN);
1985 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
1989 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1990 offsetof(struct pcie_state,
1994 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
1998 if (svc_to_pipe_map == 0) {
2000 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2004 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2005 target_service_to_ce_map_wlan,
2006 sizeof(target_service_to_ce_map_wlan));
2008 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2012 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2013 offsetof(struct pcie_state,
2015 &pcie_config_flags);
2017 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2021 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2023 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2024 offsetof(struct pcie_state,
2028 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2032 /* configure early allocation */
2033 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2035 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2037 ath10k_err(ar, "Faile to get early alloc val: %d\n", ret);
2041 /* first bank is switched to IRAM */
2042 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2043 HI_EARLY_ALLOC_MAGIC_MASK);
2044 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2045 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2046 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2048 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2050 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2054 /* Tell Target to proceed with initialization */
2055 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2057 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2059 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2063 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2065 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2067 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2074 static void ath10k_pci_override_ce_config(struct ath10k *ar)
2076 struct ce_attr *attr;
2077 struct ce_pipe_config *config;
2079 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2080 * since it is currently used for other feature.
2083 /* Override Host's Copy Engine 5 configuration */
2084 attr = &host_ce_config_wlan[5];
2085 attr->src_sz_max = 0;
2086 attr->dest_nentries = 0;
2088 /* Override Target firmware's Copy Engine configuration */
2089 config = &target_ce_config_wlan[5];
2090 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2091 config->nbytes_max = __cpu_to_le32(2048);
2093 /* Map from service/endpoint to Copy Engine */
2094 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2097 int ath10k_pci_alloc_pipes(struct ath10k *ar)
2099 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2100 struct ath10k_pci_pipe *pipe;
2103 for (i = 0; i < CE_COUNT; i++) {
2104 pipe = &ar_pci->pipe_info[i];
2105 pipe->ce_hdl = &ar_pci->ce_states[i];
2107 pipe->hif_ce_state = ar;
2109 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2111 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2116 /* Last CE is Diagnostic Window */
2117 if (i == CE_DIAG_PIPE) {
2118 ar_pci->ce_diag = pipe->ce_hdl;
2122 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2128 void ath10k_pci_free_pipes(struct ath10k *ar)
2132 for (i = 0; i < CE_COUNT; i++)
2133 ath10k_ce_free_pipe(ar, i);
2136 int ath10k_pci_init_pipes(struct ath10k *ar)
2140 for (i = 0; i < CE_COUNT; i++) {
2141 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2143 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2152 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2154 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2155 FW_IND_EVENT_PENDING;
2158 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2162 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2163 val &= ~FW_IND_EVENT_PENDING;
2164 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2167 /* this function effectively clears target memory controller assert line */
2168 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2172 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2173 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2174 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2175 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2179 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2180 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2181 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2182 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2187 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2191 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2193 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2194 SOC_RESET_CONTROL_ADDRESS);
2195 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2196 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2199 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2203 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2204 SOC_RESET_CONTROL_ADDRESS);
2206 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2207 val | SOC_RESET_CONTROL_CE_RST_MASK);
2209 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2210 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2213 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2217 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2218 SOC_LF_TIMER_CONTROL0_ADDRESS);
2219 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2220 SOC_LF_TIMER_CONTROL0_ADDRESS,
2221 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2224 static int ath10k_pci_warm_reset(struct ath10k *ar)
2228 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2230 spin_lock_bh(&ar->data_lock);
2231 ar->stats.fw_warm_reset_counter++;
2232 spin_unlock_bh(&ar->data_lock);
2234 ath10k_pci_irq_disable(ar);
2236 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2237 * were to access copy engine while host performs copy engine reset
2238 * then it is possible for the device to confuse pci-e controller to
2239 * the point of bringing host system to a complete stop (i.e. hang).
2241 ath10k_pci_warm_reset_si0(ar);
2242 ath10k_pci_warm_reset_cpu(ar);
2243 ath10k_pci_init_pipes(ar);
2244 ath10k_pci_wait_for_target_init(ar);
2246 ath10k_pci_warm_reset_clear_lf(ar);
2247 ath10k_pci_warm_reset_ce(ar);
2248 ath10k_pci_warm_reset_cpu(ar);
2249 ath10k_pci_init_pipes(ar);
2251 ret = ath10k_pci_wait_for_target_init(ar);
2253 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2257 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2262 static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2264 if (QCA_REV_988X(ar) || QCA_REV_6174(ar)) {
2265 return ath10k_pci_warm_reset(ar);
2266 } else if (QCA_REV_99X0(ar)) {
2267 ath10k_pci_irq_disable(ar);
2268 return ath10k_pci_qca99x0_chip_reset(ar);
2274 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2279 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2281 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2282 * It is thus preferred to use warm reset which is safer but may not be
2283 * able to recover the device from all possible fail scenarios.
2285 * Warm reset doesn't always work on first try so attempt it a few
2286 * times before giving up.
2288 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2289 ret = ath10k_pci_warm_reset(ar);
2291 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2292 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2297 /* FIXME: Sometimes copy engine doesn't recover after warm
2298 * reset. In most cases this needs cold reset. In some of these
2299 * cases the device is in such a state that a cold reset may
2302 * Reading any host interest register via copy engine is
2303 * sufficient to verify if device is capable of booting
2306 ret = ath10k_pci_init_pipes(ar);
2308 ath10k_warn(ar, "failed to init copy engine: %d\n",
2313 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2316 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2321 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2325 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2326 ath10k_warn(ar, "refusing cold reset as requested\n");
2330 ret = ath10k_pci_cold_reset(ar);
2332 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2336 ret = ath10k_pci_wait_for_target_init(ar);
2338 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2343 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2348 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2352 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2354 /* FIXME: QCA6174 requires cold + warm reset to work. */
2356 ret = ath10k_pci_cold_reset(ar);
2358 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2362 ret = ath10k_pci_wait_for_target_init(ar);
2364 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2369 ret = ath10k_pci_warm_reset(ar);
2371 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2375 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2380 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2384 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2386 ret = ath10k_pci_cold_reset(ar);
2388 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2392 ret = ath10k_pci_wait_for_target_init(ar);
2394 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2399 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2404 static int ath10k_pci_chip_reset(struct ath10k *ar)
2406 if (QCA_REV_988X(ar))
2407 return ath10k_pci_qca988x_chip_reset(ar);
2408 else if (QCA_REV_6174(ar))
2409 return ath10k_pci_qca6174_chip_reset(ar);
2410 else if (QCA_REV_9377(ar))
2411 return ath10k_pci_qca6174_chip_reset(ar);
2412 else if (QCA_REV_99X0(ar))
2413 return ath10k_pci_qca99x0_chip_reset(ar);
2418 static int ath10k_pci_hif_power_up(struct ath10k *ar)
2420 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2423 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2425 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2427 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2428 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2431 * Bring the target up cleanly.
2433 * The target may be in an undefined state with an AUX-powered Target
2434 * and a Host in WoW mode. If the Host crashes, loses power, or is
2435 * restarted (without unloading the driver) then the Target is left
2436 * (aux) powered and running. On a subsequent driver load, the Target
2437 * is in an unexpected state. We try to catch that here in order to
2438 * reset the Target and retry the probe.
2440 ret = ath10k_pci_chip_reset(ar);
2442 if (ath10k_pci_has_fw_crashed(ar)) {
2443 ath10k_warn(ar, "firmware crashed during chip reset\n");
2444 ath10k_pci_fw_crashed_clear(ar);
2445 ath10k_pci_fw_crashed_dump(ar);
2448 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2452 ret = ath10k_pci_init_pipes(ar);
2454 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2458 ret = ath10k_pci_init_config(ar);
2460 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2464 ret = ath10k_pci_wake_target_cpu(ar);
2466 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2473 ath10k_pci_ce_deinit(ar);
2479 void ath10k_pci_hif_power_down(struct ath10k *ar)
2481 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2483 /* Currently hif_power_up performs effectively a reset and hif_stop
2484 * resets the chip as well so there's no point in resetting here.
2490 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2492 /* The grace timer can still be counting down and ar->ps_awake be true.
2493 * It is known that the device may be asleep after resuming regardless
2494 * of the SoC powersave state before suspending. Hence make sure the
2495 * device is asleep before proceeding.
2497 ath10k_pci_sleep_sync(ar);
2502 static int ath10k_pci_hif_resume(struct ath10k *ar)
2504 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2505 struct pci_dev *pdev = ar_pci->pdev;
2509 ret = ath10k_pci_force_wake(ar);
2511 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2515 /* Suspend/Resume resets the PCI configuration space, so we have to
2516 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2517 * from interfering with C3 CPU state. pci_restore_state won't help
2518 * here since it only restores the first 64 bytes pci config header.
2520 pci_read_config_dword(pdev, 0x40, &val);
2521 if ((val & 0x0000ff00) != 0)
2522 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2528 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2529 .tx_sg = ath10k_pci_hif_tx_sg,
2530 .diag_read = ath10k_pci_hif_diag_read,
2531 .diag_write = ath10k_pci_diag_write_mem,
2532 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2533 .start = ath10k_pci_hif_start,
2534 .stop = ath10k_pci_hif_stop,
2535 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2536 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2537 .send_complete_check = ath10k_pci_hif_send_complete_check,
2538 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
2539 .power_up = ath10k_pci_hif_power_up,
2540 .power_down = ath10k_pci_hif_power_down,
2541 .read32 = ath10k_pci_read32,
2542 .write32 = ath10k_pci_write32,
2544 .suspend = ath10k_pci_hif_suspend,
2545 .resume = ath10k_pci_hif_resume,
2549 static void ath10k_pci_ce_tasklet(unsigned long ptr)
2551 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
2552 struct ath10k_pci *ar_pci = pipe->ar_pci;
2554 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2557 static void ath10k_msi_err_tasklet(unsigned long data)
2559 struct ath10k *ar = (struct ath10k *)data;
2561 if (!ath10k_pci_has_fw_crashed(ar)) {
2562 ath10k_warn(ar, "received unsolicited fw crash interrupt\n");
2566 ath10k_pci_irq_disable(ar);
2567 ath10k_pci_fw_crashed_clear(ar);
2568 ath10k_pci_fw_crashed_dump(ar);
2572 * Handler for a per-engine interrupt on a PARTICULAR CE.
2573 * This is used in cases where each CE has a private MSI interrupt.
2575 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2577 struct ath10k *ar = arg;
2578 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2579 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2581 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2582 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
2588 * NOTE: We are able to derive ce_id from irq because we
2589 * use a one-to-one mapping for CE's 0..5.
2590 * CE's 6 & 7 do not use interrupts at all.
2592 * This mapping must be kept in sync with the mapping
2595 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2599 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2601 struct ath10k *ar = arg;
2602 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2604 tasklet_schedule(&ar_pci->msi_fw_err);
2609 * Top-level interrupt handler for all PCI interrupts from a Target.
2610 * When a block of MSI interrupts is allocated, this top-level handler
2611 * is not used; instead, we directly call the correct sub-handler.
2613 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2615 struct ath10k *ar = arg;
2616 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2619 ret = ath10k_pci_force_wake(ar);
2621 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
2625 if (ar_pci->num_msi_intrs == 0) {
2626 if (!ath10k_pci_irq_pending(ar))
2629 ath10k_pci_disable_and_clear_legacy_irq(ar);
2632 tasklet_schedule(&ar_pci->intr_tq);
2637 static void ath10k_pci_tasklet(unsigned long data)
2639 struct ath10k *ar = (struct ath10k *)data;
2640 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2642 if (ath10k_pci_has_fw_crashed(ar)) {
2643 ath10k_pci_irq_disable(ar);
2644 ath10k_pci_fw_crashed_clear(ar);
2645 ath10k_pci_fw_crashed_dump(ar);
2649 ath10k_ce_per_engine_service_any(ar);
2651 /* Re-enable legacy irq that was disabled in the irq handler */
2652 if (ar_pci->num_msi_intrs == 0)
2653 ath10k_pci_enable_legacy_irq(ar);
2656 static int ath10k_pci_request_irq_msix(struct ath10k *ar)
2658 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2661 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2662 ath10k_pci_msi_fw_handler,
2663 IRQF_SHARED, "ath10k_pci", ar);
2665 ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n",
2666 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2670 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2671 ret = request_irq(ar_pci->pdev->irq + i,
2672 ath10k_pci_per_engine_handler,
2673 IRQF_SHARED, "ath10k_pci", ar);
2675 ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n",
2676 ar_pci->pdev->irq + i, ret);
2678 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2679 free_irq(ar_pci->pdev->irq + i, ar);
2681 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2689 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2691 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2694 ret = request_irq(ar_pci->pdev->irq,
2695 ath10k_pci_interrupt_handler,
2696 IRQF_SHARED, "ath10k_pci", ar);
2698 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
2699 ar_pci->pdev->irq, ret);
2706 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2708 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2711 ret = request_irq(ar_pci->pdev->irq,
2712 ath10k_pci_interrupt_handler,
2713 IRQF_SHARED, "ath10k_pci", ar);
2715 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
2716 ar_pci->pdev->irq, ret);
2723 static int ath10k_pci_request_irq(struct ath10k *ar)
2725 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2727 switch (ar_pci->num_msi_intrs) {
2729 return ath10k_pci_request_irq_legacy(ar);
2731 return ath10k_pci_request_irq_msi(ar);
2733 return ath10k_pci_request_irq_msix(ar);
2737 static void ath10k_pci_free_irq(struct ath10k *ar)
2739 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2742 /* There's at least one interrupt irregardless whether its legacy INTR
2743 * or MSI or MSI-X */
2744 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2745 free_irq(ar_pci->pdev->irq + i, ar);
2748 void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2750 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2753 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2754 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2757 for (i = 0; i < CE_COUNT; i++) {
2758 ar_pci->pipe_info[i].ar_pci = ar_pci;
2759 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
2760 (unsigned long)&ar_pci->pipe_info[i]);
2764 static int ath10k_pci_init_irq(struct ath10k *ar)
2766 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2769 ath10k_pci_init_irq_tasklets(ar);
2771 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2772 ath10k_info(ar, "limiting irq mode to: %d\n",
2773 ath10k_pci_irq_mode);
2776 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) {
2777 ar_pci->num_msi_intrs = MSI_ASSIGN_CE_MAX + 1;
2778 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2779 ar_pci->num_msi_intrs);
2787 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2788 ar_pci->num_msi_intrs = 1;
2789 ret = pci_enable_msi(ar_pci->pdev);
2798 * A potential race occurs here: The CORE_BASE write
2799 * depends on target correctly decoding AXI address but
2800 * host won't know when target writes BAR to CORE_CTRL.
2801 * This write might get lost if target has NOT written BAR.
2802 * For now, fix the race by repeating the write in below
2803 * synchronization checking. */
2804 ar_pci->num_msi_intrs = 0;
2806 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2807 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2812 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2814 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2818 static int ath10k_pci_deinit_irq(struct ath10k *ar)
2820 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2822 switch (ar_pci->num_msi_intrs) {
2824 ath10k_pci_deinit_irq_legacy(ar);
2827 pci_disable_msi(ar_pci->pdev);
2834 int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2836 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2837 unsigned long timeout;
2840 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2842 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2845 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2847 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
2850 /* target should never return this */
2851 if (val == 0xffffffff)
2854 /* the device has crashed so don't bother trying anymore */
2855 if (val & FW_IND_EVENT_PENDING)
2858 if (val & FW_IND_INITIALIZED)
2861 if (ar_pci->num_msi_intrs == 0)
2862 /* Fix potential race by repeating CORE_BASE writes */
2863 ath10k_pci_enable_legacy_irq(ar);
2866 } while (time_before(jiffies, timeout));
2868 ath10k_pci_disable_and_clear_legacy_irq(ar);
2869 ath10k_pci_irq_msi_fw_mask(ar);
2871 if (val == 0xffffffff) {
2872 ath10k_err(ar, "failed to read device register, device is gone\n");
2876 if (val & FW_IND_EVENT_PENDING) {
2877 ath10k_warn(ar, "device has crashed during init\n");
2881 if (!(val & FW_IND_INITIALIZED)) {
2882 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
2887 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
2891 static int ath10k_pci_cold_reset(struct ath10k *ar)
2895 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
2897 spin_lock_bh(&ar->data_lock);
2899 ar->stats.fw_cold_reset_counter++;
2901 spin_unlock_bh(&ar->data_lock);
2903 /* Put Target, including PCIe, into RESET. */
2904 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2906 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2908 /* After writing into SOC_GLOBAL_RESET to put device into
2909 * reset and pulling out of reset pcie may not be stable
2910 * for any immediate pcie register access and cause bus error,
2911 * add delay before any pcie access request to fix this issue.
2915 /* Pull Target, including PCIe, out of RESET. */
2917 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2921 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
2926 static int ath10k_pci_claim(struct ath10k *ar)
2928 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2929 struct pci_dev *pdev = ar_pci->pdev;
2932 pci_set_drvdata(pdev, ar);
2934 ret = pci_enable_device(pdev);
2936 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
2940 ret = pci_request_region(pdev, BAR_NUM, "ath");
2942 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
2947 /* Target expects 32 bit DMA. Enforce it. */
2948 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2950 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
2954 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2956 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
2961 pci_set_master(pdev);
2963 /* Arrange for access to Target SoC registers. */
2964 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
2965 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
2967 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
2972 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2976 pci_clear_master(pdev);
2979 pci_release_region(pdev, BAR_NUM);
2982 pci_disable_device(pdev);
2987 static void ath10k_pci_release(struct ath10k *ar)
2989 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2990 struct pci_dev *pdev = ar_pci->pdev;
2992 pci_iounmap(pdev, ar_pci->mem);
2993 pci_release_region(pdev, BAR_NUM);
2994 pci_clear_master(pdev);
2995 pci_disable_device(pdev);
2998 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
3000 const struct ath10k_pci_supp_chip *supp_chip;
3002 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3004 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3005 supp_chip = &ath10k_pci_supp_chips[i];
3007 if (supp_chip->dev_id == dev_id &&
3008 supp_chip->rev_id == rev_id)
3015 int ath10k_pci_setup_resource(struct ath10k *ar)
3017 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3020 spin_lock_init(&ar_pci->ce_lock);
3021 spin_lock_init(&ar_pci->ps_lock);
3023 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
3026 if (QCA_REV_6174(ar))
3027 ath10k_pci_override_ce_config(ar);
3029 ret = ath10k_pci_alloc_pipes(ar);
3031 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3039 void ath10k_pci_release_resource(struct ath10k *ar)
3041 ath10k_pci_kill_tasklet(ar);
3042 ath10k_pci_ce_deinit(ar);
3043 ath10k_pci_free_pipes(ar);
3046 static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3047 .read32 = ath10k_bus_pci_read32,
3048 .write32 = ath10k_bus_pci_write32,
3049 .get_num_banks = ath10k_pci_get_num_banks,
3052 static int ath10k_pci_probe(struct pci_dev *pdev,
3053 const struct pci_device_id *pci_dev)
3057 struct ath10k_pci *ar_pci;
3058 enum ath10k_hw_rev hw_rev;
3062 switch (pci_dev->device) {
3063 case QCA988X_2_0_DEVICE_ID:
3064 hw_rev = ATH10K_HW_QCA988X;
3067 case QCA6164_2_1_DEVICE_ID:
3068 case QCA6174_2_1_DEVICE_ID:
3069 hw_rev = ATH10K_HW_QCA6174;
3072 case QCA99X0_2_0_DEVICE_ID:
3073 hw_rev = ATH10K_HW_QCA99X0;
3076 case QCA9377_1_0_DEVICE_ID:
3077 hw_rev = ATH10K_HW_QCA9377;
3085 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3086 hw_rev, &ath10k_pci_hif_ops);
3088 dev_err(&pdev->dev, "failed to allocate core\n");
3092 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3093 pdev->vendor, pdev->device,
3094 pdev->subsystem_vendor, pdev->subsystem_device);
3096 ar_pci = ath10k_pci_priv(ar);
3097 ar_pci->pdev = pdev;
3098 ar_pci->dev = &pdev->dev;
3100 ar->dev_id = pci_dev->device;
3101 ar_pci->pci_ps = pci_ps;
3102 ar_pci->bus_ops = &ath10k_pci_bus_ops;
3104 ar->id.vendor = pdev->vendor;
3105 ar->id.device = pdev->device;
3106 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3107 ar->id.subsystem_device = pdev->subsystem_device;
3109 setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer,
3112 ret = ath10k_pci_setup_resource(ar);
3114 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3115 goto err_core_destroy;
3118 ret = ath10k_pci_claim(ar);
3120 ath10k_err(ar, "failed to claim device: %d\n", ret);
3121 goto err_free_pipes;
3124 ret = ath10k_pci_force_wake(ar);
3126 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3130 ath10k_pci_ce_deinit(ar);
3131 ath10k_pci_irq_disable(ar);
3133 ret = ath10k_pci_init_irq(ar);
3135 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3139 ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
3140 ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs,
3141 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3143 ret = ath10k_pci_request_irq(ar);
3145 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3146 goto err_deinit_irq;
3149 ret = ath10k_pci_chip_reset(ar);
3151 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3155 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3156 if (chip_id == 0xffffffff) {
3157 ath10k_err(ar, "failed to get chip id\n");
3161 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
3162 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3163 pdev->device, chip_id);
3167 ret = ath10k_core_register(ar, chip_id);
3169 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3176 ath10k_pci_free_irq(ar);
3177 ath10k_pci_kill_tasklet(ar);
3180 ath10k_pci_deinit_irq(ar);
3183 ath10k_pci_sleep_sync(ar);
3184 ath10k_pci_release(ar);
3187 ath10k_pci_free_pipes(ar);
3190 ath10k_core_destroy(ar);
3195 static void ath10k_pci_remove(struct pci_dev *pdev)
3197 struct ath10k *ar = pci_get_drvdata(pdev);
3198 struct ath10k_pci *ar_pci;
3200 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3205 ar_pci = ath10k_pci_priv(ar);
3210 ath10k_core_unregister(ar);
3211 ath10k_pci_free_irq(ar);
3212 ath10k_pci_deinit_irq(ar);
3213 ath10k_pci_release_resource(ar);
3214 ath10k_pci_sleep_sync(ar);
3215 ath10k_pci_release(ar);
3216 ath10k_core_destroy(ar);
3219 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3221 static struct pci_driver ath10k_pci_driver = {
3222 .name = "ath10k_pci",
3223 .id_table = ath10k_pci_id_table,
3224 .probe = ath10k_pci_probe,
3225 .remove = ath10k_pci_remove,
3228 static int __init ath10k_pci_init(void)
3232 ret = pci_register_driver(&ath10k_pci_driver);
3234 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3237 ret = ath10k_ahb_init();
3239 printk(KERN_ERR "ahb init failed: %d\n", ret);
3243 module_init(ath10k_pci_init);
3245 static void __exit ath10k_pci_exit(void)
3247 pci_unregister_driver(&ath10k_pci_driver);
3251 module_exit(ath10k_pci_exit);
3253 MODULE_AUTHOR("Qualcomm Atheros");
3254 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
3255 MODULE_LICENSE("Dual BSD/GPL");
3257 /* QCA988x 2.0 firmware files */
3258 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
3259 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3260 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3261 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3262 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3263 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3264 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3266 /* QCA6174 2.1 firmware files */
3267 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3268 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3269 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3270 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3272 /* QCA6174 3.1 firmware files */
3273 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3274 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3275 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3276 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3278 /* QCA9377 1.0 firmware files */
3279 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3280 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);