2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 /******************************\
21 Hardware Descriptor Functions
22 \******************************/
34 * Initialize the 2-word tx control descriptor on 5210/5211
37 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
38 unsigned int pkt_len, unsigned int hdr_len, int padsize,
39 enum ath5k_pkt_type type,
40 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
41 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
42 unsigned int rtscts_rate, unsigned int rtscts_duration)
45 struct ath5k_hw_2w_tx_ctl *tx_ctl;
46 unsigned int frame_len;
48 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
52 * - Zero retries don't make sense.
53 * - A zero rate will put the HW into a mode where it continously sends
54 * noise on the channel, so it is important to avoid this.
56 if (unlikely(tx_tries0 == 0)) {
57 ATH5K_ERR(ah->ah_sc, "zero retries\n");
61 if (unlikely(tx_rate0 == 0)) {
62 ATH5K_ERR(ah->ah_sc, "zero rate\n");
67 /* Clear descriptor */
68 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
70 /* Setup control descriptor */
72 /* Verify and set frame length */
74 /* remove padding we might have added before */
75 frame_len = pkt_len - padsize + FCS_LEN;
77 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
80 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
82 /* Verify and set buffer length */
84 /* NB: beacon's BufLen must be a multiple of 4 bytes */
85 if (type == AR5K_PKT_TYPE_BEACON)
86 pkt_len = roundup(pkt_len, 4);
88 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
91 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
94 * Verify and set header length (only 5210)
96 if (ah->ah_version == AR5K_AR5210) {
97 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210)
99 tx_ctl->tx_control_0 |=
100 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210);
103 /*Differences between 5210-5211*/
104 if (ah->ah_version == AR5K_AR5210) {
106 case AR5K_PKT_TYPE_BEACON:
107 case AR5K_PKT_TYPE_PROBE_RESP:
108 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
109 case AR5K_PKT_TYPE_PIFS:
110 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
115 tx_ctl->tx_control_0 |=
116 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210) |
117 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
120 tx_ctl->tx_control_0 |=
121 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
122 AR5K_REG_SM(antenna_mode,
123 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
124 tx_ctl->tx_control_1 |=
125 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211);
128 #define _TX_FLAGS(_c, _flag) \
129 if (flags & AR5K_TXDESC_##_flag) { \
130 tx_ctl->tx_control_##_c |= \
131 AR5K_2W_TX_DESC_CTL##_c##_##_flag; \
133 #define _TX_FLAGS_5211(_c, _flag) \
134 if (flags & AR5K_TXDESC_##_flag) { \
135 tx_ctl->tx_control_##_c |= \
136 AR5K_2W_TX_DESC_CTL##_c##_##_flag##_5211; \
138 _TX_FLAGS(0, CLRDMASK);
139 _TX_FLAGS(0, INTREQ);
140 _TX_FLAGS(0, RTSENA);
142 if (ah->ah_version == AR5K_AR5211) {
143 _TX_FLAGS_5211(0, VEOL);
144 _TX_FLAGS_5211(1, NOACK);
148 #undef _TX_FLAGS_5211
153 if (key_index != AR5K_TXKEYIX_INVALID) {
154 tx_ctl->tx_control_0 |=
155 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
156 tx_ctl->tx_control_1 |=
157 AR5K_REG_SM(key_index,
158 AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX);
162 * RTS/CTS Duration [5210 ?]
164 if ((ah->ah_version == AR5K_AR5210) &&
165 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
166 tx_ctl->tx_control_1 |= rtscts_duration &
167 AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210;
173 * Initialize the 4-word tx control descriptor on 5212
175 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
176 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
178 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
179 unsigned int tx_tries0, unsigned int key_index,
180 unsigned int antenna_mode, unsigned int flags,
181 unsigned int rtscts_rate,
182 unsigned int rtscts_duration)
184 struct ath5k_hw_4w_tx_ctl *tx_ctl;
185 unsigned int frame_len;
187 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
191 * - Zero retries don't make sense.
192 * - A zero rate will put the HW into a mode where it continously sends
193 * noise on the channel, so it is important to avoid this.
195 if (unlikely(tx_tries0 == 0)) {
196 ATH5K_ERR(ah->ah_sc, "zero retries\n");
200 if (unlikely(tx_rate0 == 0)) {
201 ATH5K_ERR(ah->ah_sc, "zero rate\n");
206 tx_power += ah->ah_txpower.txp_offset;
207 if (tx_power > AR5K_TUNE_MAX_TXPOWER)
208 tx_power = AR5K_TUNE_MAX_TXPOWER;
210 /* Clear descriptor */
211 memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
213 /* Setup control descriptor */
215 /* Verify and set frame length */
217 /* remove padding we might have added before */
218 frame_len = pkt_len - padsize + FCS_LEN;
220 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
223 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
225 /* Verify and set buffer length */
227 /* NB: beacon's BufLen must be a multiple of 4 bytes */
228 if (type == AR5K_PKT_TYPE_BEACON)
229 pkt_len = roundup(pkt_len, 4);
231 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
234 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
236 tx_ctl->tx_control_0 |=
237 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
238 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
239 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
240 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
241 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0,
242 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
243 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
245 #define _TX_FLAGS(_c, _flag) \
246 if (flags & AR5K_TXDESC_##_flag) { \
247 tx_ctl->tx_control_##_c |= \
248 AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
251 _TX_FLAGS(0, CLRDMASK);
253 _TX_FLAGS(0, INTREQ);
254 _TX_FLAGS(0, RTSENA);
255 _TX_FLAGS(0, CTSENA);
263 if (key_index != AR5K_TXKEYIX_INVALID) {
264 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
265 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
266 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX);
272 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
273 if ((flags & AR5K_TXDESC_RTSENA) &&
274 (flags & AR5K_TXDESC_CTSENA))
276 tx_ctl->tx_control_2 |= rtscts_duration &
277 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
278 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
279 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
286 * Initialize a 4-word multi rate retry tx control descriptor on 5212
289 ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
290 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
291 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
293 struct ath5k_hw_4w_tx_ctl *tx_ctl;
295 /* no mrr support for cards older than 5212 */
296 if (ah->ah_version < AR5K_AR5212)
300 * Rates can be 0 as long as the retry count is 0 too.
301 * A zero rate and nonzero retry count will put the HW into a mode where
302 * it continously sends noise on the channel, so it is important to
305 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
306 (tx_rate2 == 0 && tx_tries2 != 0) ||
307 (tx_rate3 == 0 && tx_tries3 != 0))) {
308 ATH5K_ERR(ah->ah_sc, "zero rate\n");
313 if (ah->ah_version == AR5K_AR5212) {
314 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
316 #define _XTX_TRIES(_n) \
317 if (tx_tries##_n) { \
318 tx_ctl->tx_control_2 |= \
319 AR5K_REG_SM(tx_tries##_n, \
320 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
321 tx_ctl->tx_control_3 |= \
322 AR5K_REG_SM(tx_rate##_n, \
323 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
339 * Proccess the tx status descriptor on 5210/5211
341 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
342 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
344 struct ath5k_hw_2w_tx_ctl *tx_ctl;
345 struct ath5k_hw_tx_status *tx_status;
347 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
348 tx_status = &desc->ud.ds_tx5210.tx_stat;
350 /* No frame has been send or error */
351 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
355 * Get descriptor status
357 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
358 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
359 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
360 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
361 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
362 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
363 /*TODO: ts->ts_virtcol + test*/
364 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
365 AR5K_DESC_TX_STATUS1_SEQ_NUM);
366 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
367 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
370 ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
371 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
372 ts->ts_retry[0] = ts->ts_longretry;
373 ts->ts_final_idx = 0;
375 if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
376 if (tx_status->tx_status_0 &
377 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
378 ts->ts_status |= AR5K_TXERR_XRETRY;
380 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
381 ts->ts_status |= AR5K_TXERR_FIFO;
383 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
384 ts->ts_status |= AR5K_TXERR_FILT;
391 * Proccess a tx status descriptor on 5212
393 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
394 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
396 struct ath5k_hw_4w_tx_ctl *tx_ctl;
397 struct ath5k_hw_tx_status *tx_status;
399 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
400 tx_status = &desc->ud.ds_tx5212.tx_stat;
402 /* No frame has been send or error */
403 if (unlikely(!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE)))
407 * Get descriptor status
409 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
410 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
411 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
412 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
413 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
414 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
415 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
416 AR5K_DESC_TX_STATUS1_SEQ_NUM);
417 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
418 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
419 ts->ts_antenna = (tx_status->tx_status_1 &
420 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212) ? 2 : 1;
423 ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
424 AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212);
426 /* The longretry counter has the number of un-acked retries
427 * for the final rate. To get the total number of retries
428 * we have to add the retry counters for the other rates
431 ts->ts_retry[ts->ts_final_idx] = ts->ts_longretry;
432 switch (ts->ts_final_idx) {
434 ts->ts_rate[3] = AR5K_REG_MS(tx_ctl->tx_control_3,
435 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
437 ts->ts_retry[2] = AR5K_REG_MS(tx_ctl->tx_control_2,
438 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
439 ts->ts_longretry += ts->ts_retry[2];
442 ts->ts_rate[2] = AR5K_REG_MS(tx_ctl->tx_control_3,
443 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
445 ts->ts_retry[1] = AR5K_REG_MS(tx_ctl->tx_control_2,
446 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
447 ts->ts_longretry += ts->ts_retry[1];
450 ts->ts_rate[1] = AR5K_REG_MS(tx_ctl->tx_control_3,
451 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
453 ts->ts_retry[0] = AR5K_REG_MS(tx_ctl->tx_control_2,
454 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
455 ts->ts_longretry += ts->ts_retry[0];
458 ts->ts_rate[0] = tx_ctl->tx_control_3 &
459 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
464 if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
465 if (tx_status->tx_status_0 &
466 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
467 ts->ts_status |= AR5K_TXERR_XRETRY;
469 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
470 ts->ts_status |= AR5K_TXERR_FIFO;
472 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
473 ts->ts_status |= AR5K_TXERR_FILT;
484 * Initialize an rx control descriptor
486 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
487 u32 size, unsigned int flags)
489 struct ath5k_hw_rx_ctl *rx_ctl;
491 rx_ctl = &desc->ud.ds_rx.rx_ctl;
494 * Clear the descriptor
495 * If we don't clean the status descriptor,
496 * while scanning we get too many results,
497 * most of them virtual, after some secs
498 * of scanning system hangs. M.F.
500 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
502 if (unlikely(size & ~AR5K_DESC_RX_CTL1_BUF_LEN))
505 /* Setup descriptor */
506 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
508 if (flags & AR5K_RXDESC_INTREQ)
509 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
515 * Proccess the rx status descriptor on 5210/5211
517 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
518 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
520 struct ath5k_hw_rx_status *rx_status;
522 rx_status = &desc->ud.ds_rx.rx_stat;
524 /* No frame received / not ready */
525 if (unlikely(!(rx_status->rx_status_1 &
526 AR5K_5210_RX_DESC_STATUS1_DONE)))
529 memset(rs, 0, sizeof(struct ath5k_rx_status));
532 * Frame receive status
534 rs->rs_datalen = rx_status->rx_status_0 &
535 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
536 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
537 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
538 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
539 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
540 rs->rs_more = !!(rx_status->rx_status_0 &
541 AR5K_5210_RX_DESC_STATUS0_MORE);
542 /* TODO: this timestamp is 13 bit, later on we assume 15 bit!
543 * also the HAL code for 5210 says the timestamp is bits [10..22] of the
544 * TSF, and extends the timestamp here to 15 bit.
545 * we need to check on 5210...
547 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
548 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
550 if (ah->ah_version == AR5K_AR5211)
551 rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
552 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211);
554 rs->rs_antenna = (rx_status->rx_status_0 &
555 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210)
561 if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
562 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
563 AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
565 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
568 * Receive/descriptor errors
570 if (!(rx_status->rx_status_1 &
571 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
572 if (rx_status->rx_status_1 &
573 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
574 rs->rs_status |= AR5K_RXERR_CRC;
577 if ((ah->ah_version == AR5K_AR5210) &&
578 (rx_status->rx_status_1 &
579 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210))
580 rs->rs_status |= AR5K_RXERR_FIFO;
582 if (rx_status->rx_status_1 &
583 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
584 rs->rs_status |= AR5K_RXERR_PHY;
585 rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
586 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
589 if (rx_status->rx_status_1 &
590 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
591 rs->rs_status |= AR5K_RXERR_DECRYPT;
598 * Proccess the rx status descriptor on 5212
600 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
601 struct ath5k_desc *desc,
602 struct ath5k_rx_status *rs)
604 struct ath5k_hw_rx_status *rx_status;
606 rx_status = &desc->ud.ds_rx.rx_stat;
608 /* No frame received / not ready */
609 if (unlikely(!(rx_status->rx_status_1 &
610 AR5K_5212_RX_DESC_STATUS1_DONE)))
613 memset(rs, 0, sizeof(struct ath5k_rx_status));
616 * Frame receive status
618 rs->rs_datalen = rx_status->rx_status_0 &
619 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
620 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
621 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
622 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
623 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
624 rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
625 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
626 rs->rs_more = !!(rx_status->rx_status_0 &
627 AR5K_5212_RX_DESC_STATUS0_MORE);
628 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
629 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
634 if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
635 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
636 AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
638 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
641 * Receive/descriptor errors
643 if (!(rx_status->rx_status_1 &
644 AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
645 if (rx_status->rx_status_1 &
646 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
647 rs->rs_status |= AR5K_RXERR_CRC;
649 if (rx_status->rx_status_1 &
650 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
651 rs->rs_status |= AR5K_RXERR_PHY;
652 rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
653 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE);
654 ath5k_ani_phy_error_report(ah, rs->rs_phyerr);
657 if (rx_status->rx_status_1 &
658 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
659 rs->rs_status |= AR5K_RXERR_DECRYPT;
661 if (rx_status->rx_status_1 &
662 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
663 rs->rs_status |= AR5K_RXERR_MIC;
669 * Init function pointers inside ath5k_hw struct
671 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
673 if (ah->ah_version == AR5K_AR5212) {
674 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
675 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
676 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
677 } else if (ah->ah_version <= AR5K_AR5211) {
678 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
679 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
680 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;