2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include "ar9003_phy.h"
20 #include "ar9003_rtt.h"
21 #include "ar9003_mci.h"
23 #define MAX_MEASUREMENT MAX_IQCAL_MEASUREMENT
24 #define MAX_MAG_DELTA 11
25 #define MAX_PHS_DELTA 10
29 int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
30 int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
34 enum ar9003_cal_types {
35 IQ_MISMATCH_CAL = BIT(0),
36 TEMP_COMP_CAL = BIT(1),
39 static void ar9003_hw_setup_calibration(struct ath_hw *ah,
40 struct ath9k_cal_list *currCal)
42 struct ath_common *common = ath9k_hw_common(ah);
44 /* Select calibration to run */
45 switch (currCal->calData->calType) {
48 * Start calibration with
49 * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
51 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
52 AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
53 currCal->calData->calCountMax);
54 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
56 ath_dbg(common, CALIBRATE,
57 "starting IQ Mismatch Calibration\n");
60 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
63 ath_dbg(common, CALIBRATE,
64 "starting Temperature Compensation Calibration\n");
65 REG_SET_BIT(ah, AR_CH0_THERM, AR_CH0_THERM_LOCAL);
66 REG_SET_BIT(ah, AR_CH0_THERM, AR_CH0_THERM_START);
69 ath_err(common, "Invalid calibration type\n");
75 * Generic calibration routine.
76 * Recalibrate the lower PHY chips to account for temperature/environment
79 static bool ar9003_hw_per_calibration(struct ath_hw *ah,
80 struct ath9k_channel *ichan,
82 struct ath9k_cal_list *currCal)
84 struct ath9k_hw_cal_data *caldata = ah->caldata;
85 const struct ath9k_percal_data *cur_caldata = currCal->calData;
87 /* Calibration in progress. */
88 if (currCal->calState == CAL_RUNNING) {
89 /* Check to see if it has finished. */
90 if (REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)
94 * Accumulate cal measures for active chains
96 if (cur_caldata->calCollect)
97 cur_caldata->calCollect(ah);
100 if (ah->cal_samples >= cur_caldata->calNumSamples) {
101 unsigned int i, numChains = 0;
102 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
103 if (rxchainmask & (1 << i))
108 * Process accumulated data
110 if (cur_caldata->calPostProc)
111 cur_caldata->calPostProc(ah, numChains);
113 /* Calibration has finished. */
114 caldata->CalValid |= cur_caldata->calType;
115 currCal->calState = CAL_DONE;
119 * Set-up collection of another sub-sample until we
122 ar9003_hw_setup_calibration(ah, currCal);
124 } else if (!(caldata->CalValid & cur_caldata->calType)) {
125 /* If current cal is marked invalid in channel, kick it off */
126 ath9k_hw_reset_calibration(ah, currCal);
132 static int ar9003_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
133 u8 rxchainmask, bool longcal)
135 bool iscaldone = true;
136 struct ath9k_cal_list *currCal = ah->cal_list_curr;
140 * For given calibration:
141 * 1. Call generic cal routine
142 * 2. When this cal is done (isCalDone) if we have more cals waiting
143 * (eg after reset), mask this to upper layers by not propagating
144 * isCalDone if it is set to TRUE.
145 * Instead, change isCalDone to FALSE and setup the waiting cal(s)
149 (currCal->calState == CAL_RUNNING ||
150 currCal->calState == CAL_WAITING)) {
151 iscaldone = ar9003_hw_per_calibration(ah, chan,
152 rxchainmask, currCal);
154 ah->cal_list_curr = currCal = currCal->calNext;
156 if (currCal->calState == CAL_WAITING) {
158 ath9k_hw_reset_calibration(ah, currCal);
164 * Do NF cal only at longer intervals. Get the value from
165 * the previous NF cal and update history buffer.
167 if (longcal && ath9k_hw_getnf(ah, chan)) {
169 * Load the NF from history buffer of the current channel.
170 * NF is slow time-variant, so it is OK to use a historical
173 ret = ath9k_hw_loadnf(ah, ah->curchan);
177 /* start NF calibration, without updating BB NF register */
178 ath9k_hw_start_nfcal(ah, false);
184 static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
188 /* Accumulate IQ cal measures for active chains */
189 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
190 if (ah->txchainmask & BIT(i)) {
191 ah->totalPowerMeasI[i] +=
192 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
193 ah->totalPowerMeasQ[i] +=
194 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
195 ah->totalIqCorrMeas[i] +=
196 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
197 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
198 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
199 ah->cal_samples, i, ah->totalPowerMeasI[i],
200 ah->totalPowerMeasQ[i],
201 ah->totalIqCorrMeas[i]);
206 static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
208 struct ath_common *common = ath9k_hw_common(ah);
209 u32 powerMeasQ, powerMeasI, iqCorrMeas;
210 u32 qCoffDenom, iCoffDenom;
211 int32_t qCoff, iCoff;
213 static const u_int32_t offset_array[3] = {
214 AR_PHY_RX_IQCAL_CORR_B0,
215 AR_PHY_RX_IQCAL_CORR_B1,
216 AR_PHY_RX_IQCAL_CORR_B2,
219 for (i = 0; i < numChains; i++) {
220 powerMeasI = ah->totalPowerMeasI[i];
221 powerMeasQ = ah->totalPowerMeasQ[i];
222 iqCorrMeas = ah->totalIqCorrMeas[i];
224 ath_dbg(common, CALIBRATE,
225 "Starting IQ Cal and Correction for Chain %d\n", i);
227 ath_dbg(common, CALIBRATE,
228 "Original: Chn %d iq_corr_meas = 0x%08x\n",
229 i, ah->totalIqCorrMeas[i]);
233 if (iqCorrMeas > 0x80000000) {
234 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
238 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_i = 0x%08x\n",
240 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_q = 0x%08x\n",
242 ath_dbg(common, CALIBRATE, "iqCorrNeg is 0x%08x\n", iqCorrNeg);
244 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
245 qCoffDenom = powerMeasQ / 64;
247 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
248 iCoff = iqCorrMeas / iCoffDenom;
249 qCoff = powerMeasI / qCoffDenom - 64;
250 ath_dbg(common, CALIBRATE, "Chn %d iCoff = 0x%08x\n",
252 ath_dbg(common, CALIBRATE, "Chn %d qCoff = 0x%08x\n",
255 /* Force bounds on iCoff */
258 else if (iCoff <= -63)
261 /* Negate iCoff if iqCorrNeg == 0 */
262 if (iqCorrNeg == 0x0)
265 /* Force bounds on qCoff */
268 else if (qCoff <= -63)
271 iCoff = iCoff & 0x7f;
272 qCoff = qCoff & 0x7f;
274 ath_dbg(common, CALIBRATE,
275 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
277 ath_dbg(common, CALIBRATE,
278 "Register offset (0x%04x) before update = 0x%x\n",
280 REG_READ(ah, offset_array[i]));
282 if (AR_SREV_9565(ah) &&
283 (iCoff == 63 || qCoff == 63 ||
284 iCoff == -63 || qCoff == -63))
287 REG_RMW_FIELD(ah, offset_array[i],
288 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
290 REG_RMW_FIELD(ah, offset_array[i],
291 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
293 ath_dbg(common, CALIBRATE,
294 "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
296 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
297 REG_READ(ah, offset_array[i]));
298 ath_dbg(common, CALIBRATE,
299 "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
301 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
302 REG_READ(ah, offset_array[i]));
304 ath_dbg(common, CALIBRATE,
305 "IQ Cal and Correction done for Chain %d\n", i);
309 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
310 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
311 ath_dbg(common, CALIBRATE,
312 "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
313 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
314 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
315 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
318 static const struct ath9k_percal_data iq_cal_single_sample = {
322 ar9003_hw_iqcal_collect,
323 ar9003_hw_iqcalibrate
326 static const struct ath9k_percal_data temp_cal_single_sample = {
332 static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
334 ah->iq_caldata.calData = &iq_cal_single_sample;
335 ah->temp_caldata.calData = &temp_cal_single_sample;
337 if (AR_SREV_9300_20_OR_LATER(ah)) {
338 ah->enabled_cals |= TX_IQ_CAL;
339 if (AR_SREV_9485_OR_LATER(ah) && !AR_SREV_9340(ah))
340 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
343 ah->supp_cals = IQ_MISMATCH_CAL | TEMP_COMP_CAL;
346 #define OFF_UPPER_LT 24
347 #define OFF_LOWER_LT 7
349 static bool ar9003_hw_dynamic_osdac_selection(struct ath_hw *ah,
352 struct ath_common *common = ath9k_hw_common(ah);
353 int ch0_done, osdac_ch0, dc_off_ch0_i1, dc_off_ch0_q1, dc_off_ch0_i2,
354 dc_off_ch0_q2, dc_off_ch0_i3, dc_off_ch0_q3;
355 int ch1_done, osdac_ch1, dc_off_ch1_i1, dc_off_ch1_q1, dc_off_ch1_i2,
356 dc_off_ch1_q2, dc_off_ch1_i3, dc_off_ch1_q3;
357 int ch2_done, osdac_ch2, dc_off_ch2_i1, dc_off_ch2_q1, dc_off_ch2_i2,
358 dc_off_ch2_q2, dc_off_ch2_i3, dc_off_ch2_q3;
363 * Clear offset and IQ calibration, run AGC cal.
365 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
366 AR_PHY_AGC_CONTROL_OFFSET_CAL);
367 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
368 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
369 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
370 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
372 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
373 AR_PHY_AGC_CONTROL_CAL,
376 ath_dbg(common, CALIBRATE,
377 "AGC cal without offset cal failed to complete in 1ms");
382 * Allow only offset calibration and disable the others
383 * (Carrier Leak calibration, TX Filter calibration and
384 * Peak Detector offset calibration).
386 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
387 AR_PHY_AGC_CONTROL_OFFSET_CAL);
388 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
389 AR_PHY_CL_CAL_ENABLE);
390 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
391 AR_PHY_AGC_CONTROL_FLTR_CAL);
392 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
393 AR_PHY_AGC_CONTROL_PKDET_CAL);
399 while ((ch0_done == 0) || (ch1_done == 0) || (ch2_done == 0)) {
400 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3;
401 osdac_ch1 = (REG_READ(ah, AR_PHY_65NM_CH1_BB1) >> 30) & 0x3;
402 osdac_ch2 = (REG_READ(ah, AR_PHY_65NM_CH2_BB1) >> 30) & 0x3;
404 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
406 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
407 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
409 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
410 AR_PHY_AGC_CONTROL_CAL,
413 ath_dbg(common, CALIBRATE,
414 "DC offset cal failed to complete in 1ms");
418 REG_CLR_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
423 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
424 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (1 << 8)));
425 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
426 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (1 << 8)));
427 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
428 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (1 << 8)));
430 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
431 dc_off_ch0_i1 = (temp >> 26) & 0x1f;
432 dc_off_ch0_q1 = (temp >> 21) & 0x1f;
434 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
435 dc_off_ch1_i1 = (temp >> 26) & 0x1f;
436 dc_off_ch1_q1 = (temp >> 21) & 0x1f;
438 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
439 dc_off_ch2_i1 = (temp >> 26) & 0x1f;
440 dc_off_ch2_q1 = (temp >> 21) & 0x1f;
445 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
446 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (2 << 8)));
447 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
448 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (2 << 8)));
449 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
450 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (2 << 8)));
452 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
453 dc_off_ch0_i2 = (temp >> 26) & 0x1f;
454 dc_off_ch0_q2 = (temp >> 21) & 0x1f;
456 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
457 dc_off_ch1_i2 = (temp >> 26) & 0x1f;
458 dc_off_ch1_q2 = (temp >> 21) & 0x1f;
460 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
461 dc_off_ch2_i2 = (temp >> 26) & 0x1f;
462 dc_off_ch2_q2 = (temp >> 21) & 0x1f;
467 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
468 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (3 << 8)));
469 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
470 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (3 << 8)));
471 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
472 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (3 << 8)));
474 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
475 dc_off_ch0_i3 = (temp >> 26) & 0x1f;
476 dc_off_ch0_q3 = (temp >> 21) & 0x1f;
478 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
479 dc_off_ch1_i3 = (temp >> 26) & 0x1f;
480 dc_off_ch1_q3 = (temp >> 21) & 0x1f;
482 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
483 dc_off_ch2_i3 = (temp >> 26) & 0x1f;
484 dc_off_ch2_q3 = (temp >> 21) & 0x1f;
486 if ((dc_off_ch0_i1 > OFF_UPPER_LT) || (dc_off_ch0_i1 < OFF_LOWER_LT) ||
487 (dc_off_ch0_i2 > OFF_UPPER_LT) || (dc_off_ch0_i2 < OFF_LOWER_LT) ||
488 (dc_off_ch0_i3 > OFF_UPPER_LT) || (dc_off_ch0_i3 < OFF_LOWER_LT) ||
489 (dc_off_ch0_q1 > OFF_UPPER_LT) || (dc_off_ch0_q1 < OFF_LOWER_LT) ||
490 (dc_off_ch0_q2 > OFF_UPPER_LT) || (dc_off_ch0_q2 < OFF_LOWER_LT) ||
491 (dc_off_ch0_q3 > OFF_UPPER_LT) || (dc_off_ch0_q3 < OFF_LOWER_LT)) {
492 if (osdac_ch0 == 3) {
497 val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff;
498 val |= (osdac_ch0 << 30);
499 REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, val);
507 if ((dc_off_ch1_i1 > OFF_UPPER_LT) || (dc_off_ch1_i1 < OFF_LOWER_LT) ||
508 (dc_off_ch1_i2 > OFF_UPPER_LT) || (dc_off_ch1_i2 < OFF_LOWER_LT) ||
509 (dc_off_ch1_i3 > OFF_UPPER_LT) || (dc_off_ch1_i3 < OFF_LOWER_LT) ||
510 (dc_off_ch1_q1 > OFF_UPPER_LT) || (dc_off_ch1_q1 < OFF_LOWER_LT) ||
511 (dc_off_ch1_q2 > OFF_UPPER_LT) || (dc_off_ch1_q2 < OFF_LOWER_LT) ||
512 (dc_off_ch1_q3 > OFF_UPPER_LT) || (dc_off_ch1_q3 < OFF_LOWER_LT)) {
513 if (osdac_ch1 == 3) {
518 val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff;
519 val |= (osdac_ch1 << 30);
520 REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, val);
528 if ((dc_off_ch2_i1 > OFF_UPPER_LT) || (dc_off_ch2_i1 < OFF_LOWER_LT) ||
529 (dc_off_ch2_i2 > OFF_UPPER_LT) || (dc_off_ch2_i2 < OFF_LOWER_LT) ||
530 (dc_off_ch2_i3 > OFF_UPPER_LT) || (dc_off_ch2_i3 < OFF_LOWER_LT) ||
531 (dc_off_ch2_q1 > OFF_UPPER_LT) || (dc_off_ch2_q1 < OFF_LOWER_LT) ||
532 (dc_off_ch2_q2 > OFF_UPPER_LT) || (dc_off_ch2_q2 < OFF_LOWER_LT) ||
533 (dc_off_ch2_q3 > OFF_UPPER_LT) || (dc_off_ch2_q3 < OFF_LOWER_LT)) {
534 if (osdac_ch2 == 3) {
539 val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff;
540 val |= (osdac_ch2 << 30);
541 REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, val);
550 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
551 AR_PHY_AGC_CONTROL_OFFSET_CAL);
552 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
555 * We don't need to check txiqcal_done here since it is always
558 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
559 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
565 * solve 4x4 linear equation used in loopback iq cal.
567 static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
578 s32 f1 = cos_2phi_1 - cos_2phi_2,
579 f3 = sin_2phi_1 - sin_2phi_2,
581 s32 mag_tx, phs_tx, mag_rx, phs_rx;
582 const s32 result_shift = 1 << 15;
583 struct ath_common *common = ath9k_hw_common(ah);
585 f2 = ((f1 >> 3) * (f1 >> 3) + (f3 >> 3) * (f3 >> 3)) >> 9;
588 ath_dbg(common, CALIBRATE, "Divide by 0\n");
592 /* mag mismatch, tx */
593 mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
594 /* phs mismatch, tx */
595 phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
597 mag_tx = (mag_tx / f2);
598 phs_tx = (phs_tx / f2);
600 /* mag mismatch, rx */
601 mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
603 /* phs mismatch, rx */
604 phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
607 solved_eq[0] = mag_tx;
608 solved_eq[1] = phs_tx;
609 solved_eq[2] = mag_rx;
610 solved_eq[3] = phs_rx;
615 static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
617 s32 abs_i = abs(in_re),
629 return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4);
634 static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
639 s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
640 i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
641 i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
642 i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
643 s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
644 phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
645 sin_2phi_1, cos_2phi_1,
646 sin_2phi_2, cos_2phi_2;
647 s32 mag_tx, phs_tx, mag_rx, phs_rx;
648 s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
650 const s32 res_scale = 1 << 15;
651 const s32 delpt_shift = 1 << 8;
653 struct ath_common *common = ath9k_hw_common(ah);
655 i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
656 i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
657 iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
659 if (i2_m_q2_a0_d0 > 0x800)
660 i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
662 if (i2_p_q2_a0_d0 > 0x800)
663 i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
665 if (iq_corr_a0_d0 > 0x800)
666 iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
668 i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
669 i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
670 iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
672 if (i2_m_q2_a0_d1 > 0x800)
673 i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
675 if (iq_corr_a0_d1 > 0x800)
676 iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
678 i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
679 i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
680 iq_corr_a1_d0 = iq_res[4] & 0xfff;
682 if (i2_m_q2_a1_d0 > 0x800)
683 i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
685 if (i2_p_q2_a1_d0 > 0x800)
686 i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
688 if (iq_corr_a1_d0 > 0x800)
689 iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
691 i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
692 i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
693 iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
695 if (i2_m_q2_a1_d1 > 0x800)
696 i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
698 if (i2_p_q2_a1_d1 > 0x800)
699 i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
701 if (iq_corr_a1_d1 > 0x800)
702 iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
704 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
705 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
706 ath_dbg(common, CALIBRATE,
712 i2_p_q2_a0_d0, i2_p_q2_a0_d1,
713 i2_p_q2_a1_d0, i2_p_q2_a1_d1);
717 if ((i2_p_q2_a0_d0 < 1024) || (i2_p_q2_a0_d0 > 2047) ||
718 (i2_p_q2_a1_d0 < 0) || (i2_p_q2_a1_d1 < 0) ||
719 (i2_p_q2_a0_d0 <= i2_m_q2_a0_d0) ||
720 (i2_p_q2_a0_d0 <= iq_corr_a0_d0) ||
721 (i2_p_q2_a0_d1 <= i2_m_q2_a0_d1) ||
722 (i2_p_q2_a0_d1 <= iq_corr_a0_d1) ||
723 (i2_p_q2_a1_d0 <= i2_m_q2_a1_d0) ||
724 (i2_p_q2_a1_d0 <= iq_corr_a1_d0) ||
725 (i2_p_q2_a1_d1 <= i2_m_q2_a1_d1) ||
726 (i2_p_q2_a1_d1 <= iq_corr_a1_d1)) {
730 mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
731 phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
733 mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
734 phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
736 mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
737 phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
739 mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
740 phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
742 /* w/o analog phase shift */
743 sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
744 /* w/o analog phase shift */
745 cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
746 /* w/ analog phase shift */
747 sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
748 /* w/ analog phase shift */
749 cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
752 * force sin^2 + cos^2 = 1;
753 * find magnitude by approximation
755 mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
756 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
758 if ((mag1 == 0) || (mag2 == 0)) {
759 ath_dbg(common, CALIBRATE, "Divide by 0: mag1=%d, mag2=%d\n",
764 /* normalization sin and cos by mag */
765 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
766 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
767 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
768 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
770 /* calculate IQ mismatch */
771 if (!ar9003_hw_solve_iq_cal(ah,
772 sin_2phi_1, cos_2phi_1,
773 sin_2phi_2, cos_2phi_2,
774 mag_a0_d0, phs_a0_d0,
776 phs_a1_d0, solved_eq)) {
777 ath_dbg(common, CALIBRATE,
778 "Call to ar9003_hw_solve_iq_cal() failed\n");
782 mag_tx = solved_eq[0];
783 phs_tx = solved_eq[1];
784 mag_rx = solved_eq[2];
785 phs_rx = solved_eq[3];
787 ath_dbg(common, CALIBRATE,
788 "chain %d: mag mismatch=%d phase mismatch=%d\n",
789 chain_idx, mag_tx/res_scale, phs_tx/res_scale);
791 if (res_scale == mag_tx) {
792 ath_dbg(common, CALIBRATE,
793 "Divide by 0: mag_tx=%d, res_scale=%d\n",
798 /* calculate and quantize Tx IQ correction factor */
799 mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
800 phs_corr_tx = -phs_tx;
802 q_q_coff = (mag_corr_tx * 128 / res_scale);
803 q_i_coff = (phs_corr_tx * 256 / res_scale);
805 ath_dbg(common, CALIBRATE, "tx chain %d: mag corr=%d phase corr=%d\n",
806 chain_idx, q_q_coff, q_i_coff);
817 iqc_coeff[0] = (q_q_coff * 128) + (0x7f & q_i_coff);
819 ath_dbg(common, CALIBRATE, "tx chain %d: iq corr coeff=%x\n",
820 chain_idx, iqc_coeff[0]);
822 if (-mag_rx == res_scale) {
823 ath_dbg(common, CALIBRATE,
824 "Divide by 0: mag_rx=%d, res_scale=%d\n",
829 /* calculate and quantize Rx IQ correction factors */
830 mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
831 phs_corr_rx = -phs_rx;
833 q_q_coff = (mag_corr_rx * 128 / res_scale);
834 q_i_coff = (phs_corr_rx * 256 / res_scale);
836 ath_dbg(common, CALIBRATE, "rx chain %d: mag corr=%d phase corr=%d\n",
837 chain_idx, q_q_coff, q_i_coff);
848 iqc_coeff[1] = (q_q_coff * 128) + (0x7f & q_i_coff);
850 ath_dbg(common, CALIBRATE, "rx chain %d: iq corr coeff=%x\n",
851 chain_idx, iqc_coeff[1]);
856 static void ar9003_hw_detect_outlier(int mp_coeff[][MAXIQCAL],
860 int mp_max = -64, max_idx = 0;
861 int mp_min = 63, min_idx = 0;
862 int mp_avg = 0, i, outlier_idx = 0, mp_count = 0;
864 /* find min/max mismatch across all calibrated gains */
865 for (i = 0; i < nmeasurement; i++) {
866 if (mp_coeff[i][0] > mp_max) {
867 mp_max = mp_coeff[i][0];
869 } else if (mp_coeff[i][0] < mp_min) {
870 mp_min = mp_coeff[i][0];
875 /* find average (exclude max abs value) */
876 for (i = 0; i < nmeasurement; i++) {
877 if ((abs(mp_coeff[i][0]) < abs(mp_max)) ||
878 (abs(mp_coeff[i][0]) < abs(mp_min))) {
879 mp_avg += mp_coeff[i][0];
885 * finding mean magnitude/phase if possible, otherwise
886 * just use the last value as the mean
891 mp_avg = mp_coeff[nmeasurement - 1][0];
894 if (abs(mp_max - mp_min) > max_delta) {
895 if (abs(mp_max - mp_avg) > abs(mp_min - mp_avg))
896 outlier_idx = max_idx;
898 outlier_idx = min_idx;
900 mp_coeff[outlier_idx][0] = mp_avg;
904 static void ar9003_hw_tx_iq_cal_outlier_detection(struct ath_hw *ah,
908 int i, im, nmeasurement;
909 int magnitude, phase;
910 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
911 struct ath9k_hw_cal_data *caldata = ah->caldata;
913 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
914 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
915 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
916 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
917 if (!AR_SREV_9485(ah)) {
918 tx_corr_coeff[i * 2][1] =
919 tx_corr_coeff[(i * 2) + 1][1] =
920 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
922 tx_corr_coeff[i * 2][2] =
923 tx_corr_coeff[(i * 2) + 1][2] =
924 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
928 /* Load the average of 2 passes */
929 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
930 if (!(ah->txchainmask & (1 << i)))
932 nmeasurement = REG_READ_FIELD(ah,
933 AR_PHY_TX_IQCAL_STATUS_B0,
934 AR_PHY_CALIBRATED_GAINS_0);
936 if (nmeasurement > MAX_MEASUREMENT)
937 nmeasurement = MAX_MEASUREMENT;
940 * Skip normal outlier detection for AR9550.
942 if (!AR_SREV_9550(ah)) {
943 /* detect outlier only if nmeasurement > 1 */
944 if (nmeasurement > 1) {
945 /* Detect magnitude outlier */
946 ar9003_hw_detect_outlier(coeff->mag_coeff[i],
950 /* Detect phase outlier */
951 ar9003_hw_detect_outlier(coeff->phs_coeff[i],
957 for (im = 0; im < nmeasurement; im++) {
958 magnitude = coeff->mag_coeff[i][im][0];
959 phase = coeff->phs_coeff[i][im][0];
961 coeff->iqc_coeff[0] =
962 (phase & 0x7f) | ((magnitude & 0x7f) << 7);
965 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
966 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
967 coeff->iqc_coeff[0]);
969 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
970 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
971 coeff->iqc_coeff[0]);
974 caldata->tx_corr_coeff[im][i] =
978 caldata->num_measures[i] = nmeasurement;
981 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
982 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
983 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
984 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
988 set_bit(TXIQCAL_DONE, &caldata->cal_flags);
990 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
996 static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
998 struct ath_common *common = ath9k_hw_common(ah);
1001 tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
1002 AR_PHY_TXGAIN_FORCE);
1004 REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
1005 AR_PHY_TXGAIN_FORCE, 0);
1007 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
1008 AR_PHY_TX_IQCAL_START_DO_CAL, 1);
1010 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
1011 AR_PHY_TX_IQCAL_START_DO_CAL, 0,
1013 ath_dbg(common, CALIBRATE, "Tx IQ Cal is not completed\n");
1019 static void __ar955x_tx_iq_cal_sort(struct ath_hw *ah,
1020 struct coeff *coeff,
1021 int i, int nmeasurement)
1023 struct ath_common *common = ath9k_hw_common(ah);
1024 int im, ix, iy, temp;
1026 for (im = 0; im < nmeasurement; im++) {
1027 for (ix = 0; ix < MAXIQCAL - 1; ix++) {
1028 for (iy = ix + 1; iy <= MAXIQCAL - 1; iy++) {
1029 if (coeff->mag_coeff[i][im][iy] <
1030 coeff->mag_coeff[i][im][ix]) {
1031 temp = coeff->mag_coeff[i][im][ix];
1032 coeff->mag_coeff[i][im][ix] =
1033 coeff->mag_coeff[i][im][iy];
1034 coeff->mag_coeff[i][im][iy] = temp;
1036 if (coeff->phs_coeff[i][im][iy] <
1037 coeff->phs_coeff[i][im][ix]) {
1038 temp = coeff->phs_coeff[i][im][ix];
1039 coeff->phs_coeff[i][im][ix] =
1040 coeff->phs_coeff[i][im][iy];
1041 coeff->phs_coeff[i][im][iy] = temp;
1045 coeff->mag_coeff[i][im][0] = coeff->mag_coeff[i][im][MAXIQCAL / 2];
1046 coeff->phs_coeff[i][im][0] = coeff->phs_coeff[i][im][MAXIQCAL / 2];
1048 ath_dbg(common, CALIBRATE,
1049 "IQCAL: Median [ch%d][gain%d]: mag = %d phase = %d\n",
1051 coeff->mag_coeff[i][im][0],
1052 coeff->phs_coeff[i][im][0]);
1056 static bool ar955x_tx_iq_cal_median(struct ath_hw *ah,
1057 struct coeff *coeff,
1063 if ((iqcal_idx + 1) != MAXIQCAL)
1066 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1067 __ar955x_tx_iq_cal_sort(ah, coeff, i, nmeasurement);
1073 static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah,
1077 struct ath_common *common = ath9k_hw_common(ah);
1078 const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
1079 AR_PHY_TX_IQCAL_STATUS_B0,
1080 AR_PHY_TX_IQCAL_STATUS_B1,
1081 AR_PHY_TX_IQCAL_STATUS_B2,
1083 const u_int32_t chan_info_tab[] = {
1084 AR_PHY_CHAN_INFO_TAB_0,
1085 AR_PHY_CHAN_INFO_TAB_1,
1086 AR_PHY_CHAN_INFO_TAB_2,
1088 static struct coeff coeff;
1091 int nmeasurement = 0;
1092 bool outlier_detect = true;
1094 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1095 if (!(ah->txchainmask & (1 << i)))
1098 nmeasurement = REG_READ_FIELD(ah,
1099 AR_PHY_TX_IQCAL_STATUS_B0,
1100 AR_PHY_CALIBRATED_GAINS_0);
1101 if (nmeasurement > MAX_MEASUREMENT)
1102 nmeasurement = MAX_MEASUREMENT;
1104 for (im = 0; im < nmeasurement; im++) {
1105 ath_dbg(common, CALIBRATE,
1106 "Doing Tx IQ Cal for chain %d\n", i);
1108 if (REG_READ(ah, txiqcal_status[i]) &
1109 AR_PHY_TX_IQCAL_STATUS_FAILED) {
1110 ath_dbg(common, CALIBRATE,
1111 "Tx IQ Cal failed for chain %d\n", i);
1115 for (j = 0; j < 3; j++) {
1116 u32 idx = 2 * j, offset = 4 * (3 * im + j);
1119 AR_PHY_CHAN_INFO_MEMORY,
1120 AR_PHY_CHAN_INFO_TAB_S2_READ,
1124 iq_res[idx] = REG_READ(ah,
1129 AR_PHY_CHAN_INFO_MEMORY,
1130 AR_PHY_CHAN_INFO_TAB_S2_READ,
1134 iq_res[idx + 1] = 0xffff & REG_READ(ah,
1135 chan_info_tab[i] + offset);
1137 ath_dbg(common, CALIBRATE,
1138 "IQ_RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
1139 idx, iq_res[idx], idx + 1,
1143 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
1145 ath_dbg(common, CALIBRATE,
1146 "Failed in calculation of IQ correction\n");
1150 coeff.phs_coeff[i][im][iqcal_idx] =
1151 coeff.iqc_coeff[0] & 0x7f;
1152 coeff.mag_coeff[i][im][iqcal_idx] =
1153 (coeff.iqc_coeff[0] >> 7) & 0x7f;
1155 if (coeff.mag_coeff[i][im][iqcal_idx] > 63)
1156 coeff.mag_coeff[i][im][iqcal_idx] -= 128;
1157 if (coeff.phs_coeff[i][im][iqcal_idx] > 63)
1158 coeff.phs_coeff[i][im][iqcal_idx] -= 128;
1162 if (AR_SREV_9550(ah))
1163 outlier_detect = ar955x_tx_iq_cal_median(ah, &coeff,
1164 iqcal_idx, nmeasurement);
1166 ar9003_hw_tx_iq_cal_outlier_detection(ah, &coeff, is_reusable);
1171 ath_dbg(common, CALIBRATE, "Tx IQ Cal failed\n");
1175 static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah)
1177 struct ath9k_hw_cal_data *caldata = ah->caldata;
1178 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
1181 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
1182 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
1183 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
1184 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
1185 if (!AR_SREV_9485(ah)) {
1186 tx_corr_coeff[i * 2][1] =
1187 tx_corr_coeff[(i * 2) + 1][1] =
1188 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
1190 tx_corr_coeff[i * 2][2] =
1191 tx_corr_coeff[(i * 2) + 1][2] =
1192 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
1196 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1197 if (!(ah->txchainmask & (1 << i)))
1200 for (im = 0; im < caldata->num_measures[i]; im++) {
1202 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
1203 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
1204 caldata->tx_corr_coeff[im][i]);
1206 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
1207 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
1208 caldata->tx_corr_coeff[im][i]);
1212 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
1213 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
1214 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
1215 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
1218 static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
1220 int offset[8] = {0}, total = 0, test;
1221 int agc_out, i, peak_detect_threshold = 0;
1223 if (AR_SREV_9550(ah) || AR_SREV_9531(ah))
1224 peak_detect_threshold = 8;
1225 else if (AR_SREV_9561(ah))
1226 peak_detect_threshold = 11;
1231 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1232 AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE, 0x1);
1233 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1234 AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC, 0x0);
1236 if (AR_SREV_9003_PCOEM(ah) || AR_SREV_9330_11(ah)) {
1238 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1239 AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR, 0x0);
1241 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1242 AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR, 0x0);
1248 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1249 AR_PHY_65NM_RXTX2_RXON_OVR, 0x1);
1250 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1251 AR_PHY_65NM_RXTX2_RXON, 0x0);
1254 * Turn on AGC for cal.
1256 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1257 AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE, 0x1);
1258 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1259 AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1);
1260 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1261 AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1);
1263 if (AR_SREV_9330_11(ah))
1264 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1265 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0);
1268 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1269 AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR,
1270 peak_detect_threshold);
1272 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1273 AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR,
1274 peak_detect_threshold);
1276 for (i = 6; i > 0; i--) {
1277 offset[i] = BIT(i - 1);
1278 test = total + offset[i];
1281 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1282 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR,
1285 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1286 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR,
1289 agc_out = REG_READ_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1290 AR_PHY_65NM_RXRF_AGC_AGC_OUT);
1291 offset[i] = (agc_out) ? 0 : 1;
1292 total += (offset[i] << (i - 1));
1296 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1297 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, total);
1299 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1300 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR, total);
1305 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1306 AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE, 0);
1310 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1311 AR_PHY_65NM_RXTX2_RXON_OVR, 0);
1313 * Turn off peak detect calibration.
1315 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1316 AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0);
1319 static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah,
1320 struct ath9k_channel *chan,
1323 struct ath9k_hw_cal_data *caldata = ah->caldata;
1326 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && !run_rtt_cal)
1329 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1330 if (!(ah->rxchainmask & (1 << i)))
1332 ar9003_hw_manual_peak_cal(ah, i, IS_CHAN_2GHZ(chan));
1336 set_bit(SW_PKDET_DONE, &caldata->cal_flags);
1338 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && caldata) {
1339 if (IS_CHAN_2GHZ(chan)){
1340 caldata->caldac[0] = REG_READ_FIELD(ah,
1341 AR_PHY_65NM_RXRF_AGC(0),
1342 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR);
1343 caldata->caldac[1] = REG_READ_FIELD(ah,
1344 AR_PHY_65NM_RXRF_AGC(1),
1345 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR);
1347 caldata->caldac[0] = REG_READ_FIELD(ah,
1348 AR_PHY_65NM_RXRF_AGC(0),
1349 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR);
1350 caldata->caldac[1] = REG_READ_FIELD(ah,
1351 AR_PHY_65NM_RXRF_AGC(1),
1352 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR);
1357 static void ar9003_hw_cl_cal_post_proc(struct ath_hw *ah, bool is_reusable)
1359 u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
1362 struct ath9k_hw_cal_data *caldata = ah->caldata;
1363 bool txclcal_done = false;
1366 if (!caldata || !(ah->enabled_cals & TX_CL_CAL))
1369 txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
1370 AR_PHY_AGC_CONTROL_CLC_SUCCESS);
1372 if (test_bit(TXCLCAL_DONE, &caldata->cal_flags)) {
1373 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1374 if (!(ah->txchainmask & (1 << i)))
1376 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1377 REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]),
1378 caldata->tx_clcal[i][j]);
1380 } else if (is_reusable && txclcal_done) {
1381 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1382 if (!(ah->txchainmask & (1 << i)))
1384 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1385 caldata->tx_clcal[i][j] =
1386 REG_READ(ah, CL_TAB_ENTRY(cl_idx[i]));
1388 set_bit(TXCLCAL_DONE, &caldata->cal_flags);
1392 static void ar9003_hw_init_cal_common(struct ath_hw *ah)
1394 struct ath9k_hw_cal_data *caldata = ah->caldata;
1396 /* Initialize list pointers */
1397 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1399 INIT_CAL(&ah->iq_caldata);
1400 INSERT_CAL(ah, &ah->iq_caldata);
1402 INIT_CAL(&ah->temp_caldata);
1403 INSERT_CAL(ah, &ah->temp_caldata);
1405 /* Initialize current pointer to first element in list */
1406 ah->cal_list_curr = ah->cal_list;
1408 if (ah->cal_list_curr)
1409 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1412 caldata->CalValid = 0;
1415 static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
1416 struct ath9k_channel *chan)
1418 struct ath_common *common = ath9k_hw_common(ah);
1419 struct ath9k_hw_cal_data *caldata = ah->caldata;
1420 bool txiqcal_done = false;
1421 bool is_reusable = true, status = true;
1422 bool run_rtt_cal = false, run_agc_cal;
1423 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
1425 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
1426 AR_PHY_AGC_CONTROL_FLTR_CAL |
1427 AR_PHY_AGC_CONTROL_PKDET_CAL;
1429 /* Use chip chainmask only for calibration */
1430 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
1433 if (!ar9003_hw_rtt_restore(ah, chan))
1437 ath_dbg(common, CALIBRATE, "RTT calibration to be done\n");
1440 run_agc_cal = run_rtt_cal;
1443 ar9003_hw_rtt_enable(ah);
1444 ar9003_hw_rtt_set_mask(ah, 0x00);
1445 ar9003_hw_rtt_clear_hist(ah);
1450 agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
1451 agc_supp_cals &= agc_ctrl;
1452 agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
1453 AR_PHY_AGC_CONTROL_FLTR_CAL |
1454 AR_PHY_AGC_CONTROL_PKDET_CAL);
1455 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1457 if (ah->ah_flags & AH_FASTCC)
1462 if (ah->enabled_cals & TX_CL_CAL) {
1463 if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags))
1464 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
1465 AR_PHY_CL_CAL_ENABLE);
1467 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
1468 AR_PHY_CL_CAL_ENABLE);
1473 if ((IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) ||
1474 !(ah->enabled_cals & TX_IQ_CAL))
1477 /* Do Tx IQ Calibration */
1478 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
1479 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
1483 * For AR9485 or later chips, TxIQ cal runs as part of
1486 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
1487 if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags))
1488 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1489 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
1491 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1492 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
1493 txiqcal_done = run_agc_cal = true;
1497 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1498 ar9003_mci_init_cal_req(ah, &is_reusable);
1500 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
1501 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
1502 /* Disable BB_active */
1503 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1505 REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY);
1506 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1509 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1510 /* Calibrate the AGC */
1511 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1512 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1513 AR_PHY_AGC_CONTROL_CAL);
1515 /* Poll for offset calibration complete */
1516 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1517 AR_PHY_AGC_CONTROL_CAL,
1518 0, AH_WAIT_TIMEOUT);
1520 ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal);
1523 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
1524 REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay);
1528 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1529 ar9003_mci_init_cal_done(ah);
1531 if (rtt && !run_rtt_cal) {
1532 agc_ctrl |= agc_supp_cals;
1533 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1538 ar9003_hw_rtt_disable(ah);
1540 ath_dbg(common, CALIBRATE,
1541 "offset calibration failed to complete in %d ms; noisy environment?\n",
1542 AH_WAIT_TIMEOUT / 1000);
1547 ar9003_hw_tx_iq_cal_post_proc(ah, 0, is_reusable);
1548 else if (caldata && test_bit(TXIQCAL_DONE, &caldata->cal_flags))
1549 ar9003_hw_tx_iq_cal_reload(ah);
1551 ar9003_hw_cl_cal_post_proc(ah, is_reusable);
1553 if (run_rtt_cal && caldata) {
1555 if (!ath9k_hw_rfbus_req(ah)) {
1556 ath_err(ath9k_hw_common(ah),
1557 "Could not stop baseband\n");
1559 ar9003_hw_rtt_fill_hist(ah);
1561 if (test_bit(SW_PKDET_DONE, &caldata->cal_flags))
1562 ar9003_hw_rtt_load_hist(ah);
1565 ath9k_hw_rfbus_done(ah);
1568 ar9003_hw_rtt_disable(ah);
1571 /* Revert chainmask to runtime parameters */
1572 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1574 ar9003_hw_init_cal_common(ah);
1579 static bool do_ar9003_agc_cal(struct ath_hw *ah)
1581 struct ath_common *common = ath9k_hw_common(ah);
1584 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1585 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1586 AR_PHY_AGC_CONTROL_CAL);
1588 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1589 AR_PHY_AGC_CONTROL_CAL,
1590 0, AH_WAIT_TIMEOUT);
1592 ath_dbg(common, CALIBRATE,
1593 "offset calibration failed to complete in %d ms,"
1594 "noisy environment?\n",
1595 AH_WAIT_TIMEOUT / 1000);
1602 static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
1603 struct ath9k_channel *chan)
1605 bool txiqcal_done = false;
1607 bool run_agc_cal = false, sep_iq_cal = false;
1610 /* Use chip chainmask only for calibration */
1611 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
1613 if (ah->enabled_cals & TX_CL_CAL) {
1614 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1618 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
1621 /* Do Tx IQ Calibration */
1622 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
1623 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
1627 * For AR9485 or later chips, TxIQ cal runs as part of
1628 * AGC calibration. Specifically, AR9550 in SoC chips.
1630 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
1631 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1632 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) {
1633 txiqcal_done = true;
1635 txiqcal_done = false;
1644 * In the SoC family, this will run for AR9300, AR9331 and AR9340.
1647 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
1648 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1650 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1653 if (AR_SREV_9550(ah) && IS_CHAN_2GHZ(chan)) {
1654 if (!ar9003_hw_dynamic_osdac_selection(ah, txiqcal_done))
1659 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1660 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1661 if (!(ah->rxchainmask & (1 << i)))
1664 ar9003_hw_manual_peak_cal(ah, i,
1665 IS_CHAN_2GHZ(chan));
1669 * For non-AR9550 chips, we just trigger AGC calibration
1670 * in the HW, poll for completion and then process
1673 * For AR955x, we run it multiple times and use
1674 * median IQ correction.
1676 if (!AR_SREV_9550(ah)) {
1677 status = do_ar9003_agc_cal(ah);
1682 ar9003_hw_tx_iq_cal_post_proc(ah, 0, false);
1684 if (!txiqcal_done) {
1685 status = do_ar9003_agc_cal(ah);
1689 for (i = 0; i < MAXIQCAL; i++) {
1690 status = do_ar9003_agc_cal(ah);
1693 ar9003_hw_tx_iq_cal_post_proc(ah, i, false);
1699 /* Revert chainmask to runtime parameters */
1700 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1702 ar9003_hw_init_cal_common(ah);
1707 void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
1709 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1710 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1712 if (AR_SREV_9003_PCOEM(ah))
1713 priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
1715 priv_ops->init_cal = ar9003_hw_init_cal_soc;
1717 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
1718 priv_ops->setup_calibration = ar9003_hw_setup_calibration;
1720 ops->calibrate = ar9003_hw_calibrate;