drivers/net/wireless/ath/ath9k/init.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/ath9k_platform.h>
  22 #include <linux/module.h>
  23 #include <linux/relay.h>
  24 #include <net/ieee80211_radiotap.h>
  25
  26 #include "ath9k.h"
  27
  28 struct ath9k_eeprom_ctx {
  29         struct completion complete;
  30         struct ath_hw *ah;
  31 };
  32
  33 static char *dev_info = "ath9k";
  34
  35 MODULE_AUTHOR("Atheros Communications");
  36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  38 MODULE_LICENSE("Dual BSD/GPL");
  39
  40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  41 module_param_named(debug, ath9k_debug, uint, 0);
  42 MODULE_PARM_DESC(debug, "Debugging mask");
  43
  44 int ath9k_modparam_nohwcrypt;
  45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
  46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  47
  48 int led_blink;
  49 module_param_named(blink, led_blink, int, 0444);
  50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
  51
  52 static int ath9k_btcoex_enable;
  53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
  54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
  55
  56 static int ath9k_bt_ant_diversity;
  57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
  58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
  59
  60 static int ath9k_ps_enable;
  61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
  62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
  63
  64 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  65
  66 int ath9k_use_chanctx;
  67 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
  68 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
  69
  70 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
  71
  72 bool is_ath9k_unloaded;
  73
  74 #ifdef CONFIG_MAC80211_LEDS
  75 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
  76         { .throughput = 0 * 1024, .blink_time = 334 },
  77         { .throughput = 1 * 1024, .blink_time = 260 },
  78         { .throughput = 5 * 1024, .blink_time = 220 },
  79         { .throughput = 10 * 1024, .blink_time = 190 },
  80         { .throughput = 20 * 1024, .blink_time = 170 },
  81         { .throughput = 50 * 1024, .blink_time = 150 },
  82         { .throughput = 70 * 1024, .blink_time = 130 },
  83         { .throughput = 100 * 1024, .blink_time = 110 },
  84         { .throughput = 200 * 1024, .blink_time = 80 },
  85         { .throughput = 300 * 1024, .blink_time = 50 },
  86 };
  87 #endif
  88
  89 static void ath9k_deinit_softc(struct ath_softc *sc);
  90
  91 /*
  92  * Read and write, they both share the same lock. We do this to serialize
  93  * reads and writes on Atheros 802.11n PCI devices only. This is required
  94  * as the FIFO on these devices can only accept sanely 2 requests.
  95  */
  96
  97 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
  98 {
  99         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 100         struct ath_common *common = ath9k_hw_common(ah);
 101         struct ath_softc *sc = (struct ath_softc *) common->priv;
 102
 103         if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 104                 unsigned long flags;
 105                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
 106                 iowrite32(val, sc->mem + reg_offset);
 107                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 108         } else
 109                 iowrite32(val, sc->mem + reg_offset);
 110 }
 111
 112 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
 113 {
 114         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 115         struct ath_common *common = ath9k_hw_common(ah);
 116         struct ath_softc *sc = (struct ath_softc *) common->priv;
 117         u32 val;
 118
 119         if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 120                 unsigned long flags;
 121                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
 122                 val = ioread32(sc->mem + reg_offset);
 123                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 124         } else
 125                 val = ioread32(sc->mem + reg_offset);
 126         return val;
 127 }
 128
 129 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
 130                                     u32 set, u32 clr)
 131 {
 132         u32 val;
 133
 134         val = ioread32(sc->mem + reg_offset);
 135         val &= ~clr;
 136         val |= set;
 137         iowrite32(val, sc->mem + reg_offset);
 138
 139         return val;
 140 }
 141
 142 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
 143 {
 144         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 145         struct ath_common *common = ath9k_hw_common(ah);
 146         struct ath_softc *sc = (struct ath_softc *) common->priv;
 147         unsigned long uninitialized_var(flags);
 148         u32 val;
 149
 150         if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 151                 spin_lock_irqsave(&sc->sc_serial_rw, flags);
 152                 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
 153                 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 154         } else
 155                 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
 156
 157         return val;
 158 }
 159
 160 /**************************/
 161 /*     Initialization     */
 162 /**************************/
 163
 164 static void ath9k_reg_notifier(struct wiphy *wiphy,
 165                                struct regulatory_request *request)
 166 {
 167         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
 168         struct ath_softc *sc = hw->priv;
 169         struct ath_hw *ah = sc->sc_ah;
 170         struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
 171
 172         ath_reg_notifier_apply(wiphy, request, reg);
 173
 174         /* Set tx power */
 175         if (!ah->curchan)
 176                 return;
 177
 178         sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
 179         ath9k_ps_wakeup(sc);
 180         ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
 181         ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
 182                                sc->cur_chan->txpower,
 183                                &sc->cur_chan->cur_txpower);
 184         /* synchronize DFS detector if regulatory domain changed */
 185         if (sc->dfs_detector != NULL)
 186                 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
 187                                                  request->dfs_region);
 188         ath9k_ps_restore(sc);
 189 }
 190
 191 /*
 192  *  This function will allocate both the DMA descriptor structure, and the
 193  *  buffers it contains.  These are used to contain the descriptors used
 194  *  by the system.
 195 */
 196 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 197                       struct list_head *head, const char *name,
 198                       int nbuf, int ndesc, bool is_tx)
 199 {
 200         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 201         u8 *ds;
 202         int i, bsize, desc_len;
 203
 204         ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
 205                 name, nbuf, ndesc);
 206
 207         INIT_LIST_HEAD(head);
 208
 209         if (is_tx)
 210                 desc_len = sc->sc_ah->caps.tx_desc_len;
 211         else
 212                 desc_len = sizeof(struct ath_desc);
 213
 214         /* ath_desc must be a multiple of DWORDs */
 215         if ((desc_len % 4) != 0) {
 216                 ath_err(common, "ath_desc not DWORD aligned\n");
 217                 BUG_ON((desc_len % 4) != 0);
 218                 return -ENOMEM;
 219         }
 220
 221         dd->dd_desc_len = desc_len * nbuf * ndesc;
 222
 223         /*
 224          * Need additional DMA memory because we can't use
 225          * descriptors that cross the 4K page boundary. Assume
 226          * one skipped descriptor per 4K page.
 227          */
 228         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 229                 u32 ndesc_skipped =
 230                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
 231                 u32 dma_len;
 232
 233                 while (ndesc_skipped) {
 234                         dma_len = ndesc_skipped * desc_len;
 235                         dd->dd_desc_len += dma_len;
 236
 237                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
 238                 }
 239         }
 240
 241         /* allocate descriptors */
 242         dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
 243                                           &dd->dd_desc_paddr, GFP_KERNEL);
 244         if (!dd->dd_desc)
 245                 return -ENOMEM;
 246
 247         ds = (u8 *) dd->dd_desc;
 248         ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
 249                 name, ds, (u32) dd->dd_desc_len,
 250                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
 251
 252         /* allocate buffers */
 253         if (is_tx) {
 254                 struct ath_buf *bf;
 255
 256                 bsize = sizeof(struct ath_buf) * nbuf;
 257                 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
 258                 if (!bf)
 259                         return -ENOMEM;
 260
 261                 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
 262                         bf->bf_desc = ds;
 263                         bf->bf_daddr = DS2PHYS(dd, ds);
 264
 265                         if (!(sc->sc_ah->caps.hw_caps &
 266                                   ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 267                                 /*
 268                                  * Skip descriptor addresses which can cause 4KB
 269                                  * boundary crossing (addr + length) with a 32 dword
 270                                  * descriptor fetch.
 271                                  */
 272                                 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
 273                                         BUG_ON((caddr_t) bf->bf_desc >=
 274                                                    ((caddr_t) dd->dd_desc +
 275                                                 dd->dd_desc_len));
 276
 277                                         ds += (desc_len * ndesc);
 278                                         bf->bf_desc = ds;
 279                                         bf->bf_daddr = DS2PHYS(dd, ds);
 280                                 }
 281                         }
 282                         list_add_tail(&bf->list, head);
 283                 }
 284         } else {
 285                 struct ath_rxbuf *bf;
 286
 287                 bsize = sizeof(struct ath_rxbuf) * nbuf;
 288                 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
 289                 if (!bf)
 290                         return -ENOMEM;
 291
 292                 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
 293                         bf->bf_desc = ds;
 294                         bf->bf_daddr = DS2PHYS(dd, ds);
 295
 296                         if (!(sc->sc_ah->caps.hw_caps &
 297                                   ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 298                                 /*
 299                                  * Skip descriptor addresses which can cause 4KB
 300                                  * boundary crossing (addr + length) with a 32 dword
 301                                  * descriptor fetch.
 302                                  */
 303                                 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
 304                                         BUG_ON((caddr_t) bf->bf_desc >=
 305                                                    ((caddr_t) dd->dd_desc +
 306                                                 dd->dd_desc_len));
 307
 308                                         ds += (desc_len * ndesc);
 309                                         bf->bf_desc = ds;
 310                                         bf->bf_daddr = DS2PHYS(dd, ds);
 311                                 }
 312                         }
 313                         list_add_tail(&bf->list, head);
 314                 }
 315         }
 316         return 0;
 317 }
 318
 319 static int ath9k_init_queues(struct ath_softc *sc)
 320 {
 321         int i = 0;
 322
 323         sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
 324         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
 325         ath_cabq_update(sc);
 326
 327         sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
 328
 329         for (i = 0; i < IEEE80211_NUM_ACS; i++) {
 330                 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
 331                 sc->tx.txq_map[i]->mac80211_qnum = i;
 332                 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
 333         }
 334         return 0;
 335 }
 336
 337 static void ath9k_init_misc(struct ath_softc *sc)
 338 {
 339         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 340         int i = 0;
 341
 342         setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
 343
 344         common->last_rssi = ATH_RSSI_DUMMY_MARKER;
 345         memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
 346         sc->beacon.slottime = ATH9K_SLOT_TIME_9;
 347
 348         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
 349                 sc->beacon.bslot[i] = NULL;
 350
 351         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
 352                 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
 353
 354         sc->spec_config.enabled = 0;
 355         sc->spec_config.short_repeat = true;
 356         sc->spec_config.count = 8;
 357         sc->spec_config.endless = false;
 358         sc->spec_config.period = 0xFF;
 359         sc->spec_config.fft_period = 0xF;
 360 }
 361
 362 static void ath9k_init_pcoem_platform(struct ath_softc *sc)
 363 {
 364         struct ath_hw *ah = sc->sc_ah;
 365         struct ath9k_hw_capabilities *pCap = &ah->caps;
 366         struct ath_common *common = ath9k_hw_common(ah);
 367
 368         if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
 369                 return;
 370
 371         if (common->bus_ops->ath_bus_type != ATH_PCI)
 372                 return;
 373
 374         if (sc->driver_data & (ATH9K_PCI_CUS198 |
 375                                ATH9K_PCI_CUS230)) {
 376                 ah->config.xlna_gpio = 9;
 377                 ah->config.xatten_margin_cfg = true;
 378                 ah->config.alt_mingainidx = true;
 379                 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
 380                 sc->ant_comb.low_rssi_thresh = 20;
 381                 sc->ant_comb.fast_div_bias = 3;
 382
 383                 ath_info(common, "Set parameters for %s\n",
 384                          (sc->driver_data & ATH9K_PCI_CUS198) ?
 385                          "CUS198" : "CUS230");
 386         }
 387
 388         if (sc->driver_data & ATH9K_PCI_CUS217)
 389                 ath_info(common, "CUS217 card detected\n");
 390
 391         if (sc->driver_data & ATH9K_PCI_CUS252)
 392                 ath_info(common, "CUS252 card detected\n");
 393
 394         if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
 395                 ath_info(common, "WB335 1-ANT card detected\n");
 396
 397         if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
 398                 ath_info(common, "WB335 2-ANT card detected\n");
 399
 400         if (sc->driver_data & ATH9K_PCI_KILLER)
 401                 ath_info(common, "Killer Wireless card detected\n");
 402
 403         /*
 404          * Some WB335 cards do not support antenna diversity. Since
 405          * we use a hardcoded value for AR9565 instead of using the
 406          * EEPROM/OTP data, remove the combining feature from
 407          * the HW capabilities bitmap.
 408          */
 409         if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
 410                 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
 411                         pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
 412         }
 413
 414         if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
 415                 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
 416                 ath_info(common, "Set BT/WLAN RX diversity capability\n");
 417         }
 418
 419         if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
 420                 ah->config.pcie_waen = 0x0040473b;
 421                 ath_info(common, "Enable WAR for ASPM D3/L1\n");
 422         }
 423
 424         if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
 425                 ah->config.no_pll_pwrsave = true;
 426                 ath_info(common, "Disable PLL PowerSave\n");
 427         }
 428 }
 429
 430 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
 431                                     void *ctx)
 432 {
 433         struct ath9k_eeprom_ctx *ec = ctx;
 434
 435         if (eeprom_blob)
 436                 ec->ah->eeprom_blob = eeprom_blob;
 437
 438         complete(&ec->complete);
 439 }
 440
 441 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
 442 {
 443         struct ath9k_eeprom_ctx ec;
 444         struct ath_hw *ah = ah = sc->sc_ah;
 445         int err;
 446
 447         /* try to load the EEPROM content asynchronously */
 448         init_completion(&ec.complete);
 449         ec.ah = sc->sc_ah;
 450
 451         err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
 452                                       &ec, ath9k_eeprom_request_cb);
 453         if (err < 0) {
 454                 ath_err(ath9k_hw_common(ah),
 455                         "EEPROM request failed\n");
 456                 return err;
 457         }
 458
 459         wait_for_completion(&ec.complete);
 460
 461         if (!ah->eeprom_blob) {
 462                 ath_err(ath9k_hw_common(ah),
 463                         "Unable to load EEPROM file %s\n", name);
 464                 return -EINVAL;
 465         }
 466
 467         return 0;
 468 }
 469
 470 static void ath9k_eeprom_release(struct ath_softc *sc)
 471 {
 472         release_firmware(sc->sc_ah->eeprom_blob);
 473 }
 474
 475 static int ath9k_init_soc_platform(struct ath_softc *sc)
 476 {
 477         struct ath9k_platform_data *pdata = sc->dev->platform_data;
 478         struct ath_hw *ah = sc->sc_ah;
 479         int ret = 0;
 480
 481         if (!pdata)
 482                 return 0;
 483
 484         if (pdata->eeprom_name) {
 485                 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
 486                 if (ret)
 487                         return ret;
 488         }
 489
 490         if (pdata->tx_gain_buffalo)
 491                 ah->config.tx_gain_buffalo = true;
 492
 493         return ret;
 494 }
 495
 496 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
 497                             const struct ath_bus_ops *bus_ops)
 498 {
 499         struct ath9k_platform_data *pdata = sc->dev->platform_data;
 500         struct ath_hw *ah = NULL;
 501         struct ath9k_hw_capabilities *pCap;
 502         struct ath_common *common;
 503         int ret = 0, i;
 504         int csz = 0;
 505
 506         ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
 507         if (!ah)
 508                 return -ENOMEM;
 509
 510         ah->dev = sc->dev;
 511         ah->hw = sc->hw;
 512         ah->hw_version.devid = devid;
 513         ah->reg_ops.read = ath9k_ioread32;
 514         ah->reg_ops.write = ath9k_iowrite32;
 515         ah->reg_ops.rmw = ath9k_reg_rmw;
 516         sc->sc_ah = ah;
 517         pCap = &ah->caps;
 518
 519         common = ath9k_hw_common(ah);
 520         sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
 521         sc->tx99_power = MAX_RATE_POWER + 1;
 522         init_waitqueue_head(&sc->tx_wait);
 523         sc->cur_chan = &sc->chanctx[0];
 524         if (!ath9k_is_chanctx_enabled())
 525                 sc->cur_chan->hw_queue_base = 0;
 526
 527         if (!pdata || pdata->use_eeprom) {
 528                 ah->ah_flags |= AH_USE_EEPROM;
 529                 sc->sc_ah->led_pin = -1;
 530         } else {
 531                 sc->sc_ah->gpio_mask = pdata->gpio_mask;
 532                 sc->sc_ah->gpio_val = pdata->gpio_val;
 533                 sc->sc_ah->led_pin = pdata->led_pin;
 534                 ah->is_clk_25mhz = pdata->is_clk_25mhz;
 535                 ah->get_mac_revision = pdata->get_mac_revision;
 536                 ah->external_reset = pdata->external_reset;
 537                 ah->disable_2ghz = pdata->disable_2ghz;
 538                 ah->disable_5ghz = pdata->disable_5ghz;
 539                 if (!pdata->endian_check)
 540                         ah->ah_flags |= AH_NO_EEP_SWAP;
 541         }
 542
 543         common->ops = &ah->reg_ops;
 544         common->bus_ops = bus_ops;
 545         common->ah = ah;
 546         common->hw = sc->hw;
 547         common->priv = sc;
 548         common->debug_mask = ath9k_debug;
 549         common->btcoex_enabled = ath9k_btcoex_enable == 1;
 550         common->disable_ani = false;
 551
 552         /*
 553          * Platform quirks.
 554          */
 555         ath9k_init_pcoem_platform(sc);
 556
 557         ret = ath9k_init_soc_platform(sc);
 558         if (ret)
 559                 return ret;
 560
 561         /*
 562          * Enable WLAN/BT RX Antenna diversity only when:
 563          *
 564          * - BTCOEX is disabled.
 565          * - the user manually requests the feature.
 566          * - the HW cap is set using the platform data.
 567          */
 568         if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
 569             (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
 570                 common->bt_ant_diversity = 1;
 571
 572         spin_lock_init(&common->cc_lock);
 573         spin_lock_init(&sc->sc_serial_rw);
 574         spin_lock_init(&sc->sc_pm_lock);
 575         spin_lock_init(&sc->chan_lock);
 576         mutex_init(&sc->mutex);
 577         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
 578         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
 579                      (unsigned long)sc);
 580
 581         setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
 582         INIT_WORK(&sc->hw_reset_work, ath_reset_work);
 583         INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
 584         INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
 585
 586         ath9k_init_channel_context(sc);
 587
 588         /*
 589          * Cache line size is used to size and align various
 590          * structures used to communicate with the hardware.
 591          */
 592         ath_read_cachesize(common, &csz);
 593         common->cachelsz = csz << 2; /* convert to bytes */
 594
 595         /* Initializes the hardware for all supported chipsets */
 596         ret = ath9k_hw_init(ah);
 597         if (ret)
 598                 goto err_hw;
 599
 600         if (pdata && pdata->macaddr)
 601                 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
 602
 603         ret = ath9k_init_queues(sc);
 604         if (ret)
 605                 goto err_queues;
 606
 607         ret =  ath9k_init_btcoex(sc);
 608         if (ret)
 609                 goto err_btcoex;
 610
 611         ret = ath9k_cmn_init_channels_rates(common);
 612         if (ret)
 613                 goto err_btcoex;
 614
 615         ret = ath9k_init_p2p(sc);
 616         if (ret)
 617                 goto err_btcoex;
 618
 619         ath9k_cmn_init_crypto(sc->sc_ah);
 620         ath9k_init_misc(sc);
 621         ath_fill_led_pin(sc);
 622         ath_chanctx_init(sc);
 623         ath9k_offchannel_init(sc);
 624
 625         if (common->bus_ops->aspm_init)
 626                 common->bus_ops->aspm_init(common);
 627
 628         return 0;
 629
 630 err_btcoex:
 631         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
 632                 if (ATH_TXQ_SETUP(sc, i))
 633                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 634 err_queues:
 635         ath9k_hw_deinit(ah);
 636 err_hw:
 637         ath9k_eeprom_release(sc);
 638         dev_kfree_skb_any(sc->tx99_skb);
 639         return ret;
 640 }
 641
 642 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
 643 {
 644         struct ieee80211_supported_band *sband;
 645         struct ieee80211_channel *chan;
 646         struct ath_hw *ah = sc->sc_ah;
 647         struct ath_common *common = ath9k_hw_common(ah);
 648         struct cfg80211_chan_def chandef;
 649         int i;
 650
 651         sband = &common->sbands[band];
 652         for (i = 0; i < sband->n_channels; i++) {
 653                 chan = &sband->channels[i];
 654                 ah->curchan = &ah->channels[chan->hw_value];
 655                 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
 656                 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
 657                 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
 658         }
 659 }
 660
 661 static void ath9k_init_txpower_limits(struct ath_softc *sc)
 662 {
 663         struct ath_hw *ah = sc->sc_ah;
 664         struct ath9k_channel *curchan = ah->curchan;
 665
 666         if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 667                 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
 668         if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 669                 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
 670
 671         ah->curchan = curchan;
 672 }
 673
 674 static const struct ieee80211_iface_limit if_limits[] = {
 675         { .max = 2048,  .types = BIT(NL80211_IFTYPE_STATION) },
 676         { .max = 8,     .types =
 677 #ifdef CONFIG_MAC80211_MESH
 678                                  BIT(NL80211_IFTYPE_MESH_POINT) |
 679 #endif
 680                                  BIT(NL80211_IFTYPE_AP) },
 681         { .max = 1,     .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
 682                                  BIT(NL80211_IFTYPE_P2P_GO) },
 683 };
 684
 685 static const struct ieee80211_iface_limit wds_limits[] = {
 686         { .max = 2048,  .types = BIT(NL80211_IFTYPE_WDS) },
 687 };
 688
 689 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 690
 691 static const struct ieee80211_iface_limit if_limits_multi[] = {
 692         { .max = 2,     .types = BIT(NL80211_IFTYPE_STATION) |
 693                                  BIT(NL80211_IFTYPE_AP) |
 694                                  BIT(NL80211_IFTYPE_P2P_CLIENT) |
 695                                  BIT(NL80211_IFTYPE_P2P_GO) },
 696         { .max = 1,     .types = BIT(NL80211_IFTYPE_ADHOC) },
 697 };
 698
 699 static const struct ieee80211_iface_combination if_comb_multi[] = {
 700         {
 701                 .limits = if_limits_multi,
 702                 .n_limits = ARRAY_SIZE(if_limits_multi),
 703                 .max_interfaces = 2,
 704                 .num_different_channels = 2,
 705                 .beacon_int_infra_match = true,
 706         },
 707 };
 708
 709 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
 710
 711 static const struct ieee80211_iface_limit if_dfs_limits[] = {
 712         { .max = 1,     .types = BIT(NL80211_IFTYPE_AP) |
 713 #ifdef CONFIG_MAC80211_MESH
 714                                  BIT(NL80211_IFTYPE_MESH_POINT) |
 715 #endif
 716                                  BIT(NL80211_IFTYPE_ADHOC) },
 717 };
 718
 719 static const struct ieee80211_iface_combination if_comb[] = {
 720         {
 721                 .limits = if_limits,
 722                 .n_limits = ARRAY_SIZE(if_limits),
 723                 .max_interfaces = 2048,
 724                 .num_different_channels = 1,
 725                 .beacon_int_infra_match = true,
 726         },
 727         {
 728                 .limits = wds_limits,
 729                 .n_limits = ARRAY_SIZE(wds_limits),
 730                 .max_interfaces = 2048,
 731                 .num_different_channels = 1,
 732                 .beacon_int_infra_match = true,
 733         },
 734 #ifdef CONFIG_ATH9K_DFS_CERTIFIED
 735         {
 736                 .limits = if_dfs_limits,
 737                 .n_limits = ARRAY_SIZE(if_dfs_limits),
 738                 .max_interfaces = 1,
 739                 .num_different_channels = 1,
 740                 .beacon_int_infra_match = true,
 741                 .radar_detect_widths =  BIT(NL80211_CHAN_WIDTH_20_NOHT) |
 742                                         BIT(NL80211_CHAN_WIDTH_20),
 743         }
 744 #endif
 745 };
 746
 747 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 748 {
 749         struct ath_hw *ah = sc->sc_ah;
 750         struct ath_common *common = ath9k_hw_common(ah);
 751
 752         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
 753                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
 754                 IEEE80211_HW_SIGNAL_DBM |
 755                 IEEE80211_HW_PS_NULLFUNC_STACK |
 756                 IEEE80211_HW_SPECTRUM_MGMT |
 757                 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
 758                 IEEE80211_HW_SUPPORTS_RC_TABLE |
 759                 IEEE80211_HW_QUEUE_CONTROL |
 760                 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
 761
 762         if (ath9k_ps_enable)
 763                 hw->flags |= IEEE80211_HW_SUPPORTS_PS;
 764
 765         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
 766                 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
 767
 768                 if (AR_SREV_9280_20_OR_LATER(ah))
 769                         hw->radiotap_mcs_details |=
 770                                 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
 771         }
 772
 773         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
 774                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
 775
 776         hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
 777                                NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
 778                                NL80211_FEATURE_P2P_GO_CTWIN;
 779
 780         if (!config_enabled(CONFIG_ATH9K_TX99)) {
 781                 hw->wiphy->interface_modes =
 782                         BIT(NL80211_IFTYPE_P2P_GO) |
 783                         BIT(NL80211_IFTYPE_P2P_CLIENT) |
 784                         BIT(NL80211_IFTYPE_AP) |
 785                         BIT(NL80211_IFTYPE_STATION) |
 786                         BIT(NL80211_IFTYPE_ADHOC) |
 787                         BIT(NL80211_IFTYPE_MESH_POINT) |
 788                         BIT(NL80211_IFTYPE_WDS);
 789
 790                         hw->wiphy->iface_combinations = if_comb;
 791                         hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
 792         }
 793
 794 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 795
 796         if (ath9k_is_chanctx_enabled()) {
 797                 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS);
 798                 hw->wiphy->iface_combinations = if_comb_multi;
 799                 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
 800                 hw->wiphy->max_scan_ssids = 255;
 801                 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
 802                 hw->wiphy->max_remain_on_channel_duration = 10000;
 803                 hw->chanctx_data_size = sizeof(void *);
 804                 hw->extra_beacon_tailroom =
 805                         sizeof(struct ieee80211_p2p_noa_attr) + 9;
 806
 807                 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
 808         }
 809
 810 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
 811
 812         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 813
 814         hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
 815         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
 816         hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
 817         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
 818         hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
 819         hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
 820
 821         /* allow 4 queues per channel context +
 822          * 1 cab queue + 1 offchannel tx queue
 823          */
 824         hw->queues = ATH9K_NUM_TX_QUEUES;
 825         /* last queue for offchannel */
 826         hw->offchannel_tx_hw_queue = hw->queues - 1;
 827         hw->max_rates = 4;
 828         hw->max_listen_interval = 10;
 829         hw->max_rate_tries = 10;
 830         hw->sta_data_size = sizeof(struct ath_node);
 831         hw->vif_data_size = sizeof(struct ath_vif);
 832
 833         hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
 834         hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
 835
 836         /* single chain devices with rx diversity */
 837         if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
 838                 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
 839
 840         sc->ant_rx = hw->wiphy->available_antennas_rx;
 841         sc->ant_tx = hw->wiphy->available_antennas_tx;
 842
 843         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 844                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 845                         &common->sbands[IEEE80211_BAND_2GHZ];
 846         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 847                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 848                         &common->sbands[IEEE80211_BAND_5GHZ];
 849
 850         ath9k_init_wow(hw);
 851         ath9k_cmn_reload_chainmask(ah);
 852
 853         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
 854 }
 855
 856 int ath9k_init_device(u16 devid, struct ath_softc *sc,
 857                     const struct ath_bus_ops *bus_ops)
 858 {
 859         struct ieee80211_hw *hw = sc->hw;
 860         struct ath_common *common;
 861         struct ath_hw *ah;
 862         int error = 0;
 863         struct ath_regulatory *reg;
 864
 865         /* Bring up device */
 866         error = ath9k_init_softc(devid, sc, bus_ops);
 867         if (error)
 868                 return error;
 869
 870         ah = sc->sc_ah;
 871         common = ath9k_hw_common(ah);
 872         ath9k_set_hw_capab(sc, hw);
 873
 874         /* Will be cleared in ath9k_start() */
 875         set_bit(ATH_OP_INVALID, &common->op_flags);
 876
 877         /* Initialize regulatory */
 878         error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
 879                               ath9k_reg_notifier);
 880         if (error)
 881                 goto deinit;
 882
 883         reg = &common->regulatory;
 884
 885         /* Setup TX DMA */
 886         error = ath_tx_init(sc, ATH_TXBUF);
 887         if (error != 0)
 888                 goto deinit;
 889
 890         /* Setup RX DMA */
 891         error = ath_rx_init(sc, ATH_RXBUF);
 892         if (error != 0)
 893                 goto deinit;
 894
 895         ath9k_init_txpower_limits(sc);
 896
 897 #ifdef CONFIG_MAC80211_LEDS
 898         /* must be initialized before ieee80211_register_hw */
 899         sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
 900                 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
 901                 ARRAY_SIZE(ath9k_tpt_blink));
 902 #endif
 903
 904         /* Register with mac80211 */
 905         error = ieee80211_register_hw(hw);
 906         if (error)
 907                 goto rx_cleanup;
 908
 909         error = ath9k_init_debug(ah);
 910         if (error) {
 911                 ath_err(common, "Unable to create debugfs files\n");
 912                 goto unregister;
 913         }
 914
 915         /* Handle world regulatory */
 916         if (!ath_is_world_regd(reg)) {
 917                 error = regulatory_hint(hw->wiphy, reg->alpha2);
 918                 if (error)
 919                         goto debug_cleanup;
 920         }
 921
 922         ath_init_leds(sc);
 923         ath_start_rfkill_poll(sc);
 924
 925         return 0;
 926
 927 debug_cleanup:
 928         ath9k_deinit_debug(sc);
 929 unregister:
 930         ieee80211_unregister_hw(hw);
 931 rx_cleanup:
 932         ath_rx_cleanup(sc);
 933 deinit:
 934         ath9k_deinit_softc(sc);
 935         return error;
 936 }
 937
 938 /*****************************/
 939 /*     De-Initialization     */
 940 /*****************************/
 941
 942 static void ath9k_deinit_softc(struct ath_softc *sc)
 943 {
 944         int i = 0;
 945
 946         ath9k_deinit_p2p(sc);
 947         ath9k_deinit_btcoex(sc);
 948
 949         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
 950                 if (ATH_TXQ_SETUP(sc, i))
 951                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 952
 953         del_timer_sync(&sc->sleep_timer);
 954         ath9k_hw_deinit(sc->sc_ah);
 955         if (sc->dfs_detector != NULL)
 956                 sc->dfs_detector->exit(sc->dfs_detector);
 957
 958         ath9k_eeprom_release(sc);
 959 }
 960
 961 void ath9k_deinit_device(struct ath_softc *sc)
 962 {
 963         struct ieee80211_hw *hw = sc->hw;
 964
 965         ath9k_ps_wakeup(sc);
 966
 967         wiphy_rfkill_stop_polling(sc->hw->wiphy);
 968         ath_deinit_leds(sc);
 969
 970         ath9k_ps_restore(sc);
 971
 972         ath9k_deinit_debug(sc);
 973         ieee80211_unregister_hw(hw);
 974         ath_rx_cleanup(sc);
 975         ath9k_deinit_softc(sc);
 976 }
 977
 978 /************************/
 979 /*     Module Hooks     */
 980 /************************/
 981
 982 static int __init ath9k_init(void)
 983 {
 984         int error;
 985
 986         error = ath_pci_init();
 987         if (error < 0) {
 988                 pr_err("No PCI devices found, driver not installed\n");
 989                 error = -ENODEV;
 990                 goto err_out;
 991         }
 992
 993         error = ath_ahb_init();
 994         if (error < 0) {
 995                 error = -ENODEV;
 996                 goto err_pci_exit;
 997         }
 998
 999         return 0;
1000
1001  err_pci_exit:
1002         ath_pci_exit();
1003  err_out:
1004         return error;
1005 }
1006 module_init(ath9k_init);
1007
1008 static void __exit ath9k_exit(void)
1009 {
1010         is_ath9k_unloaded = true;
1011         ath_ahb_exit();
1012         ath_pci_exit();
1013         pr_info("%s: Driver unloaded\n", dev_info);
1014 }
1015 module_exit(ath9k_exit);