2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
22 static u8 parse_mpdudensity(u8 mpdudensity)
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
35 switch (mpdudensity) {
41 /* Our lower layer calculations limit our precision to
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61 spin_lock_bh(&txq->axq_lock);
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
66 spin_unlock_bh(&txq->axq_lock);
70 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
82 void ath9k_ps_wakeup(struct ath_softc *sc)
84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
86 enum ath9k_power_mode power_mode;
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
92 power_mode = sc->sc_ah->power_mode;
93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
111 void ath9k_ps_restore(struct ath_softc *sc)
113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
114 enum ath9k_power_mode mode;
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 if (--sc->ps_usecount != 0)
121 if (sc->ps_idle && (sc->ps_flags & PS_WAIT_FOR_TX_ACK))
122 mode = ATH9K_PM_FULL_SLEEP;
123 else if (sc->ps_enabled &&
124 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
126 PS_WAIT_FOR_PSPOLL_DATA |
127 PS_WAIT_FOR_TX_ACK)))
128 mode = ATH9K_PM_NETWORK_SLEEP;
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 spin_unlock(&common->cc_lock);
136 ath9k_hw_setpower(sc->sc_ah, mode);
139 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
142 void ath_start_ani(struct ath_common *common)
144 struct ath_hw *ah = common->ah;
145 unsigned long timestamp = jiffies_to_msecs(jiffies);
146 struct ath_softc *sc = (struct ath_softc *) common->priv;
148 if (!(sc->sc_flags & SC_OP_ANI_RUN))
151 if (sc->sc_flags & SC_OP_OFFCHANNEL)
154 common->ani.longcal_timer = timestamp;
155 common->ani.shortcal_timer = timestamp;
156 common->ani.checkani_timer = timestamp;
158 mod_timer(&common->ani.timer,
160 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
163 static void ath_update_survey_nf(struct ath_softc *sc, int channel)
165 struct ath_hw *ah = sc->sc_ah;
166 struct ath9k_channel *chan = &ah->channels[channel];
167 struct survey_info *survey = &sc->survey[channel];
169 if (chan->noisefloor) {
170 survey->filled |= SURVEY_INFO_NOISE_DBM;
171 survey->noise = ath9k_hw_getchan_noise(ah, chan);
176 * Updates the survey statistics and returns the busy time since last
177 * update in %, if the measurement duration was long enough for the
178 * result to be useful, -1 otherwise.
180 static int ath_update_survey_stats(struct ath_softc *sc)
182 struct ath_hw *ah = sc->sc_ah;
183 struct ath_common *common = ath9k_hw_common(ah);
184 int pos = ah->curchan - &ah->channels[0];
185 struct survey_info *survey = &sc->survey[pos];
186 struct ath_cycle_counters *cc = &common->cc_survey;
187 unsigned int div = common->clockrate * 1000;
193 if (ah->power_mode == ATH9K_PM_AWAKE)
194 ath_hw_cycle_counters_update(common);
196 if (cc->cycles > 0) {
197 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
198 SURVEY_INFO_CHANNEL_TIME_BUSY |
199 SURVEY_INFO_CHANNEL_TIME_RX |
200 SURVEY_INFO_CHANNEL_TIME_TX;
201 survey->channel_time += cc->cycles / div;
202 survey->channel_time_busy += cc->rx_busy / div;
203 survey->channel_time_rx += cc->rx_frame / div;
204 survey->channel_time_tx += cc->tx_frame / div;
207 if (cc->cycles < div)
211 ret = cc->rx_busy * 100 / cc->cycles;
213 memset(cc, 0, sizeof(*cc));
215 ath_update_survey_nf(sc, pos);
220 static void __ath_cancel_work(struct ath_softc *sc)
222 struct ath_hw *ah = sc->sc_ah;
223 struct ath_common *common = ath9k_hw_common(ah);
225 if (sc->sc_flags & SC_OP_INVALID)
228 sc->hw_busy_count = 0;
230 del_timer_sync(&common->ani.timer);
231 del_timer_sync(&sc->rx_poll_timer);
232 cancel_work_sync(&sc->paprd_work);
233 cancel_work_sync(&sc->hw_check_work);
234 cancel_work_sync(&sc->hw_reset_work);
235 cancel_delayed_work_sync(&sc->tx_complete_work);
236 cancel_delayed_work_sync(&sc->hw_pll_work);
239 static void ath_cancel_work(struct ath_softc *sc)
241 __ath_cancel_work(sc);
244 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
246 struct ath_hw *ah = sc->sc_ah;
247 struct ath_common *common = ath9k_hw_common(ah);
250 ieee80211_stop_queues(sc->hw);
252 sc->hw_busy_count = 0;
253 del_timer_sync(&common->ani.timer);
255 ath9k_debug_samp_bb_mac(sc);
256 ath9k_hw_disable_interrupts(ah);
258 ret = ath_drain_all_txq(sc, retry_tx);
260 if (!ath_stoprecv(sc))
264 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
265 ath_rx_tasklet(sc, 1, true);
266 ath_rx_tasklet(sc, 1, false);
274 static bool ath_complete_reset(struct ath_softc *sc, bool start)
276 struct ath_hw *ah = sc->sc_ah;
277 struct ath_common *common = ath9k_hw_common(ah);
279 if (ath_startrecv(sc) != 0) {
280 ath_err(common, "Unable to restart recv logic\n");
284 ath9k_cmn_update_txpow(ah, sc->curtxpow,
285 sc->config.txpowlimit, &sc->curtxpow);
286 ath9k_hw_set_interrupts(ah);
287 ath9k_hw_enable_interrupts(ah);
289 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
290 if (sc->sc_flags & SC_OP_BEACONS)
293 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
294 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
295 if (!common->disable_ani)
296 ath_start_ani(common);
297 ath_start_rx_poll(sc, 100);
300 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
301 struct ath_hw_antcomb_conf div_ant_conf;
304 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
307 lna_conf = ATH_ANT_DIV_COMB_LNA1;
309 lna_conf = ATH_ANT_DIV_COMB_LNA2;
310 div_ant_conf.main_lna_conf = lna_conf;
311 div_ant_conf.alt_lna_conf = lna_conf;
313 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
316 ieee80211_wake_queues(sc->hw);
321 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
324 struct ath_hw *ah = sc->sc_ah;
325 struct ath_common *common = ath9k_hw_common(ah);
326 struct ath9k_hw_cal_data *caldata = NULL;
331 __ath_cancel_work(sc);
333 spin_lock_bh(&sc->sc_pcu_lock);
335 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
337 caldata = &sc->caldata;
346 if (!ath_prepare_reset(sc, retry_tx, flush))
349 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
350 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
352 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
355 "Unable to reset channel, reset status %d\n", r);
359 if (!ath_complete_reset(sc, true))
363 spin_unlock_bh(&sc->sc_pcu_lock);
369 * Set/change channels. If the channel is really being changed, it's done
370 * by reseting the chip. To accomplish this we must first cleanup any pending
371 * DMA, then restart stuff.
373 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
374 struct ath9k_channel *hchan)
378 if (sc->sc_flags & SC_OP_INVALID)
381 r = ath_reset_internal(sc, hchan, false);
386 static void ath_paprd_activate(struct ath_softc *sc)
388 struct ath_hw *ah = sc->sc_ah;
389 struct ath9k_hw_cal_data *caldata = ah->caldata;
392 if (!caldata || !caldata->paprd_done)
396 ar9003_paprd_enable(ah, false);
397 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
398 if (!(ah->txchainmask & BIT(chain)))
401 ar9003_paprd_populate_single_table(ah, caldata, chain);
404 ar9003_paprd_enable(ah, true);
405 ath9k_ps_restore(sc);
408 static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
410 struct ieee80211_hw *hw = sc->hw;
411 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
412 struct ath_hw *ah = sc->sc_ah;
413 struct ath_common *common = ath9k_hw_common(ah);
414 struct ath_tx_control txctl;
417 memset(&txctl, 0, sizeof(txctl));
418 txctl.txq = sc->tx.txq_map[WME_AC_BE];
420 memset(tx_info, 0, sizeof(*tx_info));
421 tx_info->band = hw->conf.channel->band;
422 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
423 tx_info->control.rates[0].idx = 0;
424 tx_info->control.rates[0].count = 1;
425 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
426 tx_info->control.rates[1].idx = -1;
428 init_completion(&sc->paprd_complete);
429 txctl.paprd = BIT(chain);
431 if (ath_tx_start(hw, skb, &txctl) != 0) {
432 ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
433 dev_kfree_skb_any(skb);
437 time_left = wait_for_completion_timeout(&sc->paprd_complete,
438 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
441 ath_dbg(common, CALIBRATE,
442 "Timeout waiting for paprd training on TX chain %d\n",
448 void ath_paprd_calibrate(struct work_struct *work)
450 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
451 struct ieee80211_hw *hw = sc->hw;
452 struct ath_hw *ah = sc->sc_ah;
453 struct ieee80211_hdr *hdr;
454 struct sk_buff *skb = NULL;
455 struct ath9k_hw_cal_data *caldata = ah->caldata;
456 struct ath_common *common = ath9k_hw_common(ah);
467 if (ar9003_paprd_init_table(ah) < 0)
470 skb = alloc_skb(len, GFP_KERNEL);
475 memset(skb->data, 0, len);
476 hdr = (struct ieee80211_hdr *)skb->data;
477 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
478 hdr->frame_control = cpu_to_le16(ftype);
479 hdr->duration_id = cpu_to_le16(10);
480 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
481 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
482 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
484 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
485 if (!(ah->txchainmask & BIT(chain)))
490 ath_dbg(common, CALIBRATE,
491 "Sending PAPRD frame for thermal measurement on chain %d\n",
493 if (!ath_paprd_send_frame(sc, skb, chain))
496 ar9003_paprd_setup_gain_table(ah, chain);
498 ath_dbg(common, CALIBRATE,
499 "Sending PAPRD training frame on chain %d\n", chain);
500 if (!ath_paprd_send_frame(sc, skb, chain))
503 if (!ar9003_paprd_is_done(ah)) {
504 ath_dbg(common, CALIBRATE,
505 "PAPRD not yet done on chain %d\n", chain);
509 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
510 ath_dbg(common, CALIBRATE,
511 "PAPRD create curve failed on chain %d\n",
521 caldata->paprd_done = true;
522 ath_paprd_activate(sc);
526 ath9k_ps_restore(sc);
530 * This routine performs the periodic noise floor calibration function
531 * that is used to adjust and optimize the chip performance. This
532 * takes environmental changes (location, temperature) into account.
533 * When the task is complete, it reschedules itself depending on the
534 * appropriate interval that was calculated.
536 void ath_ani_calibrate(unsigned long data)
538 struct ath_softc *sc = (struct ath_softc *)data;
539 struct ath_hw *ah = sc->sc_ah;
540 struct ath_common *common = ath9k_hw_common(ah);
541 bool longcal = false;
542 bool shortcal = false;
543 bool aniflag = false;
544 unsigned int timestamp = jiffies_to_msecs(jiffies);
545 u32 cal_interval, short_cal_interval, long_cal_interval;
548 if (ah->caldata && ah->caldata->nfcal_interference)
549 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
551 long_cal_interval = ATH_LONG_CALINTERVAL;
553 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
554 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
556 /* Only calibrate if awake */
557 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
562 /* Long calibration runs independently of short calibration. */
563 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
565 common->ani.longcal_timer = timestamp;
568 /* Short calibration applies only while caldone is false */
569 if (!common->ani.caldone) {
570 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
572 common->ani.shortcal_timer = timestamp;
573 common->ani.resetcal_timer = timestamp;
576 if ((timestamp - common->ani.resetcal_timer) >=
577 ATH_RESTART_CALINTERVAL) {
578 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
579 if (common->ani.caldone)
580 common->ani.resetcal_timer = timestamp;
584 /* Verify whether we must check ANI */
585 if (sc->sc_ah->config.enable_ani
586 && (timestamp - common->ani.checkani_timer) >=
587 ah->config.ani_poll_interval) {
589 common->ani.checkani_timer = timestamp;
592 /* Call ANI routine if necessary */
594 spin_lock_irqsave(&common->cc_lock, flags);
595 ath9k_hw_ani_monitor(ah, ah->curchan);
596 ath_update_survey_stats(sc);
597 spin_unlock_irqrestore(&common->cc_lock, flags);
600 /* Perform calibration if necessary */
601 if (longcal || shortcal) {
602 common->ani.caldone =
603 ath9k_hw_calibrate(ah, ah->curchan,
604 ah->rxchainmask, longcal);
608 "Calibration @%lu finished: %s %s %s, caldone: %s\n",
610 longcal ? "long" : "", shortcal ? "short" : "",
611 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
613 ath9k_ps_restore(sc);
617 * Set timer interval based on previous results.
618 * The interval must be the shortest necessary to satisfy ANI,
619 * short calibration and long calibration.
621 ath9k_debug_samp_bb_mac(sc);
622 cal_interval = ATH_LONG_CALINTERVAL;
623 if (sc->sc_ah->config.enable_ani)
624 cal_interval = min(cal_interval,
625 (u32)ah->config.ani_poll_interval);
626 if (!common->ani.caldone)
627 cal_interval = min(cal_interval, (u32)short_cal_interval);
629 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
630 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
631 if (!ah->caldata->paprd_done)
632 ieee80211_queue_work(sc->hw, &sc->paprd_work);
633 else if (!ah->paprd_table_write_done)
634 ath_paprd_activate(sc);
638 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
639 struct ieee80211_vif *vif)
642 an = (struct ath_node *)sta->drv_priv;
644 #ifdef CONFIG_ATH9K_DEBUGFS
645 spin_lock(&sc->nodes_lock);
646 list_add(&an->list, &sc->nodes);
647 spin_unlock(&sc->nodes_lock);
652 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
653 ath_tx_node_init(sc, an);
654 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
655 sta->ht_cap.ampdu_factor);
656 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
660 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
662 struct ath_node *an = (struct ath_node *)sta->drv_priv;
664 #ifdef CONFIG_ATH9K_DEBUGFS
665 spin_lock(&sc->nodes_lock);
667 spin_unlock(&sc->nodes_lock);
671 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
672 ath_tx_node_cleanup(sc, an);
675 void ath_start_rx_poll(struct ath_softc *sc, u32 nmsec)
677 if (!AR_SREV_9300(sc->sc_ah))
680 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF))
683 mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies(nmsec));
686 void ath_rx_poll_work(unsigned long data)
688 struct ath_softc *sc = (struct ath_softc *)data;
689 struct ath_hw *ah = sc->sc_ah;
690 struct ath_common *common = ath9k_hw_common(ah);
691 struct ieee80211_conf *conf = &common->hw->conf;
692 struct ath9k_nfcal_hist *h = sc->caldata.nfCalHist;
693 static u32 iter, match_count;
696 u32 rx_clear, rx, tx, reg;
698 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
699 u8 nread, nmsec = 10, buf[200];
701 if (jiffies_to_msecs(jiffies - last_run) > 30)
702 iter = match_count = 0;
708 spin_lock_irqsave(&common->cc_lock, flags);
709 ath_hw_cycle_counters_update(common);
711 rx_clear = common->cc_rxpoll.rx_busy * 100 / common->cc_rxpoll.cycles;
712 rx = common->cc_rxpoll.rx_frame * 100 / common->cc_rxpoll.cycles;
713 tx = common->cc_rxpoll.tx_frame * 100 / common->cc_rxpoll.cycles;
714 memset(&common->cc_rxpoll, 0, sizeof(common->cc_rxpoll));
715 spin_unlock_irqrestore(&common->cc_lock, flags);
717 ath_dbg(common, RX_STUCK,
718 "--------------------------------------------------\n");
719 ath_dbg(common, RX_STUCK, "Iteration: %d\n", iter);
720 ath_dbg(common, RX_STUCK, "Cycle Counters:\n");
721 ath_dbg(common, RX_STUCK,
722 "rx_clear = %d%% rx_frame %d%% tx_frame %d%%\n",
725 ath_dbg(common, RX_STUCK, "IMR %08x IER %08x intr_cnt %d\n",
726 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER),
727 atomic_read(&ah->intr_ref_cnt));
729 ath_dbg(common, RX_STUCK, "ts tail %d\n", ah->ts_tail);
731 REG_SET_BIT(ah, AR_DIAG_SW, 0x8080000);
732 for (i = 0; i < 5; i++) {
733 ath_dbg(common, RX_STUCK,
734 "OBS_BUS_1(0x806c) = %08x "
735 "OBS_BUS_CTRL(0x8068) = %08x\n",
736 REG_READ(ah, AR_OBS_BUS_1),
737 REG_READ(ah, AR_OBS_BUS_CTRL));
739 ath_dbg(common, RX_STUCK,
740 "DIAG_SW(0x8048) = %08x MAC_PCU_LOGIC_ANALYZER(0x8264) = %08x"
741 " PCU_MISC_MODE2(0x8344) = %08x\n",
742 REG_READ(ah, AR_DIAG_SW),
743 REG_READ(ah, AR_MAC_PCU_LOGIC_ANALYZER),
744 REG_READ(ah, AR_PCU_MISC_MODE2));
746 ath_dbg(common, RX_STUCK, "0x100 = %08x 0x104 = %08x\n",
747 REG_READ(ah, 0x100), REG_READ(ah, 0x104));
748 for (i = 0; i < 10; i++)
749 ath_dbg(common, RX_STUCK, "QSTS(%d) = %08x\n",
750 i, REG_READ(ah, AR_QSTS(i)));
752 ath_dbg(common, RX_STUCK, "Rxdp: hp %08x lp %08x\n",
753 REG_READ(ah, AR_HP_RXDP), REG_READ(ah, AR_LP_RXDP));
754 ath_dbg(common, RX_STUCK,
755 "rx filter: %08x\n", REG_READ(ah, AR_RX_FILTER));
757 ath_dbg(common, RX_STUCK, "DMADBG dump:\n");
758 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++)
759 ath_dbg(common, RX_STUCK, "%d: %08x ",
760 i, REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32))));
761 ath_dbg(common, RX_STUCK, "\n");
763 ath_dbg(common, RX_STUCK, "BB Debug dump:\n");
764 /* Step 1a: Set bit 23 of register 0xa360 to 0 */
765 reg = REG_READ(ah, 0xa360);
767 REG_WRITE(ah, 0xa360, reg);
769 /* Step 2a: Set register 0xa364 to 0x1000 */
771 REG_WRITE(ah, 0xa364, reg);
773 /* Step 3a: Read bits 17:0 of register 0x9c20 */
774 reg = REG_READ(ah, 0x9c20);
776 ath_dbg(common, RX_STUCK,
777 "Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", reg);
779 /* Step 1b: Set bit 23 of register 0xa360 to 0 */
780 reg = REG_READ(ah, 0xa360);
782 REG_WRITE(ah, 0xa360, reg);
784 /* Step 2b: Set register 0xa364 to 0x1400 */
786 REG_WRITE(ah, 0xa364, reg);
788 /* Step 3b: Read bits 17:0 of register 0x9c20 */
789 reg = REG_READ(ah, 0x9c20);
791 ath_dbg(common, RX_STUCK,
792 "Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", reg);
794 /* Step 1c: Set bit 23 of register 0xa360 to 0 */
795 reg = REG_READ(ah, 0xa360);
797 REG_WRITE(ah, 0xa360, reg);
799 /* Step 2c: Set register 0xa364 to 0x3C00 */
801 REG_WRITE(ah, 0xa364, reg);
803 /* Step 3c: Read bits 17:0 of register 0x9c20 */
804 reg = REG_READ(ah, 0x9c20);
806 ath_dbg(common, RX_STUCK,
807 "Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", reg);
809 /* Step 1d: Set bit 24 of register 0xa360 to 0 */
810 reg = REG_READ(ah, 0xa360);
812 REG_WRITE(ah, 0xa360, reg);
814 /* Step 2d: Set register 0xa364 to 0x5005D */
816 REG_WRITE(ah, 0xa364, reg);
818 /* Step 3d: Read bits 17:0 of register 0xa368 */
819 reg = REG_READ(ah, 0xa368);
821 ath_dbg(common, RX_STUCK,
822 "Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", reg);
824 /* Step 1e: Set bit 24 of register 0xa360 to 0 */
825 reg = REG_READ(ah, 0xa360);
827 REG_WRITE(ah, 0xa360, reg);
829 /* Step 2e: Set register 0xa364 to 0x7005D */
831 REG_WRITE(ah, 0xa364, reg);
833 /* Step 3e: Read bits 17:0 of register 0xa368 */
834 reg = REG_READ(ah, 0xa368);
836 ath_dbg(common, RX_STUCK,
837 "Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", reg);
839 /* Step 1f: Set bit 24 of register 0xa360 to 0 */
840 reg = REG_READ(ah, 0xa360);
843 REG_WRITE(ah, 0xa360, reg);
845 /* Step 2f: Set register 0xa364 to 0x3005D */
847 REG_WRITE(ah, 0xa364, reg);
849 /* Step 3f: Read bits 17:0 of register 0xa368 */
850 reg = REG_READ(ah, 0xa368);
852 ath_dbg(common, RX_STUCK,
853 "Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", reg);
855 /* Step 1g: Set bit 24 of register 0xa360 to 0 */
856 reg = REG_READ(ah, 0xa360);
859 REG_WRITE(ah, 0xa360, reg);
861 /* Step 2g: Set register 0xa364 to 0x6005D */
863 REG_WRITE(ah, 0xa364, reg);
865 /* Step 3g: Read bits 17:0 of register 0xa368 */
866 reg = REG_READ(ah, 0xa368);
868 ath_dbg(common, RX_STUCK,
869 "Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", reg);
871 ar9003_hw_dump_ani_reg(ah);
873 ath_dbg(common, RX_STUCK,
874 "%8s: %10u\n", "RXLP", sc->debug.stats.istats.rxlp);
875 ath_dbg(common, RX_STUCK,
876 "%8s: %10u\n", "RXHP", sc->debug.stats.istats.rxhp);
877 ath_dbg(common, RX_STUCK,
878 "%8s: %10u\n", "WATCHDOG",
879 sc->debug.stats.istats.bb_watchdog);
880 ath_dbg(common, RX_STUCK,
881 "%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol);
882 ath_dbg(common, RX_STUCK,
883 "%8s: %10u\n", "RXORN", sc->debug.stats.istats.rxorn);
884 ath_dbg(common, RX_STUCK,
885 "%8s: %10u\n", "TX", sc->debug.stats.istats.txok);
886 ath_dbg(common, RX_STUCK,
887 "%8s: %10u\n", "TXURN", sc->debug.stats.istats.txurn);
888 ath_dbg(common, RX_STUCK,
889 "%8s: %10u\n", "MIB", sc->debug.stats.istats.mib);
890 ath_dbg(common, RX_STUCK, "%8s: %10u\n", "RXPHY",
891 sc->debug.stats.istats.rxphyerr);
892 ath_dbg(common, RX_STUCK, "%8s: %10u\n", "RXKCM",
893 sc->debug.stats.istats.rx_keycache_miss);
894 ath_dbg(common, RX_STUCK,
895 "%8s: %10u\n", "BMISS", sc->debug.stats.istats.bmiss);
896 ath_dbg(common, RX_STUCK,
897 "%8s: %10u\n", "CST", sc->debug.stats.istats.cst);
898 ath_dbg(common, RX_STUCK,
899 "%8s: %10u\n", "GTT", sc->debug.stats.istats.gtt);
901 ath_dbg(common, RX_STUCK, "Noise floor dump:\n");
902 ath_dbg(common, RX_STUCK,
903 "Channel Noise Floor : %d\n", ah->noise);
904 ath_dbg(common, RX_STUCK,
905 "Chain | privNF | # Readings | NF Readings\n");
906 for (i = 0; i < 6; i++) {
907 if (!(chainmask & (1 << i)) ||
908 ((i >= 3) && !conf_is_ht40(conf)))
911 memset(buf, 0, sizeof(buf));
913 nread = 5 - h[i].invalidNFcount;
914 for (j = 0; j < nread; j++)
915 len += snprintf(buf + len, sizeof(buf) - len,
916 "%d ", h[i].nfCalBuffer[j]);
917 ath_dbg(common, RX_STUCK, " %d\t %d\t %d\t\t %s",
918 i, h[i].privNF, nread, buf);
923 ath_dbg(common, RESET,
924 "rx clear %d match count %d iteration %d\n",
925 rx_clear, match_count, iter);
926 if (match_count++ > 15)
927 goto queue_reset_work;
928 } else if (ath9k_hw_detect_mac_hang(ah))
929 goto queue_reset_work;
930 else if (iter >= 9) {
931 iter = match_count = 0;
934 ath9k_ps_restore(sc);
935 ath_start_rx_poll(sc, nmsec);
939 ath9k_ps_restore(sc);
940 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
941 iter = match_count = 0;
944 void ath9k_tasklet(unsigned long data)
946 struct ath_softc *sc = (struct ath_softc *)data;
947 struct ath_hw *ah = sc->sc_ah;
948 struct ath_common *common = ath9k_hw_common(ah);
950 u32 status = sc->intrstatus;
954 spin_lock(&sc->sc_pcu_lock);
956 if ((status & ATH9K_INT_FATAL) ||
957 (status & ATH9K_INT_BB_WATCHDOG)) {
958 #ifdef CONFIG_ATH9K_DEBUGFS
959 enum ath_reset_type type;
961 if (status & ATH9K_INT_FATAL)
962 type = RESET_TYPE_FATAL_INT;
964 type = RESET_TYPE_BB_WATCHDOG;
966 RESET_STAT_INC(sc, type);
968 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
973 * Only run the baseband hang check if beacons stop working in AP or
974 * IBSS mode, because it has a high false positive rate. For station
975 * mode it should not be necessary, since the upper layers will detect
976 * this through a beacon miss automatically and the following channel
977 * change will trigger a hardware reset anyway
979 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
980 !ath9k_hw_check_alive(ah))
981 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
983 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
985 * TSF sync does not look correct; remain awake to sync with
988 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
989 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
992 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
993 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
996 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
998 if (status & rxmask) {
999 /* Check for high priority Rx first */
1000 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
1001 (status & ATH9K_INT_RXHP))
1002 ath_rx_tasklet(sc, 0, true);
1004 ath_rx_tasklet(sc, 0, false);
1007 if (status & ATH9K_INT_TX) {
1008 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1009 ath_tx_edma_tasklet(sc);
1014 ath9k_btcoex_handle_interrupt(sc, status);
1017 /* re-enable hardware interrupt */
1018 ath9k_hw_enable_interrupts(ah);
1020 spin_unlock(&sc->sc_pcu_lock);
1021 ath9k_ps_restore(sc);
1024 irqreturn_t ath_isr(int irq, void *dev)
1026 #define SCHED_INTR ( \
1028 ATH9K_INT_BB_WATCHDOG | \
1037 ATH9K_INT_TSFOOR | \
1038 ATH9K_INT_GENTIMER | \
1041 struct ath_softc *sc = dev;
1042 struct ath_hw *ah = sc->sc_ah;
1043 struct ath_common *common = ath9k_hw_common(ah);
1044 enum ath9k_int status;
1048 * The hardware is not ready/present, don't
1049 * touch anything. Note this can happen early
1050 * on if the IRQ is shared.
1052 if (sc->sc_flags & SC_OP_INVALID)
1056 /* shared irq, not for us */
1058 if (!ath9k_hw_intrpend(ah))
1062 * Figure out the reason(s) for the interrupt. Note
1063 * that the hal returns a pseudo-ISR that may include
1064 * bits we haven't explicitly enabled so we mask the
1065 * value to insure we only process bits we requested.
1067 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
1068 status &= ah->imask; /* discard unasked-for bits */
1071 * If there are no status bits set, then this interrupt was not
1072 * for me (should have been caught above).
1077 /* Cache the status */
1078 sc->intrstatus = status;
1080 if (status & SCHED_INTR)
1084 * If a FATAL or RXORN interrupt is received, we have to reset the
1087 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
1088 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
1091 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
1092 (status & ATH9K_INT_BB_WATCHDOG)) {
1094 spin_lock(&common->cc_lock);
1095 ath_hw_cycle_counters_update(common);
1096 ar9003_hw_bb_watchdog_dbg_info(ah);
1097 spin_unlock(&common->cc_lock);
1102 if (status & ATH9K_INT_SWBA)
1103 tasklet_schedule(&sc->bcon_tasklet);
1105 if (status & ATH9K_INT_TXURN)
1106 ath9k_hw_updatetxtriglevel(ah, true);
1108 if (status & ATH9K_INT_RXEOL) {
1109 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1110 ath9k_hw_set_interrupts(ah);
1113 if (status & ATH9K_INT_MIB) {
1115 * Disable interrupts until we service the MIB
1116 * interrupt; otherwise it will continue to
1119 ath9k_hw_disable_interrupts(ah);
1121 * Let the hal handle the event. We assume
1122 * it will clear whatever condition caused
1125 spin_lock(&common->cc_lock);
1126 ath9k_hw_proc_mib_event(ah);
1127 spin_unlock(&common->cc_lock);
1128 ath9k_hw_enable_interrupts(ah);
1131 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1132 if (status & ATH9K_INT_TIM_TIMER) {
1133 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
1135 /* Clear RxAbort bit so that we can
1137 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1138 ath9k_hw_setrxabort(sc->sc_ah, 0);
1139 sc->ps_flags |= PS_WAIT_FOR_BEACON;
1144 ath_debug_stat_interrupt(sc, status);
1147 /* turn off every interrupt */
1148 ath9k_hw_disable_interrupts(ah);
1149 tasklet_schedule(&sc->intr_tq);
1157 static int ath_reset(struct ath_softc *sc, bool retry_tx)
1159 struct ath_hw *ah = sc->sc_ah;
1160 struct ath_common *common = ath9k_hw_common(ah);
1163 sc->hw_busy_count = 0;
1165 ath9k_debug_samp_bb_mac(sc);
1167 del_timer_sync(&common->ani.timer);
1168 del_timer_sync(&sc->rx_poll_timer);
1170 ath9k_ps_wakeup(sc);
1172 ieee80211_stop_queues(sc->hw);
1174 ath9k_hw_disable_interrupts(ah);
1175 ath_drain_all_txq(sc, retry_tx);
1180 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
1183 "Unable to reset hardware; reset status %d\n", r);
1185 if (ath_startrecv(sc) != 0)
1186 ath_err(common, "Unable to start recv logic\n");
1189 * We may be doing a reset in response to a request
1190 * that changes the channel so update any state that
1191 * might change as a result.
1193 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1194 sc->config.txpowlimit, &sc->curtxpow);
1196 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
1197 ath_set_beacon(sc); /* restart beacons */
1199 ath_start_rx_poll(sc, 300);
1200 ath9k_hw_set_interrupts(ah);
1201 ath9k_hw_enable_interrupts(ah);
1205 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1206 if (ATH_TXQ_SETUP(sc, i)) {
1207 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1208 ath_txq_schedule(sc, &sc->tx.txq[i]);
1209 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1214 ath9k_ps_restore(sc);
1219 void ath_reset_work(struct work_struct *work)
1221 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
1223 ath_reset(sc, true);
1226 void ath_hw_check(struct work_struct *work)
1228 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
1229 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1230 unsigned long flags;
1233 ath9k_ps_wakeup(sc);
1234 if (ath9k_hw_check_alive(sc->sc_ah))
1237 spin_lock_irqsave(&common->cc_lock, flags);
1238 busy = ath_update_survey_stats(sc);
1239 spin_unlock_irqrestore(&common->cc_lock, flags);
1241 ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
1242 busy, sc->hw_busy_count + 1);
1244 if (++sc->hw_busy_count >= 3) {
1245 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
1246 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
1249 } else if (busy >= 0)
1250 sc->hw_busy_count = 0;
1253 ath9k_ps_restore(sc);
1256 static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
1259 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1261 if (pll_sqsum >= 0x40000) {
1264 /* Rx is hung for more than 500ms. Reset it */
1265 ath_dbg(common, RESET, "Possible RX hang, resetting\n");
1266 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
1267 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
1274 void ath_hw_pll_work(struct work_struct *work)
1276 struct ath_softc *sc = container_of(work, struct ath_softc,
1280 if (AR_SREV_9485(sc->sc_ah)) {
1282 ath9k_ps_wakeup(sc);
1283 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
1284 ath9k_ps_restore(sc);
1286 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
1288 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
1292 /**********************/
1293 /* mac80211 callbacks */
1294 /**********************/
1296 static int ath9k_start(struct ieee80211_hw *hw)
1298 struct ath_softc *sc = hw->priv;
1299 struct ath_hw *ah = sc->sc_ah;
1300 struct ath_common *common = ath9k_hw_common(ah);
1301 struct ieee80211_channel *curchan = hw->conf.channel;
1302 struct ath9k_channel *init_channel;
1305 ath_dbg(common, CONFIG,
1306 "Starting driver with initial channel: %d MHz\n",
1307 curchan->center_freq);
1309 ath9k_ps_wakeup(sc);
1310 mutex_lock(&sc->mutex);
1312 init_channel = ath9k_cmn_get_curchannel(hw, ah);
1314 /* Reset SERDES registers */
1315 ath9k_hw_configpcipowersave(ah, false);
1318 * The basic interface to setting the hardware in a good
1319 * state is ``reset''. On return the hardware is known to
1320 * be powered up and with interrupts disabled. This must
1321 * be followed by initialization of the appropriate bits
1322 * and then setup of the interrupt mask.
1324 spin_lock_bh(&sc->sc_pcu_lock);
1326 atomic_set(&ah->intr_ref_cnt, -1);
1328 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
1331 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1332 r, curchan->center_freq);
1333 spin_unlock_bh(&sc->sc_pcu_lock);
1337 /* Setup our intr mask. */
1338 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1339 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1342 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1343 ah->imask |= ATH9K_INT_RXHP |
1345 ATH9K_INT_BB_WATCHDOG;
1347 ah->imask |= ATH9K_INT_RX;
1349 ah->imask |= ATH9K_INT_GTT;
1351 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1352 ah->imask |= ATH9K_INT_CST;
1354 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1355 ah->imask |= ATH9K_INT_MCI;
1357 sc->sc_flags &= ~SC_OP_INVALID;
1358 sc->sc_ah->is_monitoring = false;
1360 if (!ath_complete_reset(sc, false)) {
1362 spin_unlock_bh(&sc->sc_pcu_lock);
1366 if (ah->led_pin >= 0) {
1367 ath9k_hw_cfg_output(ah, ah->led_pin,
1368 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1369 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1373 * Reset key cache to sane defaults (all entries cleared) instead of
1374 * semi-random values after suspend/resume.
1376 ath9k_cmn_init_crypto(sc->sc_ah);
1378 spin_unlock_bh(&sc->sc_pcu_lock);
1380 ath9k_start_btcoex(sc);
1382 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1383 common->bus_ops->extn_synch_en(common);
1386 mutex_unlock(&sc->mutex);
1388 ath9k_ps_restore(sc);
1393 static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1395 struct ath_softc *sc = hw->priv;
1396 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1397 struct ath_tx_control txctl;
1398 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1400 if (sc->ps_enabled) {
1402 * mac80211 does not set PM field for normal data frames, so we
1403 * need to update that based on the current PS mode.
1405 if (ieee80211_is_data(hdr->frame_control) &&
1406 !ieee80211_is_nullfunc(hdr->frame_control) &&
1407 !ieee80211_has_pm(hdr->frame_control)) {
1409 "Add PM=1 for a TX frame while in PS mode\n");
1410 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1415 * Cannot tx while the hardware is in full sleep, it first needs a full
1416 * chip reset to recover from that
1418 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP))
1421 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1423 * We are using PS-Poll and mac80211 can request TX while in
1424 * power save mode. Need to wake up hardware for the TX to be
1425 * completed and if needed, also for RX of buffered frames.
1427 ath9k_ps_wakeup(sc);
1428 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1429 ath9k_hw_setrxabort(sc->sc_ah, 0);
1430 if (ieee80211_is_pspoll(hdr->frame_control)) {
1432 "Sending PS-Poll to pick a buffered frame\n");
1433 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
1435 ath_dbg(common, PS, "Wake up to complete TX\n");
1436 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
1439 * The actual restore operation will happen only after
1440 * the sc_flags bit is cleared. We are just dropping
1441 * the ps_usecount here.
1443 ath9k_ps_restore(sc);
1446 memset(&txctl, 0, sizeof(struct ath_tx_control));
1447 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
1449 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
1451 if (ath_tx_start(hw, skb, &txctl) != 0) {
1452 ath_dbg(common, XMIT, "TX failed\n");
1458 dev_kfree_skb_any(skb);
1461 static void ath9k_stop(struct ieee80211_hw *hw)
1463 struct ath_softc *sc = hw->priv;
1464 struct ath_hw *ah = sc->sc_ah;
1465 struct ath_common *common = ath9k_hw_common(ah);
1468 mutex_lock(&sc->mutex);
1470 ath_cancel_work(sc);
1472 if (sc->sc_flags & SC_OP_INVALID) {
1473 ath_dbg(common, ANY, "Device not present\n");
1474 mutex_unlock(&sc->mutex);
1478 /* Ensure HW is awake when we try to shut it down. */
1479 ath9k_ps_wakeup(sc);
1481 ath9k_stop_btcoex(sc);
1483 spin_lock_bh(&sc->sc_pcu_lock);
1485 /* prevent tasklets to enable interrupts once we disable them */
1486 ah->imask &= ~ATH9K_INT_GLOBAL;
1488 /* make sure h/w will not generate any interrupt
1489 * before setting the invalid flag. */
1490 ath9k_hw_disable_interrupts(ah);
1492 spin_unlock_bh(&sc->sc_pcu_lock);
1494 /* we can now sync irq and kill any running tasklets, since we already
1495 * disabled interrupts and not holding a spin lock */
1496 synchronize_irq(sc->irq);
1497 tasklet_kill(&sc->intr_tq);
1498 tasklet_kill(&sc->bcon_tasklet);
1500 prev_idle = sc->ps_idle;
1503 spin_lock_bh(&sc->sc_pcu_lock);
1505 if (ah->led_pin >= 0) {
1506 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1507 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1510 ath_prepare_reset(sc, false, true);
1513 dev_kfree_skb_any(sc->rx.frag);
1518 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
1520 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
1521 ath9k_hw_phy_disable(ah);
1523 ath9k_hw_configpcipowersave(ah, true);
1525 spin_unlock_bh(&sc->sc_pcu_lock);
1527 ath9k_ps_restore(sc);
1529 sc->sc_flags |= SC_OP_INVALID;
1530 sc->ps_idle = prev_idle;
1532 mutex_unlock(&sc->mutex);
1534 ath_dbg(common, CONFIG, "Driver halt\n");
1537 bool ath9k_uses_beacons(int type)
1540 case NL80211_IFTYPE_AP:
1541 case NL80211_IFTYPE_ADHOC:
1542 case NL80211_IFTYPE_MESH_POINT:
1549 static void ath9k_reclaim_beacon(struct ath_softc *sc,
1550 struct ieee80211_vif *vif)
1552 struct ath_vif *avp = (void *)vif->drv_priv;
1554 ath9k_set_beaconing_status(sc, false);
1555 ath_beacon_return(sc, avp);
1556 ath9k_set_beaconing_status(sc, true);
1557 sc->sc_flags &= ~SC_OP_BEACONS;
1560 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1562 struct ath9k_vif_iter_data *iter_data = data;
1565 if (iter_data->hw_macaddr)
1566 for (i = 0; i < ETH_ALEN; i++)
1567 iter_data->mask[i] &=
1568 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1570 switch (vif->type) {
1571 case NL80211_IFTYPE_AP:
1574 case NL80211_IFTYPE_STATION:
1575 iter_data->nstations++;
1577 case NL80211_IFTYPE_ADHOC:
1578 iter_data->nadhocs++;
1580 case NL80211_IFTYPE_MESH_POINT:
1581 iter_data->nmeshes++;
1583 case NL80211_IFTYPE_WDS:
1591 /* Called with sc->mutex held. */
1592 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1593 struct ieee80211_vif *vif,
1594 struct ath9k_vif_iter_data *iter_data)
1596 struct ath_softc *sc = hw->priv;
1597 struct ath_hw *ah = sc->sc_ah;
1598 struct ath_common *common = ath9k_hw_common(ah);
1601 * Use the hardware MAC address as reference, the hardware uses it
1602 * together with the BSSID mask when matching addresses.
1604 memset(iter_data, 0, sizeof(*iter_data));
1605 iter_data->hw_macaddr = common->macaddr;
1606 memset(&iter_data->mask, 0xff, ETH_ALEN);
1609 ath9k_vif_iter(iter_data, vif->addr, vif);
1611 /* Get list of all active MAC addresses */
1612 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1616 /* Called with sc->mutex held. */
1617 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1618 struct ieee80211_vif *vif)
1620 struct ath_softc *sc = hw->priv;
1621 struct ath_hw *ah = sc->sc_ah;
1622 struct ath_common *common = ath9k_hw_common(ah);
1623 struct ath9k_vif_iter_data iter_data;
1625 ath9k_calculate_iter_data(hw, vif, &iter_data);
1627 /* Set BSSID mask. */
1628 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1629 ath_hw_setbssidmask(common);
1631 /* Set op-mode & TSF */
1632 if (iter_data.naps > 0) {
1633 ath9k_hw_set_tsfadjust(ah, 1);
1634 sc->sc_flags |= SC_OP_TSF_RESET;
1635 ah->opmode = NL80211_IFTYPE_AP;
1637 ath9k_hw_set_tsfadjust(ah, 0);
1638 sc->sc_flags &= ~SC_OP_TSF_RESET;
1640 if (iter_data.nmeshes)
1641 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1642 else if (iter_data.nwds)
1643 ah->opmode = NL80211_IFTYPE_AP;
1644 else if (iter_data.nadhocs)
1645 ah->opmode = NL80211_IFTYPE_ADHOC;
1647 ah->opmode = NL80211_IFTYPE_STATION;
1651 * Enable MIB interrupts when there are hardware phy counters.
1653 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
1654 if (ah->config.enable_ani)
1655 ah->imask |= ATH9K_INT_MIB;
1656 ah->imask |= ATH9K_INT_TSFOOR;
1658 ah->imask &= ~ATH9K_INT_MIB;
1659 ah->imask &= ~ATH9K_INT_TSFOOR;
1662 ath9k_hw_set_interrupts(ah);
1665 if (iter_data.naps > 0) {
1666 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1668 if (!common->disable_ani) {
1669 sc->sc_flags |= SC_OP_ANI_RUN;
1670 ath_start_ani(common);
1674 sc->sc_flags &= ~SC_OP_ANI_RUN;
1675 del_timer_sync(&common->ani.timer);
1679 /* Called with sc->mutex held, vif counts set up properly. */
1680 static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1681 struct ieee80211_vif *vif)
1683 struct ath_softc *sc = hw->priv;
1685 ath9k_calculate_summary_state(hw, vif);
1687 if (ath9k_uses_beacons(vif->type)) {
1689 /* This may fail because upper levels do not have beacons
1690 * properly configured yet. That's OK, we assume it
1691 * will be properly configured and then we will be notified
1692 * in the info_changed method and set up beacons properly
1695 ath9k_set_beaconing_status(sc, false);
1696 error = ath_beacon_alloc(sc, vif);
1698 ath_beacon_config(sc, vif);
1699 ath9k_set_beaconing_status(sc, true);
1704 static int ath9k_add_interface(struct ieee80211_hw *hw,
1705 struct ieee80211_vif *vif)
1707 struct ath_softc *sc = hw->priv;
1708 struct ath_hw *ah = sc->sc_ah;
1709 struct ath_common *common = ath9k_hw_common(ah);
1712 ath9k_ps_wakeup(sc);
1713 mutex_lock(&sc->mutex);
1715 switch (vif->type) {
1716 case NL80211_IFTYPE_STATION:
1717 case NL80211_IFTYPE_WDS:
1718 case NL80211_IFTYPE_ADHOC:
1719 case NL80211_IFTYPE_AP:
1720 case NL80211_IFTYPE_MESH_POINT:
1723 ath_err(common, "Interface type %d not yet supported\n",
1729 if (ath9k_uses_beacons(vif->type)) {
1730 if (sc->nbcnvifs >= ATH_BCBUF) {
1731 ath_err(common, "Not enough beacon buffers when adding"
1732 " new interface of type: %i\n",
1739 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1740 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1742 ath_err(common, "Cannot create ADHOC interface when other"
1743 " interfaces already exist.\n");
1748 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1752 ath9k_do_vif_add_setup(hw, vif);
1754 mutex_unlock(&sc->mutex);
1755 ath9k_ps_restore(sc);
1759 static int ath9k_change_interface(struct ieee80211_hw *hw,
1760 struct ieee80211_vif *vif,
1761 enum nl80211_iftype new_type,
1764 struct ath_softc *sc = hw->priv;
1765 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1768 ath_dbg(common, CONFIG, "Change Interface\n");
1769 mutex_lock(&sc->mutex);
1770 ath9k_ps_wakeup(sc);
1772 /* See if new interface type is valid. */
1773 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1775 ath_err(common, "When using ADHOC, it must be the only"
1781 if (ath9k_uses_beacons(new_type) &&
1782 !ath9k_uses_beacons(vif->type)) {
1783 if (sc->nbcnvifs >= ATH_BCBUF) {
1784 ath_err(common, "No beacon slot available\n");
1790 /* Clean up old vif stuff */
1791 if (ath9k_uses_beacons(vif->type))
1792 ath9k_reclaim_beacon(sc, vif);
1794 /* Add new settings */
1795 vif->type = new_type;
1798 ath9k_do_vif_add_setup(hw, vif);
1800 ath9k_ps_restore(sc);
1801 mutex_unlock(&sc->mutex);
1805 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1806 struct ieee80211_vif *vif)
1808 struct ath_softc *sc = hw->priv;
1809 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1811 ath_dbg(common, CONFIG, "Detach Interface\n");
1813 ath9k_ps_wakeup(sc);
1814 mutex_lock(&sc->mutex);
1818 /* Reclaim beacon resources */
1819 if (ath9k_uses_beacons(vif->type))
1820 ath9k_reclaim_beacon(sc, vif);
1822 ath9k_calculate_summary_state(hw, NULL);
1824 mutex_unlock(&sc->mutex);
1825 ath9k_ps_restore(sc);
1828 static void ath9k_enable_ps(struct ath_softc *sc)
1830 struct ath_hw *ah = sc->sc_ah;
1832 sc->ps_enabled = true;
1833 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1834 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1835 ah->imask |= ATH9K_INT_TIM_TIMER;
1836 ath9k_hw_set_interrupts(ah);
1838 ath9k_hw_setrxabort(ah, 1);
1842 static void ath9k_disable_ps(struct ath_softc *sc)
1844 struct ath_hw *ah = sc->sc_ah;
1846 sc->ps_enabled = false;
1847 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1848 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1849 ath9k_hw_setrxabort(ah, 0);
1850 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1852 PS_WAIT_FOR_PSPOLL_DATA |
1853 PS_WAIT_FOR_TX_ACK);
1854 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1855 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1856 ath9k_hw_set_interrupts(ah);
1862 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1864 struct ath_softc *sc = hw->priv;
1865 struct ath_hw *ah = sc->sc_ah;
1866 struct ath_common *common = ath9k_hw_common(ah);
1867 struct ieee80211_conf *conf = &hw->conf;
1868 bool reset_channel = false;
1870 ath9k_ps_wakeup(sc);
1871 mutex_lock(&sc->mutex);
1873 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1874 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1876 ath_cancel_work(sc);
1879 * The chip needs a reset to properly wake up from
1882 reset_channel = ah->chip_fullsleep;
1886 * We just prepare to enable PS. We have to wait until our AP has
1887 * ACK'd our null data frame to disable RX otherwise we'll ignore
1888 * those ACKs and end up retransmitting the same null data frames.
1889 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1891 if (changed & IEEE80211_CONF_CHANGE_PS) {
1892 unsigned long flags;
1893 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1894 if (conf->flags & IEEE80211_CONF_PS)
1895 ath9k_enable_ps(sc);
1897 ath9k_disable_ps(sc);
1898 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1901 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1902 if (conf->flags & IEEE80211_CONF_MONITOR) {
1903 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1904 sc->sc_ah->is_monitoring = true;
1906 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1907 sc->sc_ah->is_monitoring = false;
1911 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1912 struct ieee80211_channel *curchan = hw->conf.channel;
1913 int pos = curchan->hw_value;
1915 unsigned long flags;
1918 old_pos = ah->curchan - &ah->channels[0];
1920 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1921 sc->sc_flags |= SC_OP_OFFCHANNEL;
1923 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
1925 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1926 curchan->center_freq, conf->channel_type);
1928 /* update survey stats for the old channel before switching */
1929 spin_lock_irqsave(&common->cc_lock, flags);
1930 ath_update_survey_stats(sc);
1931 spin_unlock_irqrestore(&common->cc_lock, flags);
1934 * Preserve the current channel values, before updating
1937 if (ah->curchan && (old_pos == pos))
1938 ath9k_hw_getnf(ah, ah->curchan);
1940 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1941 curchan, conf->channel_type);
1944 * If the operating channel changes, change the survey in-use flags
1946 * Reset the survey data for the new channel, unless we're switching
1947 * back to the operating channel from an off-channel operation.
1949 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1950 sc->cur_survey != &sc->survey[pos]) {
1953 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1955 sc->cur_survey = &sc->survey[pos];
1957 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1958 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1959 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1960 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1963 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1964 ath_err(common, "Unable to set channel\n");
1965 mutex_unlock(&sc->mutex);
1970 * The most recent snapshot of channel->noisefloor for the old
1971 * channel is only available after the hardware reset. Copy it to
1972 * the survey stats now.
1975 ath_update_survey_nf(sc, old_pos);
1978 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1979 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1980 sc->config.txpowlimit = 2 * conf->power_level;
1981 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1982 sc->config.txpowlimit, &sc->curtxpow);
1985 mutex_unlock(&sc->mutex);
1986 ath9k_ps_restore(sc);
1991 #define SUPPORTED_FILTERS \
1992 (FIF_PROMISC_IN_BSS | \
1997 FIF_BCN_PRBRESP_PROMISC | \
2001 /* FIXME: sc->sc_full_reset ? */
2002 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2003 unsigned int changed_flags,
2004 unsigned int *total_flags,
2007 struct ath_softc *sc = hw->priv;
2010 changed_flags &= SUPPORTED_FILTERS;
2011 *total_flags &= SUPPORTED_FILTERS;
2013 sc->rx.rxfilter = *total_flags;
2014 ath9k_ps_wakeup(sc);
2015 rfilt = ath_calcrxfilter(sc);
2016 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2017 ath9k_ps_restore(sc);
2019 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
2023 static int ath9k_sta_add(struct ieee80211_hw *hw,
2024 struct ieee80211_vif *vif,
2025 struct ieee80211_sta *sta)
2027 struct ath_softc *sc = hw->priv;
2028 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2029 struct ath_node *an = (struct ath_node *) sta->drv_priv;
2030 struct ieee80211_key_conf ps_key = { };
2032 ath_node_attach(sc, sta, vif);
2034 if (vif->type != NL80211_IFTYPE_AP &&
2035 vif->type != NL80211_IFTYPE_AP_VLAN)
2038 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
2043 static void ath9k_del_ps_key(struct ath_softc *sc,
2044 struct ieee80211_vif *vif,
2045 struct ieee80211_sta *sta)
2047 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2048 struct ath_node *an = (struct ath_node *) sta->drv_priv;
2049 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
2054 ath_key_delete(common, &ps_key);
2057 static int ath9k_sta_remove(struct ieee80211_hw *hw,
2058 struct ieee80211_vif *vif,
2059 struct ieee80211_sta *sta)
2061 struct ath_softc *sc = hw->priv;
2063 ath9k_del_ps_key(sc, vif, sta);
2064 ath_node_detach(sc, sta);
2069 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2070 struct ieee80211_vif *vif,
2071 enum sta_notify_cmd cmd,
2072 struct ieee80211_sta *sta)
2074 struct ath_softc *sc = hw->priv;
2075 struct ath_node *an = (struct ath_node *) sta->drv_priv;
2077 if (!sta->ht_cap.ht_supported)
2081 case STA_NOTIFY_SLEEP:
2082 an->sleeping = true;
2083 ath_tx_aggr_sleep(sta, sc, an);
2085 case STA_NOTIFY_AWAKE:
2086 an->sleeping = false;
2087 ath_tx_aggr_wakeup(sc, an);
2092 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2093 struct ieee80211_vif *vif, u16 queue,
2094 const struct ieee80211_tx_queue_params *params)
2096 struct ath_softc *sc = hw->priv;
2097 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2098 struct ath_txq *txq;
2099 struct ath9k_tx_queue_info qi;
2102 if (queue >= WME_NUM_AC)
2105 txq = sc->tx.txq_map[queue];
2107 ath9k_ps_wakeup(sc);
2108 mutex_lock(&sc->mutex);
2110 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2112 qi.tqi_aifs = params->aifs;
2113 qi.tqi_cwmin = params->cw_min;
2114 qi.tqi_cwmax = params->cw_max;
2115 qi.tqi_burstTime = params->txop;
2117 ath_dbg(common, CONFIG,
2118 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2119 queue, txq->axq_qnum, params->aifs, params->cw_min,
2120 params->cw_max, params->txop);
2122 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
2124 ath_err(common, "TXQ Update failed\n");
2126 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
2127 if (queue == WME_AC_BE && !ret)
2128 ath_beaconq_config(sc);
2130 mutex_unlock(&sc->mutex);
2131 ath9k_ps_restore(sc);
2136 static int ath9k_set_key(struct ieee80211_hw *hw,
2137 enum set_key_cmd cmd,
2138 struct ieee80211_vif *vif,
2139 struct ieee80211_sta *sta,
2140 struct ieee80211_key_conf *key)
2142 struct ath_softc *sc = hw->priv;
2143 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2146 if (ath9k_modparam_nohwcrypt)
2149 if ((vif->type == NL80211_IFTYPE_ADHOC ||
2150 vif->type == NL80211_IFTYPE_MESH_POINT) &&
2151 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
2152 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
2153 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2155 * For now, disable hw crypto for the RSN IBSS group keys. This
2156 * could be optimized in the future to use a modified key cache
2157 * design to support per-STA RX GTK, but until that gets
2158 * implemented, use of software crypto for group addressed
2159 * frames is a acceptable to allow RSN IBSS to be used.
2164 mutex_lock(&sc->mutex);
2165 ath9k_ps_wakeup(sc);
2166 ath_dbg(common, CONFIG, "Set HW Key\n");
2171 ath9k_del_ps_key(sc, vif, sta);
2173 ret = ath_key_config(common, vif, sta, key);
2175 key->hw_key_idx = ret;
2176 /* push IV and Michael MIC generation to stack */
2177 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2178 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
2179 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2180 if (sc->sc_ah->sw_mgmt_crypto &&
2181 key->cipher == WLAN_CIPHER_SUITE_CCMP)
2182 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2187 ath_key_delete(common, key);
2193 ath9k_ps_restore(sc);
2194 mutex_unlock(&sc->mutex);
2198 static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
2200 struct ath_softc *sc = data;
2201 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2202 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2203 struct ath_vif *avp = (void *)vif->drv_priv;
2206 * Skip iteration if primary station vif's bss info
2209 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
2212 if (bss_conf->assoc) {
2213 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
2214 avp->primary_sta_vif = true;
2215 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2216 common->curaid = bss_conf->aid;
2217 ath9k_hw_write_associd(sc->sc_ah);
2218 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
2219 bss_conf->aid, common->curbssid);
2220 ath_beacon_config(sc, vif);
2222 * Request a re-configuration of Beacon related timers
2223 * on the receipt of the first Beacon frame (i.e.,
2224 * after time sync with the AP).
2226 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
2227 /* Reset rssi stats */
2228 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
2229 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
2231 if (!common->disable_ani) {
2232 sc->sc_flags |= SC_OP_ANI_RUN;
2233 ath_start_ani(common);
2235 ath_start_rx_poll(sc, 300);
2239 static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2241 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2242 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2243 struct ath_vif *avp = (void *)vif->drv_priv;
2245 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2248 /* Reconfigure bss info */
2249 if (avp->primary_sta_vif && !bss_conf->assoc) {
2250 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
2251 common->curaid, common->curbssid);
2252 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
2253 avp->primary_sta_vif = false;
2254 memset(common->curbssid, 0, ETH_ALEN);
2258 ieee80211_iterate_active_interfaces_atomic(
2259 sc->hw, ath9k_bss_iter, sc);
2262 * None of station vifs are associated.
2265 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
2266 ath9k_hw_write_associd(sc->sc_ah);
2268 sc->sc_flags &= ~SC_OP_ANI_RUN;
2269 del_timer_sync(&common->ani.timer);
2270 del_timer_sync(&sc->rx_poll_timer);
2271 memset(&sc->caldata, 0, sizeof(sc->caldata));
2275 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2276 struct ieee80211_vif *vif,
2277 struct ieee80211_bss_conf *bss_conf,
2280 struct ath_softc *sc = hw->priv;
2281 struct ath_hw *ah = sc->sc_ah;
2282 struct ath_common *common = ath9k_hw_common(ah);
2283 struct ath_vif *avp = (void *)vif->drv_priv;
2287 ath9k_ps_wakeup(sc);
2288 mutex_lock(&sc->mutex);
2290 if (changed & BSS_CHANGED_ASSOC) {
2291 ath9k_config_bss(sc, vif);
2293 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
2294 common->curbssid, common->curaid);
2297 if (changed & BSS_CHANGED_IBSS) {
2298 /* There can be only one vif available */
2299 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2300 common->curaid = bss_conf->aid;
2301 ath9k_hw_write_associd(sc->sc_ah);
2303 if (bss_conf->ibss_joined) {
2304 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
2306 if (!common->disable_ani) {
2307 sc->sc_flags |= SC_OP_ANI_RUN;
2308 ath_start_ani(common);
2312 sc->sc_flags &= ~SC_OP_ANI_RUN;
2313 del_timer_sync(&common->ani.timer);
2317 /* Enable transmission of beacons (AP, IBSS, MESH) */
2318 if ((changed & BSS_CHANGED_BEACON) ||
2319 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2320 ath9k_set_beaconing_status(sc, false);
2321 error = ath_beacon_alloc(sc, vif);
2323 ath_beacon_config(sc, vif);
2324 ath9k_set_beaconing_status(sc, true);
2327 if (changed & BSS_CHANGED_ERP_SLOT) {
2328 if (bss_conf->use_short_slot)
2332 if (vif->type == NL80211_IFTYPE_AP) {
2334 * Defer update, so that connected stations can adjust
2335 * their settings at the same time.
2336 * See beacon.c for more details
2338 sc->beacon.slottime = slottime;
2339 sc->beacon.updateslot = UPDATE;
2341 ah->slottime = slottime;
2342 ath9k_hw_init_global_settings(ah);
2346 /* Disable transmission of beacons */
2347 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2348 !bss_conf->enable_beacon) {
2349 ath9k_set_beaconing_status(sc, false);
2350 avp->is_bslot_active = false;
2351 ath9k_set_beaconing_status(sc, true);
2354 if (changed & BSS_CHANGED_BEACON_INT) {
2356 * In case of AP mode, the HW TSF has to be reset
2357 * when the beacon interval changes.
2359 if (vif->type == NL80211_IFTYPE_AP) {
2360 sc->sc_flags |= SC_OP_TSF_RESET;
2361 ath9k_set_beaconing_status(sc, false);
2362 error = ath_beacon_alloc(sc, vif);
2364 ath_beacon_config(sc, vif);
2365 ath9k_set_beaconing_status(sc, true);
2367 ath_beacon_config(sc, vif);
2370 mutex_unlock(&sc->mutex);
2371 ath9k_ps_restore(sc);
2374 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2376 struct ath_softc *sc = hw->priv;
2379 mutex_lock(&sc->mutex);
2380 ath9k_ps_wakeup(sc);
2381 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2382 ath9k_ps_restore(sc);
2383 mutex_unlock(&sc->mutex);
2388 static void ath9k_set_tsf(struct ieee80211_hw *hw,
2389 struct ieee80211_vif *vif,
2392 struct ath_softc *sc = hw->priv;
2394 mutex_lock(&sc->mutex);
2395 ath9k_ps_wakeup(sc);
2396 ath9k_hw_settsf64(sc->sc_ah, tsf);
2397 ath9k_ps_restore(sc);
2398 mutex_unlock(&sc->mutex);
2401 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2403 struct ath_softc *sc = hw->priv;
2405 mutex_lock(&sc->mutex);
2407 ath9k_ps_wakeup(sc);
2408 ath9k_hw_reset_tsf(sc->sc_ah);
2409 ath9k_ps_restore(sc);
2411 mutex_unlock(&sc->mutex);
2414 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2415 struct ieee80211_vif *vif,
2416 enum ieee80211_ampdu_mlme_action action,
2417 struct ieee80211_sta *sta,
2418 u16 tid, u16 *ssn, u8 buf_size)
2420 struct ath_softc *sc = hw->priv;
2426 case IEEE80211_AMPDU_RX_START:
2428 case IEEE80211_AMPDU_RX_STOP:
2430 case IEEE80211_AMPDU_TX_START:
2431 ath9k_ps_wakeup(sc);
2432 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2434 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2435 ath9k_ps_restore(sc);
2437 case IEEE80211_AMPDU_TX_STOP:
2438 ath9k_ps_wakeup(sc);
2439 ath_tx_aggr_stop(sc, sta, tid);
2440 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2441 ath9k_ps_restore(sc);
2443 case IEEE80211_AMPDU_TX_OPERATIONAL:
2444 ath9k_ps_wakeup(sc);
2445 ath_tx_aggr_resume(sc, sta, tid);
2446 ath9k_ps_restore(sc);
2449 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2457 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2458 struct survey_info *survey)
2460 struct ath_softc *sc = hw->priv;
2461 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2462 struct ieee80211_supported_band *sband;
2463 struct ieee80211_channel *chan;
2464 unsigned long flags;
2467 spin_lock_irqsave(&common->cc_lock, flags);
2469 ath_update_survey_stats(sc);
2471 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2472 if (sband && idx >= sband->n_channels) {
2473 idx -= sband->n_channels;
2478 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
2480 if (!sband || idx >= sband->n_channels) {
2481 spin_unlock_irqrestore(&common->cc_lock, flags);
2485 chan = &sband->channels[idx];
2486 pos = chan->hw_value;
2487 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2488 survey->channel = chan;
2489 spin_unlock_irqrestore(&common->cc_lock, flags);
2494 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2496 struct ath_softc *sc = hw->priv;
2497 struct ath_hw *ah = sc->sc_ah;
2499 mutex_lock(&sc->mutex);
2500 ah->coverage_class = coverage_class;
2502 ath9k_ps_wakeup(sc);
2503 ath9k_hw_init_global_settings(ah);
2504 ath9k_ps_restore(sc);
2506 mutex_unlock(&sc->mutex);
2509 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2511 struct ath_softc *sc = hw->priv;
2512 struct ath_hw *ah = sc->sc_ah;
2513 struct ath_common *common = ath9k_hw_common(ah);
2514 int timeout = 200; /* ms */
2518 mutex_lock(&sc->mutex);
2519 cancel_delayed_work_sync(&sc->tx_complete_work);
2521 if (ah->ah_flags & AH_UNPLUGGED) {
2522 ath_dbg(common, ANY, "Device has been unplugged!\n");
2523 mutex_unlock(&sc->mutex);
2527 if (sc->sc_flags & SC_OP_INVALID) {
2528 ath_dbg(common, ANY, "Device not present\n");
2529 mutex_unlock(&sc->mutex);
2533 for (j = 0; j < timeout; j++) {
2537 usleep_range(1000, 2000);
2539 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2540 if (!ATH_TXQ_SETUP(sc, i))
2543 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2554 ath9k_ps_wakeup(sc);
2555 spin_lock_bh(&sc->sc_pcu_lock);
2556 drain_txq = ath_drain_all_txq(sc, false);
2557 spin_unlock_bh(&sc->sc_pcu_lock);
2560 ath_reset(sc, false);
2562 ath9k_ps_restore(sc);
2563 ieee80211_wake_queues(hw);
2566 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2567 mutex_unlock(&sc->mutex);
2570 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2572 struct ath_softc *sc = hw->priv;
2575 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2576 if (!ATH_TXQ_SETUP(sc, i))
2579 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2585 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2587 struct ath_softc *sc = hw->priv;
2588 struct ath_hw *ah = sc->sc_ah;
2589 struct ieee80211_vif *vif;
2590 struct ath_vif *avp;
2592 struct ath_tx_status ts;
2593 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2596 vif = sc->beacon.bslot[0];
2600 avp = (void *)vif->drv_priv;
2601 if (!avp->is_bslot_active)
2604 if (!sc->beacon.tx_processed && !edma) {
2605 tasklet_disable(&sc->bcon_tasklet);
2608 if (!bf || !bf->bf_mpdu)
2611 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2612 if (status == -EINPROGRESS)
2615 sc->beacon.tx_processed = true;
2616 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2619 tasklet_enable(&sc->bcon_tasklet);
2622 return sc->beacon.tx_last;
2625 static int ath9k_get_stats(struct ieee80211_hw *hw,
2626 struct ieee80211_low_level_stats *stats)
2628 struct ath_softc *sc = hw->priv;
2629 struct ath_hw *ah = sc->sc_ah;
2630 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2632 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2633 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2634 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2635 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2639 static u32 fill_chainmask(u32 cap, u32 new)
2644 for (i = 0; cap && new; i++, cap >>= 1) {
2645 if (!(cap & BIT(0)))
2657 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2659 struct ath_softc *sc = hw->priv;
2660 struct ath_hw *ah = sc->sc_ah;
2662 if (!rx_ant || !tx_ant)
2665 sc->ant_rx = rx_ant;
2666 sc->ant_tx = tx_ant;
2668 if (ah->caps.rx_chainmask == 1)
2671 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2672 if (AR_SREV_9100(ah))
2673 ah->rxchainmask = 0x7;
2675 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2677 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2678 ath9k_reload_chainmask_settings(sc);
2683 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2685 struct ath_softc *sc = hw->priv;
2687 *tx_ant = sc->ant_tx;
2688 *rx_ant = sc->ant_rx;
2692 struct ieee80211_ops ath9k_ops = {
2694 .start = ath9k_start,
2696 .add_interface = ath9k_add_interface,
2697 .change_interface = ath9k_change_interface,
2698 .remove_interface = ath9k_remove_interface,
2699 .config = ath9k_config,
2700 .configure_filter = ath9k_configure_filter,
2701 .sta_add = ath9k_sta_add,
2702 .sta_remove = ath9k_sta_remove,
2703 .sta_notify = ath9k_sta_notify,
2704 .conf_tx = ath9k_conf_tx,
2705 .bss_info_changed = ath9k_bss_info_changed,
2706 .set_key = ath9k_set_key,
2707 .get_tsf = ath9k_get_tsf,
2708 .set_tsf = ath9k_set_tsf,
2709 .reset_tsf = ath9k_reset_tsf,
2710 .ampdu_action = ath9k_ampdu_action,
2711 .get_survey = ath9k_get_survey,
2712 .rfkill_poll = ath9k_rfkill_poll_state,
2713 .set_coverage_class = ath9k_set_coverage_class,
2714 .flush = ath9k_flush,
2715 .tx_frames_pending = ath9k_tx_frames_pending,
2716 .tx_last_beacon = ath9k_tx_last_beacon,
2717 .get_stats = ath9k_get_stats,
2718 .set_antenna = ath9k_set_antenna,
2719 .get_antenna = ath9k_get_antenna,