2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
22 static u8 parse_mpdudensity(u8 mpdudensity)
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
35 switch (mpdudensity) {
41 /* Our lower layer calculations limit our precision to
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61 spin_lock_bh(&txq->axq_lock);
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
66 spin_unlock_bh(&txq->axq_lock);
70 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
82 void ath9k_ps_wakeup(struct ath_softc *sc)
84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
86 enum ath9k_power_mode power_mode;
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
92 power_mode = sc->sc_ah->power_mode;
93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
111 void ath9k_ps_restore(struct ath_softc *sc)
113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
114 enum ath9k_power_mode mode;
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 if (--sc->ps_usecount != 0)
121 if (sc->ps_idle && (sc->ps_flags & PS_WAIT_FOR_TX_ACK))
122 mode = ATH9K_PM_FULL_SLEEP;
123 else if (sc->ps_enabled &&
124 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
126 PS_WAIT_FOR_PSPOLL_DATA |
127 PS_WAIT_FOR_TX_ACK)))
128 mode = ATH9K_PM_NETWORK_SLEEP;
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 spin_unlock(&common->cc_lock);
136 ath9k_hw_setpower(sc->sc_ah, mode);
139 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
142 void ath_start_ani(struct ath_common *common)
144 struct ath_hw *ah = common->ah;
145 unsigned long timestamp = jiffies_to_msecs(jiffies);
146 struct ath_softc *sc = (struct ath_softc *) common->priv;
148 if (!(sc->sc_flags & SC_OP_ANI_RUN))
151 if (sc->sc_flags & SC_OP_OFFCHANNEL)
154 common->ani.longcal_timer = timestamp;
155 common->ani.shortcal_timer = timestamp;
156 common->ani.checkani_timer = timestamp;
158 mod_timer(&common->ani.timer,
160 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
163 static void ath_update_survey_nf(struct ath_softc *sc, int channel)
165 struct ath_hw *ah = sc->sc_ah;
166 struct ath9k_channel *chan = &ah->channels[channel];
167 struct survey_info *survey = &sc->survey[channel];
169 if (chan->noisefloor) {
170 survey->filled |= SURVEY_INFO_NOISE_DBM;
171 survey->noise = ath9k_hw_getchan_noise(ah, chan);
176 * Updates the survey statistics and returns the busy time since last
177 * update in %, if the measurement duration was long enough for the
178 * result to be useful, -1 otherwise.
180 static int ath_update_survey_stats(struct ath_softc *sc)
182 struct ath_hw *ah = sc->sc_ah;
183 struct ath_common *common = ath9k_hw_common(ah);
184 int pos = ah->curchan - &ah->channels[0];
185 struct survey_info *survey = &sc->survey[pos];
186 struct ath_cycle_counters *cc = &common->cc_survey;
187 unsigned int div = common->clockrate * 1000;
193 if (ah->power_mode == ATH9K_PM_AWAKE)
194 ath_hw_cycle_counters_update(common);
196 if (cc->cycles > 0) {
197 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
198 SURVEY_INFO_CHANNEL_TIME_BUSY |
199 SURVEY_INFO_CHANNEL_TIME_RX |
200 SURVEY_INFO_CHANNEL_TIME_TX;
201 survey->channel_time += cc->cycles / div;
202 survey->channel_time_busy += cc->rx_busy / div;
203 survey->channel_time_rx += cc->rx_frame / div;
204 survey->channel_time_tx += cc->tx_frame / div;
207 if (cc->cycles < div)
211 ret = cc->rx_busy * 100 / cc->cycles;
213 memset(cc, 0, sizeof(*cc));
215 ath_update_survey_nf(sc, pos);
220 static void __ath_cancel_work(struct ath_softc *sc)
222 struct ath_hw *ah = sc->sc_ah;
223 struct ath_common *common = ath9k_hw_common(ah);
225 if (sc->sc_flags & SC_OP_INVALID)
228 sc->hw_busy_count = 0;
230 del_timer_sync(&common->ani.timer);
231 del_timer_sync(&sc->rx_poll_timer);
232 cancel_work_sync(&sc->paprd_work);
233 cancel_work_sync(&sc->hw_check_work);
234 cancel_work_sync(&sc->hw_reset_work);
235 cancel_delayed_work_sync(&sc->tx_complete_work);
236 cancel_delayed_work_sync(&sc->hw_pll_work);
239 static void ath_cancel_work(struct ath_softc *sc)
241 __ath_cancel_work(sc);
244 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
246 struct ath_hw *ah = sc->sc_ah;
247 struct ath_common *common = ath9k_hw_common(ah);
250 ieee80211_stop_queues(sc->hw);
252 sc->hw_busy_count = 0;
253 del_timer_sync(&common->ani.timer);
255 ath9k_debug_samp_bb_mac(sc);
256 ath9k_hw_disable_interrupts(ah);
258 ret = ath_drain_all_txq(sc, retry_tx);
260 if (!ath_stoprecv(sc))
264 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
265 ath_rx_tasklet(sc, 1, true);
266 ath_rx_tasklet(sc, 1, false);
274 static bool ath_complete_reset(struct ath_softc *sc, bool start)
276 struct ath_hw *ah = sc->sc_ah;
277 struct ath_common *common = ath9k_hw_common(ah);
279 if (ath_startrecv(sc) != 0) {
280 ath_err(common, "Unable to restart recv logic\n");
284 ath9k_cmn_update_txpow(ah, sc->curtxpow,
285 sc->config.txpowlimit, &sc->curtxpow);
286 ath9k_hw_set_interrupts(ah);
287 ath9k_hw_enable_interrupts(ah);
289 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
290 if (sc->sc_flags & SC_OP_BEACONS)
293 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
294 mod_timer(&sc->rx_poll_timer,
295 jiffies + msecs_to_jiffies(10));
296 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
297 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
298 if (!common->disable_ani)
299 ath_start_ani(common);
302 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
303 struct ath_hw_antcomb_conf div_ant_conf;
306 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
309 lna_conf = ATH_ANT_DIV_COMB_LNA1;
311 lna_conf = ATH_ANT_DIV_COMB_LNA2;
312 div_ant_conf.main_lna_conf = lna_conf;
313 div_ant_conf.alt_lna_conf = lna_conf;
315 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
318 ieee80211_wake_queues(sc->hw);
323 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
326 struct ath_hw *ah = sc->sc_ah;
327 struct ath_common *common = ath9k_hw_common(ah);
328 struct ath9k_hw_cal_data *caldata = NULL;
333 __ath_cancel_work(sc);
335 spin_lock_bh(&sc->sc_pcu_lock);
337 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
339 caldata = &sc->caldata;
348 if (!ath_prepare_reset(sc, retry_tx, flush))
351 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
352 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
354 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
357 "Unable to reset channel, reset status %d\n", r);
361 if (!ath_complete_reset(sc, true))
365 spin_unlock_bh(&sc->sc_pcu_lock);
371 * Set/change channels. If the channel is really being changed, it's done
372 * by reseting the chip. To accomplish this we must first cleanup any pending
373 * DMA, then restart stuff.
375 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
376 struct ath9k_channel *hchan)
380 if (sc->sc_flags & SC_OP_INVALID)
383 r = ath_reset_internal(sc, hchan, false);
388 static void ath_paprd_activate(struct ath_softc *sc)
390 struct ath_hw *ah = sc->sc_ah;
391 struct ath9k_hw_cal_data *caldata = ah->caldata;
394 if (!caldata || !caldata->paprd_done)
398 ar9003_paprd_enable(ah, false);
399 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
400 if (!(ah->txchainmask & BIT(chain)))
403 ar9003_paprd_populate_single_table(ah, caldata, chain);
406 ar9003_paprd_enable(ah, true);
407 ath9k_ps_restore(sc);
410 static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
412 struct ieee80211_hw *hw = sc->hw;
413 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
414 struct ath_hw *ah = sc->sc_ah;
415 struct ath_common *common = ath9k_hw_common(ah);
416 struct ath_tx_control txctl;
419 memset(&txctl, 0, sizeof(txctl));
420 txctl.txq = sc->tx.txq_map[WME_AC_BE];
422 memset(tx_info, 0, sizeof(*tx_info));
423 tx_info->band = hw->conf.channel->band;
424 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
425 tx_info->control.rates[0].idx = 0;
426 tx_info->control.rates[0].count = 1;
427 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
428 tx_info->control.rates[1].idx = -1;
430 init_completion(&sc->paprd_complete);
431 txctl.paprd = BIT(chain);
433 if (ath_tx_start(hw, skb, &txctl) != 0) {
434 ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
435 dev_kfree_skb_any(skb);
439 time_left = wait_for_completion_timeout(&sc->paprd_complete,
440 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
443 ath_dbg(common, CALIBRATE,
444 "Timeout waiting for paprd training on TX chain %d\n",
450 void ath_paprd_calibrate(struct work_struct *work)
452 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
453 struct ieee80211_hw *hw = sc->hw;
454 struct ath_hw *ah = sc->sc_ah;
455 struct ieee80211_hdr *hdr;
456 struct sk_buff *skb = NULL;
457 struct ath9k_hw_cal_data *caldata = ah->caldata;
458 struct ath_common *common = ath9k_hw_common(ah);
469 if (ar9003_paprd_init_table(ah) < 0)
472 skb = alloc_skb(len, GFP_KERNEL);
477 memset(skb->data, 0, len);
478 hdr = (struct ieee80211_hdr *)skb->data;
479 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
480 hdr->frame_control = cpu_to_le16(ftype);
481 hdr->duration_id = cpu_to_le16(10);
482 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
483 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
484 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
486 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
487 if (!(ah->txchainmask & BIT(chain)))
492 ath_dbg(common, CALIBRATE,
493 "Sending PAPRD frame for thermal measurement on chain %d\n",
495 if (!ath_paprd_send_frame(sc, skb, chain))
498 ar9003_paprd_setup_gain_table(ah, chain);
500 ath_dbg(common, CALIBRATE,
501 "Sending PAPRD training frame on chain %d\n", chain);
502 if (!ath_paprd_send_frame(sc, skb, chain))
505 if (!ar9003_paprd_is_done(ah)) {
506 ath_dbg(common, CALIBRATE,
507 "PAPRD not yet done on chain %d\n", chain);
511 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
512 ath_dbg(common, CALIBRATE,
513 "PAPRD create curve failed on chain %d\n",
523 caldata->paprd_done = true;
524 ath_paprd_activate(sc);
528 ath9k_ps_restore(sc);
532 * This routine performs the periodic noise floor calibration function
533 * that is used to adjust and optimize the chip performance. This
534 * takes environmental changes (location, temperature) into account.
535 * When the task is complete, it reschedules itself depending on the
536 * appropriate interval that was calculated.
538 void ath_ani_calibrate(unsigned long data)
540 struct ath_softc *sc = (struct ath_softc *)data;
541 struct ath_hw *ah = sc->sc_ah;
542 struct ath_common *common = ath9k_hw_common(ah);
543 bool longcal = false;
544 bool shortcal = false;
545 bool aniflag = false;
546 unsigned int timestamp = jiffies_to_msecs(jiffies);
547 u32 cal_interval, short_cal_interval, long_cal_interval;
550 if (ah->caldata && ah->caldata->nfcal_interference)
551 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
553 long_cal_interval = ATH_LONG_CALINTERVAL;
555 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
556 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
558 /* Only calibrate if awake */
559 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
564 /* Long calibration runs independently of short calibration. */
565 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
567 common->ani.longcal_timer = timestamp;
570 /* Short calibration applies only while caldone is false */
571 if (!common->ani.caldone) {
572 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
574 common->ani.shortcal_timer = timestamp;
575 common->ani.resetcal_timer = timestamp;
578 if ((timestamp - common->ani.resetcal_timer) >=
579 ATH_RESTART_CALINTERVAL) {
580 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
581 if (common->ani.caldone)
582 common->ani.resetcal_timer = timestamp;
586 /* Verify whether we must check ANI */
587 if (sc->sc_ah->config.enable_ani
588 && (timestamp - common->ani.checkani_timer) >=
589 ah->config.ani_poll_interval) {
591 common->ani.checkani_timer = timestamp;
594 /* Call ANI routine if necessary */
596 spin_lock_irqsave(&common->cc_lock, flags);
597 ath9k_hw_ani_monitor(ah, ah->curchan);
598 ath_update_survey_stats(sc);
599 spin_unlock_irqrestore(&common->cc_lock, flags);
602 /* Perform calibration if necessary */
603 if (longcal || shortcal) {
604 common->ani.caldone =
605 ath9k_hw_calibrate(ah, ah->curchan,
606 ah->rxchainmask, longcal);
610 "Calibration @%lu finished: %s %s %s, caldone: %s\n",
612 longcal ? "long" : "", shortcal ? "short" : "",
613 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
615 ath9k_ps_restore(sc);
619 * Set timer interval based on previous results.
620 * The interval must be the shortest necessary to satisfy ANI,
621 * short calibration and long calibration.
623 ath9k_debug_samp_bb_mac(sc);
624 cal_interval = ATH_LONG_CALINTERVAL;
625 if (sc->sc_ah->config.enable_ani)
626 cal_interval = min(cal_interval,
627 (u32)ah->config.ani_poll_interval);
628 if (!common->ani.caldone)
629 cal_interval = min(cal_interval, (u32)short_cal_interval);
631 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
632 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
633 if (!ah->caldata->paprd_done)
634 ieee80211_queue_work(sc->hw, &sc->paprd_work);
635 else if (!ah->paprd_table_write_done)
636 ath_paprd_activate(sc);
640 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
641 struct ieee80211_vif *vif)
644 an = (struct ath_node *)sta->drv_priv;
646 #ifdef CONFIG_ATH9K_DEBUGFS
647 spin_lock(&sc->nodes_lock);
648 list_add(&an->list, &sc->nodes);
649 spin_unlock(&sc->nodes_lock);
654 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
655 ath_tx_node_init(sc, an);
656 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
657 sta->ht_cap.ampdu_factor);
658 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
662 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
664 struct ath_node *an = (struct ath_node *)sta->drv_priv;
666 #ifdef CONFIG_ATH9K_DEBUGFS
667 spin_lock(&sc->nodes_lock);
669 spin_unlock(&sc->nodes_lock);
673 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
674 ath_tx_node_cleanup(sc, an);
677 void ath_rx_poll_work(unsigned long data)
679 struct ath_softc *sc = (struct ath_softc *)data;
680 struct ath_hw *ah = sc->sc_ah;
681 struct ath_common *common = ath9k_hw_common(ah);
682 struct ieee80211_conf *conf = &common->hw->conf;
683 struct ath9k_nfcal_hist *h = sc->caldata.nfCalHist;
684 static u32 iter, match_count;
687 u32 rx_clear, rx, tx, delay = 10, reg;
689 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
692 if (jiffies_to_msecs(jiffies - last_run) > 30)
693 iter = match_count = 0;
695 if (atomic_read(&sc->stop_rx_poll) && iter) {
696 iter = match_count = 0;
701 sc->ps_flags |= PS_WAIT_FOR_BEACON;
704 spin_lock_irqsave(&common->cc_lock, flags);
705 ath_hw_cycle_counters_update(common);
707 rx_clear = common->cc_rxpoll.rx_busy * 100 / common->cc_rxpoll.cycles;
708 rx = common->cc_rxpoll.rx_frame * 100 / common->cc_rxpoll.cycles;
709 tx = common->cc_rxpoll.tx_frame * 100 / common->cc_rxpoll.cycles;
710 memset(&common->cc_rxpoll, 0, sizeof(common->cc_rxpoll));
712 spin_unlock_irqrestore(&common->cc_lock, flags);
714 ath_dbg(common, RX_STUCK,
715 "--------------------------------------------------\n");
716 ath_dbg(common, RX_STUCK, "Iteration: %d\n", iter);
717 ath_dbg(common, RX_STUCK, "Cycle Counters:\n");
718 ath_dbg(common, RX_STUCK,
719 "rx_clear = %d%% rx_frame %d%% tx_frame %d%%\n",
722 ath_dbg(common, RX_STUCK, "IMR %08x IER %08x intr_cnt %d\n",
723 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER),
724 atomic_read(&ah->intr_ref_cnt));
726 ar9003_hw_dump_txdesc(ah);
728 REG_SET_BIT(ah, AR_DIAG_SW, 0x8080000);
729 for (i = 0; i < 5; i++) {
730 ath_dbg(common, RX_STUCK,
731 "OBS_BUS_1(0x806c) = %08x "
732 "OBS_BUS_CTRL(0x8068) = %08x\n",
733 REG_READ(ah, AR_OBS_BUS_1),
734 REG_READ(ah, AR_OBS_BUS_CTRL));
736 ath_dbg(common, RX_STUCK,
737 "DIAG_SW(0x8048) = %08x MAC_PCU_LOGIC_ANALYZER(0x8264) = %08x"
738 " PCU_MISC_MODE2(0x8344) = %08x\n",
739 REG_READ(ah, AR_DIAG_SW),
740 REG_READ(ah, AR_MAC_PCU_LOGIC_ANALYZER),
741 REG_READ(ah, AR_PCU_MISC_MODE2));
743 ath_dbg(common, RX_STUCK, "0x100 = %08x 0x104 = %08x\n",
744 REG_READ(ah, 0x100), REG_READ(ah, 0x104));
745 for (i = 0; i < 10; i++)
746 ath_dbg(common, RX_STUCK, "QSTS(%d) = %08x\n",
747 i, REG_READ(ah, AR_QSTS(i)));
749 ath_dbg(common, RX_STUCK, "Rxdp: hp %08x lp %08x\n",
750 REG_READ(ah, AR_HP_RXDP), REG_READ(ah, AR_LP_RXDP));
751 ath_dbg(common, RX_STUCK,
752 "rx filter: %08x\n", REG_READ(ah, AR_RX_FILTER));
754 ath_dbg(common, RX_STUCK, "DMADBG dump:\n");
755 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++)
756 ath_dbg(common, RX_STUCK, "%d: %08x ",
757 i, REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32))));
758 ath_dbg(common, RX_STUCK, "\n");
760 ath_dbg(common, RX_STUCK, "BB Debug dump:\n");
761 /* Step 1a: Set bit 23 of register 0xa360 to 0 */
762 reg = REG_READ(ah, 0xa360);
764 REG_WRITE(ah, 0xa360, reg);
766 /* Step 2a: Set register 0xa364 to 0x1000 */
768 REG_WRITE(ah, 0xa364, reg);
770 /* Step 3a: Read bits 17:0 of register 0x9c20 */
771 reg = REG_READ(ah, 0x9c20);
773 ath_dbg(common, RX_STUCK,
774 "Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", reg);
776 /* Step 1b: Set bit 23 of register 0xa360 to 0 */
777 reg = REG_READ(ah, 0xa360);
779 REG_WRITE(ah, 0xa360, reg);
781 /* Step 2b: Set register 0xa364 to 0x1400 */
783 REG_WRITE(ah, 0xa364, reg);
785 /* Step 3b: Read bits 17:0 of register 0x9c20 */
786 reg = REG_READ(ah, 0x9c20);
788 ath_dbg(common, RX_STUCK,
789 "Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", reg);
791 /* Step 1c: Set bit 23 of register 0xa360 to 0 */
792 reg = REG_READ(ah, 0xa360);
794 REG_WRITE(ah, 0xa360, reg);
796 /* Step 2c: Set register 0xa364 to 0x3C00 */
798 REG_WRITE(ah, 0xa364, reg);
800 /* Step 3c: Read bits 17:0 of register 0x9c20 */
801 reg = REG_READ(ah, 0x9c20);
803 ath_dbg(common, RX_STUCK,
804 "Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", reg);
806 /* Step 1d: Set bit 24 of register 0xa360 to 0 */
807 reg = REG_READ(ah, 0xa360);
809 REG_WRITE(ah, 0xa360, reg);
811 /* Step 2d: Set register 0xa364 to 0x5005D */
813 REG_WRITE(ah, 0xa364, reg);
815 /* Step 3d: Read bits 17:0 of register 0xa368 */
816 reg = REG_READ(ah, 0xa368);
818 ath_dbg(common, RX_STUCK,
819 "Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", reg);
821 /* Step 1e: Set bit 24 of register 0xa360 to 0 */
822 reg = REG_READ(ah, 0xa360);
824 REG_WRITE(ah, 0xa360, reg);
826 /* Step 2e: Set register 0xa364 to 0x7005D */
828 REG_WRITE(ah, 0xa364, reg);
830 /* Step 3e: Read bits 17:0 of register 0xa368 */
831 reg = REG_READ(ah, 0xa368);
833 ath_dbg(common, RX_STUCK,
834 "Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", reg);
836 /* Step 1f: Set bit 24 of register 0xa360 to 0 */
837 reg = REG_READ(ah, 0xa360);
840 REG_WRITE(ah, 0xa360, reg);
842 /* Step 2f: Set register 0xa364 to 0x3005D */
844 REG_WRITE(ah, 0xa364, reg);
846 /* Step 3f: Read bits 17:0 of register 0xa368 */
847 reg = REG_READ(ah, 0xa368);
849 ath_dbg(common, RX_STUCK,
850 "Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", reg);
852 /* Step 1g: Set bit 24 of register 0xa360 to 0 */
853 reg = REG_READ(ah, 0xa360);
856 REG_WRITE(ah, 0xa360, reg);
858 /* Step 2g: Set register 0xa364 to 0x6005D */
860 REG_WRITE(ah, 0xa364, reg);
862 /* Step 3g: Read bits 17:0 of register 0xa368 */
863 reg = REG_READ(ah, 0xa368);
865 ath_dbg(common, RX_STUCK,
866 "Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", reg);
868 ar9003_hw_dump_ani_reg(ah);
870 ath_dbg(common, RX_STUCK,
871 "%8s: %10u\n", "RXLP", sc->debug.stats.istats.rxlp);
872 ath_dbg(common, RX_STUCK,
873 "%8s: %10u\n", "RXHP", sc->debug.stats.istats.rxhp);
874 ath_dbg(common, RX_STUCK,
875 "%8s: %10u\n", "WATCHDOG",
876 sc->debug.stats.istats.bb_watchdog);
877 ath_dbg(common, RX_STUCK,
878 "%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol);
879 ath_dbg(common, RX_STUCK,
880 "%8s: %10u\n", "RXORN", sc->debug.stats.istats.rxorn);
881 ath_dbg(common, RX_STUCK,
882 "%8s: %10u\n", "TX", sc->debug.stats.istats.txok);
883 ath_dbg(common, RX_STUCK,
884 "%8s: %10u\n", "TXURN", sc->debug.stats.istats.txurn);
885 ath_dbg(common, RX_STUCK,
886 "%8s: %10u\n", "MIB", sc->debug.stats.istats.mib);
887 ath_dbg(common, RX_STUCK, "%8s: %10u\n", "RXPHY",
888 sc->debug.stats.istats.rxphyerr);
889 ath_dbg(common, RX_STUCK, "%8s: %10u\n", "RXKCM",
890 sc->debug.stats.istats.rx_keycache_miss);
891 ath_dbg(common, RX_STUCK,
892 "%8s: %10u\n", "BMISS", sc->debug.stats.istats.bmiss);
893 ath_dbg(common, RX_STUCK,
894 "%8s: %10u\n", "CST", sc->debug.stats.istats.cst);
895 ath_dbg(common, RX_STUCK,
896 "%8s: %10u\n", "GTT", sc->debug.stats.istats.gtt);
898 ath_dbg(common, RX_STUCK, "Noise floor dump:\n");
899 ath_dbg(common, RX_STUCK,
900 "Channel Noise Floor : %d\n", ah->noise);
901 ath_dbg(common, RX_STUCK,
902 "Chain | privNF | # Readings | NF Readings\n");
903 for (i = 0; i < 6; i++) {
904 if (!(chainmask & (1 << i)) ||
905 ((i >= 3) && !conf_is_ht40(conf)))
908 nread = 5 - h[i].invalidNFcount;
909 ath_dbg(common, RX_STUCK,
910 " %d\t %d\t %d\t\t", i, h[i].privNF, nread);
911 for (j = 0; j < nread; j++)
912 ath_dbg(common, RX_STUCK,
913 " %d", h[i].nfCalBuffer[j]);
914 ath_dbg(common, RX_STUCK, "\n");
919 ath_dbg(common, RX_STUCK,
920 "rx clear %d tx %d matched count %d\n",
921 rx_clear, tx, match_count);
922 if (match_count++ > 9) {
923 ath9k_ps_restore(sc);
924 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
925 iter = match_count = 0;
928 } else if (ath9k_hw_detect_mac_hang(ah)) {
929 ath_dbg(common, RX_STUCK, "MAC hang signature found\n");
930 ath9k_ps_restore(sc);
931 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
932 iter = match_count = 0;
934 } else if (iter >= 15) {
935 iter = match_count = 0;
938 ath9k_ps_restore(sc);
939 atomic_set(&sc->stop_rx_poll, 0);
940 mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies(delay));
943 void ath9k_tasklet(unsigned long data)
945 struct ath_softc *sc = (struct ath_softc *)data;
946 struct ath_hw *ah = sc->sc_ah;
947 struct ath_common *common = ath9k_hw_common(ah);
949 u32 status = sc->intrstatus;
953 spin_lock(&sc->sc_pcu_lock);
955 if ((status & ATH9K_INT_FATAL) ||
956 (status & ATH9K_INT_BB_WATCHDOG)) {
957 #ifdef CONFIG_ATH9K_DEBUGFS
958 enum ath_reset_type type;
960 if (status & ATH9K_INT_FATAL)
961 type = RESET_TYPE_FATAL_INT;
963 type = RESET_TYPE_BB_WATCHDOG;
965 RESET_STAT_INC(sc, type);
967 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
972 * Only run the baseband hang check if beacons stop working in AP or
973 * IBSS mode, because it has a high false positive rate. For station
974 * mode it should not be necessary, since the upper layers will detect
975 * this through a beacon miss automatically and the following channel
976 * change will trigger a hardware reset anyway
978 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
979 !ath9k_hw_check_alive(ah))
980 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
982 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
984 * TSF sync does not look correct; remain awake to sync with
987 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
988 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
991 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
992 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
995 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
997 if (status & rxmask) {
998 /* Check for high priority Rx first */
999 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
1000 (status & ATH9K_INT_RXHP))
1001 ath_rx_tasklet(sc, 0, true);
1003 ath_rx_tasklet(sc, 0, false);
1006 if (status & ATH9K_INT_TX) {
1007 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1008 ath_tx_edma_tasklet(sc);
1013 ath9k_btcoex_handle_interrupt(sc, status);
1016 /* re-enable hardware interrupt */
1017 ath9k_hw_enable_interrupts(ah);
1019 spin_unlock(&sc->sc_pcu_lock);
1020 ath9k_ps_restore(sc);
1023 irqreturn_t ath_isr(int irq, void *dev)
1025 #define SCHED_INTR ( \
1027 ATH9K_INT_BB_WATCHDOG | \
1036 ATH9K_INT_TSFOOR | \
1037 ATH9K_INT_GENTIMER | \
1040 struct ath_softc *sc = dev;
1041 struct ath_hw *ah = sc->sc_ah;
1042 struct ath_common *common = ath9k_hw_common(ah);
1043 enum ath9k_int status;
1047 * The hardware is not ready/present, don't
1048 * touch anything. Note this can happen early
1049 * on if the IRQ is shared.
1051 if (sc->sc_flags & SC_OP_INVALID)
1055 /* shared irq, not for us */
1057 if (!ath9k_hw_intrpend(ah))
1061 * Figure out the reason(s) for the interrupt. Note
1062 * that the hal returns a pseudo-ISR that may include
1063 * bits we haven't explicitly enabled so we mask the
1064 * value to insure we only process bits we requested.
1066 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
1067 status &= ah->imask; /* discard unasked-for bits */
1070 * If there are no status bits set, then this interrupt was not
1071 * for me (should have been caught above).
1076 /* Cache the status */
1077 sc->intrstatus = status;
1079 if (status & SCHED_INTR)
1083 * If a FATAL or RXORN interrupt is received, we have to reset the
1086 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
1087 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
1090 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
1091 (status & ATH9K_INT_BB_WATCHDOG)) {
1093 spin_lock(&common->cc_lock);
1094 ath_hw_cycle_counters_update(common);
1095 ar9003_hw_bb_watchdog_dbg_info(ah);
1096 spin_unlock(&common->cc_lock);
1101 if (status & ATH9K_INT_SWBA)
1102 tasklet_schedule(&sc->bcon_tasklet);
1104 if (status & ATH9K_INT_TXURN)
1105 ath9k_hw_updatetxtriglevel(ah, true);
1107 if (status & ATH9K_INT_RXEOL) {
1108 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1109 ath9k_hw_set_interrupts(ah);
1112 if (status & ATH9K_INT_MIB) {
1114 * Disable interrupts until we service the MIB
1115 * interrupt; otherwise it will continue to
1118 ath9k_hw_disable_interrupts(ah);
1120 * Let the hal handle the event. We assume
1121 * it will clear whatever condition caused
1124 spin_lock(&common->cc_lock);
1125 ath9k_hw_proc_mib_event(ah);
1126 spin_unlock(&common->cc_lock);
1127 ath9k_hw_enable_interrupts(ah);
1130 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1131 if (status & ATH9K_INT_TIM_TIMER) {
1132 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
1134 /* Clear RxAbort bit so that we can
1136 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1137 ath9k_hw_setrxabort(sc->sc_ah, 0);
1138 sc->ps_flags |= PS_WAIT_FOR_BEACON;
1143 ath_debug_stat_interrupt(sc, status);
1146 /* turn off every interrupt */
1147 ath9k_hw_disable_interrupts(ah);
1148 tasklet_schedule(&sc->intr_tq);
1156 static int ath_reset(struct ath_softc *sc, bool retry_tx)
1158 struct ath_hw *ah = sc->sc_ah;
1159 struct ath_common *common = ath9k_hw_common(ah);
1162 sc->hw_busy_count = 0;
1164 ath9k_debug_samp_bb_mac(sc);
1166 del_timer_sync(&common->ani.timer);
1167 del_timer_sync(&sc->rx_poll_timer);
1169 ath9k_ps_wakeup(sc);
1171 ieee80211_stop_queues(sc->hw);
1173 ath9k_hw_disable_interrupts(ah);
1174 ath_drain_all_txq(sc, retry_tx);
1179 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
1182 "Unable to reset hardware; reset status %d\n", r);
1184 if (ath_startrecv(sc) != 0)
1185 ath_err(common, "Unable to start recv logic\n");
1188 * We may be doing a reset in response to a request
1189 * that changes the channel so update any state that
1190 * might change as a result.
1192 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1193 sc->config.txpowlimit, &sc->curtxpow);
1195 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
1196 ath_set_beacon(sc); /* restart beacons */
1198 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1199 mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies(300));
1201 ath9k_hw_set_interrupts(ah);
1202 ath9k_hw_enable_interrupts(ah);
1206 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1207 if (ATH_TXQ_SETUP(sc, i)) {
1208 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1209 ath_txq_schedule(sc, &sc->tx.txq[i]);
1210 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1215 ath9k_ps_restore(sc);
1220 void ath_reset_work(struct work_struct *work)
1222 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
1224 ath_reset(sc, true);
1227 void ath_hw_check(struct work_struct *work)
1229 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
1230 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1231 unsigned long flags;
1234 ath9k_ps_wakeup(sc);
1235 if (ath9k_hw_check_alive(sc->sc_ah))
1238 spin_lock_irqsave(&common->cc_lock, flags);
1239 busy = ath_update_survey_stats(sc);
1240 spin_unlock_irqrestore(&common->cc_lock, flags);
1242 ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
1243 busy, sc->hw_busy_count + 1);
1245 if (++sc->hw_busy_count >= 3) {
1246 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
1247 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
1250 } else if (busy >= 0)
1251 sc->hw_busy_count = 0;
1254 ath9k_ps_restore(sc);
1257 static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
1260 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1262 if (pll_sqsum >= 0x40000) {
1265 /* Rx is hung for more than 500ms. Reset it */
1266 ath_dbg(common, RESET, "Possible RX hang, resetting\n");
1267 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
1268 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
1275 void ath_hw_pll_work(struct work_struct *work)
1277 struct ath_softc *sc = container_of(work, struct ath_softc,
1281 if (AR_SREV_9485(sc->sc_ah)) {
1283 ath9k_ps_wakeup(sc);
1284 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
1285 ath9k_ps_restore(sc);
1287 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
1289 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
1293 /**********************/
1294 /* mac80211 callbacks */
1295 /**********************/
1297 static int ath9k_start(struct ieee80211_hw *hw)
1299 struct ath_softc *sc = hw->priv;
1300 struct ath_hw *ah = sc->sc_ah;
1301 struct ath_common *common = ath9k_hw_common(ah);
1302 struct ieee80211_channel *curchan = hw->conf.channel;
1303 struct ath9k_channel *init_channel;
1306 ath_dbg(common, CONFIG,
1307 "Starting driver with initial channel: %d MHz\n",
1308 curchan->center_freq);
1310 ath9k_ps_wakeup(sc);
1311 mutex_lock(&sc->mutex);
1313 init_channel = ath9k_cmn_get_curchannel(hw, ah);
1315 /* Reset SERDES registers */
1316 ath9k_hw_configpcipowersave(ah, false);
1319 * The basic interface to setting the hardware in a good
1320 * state is ``reset''. On return the hardware is known to
1321 * be powered up and with interrupts disabled. This must
1322 * be followed by initialization of the appropriate bits
1323 * and then setup of the interrupt mask.
1325 spin_lock_bh(&sc->sc_pcu_lock);
1327 atomic_set(&ah->intr_ref_cnt, -1);
1329 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
1332 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1333 r, curchan->center_freq);
1334 spin_unlock_bh(&sc->sc_pcu_lock);
1338 /* Setup our intr mask. */
1339 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1340 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1343 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1344 ah->imask |= ATH9K_INT_RXHP |
1346 ATH9K_INT_BB_WATCHDOG;
1348 ah->imask |= ATH9K_INT_RX;
1350 ah->imask |= ATH9K_INT_GTT;
1352 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1353 ah->imask |= ATH9K_INT_CST;
1355 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1356 ah->imask |= ATH9K_INT_MCI;
1358 sc->sc_flags &= ~SC_OP_INVALID;
1359 sc->sc_ah->is_monitoring = false;
1361 if (!ath_complete_reset(sc, false)) {
1363 spin_unlock_bh(&sc->sc_pcu_lock);
1367 if (ah->led_pin >= 0) {
1368 ath9k_hw_cfg_output(ah, ah->led_pin,
1369 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1370 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1374 * Reset key cache to sane defaults (all entries cleared) instead of
1375 * semi-random values after suspend/resume.
1377 ath9k_cmn_init_crypto(sc->sc_ah);
1379 spin_unlock_bh(&sc->sc_pcu_lock);
1381 ath9k_start_btcoex(sc);
1383 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1384 common->bus_ops->extn_synch_en(common);
1387 mutex_unlock(&sc->mutex);
1389 ath9k_ps_restore(sc);
1394 static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1396 struct ath_softc *sc = hw->priv;
1397 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1398 struct ath_tx_control txctl;
1399 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1401 if (sc->ps_enabled) {
1403 * mac80211 does not set PM field for normal data frames, so we
1404 * need to update that based on the current PS mode.
1406 if (ieee80211_is_data(hdr->frame_control) &&
1407 !ieee80211_is_nullfunc(hdr->frame_control) &&
1408 !ieee80211_has_pm(hdr->frame_control)) {
1410 "Add PM=1 for a TX frame while in PS mode\n");
1411 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1416 * Cannot tx while the hardware is in full sleep, it first needs a full
1417 * chip reset to recover from that
1419 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP))
1422 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1424 * We are using PS-Poll and mac80211 can request TX while in
1425 * power save mode. Need to wake up hardware for the TX to be
1426 * completed and if needed, also for RX of buffered frames.
1428 ath9k_ps_wakeup(sc);
1429 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1430 ath9k_hw_setrxabort(sc->sc_ah, 0);
1431 if (ieee80211_is_pspoll(hdr->frame_control)) {
1433 "Sending PS-Poll to pick a buffered frame\n");
1434 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
1436 ath_dbg(common, PS, "Wake up to complete TX\n");
1437 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
1440 * The actual restore operation will happen only after
1441 * the sc_flags bit is cleared. We are just dropping
1442 * the ps_usecount here.
1444 ath9k_ps_restore(sc);
1447 memset(&txctl, 0, sizeof(struct ath_tx_control));
1448 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
1450 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
1452 if (ath_tx_start(hw, skb, &txctl) != 0) {
1453 ath_dbg(common, XMIT, "TX failed\n");
1459 dev_kfree_skb_any(skb);
1462 static void ath9k_stop(struct ieee80211_hw *hw)
1464 struct ath_softc *sc = hw->priv;
1465 struct ath_hw *ah = sc->sc_ah;
1466 struct ath_common *common = ath9k_hw_common(ah);
1469 mutex_lock(&sc->mutex);
1471 ath_cancel_work(sc);
1473 if (sc->sc_flags & SC_OP_INVALID) {
1474 ath_dbg(common, ANY, "Device not present\n");
1475 mutex_unlock(&sc->mutex);
1479 /* Ensure HW is awake when we try to shut it down. */
1480 ath9k_ps_wakeup(sc);
1482 ath9k_stop_btcoex(sc);
1484 spin_lock_bh(&sc->sc_pcu_lock);
1486 /* prevent tasklets to enable interrupts once we disable them */
1487 ah->imask &= ~ATH9K_INT_GLOBAL;
1489 /* make sure h/w will not generate any interrupt
1490 * before setting the invalid flag. */
1491 ath9k_hw_disable_interrupts(ah);
1493 spin_unlock_bh(&sc->sc_pcu_lock);
1495 /* we can now sync irq and kill any running tasklets, since we already
1496 * disabled interrupts and not holding a spin lock */
1497 synchronize_irq(sc->irq);
1498 tasklet_kill(&sc->intr_tq);
1499 tasklet_kill(&sc->bcon_tasklet);
1501 prev_idle = sc->ps_idle;
1504 spin_lock_bh(&sc->sc_pcu_lock);
1506 if (ah->led_pin >= 0) {
1507 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1508 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1511 ath_prepare_reset(sc, false, true);
1514 dev_kfree_skb_any(sc->rx.frag);
1519 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
1521 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
1522 ath9k_hw_phy_disable(ah);
1524 ath9k_hw_configpcipowersave(ah, true);
1526 spin_unlock_bh(&sc->sc_pcu_lock);
1528 ath9k_ps_restore(sc);
1530 sc->sc_flags |= SC_OP_INVALID;
1531 sc->ps_idle = prev_idle;
1533 mutex_unlock(&sc->mutex);
1535 ath_dbg(common, CONFIG, "Driver halt\n");
1538 bool ath9k_uses_beacons(int type)
1541 case NL80211_IFTYPE_AP:
1542 case NL80211_IFTYPE_ADHOC:
1543 case NL80211_IFTYPE_MESH_POINT:
1550 static void ath9k_reclaim_beacon(struct ath_softc *sc,
1551 struct ieee80211_vif *vif)
1553 struct ath_vif *avp = (void *)vif->drv_priv;
1555 ath9k_set_beaconing_status(sc, false);
1556 ath_beacon_return(sc, avp);
1557 ath9k_set_beaconing_status(sc, true);
1558 sc->sc_flags &= ~SC_OP_BEACONS;
1561 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1563 struct ath9k_vif_iter_data *iter_data = data;
1566 if (iter_data->hw_macaddr)
1567 for (i = 0; i < ETH_ALEN; i++)
1568 iter_data->mask[i] &=
1569 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1571 switch (vif->type) {
1572 case NL80211_IFTYPE_AP:
1575 case NL80211_IFTYPE_STATION:
1576 iter_data->nstations++;
1578 case NL80211_IFTYPE_ADHOC:
1579 iter_data->nadhocs++;
1581 case NL80211_IFTYPE_MESH_POINT:
1582 iter_data->nmeshes++;
1584 case NL80211_IFTYPE_WDS:
1592 /* Called with sc->mutex held. */
1593 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1594 struct ieee80211_vif *vif,
1595 struct ath9k_vif_iter_data *iter_data)
1597 struct ath_softc *sc = hw->priv;
1598 struct ath_hw *ah = sc->sc_ah;
1599 struct ath_common *common = ath9k_hw_common(ah);
1602 * Use the hardware MAC address as reference, the hardware uses it
1603 * together with the BSSID mask when matching addresses.
1605 memset(iter_data, 0, sizeof(*iter_data));
1606 iter_data->hw_macaddr = common->macaddr;
1607 memset(&iter_data->mask, 0xff, ETH_ALEN);
1610 ath9k_vif_iter(iter_data, vif->addr, vif);
1612 /* Get list of all active MAC addresses */
1613 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1617 /* Called with sc->mutex held. */
1618 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1619 struct ieee80211_vif *vif)
1621 struct ath_softc *sc = hw->priv;
1622 struct ath_hw *ah = sc->sc_ah;
1623 struct ath_common *common = ath9k_hw_common(ah);
1624 struct ath9k_vif_iter_data iter_data;
1626 ath9k_calculate_iter_data(hw, vif, &iter_data);
1628 /* Set BSSID mask. */
1629 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1630 ath_hw_setbssidmask(common);
1632 /* Set op-mode & TSF */
1633 if (iter_data.naps > 0) {
1634 ath9k_hw_set_tsfadjust(ah, 1);
1635 sc->sc_flags |= SC_OP_TSF_RESET;
1636 ah->opmode = NL80211_IFTYPE_AP;
1638 ath9k_hw_set_tsfadjust(ah, 0);
1639 sc->sc_flags &= ~SC_OP_TSF_RESET;
1641 if (iter_data.nmeshes)
1642 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1643 else if (iter_data.nwds)
1644 ah->opmode = NL80211_IFTYPE_AP;
1645 else if (iter_data.nadhocs)
1646 ah->opmode = NL80211_IFTYPE_ADHOC;
1648 ah->opmode = NL80211_IFTYPE_STATION;
1652 * Enable MIB interrupts when there are hardware phy counters.
1654 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
1655 if (ah->config.enable_ani)
1656 ah->imask |= ATH9K_INT_MIB;
1657 ah->imask |= ATH9K_INT_TSFOOR;
1659 ah->imask &= ~ATH9K_INT_MIB;
1660 ah->imask &= ~ATH9K_INT_TSFOOR;
1663 ath9k_hw_set_interrupts(ah);
1666 if (iter_data.naps > 0) {
1667 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1669 if (!common->disable_ani) {
1670 sc->sc_flags |= SC_OP_ANI_RUN;
1671 ath_start_ani(common);
1675 sc->sc_flags &= ~SC_OP_ANI_RUN;
1676 del_timer_sync(&common->ani.timer);
1680 /* Called with sc->mutex held, vif counts set up properly. */
1681 static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1682 struct ieee80211_vif *vif)
1684 struct ath_softc *sc = hw->priv;
1686 ath9k_calculate_summary_state(hw, vif);
1688 if (ath9k_uses_beacons(vif->type)) {
1690 /* This may fail because upper levels do not have beacons
1691 * properly configured yet. That's OK, we assume it
1692 * will be properly configured and then we will be notified
1693 * in the info_changed method and set up beacons properly
1696 ath9k_set_beaconing_status(sc, false);
1697 error = ath_beacon_alloc(sc, vif);
1699 ath_beacon_config(sc, vif);
1700 ath9k_set_beaconing_status(sc, true);
1705 static int ath9k_add_interface(struct ieee80211_hw *hw,
1706 struct ieee80211_vif *vif)
1708 struct ath_softc *sc = hw->priv;
1709 struct ath_hw *ah = sc->sc_ah;
1710 struct ath_common *common = ath9k_hw_common(ah);
1713 ath9k_ps_wakeup(sc);
1714 mutex_lock(&sc->mutex);
1716 switch (vif->type) {
1717 case NL80211_IFTYPE_STATION:
1718 case NL80211_IFTYPE_WDS:
1719 case NL80211_IFTYPE_ADHOC:
1720 case NL80211_IFTYPE_AP:
1721 case NL80211_IFTYPE_MESH_POINT:
1724 ath_err(common, "Interface type %d not yet supported\n",
1730 if (ath9k_uses_beacons(vif->type)) {
1731 if (sc->nbcnvifs >= ATH_BCBUF) {
1732 ath_err(common, "Not enough beacon buffers when adding"
1733 " new interface of type: %i\n",
1740 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1741 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1743 ath_err(common, "Cannot create ADHOC interface when other"
1744 " interfaces already exist.\n");
1749 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1753 ath9k_do_vif_add_setup(hw, vif);
1755 mutex_unlock(&sc->mutex);
1756 ath9k_ps_restore(sc);
1760 static int ath9k_change_interface(struct ieee80211_hw *hw,
1761 struct ieee80211_vif *vif,
1762 enum nl80211_iftype new_type,
1765 struct ath_softc *sc = hw->priv;
1766 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1769 ath_dbg(common, CONFIG, "Change Interface\n");
1770 mutex_lock(&sc->mutex);
1771 ath9k_ps_wakeup(sc);
1773 /* See if new interface type is valid. */
1774 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1776 ath_err(common, "When using ADHOC, it must be the only"
1782 if (ath9k_uses_beacons(new_type) &&
1783 !ath9k_uses_beacons(vif->type)) {
1784 if (sc->nbcnvifs >= ATH_BCBUF) {
1785 ath_err(common, "No beacon slot available\n");
1791 /* Clean up old vif stuff */
1792 if (ath9k_uses_beacons(vif->type))
1793 ath9k_reclaim_beacon(sc, vif);
1795 /* Add new settings */
1796 vif->type = new_type;
1799 ath9k_do_vif_add_setup(hw, vif);
1801 ath9k_ps_restore(sc);
1802 mutex_unlock(&sc->mutex);
1806 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1807 struct ieee80211_vif *vif)
1809 struct ath_softc *sc = hw->priv;
1810 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1812 ath_dbg(common, CONFIG, "Detach Interface\n");
1814 ath9k_ps_wakeup(sc);
1815 mutex_lock(&sc->mutex);
1819 /* Reclaim beacon resources */
1820 if (ath9k_uses_beacons(vif->type))
1821 ath9k_reclaim_beacon(sc, vif);
1823 ath9k_calculate_summary_state(hw, NULL);
1825 mutex_unlock(&sc->mutex);
1826 ath9k_ps_restore(sc);
1829 static void ath9k_enable_ps(struct ath_softc *sc)
1831 struct ath_hw *ah = sc->sc_ah;
1833 sc->ps_enabled = true;
1834 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1835 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1836 ah->imask |= ATH9K_INT_TIM_TIMER;
1837 ath9k_hw_set_interrupts(ah);
1839 ath9k_hw_setrxabort(ah, 1);
1843 static void ath9k_disable_ps(struct ath_softc *sc)
1845 struct ath_hw *ah = sc->sc_ah;
1847 sc->ps_enabled = false;
1848 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1849 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1850 ath9k_hw_setrxabort(ah, 0);
1851 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1853 PS_WAIT_FOR_PSPOLL_DATA |
1854 PS_WAIT_FOR_TX_ACK);
1855 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1856 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1857 ath9k_hw_set_interrupts(ah);
1863 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1865 struct ath_softc *sc = hw->priv;
1866 struct ath_hw *ah = sc->sc_ah;
1867 struct ath_common *common = ath9k_hw_common(ah);
1868 struct ieee80211_conf *conf = &hw->conf;
1869 bool reset_channel = false;
1871 ath9k_ps_wakeup(sc);
1872 mutex_lock(&sc->mutex);
1874 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1875 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1877 ath_cancel_work(sc);
1880 * The chip needs a reset to properly wake up from
1883 reset_channel = ah->chip_fullsleep;
1887 * We just prepare to enable PS. We have to wait until our AP has
1888 * ACK'd our null data frame to disable RX otherwise we'll ignore
1889 * those ACKs and end up retransmitting the same null data frames.
1890 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1892 if (changed & IEEE80211_CONF_CHANGE_PS) {
1893 unsigned long flags;
1894 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1895 if (conf->flags & IEEE80211_CONF_PS)
1896 ath9k_enable_ps(sc);
1898 ath9k_disable_ps(sc);
1899 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1902 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1903 if (conf->flags & IEEE80211_CONF_MONITOR) {
1904 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1905 sc->sc_ah->is_monitoring = true;
1907 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1908 sc->sc_ah->is_monitoring = false;
1912 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1913 struct ieee80211_channel *curchan = hw->conf.channel;
1914 int pos = curchan->hw_value;
1916 unsigned long flags;
1919 old_pos = ah->curchan - &ah->channels[0];
1921 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1922 sc->sc_flags |= SC_OP_OFFCHANNEL;
1924 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
1926 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1927 curchan->center_freq, conf->channel_type);
1929 /* update survey stats for the old channel before switching */
1930 spin_lock_irqsave(&common->cc_lock, flags);
1931 ath_update_survey_stats(sc);
1932 spin_unlock_irqrestore(&common->cc_lock, flags);
1935 * Preserve the current channel values, before updating
1938 if (ah->curchan && (old_pos == pos))
1939 ath9k_hw_getnf(ah, ah->curchan);
1941 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1942 curchan, conf->channel_type);
1945 * If the operating channel changes, change the survey in-use flags
1947 * Reset the survey data for the new channel, unless we're switching
1948 * back to the operating channel from an off-channel operation.
1950 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1951 sc->cur_survey != &sc->survey[pos]) {
1954 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1956 sc->cur_survey = &sc->survey[pos];
1958 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1959 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1960 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1961 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1964 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1965 ath_err(common, "Unable to set channel\n");
1966 mutex_unlock(&sc->mutex);
1971 * The most recent snapshot of channel->noisefloor for the old
1972 * channel is only available after the hardware reset. Copy it to
1973 * the survey stats now.
1976 ath_update_survey_nf(sc, old_pos);
1979 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1980 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1981 sc->config.txpowlimit = 2 * conf->power_level;
1982 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1983 sc->config.txpowlimit, &sc->curtxpow);
1986 mutex_unlock(&sc->mutex);
1987 ath9k_ps_restore(sc);
1992 #define SUPPORTED_FILTERS \
1993 (FIF_PROMISC_IN_BSS | \
1998 FIF_BCN_PRBRESP_PROMISC | \
2002 /* FIXME: sc->sc_full_reset ? */
2003 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2004 unsigned int changed_flags,
2005 unsigned int *total_flags,
2008 struct ath_softc *sc = hw->priv;
2011 changed_flags &= SUPPORTED_FILTERS;
2012 *total_flags &= SUPPORTED_FILTERS;
2014 sc->rx.rxfilter = *total_flags;
2015 ath9k_ps_wakeup(sc);
2016 rfilt = ath_calcrxfilter(sc);
2017 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2018 ath9k_ps_restore(sc);
2020 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
2024 static int ath9k_sta_add(struct ieee80211_hw *hw,
2025 struct ieee80211_vif *vif,
2026 struct ieee80211_sta *sta)
2028 struct ath_softc *sc = hw->priv;
2029 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2030 struct ath_node *an = (struct ath_node *) sta->drv_priv;
2031 struct ieee80211_key_conf ps_key = { };
2033 ath_node_attach(sc, sta, vif);
2035 if (vif->type != NL80211_IFTYPE_AP &&
2036 vif->type != NL80211_IFTYPE_AP_VLAN)
2039 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
2044 static void ath9k_del_ps_key(struct ath_softc *sc,
2045 struct ieee80211_vif *vif,
2046 struct ieee80211_sta *sta)
2048 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2049 struct ath_node *an = (struct ath_node *) sta->drv_priv;
2050 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
2055 ath_key_delete(common, &ps_key);
2058 static int ath9k_sta_remove(struct ieee80211_hw *hw,
2059 struct ieee80211_vif *vif,
2060 struct ieee80211_sta *sta)
2062 struct ath_softc *sc = hw->priv;
2064 ath9k_del_ps_key(sc, vif, sta);
2065 ath_node_detach(sc, sta);
2070 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2071 struct ieee80211_vif *vif,
2072 enum sta_notify_cmd cmd,
2073 struct ieee80211_sta *sta)
2075 struct ath_softc *sc = hw->priv;
2076 struct ath_node *an = (struct ath_node *) sta->drv_priv;
2078 if (!sta->ht_cap.ht_supported)
2082 case STA_NOTIFY_SLEEP:
2083 an->sleeping = true;
2084 ath_tx_aggr_sleep(sta, sc, an);
2086 case STA_NOTIFY_AWAKE:
2087 an->sleeping = false;
2088 ath_tx_aggr_wakeup(sc, an);
2093 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2094 struct ieee80211_vif *vif, u16 queue,
2095 const struct ieee80211_tx_queue_params *params)
2097 struct ath_softc *sc = hw->priv;
2098 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2099 struct ath_txq *txq;
2100 struct ath9k_tx_queue_info qi;
2103 if (queue >= WME_NUM_AC)
2106 txq = sc->tx.txq_map[queue];
2108 ath9k_ps_wakeup(sc);
2109 mutex_lock(&sc->mutex);
2111 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2113 qi.tqi_aifs = params->aifs;
2114 qi.tqi_cwmin = params->cw_min;
2115 qi.tqi_cwmax = params->cw_max;
2116 qi.tqi_burstTime = params->txop;
2118 ath_dbg(common, CONFIG,
2119 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2120 queue, txq->axq_qnum, params->aifs, params->cw_min,
2121 params->cw_max, params->txop);
2123 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
2125 ath_err(common, "TXQ Update failed\n");
2127 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
2128 if (queue == WME_AC_BE && !ret)
2129 ath_beaconq_config(sc);
2131 mutex_unlock(&sc->mutex);
2132 ath9k_ps_restore(sc);
2137 static int ath9k_set_key(struct ieee80211_hw *hw,
2138 enum set_key_cmd cmd,
2139 struct ieee80211_vif *vif,
2140 struct ieee80211_sta *sta,
2141 struct ieee80211_key_conf *key)
2143 struct ath_softc *sc = hw->priv;
2144 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2147 if (ath9k_modparam_nohwcrypt)
2150 if ((vif->type == NL80211_IFTYPE_ADHOC ||
2151 vif->type == NL80211_IFTYPE_MESH_POINT) &&
2152 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
2153 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
2154 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2156 * For now, disable hw crypto for the RSN IBSS group keys. This
2157 * could be optimized in the future to use a modified key cache
2158 * design to support per-STA RX GTK, but until that gets
2159 * implemented, use of software crypto for group addressed
2160 * frames is a acceptable to allow RSN IBSS to be used.
2165 mutex_lock(&sc->mutex);
2166 ath9k_ps_wakeup(sc);
2167 ath_dbg(common, CONFIG, "Set HW Key\n");
2172 ath9k_del_ps_key(sc, vif, sta);
2174 ret = ath_key_config(common, vif, sta, key);
2176 key->hw_key_idx = ret;
2177 /* push IV and Michael MIC generation to stack */
2178 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2179 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
2180 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2181 if (sc->sc_ah->sw_mgmt_crypto &&
2182 key->cipher == WLAN_CIPHER_SUITE_CCMP)
2183 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2188 ath_key_delete(common, key);
2194 ath9k_ps_restore(sc);
2195 mutex_unlock(&sc->mutex);
2199 static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
2201 struct ath_softc *sc = data;
2202 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2203 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2204 struct ath_vif *avp = (void *)vif->drv_priv;
2207 * Skip iteration if primary station vif's bss info
2210 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
2213 if (bss_conf->assoc) {
2214 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
2215 avp->primary_sta_vif = true;
2216 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2217 common->curaid = bss_conf->aid;
2218 ath9k_hw_write_associd(sc->sc_ah);
2219 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
2220 bss_conf->aid, common->curbssid);
2221 ath_beacon_config(sc, vif);
2223 * Request a re-configuration of Beacon related timers
2224 * on the receipt of the first Beacon frame (i.e.,
2225 * after time sync with the AP).
2227 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
2228 /* Reset rssi stats */
2229 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
2230 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
2232 if (!common->disable_ani) {
2233 sc->sc_flags |= SC_OP_ANI_RUN;
2234 ath_start_ani(common);
2235 atomic_set(&sc->stop_rx_poll, 0);
2236 mod_timer(&sc->rx_poll_timer,
2237 jiffies + msecs_to_jiffies(300));
2243 static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2245 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2246 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2247 struct ath_vif *avp = (void *)vif->drv_priv;
2249 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2252 /* Reconfigure bss info */
2253 if (avp->primary_sta_vif && !bss_conf->assoc) {
2254 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
2255 common->curaid, common->curbssid);
2256 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
2257 avp->primary_sta_vif = false;
2258 memset(common->curbssid, 0, ETH_ALEN);
2262 ieee80211_iterate_active_interfaces_atomic(
2263 sc->hw, ath9k_bss_iter, sc);
2266 * None of station vifs are associated.
2269 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
2270 ath9k_hw_write_associd(sc->sc_ah);
2272 sc->sc_flags &= ~SC_OP_ANI_RUN;
2273 del_timer_sync(&common->ani.timer);
2274 del_timer_sync(&sc->rx_poll_timer);
2275 memset(&sc->caldata, 0, sizeof(sc->caldata));
2279 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2280 struct ieee80211_vif *vif,
2281 struct ieee80211_bss_conf *bss_conf,
2284 struct ath_softc *sc = hw->priv;
2285 struct ath_hw *ah = sc->sc_ah;
2286 struct ath_common *common = ath9k_hw_common(ah);
2287 struct ath_vif *avp = (void *)vif->drv_priv;
2291 ath9k_ps_wakeup(sc);
2292 mutex_lock(&sc->mutex);
2294 if (changed & BSS_CHANGED_ASSOC) {
2295 ath9k_config_bss(sc, vif);
2297 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
2298 common->curbssid, common->curaid);
2301 if (changed & BSS_CHANGED_IBSS) {
2302 /* There can be only one vif available */
2303 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2304 common->curaid = bss_conf->aid;
2305 ath9k_hw_write_associd(sc->sc_ah);
2307 if (bss_conf->ibss_joined) {
2308 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
2310 if (!common->disable_ani) {
2311 sc->sc_flags |= SC_OP_ANI_RUN;
2312 ath_start_ani(common);
2316 sc->sc_flags &= ~SC_OP_ANI_RUN;
2317 del_timer_sync(&common->ani.timer);
2321 /* Enable transmission of beacons (AP, IBSS, MESH) */
2322 if ((changed & BSS_CHANGED_BEACON) ||
2323 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2324 ath9k_set_beaconing_status(sc, false);
2325 error = ath_beacon_alloc(sc, vif);
2327 ath_beacon_config(sc, vif);
2328 ath9k_set_beaconing_status(sc, true);
2331 if (changed & BSS_CHANGED_ERP_SLOT) {
2332 if (bss_conf->use_short_slot)
2336 if (vif->type == NL80211_IFTYPE_AP) {
2338 * Defer update, so that connected stations can adjust
2339 * their settings at the same time.
2340 * See beacon.c for more details
2342 sc->beacon.slottime = slottime;
2343 sc->beacon.updateslot = UPDATE;
2345 ah->slottime = slottime;
2346 ath9k_hw_init_global_settings(ah);
2350 /* Disable transmission of beacons */
2351 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2352 !bss_conf->enable_beacon) {
2353 ath9k_set_beaconing_status(sc, false);
2354 avp->is_bslot_active = false;
2355 ath9k_set_beaconing_status(sc, true);
2358 if (changed & BSS_CHANGED_BEACON_INT) {
2360 * In case of AP mode, the HW TSF has to be reset
2361 * when the beacon interval changes.
2363 if (vif->type == NL80211_IFTYPE_AP) {
2364 sc->sc_flags |= SC_OP_TSF_RESET;
2365 ath9k_set_beaconing_status(sc, false);
2366 error = ath_beacon_alloc(sc, vif);
2368 ath_beacon_config(sc, vif);
2369 ath9k_set_beaconing_status(sc, true);
2371 ath_beacon_config(sc, vif);
2374 mutex_unlock(&sc->mutex);
2375 ath9k_ps_restore(sc);
2378 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2380 struct ath_softc *sc = hw->priv;
2383 mutex_lock(&sc->mutex);
2384 ath9k_ps_wakeup(sc);
2385 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2386 ath9k_ps_restore(sc);
2387 mutex_unlock(&sc->mutex);
2392 static void ath9k_set_tsf(struct ieee80211_hw *hw,
2393 struct ieee80211_vif *vif,
2396 struct ath_softc *sc = hw->priv;
2398 mutex_lock(&sc->mutex);
2399 ath9k_ps_wakeup(sc);
2400 ath9k_hw_settsf64(sc->sc_ah, tsf);
2401 ath9k_ps_restore(sc);
2402 mutex_unlock(&sc->mutex);
2405 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2407 struct ath_softc *sc = hw->priv;
2409 mutex_lock(&sc->mutex);
2411 ath9k_ps_wakeup(sc);
2412 ath9k_hw_reset_tsf(sc->sc_ah);
2413 ath9k_ps_restore(sc);
2415 mutex_unlock(&sc->mutex);
2418 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2419 struct ieee80211_vif *vif,
2420 enum ieee80211_ampdu_mlme_action action,
2421 struct ieee80211_sta *sta,
2422 u16 tid, u16 *ssn, u8 buf_size)
2424 struct ath_softc *sc = hw->priv;
2430 case IEEE80211_AMPDU_RX_START:
2432 case IEEE80211_AMPDU_RX_STOP:
2434 case IEEE80211_AMPDU_TX_START:
2435 ath9k_ps_wakeup(sc);
2436 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2438 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2439 ath9k_ps_restore(sc);
2441 case IEEE80211_AMPDU_TX_STOP:
2442 ath9k_ps_wakeup(sc);
2443 ath_tx_aggr_stop(sc, sta, tid);
2444 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2445 ath9k_ps_restore(sc);
2447 case IEEE80211_AMPDU_TX_OPERATIONAL:
2448 ath9k_ps_wakeup(sc);
2449 ath_tx_aggr_resume(sc, sta, tid);
2450 ath9k_ps_restore(sc);
2453 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2461 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2462 struct survey_info *survey)
2464 struct ath_softc *sc = hw->priv;
2465 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2466 struct ieee80211_supported_band *sband;
2467 struct ieee80211_channel *chan;
2468 unsigned long flags;
2471 spin_lock_irqsave(&common->cc_lock, flags);
2473 ath_update_survey_stats(sc);
2475 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2476 if (sband && idx >= sband->n_channels) {
2477 idx -= sband->n_channels;
2482 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
2484 if (!sband || idx >= sband->n_channels) {
2485 spin_unlock_irqrestore(&common->cc_lock, flags);
2489 chan = &sband->channels[idx];
2490 pos = chan->hw_value;
2491 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2492 survey->channel = chan;
2493 spin_unlock_irqrestore(&common->cc_lock, flags);
2498 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2500 struct ath_softc *sc = hw->priv;
2501 struct ath_hw *ah = sc->sc_ah;
2503 mutex_lock(&sc->mutex);
2504 ah->coverage_class = coverage_class;
2506 ath9k_ps_wakeup(sc);
2507 ath9k_hw_init_global_settings(ah);
2508 ath9k_ps_restore(sc);
2510 mutex_unlock(&sc->mutex);
2513 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2515 struct ath_softc *sc = hw->priv;
2516 struct ath_hw *ah = sc->sc_ah;
2517 struct ath_common *common = ath9k_hw_common(ah);
2518 int timeout = 200; /* ms */
2522 mutex_lock(&sc->mutex);
2523 cancel_delayed_work_sync(&sc->tx_complete_work);
2525 if (ah->ah_flags & AH_UNPLUGGED) {
2526 ath_dbg(common, ANY, "Device has been unplugged!\n");
2527 mutex_unlock(&sc->mutex);
2531 if (sc->sc_flags & SC_OP_INVALID) {
2532 ath_dbg(common, ANY, "Device not present\n");
2533 mutex_unlock(&sc->mutex);
2537 for (j = 0; j < timeout; j++) {
2541 usleep_range(1000, 2000);
2543 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2544 if (!ATH_TXQ_SETUP(sc, i))
2547 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2558 ath9k_ps_wakeup(sc);
2559 spin_lock_bh(&sc->sc_pcu_lock);
2560 drain_txq = ath_drain_all_txq(sc, false);
2561 spin_unlock_bh(&sc->sc_pcu_lock);
2564 ath_reset(sc, false);
2566 ath9k_ps_restore(sc);
2567 ieee80211_wake_queues(hw);
2570 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2571 mutex_unlock(&sc->mutex);
2574 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2576 struct ath_softc *sc = hw->priv;
2579 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2580 if (!ATH_TXQ_SETUP(sc, i))
2583 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2589 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2591 struct ath_softc *sc = hw->priv;
2592 struct ath_hw *ah = sc->sc_ah;
2593 struct ieee80211_vif *vif;
2594 struct ath_vif *avp;
2596 struct ath_tx_status ts;
2597 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2600 vif = sc->beacon.bslot[0];
2604 avp = (void *)vif->drv_priv;
2605 if (!avp->is_bslot_active)
2608 if (!sc->beacon.tx_processed && !edma) {
2609 tasklet_disable(&sc->bcon_tasklet);
2612 if (!bf || !bf->bf_mpdu)
2615 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2616 if (status == -EINPROGRESS)
2619 sc->beacon.tx_processed = true;
2620 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2623 tasklet_enable(&sc->bcon_tasklet);
2626 return sc->beacon.tx_last;
2629 static int ath9k_get_stats(struct ieee80211_hw *hw,
2630 struct ieee80211_low_level_stats *stats)
2632 struct ath_softc *sc = hw->priv;
2633 struct ath_hw *ah = sc->sc_ah;
2634 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2636 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2637 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2638 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2639 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2643 static u32 fill_chainmask(u32 cap, u32 new)
2648 for (i = 0; cap && new; i++, cap >>= 1) {
2649 if (!(cap & BIT(0)))
2661 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2663 struct ath_softc *sc = hw->priv;
2664 struct ath_hw *ah = sc->sc_ah;
2666 if (!rx_ant || !tx_ant)
2669 sc->ant_rx = rx_ant;
2670 sc->ant_tx = tx_ant;
2672 if (ah->caps.rx_chainmask == 1)
2675 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2676 if (AR_SREV_9100(ah))
2677 ah->rxchainmask = 0x7;
2679 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2681 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2682 ath9k_reload_chainmask_settings(sc);
2687 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2689 struct ath_softc *sc = hw->priv;
2691 *tx_ant = sc->ant_tx;
2692 *rx_ant = sc->ant_rx;
2696 struct ieee80211_ops ath9k_ops = {
2698 .start = ath9k_start,
2700 .add_interface = ath9k_add_interface,
2701 .change_interface = ath9k_change_interface,
2702 .remove_interface = ath9k_remove_interface,
2703 .config = ath9k_config,
2704 .configure_filter = ath9k_configure_filter,
2705 .sta_add = ath9k_sta_add,
2706 .sta_remove = ath9k_sta_remove,
2707 .sta_notify = ath9k_sta_notify,
2708 .conf_tx = ath9k_conf_tx,
2709 .bss_info_changed = ath9k_bss_info_changed,
2710 .set_key = ath9k_set_key,
2711 .get_tsf = ath9k_get_tsf,
2712 .set_tsf = ath9k_set_tsf,
2713 .reset_tsf = ath9k_reset_tsf,
2714 .ampdu_action = ath9k_ampdu_action,
2715 .get_survey = ath9k_get_survey,
2716 .rfkill_poll = ath9k_rfkill_poll_state,
2717 .set_coverage_class = ath9k_set_coverage_class,
2718 .flush = ath9k_flush,
2719 .tx_frames_pending = ath9k_tx_frames_pending,
2720 .tx_last_beacon = ath9k_tx_last_beacon,
2721 .get_stats = ath9k_get_stats,
2722 .set_antenna = ath9k_set_antenna,
2723 .get_antenna = ath9k_get_antenna,