1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 * Copyright(c) 2016 Intel Deutschland GmbH
7 * Portions of this file are derived from the ipw3945 project, as well
8 * as portions of the ieee80211 subsystem header files.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
23 * The full GNU General Public License is included in this distribution in the
24 * file called LICENSE.
26 * Contact Information:
27 * Intel Linux Wireless <linuxwifi@intel.com>
28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *****************************************************************************/
31 #include <linux/etherdevice.h>
32 #include <linux/ieee80211.h>
33 #include <linux/slab.h>
34 #include <linux/sched.h>
35 #include <linux/pm_runtime.h>
36 #include <net/ip6_checksum.h>
39 #include "iwl-debug.h"
44 #include "iwl-op-mode.h"
46 /* FIXME: need to abstract out TX command (once we know what it looks like) */
47 #include "dvm/commands.h"
49 #define IWL_TX_CRC_SIZE 4
50 #define IWL_TX_DELIMITER_SIZE 4
52 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
57 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
58 * of buffer descriptors, each of which points to one or more data buffers for
59 * the device to read from or fill. Driver and device exchange status of each
60 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
61 * entries in each circular buffer, to protect against confusing empty and full
64 * The device reads or writes the data in the queues via the device's several
65 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
67 * For Tx queue, there are low mark and high mark limits. If, after queuing
68 * the packet for Tx, free space become < low mark, Tx queue stopped. When
69 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
72 ***************************************************/
73 static int iwl_queue_space(const struct iwl_queue *q)
79 * To avoid ambiguity between empty and completely full queues, there
80 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
81 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
82 * to reserve any queue entries for this purpose.
84 if (q->n_window < TFD_QUEUE_SIZE_MAX)
87 max = TFD_QUEUE_SIZE_MAX - 1;
90 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
91 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
93 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
95 if (WARN_ON(used > max))
102 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
104 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
106 q->n_window = slots_num;
109 /* slots_num must be power-of-two size, otherwise
110 * get_cmd_index is broken. */
111 if (WARN_ON(!is_power_of_2(slots_num)))
114 q->low_mark = q->n_window / 4;
118 q->high_mark = q->n_window / 8;
119 if (q->high_mark < 2)
128 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
129 struct iwl_dma_ptr *ptr, size_t size)
131 if (WARN_ON(ptr->addr))
134 ptr->addr = dma_alloc_coherent(trans->dev, size,
135 &ptr->dma, GFP_KERNEL);
142 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
143 struct iwl_dma_ptr *ptr)
145 if (unlikely(!ptr->addr))
148 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
149 memset(ptr, 0, sizeof(*ptr));
152 static void iwl_pcie_txq_stuck_timer(unsigned long data)
154 struct iwl_txq *txq = (void *)data;
155 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
156 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
157 u32 scd_sram_addr = trans_pcie->scd_base_addr +
158 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
162 spin_lock(&txq->lock);
163 /* check if triggered erroneously */
164 if (txq->q.read_ptr == txq->q.write_ptr) {
165 spin_unlock(&txq->lock);
168 spin_unlock(&txq->lock);
170 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
171 jiffies_to_msecs(txq->wd_timeout));
172 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
173 txq->q.read_ptr, txq->q.write_ptr);
175 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
177 iwl_print_hex_error(trans, buf, sizeof(buf));
179 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
180 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
181 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
183 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
184 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
185 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
186 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
188 iwl_trans_read_mem32(trans,
189 trans_pcie->scd_base_addr +
190 SCD_TRANS_TBL_OFFSET_QUEUE(i));
193 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
195 tbl_dw = tbl_dw & 0x0000FFFF;
198 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
199 i, active ? "" : "in", fifo, tbl_dw,
200 iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
201 (TFD_QUEUE_SIZE_MAX - 1),
202 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
205 iwl_force_nmi(trans);
209 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
211 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
212 struct iwl_txq *txq, u16 byte_cnt)
214 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
215 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
216 int write_ptr = txq->q.write_ptr;
217 int txq_id = txq->q.id;
220 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
222 struct iwl_tx_cmd *tx_cmd =
223 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
225 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
227 sta_id = tx_cmd->sta_id;
228 sec_ctl = tx_cmd->sec_ctl;
230 switch (sec_ctl & TX_CMD_SEC_MSK) {
232 len += IEEE80211_CCMP_MIC_LEN;
234 case TX_CMD_SEC_TKIP:
235 len += IEEE80211_TKIP_ICV_LEN;
238 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
242 if (trans_pcie->bc_table_dword)
243 len = DIV_ROUND_UP(len, 4);
245 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
248 bc_ent = cpu_to_le16(len | (sta_id << 12));
250 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
252 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
254 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
257 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
260 struct iwl_trans_pcie *trans_pcie =
261 IWL_TRANS_GET_PCIE_TRANS(trans);
262 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
263 int txq_id = txq->q.id;
264 int read_ptr = txq->q.read_ptr;
267 struct iwl_tx_cmd *tx_cmd =
268 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
270 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
272 if (txq_id != trans_pcie->cmd_queue)
273 sta_id = tx_cmd->sta_id;
275 bc_ent = cpu_to_le16(1 | (sta_id << 12));
276 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
278 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
280 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
284 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
286 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
289 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
291 int txq_id = txq->q.id;
293 lockdep_assert_held(&txq->lock);
296 * explicitly wake up the NIC if:
297 * 1. shadow registers aren't enabled
298 * 2. NIC is woken up for CMD regardless of shadow outside this function
299 * 3. there is a chance that the NIC is asleep
301 if (!trans->cfg->base_params->shadow_reg_enable &&
302 txq_id != trans_pcie->cmd_queue &&
303 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
305 * wake up nic if it's powered down ...
306 * uCode will wake up, and interrupt us again, so next
307 * time we'll skip this part.
309 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
311 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
312 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
314 iwl_set_bit(trans, CSR_GP_CNTRL,
315 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
316 txq->need_update = true;
322 * if not in power-save mode, uCode will never sleep when we're
323 * trying to tx (during RFKILL, we're not trying to tx).
325 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
327 iwl_write32(trans, HBUS_TARG_WRPTR,
328 txq->q.write_ptr | (txq_id << 8));
331 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
333 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
336 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
337 struct iwl_txq *txq = &trans_pcie->txq[i];
339 spin_lock_bh(&txq->lock);
340 if (trans_pcie->txq[i].need_update) {
341 iwl_pcie_txq_inc_wr_ptr(trans, txq);
342 trans_pcie->txq[i].need_update = false;
344 spin_unlock_bh(&txq->lock);
348 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
350 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
352 dma_addr_t addr = get_unaligned_le32(&tb->lo);
353 if (sizeof(dma_addr_t) > sizeof(u32))
355 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
360 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
361 dma_addr_t addr, u16 len)
363 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
364 u16 hi_n_len = len << 4;
366 put_unaligned_le32(addr, &tb->lo);
367 if (sizeof(dma_addr_t) > sizeof(u32))
368 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
370 tb->hi_n_len = cpu_to_le16(hi_n_len);
372 tfd->num_tbs = idx + 1;
375 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
377 return tfd->num_tbs & 0x1f;
380 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
381 struct iwl_cmd_meta *meta,
387 /* Sanity check on number of chunks */
388 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
390 if (num_tbs >= IWL_NUM_OF_TBS) {
391 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
392 /* @todo issue fatal error, it is quite serious situation */
396 /* first TB is never freed - it's the scratchbuf data */
398 for (i = 1; i < num_tbs; i++) {
399 if (meta->flags & BIT(i + CMD_TB_BITMAP_POS))
400 dma_unmap_page(trans->dev,
401 iwl_pcie_tfd_tb_get_addr(tfd, i),
402 iwl_pcie_tfd_tb_get_len(tfd, i),
405 dma_unmap_single(trans->dev,
406 iwl_pcie_tfd_tb_get_addr(tfd, i),
407 iwl_pcie_tfd_tb_get_len(tfd, i),
414 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
415 * @trans - transport private data
417 * @dma_dir - the direction of the DMA mapping
419 * Does NOT advance any TFD circular buffer read/write indexes
420 * Does NOT free the TFD itself (which is within circular buffer)
422 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
424 struct iwl_tfd *tfd_tmp = txq->tfds;
426 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
427 * idx is bounded by n_window
429 int rd_ptr = txq->q.read_ptr;
430 int idx = get_cmd_index(&txq->q, rd_ptr);
432 lockdep_assert_held(&txq->lock);
434 /* We have only q->n_window txq->entries, but we use
435 * TFD_QUEUE_SIZE_MAX tfds
437 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
443 skb = txq->entries[idx].skb;
445 /* Can be called from irqs-disabled context
446 * If skb is not NULL, it means that the whole queue is being
447 * freed and that the queue is not empty - free the skb
450 iwl_op_mode_free_skb(trans->op_mode, skb);
451 txq->entries[idx].skb = NULL;
456 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
457 dma_addr_t addr, u16 len, bool reset)
460 struct iwl_tfd *tfd, *tfd_tmp;
465 tfd = &tfd_tmp[q->write_ptr];
468 memset(tfd, 0, sizeof(*tfd));
470 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
472 /* Each TFD can point to a maximum 20 Tx buffers */
473 if (num_tbs >= IWL_NUM_OF_TBS) {
474 IWL_ERR(trans, "Error can not send more than %d chunks\n",
479 if (WARN(addr & ~IWL_TX_DMA_MASK,
480 "Unaligned address = %llx\n", (unsigned long long)addr))
483 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
488 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
489 struct iwl_txq *txq, int slots_num,
492 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
493 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
494 size_t scratchbuf_sz;
497 if (WARN_ON(txq->entries || txq->tfds))
500 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
502 txq->trans_pcie = trans_pcie;
504 txq->q.n_window = slots_num;
506 txq->entries = kcalloc(slots_num,
507 sizeof(struct iwl_pcie_txq_entry),
513 if (txq_id == trans_pcie->cmd_queue)
514 for (i = 0; i < slots_num; i++) {
515 txq->entries[i].cmd =
516 kmalloc(sizeof(struct iwl_device_cmd),
518 if (!txq->entries[i].cmd)
522 /* Circular buffer of transmit frame descriptors (TFDs),
523 * shared with device */
524 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
525 &txq->q.dma_addr, GFP_KERNEL);
529 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
530 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
531 sizeof(struct iwl_cmd_header) +
532 offsetof(struct iwl_tx_cmd, scratch));
534 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
536 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
537 &txq->scratchbufs_dma,
539 if (!txq->scratchbufs)
546 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
548 if (txq->entries && txq_id == trans_pcie->cmd_queue)
549 for (i = 0; i < slots_num; i++)
550 kfree(txq->entries[i].cmd);
558 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
559 int slots_num, u32 txq_id)
563 txq->need_update = false;
565 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
566 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
567 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
569 /* Initialize queue's high/low-water marks, and head/tail indexes */
570 ret = iwl_queue_init(&txq->q, slots_num, txq_id);
574 spin_lock_init(&txq->lock);
575 __skb_queue_head_init(&txq->overflow_q);
578 * Tell nic where to find circular buffer of Tx Frame Descriptors for
579 * given Tx queue, and enable the DMA channel used for that queue.
580 * Circular buffer (TFD queue in DRAM) physical base address */
581 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
582 txq->q.dma_addr >> 8);
587 static void iwl_pcie_free_tso_page(struct sk_buff *skb)
589 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
591 if (info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA]) {
593 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA];
596 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = NULL;
600 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
602 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
604 lockdep_assert_held(&trans_pcie->reg_lock);
606 if (trans_pcie->ref_cmd_in_flight) {
607 trans_pcie->ref_cmd_in_flight = false;
608 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
609 iwl_trans_unref(trans);
612 if (!trans->cfg->base_params->apmg_wake_up_wa)
614 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
617 trans_pcie->cmd_hold_nic_awake = false;
618 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
619 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
623 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
625 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
627 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
628 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
629 struct iwl_queue *q = &txq->q;
631 spin_lock_bh(&txq->lock);
632 while (q->write_ptr != q->read_ptr) {
633 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
634 txq_id, q->read_ptr);
636 if (txq_id != trans_pcie->cmd_queue) {
637 struct sk_buff *skb = txq->entries[q->read_ptr].skb;
639 if (WARN_ON_ONCE(!skb))
642 iwl_pcie_free_tso_page(skb);
644 iwl_pcie_txq_free_tfd(trans, txq);
645 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
647 if (q->read_ptr == q->write_ptr) {
650 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
651 if (txq_id != trans_pcie->cmd_queue) {
652 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
654 iwl_trans_unref(trans);
656 iwl_pcie_clear_cmd_in_flight(trans);
658 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
663 while (!skb_queue_empty(&txq->overflow_q)) {
664 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
666 iwl_op_mode_free_skb(trans->op_mode, skb);
669 spin_unlock_bh(&txq->lock);
671 /* just in case - this queue may have been stopped */
672 iwl_wake_queue(trans, txq);
676 * iwl_pcie_txq_free - Deallocate DMA queue.
677 * @txq: Transmit queue to deallocate.
679 * Empty queue by removing and destroying all BD's.
681 * 0-fill, but do not free "txq" descriptor structure.
683 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
685 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
686 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
687 struct device *dev = trans->dev;
693 iwl_pcie_txq_unmap(trans, txq_id);
695 /* De-alloc array of command/tx buffers */
696 if (txq_id == trans_pcie->cmd_queue)
697 for (i = 0; i < txq->q.n_window; i++) {
698 kzfree(txq->entries[i].cmd);
699 kzfree(txq->entries[i].free_buf);
702 /* De-alloc circular buffer of TFDs */
704 dma_free_coherent(dev,
705 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
706 txq->tfds, txq->q.dma_addr);
710 dma_free_coherent(dev,
711 sizeof(*txq->scratchbufs) * txq->q.n_window,
712 txq->scratchbufs, txq->scratchbufs_dma);
718 del_timer_sync(&txq->stuck_timer);
720 /* 0-fill queue descriptor structure */
721 memset(txq, 0, sizeof(*txq));
724 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
727 int nq = trans->cfg->base_params->num_of_queues;
730 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
731 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
733 /* make sure all queue are not stopped/used */
734 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
735 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
737 trans_pcie->scd_base_addr =
738 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
740 WARN_ON(scd_base_addr != 0 &&
741 scd_base_addr != trans_pcie->scd_base_addr);
743 /* reset context data, TX status and translation data */
744 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
745 SCD_CONTEXT_MEM_LOWER_BOUND,
748 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
749 trans_pcie->scd_bc_tbls.dma >> 10);
751 /* The chain extension of the SCD doesn't work well. This feature is
752 * enabled by default by the HW, so we need to disable it manually.
754 if (trans->cfg->base_params->scd_chain_ext_wa)
755 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
757 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
758 trans_pcie->cmd_fifo,
759 trans_pcie->cmd_q_wdg_timeout);
761 /* Activate all Tx DMA/FIFO channels */
762 iwl_scd_activate_fifos(trans);
764 /* Enable DMA channel */
765 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
766 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
767 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
768 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
770 /* Update FH chicken bits */
771 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
772 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
773 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
775 /* Enable L1-Active */
776 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
777 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
778 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
781 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
783 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
786 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
788 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
790 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
791 txq->q.dma_addr >> 8);
792 iwl_pcie_txq_unmap(trans, txq_id);
794 txq->q.write_ptr = 0;
797 /* Tell NIC where to find the "keep warm" buffer */
798 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
799 trans_pcie->kw.dma >> 4);
802 * Send 0 as the scd_base_addr since the device may have be reset
803 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
806 iwl_pcie_tx_start(trans, 0);
809 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
811 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
816 spin_lock(&trans_pcie->irq_lock);
818 if (!iwl_trans_grab_nic_access(trans, &flags))
821 /* Stop each Tx DMA channel */
822 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
823 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
824 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
827 /* Wait for DMA channels to be idle */
828 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
831 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
832 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
834 iwl_trans_release_nic_access(trans, &flags);
837 spin_unlock(&trans_pcie->irq_lock);
841 * iwl_pcie_tx_stop - Stop all Tx DMA channels
843 int iwl_pcie_tx_stop(struct iwl_trans *trans)
845 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
848 /* Turn off all Tx DMA fifos */
849 iwl_scd_deactivate_fifos(trans);
851 /* Turn off all Tx DMA channels */
852 iwl_pcie_tx_stop_fh(trans);
855 * This function can be called before the op_mode disabled the
856 * queues. This happens when we have an rfkill interrupt.
857 * Since we stop Tx altogether - mark the queues as stopped.
859 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
860 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
862 /* This can happen: start_hw, stop_device */
863 if (!trans_pcie->txq)
866 /* Unmap DMA from host system and free skb's */
867 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
869 iwl_pcie_txq_unmap(trans, txq_id);
875 * iwl_trans_tx_free - Free TXQ Context
877 * Destroy all TX DMA queues and structures
879 void iwl_pcie_tx_free(struct iwl_trans *trans)
882 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
885 if (trans_pcie->txq) {
887 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
888 iwl_pcie_txq_free(trans, txq_id);
891 kfree(trans_pcie->txq);
892 trans_pcie->txq = NULL;
894 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
896 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
900 * iwl_pcie_tx_alloc - allocate TX context
901 * Allocate all Tx DMA structures and initialize them
903 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
906 int txq_id, slots_num;
907 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
909 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
910 sizeof(struct iwlagn_scd_bc_tbl);
912 /*It is not allowed to alloc twice, so warn when this happens.
913 * We cannot rely on the previous allocation, so free and fail */
914 if (WARN_ON(trans_pcie->txq)) {
919 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
922 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
926 /* Alloc keep-warm buffer */
927 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
929 IWL_ERR(trans, "Keep Warm allocation failed\n");
933 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
934 sizeof(struct iwl_txq), GFP_KERNEL);
935 if (!trans_pcie->txq) {
936 IWL_ERR(trans, "Not enough memory for txq\n");
941 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
942 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
944 slots_num = (txq_id == trans_pcie->cmd_queue) ?
945 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
946 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
949 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
957 iwl_pcie_tx_free(trans);
961 int iwl_pcie_tx_init(struct iwl_trans *trans)
963 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
965 int txq_id, slots_num;
968 if (!trans_pcie->txq) {
969 ret = iwl_pcie_tx_alloc(trans);
975 spin_lock(&trans_pcie->irq_lock);
977 /* Turn off all Tx DMA fifos */
978 iwl_scd_deactivate_fifos(trans);
980 /* Tell NIC where to find the "keep warm" buffer */
981 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
982 trans_pcie->kw.dma >> 4);
984 spin_unlock(&trans_pcie->irq_lock);
986 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
987 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
989 slots_num = (txq_id == trans_pcie->cmd_queue) ?
990 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
991 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
994 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
999 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1000 if (trans->cfg->base_params->num_of_queues > 20)
1001 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1002 SCD_GP_CTRL_ENABLE_31_QUEUES);
1006 /*Upon error, free only if we allocated something */
1008 iwl_pcie_tx_free(trans);
1012 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1014 lockdep_assert_held(&txq->lock);
1016 if (!txq->wd_timeout)
1020 * station is asleep and we send data - that must
1021 * be uAPSD or PS-Poll. Don't rearm the timer.
1027 * if empty delete timer, otherwise move timer forward
1028 * since we're making progress on this queue
1030 if (txq->q.read_ptr == txq->q.write_ptr)
1031 del_timer(&txq->stuck_timer);
1033 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1036 /* Frees buffers until index _not_ inclusive */
1037 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1038 struct sk_buff_head *skbs)
1040 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1041 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1042 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
1043 struct iwl_queue *q = &txq->q;
1046 /* This function is not meant to release cmd queue*/
1047 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1050 spin_lock_bh(&txq->lock);
1053 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1058 if (txq->q.read_ptr == tfd_num)
1061 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1062 txq_id, txq->q.read_ptr, tfd_num, ssn);
1064 /*Since we free until index _not_ inclusive, the one before index is
1065 * the last we will free. This one must be used */
1066 last_to_free = iwl_queue_dec_wrap(tfd_num);
1068 if (!iwl_queue_used(q, last_to_free)) {
1070 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1071 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
1072 q->write_ptr, q->read_ptr);
1076 if (WARN_ON(!skb_queue_empty(skbs)))
1080 q->read_ptr != tfd_num;
1081 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1082 struct sk_buff *skb = txq->entries[txq->q.read_ptr].skb;
1084 if (WARN_ON_ONCE(!skb))
1087 iwl_pcie_free_tso_page(skb);
1089 __skb_queue_tail(skbs, skb);
1091 txq->entries[txq->q.read_ptr].skb = NULL;
1093 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1095 iwl_pcie_txq_free_tfd(trans, txq);
1098 iwl_pcie_txq_progress(txq);
1100 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1101 test_bit(txq_id, trans_pcie->queue_stopped)) {
1102 struct sk_buff_head overflow_skbs;
1104 __skb_queue_head_init(&overflow_skbs);
1105 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1108 * This is tricky: we are in reclaim path which is non
1109 * re-entrant, so noone will try to take the access the
1110 * txq data from that path. We stopped tx, so we can't
1111 * have tx as well. Bottom line, we can unlock and re-lock
1114 spin_unlock_bh(&txq->lock);
1116 while (!skb_queue_empty(&overflow_skbs)) {
1117 struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1118 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1119 u8 dev_cmd_idx = IWL_TRANS_FIRST_DRIVER_DATA + 1;
1120 struct iwl_device_cmd *dev_cmd =
1121 info->driver_data[dev_cmd_idx];
1124 * Note that we can very well be overflowing again.
1125 * In that case, iwl_queue_space will be small again
1126 * and we won't wake mac80211's queue.
1128 iwl_trans_pcie_tx(trans, skb, dev_cmd, txq_id);
1130 spin_lock_bh(&txq->lock);
1132 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1133 iwl_wake_queue(trans, txq);
1136 if (q->read_ptr == q->write_ptr) {
1137 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
1138 iwl_trans_unref(trans);
1142 spin_unlock_bh(&txq->lock);
1145 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1146 const struct iwl_host_cmd *cmd)
1148 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1151 lockdep_assert_held(&trans_pcie->reg_lock);
1153 if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1154 !trans_pcie->ref_cmd_in_flight) {
1155 trans_pcie->ref_cmd_in_flight = true;
1156 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1157 iwl_trans_ref(trans);
1161 * wake up the NIC to make sure that the firmware will see the host
1162 * command - we will let the NIC sleep once all the host commands
1163 * returned. This needs to be done only on NICs that have
1164 * apmg_wake_up_wa set.
1166 if (trans->cfg->base_params->apmg_wake_up_wa &&
1167 !trans_pcie->cmd_hold_nic_awake) {
1168 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1169 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1171 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1172 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1173 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1174 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1177 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1178 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1179 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1182 trans_pcie->cmd_hold_nic_awake = true;
1189 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1191 * When FW advances 'R' index, all entries between old and new 'R' index
1192 * need to be reclaimed. As result, some free space forms. If there is
1193 * enough free space (> low mark), wake the stack that feeds us.
1195 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1197 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1198 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1199 struct iwl_queue *q = &txq->q;
1200 unsigned long flags;
1203 lockdep_assert_held(&txq->lock);
1205 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1207 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1208 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1209 q->write_ptr, q->read_ptr);
1213 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1214 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1217 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1218 idx, q->write_ptr, q->read_ptr);
1219 iwl_force_nmi(trans);
1223 if (q->read_ptr == q->write_ptr) {
1224 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1225 iwl_pcie_clear_cmd_in_flight(trans);
1226 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1229 iwl_pcie_txq_progress(txq);
1232 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1235 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1240 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1242 tbl_dw_addr = trans_pcie->scd_base_addr +
1243 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1245 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1248 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1250 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1252 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1257 /* Receiver address (actually, Rx station's index into station table),
1258 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1259 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1261 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1262 const struct iwl_trans_txq_scd_cfg *cfg,
1263 unsigned int wdg_timeout)
1265 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1266 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1269 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1270 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1272 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1277 /* Disable the scheduler prior configuring the cmd queue */
1278 if (txq_id == trans_pcie->cmd_queue &&
1279 trans_pcie->scd_set_active)
1280 iwl_scd_enable_set_active(trans, 0);
1282 /* Stop this Tx queue before configuring it */
1283 iwl_scd_txq_set_inactive(trans, txq_id);
1285 /* Set this queue as a chain-building queue unless it is CMD */
1286 if (txq_id != trans_pcie->cmd_queue)
1287 iwl_scd_txq_set_chain(trans, txq_id);
1289 if (cfg->aggregate) {
1290 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1292 /* Map receiver-address / traffic-ID to this queue */
1293 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1295 /* enable aggregations for the queue */
1296 iwl_scd_txq_enable_agg(trans, txq_id);
1300 * disable aggregations for the queue, this will also
1301 * make the ra_tid mapping configuration irrelevant
1302 * since it is now a non-AGG queue.
1304 iwl_scd_txq_disable_agg(trans, txq_id);
1306 ssn = txq->q.read_ptr;
1310 /* Place first TFD at index corresponding to start sequence number.
1311 * Assumes that ssn_idx is valid (!= 0xFFF) */
1312 txq->q.read_ptr = (ssn & 0xff);
1313 txq->q.write_ptr = (ssn & 0xff);
1314 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1315 (ssn & 0xff) | (txq_id << 8));
1318 u8 frame_limit = cfg->frame_limit;
1320 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1322 /* Set up Tx window size and frame limit for this queue */
1323 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1324 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1325 iwl_trans_write_mem32(trans,
1326 trans_pcie->scd_base_addr +
1327 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1328 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1329 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1330 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1331 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1333 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1334 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1335 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1336 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1337 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1338 SCD_QUEUE_STTS_REG_MSK);
1340 /* enable the scheduler for this queue (only) */
1341 if (txq_id == trans_pcie->cmd_queue &&
1342 trans_pcie->scd_set_active)
1343 iwl_scd_enable_set_active(trans, BIT(txq_id));
1345 IWL_DEBUG_TX_QUEUES(trans,
1346 "Activate queue %d on FIFO %d WrPtr: %d\n",
1347 txq_id, fifo, ssn & 0xff);
1349 IWL_DEBUG_TX_QUEUES(trans,
1350 "Activate queue %d WrPtr: %d\n",
1351 txq_id, ssn & 0xff);
1357 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1360 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1361 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1363 txq->ampdu = !shared_mode;
1366 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1369 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1370 u32 stts_addr = trans_pcie->scd_base_addr +
1371 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1372 static const u32 zero_val[4] = {};
1374 trans_pcie->txq[txq_id].frozen_expiry_remainder = 0;
1375 trans_pcie->txq[txq_id].frozen = false;
1378 * Upon HW Rfkill - we stop the device, and then stop the queues
1379 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1380 * allow the op_mode to call txq_disable after it already called
1383 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1384 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1385 "queue %d not used", txq_id);
1389 if (configure_scd) {
1390 iwl_scd_txq_set_inactive(trans, txq_id);
1392 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1393 ARRAY_SIZE(zero_val));
1396 iwl_pcie_txq_unmap(trans, txq_id);
1397 trans_pcie->txq[txq_id].ampdu = false;
1399 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1402 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1405 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1406 * @priv: device private data point
1407 * @cmd: a pointer to the ucode command structure
1409 * The function returns < 0 values to indicate the operation
1410 * failed. On success, it returns the index (>= 0) of command in the
1413 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1414 struct iwl_host_cmd *cmd)
1416 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1417 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1418 struct iwl_queue *q = &txq->q;
1419 struct iwl_device_cmd *out_cmd;
1420 struct iwl_cmd_meta *out_meta;
1421 unsigned long flags;
1422 void *dup_buf = NULL;
1423 dma_addr_t phys_addr;
1425 u16 copy_size, cmd_size, scratch_size;
1426 bool had_nocopy = false;
1427 u8 group_id = iwl_cmd_groupid(cmd->id);
1430 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1431 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1433 if (WARN(!trans_pcie->wide_cmd_header &&
1434 group_id > IWL_ALWAYS_LONG_GROUP,
1435 "unsupported wide command %#x\n", cmd->id))
1438 if (group_id != 0) {
1439 copy_size = sizeof(struct iwl_cmd_header_wide);
1440 cmd_size = sizeof(struct iwl_cmd_header_wide);
1442 copy_size = sizeof(struct iwl_cmd_header);
1443 cmd_size = sizeof(struct iwl_cmd_header);
1446 /* need one for the header if the first is NOCOPY */
1447 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1449 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1450 cmddata[i] = cmd->data[i];
1451 cmdlen[i] = cmd->len[i];
1456 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1457 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1458 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1460 if (copy > cmdlen[i])
1467 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1469 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1473 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1475 * This is also a chunk that isn't copied
1476 * to the static buffer so set had_nocopy.
1480 /* only allowed once */
1481 if (WARN_ON(dup_buf)) {
1486 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1491 /* NOCOPY must not be followed by normal! */
1492 if (WARN_ON(had_nocopy)) {
1496 copy_size += cmdlen[i];
1498 cmd_size += cmd->len[i];
1502 * If any of the command structures end up being larger than
1503 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1504 * allocated into separate TFDs, then we will need to
1505 * increase the size of the buffers.
1507 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1508 "Command %s (%#x) is too large (%d bytes)\n",
1509 iwl_get_cmd_string(trans, cmd->id),
1510 cmd->id, copy_size)) {
1515 spin_lock_bh(&txq->lock);
1517 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1518 spin_unlock_bh(&txq->lock);
1520 IWL_ERR(trans, "No space in command queue\n");
1521 iwl_op_mode_cmd_queue_full(trans->op_mode);
1526 idx = get_cmd_index(q, q->write_ptr);
1527 out_cmd = txq->entries[idx].cmd;
1528 out_meta = &txq->entries[idx].meta;
1530 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1531 if (cmd->flags & CMD_WANT_SKB)
1532 out_meta->source = cmd;
1534 /* set up the header */
1535 if (group_id != 0) {
1536 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1537 out_cmd->hdr_wide.group_id = group_id;
1538 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1539 out_cmd->hdr_wide.length =
1540 cpu_to_le16(cmd_size -
1541 sizeof(struct iwl_cmd_header_wide));
1542 out_cmd->hdr_wide.reserved = 0;
1543 out_cmd->hdr_wide.sequence =
1544 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1545 INDEX_TO_SEQ(q->write_ptr));
1547 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1548 copy_size = sizeof(struct iwl_cmd_header_wide);
1550 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1551 out_cmd->hdr.sequence =
1552 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1553 INDEX_TO_SEQ(q->write_ptr));
1554 out_cmd->hdr.group_id = 0;
1556 cmd_pos = sizeof(struct iwl_cmd_header);
1557 copy_size = sizeof(struct iwl_cmd_header);
1560 /* and copy the data that needs to be copied */
1561 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1567 /* copy everything if not nocopy/dup */
1568 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1569 IWL_HCMD_DFL_DUP))) {
1572 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1579 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1580 * in total (for the scratchbuf handling), but copy up to what
1581 * we can fit into the payload for debug dump purposes.
1583 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1585 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1588 /* However, treat copy_size the proper way, we need it below */
1589 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1590 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1592 if (copy > cmd->len[i])
1599 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1600 iwl_get_cmd_string(trans, cmd->id),
1601 group_id, out_cmd->hdr.cmd,
1602 le16_to_cpu(out_cmd->hdr.sequence),
1603 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1605 /* start the TFD with the scratchbuf */
1606 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1607 memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size);
1608 iwl_pcie_txq_build_tfd(trans, txq,
1609 iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr),
1610 scratch_size, true);
1612 /* map first command fragment, if any remains */
1613 if (copy_size > scratch_size) {
1614 phys_addr = dma_map_single(trans->dev,
1615 ((u8 *)&out_cmd->hdr) + scratch_size,
1616 copy_size - scratch_size,
1618 if (dma_mapping_error(trans->dev, phys_addr)) {
1619 iwl_pcie_tfd_unmap(trans, out_meta,
1620 &txq->tfds[q->write_ptr]);
1625 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1626 copy_size - scratch_size, false);
1629 /* map the remaining (adjusted) nocopy/dup fragments */
1630 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1631 const void *data = cmddata[i];
1635 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1638 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1640 phys_addr = dma_map_single(trans->dev, (void *)data,
1641 cmdlen[i], DMA_TO_DEVICE);
1642 if (dma_mapping_error(trans->dev, phys_addr)) {
1643 iwl_pcie_tfd_unmap(trans, out_meta,
1644 &txq->tfds[q->write_ptr]);
1649 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1652 BUILD_BUG_ON(IWL_NUM_OF_TBS + CMD_TB_BITMAP_POS >
1653 sizeof(out_meta->flags) * BITS_PER_BYTE);
1654 out_meta->flags = cmd->flags;
1655 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1656 kzfree(txq->entries[idx].free_buf);
1657 txq->entries[idx].free_buf = dup_buf;
1659 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1661 /* start timer if queue currently empty */
1662 if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1663 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1665 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1666 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1669 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1673 /* Increment and update queue's write index */
1674 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1675 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1677 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1680 spin_unlock_bh(&txq->lock);
1688 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1689 * @rxb: Rx buffer to reclaim
1691 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1692 struct iwl_rx_cmd_buffer *rxb)
1694 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1695 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1696 u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id);
1698 int txq_id = SEQ_TO_QUEUE(sequence);
1699 int index = SEQ_TO_INDEX(sequence);
1701 struct iwl_device_cmd *cmd;
1702 struct iwl_cmd_meta *meta;
1703 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1704 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1706 /* If a Tx command is being handled and it isn't in the actual
1707 * command queue then there a command routing bug has been introduced
1708 * in the queue management code. */
1709 if (WARN(txq_id != trans_pcie->cmd_queue,
1710 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1711 txq_id, trans_pcie->cmd_queue, sequence,
1712 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1713 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1714 iwl_print_hex_error(trans, pkt, 32);
1718 spin_lock_bh(&txq->lock);
1720 cmd_index = get_cmd_index(&txq->q, index);
1721 cmd = txq->entries[cmd_index].cmd;
1722 meta = &txq->entries[cmd_index].meta;
1723 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1725 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1727 /* Input error checking is done when commands are added to queue. */
1728 if (meta->flags & CMD_WANT_SKB) {
1729 struct page *p = rxb_steal_page(rxb);
1731 meta->source->resp_pkt = pkt;
1732 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1733 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1736 if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1737 iwl_op_mode_async_cb(trans->op_mode, cmd);
1739 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1741 if (!(meta->flags & CMD_ASYNC)) {
1742 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1744 "HCMD_ACTIVE already clear for command %s\n",
1745 iwl_get_cmd_string(trans, cmd_id));
1747 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1748 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1749 iwl_get_cmd_string(trans, cmd_id));
1750 wake_up(&trans_pcie->wait_command_queue);
1753 if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1754 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1755 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1756 set_bit(STATUS_TRANS_IDLE, &trans->status);
1757 wake_up(&trans_pcie->d0i3_waitq);
1760 if (meta->flags & CMD_WAKE_UP_TRANS) {
1761 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1762 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1763 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1764 wake_up(&trans_pcie->d0i3_waitq);
1769 spin_unlock_bh(&txq->lock);
1772 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1774 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1775 struct iwl_host_cmd *cmd)
1779 /* An asynchronous command can not expect an SKB to be set. */
1780 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1783 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1786 "Error sending %s: enqueue_hcmd failed: %d\n",
1787 iwl_get_cmd_string(trans, cmd->id), ret);
1793 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1794 struct iwl_host_cmd *cmd)
1796 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1800 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1801 iwl_get_cmd_string(trans, cmd->id));
1803 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1805 "Command %s: a command is already active!\n",
1806 iwl_get_cmd_string(trans, cmd->id)))
1809 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1810 iwl_get_cmd_string(trans, cmd->id));
1812 if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
1813 ret = wait_event_timeout(trans_pcie->d0i3_waitq,
1814 pm_runtime_active(&trans_pcie->pci_dev->dev),
1815 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
1817 IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
1822 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1825 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1827 "Error sending %s: enqueue_hcmd failed: %d\n",
1828 iwl_get_cmd_string(trans, cmd->id), ret);
1832 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1833 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1835 HOST_COMPLETE_TIMEOUT);
1837 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1838 struct iwl_queue *q = &txq->q;
1840 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1841 iwl_get_cmd_string(trans, cmd->id),
1842 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1844 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1845 q->read_ptr, q->write_ptr);
1847 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1848 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1849 iwl_get_cmd_string(trans, cmd->id));
1852 iwl_force_nmi(trans);
1853 iwl_trans_fw_error(trans);
1858 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1859 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1860 iwl_get_cmd_string(trans, cmd->id));
1866 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1867 test_bit(STATUS_RFKILL, &trans->status)) {
1868 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1873 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1874 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1875 iwl_get_cmd_string(trans, cmd->id));
1883 if (cmd->flags & CMD_WANT_SKB) {
1885 * Cancel the CMD_WANT_SKB flag for the cmd in the
1886 * TX cmd queue. Otherwise in case the cmd comes
1887 * in later, it will possibly set an invalid
1888 * address (cmd->meta.source).
1890 trans_pcie->txq[trans_pcie->cmd_queue].
1891 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1894 if (cmd->resp_pkt) {
1896 cmd->resp_pkt = NULL;
1902 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1904 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1905 test_bit(STATUS_RFKILL, &trans->status)) {
1906 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1911 if (cmd->flags & CMD_ASYNC)
1912 return iwl_pcie_send_hcmd_async(trans, cmd);
1914 /* We still can fail on RFKILL that can be asserted while we wait */
1915 return iwl_pcie_send_hcmd_sync(trans, cmd);
1918 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1919 struct iwl_txq *txq, u8 hdr_len,
1920 struct iwl_cmd_meta *out_meta,
1921 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1923 struct iwl_queue *q = &txq->q;
1928 * Set up TFD's third entry to point directly to remainder
1929 * of skb's head, if any
1931 tb2_len = skb_headlen(skb) - hdr_len;
1934 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1935 skb->data + hdr_len,
1936 tb2_len, DMA_TO_DEVICE);
1937 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1938 iwl_pcie_tfd_unmap(trans, out_meta,
1939 &txq->tfds[q->write_ptr]);
1942 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1945 /* set up the remaining entries to point to the data */
1946 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1947 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1951 if (!skb_frag_size(frag))
1954 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1955 skb_frag_size(frag), DMA_TO_DEVICE);
1957 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
1958 iwl_pcie_tfd_unmap(trans, out_meta,
1959 &txq->tfds[q->write_ptr]);
1962 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1963 skb_frag_size(frag), false);
1965 out_meta->flags |= BIT(tb_idx + CMD_TB_BITMAP_POS);
1968 trace_iwlwifi_dev_tx(trans->dev, skb,
1969 &txq->tfds[txq->q.write_ptr],
1970 sizeof(struct iwl_tfd),
1971 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1972 skb->data + hdr_len, tb2_len);
1973 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1974 hdr_len, skb->len - hdr_len);
1979 static struct iwl_tso_hdr_page *
1980 get_page_hdr(struct iwl_trans *trans, size_t len)
1982 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1983 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
1988 /* enough room on this page */
1989 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
1992 /* We don't have enough room on this page, get a new one. */
1993 __free_page(p->page);
1996 p->page = alloc_page(GFP_ATOMIC);
1999 p->pos = page_address(p->page);
2003 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2004 bool ipv6, unsigned int len)
2007 struct ipv6hdr *iphv6 = iph;
2009 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2010 len + tcph->doff * 4,
2013 struct iphdr *iphv4 = iph;
2015 ip_send_check(iphv4);
2016 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2017 len + tcph->doff * 4,
2022 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2023 struct iwl_txq *txq, u8 hdr_len,
2024 struct iwl_cmd_meta *out_meta,
2025 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2027 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2028 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2029 struct ieee80211_hdr *hdr = (void *)skb->data;
2030 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2031 unsigned int mss = skb_shinfo(skb)->gso_size;
2032 struct iwl_queue *q = &txq->q;
2033 u16 length, iv_len, amsdu_pad;
2035 struct iwl_tso_hdr_page *hdr_page;
2039 /* if the packet is protected, then it must be CCMP or GCMP */
2040 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2041 iv_len = ieee80211_has_protected(hdr->frame_control) ?
2042 IEEE80211_CCMP_HDR_LEN : 0;
2044 trace_iwlwifi_dev_tx(trans->dev, skb,
2045 &txq->tfds[txq->q.write_ptr],
2046 sizeof(struct iwl_tfd),
2047 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
2050 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2051 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2052 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2055 /* total amount of header we may need for this A-MSDU */
2056 hdr_room = DIV_ROUND_UP(total_len, mss) *
2057 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2059 /* Our device supports 9 segments at most, it will fit in 1 page */
2060 hdr_page = get_page_hdr(trans, hdr_room);
2064 get_page(hdr_page->page);
2065 start_hdr = hdr_page->pos;
2066 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = hdr_page->page;
2067 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2068 hdr_page->pos += iv_len;
2071 * Pull the ieee80211 header + IV to be able to use TSO core,
2072 * we will restore it for the tx_status flow.
2074 skb_pull(skb, hdr_len + iv_len);
2076 tso_start(skb, &tso);
2079 /* this is the data left for this subframe */
2080 unsigned int data_left =
2081 min_t(unsigned int, mss, total_len);
2082 struct sk_buff *csum_skb = NULL;
2083 unsigned int hdr_tb_len;
2084 dma_addr_t hdr_tb_phys;
2085 struct tcphdr *tcph;
2088 total_len -= data_left;
2090 memset(hdr_page->pos, 0, amsdu_pad);
2091 hdr_page->pos += amsdu_pad;
2092 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2094 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2095 hdr_page->pos += ETH_ALEN;
2096 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2097 hdr_page->pos += ETH_ALEN;
2099 length = snap_ip_tcp_hdrlen + data_left;
2100 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2101 hdr_page->pos += sizeof(length);
2104 * This will copy the SNAP as well which will be considered
2107 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2108 iph = hdr_page->pos + 8;
2109 tcph = (void *)(iph + ip_hdrlen);
2111 /* For testing on current hardware only */
2112 if (trans_pcie->sw_csum_tx) {
2113 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2120 iwl_compute_pseudo_hdr_csum(iph, tcph,
2125 memcpy(skb_put(csum_skb, tcp_hdrlen(skb)),
2126 tcph, tcp_hdrlen(skb));
2127 skb_set_transport_header(csum_skb, 0);
2128 csum_skb->csum_start =
2129 (unsigned char *)tcp_hdr(csum_skb) -
2133 hdr_page->pos += snap_ip_tcp_hdrlen;
2135 hdr_tb_len = hdr_page->pos - start_hdr;
2136 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2137 hdr_tb_len, DMA_TO_DEVICE);
2138 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2139 dev_kfree_skb(csum_skb);
2143 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2145 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr,
2148 /* prepare the start_hdr for the next subframe */
2149 start_hdr = hdr_page->pos;
2151 /* put the payload */
2153 unsigned int size = min_t(unsigned int, tso.size,
2157 if (trans_pcie->sw_csum_tx)
2158 memcpy(skb_put(csum_skb, size), tso.data, size);
2160 tb_phys = dma_map_single(trans->dev, tso.data,
2161 size, DMA_TO_DEVICE);
2162 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2163 dev_kfree_skb(csum_skb);
2168 iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2170 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
2174 tso_build_data(skb, &tso, size);
2177 /* For testing on early hardware only */
2178 if (trans_pcie->sw_csum_tx) {
2181 csum = skb_checksum(csum_skb,
2182 skb_checksum_start_offset(csum_skb),
2184 skb_checksum_start_offset(csum_skb),
2186 dev_kfree_skb(csum_skb);
2187 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2188 hdr_tb_len, DMA_TO_DEVICE);
2189 tcph->check = csum_fold(csum);
2190 dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2191 hdr_tb_len, DMA_TO_DEVICE);
2195 /* re -add the WiFi header and IV */
2196 skb_push(skb, hdr_len + iv_len);
2201 iwl_pcie_tfd_unmap(trans, out_meta, &txq->tfds[q->write_ptr]);
2204 #else /* CONFIG_INET */
2205 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2206 struct iwl_txq *txq, u8 hdr_len,
2207 struct iwl_cmd_meta *out_meta,
2208 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2210 /* No A-MSDU without CONFIG_INET */
2215 #endif /* CONFIG_INET */
2217 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2218 struct iwl_device_cmd *dev_cmd, int txq_id)
2220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2221 struct ieee80211_hdr *hdr;
2222 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2223 struct iwl_cmd_meta *out_meta;
2224 struct iwl_txq *txq;
2225 struct iwl_queue *q;
2226 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2229 bool wait_write_ptr;
2235 txq = &trans_pcie->txq[txq_id];
2238 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2239 "TX on unused queue %d\n", txq_id))
2242 if (unlikely(trans_pcie->sw_csum_tx &&
2243 skb->ip_summed == CHECKSUM_PARTIAL)) {
2244 int offs = skb_checksum_start_offset(skb);
2245 int csum_offs = offs + skb->csum_offset;
2248 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2251 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2252 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2254 skb->ip_summed = CHECKSUM_UNNECESSARY;
2257 if (skb_is_nonlinear(skb) &&
2258 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS &&
2259 __skb_linearize(skb))
2262 /* mac80211 always puts the full header into the SKB's head,
2263 * so there's no need to check if it's readable there
2265 hdr = (struct ieee80211_hdr *)skb->data;
2266 fc = hdr->frame_control;
2267 hdr_len = ieee80211_hdrlen(fc);
2269 spin_lock(&txq->lock);
2271 if (iwl_queue_space(q) < q->high_mark) {
2272 iwl_stop_queue(trans, txq);
2274 /* don't put the packet on the ring, if there is no room */
2275 if (unlikely(iwl_queue_space(q) < 3)) {
2276 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2278 info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA + 1] =
2280 __skb_queue_tail(&txq->overflow_q, skb);
2282 spin_unlock(&txq->lock);
2287 /* In AGG mode, the index in the ring must correspond to the WiFi
2288 * sequence number. This is a HW requirements to help the SCD to parse
2290 * Check here that the packets are in the right place on the ring.
2292 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2293 WARN_ONCE(txq->ampdu &&
2294 (wifi_seq & 0xff) != q->write_ptr,
2295 "Q: %d WiFi Seq %d tfdNum %d",
2296 txq_id, wifi_seq, q->write_ptr);
2298 /* Set up driver data for this TFD */
2299 txq->entries[q->write_ptr].skb = skb;
2300 txq->entries[q->write_ptr].cmd = dev_cmd;
2302 dev_cmd->hdr.sequence =
2303 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2304 INDEX_TO_SEQ(q->write_ptr)));
2306 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
2307 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2308 offsetof(struct iwl_tx_cmd, scratch);
2310 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2311 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2313 /* Set up first empty entry in queue's array of Tx/cmd buffers */
2314 out_meta = &txq->entries[q->write_ptr].meta;
2315 out_meta->flags = 0;
2318 * The second TB (tb1) points to the remainder of the TX command
2319 * and the 802.11 header - dword aligned size
2320 * (This calculation modifies the TX command, so do it before the
2321 * setup of the first TB)
2323 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2324 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
2325 /* do not align A-MSDU to dword as the subframe header aligns it */
2326 amsdu = ieee80211_is_data_qos(fc) &&
2327 (*ieee80211_get_qos_ctl(hdr) &
2328 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2329 if (trans_pcie->sw_csum_tx || !amsdu) {
2330 tb1_len = ALIGN(len, 4);
2331 /* Tell NIC about any 2-byte padding after MAC header */
2333 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
2338 /* The first TB points to the scratchbuf data - min_copy bytes */
2339 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
2340 IWL_HCMD_SCRATCHBUF_SIZE);
2341 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2342 IWL_HCMD_SCRATCHBUF_SIZE, true);
2344 /* there must be data left over for TB1 or this code must be changed */
2345 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
2347 /* map the data for TB1 */
2348 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
2349 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2350 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2352 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2355 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2359 } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2360 out_meta, dev_cmd, tb1_len))) {
2364 /* Set up entry for this TFD in Tx byte-count array */
2365 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
2367 wait_write_ptr = ieee80211_has_morefrags(fc);
2369 /* start timer if queue currently empty */
2370 if (q->read_ptr == q->write_ptr) {
2371 if (txq->wd_timeout) {
2373 * If the TXQ is active, then set the timer, if not,
2374 * set the timer in remainder so that the timer will
2375 * be armed with the right value when the station will
2379 mod_timer(&txq->stuck_timer,
2380 jiffies + txq->wd_timeout);
2382 txq->frozen_expiry_remainder = txq->wd_timeout;
2384 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
2385 iwl_trans_ref(trans);
2388 /* Tell device the write index *just past* this latest filled TFD */
2389 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
2390 if (!wait_write_ptr)
2391 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2394 * At this point the frame is "transmitted" successfully
2395 * and we will get a TX status notification eventually.
2397 spin_unlock(&txq->lock);
2400 spin_unlock(&txq->lock);