drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/delay.h>
  34 #include <linux/sched.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/wireless.h>
  38 #include <linux/firmware.h>
  39 #include <linux/etherdevice.h>
  40 #include <asm/unaligned.h>
  41 #include <net/mac80211.h>
  42
  43 #include "iwl-fh.h"
  44 #include "iwl-3945-fh.h"
  45 #include "iwl-commands.h"
  46 #include "iwl-sta.h"
  47 #include "iwl-3945.h"
  48 #include "iwl-eeprom.h"
  49 #include "iwl-core.h"
  50 #include "iwl-helpers.h"
  51 #include "iwl-led.h"
  52 #include "iwl-3945-led.h"
  53 #include "iwl-3945-debugfs.h"
  54
  55 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  56         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  57                                     IWL_RATE_##r##M_IEEE,   \
  58                                     IWL_RATE_##ip##M_INDEX, \
  59                                     IWL_RATE_##in##M_INDEX, \
  60                                     IWL_RATE_##rp##M_INDEX, \
  61                                     IWL_RATE_##rn##M_INDEX, \
  62                                     IWL_RATE_##pp##M_INDEX, \
  63                                     IWL_RATE_##np##M_INDEX, \
  64                                     IWL_RATE_##r##M_INDEX_TABLE, \
  65                                     IWL_RATE_##ip##M_INDEX_TABLE }
  66
  67 /*
  68  * Parameter order:
  69  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  70  *
  71  * If there isn't a valid next or previous rate then INV is used which
  72  * maps to IWL_RATE_INVALID
  73  *
  74  */
  75 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  76         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  77         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  78         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  79         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  80         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  81         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  82         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  83         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  84         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  85         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  86         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  87         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  88 };
  89
  90 /* 1 = enable the iwl3945_disable_events() function */
  91 #define IWL_EVT_DISABLE (0)
  92 #define IWL_EVT_DISABLE_SIZE (1532/32)
  93
  94 /**
  95  * iwl3945_disable_events - Disable selected events in uCode event log
  96  *
  97  * Disable an event by writing "1"s into "disable"
  98  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  99  *   Default values of 0 enable uCode events to be logged.
 100  * Use for only special debugging.  This function is just a placeholder as-is,
 101  *   you'll need to provide the special bits! ...
 102  *   ... and set IWL_EVT_DISABLE to 1. */
 103 void iwl3945_disable_events(struct iwl_priv *priv)
 104 {
 105         int i;
 106         u32 base;               /* SRAM address of event log header */
 107         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 108         u32 array_size;         /* # of u32 entries in array */
 109         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 110                 0x00000000,     /*   31 -    0  Event id numbers */
 111                 0x00000000,     /*   63 -   32 */
 112                 0x00000000,     /*   95 -   64 */
 113                 0x00000000,     /*  127 -   96 */
 114                 0x00000000,     /*  159 -  128 */
 115                 0x00000000,     /*  191 -  160 */
 116                 0x00000000,     /*  223 -  192 */
 117                 0x00000000,     /*  255 -  224 */
 118                 0x00000000,     /*  287 -  256 */
 119                 0x00000000,     /*  319 -  288 */
 120                 0x00000000,     /*  351 -  320 */
 121                 0x00000000,     /*  383 -  352 */
 122                 0x00000000,     /*  415 -  384 */
 123                 0x00000000,     /*  447 -  416 */
 124                 0x00000000,     /*  479 -  448 */
 125                 0x00000000,     /*  511 -  480 */
 126                 0x00000000,     /*  543 -  512 */
 127                 0x00000000,     /*  575 -  544 */
 128                 0x00000000,     /*  607 -  576 */
 129                 0x00000000,     /*  639 -  608 */
 130                 0x00000000,     /*  671 -  640 */
 131                 0x00000000,     /*  703 -  672 */
 132                 0x00000000,     /*  735 -  704 */
 133                 0x00000000,     /*  767 -  736 */
 134                 0x00000000,     /*  799 -  768 */
 135                 0x00000000,     /*  831 -  800 */
 136                 0x00000000,     /*  863 -  832 */
 137                 0x00000000,     /*  895 -  864 */
 138                 0x00000000,     /*  927 -  896 */
 139                 0x00000000,     /*  959 -  928 */
 140                 0x00000000,     /*  991 -  960 */
 141                 0x00000000,     /* 1023 -  992 */
 142                 0x00000000,     /* 1055 - 1024 */
 143                 0x00000000,     /* 1087 - 1056 */
 144                 0x00000000,     /* 1119 - 1088 */
 145                 0x00000000,     /* 1151 - 1120 */
 146                 0x00000000,     /* 1183 - 1152 */
 147                 0x00000000,     /* 1215 - 1184 */
 148                 0x00000000,     /* 1247 - 1216 */
 149                 0x00000000,     /* 1279 - 1248 */
 150                 0x00000000,     /* 1311 - 1280 */
 151                 0x00000000,     /* 1343 - 1312 */
 152                 0x00000000,     /* 1375 - 1344 */
 153                 0x00000000,     /* 1407 - 1376 */
 154                 0x00000000,     /* 1439 - 1408 */
 155                 0x00000000,     /* 1471 - 1440 */
 156                 0x00000000,     /* 1503 - 1472 */
 157         };
 158
 159         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 160         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 161                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 162                 return;
 163         }
 164
 165         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 166         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 167
 168         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 169                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 170                                disable_ptr);
 171                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 172                         iwl_write_targ_mem(priv,
 173                                            disable_ptr + (i * sizeof(u32)),
 174                                            evt_disable[i]);
 175
 176         } else {
 177                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 178                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 179                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 180                                disable_ptr, array_size);
 181         }
 182
 183 }
 184
 185 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 186 {
 187         int idx;
 188
 189         for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
 190                 if (iwl3945_rates[idx].plcp == plcp)
 191                         return idx;
 192         return -1;
 193 }
 194
 195 #ifdef CONFIG_IWLWIFI_DEBUG
 196 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
 197
 198 static const char *iwl3945_get_tx_fail_reason(u32 status)
 199 {
 200         switch (status & TX_STATUS_MSK) {
 201         case TX_3945_STATUS_SUCCESS:
 202                 return "SUCCESS";
 203                 TX_STATUS_ENTRY(SHORT_LIMIT);
 204                 TX_STATUS_ENTRY(LONG_LIMIT);
 205                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 206                 TX_STATUS_ENTRY(MGMNT_ABORT);
 207                 TX_STATUS_ENTRY(NEXT_FRAG);
 208                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 209                 TX_STATUS_ENTRY(DEST_PS);
 210                 TX_STATUS_ENTRY(ABORTED);
 211                 TX_STATUS_ENTRY(BT_RETRY);
 212                 TX_STATUS_ENTRY(STA_INVALID);
 213                 TX_STATUS_ENTRY(FRAG_DROPPED);
 214                 TX_STATUS_ENTRY(TID_DISABLE);
 215                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 216                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 217                 TX_STATUS_ENTRY(TX_LOCKED);
 218                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 219         }
 220
 221         return "UNKNOWN";
 222 }
 223 #else
 224 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 225 {
 226         return "";
 227 }
 228 #endif
 229
 230 /*
 231  * get ieee prev rate from rate scale table.
 232  * for A and B mode we need to overright prev
 233  * value
 234  */
 235 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 236 {
 237         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 238
 239         switch (priv->band) {
 240         case IEEE80211_BAND_5GHZ:
 241                 if (rate == IWL_RATE_12M_INDEX)
 242                         next_rate = IWL_RATE_9M_INDEX;
 243                 else if (rate == IWL_RATE_6M_INDEX)
 244                         next_rate = IWL_RATE_6M_INDEX;
 245                 break;
 246         case IEEE80211_BAND_2GHZ:
 247                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 248                     iwl_is_associated(priv)) {
 249                         if (rate == IWL_RATE_11M_INDEX)
 250                                 next_rate = IWL_RATE_5M_INDEX;
 251                 }
 252                 break;
 253
 254         default:
 255                 break;
 256         }
 257
 258         return next_rate;
 259 }
 260
 261
 262 /**
 263  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 264  *
 265  * When FW advances 'R' index, all entries between old and new 'R' index
 266  * need to be reclaimed. As result, some free space forms. If there is
 267  * enough free space (> low mark), wake the stack that feeds us.
 268  */
 269 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 270                                      int txq_id, int index)
 271 {
 272         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 273         struct iwl_queue *q = &txq->q;
 274         struct iwl_tx_info *tx_info;
 275
 276         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 277
 278         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 279                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 280
 281                 tx_info = &txq->txb[txq->q.read_ptr];
 282                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
 283                 tx_info->skb = NULL;
 284                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 285         }
 286
 287         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 288                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 289                         priv->mac80211_registered)
 290                 iwl_wake_queue(priv, txq_id);
 291 }
 292
 293 /**
 294  * iwl3945_rx_reply_tx - Handle Tx response
 295  */
 296 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 297                                 struct iwl_rx_mem_buffer *rxb)
 298 {
 299         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 300         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 301         int txq_id = SEQ_TO_QUEUE(sequence);
 302         int index = SEQ_TO_INDEX(sequence);
 303         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 304         struct ieee80211_tx_info *info;
 305         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 306         u32  status = le32_to_cpu(tx_resp->status);
 307         int rate_idx;
 308         int fail;
 309
 310         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 311                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 312                           "is out of range [0-%d] %d %d\n", txq_id,
 313                           index, txq->q.n_bd, txq->q.write_ptr,
 314                           txq->q.read_ptr);
 315                 return;
 316         }
 317
 318         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
 319         ieee80211_tx_info_clear_status(info);
 320
 321         /* Fill the MRR chain with some info about on-chip retransmissions */
 322         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 323         if (info->band == IEEE80211_BAND_5GHZ)
 324                 rate_idx -= IWL_FIRST_OFDM_RATE;
 325
 326         fail = tx_resp->failure_frame;
 327
 328         info->status.rates[0].idx = rate_idx;
 329         info->status.rates[0].count = fail + 1; /* add final attempt */
 330
 331         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 332         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 333                                 IEEE80211_TX_STAT_ACK : 0;
 334
 335         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 336                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 337                         tx_resp->rate, tx_resp->failure_frame);
 338
 339         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 340         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 341
 342         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 343                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 344 }
 345
 346
 347
 348 /*****************************************************************************
 349  *
 350  * Intel PRO/Wireless 3945ABG/BG Network Connection
 351  *
 352  *  RX handler implementations
 353  *
 354  *****************************************************************************/
 355 #ifdef CONFIG_IWLWIFI_DEBUGFS
 356 /*
 357  *  based on the assumption of all statistics counter are in DWORD
 358  *  FIXME: This function is for debugging, do not deal with
 359  *  the case of counters roll-over.
 360  */
 361 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
 362                                             __le32 *stats)
 363 {
 364         int i;
 365         __le32 *prev_stats;
 366         u32 *accum_stats;
 367         u32 *delta, *max_delta;
 368
 369         prev_stats = (__le32 *)&priv->_3945.statistics;
 370         accum_stats = (u32 *)&priv->_3945.accum_statistics;
 371         delta = (u32 *)&priv->_3945.delta_statistics;
 372         max_delta = (u32 *)&priv->_3945.max_delta;
 373
 374         for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
 375              i += sizeof(__le32), stats++, prev_stats++, delta++,
 376              max_delta++, accum_stats++) {
 377                 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
 378                         *delta = (le32_to_cpu(*stats) -
 379                                 le32_to_cpu(*prev_stats));
 380                         *accum_stats += *delta;
 381                         if (*delta > *max_delta)
 382                                 *max_delta = *delta;
 383                 }
 384         }
 385
 386         /* reset accumulative statistics for "no-counter" type statistics */
 387         priv->_3945.accum_statistics.general.temperature =
 388                 priv->_3945.statistics.general.temperature;
 389         priv->_3945.accum_statistics.general.ttl_timestamp =
 390                 priv->_3945.statistics.general.ttl_timestamp;
 391 }
 392 #endif
 393
 394 /**
 395  * iwl3945_good_plcp_health - checks for plcp error.
 396  *
 397  * When the plcp error is exceeding the thresholds, reset the radio
 398  * to improve the throughput.
 399  */
 400 static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
 401                                 struct iwl_rx_packet *pkt)
 402 {
 403         bool rc = true;
 404         struct iwl3945_notif_statistics current_stat;
 405         int combined_plcp_delta;
 406         unsigned int plcp_msec;
 407         unsigned long plcp_received_jiffies;
 408
 409         memcpy(&current_stat, pkt->u.raw, sizeof(struct
 410                         iwl3945_notif_statistics));
 411         /*
 412          * check for plcp_err and trigger radio reset if it exceeds
 413          * the plcp error threshold plcp_delta.
 414          */
 415         plcp_received_jiffies = jiffies;
 416         plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
 417                                         (long) priv->plcp_jiffies);
 418         priv->plcp_jiffies = plcp_received_jiffies;
 419         /*
 420          * check to make sure plcp_msec is not 0 to prevent division
 421          * by zero.
 422          */
 423         if (plcp_msec) {
 424                 combined_plcp_delta =
 425                         (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
 426                         le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
 427
 428                 if ((combined_plcp_delta > 0) &&
 429                         ((combined_plcp_delta * 100) / plcp_msec) >
 430                         priv->cfg->plcp_delta_threshold) {
 431                         /*
 432                          * if plcp_err exceed the threshold, the following
 433                          * data is printed in csv format:
 434                          *    Text: plcp_err exceeded %d,
 435                          *    Received ofdm.plcp_err,
 436                          *    Current ofdm.plcp_err,
 437                          *    combined_plcp_delta,
 438                          *    plcp_msec
 439                          */
 440                         IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
 441                                 "%u, %d, %u mSecs\n",
 442                                 priv->cfg->plcp_delta_threshold,
 443                                 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
 444                                 combined_plcp_delta, plcp_msec);
 445                         /*
 446                          * Reset the RF radio due to the high plcp
 447                          * error rate
 448                          */
 449                         rc = false;
 450                 }
 451         }
 452         return rc;
 453 }
 454
 455 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 456                 struct iwl_rx_mem_buffer *rxb)
 457 {
 458         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 459
 460         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 461                      (int)sizeof(struct iwl3945_notif_statistics),
 462                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 463 #ifdef CONFIG_IWLWIFI_DEBUGFS
 464         iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
 465 #endif
 466         iwl_recover_from_statistics(priv, pkt);
 467
 468         memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
 469 }
 470
 471 void iwl3945_reply_statistics(struct iwl_priv *priv,
 472                               struct iwl_rx_mem_buffer *rxb)
 473 {
 474         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 475         __le32 *flag = (__le32 *)&pkt->u.raw;
 476
 477         if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
 478 #ifdef CONFIG_IWLWIFI_DEBUGFS
 479                 memset(&priv->_3945.accum_statistics, 0,
 480                         sizeof(struct iwl3945_notif_statistics));
 481                 memset(&priv->_3945.delta_statistics, 0,
 482                         sizeof(struct iwl3945_notif_statistics));
 483                 memset(&priv->_3945.max_delta, 0,
 484                         sizeof(struct iwl3945_notif_statistics));
 485 #endif
 486                 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
 487         }
 488         iwl3945_hw_rx_statistics(priv, rxb);
 489 }
 490
 491
 492 /******************************************************************************
 493  *
 494  * Misc. internal state and helper functions
 495  *
 496  ******************************************************************************/
 497
 498 /* This is necessary only for a number of statistics, see the caller. */
 499 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 500                 struct ieee80211_hdr *header)
 501 {
 502         /* Filter incoming packets to determine if they are targeted toward
 503          * this network, discarding packets coming from ourselves */
 504         switch (priv->iw_mode) {
 505         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 506                 /* packets to our IBSS update information */
 507                 return !compare_ether_addr(header->addr3, priv->bssid);
 508         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 509                 /* packets to our IBSS update information */
 510                 return !compare_ether_addr(header->addr2, priv->bssid);
 511         default:
 512                 return 1;
 513         }
 514 }
 515
 516 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 517                                    struct iwl_rx_mem_buffer *rxb,
 518                                    struct ieee80211_rx_status *stats)
 519 {
 520         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 521         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 522         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 523         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 524         u16 len = le16_to_cpu(rx_hdr->len);
 525         struct sk_buff *skb;
 526         __le16 fc = hdr->frame_control;
 527
 528         /* We received data from the HW, so stop the watchdog */
 529         if (unlikely(len + IWL39_RX_FRAME_SIZE >
 530                      PAGE_SIZE << priv->hw_params.rx_page_order)) {
 531                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 532                 return;
 533         }
 534
 535         /* We only process data packets if the interface is open */
 536         if (unlikely(!priv->is_open)) {
 537                 IWL_DEBUG_DROP_LIMIT(priv,
 538                         "Dropping packet while interface is not open.\n");
 539                 return;
 540         }
 541
 542         skb = dev_alloc_skb(128);
 543         if (!skb) {
 544                 IWL_ERR(priv, "dev_alloc_skb failed\n");
 545                 return;
 546         }
 547
 548         if (!iwl3945_mod_params.sw_crypto)
 549                 iwl_set_decrypted_flag(priv,
 550                                        (struct ieee80211_hdr *)rxb_addr(rxb),
 551                                        le32_to_cpu(rx_end->status), stats);
 552
 553         skb_add_rx_frag(skb, 0, rxb->page,
 554                         (void *)rx_hdr->payload - (void *)pkt, len);
 555
 556         iwl_update_stats(priv, false, fc, len);
 557         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
 558
 559         ieee80211_rx(priv->hw, skb);
 560         priv->alloc_rxb_page--;
 561         rxb->page = NULL;
 562 }
 563
 564 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 565
 566 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 567                                 struct iwl_rx_mem_buffer *rxb)
 568 {
 569         struct ieee80211_hdr *header;
 570         struct ieee80211_rx_status rx_status;
 571         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 572         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 573         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 574         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 575         u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
 576         u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
 577         u8 network_packet;
 578
 579         rx_status.flag = 0;
 580         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 581         rx_status.freq =
 582                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 583         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 584                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 585
 586         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 587         if (rx_status.band == IEEE80211_BAND_5GHZ)
 588                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 589
 590         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
 591                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 592
 593         /* set the preamble flag if appropriate */
 594         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 595                 rx_status.flag |= RX_FLAG_SHORTPRE;
 596
 597         if ((unlikely(rx_stats->phy_count > 20))) {
 598                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 599                                 rx_stats->phy_count);
 600                 return;
 601         }
 602
 603         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 604             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 605                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 606                 return;
 607         }
 608
 609
 610
 611         /* Convert 3945's rssi indicator to dBm */
 612         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 613
 614         IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
 615                         rx_status.signal, rx_stats_sig_avg,
 616                         rx_stats_noise_diff);
 617
 618         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 619
 620         network_packet = iwl3945_is_network_packet(priv, header);
 621
 622         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
 623                               network_packet ? '*' : ' ',
 624                               le16_to_cpu(rx_hdr->channel),
 625                               rx_status.signal, rx_status.signal,
 626                               rx_status.rate_idx);
 627
 628         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 629
 630         if (network_packet) {
 631                 priv->_3945.last_beacon_time =
 632                         le32_to_cpu(rx_end->beacon_timestamp);
 633                 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
 634                 priv->_3945.last_rx_rssi = rx_status.signal;
 635         }
 636
 637         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 638 }
 639
 640 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 641                                      struct iwl_tx_queue *txq,
 642                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 643 {
 644         int count;
 645         struct iwl_queue *q;
 646         struct iwl3945_tfd *tfd, *tfd_tmp;
 647
 648         q = &txq->q;
 649         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 650         tfd = &tfd_tmp[q->write_ptr];
 651
 652         if (reset)
 653                 memset(tfd, 0, sizeof(*tfd));
 654
 655         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 656
 657         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 658                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 659                           NUM_TFD_CHUNKS);
 660                 return -EINVAL;
 661         }
 662
 663         tfd->tbs[count].addr = cpu_to_le32(addr);
 664         tfd->tbs[count].len = cpu_to_le32(len);
 665
 666         count++;
 667
 668         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 669                                          TFD_CTL_PAD_SET(pad));
 670
 671         return 0;
 672 }
 673
 674 /**
 675  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 676  *
 677  * Does NOT advance any indexes
 678  */
 679 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 680 {
 681         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 682         int index = txq->q.read_ptr;
 683         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 684         struct pci_dev *dev = priv->pci_dev;
 685         int i;
 686         int counter;
 687
 688         /* sanity check */
 689         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 690         if (counter > NUM_TFD_CHUNKS) {
 691                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 692                 /* @todo issue fatal error, it is quite serious situation */
 693                 return;
 694         }
 695
 696         /* Unmap tx_cmd */
 697         if (counter)
 698                 pci_unmap_single(dev,
 699                                 dma_unmap_addr(&txq->meta[index], mapping),
 700                                 dma_unmap_len(&txq->meta[index], len),
 701                                 PCI_DMA_TODEVICE);
 702
 703         /* unmap chunks if any */
 704
 705         for (i = 1; i < counter; i++)
 706                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 707                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 708
 709         /* free SKB */
 710         if (txq->txb) {
 711                 struct sk_buff *skb;
 712
 713                 skb = txq->txb[txq->q.read_ptr].skb;
 714
 715                 /* can be called from irqs-disabled context */
 716                 if (skb) {
 717                         dev_kfree_skb_any(skb);
 718                         txq->txb[txq->q.read_ptr].skb = NULL;
 719                 }
 720         }
 721 }
 722
 723 /**
 724  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 725  *
 726 */
 727 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 728                                   struct iwl_device_cmd *cmd,
 729                                   struct ieee80211_tx_info *info,
 730                                   struct ieee80211_hdr *hdr,
 731                                   int sta_id, int tx_id)
 732 {
 733         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 734         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
 735         u16 rate_mask;
 736         int rate;
 737         u8 rts_retry_limit;
 738         u8 data_retry_limit;
 739         __le32 tx_flags;
 740         __le16 fc = hdr->frame_control;
 741         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 742
 743         rate = iwl3945_rates[rate_index].plcp;
 744         tx_flags = tx_cmd->tx_flags;
 745
 746         /* We need to figure out how to get the sta->supp_rates while
 747          * in this running context */
 748         rate_mask = IWL_RATES_MASK;
 749
 750
 751         /* Set retry limit on DATA packets and Probe Responses*/
 752         if (ieee80211_is_probe_resp(fc))
 753                 data_retry_limit = 3;
 754         else
 755                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 756         tx_cmd->data_retry_limit = data_retry_limit;
 757
 758         if (tx_id >= IWL_CMD_QUEUE_NUM)
 759                 rts_retry_limit = 3;
 760         else
 761                 rts_retry_limit = 7;
 762
 763         if (data_retry_limit < rts_retry_limit)
 764                 rts_retry_limit = data_retry_limit;
 765         tx_cmd->rts_retry_limit = rts_retry_limit;
 766
 767         if (ieee80211_is_mgmt(fc)) {
 768                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 769                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 770                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 771                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 772                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 773                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 774                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 775                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 776                         }
 777                         break;
 778                 default:
 779                         break;
 780                 }
 781         }
 782
 783         tx_cmd->rate = rate;
 784         tx_cmd->tx_flags = tx_flags;
 785
 786         /* OFDM */
 787         tx_cmd->supp_rates[0] =
 788            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 789
 790         /* CCK */
 791         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
 792
 793         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 794                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 795                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
 796                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
 797 }
 798
 799 static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
 800 {
 801         unsigned long flags_spin;
 802         struct iwl_station_entry *station;
 803
 804         if (sta_id == IWL_INVALID_STATION)
 805                 return IWL_INVALID_STATION;
 806
 807         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 808         station = &priv->stations[sta_id];
 809
 810         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 811         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 812         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 813         iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
 814         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 815
 816         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 817                         sta_id, tx_rate);
 818         return sta_id;
 819 }
 820
 821 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 822 {
 823         if (src == IWL_PWR_SRC_VAUX) {
 824                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 825                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 826                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 827                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 828
 829                         iwl_poll_bit(priv, CSR_GPIO_IN,
 830                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 831                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 832                 }
 833         } else {
 834                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 835                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 836                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 837
 838                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 839                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 840         }
 841
 842         return 0;
 843 }
 844
 845 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 846 {
 847         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 848         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 849         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 850         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 851                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 852                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 853                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 854                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 855                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 856                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 857                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 858                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 859
 860         /* fake read to flush all prev I/O */
 861         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 862
 863         return 0;
 864 }
 865
 866 static int iwl3945_tx_reset(struct iwl_priv *priv)
 867 {
 868
 869         /* bypass mode */
 870         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 871
 872         /* RA 0 is active */
 873         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 874
 875         /* all 6 fifo are active */
 876         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 877
 878         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 879         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 880         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 881         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 882
 883         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 884                              priv->_3945.shared_phys);
 885
 886         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 887                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 888                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 889                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 890                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 891                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 892                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 893                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 894
 895
 896         return 0;
 897 }
 898
 899 /**
 900  * iwl3945_txq_ctx_reset - Reset TX queue context
 901  *
 902  * Destroys all DMA structures and initialize them again
 903  */
 904 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 905 {
 906         int rc;
 907         int txq_id, slots_num;
 908
 909         iwl3945_hw_txq_ctx_free(priv);
 910
 911         /* allocate tx queue structure */
 912         rc = iwl_alloc_txq_mem(priv);
 913         if (rc)
 914                 return rc;
 915
 916         /* Tx CMD queue */
 917         rc = iwl3945_tx_reset(priv);
 918         if (rc)
 919                 goto error;
 920
 921         /* Tx queue(s) */
 922         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 923                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
 924                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 925                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 926                                        txq_id);
 927                 if (rc) {
 928                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
 929                         goto error;
 930                 }
 931         }
 932
 933         return rc;
 934
 935  error:
 936         iwl3945_hw_txq_ctx_free(priv);
 937         return rc;
 938 }
 939
 940
 941 /*
 942  * Start up 3945's basic functionality after it has been reset
 943  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 944  * NOTE:  This does not load uCode nor start the embedded processor
 945  */
 946 static int iwl3945_apm_init(struct iwl_priv *priv)
 947 {
 948         int ret = iwl_apm_init(priv);
 949
 950         /* Clear APMG (NIC's internal power management) interrupts */
 951         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
 952         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
 953
 954         /* Reset radio chip */
 955         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 956         udelay(5);
 957         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 958
 959         return ret;
 960 }
 961
 962 static void iwl3945_nic_config(struct iwl_priv *priv)
 963 {
 964         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
 965         unsigned long flags;
 966         u8 rev_id = 0;
 967
 968         spin_lock_irqsave(&priv->lock, flags);
 969
 970         /* Determine HW type */
 971         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
 972
 973         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
 974
 975         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
 976                 IWL_DEBUG_INFO(priv, "RTP type\n");
 977         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
 978                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
 979                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 980                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
 981         } else {
 982                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
 983                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 984                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
 985         }
 986
 987         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
 988                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
 989                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 990                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
 991         } else
 992                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
 993
 994         if ((eeprom->board_revision & 0xF0) == 0xD0) {
 995                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
 996                                eeprom->board_revision);
 997                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 998                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
 999         } else {
1000                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1001                                eeprom->board_revision);
1002                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1003                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1004         }
1005
1006         if (eeprom->almgor_m_version <= 1) {
1007                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1008                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1009                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1010                                eeprom->almgor_m_version);
1011         } else {
1012                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1013                                eeprom->almgor_m_version);
1014                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1015                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1016         }
1017         spin_unlock_irqrestore(&priv->lock, flags);
1018
1019         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1020                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1021
1022         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1023                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1024 }
1025
1026 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1027 {
1028         int rc;
1029         unsigned long flags;
1030         struct iwl_rx_queue *rxq = &priv->rxq;
1031
1032         spin_lock_irqsave(&priv->lock, flags);
1033         priv->cfg->ops->lib->apm_ops.init(priv);
1034         spin_unlock_irqrestore(&priv->lock, flags);
1035
1036         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1037         if (rc)
1038                 return rc;
1039
1040         priv->cfg->ops->lib->apm_ops.config(priv);
1041
1042         /* Allocate the RX queue, or reset if it is already allocated */
1043         if (!rxq->bd) {
1044                 rc = iwl_rx_queue_alloc(priv);
1045                 if (rc) {
1046                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1047                         return -ENOMEM;
1048                 }
1049         } else
1050                 iwl3945_rx_queue_reset(priv, rxq);
1051
1052         iwl3945_rx_replenish(priv);
1053
1054         iwl3945_rx_init(priv, rxq);
1055
1056
1057         /* Look at using this instead:
1058         rxq->need_update = 1;
1059         iwl_rx_queue_update_write_ptr(priv, rxq);
1060         */
1061
1062         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1063
1064         rc = iwl3945_txq_ctx_reset(priv);
1065         if (rc)
1066                 return rc;
1067
1068         set_bit(STATUS_INIT, &priv->status);
1069
1070         return 0;
1071 }
1072
1073 /**
1074  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1075  *
1076  * Destroy all TX DMA queues and structures
1077  */
1078 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1079 {
1080         int txq_id;
1081
1082         /* Tx queues */
1083         if (priv->txq)
1084                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1085                      txq_id++)
1086                         if (txq_id == IWL_CMD_QUEUE_NUM)
1087                                 iwl_cmd_queue_free(priv);
1088                         else
1089                                 iwl_tx_queue_free(priv, txq_id);
1090
1091         /* free tx queue structure */
1092         iwl_free_txq_mem(priv);
1093 }
1094
1095 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1096 {
1097         int txq_id;
1098
1099         /* stop SCD */
1100         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1101         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1102
1103         /* reset TFD queues */
1104         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1105                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1106                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1107                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1108                                 1000);
1109         }
1110
1111         iwl3945_hw_txq_ctx_free(priv);
1112 }
1113
1114 /**
1115  * iwl3945_hw_reg_adjust_power_by_temp
1116  * return index delta into power gain settings table
1117 */
1118 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1119 {
1120         return (new_reading - old_reading) * (-11) / 100;
1121 }
1122
1123 /**
1124  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1125  */
1126 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1127 {
1128         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1129 }
1130
1131 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1132 {
1133         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1134 }
1135
1136 /**
1137  * iwl3945_hw_reg_txpower_get_temperature
1138  * get the current temperature by reading from NIC
1139 */
1140 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1141 {
1142         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1143         int temperature;
1144
1145         temperature = iwl3945_hw_get_temperature(priv);
1146
1147         /* driver's okay range is -260 to +25.
1148          *   human readable okay range is 0 to +285 */
1149         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1150
1151         /* handle insane temp reading */
1152         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1153                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1154
1155                 /* if really really hot(?),
1156                  *   substitute the 3rd band/group's temp measured at factory */
1157                 if (priv->last_temperature > 100)
1158                         temperature = eeprom->groups[2].temperature;
1159                 else /* else use most recent "sane" value from driver */
1160                         temperature = priv->last_temperature;
1161         }
1162
1163         return temperature;     /* raw, not "human readable" */
1164 }
1165
1166 /* Adjust Txpower only if temperature variance is greater than threshold.
1167  *
1168  * Both are lower than older versions' 9 degrees */
1169 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1170
1171 /**
1172  * is_temp_calib_needed - determines if new calibration is needed
1173  *
1174  * records new temperature in tx_mgr->temperature.
1175  * replaces tx_mgr->last_temperature *only* if calib needed
1176  *    (assumes caller will actually do the calibration!). */
1177 static int is_temp_calib_needed(struct iwl_priv *priv)
1178 {
1179         int temp_diff;
1180
1181         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1182         temp_diff = priv->temperature - priv->last_temperature;
1183
1184         /* get absolute value */
1185         if (temp_diff < 0) {
1186                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1187                 temp_diff = -temp_diff;
1188         } else if (temp_diff == 0)
1189                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1190         else
1191                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1192
1193         /* if we don't need calibration, *don't* update last_temperature */
1194         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1195                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1196                 return 0;
1197         }
1198
1199         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1200
1201         /* assume that caller will actually do calib ...
1202          *   update the "last temperature" value */
1203         priv->last_temperature = priv->temperature;
1204         return 1;
1205 }
1206
1207 #define IWL_MAX_GAIN_ENTRIES 78
1208 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1209 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1210
1211 /* radio and DSP power table, each step is 1/2 dB.
1212  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1213 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1214         {
1215          {251, 127},            /* 2.4 GHz, highest power */
1216          {251, 127},
1217          {251, 127},
1218          {251, 127},
1219          {251, 125},
1220          {251, 110},
1221          {251, 105},
1222          {251, 98},
1223          {187, 125},
1224          {187, 115},
1225          {187, 108},
1226          {187, 99},
1227          {243, 119},
1228          {243, 111},
1229          {243, 105},
1230          {243, 97},
1231          {243, 92},
1232          {211, 106},
1233          {211, 100},
1234          {179, 120},
1235          {179, 113},
1236          {179, 107},
1237          {147, 125},
1238          {147, 119},
1239          {147, 112},
1240          {147, 106},
1241          {147, 101},
1242          {147, 97},
1243          {147, 91},
1244          {115, 107},
1245          {235, 121},
1246          {235, 115},
1247          {235, 109},
1248          {203, 127},
1249          {203, 121},
1250          {203, 115},
1251          {203, 108},
1252          {203, 102},
1253          {203, 96},
1254          {203, 92},
1255          {171, 110},
1256          {171, 104},
1257          {171, 98},
1258          {139, 116},
1259          {227, 125},
1260          {227, 119},
1261          {227, 113},
1262          {227, 107},
1263          {227, 101},
1264          {227, 96},
1265          {195, 113},
1266          {195, 106},
1267          {195, 102},
1268          {195, 95},
1269          {163, 113},
1270          {163, 106},
1271          {163, 102},
1272          {163, 95},
1273          {131, 113},
1274          {131, 106},
1275          {131, 102},
1276          {131, 95},
1277          {99, 113},
1278          {99, 106},
1279          {99, 102},
1280          {99, 95},
1281          {67, 113},
1282          {67, 106},
1283          {67, 102},
1284          {67, 95},
1285          {35, 113},
1286          {35, 106},
1287          {35, 102},
1288          {35, 95},
1289          {3, 113},
1290          {3, 106},
1291          {3, 102},
1292          {3, 95} },             /* 2.4 GHz, lowest power */
1293         {
1294          {251, 127},            /* 5.x GHz, highest power */
1295          {251, 120},
1296          {251, 114},
1297          {219, 119},
1298          {219, 101},
1299          {187, 113},
1300          {187, 102},
1301          {155, 114},
1302          {155, 103},
1303          {123, 117},
1304          {123, 107},
1305          {123, 99},
1306          {123, 92},
1307          {91, 108},
1308          {59, 125},
1309          {59, 118},
1310          {59, 109},
1311          {59, 102},
1312          {59, 96},
1313          {59, 90},
1314          {27, 104},
1315          {27, 98},
1316          {27, 92},
1317          {115, 118},
1318          {115, 111},
1319          {115, 104},
1320          {83, 126},
1321          {83, 121},
1322          {83, 113},
1323          {83, 105},
1324          {83, 99},
1325          {51, 118},
1326          {51, 111},
1327          {51, 104},
1328          {51, 98},
1329          {19, 116},
1330          {19, 109},
1331          {19, 102},
1332          {19, 98},
1333          {19, 93},
1334          {171, 113},
1335          {171, 107},
1336          {171, 99},
1337          {139, 120},
1338          {139, 113},
1339          {139, 107},
1340          {139, 99},
1341          {107, 120},
1342          {107, 113},
1343          {107, 107},
1344          {107, 99},
1345          {75, 120},
1346          {75, 113},
1347          {75, 107},
1348          {75, 99},
1349          {43, 120},
1350          {43, 113},
1351          {43, 107},
1352          {43, 99},
1353          {11, 120},
1354          {11, 113},
1355          {11, 107},
1356          {11, 99},
1357          {131, 107},
1358          {131, 99},
1359          {99, 120},
1360          {99, 113},
1361          {99, 107},
1362          {99, 99},
1363          {67, 120},
1364          {67, 113},
1365          {67, 107},
1366          {67, 99},
1367          {35, 120},
1368          {35, 113},
1369          {35, 107},
1370          {35, 99},
1371          {3, 120} }             /* 5.x GHz, lowest power */
1372 };
1373
1374 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1375 {
1376         if (index < 0)
1377                 return 0;
1378         if (index >= IWL_MAX_GAIN_ENTRIES)
1379                 return IWL_MAX_GAIN_ENTRIES - 1;
1380         return (u8) index;
1381 }
1382
1383 /* Kick off thermal recalibration check every 60 seconds */
1384 #define REG_RECALIB_PERIOD (60)
1385
1386 /**
1387  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1388  *
1389  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1390  * or 6 Mbit (OFDM) rates.
1391  */
1392 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1393                                s32 rate_index, const s8 *clip_pwrs,
1394                                struct iwl_channel_info *ch_info,
1395                                int band_index)
1396 {
1397         struct iwl3945_scan_power_info *scan_power_info;
1398         s8 power;
1399         u8 power_index;
1400
1401         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1402
1403         /* use this channel group's 6Mbit clipping/saturation pwr,
1404          *   but cap at regulatory scan power restriction (set during init
1405          *   based on eeprom channel data) for this channel.  */
1406         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1407
1408         /* further limit to user's max power preference.
1409          * FIXME:  Other spectrum management power limitations do not
1410          *   seem to apply?? */
1411         power = min(power, priv->tx_power_user_lmt);
1412         scan_power_info->requested_power = power;
1413
1414         /* find difference between new scan *power* and current "normal"
1415          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1416          *   current "normal" temperature-compensated Tx power *index* for
1417          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1418          *   *index*. */
1419         power_index = ch_info->power_info[rate_index].power_table_index
1420             - (power - ch_info->power_info
1421                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1422
1423         /* store reference index that we use when adjusting *all* scan
1424          *   powers.  So we can accommodate user (all channel) or spectrum
1425          *   management (single channel) power changes "between" temperature
1426          *   feedback compensation procedures.
1427          * don't force fit this reference index into gain table; it may be a
1428          *   negative number.  This will help avoid errors when we're at
1429          *   the lower bounds (highest gains, for warmest temperatures)
1430          *   of the table. */
1431
1432         /* don't exceed table bounds for "real" setting */
1433         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1434
1435         scan_power_info->power_table_index = power_index;
1436         scan_power_info->tpc.tx_gain =
1437             power_gain_table[band_index][power_index].tx_gain;
1438         scan_power_info->tpc.dsp_atten =
1439             power_gain_table[band_index][power_index].dsp_atten;
1440 }
1441
1442 /**
1443  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1444  *
1445  * Configures power settings for all rates for the current channel,
1446  * using values from channel info struct, and send to NIC
1447  */
1448 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1449 {
1450         int rate_idx, i;
1451         const struct iwl_channel_info *ch_info = NULL;
1452         struct iwl3945_txpowertable_cmd txpower = {
1453                 .channel = priv->active_rxon.channel,
1454         };
1455
1456         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1457         ch_info = iwl_get_channel_info(priv,
1458                                        priv->band,
1459                                        le16_to_cpu(priv->active_rxon.channel));
1460         if (!ch_info) {
1461                 IWL_ERR(priv,
1462                         "Failed to get channel info for channel %d [%d]\n",
1463                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1464                 return -EINVAL;
1465         }
1466
1467         if (!is_channel_valid(ch_info)) {
1468                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1469                                 "non-Tx channel.\n");
1470                 return 0;
1471         }
1472
1473         /* fill cmd with power settings for all rates for current channel */
1474         /* Fill OFDM rate */
1475         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1476              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1477
1478                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1479                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1480
1481                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1482                                 le16_to_cpu(txpower.channel),
1483                                 txpower.band,
1484                                 txpower.power[i].tpc.tx_gain,
1485                                 txpower.power[i].tpc.dsp_atten,
1486                                 txpower.power[i].rate);
1487         }
1488         /* Fill CCK rates */
1489         for (rate_idx = IWL_FIRST_CCK_RATE;
1490              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1491                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1492                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1493
1494                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1495                                 le16_to_cpu(txpower.channel),
1496                                 txpower.band,
1497                                 txpower.power[i].tpc.tx_gain,
1498                                 txpower.power[i].tpc.dsp_atten,
1499                                 txpower.power[i].rate);
1500         }
1501
1502         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1503                                 sizeof(struct iwl3945_txpowertable_cmd),
1504                                 &txpower);
1505
1506 }
1507
1508 /**
1509  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1510  * @ch_info: Channel to update.  Uses power_info.requested_power.
1511  *
1512  * Replace requested_power and base_power_index ch_info fields for
1513  * one channel.
1514  *
1515  * Called if user or spectrum management changes power preferences.
1516  * Takes into account h/w and modulation limitations (clip power).
1517  *
1518  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1519  *
1520  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1521  *       properly fill out the scan powers, and actual h/w gain settings,
1522  *       and send changes to NIC
1523  */
1524 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1525                              struct iwl_channel_info *ch_info)
1526 {
1527         struct iwl3945_channel_power_info *power_info;
1528         int power_changed = 0;
1529         int i;
1530         const s8 *clip_pwrs;
1531         int power;
1532
1533         /* Get this chnlgrp's rate-to-max/clip-powers table */
1534         clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1535
1536         /* Get this channel's rate-to-current-power settings table */
1537         power_info = ch_info->power_info;
1538
1539         /* update OFDM Txpower settings */
1540         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1541              i++, ++power_info) {
1542                 int delta_idx;
1543
1544                 /* limit new power to be no more than h/w capability */
1545                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1546                 if (power == power_info->requested_power)
1547                         continue;
1548
1549                 /* find difference between old and new requested powers,
1550                  *    update base (non-temp-compensated) power index */
1551                 delta_idx = (power - power_info->requested_power) * 2;
1552                 power_info->base_power_index -= delta_idx;
1553
1554                 /* save new requested power value */
1555                 power_info->requested_power = power;
1556
1557                 power_changed = 1;
1558         }
1559
1560         /* update CCK Txpower settings, based on OFDM 12M setting ...
1561          *    ... all CCK power settings for a given channel are the *same*. */
1562         if (power_changed) {
1563                 power =
1564                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1565                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1566
1567                 /* do all CCK rates' iwl3945_channel_power_info structures */
1568                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1569                         power_info->requested_power = power;
1570                         power_info->base_power_index =
1571                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1572                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1573                         ++power_info;
1574                 }
1575         }
1576
1577         return 0;
1578 }
1579
1580 /**
1581  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1582  *
1583  * NOTE: Returned power limit may be less (but not more) than requested,
1584  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1585  *       (no consideration for h/w clipping limitations).
1586  */
1587 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1588 {
1589         s8 max_power;
1590
1591 #if 0
1592         /* if we're using TGd limits, use lower of TGd or EEPROM */
1593         if (ch_info->tgd_data.max_power != 0)
1594                 max_power = min(ch_info->tgd_data.max_power,
1595                                 ch_info->eeprom.max_power_avg);
1596
1597         /* else just use EEPROM limits */
1598         else
1599 #endif
1600                 max_power = ch_info->eeprom.max_power_avg;
1601
1602         return min(max_power, ch_info->max_power_avg);
1603 }
1604
1605 /**
1606  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1607  *
1608  * Compensate txpower settings of *all* channels for temperature.
1609  * This only accounts for the difference between current temperature
1610  *   and the factory calibration temperatures, and bases the new settings
1611  *   on the channel's base_power_index.
1612  *
1613  * If RxOn is "associated", this sends the new Txpower to NIC!
1614  */
1615 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1616 {
1617         struct iwl_channel_info *ch_info = NULL;
1618         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1619         int delta_index;
1620         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1621         u8 a_band;
1622         u8 rate_index;
1623         u8 scan_tbl_index;
1624         u8 i;
1625         int ref_temp;
1626         int temperature = priv->temperature;
1627
1628         if (priv->disable_tx_power_cal ||
1629             test_bit(STATUS_SCANNING, &priv->status)) {
1630                 /* do not perform tx power calibration */
1631                 return 0;
1632         }
1633         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1634         for (i = 0; i < priv->channel_count; i++) {
1635                 ch_info = &priv->channel_info[i];
1636                 a_band = is_channel_a_band(ch_info);
1637
1638                 /* Get this chnlgrp's factory calibration temperature */
1639                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1640                     temperature;
1641
1642                 /* get power index adjustment based on current and factory
1643                  * temps */
1644                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1645                                                               ref_temp);
1646
1647                 /* set tx power value for all rates, OFDM and CCK */
1648                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1649                      rate_index++) {
1650                         int power_idx =
1651                             ch_info->power_info[rate_index].base_power_index;
1652
1653                         /* temperature compensate */
1654                         power_idx += delta_index;
1655
1656                         /* stay within table range */
1657                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1658                         ch_info->power_info[rate_index].
1659                             power_table_index = (u8) power_idx;
1660                         ch_info->power_info[rate_index].tpc =
1661                             power_gain_table[a_band][power_idx];
1662                 }
1663
1664                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1665                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1666
1667                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1668                 for (scan_tbl_index = 0;
1669                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1670                         s32 actual_index = (scan_tbl_index == 0) ?
1671                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1672                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1673                                            actual_index, clip_pwrs,
1674                                            ch_info, a_band);
1675                 }
1676         }
1677
1678         /* send Txpower command for current channel to ucode */
1679         return priv->cfg->ops->lib->send_tx_power(priv);
1680 }
1681
1682 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1683 {
1684         struct iwl_channel_info *ch_info;
1685         s8 max_power;
1686         u8 a_band;
1687         u8 i;
1688
1689         if (priv->tx_power_user_lmt == power) {
1690                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1691                                 "limit: %ddBm.\n", power);
1692                 return 0;
1693         }
1694
1695         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1696         priv->tx_power_user_lmt = power;
1697
1698         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1699
1700         for (i = 0; i < priv->channel_count; i++) {
1701                 ch_info = &priv->channel_info[i];
1702                 a_band = is_channel_a_band(ch_info);
1703
1704                 /* find minimum power of all user and regulatory constraints
1705                  *    (does not consider h/w clipping limitations) */
1706                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1707                 max_power = min(power, max_power);
1708                 if (max_power != ch_info->curr_txpow) {
1709                         ch_info->curr_txpow = max_power;
1710
1711                         /* this considers the h/w clipping limitations */
1712                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1713                 }
1714         }
1715
1716         /* update txpower settings for all channels,
1717          *   send to NIC if associated. */
1718         is_temp_calib_needed(priv);
1719         iwl3945_hw_reg_comp_txpower_temp(priv);
1720
1721         return 0;
1722 }
1723
1724 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1725 {
1726         int rc = 0;
1727         struct iwl_rx_packet *pkt;
1728         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1729         struct iwl_host_cmd cmd = {
1730                 .id = REPLY_RXON_ASSOC,
1731                 .len = sizeof(rxon_assoc),
1732                 .flags = CMD_WANT_SKB,
1733                 .data = &rxon_assoc,
1734         };
1735         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1736         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1737
1738         if ((rxon1->flags == rxon2->flags) &&
1739             (rxon1->filter_flags == rxon2->filter_flags) &&
1740             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1741             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1742                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1743                 return 0;
1744         }
1745
1746         rxon_assoc.flags = priv->staging_rxon.flags;
1747         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1748         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1749         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1750         rxon_assoc.reserved = 0;
1751
1752         rc = iwl_send_cmd_sync(priv, &cmd);
1753         if (rc)
1754                 return rc;
1755
1756         pkt = (struct iwl_rx_packet *)cmd.reply_page;
1757         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1758                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1759                 rc = -EIO;
1760         }
1761
1762         iwl_free_pages(priv, cmd.reply_page);
1763
1764         return rc;
1765 }
1766
1767 /**
1768  * iwl3945_commit_rxon - commit staging_rxon to hardware
1769  *
1770  * The RXON command in staging_rxon is committed to the hardware and
1771  * the active_rxon structure is updated with the new data.  This
1772  * function correctly transitions out of the RXON_ASSOC_MSK state if
1773  * a HW tune is required based on the RXON structure changes.
1774  */
1775 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1776 {
1777         /* cast away the const for active_rxon in this function */
1778         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1779         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1780         int rc = 0;
1781         bool new_assoc =
1782                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1783
1784         if (!iwl_is_alive(priv))
1785                 return -1;
1786
1787         /* always get timestamp with Rx frame */
1788         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1789
1790         /* select antenna */
1791         staging_rxon->flags &=
1792             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1793         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1794
1795         rc = iwl_check_rxon_cmd(priv);
1796         if (rc) {
1797                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1798                 return -EINVAL;
1799         }
1800
1801         /* If we don't need to send a full RXON, we can use
1802          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1803          * and other flags for the current radio configuration. */
1804         if (!iwl_full_rxon_required(priv)) {
1805                 rc = iwl_send_rxon_assoc(priv);
1806                 if (rc) {
1807                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1808                                   "configuration (%d).\n", rc);
1809                         return rc;
1810                 }
1811
1812                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1813
1814                 return 0;
1815         }
1816
1817         /* If we are currently associated and the new config requires
1818          * an RXON_ASSOC and the new config wants the associated mask enabled,
1819          * we must clear the associated from the active configuration
1820          * before we apply the new config */
1821         if (iwl_is_associated(priv) && new_assoc) {
1822                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1823                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1824
1825                 /*
1826                  * reserved4 and 5 could have been filled by the iwlcore code.
1827                  * Let's clear them before pushing to the 3945.
1828                  */
1829                 active_rxon->reserved4 = 0;
1830                 active_rxon->reserved5 = 0;
1831                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1832                                       sizeof(struct iwl3945_rxon_cmd),
1833                                       &priv->active_rxon);
1834
1835                 /* If the mask clearing failed then we set
1836                  * active_rxon back to what it was previously */
1837                 if (rc) {
1838                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1839                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1840                                   "configuration (%d).\n", rc);
1841                         return rc;
1842                 }
1843                 iwl_clear_ucode_stations(priv);
1844                 iwl_restore_stations(priv);
1845         }
1846
1847         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1848                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1849                        "* channel = %d\n"
1850                        "* bssid = %pM\n",
1851                        (new_assoc ? "" : "out"),
1852                        le16_to_cpu(staging_rxon->channel),
1853                        staging_rxon->bssid_addr);
1854
1855         /*
1856          * reserved4 and 5 could have been filled by the iwlcore code.
1857          * Let's clear them before pushing to the 3945.
1858          */
1859         staging_rxon->reserved4 = 0;
1860         staging_rxon->reserved5 = 0;
1861
1862         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1863
1864         /* Apply the new configuration */
1865         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1866                               sizeof(struct iwl3945_rxon_cmd),
1867                               staging_rxon);
1868         if (rc) {
1869                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1870                 return rc;
1871         }
1872
1873         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1874
1875         if (!new_assoc) {
1876                 iwl_clear_ucode_stations(priv);
1877                 iwl_restore_stations(priv);
1878         }
1879
1880         /* If we issue a new RXON command which required a tune then we must
1881          * send a new TXPOWER command or we won't be able to Tx any frames */
1882         rc = priv->cfg->ops->lib->send_tx_power(priv);
1883         if (rc) {
1884                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1885                 return rc;
1886         }
1887
1888         /* Init the hardware's rate fallback order based on the band */
1889         rc = iwl3945_init_hw_rate_table(priv);
1890         if (rc) {
1891                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1892                 return -EIO;
1893         }
1894
1895         return 0;
1896 }
1897
1898 /**
1899  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1900  *
1901  * -- reset periodic timer
1902  * -- see if temp has changed enough to warrant re-calibration ... if so:
1903  *     -- correct coeffs for temp (can reset temp timer)
1904  *     -- save this temp as "last",
1905  *     -- send new set of gain settings to NIC
1906  * NOTE:  This should continue working, even when we're not associated,
1907  *   so we can keep our internal table of scan powers current. */
1908 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1909 {
1910         /* This will kick in the "brute force"
1911          * iwl3945_hw_reg_comp_txpower_temp() below */
1912         if (!is_temp_calib_needed(priv))
1913                 goto reschedule;
1914
1915         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1916          * This is based *only* on current temperature,
1917          * ignoring any previous power measurements */
1918         iwl3945_hw_reg_comp_txpower_temp(priv);
1919
1920  reschedule:
1921         queue_delayed_work(priv->workqueue,
1922                            &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1923 }
1924
1925 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1926 {
1927         struct iwl_priv *priv = container_of(work, struct iwl_priv,
1928                                              _3945.thermal_periodic.work);
1929
1930         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1931                 return;
1932
1933         mutex_lock(&priv->mutex);
1934         iwl3945_reg_txpower_periodic(priv);
1935         mutex_unlock(&priv->mutex);
1936 }
1937
1938 /**
1939  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1940  *                                 for the channel.
1941  *
1942  * This function is used when initializing channel-info structs.
1943  *
1944  * NOTE: These channel groups do *NOT* match the bands above!
1945  *       These channel groups are based on factory-tested channels;
1946  *       on A-band, EEPROM's "group frequency" entries represent the top
1947  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
1948  */
1949 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1950                                        const struct iwl_channel_info *ch_info)
1951 {
1952         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1953         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1954         u8 group;
1955         u16 group_index = 0;    /* based on factory calib frequencies */
1956         u8 grp_channel;
1957
1958         /* Find the group index for the channel ... don't use index 1(?) */
1959         if (is_channel_a_band(ch_info)) {
1960                 for (group = 1; group < 5; group++) {
1961                         grp_channel = ch_grp[group].group_channel;
1962                         if (ch_info->channel <= grp_channel) {
1963                                 group_index = group;
1964                                 break;
1965                         }
1966                 }
1967                 /* group 4 has a few channels *above* its factory cal freq */
1968                 if (group == 5)
1969                         group_index = 4;
1970         } else
1971                 group_index = 0;        /* 2.4 GHz, group 0 */
1972
1973         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1974                         group_index);
1975         return group_index;
1976 }
1977
1978 /**
1979  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1980  *
1981  * Interpolate to get nominal (i.e. at factory calibration temperature) index
1982  *   into radio/DSP gain settings table for requested power.
1983  */
1984 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1985                                        s8 requested_power,
1986                                        s32 setting_index, s32 *new_index)
1987 {
1988         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
1989         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1990         s32 index0, index1;
1991         s32 power = 2 * requested_power;
1992         s32 i;
1993         const struct iwl3945_eeprom_txpower_sample *samples;
1994         s32 gains0, gains1;
1995         s32 res;
1996         s32 denominator;
1997
1998         chnl_grp = &eeprom->groups[setting_index];
1999         samples = chnl_grp->samples;
2000         for (i = 0; i < 5; i++) {
2001                 if (power == samples[i].power) {
2002                         *new_index = samples[i].gain_index;
2003                         return 0;
2004                 }
2005         }
2006
2007         if (power > samples[1].power) {
2008                 index0 = 0;
2009                 index1 = 1;
2010         } else if (power > samples[2].power) {
2011                 index0 = 1;
2012                 index1 = 2;
2013         } else if (power > samples[3].power) {
2014                 index0 = 2;
2015                 index1 = 3;
2016         } else {
2017                 index0 = 3;
2018                 index1 = 4;
2019         }
2020
2021         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2022         if (denominator == 0)
2023                 return -EINVAL;
2024         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2025         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2026         res = gains0 + (gains1 - gains0) *
2027             ((s32) power - (s32) samples[index0].power) / denominator +
2028             (1 << 18);
2029         *new_index = res >> 19;
2030         return 0;
2031 }
2032
2033 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2034 {
2035         u32 i;
2036         s32 rate_index;
2037         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2038         const struct iwl3945_eeprom_txpower_group *group;
2039
2040         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2041
2042         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2043                 s8 *clip_pwrs;  /* table of power levels for each rate */
2044                 s8 satur_pwr;   /* saturation power for each chnl group */
2045                 group = &eeprom->groups[i];
2046
2047                 /* sanity check on factory saturation power value */
2048                 if (group->saturation_power < 40) {
2049                         IWL_WARN(priv, "Error: saturation power is %d, "
2050                                     "less than minimum expected 40\n",
2051                                     group->saturation_power);
2052                         return;
2053                 }
2054
2055                 /*
2056                  * Derive requested power levels for each rate, based on
2057                  *   hardware capabilities (saturation power for band).
2058                  * Basic value is 3dB down from saturation, with further
2059                  *   power reductions for highest 3 data rates.  These
2060                  *   backoffs provide headroom for high rate modulation
2061                  *   power peaks, without too much distortion (clipping).
2062                  */
2063                 /* we'll fill in this array with h/w max power levels */
2064                 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2065
2066                 /* divide factory saturation power by 2 to find -3dB level */
2067                 satur_pwr = (s8) (group->saturation_power >> 1);
2068
2069                 /* fill in channel group's nominal powers for each rate */
2070                 for (rate_index = 0;
2071                      rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2072                         switch (rate_index) {
2073                         case IWL_RATE_36M_INDEX_TABLE:
2074                                 if (i == 0)     /* B/G */
2075                                         *clip_pwrs = satur_pwr;
2076                                 else    /* A */
2077                                         *clip_pwrs = satur_pwr - 5;
2078                                 break;
2079                         case IWL_RATE_48M_INDEX_TABLE:
2080                                 if (i == 0)
2081                                         *clip_pwrs = satur_pwr - 7;
2082                                 else
2083                                         *clip_pwrs = satur_pwr - 10;
2084                                 break;
2085                         case IWL_RATE_54M_INDEX_TABLE:
2086                                 if (i == 0)
2087                                         *clip_pwrs = satur_pwr - 9;
2088                                 else
2089                                         *clip_pwrs = satur_pwr - 12;
2090                                 break;
2091                         default:
2092                                 *clip_pwrs = satur_pwr;
2093                                 break;
2094                         }
2095                 }
2096         }
2097 }
2098
2099 /**
2100  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2101  *
2102  * Second pass (during init) to set up priv->channel_info
2103  *
2104  * Set up Tx-power settings in our channel info database for each VALID
2105  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2106  * and current temperature.
2107  *
2108  * Since this is based on current temperature (at init time), these values may
2109  * not be valid for very long, but it gives us a starting/default point,
2110  * and allows us to active (i.e. using Tx) scan.
2111  *
2112  * This does *not* write values to NIC, just sets up our internal table.
2113  */
2114 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2115 {
2116         struct iwl_channel_info *ch_info = NULL;
2117         struct iwl3945_channel_power_info *pwr_info;
2118         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2119         int delta_index;
2120         u8 rate_index;
2121         u8 scan_tbl_index;
2122         const s8 *clip_pwrs;    /* array of power levels for each rate */
2123         u8 gain, dsp_atten;
2124         s8 power;
2125         u8 pwr_index, base_pwr_index, a_band;
2126         u8 i;
2127         int temperature;
2128
2129         /* save temperature reference,
2130          *   so we can determine next time to calibrate */
2131         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2132         priv->last_temperature = temperature;
2133
2134         iwl3945_hw_reg_init_channel_groups(priv);
2135
2136         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2137         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2138              i++, ch_info++) {
2139                 a_band = is_channel_a_band(ch_info);
2140                 if (!is_channel_valid(ch_info))
2141                         continue;
2142
2143                 /* find this channel's channel group (*not* "band") index */
2144                 ch_info->group_index =
2145                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2146
2147                 /* Get this chnlgrp's rate->max/clip-powers table */
2148                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2149
2150                 /* calculate power index *adjustment* value according to
2151                  *  diff between current temperature and factory temperature */
2152                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2153                                 eeprom->groups[ch_info->group_index].
2154                                 temperature);
2155
2156                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2157                                 ch_info->channel, delta_index, temperature +
2158                                 IWL_TEMP_CONVERT);
2159
2160                 /* set tx power value for all OFDM rates */
2161                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2162                      rate_index++) {
2163                         s32 uninitialized_var(power_idx);
2164                         int rc;
2165
2166                         /* use channel group's clip-power table,
2167                          *   but don't exceed channel's max power */
2168                         s8 pwr = min(ch_info->max_power_avg,
2169                                      clip_pwrs[rate_index]);
2170
2171                         pwr_info = &ch_info->power_info[rate_index];
2172
2173                         /* get base (i.e. at factory-measured temperature)
2174                          *    power table index for this rate's power */
2175                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2176                                                          ch_info->group_index,
2177                                                          &power_idx);
2178                         if (rc) {
2179                                 IWL_ERR(priv, "Invalid power index\n");
2180                                 return rc;
2181                         }
2182                         pwr_info->base_power_index = (u8) power_idx;
2183
2184                         /* temperature compensate */
2185                         power_idx += delta_index;
2186
2187                         /* stay within range of gain table */
2188                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2189
2190                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2191                         pwr_info->requested_power = pwr;
2192                         pwr_info->power_table_index = (u8) power_idx;
2193                         pwr_info->tpc.tx_gain =
2194                             power_gain_table[a_band][power_idx].tx_gain;
2195                         pwr_info->tpc.dsp_atten =
2196                             power_gain_table[a_band][power_idx].dsp_atten;
2197                 }
2198
2199                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2200                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2201                 power = pwr_info->requested_power +
2202                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2203                 pwr_index = pwr_info->power_table_index +
2204                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2205                 base_pwr_index = pwr_info->base_power_index +
2206                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2207
2208                 /* stay within table range */
2209                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2210                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2211                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2212
2213                 /* fill each CCK rate's iwl3945_channel_power_info structure
2214                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2215                  * NOTE:  CCK rates start at end of OFDM rates! */
2216                 for (rate_index = 0;
2217                      rate_index < IWL_CCK_RATES; rate_index++) {
2218                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2219                         pwr_info->requested_power = power;
2220                         pwr_info->power_table_index = pwr_index;
2221                         pwr_info->base_power_index = base_pwr_index;
2222                         pwr_info->tpc.tx_gain = gain;
2223                         pwr_info->tpc.dsp_atten = dsp_atten;
2224                 }
2225
2226                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2227                 for (scan_tbl_index = 0;
2228                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2229                         s32 actual_index = (scan_tbl_index == 0) ?
2230                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2231                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2232                                 actual_index, clip_pwrs, ch_info, a_band);
2233                 }
2234         }
2235
2236         return 0;
2237 }
2238
2239 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2240 {
2241         int rc;
2242
2243         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2244         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2245                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2246         if (rc < 0)
2247                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2248
2249         return 0;
2250 }
2251
2252 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2253 {
2254         int txq_id = txq->q.id;
2255
2256         struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2257
2258         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2259
2260         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2261         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2262
2263         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2264                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2265                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2266                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2267                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2268                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2269
2270         /* fake read to flush all prev. writes */
2271         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2272
2273         return 0;
2274 }
2275
2276 /*
2277  * HCMD utils
2278  */
2279 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2280 {
2281         switch (cmd_id) {
2282         case REPLY_RXON:
2283                 return sizeof(struct iwl3945_rxon_cmd);
2284         case POWER_TABLE_CMD:
2285                 return sizeof(struct iwl3945_powertable_cmd);
2286         default:
2287                 return len;
2288         }
2289 }
2290
2291
2292 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2293 {
2294         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2295         addsta->mode = cmd->mode;
2296         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2297         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2298         addsta->station_flags = cmd->station_flags;
2299         addsta->station_flags_msk = cmd->station_flags_msk;
2300         addsta->tid_disable_tx = cpu_to_le16(0);
2301         addsta->rate_n_flags = cmd->rate_n_flags;
2302         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2303         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2304         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2305
2306         return (u16)sizeof(struct iwl3945_addsta_cmd);
2307 }
2308
2309 static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2310                                        struct ieee80211_vif *vif, bool add)
2311 {
2312         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2313         int ret;
2314
2315         if (add) {
2316                 ret = iwl_add_bssid_station(priv, vif->bss_conf.bssid, false,
2317                                             &vif_priv->ibss_bssid_sta_id);
2318                 if (ret)
2319                         return ret;
2320
2321                 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
2322                                  (priv->band == IEEE80211_BAND_5GHZ) ?
2323                                  IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
2324                 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
2325
2326                 return 0;
2327         }
2328
2329         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2330                                   vif->bss_conf.bssid);
2331 }
2332
2333 /**
2334  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2335  */
2336 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2337 {
2338         int rc, i, index, prev_index;
2339         struct iwl3945_rate_scaling_cmd rate_cmd = {
2340                 .reserved = {0, 0, 0},
2341         };
2342         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2343
2344         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2345                 index = iwl3945_rates[i].table_rs_index;
2346
2347                 table[index].rate_n_flags =
2348                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2349                 table[index].try_cnt = priv->retry_rate;
2350                 prev_index = iwl3945_get_prev_ieee_rate(i);
2351                 table[index].next_rate_index =
2352                                 iwl3945_rates[prev_index].table_rs_index;
2353         }
2354
2355         switch (priv->band) {
2356         case IEEE80211_BAND_5GHZ:
2357                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2358                 /* If one of the following CCK rates is used,
2359                  * have it fall back to the 6M OFDM rate */
2360                 for (i = IWL_RATE_1M_INDEX_TABLE;
2361                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2362                         table[i].next_rate_index =
2363                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2364
2365                 /* Don't fall back to CCK rates */
2366                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2367                                                 IWL_RATE_9M_INDEX_TABLE;
2368
2369                 /* Don't drop out of OFDM rates */
2370                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2371                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2372                 break;
2373
2374         case IEEE80211_BAND_2GHZ:
2375                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2376                 /* If an OFDM rate is used, have it fall back to the
2377                  * 1M CCK rates */
2378
2379                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2380                     iwl_is_associated(priv)) {
2381
2382                         index = IWL_FIRST_CCK_RATE;
2383                         for (i = IWL_RATE_6M_INDEX_TABLE;
2384                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2385                                 table[i].next_rate_index =
2386                                         iwl3945_rates[index].table_rs_index;
2387
2388                         index = IWL_RATE_11M_INDEX_TABLE;
2389                         /* CCK shouldn't fall back to OFDM... */
2390                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2391                 }
2392                 break;
2393
2394         default:
2395                 WARN_ON(1);
2396                 break;
2397         }
2398
2399         /* Update the rate scaling for control frame Tx */
2400         rate_cmd.table_id = 0;
2401         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2402                               &rate_cmd);
2403         if (rc)
2404                 return rc;
2405
2406         /* Update the rate scaling for data frame Tx */
2407         rate_cmd.table_id = 1;
2408         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2409                                 &rate_cmd);
2410 }
2411
2412 /* Called when initializing driver */
2413 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2414 {
2415         memset((void *)&priv->hw_params, 0,
2416                sizeof(struct iwl_hw_params));
2417
2418         priv->_3945.shared_virt =
2419                 dma_alloc_coherent(&priv->pci_dev->dev,
2420                                    sizeof(struct iwl3945_shared),
2421                                    &priv->_3945.shared_phys, GFP_KERNEL);
2422         if (!priv->_3945.shared_virt) {
2423                 IWL_ERR(priv, "failed to allocate pci memory\n");
2424                 return -ENOMEM;
2425         }
2426
2427         /* Assign number of Usable TX queues */
2428         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2429
2430         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2431         priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2432         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2433         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2434         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2435         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2436
2437         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2438         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2439         priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
2440
2441         return 0;
2442 }
2443
2444 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2445                           struct iwl3945_frame *frame, u8 rate)
2446 {
2447         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2448         unsigned int frame_size;
2449
2450         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2451         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2452
2453         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2454         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2455
2456         frame_size = iwl3945_fill_beacon_frame(priv,
2457                                 tx_beacon_cmd->frame,
2458                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2459
2460         BUG_ON(frame_size > MAX_MPDU_SIZE);
2461         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2462
2463         tx_beacon_cmd->tx.rate = rate;
2464         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2465                                       TX_CMD_FLG_TSF_MSK);
2466
2467         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2468         tx_beacon_cmd->tx.supp_rates[0] =
2469                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2470
2471         tx_beacon_cmd->tx.supp_rates[1] =
2472                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2473
2474         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2475 }
2476
2477 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2478 {
2479         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2480         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2481 }
2482
2483 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2484 {
2485         INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2486                           iwl3945_bg_reg_txpower_periodic);
2487 }
2488
2489 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2490 {
2491         cancel_delayed_work(&priv->_3945.thermal_periodic);
2492 }
2493
2494 /* check contents of special bootstrap uCode SRAM */
2495 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2496  {
2497         __le32 *image = priv->ucode_boot.v_addr;
2498         u32 len = priv->ucode_boot.len;
2499         u32 reg;
2500         u32 val;
2501
2502         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2503
2504         /* verify BSM SRAM contents */
2505         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2506         for (reg = BSM_SRAM_LOWER_BOUND;
2507              reg < BSM_SRAM_LOWER_BOUND + len;
2508              reg += sizeof(u32), image++) {
2509                 val = iwl_read_prph(priv, reg);
2510                 if (val != le32_to_cpu(*image)) {
2511                         IWL_ERR(priv, "BSM uCode verification failed at "
2512                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2513                                   BSM_SRAM_LOWER_BOUND,
2514                                   reg - BSM_SRAM_LOWER_BOUND, len,
2515                                   val, le32_to_cpu(*image));
2516                         return -EIO;
2517                 }
2518         }
2519
2520         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2521
2522         return 0;
2523 }
2524
2525
2526 /******************************************************************************
2527  *
2528  * EEPROM related functions
2529  *
2530  ******************************************************************************/
2531
2532 /*
2533  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2534  * embedded controller) as EEPROM reader; each read is a series of pulses
2535  * to/from the EEPROM chip, not a single event, so even reads could conflict
2536  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2537  * simply claims ownership, which should be safe when this function is called
2538  * (i.e. before loading uCode!).
2539  */
2540 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2541 {
2542         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2543         return 0;
2544 }
2545
2546
2547 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2548 {
2549         return;
2550 }
2551
2552  /**
2553   * iwl3945_load_bsm - Load bootstrap instructions
2554   *
2555   * BSM operation:
2556   *
2557   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2558   * in special SRAM that does not power down during RFKILL.  When powering back
2559   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2560   * the bootstrap program into the on-board processor, and starts it.
2561   *
2562   * The bootstrap program loads (via DMA) instructions and data for a new
2563   * program from host DRAM locations indicated by the host driver in the
2564   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2565   * automatically.
2566   *
2567   * When initializing the NIC, the host driver points the BSM to the
2568   * "initialize" uCode image.  This uCode sets up some internal data, then
2569   * notifies host via "initialize alive" that it is complete.
2570   *
2571   * The host then replaces the BSM_DRAM_* pointer values to point to the
2572   * normal runtime uCode instructions and a backup uCode data cache buffer
2573   * (filled initially with starting data values for the on-board processor),
2574   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2575   * which begins normal operation.
2576   *
2577   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2578   * the backup data cache in DRAM before SRAM is powered down.
2579   *
2580   * When powering back up, the BSM loads the bootstrap program.  This reloads
2581   * the runtime uCode instructions and the backup data cache into SRAM,
2582   * and re-launches the runtime uCode from where it left off.
2583   */
2584 static int iwl3945_load_bsm(struct iwl_priv *priv)
2585 {
2586         __le32 *image = priv->ucode_boot.v_addr;
2587         u32 len = priv->ucode_boot.len;
2588         dma_addr_t pinst;
2589         dma_addr_t pdata;
2590         u32 inst_len;
2591         u32 data_len;
2592         int rc;
2593         int i;
2594         u32 done;
2595         u32 reg_offset;
2596
2597         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2598
2599         /* make sure bootstrap program is no larger than BSM's SRAM size */
2600         if (len > IWL39_MAX_BSM_SIZE)
2601                 return -EINVAL;
2602
2603         /* Tell bootstrap uCode where to find the "Initialize" uCode
2604         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2605         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2606         *        after the "initialize" uCode has run, to point to
2607         *        runtime/protocol instructions and backup data cache. */
2608         pinst = priv->ucode_init.p_addr;
2609         pdata = priv->ucode_init_data.p_addr;
2610         inst_len = priv->ucode_init.len;
2611         data_len = priv->ucode_init_data.len;
2612
2613         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2614         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2615         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2616         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2617
2618         /* Fill BSM memory with bootstrap instructions */
2619         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2620              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2621              reg_offset += sizeof(u32), image++)
2622                 _iwl_write_prph(priv, reg_offset,
2623                                           le32_to_cpu(*image));
2624
2625         rc = iwl3945_verify_bsm(priv);
2626         if (rc)
2627                 return rc;
2628
2629         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2630         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2631         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2632                                  IWL39_RTC_INST_LOWER_BOUND);
2633         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2634
2635         /* Load bootstrap code into instruction SRAM now,
2636          *   to prepare to load "initialize" uCode */
2637         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2638                 BSM_WR_CTRL_REG_BIT_START);
2639
2640         /* Wait for load of bootstrap uCode to finish */
2641         for (i = 0; i < 100; i++) {
2642                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2643                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2644                         break;
2645                 udelay(10);
2646         }
2647         if (i < 100)
2648                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2649         else {
2650                 IWL_ERR(priv, "BSM write did not complete!\n");
2651                 return -EIO;
2652         }
2653
2654         /* Enable future boot loads whenever power management unit triggers it
2655          *   (e.g. when powering back up after power-save shutdown) */
2656         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2657                 BSM_WR_CTRL_REG_BIT_START_EN);
2658
2659         return 0;
2660 }
2661
2662 static struct iwl_hcmd_ops iwl3945_hcmd = {
2663         .rxon_assoc = iwl3945_send_rxon_assoc,
2664         .commit_rxon = iwl3945_commit_rxon,
2665         .send_bt_config = iwl_send_bt_config,
2666 };
2667
2668 static struct iwl_lib_ops iwl3945_lib = {
2669         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2670         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2671         .txq_init = iwl3945_hw_tx_queue_init,
2672         .load_ucode = iwl3945_load_bsm,
2673         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2674         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2675         .apm_ops = {
2676                 .init = iwl3945_apm_init,
2677                 .stop = iwl_apm_stop,
2678                 .config = iwl3945_nic_config,
2679                 .set_pwr_src = iwl3945_set_pwr_src,
2680         },
2681         .eeprom_ops = {
2682                 .regulatory_bands = {
2683                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2684                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2685                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2686                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2687                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2688                         EEPROM_REGULATORY_BAND_NO_HT40,
2689                         EEPROM_REGULATORY_BAND_NO_HT40,
2690                 },
2691                 .verify_signature  = iwlcore_eeprom_verify_signature,
2692                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2693                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2694                 .query_addr = iwlcore_eeprom_query_addr,
2695         },
2696         .send_tx_power  = iwl3945_send_tx_power,
2697         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2698         .post_associate = iwl3945_post_associate,
2699         .isr = iwl_isr_legacy,
2700         .config_ap = iwl3945_config_ap,
2701         .manage_ibss_station = iwl3945_manage_ibss_station,
2702         .check_plcp_health = iwl3945_good_plcp_health,
2703
2704         .debugfs_ops = {
2705                 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2706                 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2707                 .general_stats_read = iwl3945_ucode_general_stats_read,
2708         },
2709 };
2710
2711 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2712         .get_hcmd_size = iwl3945_get_hcmd_size,
2713         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2714         .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2715         .request_scan = iwl3945_request_scan,
2716 };
2717
2718 static const struct iwl_ops iwl3945_ops = {
2719         .lib = &iwl3945_lib,
2720         .hcmd = &iwl3945_hcmd,
2721         .utils = &iwl3945_hcmd_utils,
2722         .led = &iwl3945_led_ops,
2723 };
2724
2725 static struct iwl_cfg iwl3945_bg_cfg = {
2726         .name = "3945BG",
2727         .fw_name_pre = IWL3945_FW_PRE,
2728         .ucode_api_max = IWL3945_UCODE_API_MAX,
2729         .ucode_api_min = IWL3945_UCODE_API_MIN,
2730         .sku = IWL_SKU_G,
2731         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2732         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2733         .ops = &iwl3945_ops,
2734         .num_of_queues = IWL39_NUM_QUEUES,
2735         .mod_params = &iwl3945_mod_params,
2736         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2737         .set_l0s = false,
2738         .use_bsm = true,
2739         .use_isr_legacy = true,
2740         .ht_greenfield_support = false,
2741         .led_compensation = 64,
2742         .broken_powersave = true,
2743         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2744         .monitor_recover_period = IWL_MONITORING_PERIOD,
2745         .max_event_log_size = 512,
2746         .tx_power_by_driver = true,
2747 };
2748
2749 static struct iwl_cfg iwl3945_abg_cfg = {
2750         .name = "3945ABG",
2751         .fw_name_pre = IWL3945_FW_PRE,
2752         .ucode_api_max = IWL3945_UCODE_API_MAX,
2753         .ucode_api_min = IWL3945_UCODE_API_MIN,
2754         .sku = IWL_SKU_A|IWL_SKU_G,
2755         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2756         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2757         .ops = &iwl3945_ops,
2758         .num_of_queues = IWL39_NUM_QUEUES,
2759         .mod_params = &iwl3945_mod_params,
2760         .use_isr_legacy = true,
2761         .ht_greenfield_support = false,
2762         .led_compensation = 64,
2763         .broken_powersave = true,
2764         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2765         .monitor_recover_period = IWL_MONITORING_PERIOD,
2766         .max_event_log_size = 512,
2767         .tx_power_by_driver = true,
2768 };
2769
2770 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2771         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2772         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2773         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2774         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2775         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2776         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2777         {0}
2778 };
2779
2780 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);