drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
  52 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
  53 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
  54 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
  55 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
  56 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
  57 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
  58 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
  59 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
  60
  61 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  62 MODULE_PARM_DESC(debug, "Set debug mask");
  63 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  64 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  65
  66 #define USB_VENDOR_ID_REALTEK           0x0bda
  67 /* Minimum IEEE80211_MAX_FRAME_LEN */
  68 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  69 #define RTL8XXXU_RX_URBS                32
  70 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  71 #define RTL8XXXU_TX_URBS                64
  72 #define RTL8XXXU_TX_URB_LOW_WATER       25
  73 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  74
  75 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  76                                   struct rtl8xxxu_rx_urb *rx_urb);
  77
  78 static struct ieee80211_rate rtl8xxxu_rates[] = {
  79         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  80         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  81         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  82         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  83         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  84         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  85         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  86         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  87         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  88         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  89         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  90         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  91 };
  92
  93 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  94         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
  95           .hw_value = 1, .max_power = 30 },
  96         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
  97           .hw_value = 2, .max_power = 30 },
  98         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
  99           .hw_value = 3, .max_power = 30 },
 100         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
 101           .hw_value = 4, .max_power = 30 },
 102         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
 103           .hw_value = 5, .max_power = 30 },
 104         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
 105           .hw_value = 6, .max_power = 30 },
 106         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
 107           .hw_value = 7, .max_power = 30 },
 108         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
 109           .hw_value = 8, .max_power = 30 },
 110         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
 111           .hw_value = 9, .max_power = 30 },
 112         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
 113           .hw_value = 10, .max_power = 30 },
 114         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
 115           .hw_value = 11, .max_power = 30 },
 116         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
 117           .hw_value = 12, .max_power = 30 },
 118         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
 119           .hw_value = 13, .max_power = 30 },
 120         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
 121           .hw_value = 14, .max_power = 30 }
 122 };
 123
 124 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 125         .channels = rtl8xxxu_channels_2g,
 126         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 127         .bitrates = rtl8xxxu_rates,
 128         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 129 };
 130
 131 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 132         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 133         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 134         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 135         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 136         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 137         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 138         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 139         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 140         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 141         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 142         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 143         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 144         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 145         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 146         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 147         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 148         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 149         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 150         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 151         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 152         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 153         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 154 };
 155
 156 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
 157         {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
 158         {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
 159         {0x430, 0x00}, {0x431, 0x00},
 160         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 161         {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
 162         {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
 163         {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
 164         {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
 165         {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
 166         {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
 167         {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
 168         {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 169         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 170         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 171         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 172         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 173         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 174         {0x516, 0x0a}, {0x525, 0x4f},
 175         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
 176         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 177         {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
 178         {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
 179         {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 180         {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
 181         {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 182         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 183         {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
 184         {0xffff, 0xff},
 185 };
 186
 187 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 188         {0x800, 0x80040000}, {0x804, 0x00000003},
 189         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 190         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 191         {0x818, 0x02200385}, {0x81c, 0x00000000},
 192         {0x820, 0x01000100}, {0x824, 0x00390004},
 193         {0x828, 0x00000000}, {0x82c, 0x00000000},
 194         {0x830, 0x00000000}, {0x834, 0x00000000},
 195         {0x838, 0x00000000}, {0x83c, 0x00000000},
 196         {0x840, 0x00010000}, {0x844, 0x00000000},
 197         {0x848, 0x00000000}, {0x84c, 0x00000000},
 198         {0x850, 0x00000000}, {0x854, 0x00000000},
 199         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 200         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 201         {0x868, 0x00000000}, {0x86c, 0x32323200},
 202         {0x870, 0x07000760}, {0x874, 0x22004000},
 203         {0x878, 0x00000808}, {0x87c, 0x00000000},
 204         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 205         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 206         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 207         {0x898, 0x40302010}, {0x89c, 0x00706050},
 208         {0x900, 0x00000000}, {0x904, 0x00000023},
 209         {0x908, 0x00000000}, {0x90c, 0x81121111},
 210         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 211         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 212         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 213         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 214         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 215         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 216         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 217         {0xa78, 0x00000900},
 218         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 219         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 220         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 221         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 222         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 223         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 224         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 225         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 226         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 227         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 228         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 229         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 230         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 231         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 232         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 233         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 234         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 235         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 236         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 237         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 238         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 239         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 240         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 241         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 242         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 243         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 244         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 245         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 246         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 247         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 248         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 249         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 250         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 251         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 252         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 253         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 254         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 255         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 256         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 257         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 258         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 259         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 260         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 261         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 262         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 263         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 264         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 265         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 266         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 267         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 268         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 269         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 270         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 271         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 272         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 273         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 274         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 275         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 276         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 277         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 278         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 279         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 280         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 281         {0xf00, 0x00000300},
 282         {0xffff, 0xffffffff},
 283 };
 284
 285 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
 286         {0x800, 0x80040000}, {0x804, 0x00000003},
 287         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 288         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 289         {0x818, 0x02200385}, {0x81c, 0x00000000},
 290         {0x820, 0x01000100}, {0x824, 0x00190204},
 291         {0x828, 0x00000000}, {0x82c, 0x00000000},
 292         {0x830, 0x00000000}, {0x834, 0x00000000},
 293         {0x838, 0x00000000}, {0x83c, 0x00000000},
 294         {0x840, 0x00010000}, {0x844, 0x00000000},
 295         {0x848, 0x00000000}, {0x84c, 0x00000000},
 296         {0x850, 0x00000000}, {0x854, 0x00000000},
 297         {0x858, 0x569a11a9}, {0x85c, 0x01000014},
 298         {0x860, 0x66f60110}, {0x864, 0x061f0649},
 299         {0x868, 0x00000000}, {0x86c, 0x27272700},
 300         {0x870, 0x07000760}, {0x874, 0x25004000},
 301         {0x878, 0x00000808}, {0x87c, 0x00000000},
 302         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
 303         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 304         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 305         {0x898, 0x40302010}, {0x89c, 0x00706050},
 306         {0x900, 0x00000000}, {0x904, 0x00000023},
 307         {0x908, 0x00000000}, {0x90c, 0x81121111},
 308         {0x910, 0x00000002}, {0x914, 0x00000201},
 309         {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
 310         {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
 311         {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
 312         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 313         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 314         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 315         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 316         {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
 317         {0xa80, 0x21806490}, {0xb2c, 0x00000000},
 318         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 319         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 320         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 321         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 322         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 323         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 324         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 325         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 326         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 327         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 328         {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
 329         {0xc58, 0x00013149}, {0xc5c, 0x00250492},
 330         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 331         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 332         {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
 333         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 334         {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
 335         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 336         {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
 337         {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
 338         {0xca0, 0x00000000}, {0xca4, 0x000300a0},
 339         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 340         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 341         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 342         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 343         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 344         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 345         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 346         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 347         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 348         {0xd00, 0x00000740}, {0xd04, 0x40020401},
 349         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 350         {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
 351         {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
 352         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 353         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 354         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 355         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 356         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 357         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 358         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 359         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 360         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 361         {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
 362         {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
 363         {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
 364         {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
 365         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 366         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 367         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 368         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 369         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 370         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 371         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 372         {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
 373         {0xe70, 0x00c00096}, {0xe74, 0x01000056},
 374         {0xe78, 0x01000014}, {0xe7c, 0x01000056},
 375         {0xe80, 0x01000014}, {0xe84, 0x00c00096},
 376         {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
 377         {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
 378         {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
 379         {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
 380         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 381         {0xf00, 0x00000300},
 382         {0x820, 0x01000100}, {0x800, 0x83040000},
 383         {0xffff, 0xffffffff},
 384 };
 385
 386 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 387         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 388         {0x800, 0x80040002}, {0x804, 0x00000003},
 389         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 390         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 391         {0x818, 0x02200385}, {0x81c, 0x00000000},
 392         {0x820, 0x01000100}, {0x824, 0x00390004},
 393         {0x828, 0x01000100}, {0x82c, 0x00390004},
 394         {0x830, 0x27272727}, {0x834, 0x27272727},
 395         {0x838, 0x27272727}, {0x83c, 0x27272727},
 396         {0x840, 0x00010000}, {0x844, 0x00010000},
 397         {0x848, 0x27272727}, {0x84c, 0x27272727},
 398         {0x850, 0x00000000}, {0x854, 0x00000000},
 399         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 400         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 401         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 402         {0x870, 0x07000700}, {0x874, 0x22184000},
 403         {0x878, 0x08080808}, {0x87c, 0x00000000},
 404         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 405         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 406         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 407         {0x898, 0x40302010}, {0x89c, 0x00706050},
 408         {0x900, 0x00000000}, {0x904, 0x00000023},
 409         {0x908, 0x00000000}, {0x90c, 0x81121313},
 410         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 411         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 412         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 413         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 414         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 415         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 416         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 417         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 418         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 419         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 420         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 421         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 422         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 423         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 424         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 425         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 426         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 427         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 428         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 429         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 430         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 431         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 432         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 433         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 434         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 435         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 436         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 437         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 438         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 439         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 440         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 441         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 442         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 443         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 444         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 445         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 446         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 447         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 448         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 449         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 450         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 451         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 452         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 453         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 454         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 455         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 456         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 457         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 458         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 459         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 460         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 461         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 462         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 463         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 464         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 465         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 466         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 467         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 468         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 469         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 470         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 471         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 472         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 473         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 474         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 475         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 476         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 477         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 478         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 479         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 480         {0xf00, 0x00000300},
 481         {0xffff, 0xffffffff},
 482 };
 483
 484 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 485         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 486         {0x040, 0x000c0004}, {0x800, 0x80040000},
 487         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 488         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 489         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 490         {0x81c, 0x00000000}, {0x820, 0x01000100},
 491         {0x824, 0x00390204}, {0x828, 0x00000000},
 492         {0x82c, 0x00000000}, {0x830, 0x00000000},
 493         {0x834, 0x00000000}, {0x838, 0x00000000},
 494         {0x83c, 0x00000000}, {0x840, 0x00010000},
 495         {0x844, 0x00000000}, {0x848, 0x00000000},
 496         {0x84c, 0x00000000}, {0x850, 0x00000000},
 497         {0x854, 0x00000000}, {0x858, 0x569a569a},
 498         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 499         {0x864, 0x061f0130}, {0x868, 0x00000000},
 500         {0x86c, 0x20202000}, {0x870, 0x03000300},
 501         {0x874, 0x22004000}, {0x878, 0x00000808},
 502         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 503         {0x884, 0x000004d5}, {0x888, 0x00000000},
 504         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 505         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 506         {0x89c, 0x00706050}, {0x900, 0x00000000},
 507         {0x904, 0x00000023}, {0x908, 0x00000000},
 508         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 509         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 510         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 511         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 512         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 513         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 514         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 515         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 516         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 517         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 518         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 519         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 520         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 521         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 522         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 523         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 524         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 525         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 526         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 527         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 528         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 529         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 530         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 531         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 532         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 533         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 534         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 535         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 536         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 537         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 538         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 539         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 540         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 541         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 542         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 543         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 544         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 545         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 546         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 547         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 548         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 549         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 550         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 551         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 552         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 553         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 554         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 555         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 556         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 557         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 558         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 559         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 560         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 561         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 562         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 563         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 564         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 565         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 566         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 567         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 568         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 569         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 570         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 571         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 572         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 573         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 574         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 575         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 576         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 577         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 578         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 579         {0xf00, 0x00000300},
 580         {0xffff, 0xffffffff},
 581 };
 582
 583 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 584         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 585         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 586         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 587         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 588         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 589         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 590         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 591         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 592         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 593         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 594         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 595         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 596         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 597         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 598         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 599         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 600         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 601         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 602         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 603         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 604         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 605         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 606         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 607         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 608         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 609         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 610         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 611         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 612         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 613         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 614         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 615         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 616         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 617         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 618         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 619         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 620         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 621         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 622         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 623         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 624         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 625         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 626         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 627         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 628         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 629         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 630         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 631         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 632         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 633         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 634         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 635         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 636         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 637         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 638         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 639         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 640         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 641         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 642         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 643         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 644         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 645         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 646         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 647         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 648         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 649         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 650         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 651         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 652         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 653         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 654         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 655         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 656         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 657         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 658         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 659         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 660         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 661         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 662         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 663         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 664         {0xffff, 0xffffffff}
 665 };
 666
 667 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 668         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 669         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 670         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 671         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 672         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 673         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 674         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 675         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 676         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 677         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 678         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 679         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 680         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 681         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 682         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 683         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 684         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 685         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 686         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 687         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 688         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 689         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 690         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 691         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 692         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 693         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 694         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 695         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 696         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 697         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 698         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 699         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 700         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 701         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 702         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 703         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 704         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 705         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 706         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 707         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 708         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 709         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 710         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 711         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 712         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 713         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 714         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 715         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 716         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 717         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 718         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 719         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 720         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 721         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 722         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 723         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 724         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 725         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 726         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 727         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 728         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 729         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 730         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 731         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 732         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 733         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 734         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 735         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 736         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 737         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 738         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 739         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 740         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 741         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 742         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 743         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 744         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 745         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 746         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 747         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 748         {0xffff, 0xffffffff}
 749 };
 750
 751 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
 752         {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
 753         {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
 754         {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
 755         {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
 756         {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
 757         {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
 758         {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
 759         {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
 760         {0xc78, 0xed100001}, {0xc78, 0xec110001},
 761         {0xc78, 0xeb120001}, {0xc78, 0xea130001},
 762         {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
 763         {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
 764         {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
 765         {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
 766         {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
 767         {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
 768         {0xc78, 0x65200001}, {0xc78, 0x64210001},
 769         {0xc78, 0x63220001}, {0xc78, 0x4a230001},
 770         {0xc78, 0x49240001}, {0xc78, 0x48250001},
 771         {0xc78, 0x47260001}, {0xc78, 0x46270001},
 772         {0xc78, 0x45280001}, {0xc78, 0x44290001},
 773         {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
 774         {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
 775         {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
 776         {0xc78, 0x0a300001}, {0xc78, 0x09310001},
 777         {0xc78, 0x08320001}, {0xc78, 0x07330001},
 778         {0xc78, 0x06340001}, {0xc78, 0x05350001},
 779         {0xc78, 0x04360001}, {0xc78, 0x03370001},
 780         {0xc78, 0x02380001}, {0xc78, 0x01390001},
 781         {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
 782         {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
 783         {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
 784         {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
 785         {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
 786         {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
 787         {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
 788         {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
 789         {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
 790         {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
 791         {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
 792         {0xc78, 0xec500001}, {0xc78, 0xeb510001},
 793         {0xc78, 0xea520001}, {0xc78, 0xe9530001},
 794         {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
 795         {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
 796         {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
 797         {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
 798         {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
 799         {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
 800         {0xc78, 0x65600001}, {0xc78, 0x64610001},
 801         {0xc78, 0x63620001}, {0xc78, 0x62630001},
 802         {0xc78, 0x61640001}, {0xc78, 0x48650001},
 803         {0xc78, 0x47660001}, {0xc78, 0x46670001},
 804         {0xc78, 0x45680001}, {0xc78, 0x44690001},
 805         {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
 806         {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
 807         {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
 808         {0xc78, 0x24700001}, {0xc78, 0x09710001},
 809         {0xc78, 0x08720001}, {0xc78, 0x07730001},
 810         {0xc78, 0x06740001}, {0xc78, 0x05750001},
 811         {0xc78, 0x04760001}, {0xc78, 0x03770001},
 812         {0xc78, 0x02780001}, {0xc78, 0x01790001},
 813         {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
 814         {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
 815         {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
 816         {0xc50, 0x69553422},
 817         {0xc50, 0x69553420},
 818         {0x824, 0x00390204},
 819         {0xffff, 0xffffffff}
 820 };
 821
 822 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 823         {0x00, 0x00030159}, {0x01, 0x00031284},
 824         {0x02, 0x00098000}, {0x03, 0x00039c63},
 825         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 826         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 827         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 828         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 829         {0x19, 0x00000000}, {0x1a, 0x00030355},
 830         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 831         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 832         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 833         {0x21, 0x0006c000}, {0x22, 0x00000000},
 834         {0x23, 0x00001558}, {0x24, 0x00000060},
 835         {0x25, 0x00000483}, {0x26, 0x0004f000},
 836         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 837         {0x29, 0x00004783}, {0x2a, 0x00000001},
 838         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 839         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 840         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 841         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 842         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 843         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 844         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 845         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 846         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 847         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 848         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 849         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 850         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 851         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 852         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 853         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 854         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 855         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 856         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 857         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 858         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 859         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 860         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 861         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 862         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 863         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 864         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 865         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 866         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 867         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 868         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 869         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 870         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 871         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 872         {0x10, 0x00000000}, {0x11, 0x00000000},
 873         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 874         {0x10, 0x0009000f}, {0x11, 0x00023100},
 875         {0x12, 0x00032000}, {0x12, 0x00071000},
 876         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 877         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 878         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 879         {0x13, 0x00018493}, {0x13, 0x0001429b},
 880         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 881         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 882         {0x13, 0x00000020}, {0x14, 0x0001944c},
 883         {0x14, 0x00059444}, {0x14, 0x0009944c},
 884         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 885         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 886         {0x15, 0x000cf455}, {0x16, 0x00000339},
 887         {0x16, 0x00040339}, {0x16, 0x00080339},
 888         {0x16, 0x000c0366}, {0x00, 0x00010159},
 889         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 890         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 891         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 892         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 893         {0x00, 0x00030159},
 894         {0xff, 0xffffffff}
 895 };
 896
 897 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
 898         {0x00, 0x00010000}, {0xb0, 0x000dffe0},
 899         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 900         {0xfe, 0x00000000}, {0xb1, 0x00000018},
 901         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 902         {0xfe, 0x00000000}, {0xb2, 0x00084c00},
 903         {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
 904         {0xb7, 0x00000010}, {0xb8, 0x0000907f},
 905         {0x5c, 0x00000002}, {0x7c, 0x00000002},
 906         {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
 907         {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
 908         {0x1e, 0x00000000}, {0xdf, 0x00000780},
 909         {0x50, 0x00067435},
 910         /*
 911          * The 8723bu vendor driver indicates that bit 8 should be set in
 912          * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
 913          * they never actually check the package type - and just default
 914          * to not setting it.
 915          */
 916         {0x51, 0x0006b04e},
 917         {0x52, 0x000007d2}, {0x53, 0x00000000},
 918         {0x54, 0x00050400}, {0x55, 0x0004026e},
 919         {0xdd, 0x0000004c}, {0x70, 0x00067435},
 920         /*
 921          * 0x71 has same package type condition as for register 0x51
 922          */
 923         {0x71, 0x0006b04e},
 924         {0x72, 0x000007d2}, {0x73, 0x00000000},
 925         {0x74, 0x00050400}, {0x75, 0x0004026e},
 926         {0xef, 0x00000100}, {0x34, 0x0000add7},
 927         {0x35, 0x00005c00}, {0x34, 0x00009dd4},
 928         {0x35, 0x00005000}, {0x34, 0x00008dd1},
 929         {0x35, 0x00004400}, {0x34, 0x00007dce},
 930         {0x35, 0x00003800}, {0x34, 0x00006cd1},
 931         {0x35, 0x00004400}, {0x34, 0x00005cce},
 932         {0x35, 0x00003800}, {0x34, 0x000048ce},
 933         {0x35, 0x00004400}, {0x34, 0x000034ce},
 934         {0x35, 0x00003800}, {0x34, 0x00002451},
 935         {0x35, 0x00004400}, {0x34, 0x0000144e},
 936         {0x35, 0x00003800}, {0x34, 0x00000051},
 937         {0x35, 0x00004400}, {0xef, 0x00000000},
 938         {0xef, 0x00000100}, {0xed, 0x00000010},
 939         {0x44, 0x0000add7}, {0x44, 0x00009dd4},
 940         {0x44, 0x00008dd1}, {0x44, 0x00007dce},
 941         {0x44, 0x00006cc1}, {0x44, 0x00005cce},
 942         {0x44, 0x000044d1}, {0x44, 0x000034ce},
 943         {0x44, 0x00002451}, {0x44, 0x0000144e},
 944         {0x44, 0x00000051}, {0xef, 0x00000000},
 945         {0xed, 0x00000000}, {0x7f, 0x00020080},
 946         {0xef, 0x00002000}, {0x3b, 0x000380ef},
 947         {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
 948         {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
 949         {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
 950         {0x3b, 0x00000900}, {0xef, 0x00000000},
 951         {0xed, 0x00000001}, {0x40, 0x000380ef},
 952         {0x40, 0x000302fe}, {0x40, 0x00028ce6},
 953         {0x40, 0x000200bc}, {0x40, 0x000188a5},
 954         {0x40, 0x00010fbc}, {0x40, 0x00008f71},
 955         {0x40, 0x00000900}, {0xed, 0x00000000},
 956         {0x82, 0x00080000}, {0x83, 0x00008000},
 957         {0x84, 0x00048d80}, {0x85, 0x00068000},
 958         {0xa2, 0x00080000}, {0xa3, 0x00008000},
 959         {0xa4, 0x00048d80}, {0xa5, 0x00068000},
 960         {0xed, 0x00000002}, {0xef, 0x00000002},
 961         {0x56, 0x00000032}, {0x76, 0x00000032},
 962         {0x01, 0x00000780},
 963         {0xff, 0xffffffff}
 964 };
 965
 966 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 967         {0x00, 0x00030159}, {0x01, 0x00031284},
 968         {0x02, 0x00098000}, {0x03, 0x00018c63},
 969         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 970         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 971         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 972         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 973         {0x19, 0x00000000}, {0x1a, 0x00010255},
 974         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 975         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 976         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 977         {0x21, 0x0006c000}, {0x22, 0x00000000},
 978         {0x23, 0x00001558}, {0x24, 0x00000060},
 979         {0x25, 0x00000483}, {0x26, 0x0004f000},
 980         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 981         {0x29, 0x00004783}, {0x2a, 0x00000001},
 982         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 983         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 984         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 985         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 986         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 987         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 988         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 989         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 990         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 991         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 992         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 993         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 994         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 995         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 996         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 997         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 998         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 999         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016         {0x10, 0x00000000}, {0x11, 0x00000000},
1017         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018         {0x10, 0x0009000f}, {0x11, 0x00023100},
1019         {0x12, 0x00032000}, {0x12, 0x00071000},
1020         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021         {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023         {0x13, 0x00018493}, {0x13, 0x0001429b},
1024         {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025         {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026         {0x13, 0x00000020}, {0x14, 0x0001944c},
1027         {0x14, 0x00059444}, {0x14, 0x0009944c},
1028         {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029         {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030         {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031         {0x16, 0x000a0330}, {0x16, 0x00060330},
1032         {0x16, 0x00020330}, {0x00, 0x00010159},
1033         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037         {0x00, 0x00030159},
1038         {0xff, 0xffffffff}
1039 };
1040
1041 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042         {0x00, 0x00030159}, {0x01, 0x00031284},
1043         {0x02, 0x00098000}, {0x03, 0x00018c63},
1044         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048         {0x12, 0x00032000}, {0x12, 0x00071000},
1049         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050         {0x13, 0x000287af}, {0x13, 0x000244b7},
1051         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052         {0x13, 0x00018493}, {0x13, 0x00014297},
1053         {0x13, 0x00010295}, {0x13, 0x0000c298},
1054         {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055         {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056         {0x14, 0x00059444}, {0x14, 0x0009944c},
1057         {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058         {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059         {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060         {0x16, 0x000a0330}, {0x16, 0x00060330},
1061         {0x16, 0x00020330},
1062         {0xff, 0xffffffff}
1063 };
1064
1065 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066         {0x00, 0x00030159}, {0x01, 0x00031284},
1067         {0x02, 0x00098000}, {0x03, 0x00018c63},
1068         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072         {0x19, 0x00000000}, {0x1a, 0x00010255},
1073         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075         {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076         {0x21, 0x0006c000}, {0x22, 0x00000000},
1077         {0x23, 0x00001558}, {0x24, 0x00000060},
1078         {0x25, 0x00000483}, {0x26, 0x0004f000},
1079         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080         {0x29, 0x00004783}, {0x2a, 0x00000001},
1081         {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082         {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083         {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087         {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091         {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115         {0x10, 0x00000000}, {0x11, 0x00000000},
1116         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117         {0x10, 0x0009000f}, {0x11, 0x00023100},
1118         {0x12, 0x00032000}, {0x12, 0x00071000},
1119         {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120         {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122         {0x13, 0x00018493}, {0x13, 0x0001429b},
1123         {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124         {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125         {0x13, 0x00000020}, {0x14, 0x0001944c},
1126         {0x14, 0x00059444}, {0x14, 0x0009944c},
1127         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130         {0x16, 0x000a0330}, {0x16, 0x00060330},
1131         {0x16, 0x00020330}, {0x00, 0x00010159},
1132         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136         {0x00, 0x00030159},
1137         {0xff, 0xffffffff}
1138 };
1139
1140 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141         {0x00, 0x00030159}, {0x01, 0x00031284},
1142         {0x02, 0x00098000}, {0x03, 0x00018c63},
1143         {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147         {0x19, 0x00000000}, {0x1a, 0x00000255},
1148         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150         {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151         {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152         {0x23, 0x00001558}, {0x24, 0x00000060},
1153         {0x25, 0x00000483}, {0x26, 0x0004f000},
1154         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155         {0x29, 0x00004783}, {0x2a, 0x00000001},
1156         {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157         {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158         {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162         {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166         {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170         {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188         {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189         {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190         {0x10, 0x00000000}, {0x11, 0x00000000},
1191         {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192         {0x10, 0x0009000f}, {0x11, 0x00023100},
1193         {0x12, 0x000d8000}, {0x12, 0x00090000},
1194         {0x12, 0x00051000}, {0x12, 0x00012000},
1195         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197         {0x13, 0x000183a4}, {0x13, 0x00014398},
1198         {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199         {0x13, 0x000080a4}, {0x13, 0x00004098},
1200         {0x13, 0x00000000}, {0x14, 0x0001944c},
1201         {0x14, 0x00059444}, {0x14, 0x0009944c},
1202         {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203         {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204         {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205         {0x16, 0x000a0330}, {0x16, 0x00060330},
1206         {0x16, 0x00020330}, {0x00, 0x00010159},
1207         {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208         {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209         {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210         {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211         {0x00, 0x00030159},
1212         {0xff, 0xffffffff}
1213 };
1214
1215 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216         {       /* RF_A */
1217                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220                 .hspiread = REG_HSPI_XA_READBACK,
1221                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223         },
1224         {       /* RF_B */
1225                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228                 .hspiread = REG_HSPI_XB_READBACK,
1229                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231         },
1232 };
1233
1234 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235         REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236         REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237         REG_OFDM0_ENERGY_CCA_THRES,
1238         REG_OFDM0_AGCR_SSI_TABLE,
1239         REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240         REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241         REG_OFDM0_XC_TX_AFE,
1242         REG_OFDM0_XD_TX_AFE,
1243         REG_OFDM0_RX_IQ_EXT_ANTA
1244 };
1245
1246 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247 {
1248         struct usb_device *udev = priv->udev;
1249         int len;
1250         u8 data;
1251
1252         mutex_lock(&priv->usb_buf_mutex);
1253         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256                               RTW_USB_CONTROL_MSG_TIMEOUT);
1257         data = priv->usb_buf.val8;
1258         mutex_unlock(&priv->usb_buf_mutex);
1259
1260         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
1262                          __func__, addr, data, len);
1263         return data;
1264 }
1265
1266 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267 {
1268         struct usb_device *udev = priv->udev;
1269         int len;
1270         u16 data;
1271
1272         mutex_lock(&priv->usb_buf_mutex);
1273         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276                               RTW_USB_CONTROL_MSG_TIMEOUT);
1277         data = le16_to_cpu(priv->usb_buf.val16);
1278         mutex_unlock(&priv->usb_buf_mutex);
1279
1280         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1282                          __func__, addr, data, len);
1283         return data;
1284 }
1285
1286 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287 {
1288         struct usb_device *udev = priv->udev;
1289         int len;
1290         u32 data;
1291
1292         mutex_lock(&priv->usb_buf_mutex);
1293         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296                               RTW_USB_CONTROL_MSG_TIMEOUT);
1297         data = le32_to_cpu(priv->usb_buf.val32);
1298         mutex_unlock(&priv->usb_buf_mutex);
1299
1300         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1302                          __func__, addr, data, len);
1303         return data;
1304 }
1305
1306 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307 {
1308         struct usb_device *udev = priv->udev;
1309         int ret;
1310
1311         mutex_lock(&priv->usb_buf_mutex);
1312         priv->usb_buf.val8 = val;
1313         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316                               RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318         mutex_unlock(&priv->usb_buf_mutex);
1319
1320         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322                          __func__, addr, val);
1323         return ret;
1324 }
1325
1326 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327 {
1328         struct usb_device *udev = priv->udev;
1329         int ret;
1330
1331         mutex_lock(&priv->usb_buf_mutex);
1332         priv->usb_buf.val16 = cpu_to_le16(val);
1333         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336                               RTW_USB_CONTROL_MSG_TIMEOUT);
1337         mutex_unlock(&priv->usb_buf_mutex);
1338
1339         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341                          __func__, addr, val);
1342         return ret;
1343 }
1344
1345 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346 {
1347         struct usb_device *udev = priv->udev;
1348         int ret;
1349
1350         mutex_lock(&priv->usb_buf_mutex);
1351         priv->usb_buf.val32 = cpu_to_le32(val);
1352         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355                               RTW_USB_CONTROL_MSG_TIMEOUT);
1356         mutex_unlock(&priv->usb_buf_mutex);
1357
1358         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360                          __func__, addr, val);
1361         return ret;
1362 }
1363
1364 static int
1365 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366 {
1367         struct usb_device *udev = priv->udev;
1368         int blocksize = priv->fops->writeN_block_size;
1369         int ret, i, count, remainder;
1370
1371         count = len / blocksize;
1372         remainder = len % blocksize;
1373
1374         for (i = 0; i < count; i++) {
1375                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377                                       addr, 0, buf, blocksize,
1378                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1379                 if (ret != blocksize)
1380                         goto write_error;
1381
1382                 addr += blocksize;
1383                 buf += blocksize;
1384         }
1385
1386         if (remainder) {
1387                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389                                       addr, 0, buf, remainder,
1390                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1391                 if (ret != remainder)
1392                         goto write_error;
1393         }
1394
1395         return len;
1396
1397 write_error:
1398         dev_info(&udev->dev,
1399                  "%s: Failed to write block at addr: %04x size: %04x\n",
1400                  __func__, addr, blocksize);
1401         return -EAGAIN;
1402 }
1403
1404 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405                                enum rtl8xxxu_rfpath path, u8 reg)
1406 {
1407         u32 hssia, val32, retval;
1408
1409         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410         if (path != RF_A)
1411                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412         else
1413                 val32 = hssia;
1414
1415         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421         udelay(10);
1422
1423         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424         udelay(100);
1425
1426         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428         udelay(10);
1429
1430         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431         if (val32 & FPGA0_HSSI_PARM1_PI)
1432                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433         else
1434                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436         retval &= 0xfffff;
1437
1438         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440                          __func__, reg, retval);
1441         return retval;
1442 }
1443
1444 /*
1445  * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446  * have write issues in high temperature conditions. We may have to
1447  * retry writing them.
1448  */
1449 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451 {
1452         int ret, retval;
1453         u32 dataaddr;
1454
1455         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457                          __func__, reg, data);
1458
1459         data &= FPGA0_LSSI_PARM_DATA_MASK;
1460         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462         /* Use XB for path B */
1463         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464         if (ret != sizeof(dataaddr))
1465                 retval = -EIO;
1466         else
1467                 retval = 0;
1468
1469         udelay(1);
1470
1471         return retval;
1472 }
1473
1474 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475                             struct h2c_cmd *h2c, int len)
1476 {
1477         struct device *dev = &priv->udev->dev;
1478         int mbox_nr, retry, retval = 0;
1479         int mbox_reg, mbox_ext_reg;
1480         u8 val8;
1481
1482         mutex_lock(&priv->h2c_mutex);
1483
1484         mbox_nr = priv->next_mbox;
1485         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1486         mbox_ext_reg = priv->fops->mbox_ext_reg +
1487                 (mbox_nr * priv->fops->mbox_ext_width);
1488
1489         /*
1490          * MBOX ready?
1491          */
1492         retry = 100;
1493         do {
1494                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495                 if (!(val8 & BIT(mbox_nr)))
1496                         break;
1497         } while (retry--);
1498
1499         if (!retry) {
1500                 dev_info(dev, "%s: Mailbox busy\n", __func__);
1501                 retval = -EBUSY;
1502                 goto error;
1503         }
1504
1505         /*
1506          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1507          */
1508         if (len > sizeof(u32)) {
1509                 if (priv->fops->mbox_ext_width == 4) {
1510                         rtl8xxxu_write32(priv, mbox_ext_reg,
1511                                          le32_to_cpu(h2c->raw_wide.ext));
1512                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513                                 dev_info(dev, "H2C_EXT %08x\n",
1514                                          le32_to_cpu(h2c->raw_wide.ext));
1515                 } else {
1516                         rtl8xxxu_write16(priv, mbox_ext_reg,
1517                                          le16_to_cpu(h2c->raw.ext));
1518                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519                                 dev_info(dev, "H2C_EXT %04x\n",
1520                                          le16_to_cpu(h2c->raw.ext));
1521                 }
1522         }
1523         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1526
1527         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1528
1529 error:
1530         mutex_unlock(&priv->h2c_mutex);
1531         return retval;
1532 }
1533
1534 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1535 {
1536         struct h2c_cmd h2c;
1537         int reqnum = 0;
1538
1539         memset(&h2c, 0, sizeof(struct h2c_cmd));
1540         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1541         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1542         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1543         h2c.bt_mp_oper.data = data;
1544         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1545
1546         reqnum++;
1547         memset(&h2c, 0, sizeof(struct h2c_cmd));
1548         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1549         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1550         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1551         h2c.bt_mp_oper.addr = reg;
1552         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1553 }
1554
1555 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1556 {
1557         u8 val8;
1558         u32 val32;
1559
1560         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1561         val8 |= BIT(0) | BIT(3);
1562         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1563
1564         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1565         val32 &= ~(BIT(4) | BIT(5));
1566         val32 |= BIT(3);
1567         if (priv->rf_paths == 2) {
1568                 val32 &= ~(BIT(20) | BIT(21));
1569                 val32 |= BIT(19);
1570         }
1571         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1572
1573         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1574         val32 &= ~OFDM_RF_PATH_TX_MASK;
1575         if (priv->tx_paths == 2)
1576                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1577         else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1578                 val32 |= OFDM_RF_PATH_TX_B;
1579         else
1580                 val32 |= OFDM_RF_PATH_TX_A;
1581         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1582
1583         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1584         val32 &= ~FPGA_RF_MODE_JAPAN;
1585         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1586
1587         if (priv->rf_paths == 2)
1588                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1589         else
1590                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1591
1592         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1593         if (priv->rf_paths == 2)
1594                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1595
1596         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1597 }
1598
1599 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1600 {
1601         u8 sps0;
1602         u32 val32;
1603
1604         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1605
1606         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1607
1608         /* RF RX code for preamble power saving */
1609         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1610         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1611         if (priv->rf_paths == 2)
1612                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1613         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1614
1615         /* Disable TX for four paths */
1616         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1617         val32 &= ~OFDM_RF_PATH_TX_MASK;
1618         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1619
1620         /* Enable power saving */
1621         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1622         val32 |= FPGA_RF_MODE_JAPAN;
1623         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1624
1625         /* AFE control register to power down bits [30:22] */
1626         if (priv->rf_paths == 2)
1627                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1628         else
1629                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1630
1631         /* Power down RF module */
1632         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1633         if (priv->rf_paths == 2)
1634                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1635
1636         sps0 &= ~(BIT(0) | BIT(3));
1637         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1638 }
1639
1640
1641 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1642 {
1643         u8 val8;
1644
1645         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1646         val8 &= ~BIT(6);
1647         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1648
1649         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1650         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1651         val8 &= ~BIT(0);
1652         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1653 }
1654
1655
1656 /*
1657  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1658  * supports the 2.4GHz band, so channels 1 - 14:
1659  *  group 0: channels 1 - 3
1660  *  group 1: channels 4 - 9
1661  *  group 2: channels 10 - 14
1662  *
1663  * Note: We index from 0 in the code
1664  */
1665 static int rtl8723a_channel_to_group(int channel)
1666 {
1667         int group;
1668
1669         if (channel < 4)
1670                 group = 0;
1671         else if (channel < 10)
1672                 group = 1;
1673         else
1674                 group = 2;
1675
1676         return group;
1677 }
1678
1679 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1680 {
1681         struct rtl8xxxu_priv *priv = hw->priv;
1682         u32 val32, rsr;
1683         u8 val8, opmode;
1684         bool ht = true;
1685         int sec_ch_above, channel;
1686         int i;
1687
1688         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1689         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1690         channel = hw->conf.chandef.chan->hw_value;
1691
1692         switch (hw->conf.chandef.width) {
1693         case NL80211_CHAN_WIDTH_20_NOHT:
1694                 ht = false;
1695         case NL80211_CHAN_WIDTH_20:
1696                 opmode |= BW_OPMODE_20MHZ;
1697                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1698
1699                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1700                 val32 &= ~FPGA_RF_MODE;
1701                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1702
1703                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1704                 val32 &= ~FPGA_RF_MODE;
1705                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1706
1707                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1708                 val32 |= FPGA0_ANALOG2_20MHZ;
1709                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1710                 break;
1711         case NL80211_CHAN_WIDTH_40:
1712                 if (hw->conf.chandef.center_freq1 >
1713                     hw->conf.chandef.chan->center_freq) {
1714                         sec_ch_above = 1;
1715                         channel += 2;
1716                 } else {
1717                         sec_ch_above = 0;
1718                         channel -= 2;
1719                 }
1720
1721                 opmode &= ~BW_OPMODE_20MHZ;
1722                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1723                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1724                 if (sec_ch_above)
1725                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1726                 else
1727                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1728                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1729
1730                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1731                 val32 |= FPGA_RF_MODE;
1732                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1733
1734                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1735                 val32 |= FPGA_RF_MODE;
1736                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1737
1738                 /*
1739                  * Set Control channel to upper or lower. These settings
1740                  * are required only for 40MHz
1741                  */
1742                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1743                 val32 &= ~CCK0_SIDEBAND;
1744                 if (!sec_ch_above)
1745                         val32 |= CCK0_SIDEBAND;
1746                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1747
1748                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1749                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1750                 if (sec_ch_above)
1751                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1752                 else
1753                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1754                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1755
1756                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1757                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1758                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1759
1760                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1761                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1762                 if (sec_ch_above)
1763                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1764                 else
1765                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1766                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1767                 break;
1768
1769         default:
1770                 break;
1771         }
1772
1773         for (i = RF_A; i < priv->rf_paths; i++) {
1774                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1775                 val32 &= ~MODE_AG_CHANNEL_MASK;
1776                 val32 |= channel;
1777                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1778         }
1779
1780         if (ht)
1781                 val8 = 0x0e;
1782         else
1783                 val8 = 0x0a;
1784
1785         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1786         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1787
1788         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1789         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1790
1791         for (i = RF_A; i < priv->rf_paths; i++) {
1792                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1793                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1794                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1795                 else
1796                         val32 |= MODE_AG_CHANNEL_20MHZ;
1797                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1798         }
1799 }
1800
1801 static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1802 {
1803         struct rtl8xxxu_priv *priv = hw->priv;
1804         u32 val32, rsr;
1805         u8 val8, subchannel;
1806         u16 rf_mode_bw;
1807         bool ht = true;
1808         int sec_ch_above, channel;
1809         int i;
1810
1811         rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1812         rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1813         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1814         channel = hw->conf.chandef.chan->hw_value;
1815
1816 /* Hack */
1817         subchannel = 0;
1818
1819         switch (hw->conf.chandef.width) {
1820         case NL80211_CHAN_WIDTH_20_NOHT:
1821                 ht = false;
1822         case NL80211_CHAN_WIDTH_20:
1823                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1824                 subchannel = 0;
1825
1826                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1827                 val32 &= ~FPGA_RF_MODE;
1828                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1829
1830                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1831                 val32 &= ~FPGA_RF_MODE;
1832                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1833
1834                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1835                 val32 &= ~(BIT(30) | BIT(31));
1836                 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1837
1838                 break;
1839         case NL80211_CHAN_WIDTH_40:
1840                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1841
1842                 if (hw->conf.chandef.center_freq1 >
1843                     hw->conf.chandef.chan->center_freq) {
1844                         sec_ch_above = 1;
1845                         channel += 2;
1846                 } else {
1847                         sec_ch_above = 0;
1848                         channel -= 2;
1849                 }
1850
1851                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1852                 val32 |= FPGA_RF_MODE;
1853                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1854
1855                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1856                 val32 |= FPGA_RF_MODE;
1857                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1858
1859                 /*
1860                  * Set Control channel to upper or lower. These settings
1861                  * are required only for 40MHz
1862                  */
1863                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1864                 val32 &= ~CCK0_SIDEBAND;
1865                 if (!sec_ch_above)
1866                         val32 |= CCK0_SIDEBAND;
1867                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1868
1869                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1870                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1871                 if (sec_ch_above)
1872                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1873                 else
1874                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1875                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1876
1877                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1878                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1879                 if (sec_ch_above)
1880                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1881                 else
1882                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1883                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1884                 break;
1885         case NL80211_CHAN_WIDTH_80:
1886                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1887                 break;
1888         default:
1889                 break;
1890         }
1891
1892         for (i = RF_A; i < priv->rf_paths; i++) {
1893                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1894                 val32 &= ~MODE_AG_CHANNEL_MASK;
1895                 val32 |= channel;
1896                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1897         }
1898
1899         rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1900         rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1901
1902         if (ht)
1903                 val8 = 0x0e;
1904         else
1905                 val8 = 0x0a;
1906
1907         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1908         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1909
1910         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1911         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1912
1913         for (i = RF_A; i < priv->rf_paths; i++) {
1914                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1915                 val32 &= ~MODE_AG_BW_MASK;
1916                 switch(hw->conf.chandef.width) {
1917                 case NL80211_CHAN_WIDTH_80:
1918                         val32 |= MODE_AG_BW_80MHZ_8723B;
1919                         break;
1920                 case NL80211_CHAN_WIDTH_40:
1921                         val32 |= MODE_AG_BW_40MHZ_8723B;
1922                         break;
1923                 default:
1924                         val32 |= MODE_AG_BW_20MHZ_8723B;
1925                         break;
1926                 }
1927                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1928         }
1929 }
1930
1931 static void
1932 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1933 {
1934         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1935         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1936         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1937         u8 val8;
1938         int group, i;
1939
1940         group = rtl8723a_channel_to_group(channel);
1941
1942         cck[0] = priv->cck_tx_power_index_A[group];
1943         cck[1] = priv->cck_tx_power_index_B[group];
1944
1945         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1946         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1947
1948         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1949         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1950
1951         mcsbase[0] = ofdm[0];
1952         mcsbase[1] = ofdm[1];
1953         if (!ht40) {
1954                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1955                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1956         }
1957
1958         if (priv->tx_paths > 1) {
1959                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1960                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1961                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1962                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1963         }
1964
1965         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1966                 dev_info(&priv->udev->dev,
1967                          "%s: Setting TX power CCK A: %02x, "
1968                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1969                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1970
1971         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1972                 if (cck[i] > RF6052_MAX_TX_PWR)
1973                         cck[i] = RF6052_MAX_TX_PWR;
1974                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1975                         ofdm[i] = RF6052_MAX_TX_PWR;
1976         }
1977
1978         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1979         val32 &= 0xffff00ff;
1980         val32 |= (cck[0] << 8);
1981         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1982
1983         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1984         val32 &= 0xff;
1985         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1986         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1987
1988         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1989         val32 &= 0xffffff00;
1990         val32 |= cck[1];
1991         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1992
1993         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1994         val32 &= 0xff;
1995         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1996         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1997
1998         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1999                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2000         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2001                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2002         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2003         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2004
2005         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2006         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2007
2008         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2009                 mcsbase[0] << 16 | mcsbase[0] << 24;
2010         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2011                 mcsbase[1] << 16 | mcsbase[1] << 24;
2012
2013         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2014         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2015
2016         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2017         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2018
2019         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2020         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2021
2022         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2023         for (i = 0; i < 3; i++) {
2024                 if (i != 2)
2025                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2026                 else
2027                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2028                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2029         }
2030         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2031         for (i = 0; i < 3; i++) {
2032                 if (i != 2)
2033                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2034                 else
2035                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2036                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2037         }
2038 }
2039
2040 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2041                                   enum nl80211_iftype linktype)
2042 {
2043         u8 val8;
2044
2045         val8 = rtl8xxxu_read8(priv, REG_MSR);
2046         val8 &= ~MSR_LINKTYPE_MASK;
2047
2048         switch (linktype) {
2049         case NL80211_IFTYPE_UNSPECIFIED:
2050                 val8 |= MSR_LINKTYPE_NONE;
2051                 break;
2052         case NL80211_IFTYPE_ADHOC:
2053                 val8 |= MSR_LINKTYPE_ADHOC;
2054                 break;
2055         case NL80211_IFTYPE_STATION:
2056                 val8 |= MSR_LINKTYPE_STATION;
2057                 break;
2058         case NL80211_IFTYPE_AP:
2059                 val8 |= MSR_LINKTYPE_AP;
2060                 break;
2061         default:
2062                 goto out;
2063         }
2064
2065         rtl8xxxu_write8(priv, REG_MSR, val8);
2066 out:
2067         return;
2068 }
2069
2070 static void
2071 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2072 {
2073         u16 val16;
2074
2075         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2076                  RETRY_LIMIT_SHORT_MASK) |
2077                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2078                  RETRY_LIMIT_LONG_MASK);
2079
2080         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2081 }
2082
2083 static void
2084 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2085 {
2086         u16 val16;
2087
2088         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2089                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2090
2091         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2092 }
2093
2094 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2095 {
2096         struct device *dev = &priv->udev->dev;
2097         char *cut;
2098
2099         switch (priv->chip_cut) {
2100         case 0:
2101                 cut = "A";
2102                 break;
2103         case 1:
2104                 cut = "B";
2105                 break;
2106         case 2:
2107                 cut = "C";
2108                 break;
2109         case 3:
2110                 cut = "D";
2111                 break;
2112         case 4:
2113                 cut = "E";
2114                 break;
2115         default:
2116                 cut = "unknown";
2117         }
2118
2119         dev_info(dev,
2120                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
2121                  priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2122                  priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2123                  priv->has_bluetooth, priv->has_gps, priv->hi_pa);
2124
2125         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2126 }
2127
2128 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2129 {
2130         struct device *dev = &priv->udev->dev;
2131         u32 val32, bonding;
2132         u16 val16;
2133
2134         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2135         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2136                 SYS_CFG_CHIP_VERSION_SHIFT;
2137         if (val32 & SYS_CFG_TRP_VAUX_EN) {
2138                 dev_info(dev, "Unsupported test chip\n");
2139                 return -ENOTSUPP;
2140         }
2141
2142         if (val32 & SYS_CFG_BT_FUNC) {
2143                 if (priv->chip_cut >= 3) {
2144                         sprintf(priv->chip_name, "8723BU");
2145                         priv->rtlchip = 0x8723b;
2146                 } else {
2147                         sprintf(priv->chip_name, "8723AU");
2148                         priv->usb_interrupts = 1;
2149                         priv->rtlchip = 0x8723a;
2150                 }
2151
2152                 priv->rf_paths = 1;
2153                 priv->rx_paths = 1;
2154                 priv->tx_paths = 1;
2155
2156                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2157                 if (val32 & MULTI_WIFI_FUNC_EN)
2158                         priv->has_wifi = 1;
2159                 if (val32 & MULTI_BT_FUNC_EN)
2160                         priv->has_bluetooth = 1;
2161                 if (val32 & MULTI_GPS_FUNC_EN)
2162                         priv->has_gps = 1;
2163                 priv->is_multi_func = 1;
2164         } else if (val32 & SYS_CFG_TYPE_ID) {
2165                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2166                 bonding &= HPON_FSM_BONDING_MASK;
2167                 if (priv->chip_cut >= 3) {
2168                         if (bonding == HPON_FSM_BONDING_1T2R) {
2169                                 sprintf(priv->chip_name, "8191EU");
2170                                 priv->rf_paths = 2;
2171                                 priv->rx_paths = 2;
2172                                 priv->tx_paths = 1;
2173                                 priv->rtlchip = 0x8191e;
2174                         } else {
2175                                 sprintf(priv->chip_name, "8192EU");
2176                                 priv->rf_paths = 2;
2177                                 priv->rx_paths = 2;
2178                                 priv->tx_paths = 2;
2179                                 priv->rtlchip = 0x8192e;
2180                         }
2181                 } else if (bonding == HPON_FSM_BONDING_1T2R) {
2182                         sprintf(priv->chip_name, "8191CU");
2183                         priv->rf_paths = 2;
2184                         priv->rx_paths = 2;
2185                         priv->tx_paths = 1;
2186                         priv->usb_interrupts = 1;
2187                         priv->rtlchip = 0x8191c;
2188                 } else {
2189                         sprintf(priv->chip_name, "8192CU");
2190                         priv->rf_paths = 2;
2191                         priv->rx_paths = 2;
2192                         priv->tx_paths = 2;
2193                         priv->usb_interrupts = 1;
2194                         priv->rtlchip = 0x8192c;
2195                 }
2196                 priv->has_wifi = 1;
2197         } else {
2198                 sprintf(priv->chip_name, "8188CU");
2199                 priv->rf_paths = 1;
2200                 priv->rx_paths = 1;
2201                 priv->tx_paths = 1;
2202                 priv->rtlchip = 0x8188c;
2203                 priv->usb_interrupts = 1;
2204                 priv->has_wifi = 1;
2205         }
2206
2207         switch (priv->rtlchip) {
2208         case 0x8188e:
2209         case 0x8192e:
2210         case 0x8723b:
2211                 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2212                 case SYS_CFG_VENDOR_ID_TSMC:
2213                         sprintf(priv->chip_vendor, "TSMC");
2214                         break;
2215                 case SYS_CFG_VENDOR_ID_SMIC:
2216                         sprintf(priv->chip_vendor, "SMIC");
2217                         priv->vendor_smic = 1;
2218                         break;
2219                 case SYS_CFG_VENDOR_ID_UMC:
2220                         sprintf(priv->chip_vendor, "UMC");
2221                         priv->vendor_umc = 1;
2222                         break;
2223                 default:
2224                         sprintf(priv->chip_vendor, "unknown");
2225                 }
2226                 break;
2227         default:
2228                 if (val32 & SYS_CFG_VENDOR_ID) {
2229                         sprintf(priv->chip_vendor, "UMC");
2230                         priv->vendor_umc = 1;
2231                 } else {
2232                         sprintf(priv->chip_vendor, "TSMC");
2233                 }
2234         }
2235
2236         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2237         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2238
2239         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2240         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2241                 priv->ep_tx_high_queue = 1;
2242                 priv->ep_tx_count++;
2243         }
2244
2245         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2246                 priv->ep_tx_normal_queue = 1;
2247                 priv->ep_tx_count++;
2248         }
2249
2250         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2251                 priv->ep_tx_low_queue = 1;
2252                 priv->ep_tx_count++;
2253         }
2254
2255         /*
2256          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2257          */
2258         if (!priv->ep_tx_count) {
2259                 switch (priv->nr_out_eps) {
2260                 case 4:
2261                 case 3:
2262                         priv->ep_tx_low_queue = 1;
2263                         priv->ep_tx_count++;
2264                 case 2:
2265                         priv->ep_tx_normal_queue = 1;
2266                         priv->ep_tx_count++;
2267                 case 1:
2268                         priv->ep_tx_high_queue = 1;
2269                         priv->ep_tx_count++;
2270                         break;
2271                 default:
2272                         dev_info(dev, "Unsupported USB TX end-points\n");
2273                         return -ENOTSUPP;
2274                 }
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2281 {
2282         struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2283
2284         if (efuse->rtl_id != cpu_to_le16(0x8129))
2285                 return -EINVAL;
2286
2287         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2288
2289         memcpy(priv->cck_tx_power_index_A,
2290                efuse->cck_tx_power_index_A,
2291                sizeof(priv->cck_tx_power_index_A));
2292         memcpy(priv->cck_tx_power_index_B,
2293                efuse->cck_tx_power_index_B,
2294                sizeof(priv->cck_tx_power_index_B));
2295
2296         memcpy(priv->ht40_1s_tx_power_index_A,
2297                efuse->ht40_1s_tx_power_index_A,
2298                sizeof(priv->ht40_1s_tx_power_index_A));
2299         memcpy(priv->ht40_1s_tx_power_index_B,
2300                efuse->ht40_1s_tx_power_index_B,
2301                sizeof(priv->ht40_1s_tx_power_index_B));
2302
2303         memcpy(priv->ht20_tx_power_index_diff,
2304                efuse->ht20_tx_power_index_diff,
2305                sizeof(priv->ht20_tx_power_index_diff));
2306         memcpy(priv->ofdm_tx_power_index_diff,
2307                efuse->ofdm_tx_power_index_diff,
2308                sizeof(priv->ofdm_tx_power_index_diff));
2309
2310         memcpy(priv->ht40_max_power_offset,
2311                efuse->ht40_max_power_offset,
2312                sizeof(priv->ht40_max_power_offset));
2313         memcpy(priv->ht20_max_power_offset,
2314                efuse->ht20_max_power_offset,
2315                sizeof(priv->ht20_max_power_offset));
2316
2317         if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2318                 priv->has_xtalk = 1;
2319                 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2320         }
2321         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2322                  efuse->vendor_name);
2323         dev_info(&priv->udev->dev, "Product: %.41s\n",
2324                  efuse->device_name);
2325         return 0;
2326 }
2327
2328 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2329 {
2330         struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
2331
2332         if (efuse->rtl_id != cpu_to_le16(0x8129))
2333                 return -EINVAL;
2334
2335         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2336
2337         memcpy(priv->cck_tx_power_index_A, efuse->cck_tx_power_index_A,
2338                sizeof(priv->cck_tx_power_index_A));
2339         memcpy(priv->cck_tx_power_index_B, efuse->cck_tx_power_index_B,
2340                sizeof(priv->cck_tx_power_index_B));
2341
2342         memcpy(priv->ht40_1s_tx_power_index_A, efuse->ht40_1s_tx_power_index_A,
2343                sizeof(priv->ht40_1s_tx_power_index_A));
2344         memcpy(priv->ht40_1s_tx_power_index_B, efuse->ht40_1s_tx_power_index_B,
2345                sizeof(priv->ht40_1s_tx_power_index_B));
2346
2347         priv->has_xtalk = 1;
2348         priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2349
2350         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2351         dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
2352
2353         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2354                 int i;
2355                 unsigned char *raw = priv->efuse_wifi.raw;
2356
2357                 dev_info(&priv->udev->dev,
2358                          "%s: dumping efuse (0x%02zx bytes):\n",
2359                          __func__, sizeof(struct rtl8723bu_efuse));
2360                 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2361                         dev_info(&priv->udev->dev, "%02x: "
2362                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2363                                  raw[i], raw[i + 1], raw[i + 2],
2364                                  raw[i + 3], raw[i + 4], raw[i + 5],
2365                                  raw[i + 6], raw[i + 7]);
2366                 }
2367         }
2368
2369         return 0;
2370 }
2371
2372 #ifdef CONFIG_RTL8XXXU_UNTESTED
2373
2374 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2375 {
2376         struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
2377         int i;
2378
2379         if (efuse->rtl_id != cpu_to_le16(0x8129))
2380                 return -EINVAL;
2381
2382         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2383
2384         memcpy(priv->cck_tx_power_index_A,
2385                efuse->cck_tx_power_index_A,
2386                sizeof(priv->cck_tx_power_index_A));
2387         memcpy(priv->cck_tx_power_index_B,
2388                efuse->cck_tx_power_index_B,
2389                sizeof(priv->cck_tx_power_index_B));
2390
2391         memcpy(priv->ht40_1s_tx_power_index_A,
2392                efuse->ht40_1s_tx_power_index_A,
2393                sizeof(priv->ht40_1s_tx_power_index_A));
2394         memcpy(priv->ht40_1s_tx_power_index_B,
2395                efuse->ht40_1s_tx_power_index_B,
2396                sizeof(priv->ht40_1s_tx_power_index_B));
2397         memcpy(priv->ht40_2s_tx_power_index_diff,
2398                efuse->ht40_2s_tx_power_index_diff,
2399                sizeof(priv->ht40_2s_tx_power_index_diff));
2400
2401         memcpy(priv->ht20_tx_power_index_diff,
2402                efuse->ht20_tx_power_index_diff,
2403                sizeof(priv->ht20_tx_power_index_diff));
2404         memcpy(priv->ofdm_tx_power_index_diff,
2405                efuse->ofdm_tx_power_index_diff,
2406                sizeof(priv->ofdm_tx_power_index_diff));
2407
2408         memcpy(priv->ht40_max_power_offset,
2409                efuse->ht40_max_power_offset,
2410                sizeof(priv->ht40_max_power_offset));
2411         memcpy(priv->ht20_max_power_offset,
2412                efuse->ht20_max_power_offset,
2413                sizeof(priv->ht20_max_power_offset));
2414
2415         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2416                  efuse->vendor_name);
2417         dev_info(&priv->udev->dev, "Product: %.20s\n",
2418                  efuse->device_name);
2419
2420         if (efuse->rf_regulatory & 0x20) {
2421                 sprintf(priv->chip_name, "8188RU");
2422                 priv->hi_pa = 1;
2423         }
2424
2425         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2426                 unsigned char *raw = priv->efuse_wifi.raw;
2427
2428                 dev_info(&priv->udev->dev,
2429                          "%s: dumping efuse (0x%02zx bytes):\n",
2430                          __func__, sizeof(struct rtl8192cu_efuse));
2431                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2432                         dev_info(&priv->udev->dev, "%02x: "
2433                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2434                                  raw[i], raw[i + 1], raw[i + 2],
2435                                  raw[i + 3], raw[i + 4], raw[i + 5],
2436                                  raw[i + 6], raw[i + 7]);
2437                 }
2438         }
2439         return 0;
2440 }
2441
2442 #endif
2443
2444 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2445 {
2446         struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
2447         int i;
2448
2449         if (efuse->rtl_id != cpu_to_le16(0x8129))
2450                 return -EINVAL;
2451
2452         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
2453
2454         priv->has_xtalk = 1;
2455         priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
2456
2457         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2458         dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2459         dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
2460
2461         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2462                 unsigned char *raw = priv->efuse_wifi.raw;
2463
2464                 dev_info(&priv->udev->dev,
2465                          "%s: dumping efuse (0x%02zx bytes):\n",
2466                          __func__, sizeof(struct rtl8192eu_efuse));
2467                 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2468                         dev_info(&priv->udev->dev, "%02x: "
2469                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2470                                  raw[i], raw[i + 1], raw[i + 2],
2471                                  raw[i + 3], raw[i + 4], raw[i + 5],
2472                                  raw[i + 6], raw[i + 7]);
2473                 }
2474         }
2475         return 0;
2476 }
2477
2478 static int
2479 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2480 {
2481         int i;
2482         u8 val8;
2483         u32 val32;
2484
2485         /* Write Address */
2486         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2487         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2488         val8 &= 0xfc;
2489         val8 |= (offset >> 8) & 0x03;
2490         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2491
2492         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2493         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2494
2495         /* Poll for data read */
2496         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2497         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2498                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2499                 if (val32 & BIT(31))
2500                         break;
2501         }
2502
2503         if (i == RTL8XXXU_MAX_REG_POLL)
2504                 return -EIO;
2505
2506         udelay(50);
2507         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2508
2509         *data = val32 & 0xff;
2510         return 0;
2511 }
2512
2513 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2514 {
2515         struct device *dev = &priv->udev->dev;
2516         int i, ret = 0;
2517         u8 val8, word_mask, header, extheader;
2518         u16 val16, efuse_addr, offset;
2519         u32 val32;
2520
2521         val16 = rtl8xxxu_read16(priv, REG_9346CR);
2522         if (val16 & EEPROM_ENABLE)
2523                 priv->has_eeprom = 1;
2524         if (val16 & EEPROM_BOOT)
2525                 priv->boot_eeprom = 1;
2526
2527         if (priv->is_multi_func) {
2528                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2529                 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2530                 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2531         }
2532
2533         dev_dbg(dev, "Booting from %s\n",
2534                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2535
2536         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2537
2538         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2539         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2540         if (!(val16 & SYS_ISO_PWC_EV12V)) {
2541                 val16 |= SYS_ISO_PWC_EV12V;
2542                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2543         }
2544         /*  Reset: 0x0000[28], default valid */
2545         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2546         if (!(val16 & SYS_FUNC_ELDR)) {
2547                 val16 |= SYS_FUNC_ELDR;
2548                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2549         }
2550
2551         /*
2552          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2553          */
2554         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2555         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2556                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2557                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2558         }
2559
2560         /* Default value is 0xff */
2561         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
2562
2563         efuse_addr = 0;
2564         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2565                 u16 map_addr;
2566
2567                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2568                 if (ret || header == 0xff)
2569                         goto exit;
2570
2571                 if ((header & 0x1f) == 0x0f) {  /* extended header */
2572                         offset = (header & 0xe0) >> 5;
2573
2574                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2575                                                    &extheader);
2576                         if (ret)
2577                                 goto exit;
2578                         /* All words disabled */
2579                         if ((extheader & 0x0f) == 0x0f)
2580                                 continue;
2581
2582                         offset |= ((extheader & 0xf0) >> 1);
2583                         word_mask = extheader & 0x0f;
2584                 } else {
2585                         offset = (header >> 4) & 0x0f;
2586                         word_mask = header & 0x0f;
2587                 }
2588
2589                 /* Get word enable value from PG header */
2590
2591                 /* We have 8 bits to indicate validity */
2592                 map_addr = offset * 8;
2593                 if (map_addr >= EFUSE_MAP_LEN) {
2594                         dev_warn(dev, "%s: Illegal map_addr (%04x), "
2595                                  "efuse corrupt!\n",
2596                                  __func__, map_addr);
2597                         ret = -EINVAL;
2598                         goto exit;
2599                 }
2600                 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2601                         /* Check word enable condition in the section */
2602                         if (word_mask & BIT(i)) {
2603                                 map_addr += 2;
2604                                 continue;
2605                         }
2606
2607                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2608                         if (ret)
2609                                 goto exit;
2610                         priv->efuse_wifi.raw[map_addr++] = val8;
2611
2612                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2613                         if (ret)
2614                                 goto exit;
2615                         priv->efuse_wifi.raw[map_addr++] = val8;
2616                 }
2617         }
2618
2619 exit:
2620         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2621
2622         return ret;
2623 }
2624
2625 static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2626 {
2627         u8 val8;
2628         u16 sys_func;
2629
2630         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2631         val8 &= ~BIT(0);
2632         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2633         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2634         sys_func &= ~SYS_FUNC_CPU_ENABLE;
2635         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2636         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2637         val8 |= BIT(0);
2638         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2639         sys_func |= SYS_FUNC_CPU_ENABLE;
2640         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2641 }
2642
2643 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2644 {
2645         struct device *dev = &priv->udev->dev;
2646         int ret = 0, i;
2647         u32 val32;
2648
2649         /* Poll checksum report */
2650         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2651                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2652                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2653                         break;
2654         }
2655
2656         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2657                 dev_warn(dev, "Firmware checksum poll timed out\n");
2658                 ret = -EAGAIN;
2659                 goto exit;
2660         }
2661
2662         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2663         val32 |= MCU_FW_DL_READY;
2664         val32 &= ~MCU_WINT_INIT_READY;
2665         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2666
2667         /*
2668          * Reset the 8051 in order for the firmware to start running,
2669          * otherwise it won't come up on the 8192eu
2670          */
2671         rtl8xxxu_reset_8051(priv);
2672
2673         /* Wait for firmware to become ready */
2674         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2675                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2676                 if (val32 & MCU_WINT_INIT_READY)
2677                         break;
2678
2679                 udelay(100);
2680         }
2681
2682         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2683                 dev_warn(dev, "Firmware failed to start\n");
2684                 ret = -EAGAIN;
2685                 goto exit;
2686         }
2687
2688         /*
2689          * Init H2C command
2690          */
2691         if (priv->rtlchip == 0x8723b)
2692                 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2693 exit:
2694         return ret;
2695 }
2696
2697 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2698 {
2699         int pages, remainder, i, ret;
2700         u8 val8;
2701         u16 val16;
2702         u32 val32;
2703         u8 *fwptr;
2704
2705         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2706         val8 |= 4;
2707         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2708
2709         /* 8051 enable */
2710         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2711         val16 |= SYS_FUNC_CPU_ENABLE;
2712         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2713
2714         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2715         if (val8 & MCU_FW_RAM_SEL) {
2716                 pr_info("do the RAM reset\n");
2717                 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2718                 rtl8xxxu_reset_8051(priv);
2719         }
2720
2721         /* MCU firmware download enable */
2722         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2723         val8 |= MCU_FW_DL_ENABLE;
2724         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2725
2726         /* 8051 reset */
2727         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2728         val32 &= ~BIT(19);
2729         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2730
2731         /* Reset firmware download checksum */
2732         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2733         val8 |= MCU_FW_DL_CSUM_REPORT;
2734         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2735
2736         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2737         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2738
2739         fwptr = priv->fw_data->data;
2740
2741         for (i = 0; i < pages; i++) {
2742                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2743                 val8 |= i;
2744                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2745
2746                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2747                                       fwptr, RTL_FW_PAGE_SIZE);
2748                 if (ret != RTL_FW_PAGE_SIZE) {
2749                         ret = -EAGAIN;
2750                         goto fw_abort;
2751                 }
2752
2753                 fwptr += RTL_FW_PAGE_SIZE;
2754         }
2755
2756         if (remainder) {
2757                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2758                 val8 |= i;
2759                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2760                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2761                                       fwptr, remainder);
2762                 if (ret != remainder) {
2763                         ret = -EAGAIN;
2764                         goto fw_abort;
2765                 }
2766         }
2767
2768         ret = 0;
2769 fw_abort:
2770         /* MCU firmware download disable */
2771         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2772         val16 &= ~MCU_FW_DL_ENABLE;
2773         rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2774
2775         return ret;
2776 }
2777
2778 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2779 {
2780         struct device *dev = &priv->udev->dev;
2781         const struct firmware *fw;
2782         int ret = 0;
2783         u16 signature;
2784
2785         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2786         if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2787                 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2788                 ret = -EAGAIN;
2789                 goto exit;
2790         }
2791         if (!fw) {
2792                 dev_warn(dev, "Firmware data not available\n");
2793                 ret = -EINVAL;
2794                 goto exit;
2795         }
2796
2797         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2798         if (!priv->fw_data) {
2799                 ret = -ENOMEM;
2800                 goto exit;
2801         }
2802         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2803
2804         signature = le16_to_cpu(priv->fw_data->signature);
2805         switch (signature & 0xfff0) {
2806         case 0x92e0:
2807         case 0x92c0:
2808         case 0x88c0:
2809         case 0x5300:
2810         case 0x2300:
2811                 break;
2812         default:
2813                 ret = -EINVAL;
2814                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2815                          __func__, signature);
2816         }
2817
2818         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2819                  le16_to_cpu(priv->fw_data->major_version),
2820                  priv->fw_data->minor_version, signature);
2821
2822 exit:
2823         release_firmware(fw);
2824         return ret;
2825 }
2826
2827 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2828 {
2829         char *fw_name;
2830         int ret;
2831
2832         switch (priv->chip_cut) {
2833         case 0:
2834                 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2835                 break;
2836         case 1:
2837                 if (priv->enable_bluetooth)
2838                         fw_name = "rtlwifi/rtl8723aufw_B.bin";
2839                 else
2840                         fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2841
2842                 break;
2843         default:
2844                 return -EINVAL;
2845         }
2846
2847         ret = rtl8xxxu_load_firmware(priv, fw_name);
2848         return ret;
2849 }
2850
2851 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2852 {
2853         char *fw_name;
2854         int ret;
2855
2856         if (priv->enable_bluetooth)
2857                 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2858         else
2859                 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2860
2861         ret = rtl8xxxu_load_firmware(priv, fw_name);
2862         return ret;
2863 }
2864
2865 #ifdef CONFIG_RTL8XXXU_UNTESTED
2866
2867 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2868 {
2869         char *fw_name;
2870         int ret;
2871
2872         if (!priv->vendor_umc)
2873                 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2874         else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2875                 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2876         else
2877                 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2878
2879         ret = rtl8xxxu_load_firmware(priv, fw_name);
2880
2881         return ret;
2882 }
2883
2884 #endif
2885
2886 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2887 {
2888         char *fw_name;
2889         int ret;
2890
2891         fw_name = "rtlwifi/rtl8192eu_nic.bin";
2892
2893         ret = rtl8xxxu_load_firmware(priv, fw_name);
2894
2895         return ret;
2896 }
2897
2898 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2899 {
2900         u16 val16;
2901         int i = 100;
2902
2903         /* Inform 8051 to perform reset */
2904         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2905
2906         for (i = 100; i > 0; i--) {
2907                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2908
2909                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2910                         dev_dbg(&priv->udev->dev,
2911                                 "%s: Firmware self reset success!\n", __func__);
2912                         break;
2913                 }
2914                 udelay(50);
2915         }
2916
2917         if (!i) {
2918                 /* Force firmware reset */
2919                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2920                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2921                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2922         }
2923 }
2924
2925 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
2926 {
2927         u32 val32;
2928
2929         val32 = rtl8xxxu_read32(priv, 0x64);
2930         val32 &= ~(BIT(20) | BIT(24));
2931         rtl8xxxu_write32(priv, 0x64, val32);
2932
2933         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2934         val32 &= ~BIT(4);
2935         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2936
2937         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
2938         val32 |= BIT(3);
2939         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
2940
2941         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2942         val32 |= BIT(24);
2943         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2944
2945         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
2946         val32 &= ~BIT(23);
2947         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
2948
2949         val32 = rtl8xxxu_read32(priv, 0x0944);
2950         val32 |= (BIT(0) | BIT(1));
2951         rtl8xxxu_write32(priv, 0x0944, val32);
2952
2953         val32 = rtl8xxxu_read32(priv, 0x0930);
2954         val32 &= 0xffffff00;
2955         val32 |= 0x77;
2956         rtl8xxxu_write32(priv, 0x0930, val32);
2957
2958         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
2959         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
2960         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
2961 }
2962
2963 static int
2964 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2965 {
2966         int i, ret;
2967         u16 reg;
2968         u8 val;
2969
2970         for (i = 0; ; i++) {
2971                 reg = array[i].reg;
2972                 val = array[i].val;
2973
2974                 if (reg == 0xffff && val == 0xff)
2975                         break;
2976
2977                 ret = rtl8xxxu_write8(priv, reg, val);
2978                 if (ret != 1) {
2979                         dev_warn(&priv->udev->dev,
2980                                  "Failed to initialize MAC\n");
2981                         return -EAGAIN;
2982                 }
2983         }
2984
2985         if (priv->rtlchip != 0x8723b)
2986                 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2987
2988         return 0;
2989 }
2990
2991 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2992                                   struct rtl8xxxu_reg32val *array)
2993 {
2994         int i, ret;
2995         u16 reg;
2996         u32 val;
2997
2998         for (i = 0; ; i++) {
2999                 reg = array[i].reg;
3000                 val = array[i].val;
3001
3002                 if (reg == 0xffff && val == 0xffffffff)
3003                         break;
3004
3005                 ret = rtl8xxxu_write32(priv, reg, val);
3006                 if (ret != sizeof(val)) {
3007                         dev_warn(&priv->udev->dev,
3008                                  "Failed to initialize PHY\n");
3009                         return -EAGAIN;
3010                 }
3011                 udelay(1);
3012         }
3013
3014         return 0;
3015 }
3016
3017 /*
3018  * Most of this is black magic retrieved from the old rtl8723au driver
3019  */
3020 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3021 {
3022         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
3023         u16 val16;
3024         u32 val32;
3025
3026         /*
3027          * Todo: The vendor driver maintains a table of PHY register
3028          *       addresses, which is initialized here. Do we need this?
3029          */
3030
3031         if (priv->rtlchip == 0x8723b) {
3032                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3033                 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB |
3034                         SYS_FUNC_DIO_RF;
3035                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3036
3037                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3038         } else {
3039                 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3040                 udelay(2);
3041                 val8 |= AFE_PLL_320_ENABLE;
3042                 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3043                 udelay(2);
3044
3045                 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3046                 udelay(2);
3047
3048                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3049                 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3050                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3051         }
3052
3053         if (priv->rtlchip != 0x8723b) {
3054                 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3055                 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3056                 val32 &= ~AFE_XTAL_RF_GATE;
3057                 if (priv->has_bluetooth)
3058                         val32 &= ~AFE_XTAL_BT_GATE;
3059                 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3060         }
3061
3062         /* 6. 0x1f[7:0] = 0x07 */
3063         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3064         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3065
3066         if (priv->hi_pa)
3067                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3068         else if (priv->tx_paths == 2)
3069                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3070         else if (priv->rtlchip == 0x8723b) {
3071                 /*
3072                  * Why?
3073                  */
3074                 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3075                 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3076                 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
3077         } else
3078                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3079
3080
3081         if (priv->rtlchip == 0x8188c && priv->hi_pa &&
3082             priv->vendor_umc && priv->chip_cut == 1)
3083                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3084
3085         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3086                 /*
3087                  * For 1T2R boards, patch the registers.
3088                  *
3089                  * It looks like 8191/2 1T2R boards use path B for TX
3090                  */
3091                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3092                 val32 &= ~(BIT(0) | BIT(1));
3093                 val32 |= BIT(1);
3094                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3095
3096                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3097                 val32 &= ~0x300033;
3098                 val32 |= 0x200022;
3099                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3100
3101                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3102                 val32 &= 0xff000000;
3103                 val32 |= 0x45000000;
3104                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3105
3106                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3107                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3108                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3109                           OFDM_RF_PATH_TX_B);
3110                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3111
3112                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3113                 val32 &= ~(BIT(4) | BIT(5));
3114                 val32 |= BIT(4);
3115                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3116
3117                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3118                 val32 &= ~(BIT(27) | BIT(26));
3119                 val32 |= BIT(27);
3120                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3121
3122                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3123                 val32 &= ~(BIT(27) | BIT(26));
3124                 val32 |= BIT(27);
3125                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3126
3127                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3128                 val32 &= ~(BIT(27) | BIT(26));
3129                 val32 |= BIT(27);
3130                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3131
3132                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3133                 val32 &= ~(BIT(27) | BIT(26));
3134                 val32 |= BIT(27);
3135                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3136
3137                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3138                 val32 &= ~(BIT(27) | BIT(26));
3139                 val32 |= BIT(27);
3140                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3141         }
3142
3143         if (priv->rtlchip == 0x8723b)
3144                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3145         else if (priv->hi_pa)
3146                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3147         else
3148                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3149
3150         if (priv->has_xtalk) {
3151                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3152
3153                 val8 = priv->xtalk;
3154                 val32 &= 0xff000fff;
3155                 val32 |= ((val8 | (val8 << 6)) << 12);
3156
3157                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3158         }
3159
3160         if (priv->rtlchip != 0x8723bu) {
3161                 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3162                 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3163                 ldohci12 = 0x57;
3164                 lpldo = 1;
3165                 val32 = (lpldo << 24) | (ldohci12 << 16) |
3166                         (ldov12d << 8) | ldoa15;
3167
3168                 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3169         }
3170
3171         return 0;
3172 }
3173
3174 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3175                                  struct rtl8xxxu_rfregval *array,
3176                                  enum rtl8xxxu_rfpath path)
3177 {
3178         int i, ret;
3179         u8 reg;
3180         u32 val;
3181
3182         for (i = 0; ; i++) {
3183                 reg = array[i].reg;
3184                 val = array[i].val;
3185
3186                 if (reg == 0xff && val == 0xffffffff)
3187                         break;
3188
3189                 switch (reg) {
3190                 case 0xfe:
3191                         msleep(50);
3192                         continue;
3193                 case 0xfd:
3194                         mdelay(5);
3195                         continue;
3196                 case 0xfc:
3197                         mdelay(1);
3198                         continue;
3199                 case 0xfb:
3200                         udelay(50);
3201                         continue;
3202                 case 0xfa:
3203                         udelay(5);
3204                         continue;
3205                 case 0xf9:
3206                         udelay(1);
3207                         continue;
3208                 }
3209
3210                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3211                 if (ret) {
3212                         dev_warn(&priv->udev->dev,
3213                                  "Failed to initialize RF\n");
3214                         return -EAGAIN;
3215                 }
3216                 udelay(1);
3217         }
3218
3219         return 0;
3220 }
3221
3222 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3223                                 struct rtl8xxxu_rfregval *table,
3224                                 enum rtl8xxxu_rfpath path)
3225 {
3226         u32 val32;
3227         u16 val16, rfsi_rfenv;
3228         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3229
3230         switch (path) {
3231         case RF_A:
3232                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3233                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3234                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3235                 break;
3236         case RF_B:
3237                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3238                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3239                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3240                 break;
3241         default:
3242                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3243                         __func__, path + 'A');
3244                 return -EINVAL;
3245         }
3246         /* For path B, use XB */
3247         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3248         rfsi_rfenv &= FPGA0_RF_RFENV;
3249
3250         /*
3251          * These two we might be able to optimize into one
3252          */
3253         val32 = rtl8xxxu_read32(priv, reg_int_oe);
3254         val32 |= BIT(20);       /* 0x10 << 16 */
3255         rtl8xxxu_write32(priv, reg_int_oe, val32);
3256         udelay(1);
3257
3258         val32 = rtl8xxxu_read32(priv, reg_int_oe);
3259         val32 |= BIT(4);
3260         rtl8xxxu_write32(priv, reg_int_oe, val32);
3261         udelay(1);
3262
3263         /*
3264          * These two we might be able to optimize into one
3265          */
3266         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3267         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3268         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3269         udelay(1);
3270
3271         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3272         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3273         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3274         udelay(1);
3275
3276         rtl8xxxu_init_rf_regs(priv, table, path);
3277
3278         /* For path B, use XB */
3279         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3280         val16 &= ~FPGA0_RF_RFENV;
3281         val16 |= rfsi_rfenv;
3282         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3283
3284         return 0;
3285 }
3286
3287 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3288 {
3289         int ret = -EBUSY;
3290         int count = 0;
3291         u32 value;
3292
3293         value = LLT_OP_WRITE | address << 8 | data;
3294
3295         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3296
3297         do {
3298                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3299                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3300                         ret = 0;
3301                         break;
3302                 }
3303         } while (count++ < 20);
3304
3305         return ret;
3306 }
3307
3308 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3309 {
3310         int ret;
3311         int i;
3312
3313         for (i = 0; i < last_tx_page; i++) {
3314                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3315                 if (ret)
3316                         goto exit;
3317         }
3318
3319         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3320         if (ret)
3321                 goto exit;
3322
3323         /* Mark remaining pages as a ring buffer */
3324         for (i = last_tx_page + 1; i < 0xff; i++) {
3325                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3326                 if (ret)
3327                         goto exit;
3328         }
3329
3330         /*  Let last entry point to the start entry of ring buffer */
3331         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3332         if (ret)
3333                 goto exit;
3334
3335 exit:
3336         return ret;
3337 }
3338
3339 static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3340 {
3341         u32 val32;
3342         int ret = 0;
3343         int i;
3344
3345         val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3346         val32 |= AUTO_LLT_INIT_LLT;
3347         rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3348
3349         for (i = 500; i; i--) {
3350                 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3351                 if (!(val32 & AUTO_LLT_INIT_LLT))
3352                         break;
3353                 usleep_range(2, 4);
3354         }
3355
3356         if (!i) {
3357                 ret = -EBUSY;
3358                 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3359         }
3360
3361         return ret;
3362 }
3363
3364 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3365 {
3366         u16 val16, hi, lo;
3367         u16 hiq, mgq, bkq, beq, viq, voq;
3368         int hip, mgp, bkp, bep, vip, vop;
3369         int ret = 0;
3370
3371         switch (priv->ep_tx_count) {
3372         case 1:
3373                 if (priv->ep_tx_high_queue) {
3374                         hi = TRXDMA_QUEUE_HIGH;
3375                 } else if (priv->ep_tx_low_queue) {
3376                         hi = TRXDMA_QUEUE_LOW;
3377                 } else if (priv->ep_tx_normal_queue) {
3378                         hi = TRXDMA_QUEUE_NORMAL;
3379                 } else {
3380                         hi = 0;
3381                         ret = -EINVAL;
3382                 }
3383
3384                 hiq = hi;
3385                 mgq = hi;
3386                 bkq = hi;
3387                 beq = hi;
3388                 viq = hi;
3389                 voq = hi;
3390
3391                 hip = 0;
3392                 mgp = 0;
3393                 bkp = 0;
3394                 bep = 0;
3395                 vip = 0;
3396                 vop = 0;
3397                 break;
3398         case 2:
3399                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3400                         hi = TRXDMA_QUEUE_HIGH;
3401                         lo = TRXDMA_QUEUE_LOW;
3402                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3403                         hi = TRXDMA_QUEUE_NORMAL;
3404                         lo = TRXDMA_QUEUE_LOW;
3405                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3406                         hi = TRXDMA_QUEUE_HIGH;
3407                         lo = TRXDMA_QUEUE_NORMAL;
3408                 } else {
3409                         ret = -EINVAL;
3410                         hi = 0;
3411                         lo = 0;
3412                 }
3413
3414                 hiq = hi;
3415                 mgq = hi;
3416                 bkq = lo;
3417                 beq = lo;
3418                 viq = hi;
3419                 voq = hi;
3420
3421                 hip = 0;
3422                 mgp = 0;
3423                 bkp = 1;
3424                 bep = 1;
3425                 vip = 0;
3426                 vop = 0;
3427                 break;
3428         case 3:
3429                 beq = TRXDMA_QUEUE_LOW;
3430                 bkq = TRXDMA_QUEUE_LOW;
3431                 viq = TRXDMA_QUEUE_NORMAL;
3432                 voq = TRXDMA_QUEUE_HIGH;
3433                 mgq = TRXDMA_QUEUE_HIGH;
3434                 hiq = TRXDMA_QUEUE_HIGH;
3435
3436                 hip = hiq ^ 3;
3437                 mgp = mgq ^ 3;
3438                 bkp = bkq ^ 3;
3439                 bep = beq ^ 3;
3440                 vip = viq ^ 3;
3441                 vop = viq ^ 3;
3442                 break;
3443         default:
3444                 ret = -EINVAL;
3445         }
3446
3447         /*
3448          * None of the vendor drivers are configuring the beacon
3449          * queue here .... why?
3450          */
3451         if (!ret) {
3452                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3453                 val16 &= 0x7;
3454                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3455                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3456                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3457                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3458                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3459                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3460                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3461
3462                 priv->pipe_out[TXDESC_QUEUE_VO] =
3463                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3464                 priv->pipe_out[TXDESC_QUEUE_VI] =
3465                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3466                 priv->pipe_out[TXDESC_QUEUE_BE] =
3467                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3468                 priv->pipe_out[TXDESC_QUEUE_BK] =
3469                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3470                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3471                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3472                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3473                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3474                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3475                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3476                 priv->pipe_out[TXDESC_QUEUE_CMD] =
3477                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3478         }
3479
3480         return ret;
3481 }
3482
3483 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3484                                        bool iqk_ok, int result[][8],
3485                                        int candidate, bool tx_only)
3486 {
3487         u32 oldval, x, tx0_a, reg;
3488         int y, tx0_c;
3489         u32 val32;
3490
3491         if (!iqk_ok)
3492                 return;
3493
3494         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3495         oldval = val32 >> 22;
3496
3497         x = result[candidate][0];
3498         if ((x & 0x00000200) != 0)
3499                 x = x | 0xfffffc00;
3500         tx0_a = (x * oldval) >> 8;
3501
3502         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3503         val32 &= ~0x3ff;
3504         val32 |= tx0_a;
3505         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3506
3507         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3508         val32 &= ~BIT(31);
3509         if ((x * oldval >> 7) & 0x1)
3510                 val32 |= BIT(31);
3511         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3512
3513         y = result[candidate][1];
3514         if ((y & 0x00000200) != 0)
3515                 y = y | 0xfffffc00;
3516         tx0_c = (y * oldval) >> 8;
3517
3518         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3519         val32 &= ~0xf0000000;
3520         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3521         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3522
3523         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3524         val32 &= ~0x003f0000;
3525         val32 |= ((tx0_c & 0x3f) << 16);
3526         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3527
3528         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3529         val32 &= ~BIT(29);
3530         if ((y * oldval >> 7) & 0x1)
3531                 val32 |= BIT(29);
3532         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3533
3534         if (tx_only) {
3535                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3536                 return;
3537         }
3538
3539         reg = result[candidate][2];
3540
3541         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3542         val32 &= ~0x3ff;
3543         val32 |= (reg & 0x3ff);
3544         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3545
3546         reg = result[candidate][3] & 0x3F;
3547
3548         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3549         val32 &= ~0xfc00;
3550         val32 |= ((reg << 10) & 0xfc00);
3551         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3552
3553         reg = (result[candidate][3] >> 6) & 0xF;
3554
3555         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3556         val32 &= ~0xf0000000;
3557         val32 |= (reg << 28);
3558         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3559 }
3560
3561 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3562                                        bool iqk_ok, int result[][8],
3563                                        int candidate, bool tx_only)
3564 {
3565         u32 oldval, x, tx1_a, reg;
3566         int y, tx1_c;
3567         u32 val32;
3568
3569         if (!iqk_ok)
3570                 return;
3571
3572         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3573         oldval = val32 >> 22;
3574
3575         x = result[candidate][4];
3576         if ((x & 0x00000200) != 0)
3577                 x = x | 0xfffffc00;
3578         tx1_a = (x * oldval) >> 8;
3579
3580         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3581         val32 &= ~0x3ff;
3582         val32 |= tx1_a;
3583         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3584
3585         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3586         val32 &= ~BIT(27);
3587         if ((x * oldval >> 7) & 0x1)
3588                 val32 |= BIT(27);
3589         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3590
3591         y = result[candidate][5];
3592         if ((y & 0x00000200) != 0)
3593                 y = y | 0xfffffc00;
3594         tx1_c = (y * oldval) >> 8;
3595
3596         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3597         val32 &= ~0xf0000000;
3598         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3599         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3600
3601         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3602         val32 &= ~0x003f0000;
3603         val32 |= ((tx1_c & 0x3f) << 16);
3604         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3605
3606         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3607         val32 &= ~BIT(25);
3608         if ((y * oldval >> 7) & 0x1)
3609                 val32 |= BIT(25);
3610         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3611
3612         if (tx_only) {
3613                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3614                 return;
3615         }
3616
3617         reg = result[candidate][6];
3618
3619         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3620         val32 &= ~0x3ff;
3621         val32 |= (reg & 0x3ff);
3622         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3623
3624         reg = result[candidate][7] & 0x3f;
3625
3626         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3627         val32 &= ~0xfc00;
3628         val32 |= ((reg << 10) & 0xfc00);
3629         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3630
3631         reg = (result[candidate][7] >> 6) & 0xf;
3632
3633         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3634         val32 &= ~0x0000f000;
3635         val32 |= (reg << 12);
3636         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3637 }
3638
3639 #define MAX_TOLERANCE           5
3640
3641 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3642                                         int result[][8], int c1, int c2)
3643 {
3644         u32 i, j, diff, simubitmap, bound = 0;
3645         int candidate[2] = {-1, -1};    /* for path A and path B */
3646         bool retval = true;
3647
3648         if (priv->tx_paths > 1)
3649                 bound = 8;
3650         else
3651                 bound = 4;
3652
3653         simubitmap = 0;
3654
3655         for (i = 0; i < bound; i++) {
3656                 diff = (result[c1][i] > result[c2][i]) ?
3657                         (result[c1][i] - result[c2][i]) :
3658                         (result[c2][i] - result[c1][i]);
3659                 if (diff > MAX_TOLERANCE) {
3660                         if ((i == 2 || i == 6) && !simubitmap) {
3661                                 if (result[c1][i] + result[c1][i + 1] == 0)
3662                                         candidate[(i / 4)] = c2;
3663                                 else if (result[c2][i] + result[c2][i + 1] == 0)
3664                                         candidate[(i / 4)] = c1;
3665                                 else
3666                                         simubitmap = simubitmap | (1 << i);
3667                         } else {
3668                                 simubitmap = simubitmap | (1 << i);
3669                         }
3670                 }
3671         }
3672
3673         if (simubitmap == 0) {
3674                 for (i = 0; i < (bound / 4); i++) {
3675                         if (candidate[i] >= 0) {
3676                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3677                                         result[3][j] = result[candidate[i]][j];
3678                                 retval = false;
3679                         }
3680                 }
3681                 return retval;
3682         } else if (!(simubitmap & 0x0f)) {
3683                 /* path A OK */
3684                 for (i = 0; i < 4; i++)
3685                         result[3][i] = result[c1][i];
3686         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3687                 /* path B OK */
3688                 for (i = 4; i < 8; i++)
3689                         result[3][i] = result[c1][i];
3690         }
3691
3692         return false;
3693 }
3694
3695 static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3696                                          int result[][8], int c1, int c2)
3697 {
3698         u32 i, j, diff, simubitmap, bound = 0;
3699         int candidate[2] = {-1, -1};    /* for path A and path B */
3700         int tmp1, tmp2;
3701         bool retval = true;
3702
3703         if (priv->tx_paths > 1)
3704                 bound = 8;
3705         else
3706                 bound = 4;
3707
3708         simubitmap = 0;
3709
3710         for (i = 0; i < bound; i++) {
3711                 if (i & 1) {
3712                         if ((result[c1][i] & 0x00000200))
3713                                 tmp1 = result[c1][i] | 0xfffffc00;
3714                         else
3715                                 tmp1 = result[c1][i];
3716
3717                         if ((result[c2][i]& 0x00000200))
3718                                 tmp2 = result[c2][i] | 0xfffffc00;
3719                         else
3720                                 tmp2 = result[c2][i];
3721                 } else {
3722                         tmp1 = result[c1][i];
3723                         tmp2 = result[c2][i];
3724                 }
3725
3726                 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3727
3728                 if (diff > MAX_TOLERANCE) {
3729                         if ((i == 2 || i == 6) && !simubitmap) {
3730                                 if (result[c1][i] + result[c1][i + 1] == 0)
3731                                         candidate[(i / 4)] = c2;
3732                                 else if (result[c2][i] + result[c2][i + 1] == 0)
3733                                         candidate[(i / 4)] = c1;
3734                                 else
3735                                         simubitmap = simubitmap | (1 << i);
3736                         } else {
3737                                 simubitmap = simubitmap | (1 << i);
3738                         }
3739                 }
3740         }
3741
3742         if (simubitmap == 0) {
3743                 for (i = 0; i < (bound / 4); i++) {
3744                         if (candidate[i] >= 0) {
3745                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3746                                         result[3][j] = result[candidate[i]][j];
3747                                 retval = false;
3748                         }
3749                 }
3750                 return retval;
3751         } else {
3752                 if (!(simubitmap & 0x03)) {
3753                         /* path A TX OK */
3754                         for (i = 0; i < 2; i++)
3755                                 result[3][i] = result[c1][i];
3756                 }
3757
3758                 if (!(simubitmap & 0x0c)) {
3759                         /* path A RX OK */
3760                         for (i = 2; i < 4; i++)
3761                                 result[3][i] = result[c1][i];
3762                 }
3763
3764                 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3765                         /* path B RX OK */
3766                         for (i = 4; i < 6; i++)
3767                                 result[3][i] = result[c1][i];
3768                 }
3769
3770                 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3771                         /* path B RX OK */
3772                         for (i = 6; i < 8; i++)
3773                                 result[3][i] = result[c1][i];
3774                 }
3775         }
3776
3777         return false;
3778 }
3779
3780 static void
3781 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3782 {
3783         int i;
3784
3785         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3786                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3787
3788         backup[i] = rtl8xxxu_read32(priv, reg[i]);
3789 }
3790
3791 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3792                                       const u32 *reg, u32 *backup)
3793 {
3794         int i;
3795
3796         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3797                 rtl8xxxu_write8(priv, reg[i], backup[i]);
3798
3799         rtl8xxxu_write32(priv, reg[i], backup[i]);
3800 }
3801
3802 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3803                                u32 *backup, int count)
3804 {
3805         int i;
3806
3807         for (i = 0; i < count; i++)
3808                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3809 }
3810
3811 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3812                                   u32 *backup, int count)
3813 {
3814         int i;
3815
3816         for (i = 0; i < count; i++)
3817                 rtl8xxxu_write32(priv, regs[i], backup[i]);
3818 }
3819
3820
3821 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3822                                   bool path_a_on)
3823 {
3824         u32 path_on;
3825         int i;
3826
3827         if (priv->tx_paths == 1) {
3828                 path_on = priv->fops->adda_1t_path_on;
3829                 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3830         } else {
3831                 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3832                         priv->fops->adda_2t_path_on_b;
3833
3834                 rtl8xxxu_write32(priv, regs[0], path_on);
3835         }
3836
3837         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3838                 rtl8xxxu_write32(priv, regs[i], path_on);
3839 }
3840
3841 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3842                                      const u32 *regs, u32 *backup)
3843 {
3844         int i = 0;
3845
3846         rtl8xxxu_write8(priv, regs[i], 0x3f);
3847
3848         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3849                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3850
3851         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3852 }
3853
3854 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3855 {
3856         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3857         int result = 0;
3858
3859         /* path-A IQK setting */
3860         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3861         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3862         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3863
3864         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3865                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3866                 0x28160502;
3867         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3868
3869         /* path-B IQK setting */
3870         if (priv->rf_paths > 1) {
3871                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3872                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3873                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3874                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3875         }
3876
3877         /* LO calibration setting */
3878         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3879
3880         /* One shot, path A LOK & IQK */
3881         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3882         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3883
3884         mdelay(1);
3885
3886         /* Check failed */
3887         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3888         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3889         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3890         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3891
3892         if (!(reg_eac & BIT(28)) &&
3893             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3894             ((reg_e9c & 0x03ff0000) != 0x00420000))
3895                 result |= 0x01;
3896         else    /* If TX not OK, ignore RX */
3897                 goto out;
3898
3899         /* If TX is OK, check whether RX is OK */
3900         if (!(reg_eac & BIT(27)) &&
3901             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3902             ((reg_eac & 0x03ff0000) != 0x00360000))
3903                 result |= 0x02;
3904         else
3905                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3906                          __func__);
3907 out:
3908         return result;
3909 }
3910
3911 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3912 {
3913         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3914         int result = 0;
3915
3916         /* One shot, path B LOK & IQK */
3917         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3918         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3919
3920         mdelay(1);
3921
3922         /* Check failed */
3923         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3924         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3925         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3926         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3927         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3928
3929         if (!(reg_eac & BIT(31)) &&
3930             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3931             ((reg_ebc & 0x03ff0000) != 0x00420000))
3932                 result |= 0x01;
3933         else
3934                 goto out;
3935
3936         if (!(reg_eac & BIT(30)) &&
3937             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3938             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3939                 result |= 0x02;
3940         else
3941                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3942                          __func__);
3943 out:
3944         return result;
3945 }
3946
3947 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
3948 {
3949         u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
3950         int result = 0;
3951
3952         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
3953
3954         /*
3955          * Leave IQK mode
3956          */
3957         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3958         val32 &= 0x000000ff;
3959         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3960
3961         /*
3962          * Enable path A PA in TX IQK mode
3963          */
3964         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
3965         val32 |= 0x80000;
3966         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
3967         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
3968         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
3969         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
3970
3971         /*
3972          * Tx IQK setting
3973          */
3974         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3975         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3976
3977         /* path-A IQK setting */
3978         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
3979         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
3980         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
3981         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
3982
3983         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
3984         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
3985         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
3986         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
3987
3988         /* LO calibration setting */
3989         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
3990
3991         /*
3992          * Enter IQK mode
3993          */
3994         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
3995         val32 &= 0x000000ff;
3996         val32 |= 0x80800000;
3997         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
3998
3999         /*
4000          * The vendor driver indicates the USB module is always using
4001          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4002          */
4003         if (priv->rf_paths > 1)
4004                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4005         else
4006                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4007
4008         /*
4009          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4010          * No trace of this in the 8192eu or 8188eu vendor drivers.
4011          */
4012         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4013
4014         /* One shot, path A LOK & IQK */
4015         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4016         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4017
4018         mdelay(1);
4019
4020         /* Restore Ant Path */
4021         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4022 #ifdef RTL8723BU_BT
4023         /* GNT_BT = 1 */
4024         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4025 #endif
4026
4027         /*
4028          * Leave IQK mode
4029          */
4030         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4031         val32 &= 0x000000ff;
4032         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4033
4034         /* Check failed */
4035         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4036         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4037         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4038
4039         val32 = (reg_e9c >> 16) & 0x3ff;
4040         if (val32 & 0x200)
4041                 val32 = 0x400 - val32;
4042
4043         if (!(reg_eac & BIT(28)) &&
4044             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4045             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4046             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
4047             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
4048             val32 < 0xf)
4049                 result |= 0x01;
4050         else    /* If TX not OK, ignore RX */
4051                 goto out;
4052
4053 out:
4054         return result;
4055 }
4056
4057 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4058 {
4059         u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4060         int result = 0;
4061
4062         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4063
4064         /*
4065          * Leave IQK mode
4066          */
4067         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4068         val32 &= 0x000000ff;
4069         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4070
4071         /*
4072          * Enable path A PA in TX IQK mode
4073          */
4074         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4075         val32 |= 0x80000;
4076         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4077         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4078         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4079         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4080
4081         /*
4082          * Tx IQK setting
4083          */
4084         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4085         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4086
4087         /* path-A IQK setting */
4088         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4089         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4090         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4091         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4092
4093         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4094         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4095         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4096         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4097
4098         /* LO calibration setting */
4099         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4100
4101         /*
4102          * Enter IQK mode
4103          */
4104         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4105         val32 &= 0x000000ff;
4106         val32 |= 0x80800000;
4107         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4108
4109         /*
4110          * The vendor driver indicates the USB module is always using
4111          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4112          */
4113         if (priv->rf_paths > 1)
4114                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4115         else
4116                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4117
4118         /*
4119          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4120          * No trace of this in the 8192eu or 8188eu vendor drivers.
4121          */
4122         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4123
4124         /* One shot, path A LOK & IQK */
4125         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4126         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4127
4128         mdelay(1);
4129
4130         /* Restore Ant Path */
4131         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4132 #ifdef RTL8723BU_BT
4133         /* GNT_BT = 1 */
4134         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4135 #endif
4136
4137         /*
4138          * Leave IQK mode
4139          */
4140         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4141         val32 &= 0x000000ff;
4142         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4143
4144         /* Check failed */
4145         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4146         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4147         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4148
4149         val32 = (reg_e9c >> 16) & 0x3ff;
4150         if (val32 & 0x200)
4151                 val32 = 0x400 - val32;
4152
4153         if (!(reg_eac & BIT(28)) &&
4154             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4155             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4156             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
4157             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
4158             val32 < 0xf)
4159                 result |= 0x01;
4160         else    /* If TX not OK, ignore RX */
4161                 goto out;
4162
4163         val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4164                 ((reg_e9c & 0x3ff0000) >> 16);
4165         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4166
4167         /*
4168          * Modify RX IQK mode
4169          */
4170         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4171         val32 &= 0x000000ff;
4172         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4173         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4174         val32 |= 0x80000;
4175         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4176         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4177         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4178         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4179
4180         /*
4181          * PA, PAD setting
4182          */
4183         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4184         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4185
4186         /*
4187          * RX IQK setting
4188          */
4189         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4190
4191         /* path-A IQK setting */
4192         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4193         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4194         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4195         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4196
4197         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4198         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4199         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4200         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4201
4202         /* LO calibration setting */
4203         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4204
4205         /*
4206          * Enter IQK mode
4207          */
4208         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4209         val32 &= 0x000000ff;
4210         val32 |= 0x80800000;
4211         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4212
4213         if (priv->rf_paths > 1)
4214                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4215         else
4216                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4217
4218         /*
4219          * Disable BT
4220          */
4221         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4222
4223         /* One shot, path A LOK & IQK */
4224         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4225         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4226
4227         mdelay(1);
4228
4229         /* Restore Ant Path */
4230         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4231 #ifdef RTL8723BU_BT
4232         /* GNT_BT = 1 */
4233         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4234 #endif
4235
4236         /*
4237          * Leave IQK mode
4238          */
4239         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4240         val32 &= 0x000000ff;
4241         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4242
4243         /* Check failed */
4244         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4245         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4246
4247         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4248
4249         val32 = (reg_eac >> 16) & 0x3ff;
4250         if (val32 & 0x200)
4251                 val32 = 0x400 - val32;
4252
4253         if (!(reg_eac & BIT(27)) &&
4254             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4255             ((reg_eac & 0x03ff0000) != 0x00360000) &&
4256             ((reg_ea4 & 0x03ff0000)  < 0x01100000) &&
4257             ((reg_ea4 & 0x03ff0000)  > 0x00f00000) &&
4258             val32 < 0xf)
4259                 result |= 0x02;
4260         else    /* If TX not OK, ignore RX */
4261                 goto out;
4262 out:
4263         return result;
4264 }
4265
4266 #ifdef RTL8723BU_PATH_B
4267 static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4268 {
4269         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4270         int result = 0;
4271
4272         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4273
4274         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4275         val32 &= 0x000000ff;
4276         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4277
4278         /* One shot, path B LOK & IQK */
4279         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4280         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4281
4282         mdelay(1);
4283
4284         /* Check failed */
4285         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4286         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4287         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4288         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4289         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4290
4291         if (!(reg_eac & BIT(31)) &&
4292             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4293             ((reg_ebc & 0x03ff0000) != 0x00420000))
4294                 result |= 0x01;
4295         else
4296                 goto out;
4297
4298         if (!(reg_eac & BIT(30)) &&
4299             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4300             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4301                 result |= 0x02;
4302         else
4303                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4304                          __func__);
4305 out:
4306         return result;
4307 }
4308 #endif
4309
4310 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4311                                      int result[][8], int t)
4312 {
4313         struct device *dev = &priv->udev->dev;
4314         u32 i, val32;
4315         int path_a_ok, path_b_ok;
4316         int retry = 2;
4317         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4318                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4319                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4320                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4321                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4322                 REG_TX_TO_TX, REG_RX_CCK,
4323                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4324                 REG_RX_TO_RX, REG_STANDBY,
4325                 REG_SLEEP, REG_PMPD_ANAEN
4326         };
4327         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4328                 REG_TXPAUSE, REG_BEACON_CTRL,
4329                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4330         };
4331         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4332                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4333                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4334                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4335                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4336         };
4337
4338         /*
4339          * Note: IQ calibration must be performed after loading
4340          *       PHY_REG.txt , and radio_a, radio_b.txt
4341          */
4342
4343         if (t == 0) {
4344                 /* Save ADDA parameters, turn Path A ADDA on */
4345                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4346                                    RTL8XXXU_ADDA_REGS);
4347                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4348                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4349                                    priv->bb_backup, RTL8XXXU_BB_REGS);
4350         }
4351
4352         rtl8xxxu_path_adda_on(priv, adda_regs, true);
4353
4354         if (t == 0) {
4355                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4356                 if (val32 & FPGA0_HSSI_PARM1_PI)
4357                         priv->pi_enabled = 1;
4358         }
4359
4360         if (!priv->pi_enabled) {
4361                 /* Switch BB to PI mode to do IQ Calibration. */
4362                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4363                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4364         }
4365
4366         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4367         val32 &= ~FPGA_RF_MODE_CCK;
4368         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4369
4370         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4371         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4372         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4373
4374         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4375         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4376         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4377
4378         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4379         val32 &= ~BIT(10);
4380         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4381         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4382         val32 &= ~BIT(10);
4383         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4384
4385         if (priv->tx_paths > 1) {
4386                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4387                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4388         }
4389
4390         /* MAC settings */
4391         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4392
4393         /* Page B init */
4394         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4395
4396         if (priv->tx_paths > 1)
4397                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4398
4399         /* IQ calibration setting */
4400         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4401         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4402         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4403
4404         for (i = 0; i < retry; i++) {
4405                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4406                 if (path_a_ok == 0x03) {
4407                         val32 = rtl8xxxu_read32(priv,
4408                                                 REG_TX_POWER_BEFORE_IQK_A);
4409                         result[t][0] = (val32 >> 16) & 0x3ff;
4410                         val32 = rtl8xxxu_read32(priv,
4411                                                 REG_TX_POWER_AFTER_IQK_A);
4412                         result[t][1] = (val32 >> 16) & 0x3ff;
4413                         val32 = rtl8xxxu_read32(priv,
4414                                                 REG_RX_POWER_BEFORE_IQK_A_2);
4415                         result[t][2] = (val32 >> 16) & 0x3ff;
4416                         val32 = rtl8xxxu_read32(priv,
4417                                                 REG_RX_POWER_AFTER_IQK_A_2);
4418                         result[t][3] = (val32 >> 16) & 0x3ff;
4419                         break;
4420                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4421                         /* TX IQK OK */
4422                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4423                                 __func__);
4424
4425                         val32 = rtl8xxxu_read32(priv,
4426                                                 REG_TX_POWER_BEFORE_IQK_A);
4427                         result[t][0] = (val32 >> 16) & 0x3ff;
4428                         val32 = rtl8xxxu_read32(priv,
4429                                                 REG_TX_POWER_AFTER_IQK_A);
4430                         result[t][1] = (val32 >> 16) & 0x3ff;
4431                 }
4432         }
4433
4434         if (!path_a_ok)
4435                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4436
4437         if (priv->tx_paths > 1) {
4438                 /*
4439                  * Path A into standby
4440                  */
4441                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4442                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4443                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4444
4445                 /* Turn Path B ADDA on */
4446                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4447
4448                 for (i = 0; i < retry; i++) {
4449                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
4450                         if (path_b_ok == 0x03) {
4451                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4452                                 result[t][4] = (val32 >> 16) & 0x3ff;
4453                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4454                                 result[t][5] = (val32 >> 16) & 0x3ff;
4455                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4456                                 result[t][6] = (val32 >> 16) & 0x3ff;
4457                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4458                                 result[t][7] = (val32 >> 16) & 0x3ff;
4459                                 break;
4460                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
4461                                 /* TX IQK OK */
4462                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4463                                 result[t][4] = (val32 >> 16) & 0x3ff;
4464                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4465                                 result[t][5] = (val32 >> 16) & 0x3ff;
4466                         }
4467                 }
4468
4469                 if (!path_b_ok)
4470                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4471         }
4472
4473         /* Back to BB mode, load original value */
4474         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4475
4476         if (t) {
4477                 if (!priv->pi_enabled) {
4478                         /*
4479                          * Switch back BB to SI mode after finishing
4480                          * IQ Calibration
4481                          */
4482                         val32 = 0x01000000;
4483                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4484                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4485                 }
4486
4487                 /* Reload ADDA power saving parameters */
4488                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4489                                       RTL8XXXU_ADDA_REGS);
4490
4491                 /* Reload MAC parameters */
4492                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4493
4494                 /* Reload BB parameters */
4495                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4496                                       priv->bb_backup, RTL8XXXU_BB_REGS);
4497
4498                 /* Restore RX initial gain */
4499                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4500
4501                 if (priv->tx_paths > 1) {
4502                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4503                                          0x00032ed3);
4504                 }
4505
4506                 /* Load 0xe30 IQC default value */
4507                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4508                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4509         }
4510 }
4511
4512 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4513                                       int result[][8], int t)
4514 {
4515         struct device *dev = &priv->udev->dev;
4516         u32 i, val32;
4517         int path_a_ok /*, path_b_ok */;
4518         int retry = 2;
4519         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4520                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4521                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4522                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4523                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4524                 REG_TX_TO_TX, REG_RX_CCK,
4525                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4526                 REG_RX_TO_RX, REG_STANDBY,
4527                 REG_SLEEP, REG_PMPD_ANAEN
4528         };
4529         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4530                 REG_TXPAUSE, REG_BEACON_CTRL,
4531                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4532         };
4533         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4534                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4535                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4536                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4537                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4538         };
4539         u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4540         u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4541
4542         /*
4543          * Note: IQ calibration must be performed after loading
4544          *       PHY_REG.txt , and radio_a, radio_b.txt
4545          */
4546
4547         if (t == 0) {
4548                 /* Save ADDA parameters, turn Path A ADDA on */
4549                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4550                                    RTL8XXXU_ADDA_REGS);
4551                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4552                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4553                                    priv->bb_backup, RTL8XXXU_BB_REGS);
4554         }
4555
4556         rtl8xxxu_path_adda_on(priv, adda_regs, true);
4557
4558         /* MAC settings */
4559         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4560
4561         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4562         val32 |= 0x0f000000;
4563         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4564
4565         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4566         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4567         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4568
4569 #ifdef RTL8723BU_PATH_B
4570         /* Set RF mode to standby Path B */
4571         if (priv->tx_paths > 1)
4572                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4573 #endif
4574
4575 #if 0
4576         /* Page B init */
4577         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4578
4579         if (priv->tx_paths > 1)
4580                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4581 #endif
4582
4583         /*
4584          * RX IQ calibration setting for 8723B D cut large current issue
4585          * when leaving IPS
4586          */
4587         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4588         val32 &= 0x000000ff;
4589         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4590
4591         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4592         val32 |= 0x80000;
4593         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4594
4595         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4596         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4597         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4598
4599         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4600         val32 |= 0x20;
4601         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4602
4603         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4604
4605         for (i = 0; i < retry; i++) {
4606                 path_a_ok = rtl8723bu_iqk_path_a(priv);
4607                 if (path_a_ok == 0x01) {
4608                         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4609                         val32 &= 0x000000ff;
4610                         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4611
4612 #if 0 /* Only needed in restore case, we may need this when going to suspend */
4613                         priv->RFCalibrateInfo.TxLOK[RF_A] =
4614                                 rtl8xxxu_read_rfreg(priv, RF_A,
4615                                                     RF6052_REG_TXM_IDAC);
4616 #endif
4617
4618                         val32 = rtl8xxxu_read32(priv,
4619                                                 REG_TX_POWER_BEFORE_IQK_A);
4620                         result[t][0] = (val32 >> 16) & 0x3ff;
4621                         val32 = rtl8xxxu_read32(priv,
4622                                                 REG_TX_POWER_AFTER_IQK_A);
4623                         result[t][1] = (val32 >> 16) & 0x3ff;
4624
4625                         break;
4626                 }
4627         }
4628
4629         if (!path_a_ok)
4630                 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4631
4632         for (i = 0; i < retry; i++) {
4633                 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4634                 if (path_a_ok == 0x03) {
4635                         val32 = rtl8xxxu_read32(priv,
4636                                                 REG_RX_POWER_BEFORE_IQK_A_2);
4637                         result[t][2] = (val32 >> 16) & 0x3ff;
4638                         val32 = rtl8xxxu_read32(priv,
4639                                                 REG_RX_POWER_AFTER_IQK_A_2);
4640                         result[t][3] = (val32 >> 16) & 0x3ff;
4641
4642                         break;
4643                 }
4644         }
4645
4646         if (!path_a_ok)
4647                 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4648
4649         if (priv->tx_paths > 1) {
4650 #if 1
4651                 dev_warn(dev, "%s: Path B not supported\n", __func__);
4652 #else
4653
4654                 /*
4655                  * Path A into standby
4656                  */
4657                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4658                 val32 &= 0x000000ff;
4659                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4660                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4661
4662                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4663                 val32 &= 0x000000ff;
4664                 val32 |= 0x80800000;
4665                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4666
4667                 /* Turn Path B ADDA on */
4668                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4669
4670                 for (i = 0; i < retry; i++) {
4671                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
4672                         if (path_b_ok == 0x03) {
4673                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4674                                 result[t][4] = (val32 >> 16) & 0x3ff;
4675                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4676                                 result[t][5] = (val32 >> 16) & 0x3ff;
4677                                 break;
4678                         }
4679                 }
4680
4681                 if (!path_b_ok)
4682                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4683
4684                 for (i = 0; i < retry; i++) {
4685                         path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4686                         if (path_a_ok == 0x03) {
4687                                 val32 = rtl8xxxu_read32(priv,
4688                                                         REG_RX_POWER_BEFORE_IQK_B_2);
4689                                 result[t][6] = (val32 >> 16) & 0x3ff;
4690                                 val32 = rtl8xxxu_read32(priv,
4691                                                         REG_RX_POWER_AFTER_IQK_B_2);
4692                                 result[t][7] = (val32 >> 16) & 0x3ff;
4693                                 break;
4694                         }
4695                 }
4696
4697                 if (!path_b_ok)
4698                         dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4699 #endif
4700         }
4701
4702         /* Back to BB mode, load original value */
4703         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4704         val32 &= 0x000000ff;
4705         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4706
4707         if (t) {
4708                 /* Reload ADDA power saving parameters */
4709                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4710                                       RTL8XXXU_ADDA_REGS);
4711
4712                 /* Reload MAC parameters */
4713                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4714
4715                 /* Reload BB parameters */
4716                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4717                                       priv->bb_backup, RTL8XXXU_BB_REGS);
4718
4719                 /* Restore RX initial gain */
4720                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4721                 val32 &= 0xffffff00;
4722                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4723                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4724
4725                 if (priv->tx_paths > 1) {
4726                         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4727                         val32 &= 0xffffff00;
4728                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4729                                          val32 | 0x50);
4730                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4731                                          val32 | xb_agc);
4732                 }
4733
4734                 /* Load 0xe30 IQC default value */
4735                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4736                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4737         }
4738 }
4739
4740 static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4741 {
4742         struct h2c_cmd h2c;
4743
4744         if (priv->fops->mbox_ext_width < 4)
4745                 return;
4746
4747         memset(&h2c, 0, sizeof(struct h2c_cmd));
4748         h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4749         h2c.bt_wlan_calibration.data = start;
4750
4751         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4752 }
4753
4754 static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4755 {
4756         struct device *dev = &priv->udev->dev;
4757         int result[4][8];       /* last is final result */
4758         int i, candidate;
4759         bool path_a_ok, path_b_ok;
4760         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4761         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4762         s32 reg_tmp = 0;
4763         bool simu;
4764
4765         rtl8xxxu_prepare_calibrate(priv, 1);
4766
4767         memset(result, 0, sizeof(result));
4768         candidate = -1;
4769
4770         path_a_ok = false;
4771         path_b_ok = false;
4772
4773         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4774
4775         for (i = 0; i < 3; i++) {
4776                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4777
4778                 if (i == 1) {
4779                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4780                         if (simu) {
4781                                 candidate = 0;
4782                                 break;
4783                         }
4784                 }
4785
4786                 if (i == 2) {
4787                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4788                         if (simu) {
4789                                 candidate = 0;
4790                                 break;
4791                         }
4792
4793                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4794                         if (simu) {
4795                                 candidate = 1;
4796                         } else {
4797                                 for (i = 0; i < 8; i++)
4798                                         reg_tmp += result[3][i];
4799
4800                                 if (reg_tmp)
4801                                         candidate = 3;
4802                                 else
4803                                         candidate = -1;
4804                         }
4805                 }
4806         }
4807
4808         for (i = 0; i < 4; i++) {
4809                 reg_e94 = result[i][0];
4810                 reg_e9c = result[i][1];
4811                 reg_ea4 = result[i][2];
4812                 reg_eac = result[i][3];
4813                 reg_eb4 = result[i][4];
4814                 reg_ebc = result[i][5];
4815                 reg_ec4 = result[i][6];
4816                 reg_ecc = result[i][7];
4817         }
4818
4819         if (candidate >= 0) {
4820                 reg_e94 = result[candidate][0];
4821                 priv->rege94 =  reg_e94;
4822                 reg_e9c = result[candidate][1];
4823                 priv->rege9c = reg_e9c;
4824                 reg_ea4 = result[candidate][2];
4825                 reg_eac = result[candidate][3];
4826                 reg_eb4 = result[candidate][4];
4827                 priv->regeb4 = reg_eb4;
4828                 reg_ebc = result[candidate][5];
4829                 priv->regebc = reg_ebc;
4830                 reg_ec4 = result[candidate][6];
4831                 reg_ecc = result[candidate][7];
4832                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4833                 dev_dbg(dev,
4834                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4835                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4836                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4837                 path_a_ok = true;
4838                 path_b_ok = true;
4839         } else {
4840                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4841                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4842         }
4843
4844         if (reg_e94 && candidate >= 0)
4845                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4846                                            candidate, (reg_ea4 == 0));
4847
4848         if (priv->tx_paths > 1 && reg_eb4)
4849                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4850                                            candidate, (reg_ec4 == 0));
4851
4852         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4853                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4854
4855         rtl8xxxu_prepare_calibrate(priv, 0);
4856 }
4857
4858 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4859 {
4860         struct device *dev = &priv->udev->dev;
4861         int result[4][8];       /* last is final result */
4862         int i, candidate;
4863         bool path_a_ok, path_b_ok;
4864         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4865         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4866         u32 val32, bt_control;
4867         s32 reg_tmp = 0;
4868         bool simu;
4869
4870         rtl8xxxu_prepare_calibrate(priv, 1);
4871
4872         memset(result, 0, sizeof(result));
4873         candidate = -1;
4874
4875         path_a_ok = false;
4876         path_b_ok = false;
4877
4878         bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
4879
4880         for (i = 0; i < 3; i++) {
4881                 rtl8723bu_phy_iqcalibrate(priv, result, i);
4882
4883                 if (i == 1) {
4884                         simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
4885                         if (simu) {
4886                                 candidate = 0;
4887                                 break;
4888                         }
4889                 }
4890
4891                 if (i == 2) {
4892                         simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
4893                         if (simu) {
4894                                 candidate = 0;
4895                                 break;
4896                         }
4897
4898                         simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
4899                         if (simu) {
4900                                 candidate = 1;
4901                         } else {
4902                                 for (i = 0; i < 8; i++)
4903                                         reg_tmp += result[3][i];
4904
4905                                 if (reg_tmp)
4906                                         candidate = 3;
4907                                 else
4908                                         candidate = -1;
4909                         }
4910                 }
4911         }
4912
4913         for (i = 0; i < 4; i++) {
4914                 reg_e94 = result[i][0];
4915                 reg_e9c = result[i][1];
4916                 reg_ea4 = result[i][2];
4917                 reg_eac = result[i][3];
4918                 reg_eb4 = result[i][4];
4919                 reg_ebc = result[i][5];
4920                 reg_ec4 = result[i][6];
4921                 reg_ecc = result[i][7];
4922         }
4923
4924         if (candidate >= 0) {
4925                 reg_e94 = result[candidate][0];
4926                 priv->rege94 =  reg_e94;
4927                 reg_e9c = result[candidate][1];
4928                 priv->rege9c = reg_e9c;
4929                 reg_ea4 = result[candidate][2];
4930                 reg_eac = result[candidate][3];
4931                 reg_eb4 = result[candidate][4];
4932                 priv->regeb4 = reg_eb4;
4933                 reg_ebc = result[candidate][5];
4934                 priv->regebc = reg_ebc;
4935                 reg_ec4 = result[candidate][6];
4936                 reg_ecc = result[candidate][7];
4937                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4938                 dev_dbg(dev,
4939                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4940                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4941                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4942                 path_a_ok = true;
4943                 path_b_ok = true;
4944         } else {
4945                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4946                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4947         }
4948
4949         if (reg_e94 && candidate >= 0)
4950                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4951                                            candidate, (reg_ea4 == 0));
4952
4953         if (priv->tx_paths > 1 && reg_eb4)
4954                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4955                                            candidate, (reg_ec4 == 0));
4956
4957         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4958                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
4959
4960         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
4961
4962         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4963         val32 |= 0x80000;
4964         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4965         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
4966         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4967         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
4968         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4969         val32 |= 0x20;
4970         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4971         rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
4972
4973         if (priv->rf_paths > 1) {
4974                 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
4975 #ifdef RTL8723BU_PATH_B
4976                 if (RF_Path == 0x0)     //S1
4977                         ODM_SetIQCbyRFpath(pDM_Odm, 0);
4978                 else    //S0
4979                         ODM_SetIQCbyRFpath(pDM_Odm, 1);
4980 #endif
4981         }
4982         rtl8xxxu_prepare_calibrate(priv, 0);
4983 }
4984
4985 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
4986 {
4987         u32 val32;
4988         u32 rf_amode, rf_bmode = 0, lstf;
4989
4990         /* Check continuous TX and Packet TX */
4991         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
4992
4993         if (lstf & OFDM_LSTF_MASK) {
4994                 /* Disable all continuous TX */
4995                 val32 = lstf & ~OFDM_LSTF_MASK;
4996                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
4997
4998                 /* Read original RF mode Path A */
4999                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5000
5001                 /* Set RF mode to standby Path A */
5002                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5003                                      (rf_amode & 0x8ffff) | 0x10000);
5004
5005                 /* Path-B */
5006                 if (priv->tx_paths > 1) {
5007                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5008                                                        RF6052_REG_AC);
5009
5010                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5011                                              (rf_bmode & 0x8ffff) | 0x10000);
5012                 }
5013         } else {
5014                 /*  Deal with Packet TX case */
5015                 /*  block all queues */
5016                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5017         }
5018
5019         /* Start LC calibration */
5020         if (priv->fops->has_s0s1)
5021                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
5022         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5023         val32 |= 0x08000;
5024         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5025
5026         msleep(100);
5027
5028         if (priv->fops->has_s0s1)
5029                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5030
5031         /* Restore original parameters */
5032         if (lstf & OFDM_LSTF_MASK) {
5033                 /* Path-A */
5034                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5035                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5036
5037                 /* Path-B */
5038                 if (priv->tx_paths > 1)
5039                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5040                                              rf_bmode);
5041         } else /*  Deal with Packet TX case */
5042                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5043 }
5044
5045 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5046 {
5047         int i;
5048         u16 reg;
5049
5050         reg = REG_MACID;
5051
5052         for (i = 0; i < ETH_ALEN; i++)
5053                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5054
5055         return 0;
5056 }
5057
5058 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5059 {
5060         int i;
5061         u16 reg;
5062
5063         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5064
5065         reg = REG_BSSID;
5066
5067         for (i = 0; i < ETH_ALEN; i++)
5068                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5069
5070         return 0;
5071 }
5072
5073 static void
5074 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5075 {
5076         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5077         u8 max_agg = 0xf;
5078         int i;
5079
5080         ampdu_factor = 1 << (ampdu_factor + 2);
5081         if (ampdu_factor > max_agg)
5082                 ampdu_factor = max_agg;
5083
5084         for (i = 0; i < 4; i++) {
5085                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5086                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5087
5088                 if ((vals[i] & 0x0f) > ampdu_factor)
5089                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5090
5091                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5092         }
5093 }
5094
5095 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5096 {
5097         u8 val8;
5098
5099         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5100         val8 &= 0xf8;
5101         val8 |= density;
5102         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5103 }
5104
5105 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5106 {
5107         u8 val8;
5108         int count, ret;
5109
5110         /* Start of rtl8723AU_card_enable_flow */
5111         /* Act to Cardemu sequence*/
5112         /* Turn off RF */
5113         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5114
5115         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5116         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5117         val8 &= ~LEDCFG2_DPDT_SELECT;
5118         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5119
5120         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5121         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5122         val8 |= BIT(1);
5123         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5124
5125         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5126                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5127                 if ((val8 & BIT(1)) == 0)
5128                         break;
5129                 udelay(10);
5130         }
5131
5132         if (!count) {
5133                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5134                          __func__);
5135                 ret = -EBUSY;
5136                 goto exit;
5137         }
5138
5139         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5140         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5141         val8 |= SYS_ISO_ANALOG_IPS;
5142         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5143
5144         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5145         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5146         val8 &= ~LDOA15_ENABLE;
5147         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5148
5149 exit:
5150         return ret;
5151 }
5152
5153 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5154 {
5155         u8 val8;
5156         u8 val32;
5157         int count, ret;
5158
5159         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5160
5161         /*
5162          * Poll - wait for RX packet to complete
5163          */
5164         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5165                 val32 = rtl8xxxu_read32(priv, 0x5f8);
5166                 if (!val32)
5167                         break;
5168                 udelay(10);
5169         }
5170
5171         if (!count) {
5172                 dev_warn(&priv->udev->dev,
5173                          "%s: RX poll timed out (0x05f8)\n", __func__);
5174                 ret = -EBUSY;
5175                 goto exit;
5176         }
5177
5178         /* Disable CCK and OFDM, clock gated */
5179         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5180         val8 &= ~SYS_FUNC_BBRSTB;
5181         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5182
5183         udelay(2);
5184
5185         /* Reset baseband */
5186         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5187         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5188         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5189
5190         /* Reset MAC TRX */
5191         val8 = rtl8xxxu_read8(priv, REG_CR);
5192         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5193         rtl8xxxu_write8(priv, REG_CR, val8);
5194
5195         /* Reset MAC TRX */
5196         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5197         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5198         rtl8xxxu_write8(priv, REG_CR + 1, val8);
5199
5200         /* Respond TX OK to scheduler */
5201         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5202         val8 |= DUAL_TSF_TX_OK;
5203         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5204
5205 exit:
5206         return ret;
5207 }
5208
5209 static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
5210 {
5211         u8 val8;
5212
5213         /* Clear suspend enable and power down enable*/
5214         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5215         val8 &= ~(BIT(3) | BIT(7));
5216         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5217
5218         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5219         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5220         val8 &= ~BIT(0);
5221         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5222
5223         /* 0x04[12:11] = 11 enable WL suspend*/
5224         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5225         val8 &= ~(BIT(3) | BIT(4));
5226         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5227 }
5228
5229 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5230 {
5231         u8 val8;
5232
5233         /* Clear suspend enable and power down enable*/
5234         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5235         val8 &= ~(BIT(3) | BIT(4));
5236         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5237 }
5238
5239 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5240 {
5241         u8 val8;
5242         u32 val32;
5243         int count, ret = 0;
5244
5245         /* disable HWPDN 0x04[15]=0*/
5246         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5247         val8 &= ~BIT(7);
5248         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5249
5250         /* disable SW LPS 0x04[10]= 0 */
5251         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5252         val8 &= ~BIT(2);
5253         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5254
5255         /* disable WL suspend*/
5256         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5257         val8 &= ~(BIT(3) | BIT(4));
5258         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5259
5260         /* wait till 0x04[17] = 1 power ready*/
5261         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5262                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5263                 if (val32 & BIT(17))
5264                         break;
5265
5266                 udelay(10);
5267         }
5268
5269         if (!count) {
5270                 ret = -EBUSY;
5271                 goto exit;
5272         }
5273
5274         /* We should be able to optimize the following three entries into one */
5275
5276         /* release WLON reset 0x04[16]= 1*/
5277         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5278         val8 |= BIT(0);
5279         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5280
5281         /* set, then poll until 0 */
5282         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5283         val32 |= APS_FSMCO_MAC_ENABLE;
5284         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5285
5286         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5287                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5288                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5289                         ret = 0;
5290                         break;
5291                 }
5292                 udelay(10);
5293         }
5294
5295         if (!count) {
5296                 ret = -EBUSY;
5297                 goto exit;
5298         }
5299
5300 exit:
5301         return ret;
5302 }
5303
5304 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
5305 {
5306         u8 val8;
5307         u32 val32;
5308         int count, ret = 0;
5309
5310         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5311         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5312         val8 |= LDOA15_ENABLE;
5313         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5314
5315         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5316         val8 = rtl8xxxu_read8(priv, 0x0067);
5317         val8 &= ~BIT(4);
5318         rtl8xxxu_write8(priv, 0x0067, val8);
5319
5320         mdelay(1);
5321
5322         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5323         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5324         val8 &= ~SYS_ISO_ANALOG_IPS;
5325         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5326
5327         /* disable SW LPS 0x04[10]= 0 */
5328         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5329         val8 &= ~BIT(2);
5330         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5331
5332         /* wait till 0x04[17] = 1 power ready*/
5333         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5334                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5335                 if (val32 & BIT(17))
5336                         break;
5337
5338                 udelay(10);
5339         }
5340
5341         if (!count) {
5342                 ret = -EBUSY;
5343                 goto exit;
5344         }
5345
5346         /* We should be able to optimize the following three entries into one */
5347
5348         /* release WLON reset 0x04[16]= 1*/
5349         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5350         val8 |= BIT(0);
5351         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5352
5353         /* disable HWPDN 0x04[15]= 0*/
5354         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5355         val8 &= ~BIT(7);
5356         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5357
5358         /* disable WL suspend*/
5359         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5360         val8 &= ~(BIT(3) | BIT(4));
5361         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5362
5363         /* set, then poll until 0 */
5364         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5365         val32 |= APS_FSMCO_MAC_ENABLE;
5366         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5367
5368         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5369                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5370                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5371                         ret = 0;
5372                         break;
5373                 }
5374                 udelay(10);
5375         }
5376
5377         if (!count) {
5378                 ret = -EBUSY;
5379                 goto exit;
5380         }
5381
5382         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5383         /*
5384          * Note: Vendor driver actually clears this bit, despite the
5385          * documentation claims it's being set!
5386          */
5387         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5388         val8 |= LEDCFG2_DPDT_SELECT;
5389         val8 &= ~LEDCFG2_DPDT_SELECT;
5390         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5391
5392 exit:
5393         return ret;
5394 }
5395
5396 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5397 {
5398         u8 val8;
5399         u32 val32;
5400         int count, ret = 0;
5401
5402         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5403         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5404         val8 |= LDOA15_ENABLE;
5405         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5406
5407         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5408         val8 = rtl8xxxu_read8(priv, 0x0067);
5409         val8 &= ~BIT(4);
5410         rtl8xxxu_write8(priv, 0x0067, val8);
5411
5412         mdelay(1);
5413
5414         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5415         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5416         val8 &= ~SYS_ISO_ANALOG_IPS;
5417         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5418
5419         /* Disable SW LPS 0x04[10]= 0 */
5420         val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5421         val32 &= ~APS_FSMCO_SW_LPS;
5422         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5423
5424         /* Wait until 0x04[17] = 1 power ready */
5425         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5426                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5427                 if (val32 & BIT(17))
5428                         break;
5429
5430                 udelay(10);
5431         }
5432
5433         if (!count) {
5434                 ret = -EBUSY;
5435                 goto exit;
5436         }
5437
5438         /* We should be able to optimize the following three entries into one */
5439
5440         /* Release WLON reset 0x04[16]= 1*/
5441         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5442         val32 |= APS_FSMCO_WLON_RESET;
5443         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5444
5445         /* Disable HWPDN 0x04[15]= 0*/
5446         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5447         val32 &= ~APS_FSMCO_HW_POWERDOWN;
5448         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5449
5450         /* Disable WL suspend*/
5451         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5452         val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5453         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5454
5455         /* Set, then poll until 0 */
5456         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5457         val32 |= APS_FSMCO_MAC_ENABLE;
5458         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5459
5460         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5461                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5462                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5463                         ret = 0;
5464                         break;
5465                 }
5466                 udelay(10);
5467         }
5468
5469         if (!count) {
5470                 ret = -EBUSY;
5471                 goto exit;
5472         }
5473
5474         /* Enable WL control XTAL setting */
5475         val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5476         val8 |= AFE_MISC_WL_XTAL_CTRL;
5477         rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5478
5479         /* Enable falling edge triggering interrupt */
5480         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5481         val8 |= BIT(1);
5482         rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5483
5484         /* Enable GPIO9 interrupt mode */
5485         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5486         val8 |= BIT(1);
5487         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5488
5489         /* Enable GPIO9 input mode */
5490         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5491         val8 &= ~BIT(1);
5492         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5493
5494         /* Enable HSISR GPIO[C:0] interrupt */
5495         val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5496         val8 |= BIT(0);
5497         rtl8xxxu_write8(priv, REG_HSIMR, val8);
5498
5499         /* Enable HSISR GPIO9 interrupt */
5500         val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5501         val8 |= BIT(1);
5502         rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5503
5504         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5505         val8 |= MULTI_WIFI_HW_ROF_EN;
5506         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5507
5508         /* For GPIO9 internal pull high setting BIT(14) */
5509         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5510         val8 |= BIT(6);
5511         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5512
5513 exit:
5514         return ret;
5515 }
5516
5517 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5518 {
5519         u8 val8;
5520
5521         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5522         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5523
5524         /* 0x04[12:11] = 01 enable WL suspend */
5525         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5526         val8 &= ~BIT(4);
5527         val8 |= BIT(3);
5528         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5529
5530         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5531         val8 |= BIT(7);
5532         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5533
5534         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5535         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5536         val8 |= BIT(0);
5537         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5538
5539         return 0;
5540 }
5541
5542 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5543 {
5544         u8 val8;
5545         u16 val16;
5546         u32 val32;
5547         int ret;
5548
5549         /*
5550          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5551          */
5552         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5553
5554         rtl8723a_disabled_to_emu(priv);
5555
5556         ret = rtl8723a_emu_to_active(priv);
5557         if (ret)
5558                 goto exit;
5559
5560         /*
5561          * 0x0004[19] = 1, reset 8051
5562          */
5563         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5564         val8 |= BIT(3);
5565         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5566
5567         /*
5568          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5569          * Set CR bit10 to enable 32k calibration.
5570          */
5571         val16 = rtl8xxxu_read16(priv, REG_CR);
5572         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5573                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5574                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5575                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5576                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5577         rtl8xxxu_write16(priv, REG_CR, val16);
5578
5579         /* For EFuse PG */
5580         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5581         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5582         val32 |= (0x06 << 28);
5583         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5584 exit:
5585         return ret;
5586 }
5587
5588 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5589 {
5590         u8 val8;
5591         u16 val16;
5592         u32 val32;
5593         int ret;
5594
5595         rtl8723a_disabled_to_emu(priv);
5596
5597         ret = rtl8723b_emu_to_active(priv);
5598         if (ret)
5599                 goto exit;
5600
5601         /*
5602          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5603          * Set CR bit10 to enable 32k calibration.
5604          */
5605         val16 = rtl8xxxu_read16(priv, REG_CR);
5606         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5607                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5608                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5609                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5610                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5611         rtl8xxxu_write16(priv, REG_CR, val16);
5612
5613         /*
5614          * BT coexist power on settings. This is identical for 1 and 2
5615          * antenna parts.
5616          */
5617         rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
5618
5619         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5620         val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
5621         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5622
5623         rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
5624         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5625         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5626         /* Antenna inverse */
5627         rtl8xxxu_write8(priv, 0xfe08, 0x01);
5628
5629         val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
5630         val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
5631         rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
5632
5633         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5634         val32 |= LEDCFG0_DPDT_SELECT;
5635         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5636
5637         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5638         val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
5639         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5640 exit:
5641         return ret;
5642 }
5643
5644 #ifdef CONFIG_RTL8XXXU_UNTESTED
5645
5646 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5647 {
5648         u8 val8;
5649         u16 val16;
5650         u32 val32;
5651         int i;
5652
5653         for (i = 100; i; i--) {
5654                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5655                 if (val8 & APS_FSMCO_PFM_ALDN)
5656                         break;
5657         }
5658
5659         if (!i) {
5660                 pr_info("%s: Poll failed\n", __func__);
5661                 return -ENODEV;
5662         }
5663
5664         /*
5665          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5666          */
5667         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5668         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5669         udelay(100);
5670
5671         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5672         if (!(val8 & LDOV12D_ENABLE)) {
5673                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5674                 val8 |= LDOV12D_ENABLE;
5675                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5676
5677                 udelay(100);
5678
5679                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5680                 val8 &= ~SYS_ISO_MD2PP;
5681                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5682         }
5683
5684         /*
5685          * Auto enable WLAN
5686          */
5687         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5688         val16 |= APS_FSMCO_MAC_ENABLE;
5689         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5690
5691         for (i = 1000; i; i--) {
5692                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5693                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5694                         break;
5695         }
5696         if (!i) {
5697                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5698                 return -EBUSY;
5699         }
5700
5701         /*
5702          * Enable radio, GPIO, LED
5703          */
5704         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5705                 APS_FSMCO_PFM_ALDN;
5706         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5707
5708         /*
5709          * Release RF digital isolation
5710          */
5711         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5712         val16 &= ~SYS_ISO_DIOR;
5713         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5714
5715         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5716         val8 &= ~APSD_CTRL_OFF;
5717         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5718         for (i = 200; i; i--) {
5719                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5720                 if (!(val8 & APSD_CTRL_OFF_STATUS))
5721                         break;
5722         }
5723
5724         if (!i) {
5725                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5726                 return -EBUSY;
5727         }
5728
5729         /*
5730          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5731          */
5732         val16 = rtl8xxxu_read16(priv, REG_CR);
5733         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5734                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5735                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5736         rtl8xxxu_write16(priv, REG_CR, val16);
5737
5738         /*
5739          * Workaround for 8188RU LNA power leakage problem.
5740          */
5741         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5742                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5743                 val32 &= ~BIT(1);
5744                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5745         }
5746         return 0;
5747 }
5748
5749 #endif
5750
5751 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5752 {
5753         u16 val16;
5754         u32 val32;
5755         int ret;
5756
5757         ret = 0;
5758
5759         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5760         if (val32 & SYS_CFG_SPS_LDO_SEL) {
5761                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5762         } else {
5763                 /*
5764                  * Raise 1.2V voltage
5765                  */
5766                 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5767                 val32 &= 0xff0fffff;
5768                 val32 |= 0x00500000;
5769                 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5770                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5771         }
5772
5773         rtl8192e_disabled_to_emu(priv);
5774
5775         ret = rtl8192e_emu_to_active(priv);
5776         if (ret)
5777                 goto exit;
5778
5779         rtl8xxxu_write16(priv, REG_CR, 0x0000);
5780
5781         /*
5782          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5783          * Set CR bit10 to enable 32k calibration.
5784          */
5785         val16 = rtl8xxxu_read16(priv, REG_CR);
5786         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5787                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5788                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5789                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5790                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5791         rtl8xxxu_write16(priv, REG_CR, val16);
5792
5793 exit:
5794         return ret;
5795 }
5796
5797 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
5798 {
5799         u8 val8;
5800         u16 val16;
5801         u32 val32;
5802
5803         /*
5804          * Workaround for 8188RU LNA power leakage problem.
5805          */
5806         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5807                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5808                 val32 |= BIT(1);
5809                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5810         }
5811
5812         rtl8xxxu_active_to_lps(priv);
5813
5814         /* Turn off RF */
5815         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
5816
5817         /* Reset Firmware if running in RAM */
5818         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
5819                 rtl8xxxu_firmware_self_reset(priv);
5820
5821         /* Reset MCU */
5822         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5823         val16 &= ~SYS_FUNC_CPU_ENABLE;
5824         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5825
5826         /* Reset MCU ready status */
5827         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
5828
5829         rtl8xxxu_active_to_emu(priv);
5830         rtl8xxxu_emu_to_disabled(priv);
5831
5832         /* Reset MCU IO Wrapper */
5833         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5834         val8 &= ~BIT(0);
5835         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5836
5837         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5838         val8 |= BIT(0);
5839         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5840
5841         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
5842         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
5843 }
5844
5845 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
5846                                   u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
5847 {
5848         struct h2c_cmd h2c;
5849
5850         memset(&h2c, 0, sizeof(struct h2c_cmd));
5851         h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
5852         h2c.b_type_dma.data1 = arg1;
5853         h2c.b_type_dma.data2 = arg2;
5854         h2c.b_type_dma.data3 = arg3;
5855         h2c.b_type_dma.data4 = arg4;
5856         h2c.b_type_dma.data5 = arg5;
5857         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
5858 }
5859
5860 static void rtl8723bu_init_bt(struct rtl8xxxu_priv *priv)
5861 {
5862         struct h2c_cmd h2c;
5863         u32 val32;
5864         u8 val8;
5865
5866         /*
5867          * No indication anywhere as to what 0x0790 does. The 2 antenna
5868          * vendor code preserves bits 6-7 here.
5869          */
5870         rtl8xxxu_write8(priv, 0x0790, 0x05);
5871         /*
5872          * 0x0778 seems to be related to enabling the number of antennas
5873          * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
5874          * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
5875          */
5876         rtl8xxxu_write8(priv, 0x0778, 0x01);
5877
5878         val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
5879         val8 |= BIT(5);
5880         rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
5881
5882         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
5883
5884         rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
5885
5886         /*
5887          * Set BT grant to low
5888          */
5889         memset(&h2c, 0, sizeof(struct h2c_cmd));
5890         h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
5891         h2c.bt_grant.data = 0;
5892         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
5893
5894         /*
5895          * WLAN action by PTA
5896          */
5897         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5898
5899         /*
5900          * BT select S0/S1 controlled by WiFi
5901          */
5902         val8 = rtl8xxxu_read8(priv, 0x0067);
5903         val8 |= BIT(5);
5904         rtl8xxxu_write8(priv, 0x0067, val8);
5905
5906         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
5907         val32 |= BIT(11);
5908         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
5909
5910         /*
5911          * Bits 6/7 are marked in/out ... but for what?
5912          */
5913         rtl8xxxu_write8(priv, 0x0974, 0xff);
5914
5915         val32 = rtl8xxxu_read32(priv, 0x0944);
5916         val32 |= (BIT(0) | BIT(1));
5917         rtl8xxxu_write32(priv, 0x0944, val32);
5918
5919         rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
5920
5921         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5922         val32 &= ~BIT(24);
5923         val32 |= BIT(23);
5924         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5925
5926         /*
5927          * Fix external switch Main->S1, Aux->S0
5928          */
5929         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5930         val8 &= ~BIT(0);
5931         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5932
5933         memset(&h2c, 0, sizeof(struct h2c_cmd));
5934         h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
5935         h2c.ant_sel_rsv.ant_inverse = 1;
5936         h2c.ant_sel_rsv.int_switch_type = 0;
5937         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
5938
5939         /*
5940          * 0x280, 0x00, 0x200, 0x80 - not clear
5941          */
5942         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5943
5944         /*
5945          * Software control, antenna at WiFi side
5946          */
5947         rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
5948
5949         memset(&h2c, 0, sizeof(struct h2c_cmd));
5950         h2c.bt_info.cmd = H2C_8723B_BT_INFO;
5951         h2c.bt_info.data = BIT(0);
5952         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
5953
5954         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5955         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5956         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5957         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5958
5959         memset(&h2c, 0, sizeof(struct h2c_cmd));
5960         h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
5961         h2c.ignore_wlan.data = 0;
5962         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
5963 }
5964
5965 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
5966 {
5967         u32 agg_rx;
5968         u8 agg_ctrl;
5969
5970         /*
5971          * For now simply disable RX aggregation
5972          */
5973         agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
5974         agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
5975
5976         agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
5977         agg_rx &= ~RXDMA_USB_AGG_ENABLE;
5978         agg_rx &= ~0xff0f;
5979
5980         rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
5981         rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
5982 }
5983
5984 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
5985 {
5986         u32 val32;
5987
5988         /* Time duration for NHM unit: 4us, 0x2710=40ms */
5989         rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
5990         rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
5991         rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
5992         rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
5993         /* TH8 */
5994         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5995         val32 |= 0xff;
5996         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5997         /* Enable CCK */
5998         val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
5999         val32 |= BIT(8) | BIT(9) | BIT(10);
6000         rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6001         /* Max power amongst all RX antennas */
6002         val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6003         val32 |= BIT(7);
6004         rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6005 }
6006
6007 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6008 {
6009         struct rtl8xxxu_priv *priv = hw->priv;
6010         struct device *dev = &priv->udev->dev;
6011         struct rtl8xxxu_rfregval *rftable;
6012         bool macpower;
6013         int ret;
6014         u8 val8;
6015         u16 val16;
6016         u32 val32;
6017
6018         /* Check if MAC is already powered on */
6019         val8 = rtl8xxxu_read8(priv, REG_CR);
6020
6021         /*
6022          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6023          * initialized. First MAC returns 0xea, second MAC returns 0x00
6024          */
6025         if (val8 == 0xea)
6026                 macpower = false;
6027         else
6028                 macpower = true;
6029
6030         ret = priv->fops->power_on(priv);
6031         if (ret < 0) {
6032                 dev_warn(dev, "%s: Failed power on\n", __func__);
6033                 goto exit;
6034         }
6035
6036         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6037         if (!macpower) {
6038                 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6039                 if (ret) {
6040                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
6041                         goto exit;
6042                 }
6043
6044                 /*
6045                  * Presumably this is for 8188EU as well
6046                  * Enable TX report and TX report timer
6047                  */
6048                 if (priv->rtlchip == 0x8723bu) {
6049                         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6050                         val8 |= BIT(1);
6051                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6052                         /* Set MAX RPT MACID */
6053                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6054                         /* TX report Timer. Unit: 32us */
6055                         rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
6056
6057                         /* tmp ps ? */
6058                         val8 = rtl8xxxu_read8(priv, 0xa3);
6059                         val8 &= 0xf8;
6060                         rtl8xxxu_write8(priv, 0xa3, val8);
6061                 }
6062         }
6063
6064         ret = rtl8xxxu_download_firmware(priv);
6065         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6066         if (ret)
6067                 goto exit;
6068         ret = rtl8xxxu_start_firmware(priv);
6069         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6070         if (ret)
6071                 goto exit;
6072
6073         /* Solve too many protocol error on USB bus */
6074         /* Can't do this for 8188/8192 UMC A cut parts */
6075         if (priv->rtlchip == 0x8723a ||
6076             ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
6077               priv->rtlchip == 0x8188c) &&
6078              (priv->chip_cut || !priv->vendor_umc))) {
6079                 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6080                 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6081                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6082
6083                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6084                 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6085                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6086
6087                 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6088                 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6089                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6090
6091                 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6092                 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6093                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6094         }
6095
6096         if (priv->rtlchip == 0x8192e) {
6097                 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6098                 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
6099         }
6100
6101         if (priv->fops->phy_init_antenna_selection)
6102                 priv->fops->phy_init_antenna_selection(priv);
6103
6104         if (priv->rtlchip == 0x8723b)
6105                 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
6106         else
6107                 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
6108
6109         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6110         if (ret)
6111                 goto exit;
6112
6113         ret = rtl8xxxu_init_phy_bb(priv);
6114         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6115         if (ret)
6116                 goto exit;
6117
6118         switch(priv->rtlchip) {
6119         case 0x8723a:
6120                 rftable = rtl8723au_radioa_1t_init_table;
6121                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6122                 break;
6123         case 0x8723b:
6124                 rftable = rtl8723bu_radioa_1t_init_table;
6125                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6126                 /*
6127                  * PHY LCK
6128                  */
6129                 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
6130                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
6131                 msleep(200);
6132                 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
6133                 break;
6134         case 0x8188c:
6135                 if (priv->hi_pa)
6136                         rftable = rtl8188ru_radioa_1t_highpa_table;
6137                 else
6138                         rftable = rtl8192cu_radioa_1t_init_table;
6139                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6140                 break;
6141         case 0x8191c:
6142                 rftable = rtl8192cu_radioa_1t_init_table;
6143                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6144                 break;
6145         case 0x8192c:
6146                 rftable = rtl8192cu_radioa_2t_init_table;
6147                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6148                 if (ret)
6149                         break;
6150                 rftable = rtl8192cu_radiob_2t_init_table;
6151                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6152                 break;
6153         default:
6154                 ret = -EINVAL;
6155         }
6156
6157         if (ret)
6158                 goto exit;
6159
6160         /*
6161          * Chip specific quirks
6162          */
6163         if (priv->rtlchip == 0x8723a) {
6164                 /* Fix USB interface interference issue */
6165                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6166                 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6167                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6168                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6169
6170                 /* Reduce 80M spur */
6171                 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6172                 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6173                 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6174                 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6175         } else {
6176                 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6177                 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6178                 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
6179         }
6180
6181         if (!macpower) {
6182                 if (priv->ep_tx_normal_queue)
6183                         val8 = TX_PAGE_NUM_NORM_PQ;
6184                 else
6185                         val8 = 0;
6186
6187                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6188
6189                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
6190
6191                 if (priv->ep_tx_high_queue)
6192                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6193                 if (priv->ep_tx_low_queue)
6194                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6195
6196                 rtl8xxxu_write32(priv, REG_RQPN, val32);
6197
6198                 /*
6199                  * Set TX buffer boundary
6200                  */
6201                 val8 = TX_TOTAL_PAGE_NUM + 1;
6202
6203                 if (priv->rtlchip == 0x8723b)
6204                         val8 -= 1;
6205
6206                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6207                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6208                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6209                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6210                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6211         }
6212
6213         ret = rtl8xxxu_init_queue_priority(priv);
6214         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6215         if (ret)
6216                 goto exit;
6217
6218         /* RFSW Control - clear bit 14 ?? */
6219         if (priv->rtlchip != 0x8723b)
6220                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
6221         /* 0x07000760 */
6222         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
6223                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
6224                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
6225                  FPGA0_RF_BD_CTRL_SHIFT);
6226         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
6227         /* 0x860[6:5]= 00 - why? - this sets antenna B */
6228         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
6229
6230         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
6231                                                   RF6052_REG_MODE_AG);
6232
6233         /*
6234          * Set RX page boundary
6235          */
6236         if (priv->rtlchip == 0x8723b)
6237                 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f);
6238         else
6239                 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
6240         /*
6241          * Transfer page size is always 128
6242          */
6243         if (priv->rtlchip == 0x8723b)
6244                 val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) |
6245                         (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT);
6246         else
6247                 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
6248                         (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
6249         rtl8xxxu_write8(priv, REG_PBP, val8);
6250
6251         /*
6252          * Unit in 8 bytes, not obvious what it is used for
6253          */
6254         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6255
6256         /*
6257          * Enable all interrupts - not obvious USB needs to do this
6258          */
6259         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6260         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6261
6262         rtl8xxxu_set_mac(priv);
6263         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6264
6265         /*
6266          * Configure initial WMAC settings
6267          */
6268         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
6269                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6270                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6271         rtl8xxxu_write32(priv, REG_RCR, val32);
6272
6273         /*
6274          * Accept all multicast
6275          */
6276         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6277         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6278
6279         /*
6280          * Init adaptive controls
6281          */
6282         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6283         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6284         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6285         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6286
6287         /* CCK = 0x0a, OFDM = 0x10 */
6288         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6289         rtl8xxxu_set_retry(priv, 0x30, 0x30);
6290         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6291
6292         /*
6293          * Init EDCA
6294          */
6295         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6296
6297         /* Set CCK SIFS */
6298         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6299
6300         /* Set OFDM SIFS */
6301         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6302
6303         /* TXOP */
6304         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6305         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6306         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6307         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6308
6309         /* Set data auto rate fallback retry count */
6310         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6311         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6312         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6313         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6314
6315         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6316         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6317         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6318
6319         /*  Set ACK timeout */
6320         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6321
6322         /*
6323          * Initialize beacon parameters
6324          */
6325         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6326         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6327         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6328         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6329         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6330         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6331
6332         /*
6333          * Initialize burst parameters
6334          */
6335         if (priv->rtlchip == 0x8723b) {
6336                 /*
6337                  * For USB high speed set 512B packets
6338                  */
6339                 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
6340                 val8 &= ~(BIT(4) | BIT(5));
6341                 val8 |= BIT(4);
6342                 val8 |= BIT(1) | BIT(2) | BIT(3);
6343                 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
6344
6345                 /*
6346                  * For USB high speed set 512B packets
6347                  */
6348                 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
6349                 val8 |= BIT(7);
6350                 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
6351
6352                 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
6353                 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
6354                 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
6355                 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
6356                 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
6357                 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
6358                 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
6359
6360                 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
6361                 val8 |= BIT(5) | BIT(6);
6362                 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
6363         }
6364
6365         if (priv->fops->init_aggregation)
6366                 priv->fops->init_aggregation(priv);
6367
6368         /*
6369          * Enable CCK and OFDM block
6370          */
6371         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6372         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6373         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6374
6375         /*
6376          * Invalidate all CAM entries - bit 30 is undocumented
6377          */
6378         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6379
6380         /*
6381          * Start out with default power levels for channel 6, 20MHz
6382          */
6383         rtl8723a_set_tx_power(priv, 1, false);
6384
6385         /* Let the 8051 take control of antenna setting */
6386         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6387         val8 |= LEDCFG2_DPDT_SELECT;
6388         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6389
6390         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6391
6392         /* Disable BAR - not sure if this has any effect on USB */
6393         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6394
6395         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6396
6397         if (priv->fops->init_statistics)
6398                 priv->fops->init_statistics(priv);
6399
6400         rtl8723a_phy_lc_calibrate(priv);
6401
6402         priv->fops->phy_iq_calibrate(priv);
6403
6404         /*
6405          * This should enable thermal meter
6406          */
6407         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6408
6409         /* Init BT hw config. */
6410         if (priv->fops->init_bt)
6411                 priv->fops->init_bt(priv);
6412
6413         /* Set NAV_UPPER to 30000us */
6414         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6415         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6416
6417         if (priv->rtlchip == 0x8723a) {
6418                 /*
6419                  * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6420                  * but we need to find root cause.
6421                  * This is 8723au only.
6422                  */
6423                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6424                 if ((val32 & 0xff000000) != 0x83000000) {
6425                         val32 |= FPGA_RF_MODE_CCK;
6426                         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6427                 }
6428         }
6429
6430         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6431         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6432         /* ack for xmit mgmt frames. */
6433         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6434
6435 exit:
6436         return ret;
6437 }
6438
6439 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6440 {
6441         struct rtl8xxxu_priv *priv = hw->priv;
6442
6443         rtl8xxxu_power_off(priv);
6444 }
6445
6446 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6447                                struct ieee80211_key_conf *key, const u8 *mac)
6448 {
6449         u32 cmd, val32, addr, ctrl;
6450         int j, i, tmp_debug;
6451
6452         tmp_debug = rtl8xxxu_debug;
6453         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6454                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6455
6456         /*
6457          * This is a bit of a hack - the lower bits of the cipher
6458          * suite selector happens to match the cipher index in the CAM
6459          */
6460         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6461         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6462
6463         for (j = 5; j >= 0; j--) {
6464                 switch (j) {
6465                 case 0:
6466                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6467                         break;
6468                 case 1:
6469                         val32 = mac[2] | (mac[3] << 8) |
6470                                 (mac[4] << 16) | (mac[5] << 24);
6471                         break;
6472                 default:
6473                         i = (j - 2) << 2;
6474                         val32 = key->key[i] | (key->key[i + 1] << 8) |
6475                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6476                         break;
6477                 }
6478
6479                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6480                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6481                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6482                 udelay(100);
6483         }
6484
6485         rtl8xxxu_debug = tmp_debug;
6486 }
6487
6488 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
6489                                    struct ieee80211_vif *vif, const u8 *mac)
6490 {
6491         struct rtl8xxxu_priv *priv = hw->priv;
6492         u8 val8;
6493
6494         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6495         val8 |= BEACON_DISABLE_TSF_UPDATE;
6496         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6497 }
6498
6499 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6500                                       struct ieee80211_vif *vif)
6501 {
6502         struct rtl8xxxu_priv *priv = hw->priv;
6503         u8 val8;
6504
6505         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6506         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6507         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6508 }
6509
6510 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
6511                                       u32 ramask, int sgi)
6512 {
6513         struct h2c_cmd h2c;
6514
6515         h2c.ramask.cmd = H2C_SET_RATE_MASK;
6516         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6517         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6518
6519         h2c.ramask.arg = 0x80;
6520         if (sgi)
6521                 h2c.ramask.arg |= 0x20;
6522
6523         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
6524                 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6525         rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
6526 }
6527
6528 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6529 {
6530         u32 val32;
6531         u8 rate_idx = 0;
6532
6533         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6534
6535         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6536         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6537         val32 |= rate_cfg;
6538         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6539
6540         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6541
6542         while (rate_cfg) {
6543                 rate_cfg = (rate_cfg >> 1);
6544                 rate_idx++;
6545         }
6546         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6547 }
6548
6549 static void
6550 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6551                           struct ieee80211_bss_conf *bss_conf, u32 changed)
6552 {
6553         struct rtl8xxxu_priv *priv = hw->priv;
6554         struct device *dev = &priv->udev->dev;
6555         struct ieee80211_sta *sta;
6556         u32 val32;
6557         u8 val8;
6558
6559         if (changed & BSS_CHANGED_ASSOC) {
6560                 struct h2c_cmd h2c;
6561
6562                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6563
6564                 memset(&h2c, 0, sizeof(struct h2c_cmd));
6565                 rtl8xxxu_set_linktype(priv, vif->type);
6566
6567                 if (bss_conf->assoc) {
6568                         u32 ramask;
6569                         int sgi = 0;
6570
6571                         rcu_read_lock();
6572                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
6573                         if (!sta) {
6574                                 dev_info(dev, "%s: ASSOC no sta found\n",
6575                                          __func__);
6576                                 rcu_read_unlock();
6577                                 goto error;
6578                         }
6579
6580                         if (sta->ht_cap.ht_supported)
6581                                 dev_info(dev, "%s: HT supported\n", __func__);
6582                         if (sta->vht_cap.vht_supported)
6583                                 dev_info(dev, "%s: VHT supported\n", __func__);
6584
6585                         /* TODO: Set bits 28-31 for rate adaptive id */
6586                         ramask = (sta->supp_rates[0] & 0xfff) |
6587                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
6588                                 sta->ht_cap.mcs.rx_mask[1] << 20;
6589                         if (sta->ht_cap.cap &
6590                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6591                                 sgi = 1;
6592                         rcu_read_unlock();
6593
6594                         rtl8xxxu_update_rate_mask(priv, ramask, sgi);
6595
6596                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6597
6598                         rtl8723a_stop_tx_beacon(priv);
6599
6600                         /* joinbss sequence */
6601                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6602                                          0xc000 | bss_conf->aid);
6603
6604                         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6605                 } else {
6606                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6607                         val8 |= BEACON_DISABLE_TSF_UPDATE;
6608                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6609
6610                         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6611                 }
6612                 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
6613                 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
6614         }
6615
6616         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6617                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6618                         bss_conf->use_short_preamble);
6619                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6620                 if (bss_conf->use_short_preamble)
6621                         val32 |= RSR_ACK_SHORT_PREAMBLE;
6622                 else
6623                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6624                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6625         }
6626
6627         if (changed & BSS_CHANGED_ERP_SLOT) {
6628                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6629                         bss_conf->use_short_slot);
6630
6631                 if (bss_conf->use_short_slot)
6632                         val8 = 9;
6633                 else
6634                         val8 = 20;
6635                 rtl8xxxu_write8(priv, REG_SLOT, val8);
6636         }
6637
6638         if (changed & BSS_CHANGED_BSSID) {
6639                 dev_dbg(dev, "Changed BSSID!\n");
6640                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6641         }
6642
6643         if (changed & BSS_CHANGED_BASIC_RATES) {
6644                 dev_dbg(dev, "Changed BASIC_RATES!\n");
6645                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6646         }
6647 error:
6648         return;
6649 }
6650
6651 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6652 {
6653         u32 rtlqueue;
6654
6655         switch (queue) {
6656         case IEEE80211_AC_VO:
6657                 rtlqueue = TXDESC_QUEUE_VO;
6658                 break;
6659         case IEEE80211_AC_VI:
6660                 rtlqueue = TXDESC_QUEUE_VI;
6661                 break;
6662         case IEEE80211_AC_BE:
6663                 rtlqueue = TXDESC_QUEUE_BE;
6664                 break;
6665         case IEEE80211_AC_BK:
6666                 rtlqueue = TXDESC_QUEUE_BK;
6667                 break;
6668         default:
6669                 rtlqueue = TXDESC_QUEUE_BE;
6670         }
6671
6672         return rtlqueue;
6673 }
6674
6675 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6676 {
6677         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6678         u32 queue;
6679
6680         if (ieee80211_is_mgmt(hdr->frame_control))
6681                 queue = TXDESC_QUEUE_MGNT;
6682         else
6683                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6684
6685         return queue;
6686 }
6687
6688 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
6689 {
6690         __le16 *ptr = (__le16 *)tx_desc;
6691         u16 csum = 0;
6692         int i;
6693
6694         /*
6695          * Clear csum field before calculation, as the csum field is
6696          * in the middle of the struct.
6697          */
6698         tx_desc->csum = cpu_to_le16(0);
6699
6700         for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
6701                 csum = csum ^ le16_to_cpu(ptr[i]);
6702
6703         tx_desc->csum |= cpu_to_le16(csum);
6704 }
6705
6706 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
6707 {
6708         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
6709         unsigned long flags;
6710
6711         spin_lock_irqsave(&priv->tx_urb_lock, flags);
6712         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
6713                 list_del(&tx_urb->list);
6714                 priv->tx_urb_free_count--;
6715                 usb_free_urb(&tx_urb->urb);
6716         }
6717         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6718 }
6719
6720 static struct rtl8xxxu_tx_urb *
6721 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
6722 {
6723         struct rtl8xxxu_tx_urb *tx_urb;
6724         unsigned long flags;
6725
6726         spin_lock_irqsave(&priv->tx_urb_lock, flags);
6727         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
6728                                           struct rtl8xxxu_tx_urb, list);
6729         if (tx_urb) {
6730                 list_del(&tx_urb->list);
6731                 priv->tx_urb_free_count--;
6732                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
6733                     !priv->tx_stopped) {
6734                         priv->tx_stopped = true;
6735                         ieee80211_stop_queues(priv->hw);
6736                 }
6737         }
6738
6739         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6740
6741         return tx_urb;
6742 }
6743
6744 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
6745                                  struct rtl8xxxu_tx_urb *tx_urb)
6746 {
6747         unsigned long flags;
6748
6749         INIT_LIST_HEAD(&tx_urb->list);
6750
6751         spin_lock_irqsave(&priv->tx_urb_lock, flags);
6752
6753         list_add(&tx_urb->list, &priv->tx_urb_free_list);
6754         priv->tx_urb_free_count++;
6755         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
6756             priv->tx_stopped) {
6757                 priv->tx_stopped = false;
6758                 ieee80211_wake_queues(priv->hw);
6759         }
6760
6761         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6762 }
6763
6764 static void rtl8xxxu_tx_complete(struct urb *urb)
6765 {
6766         struct sk_buff *skb = (struct sk_buff *)urb->context;
6767         struct ieee80211_tx_info *tx_info;
6768         struct ieee80211_hw *hw;
6769         struct rtl8xxxu_tx_urb *tx_urb =
6770                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
6771
6772         tx_info = IEEE80211_SKB_CB(skb);
6773         hw = tx_info->rate_driver_data[0];
6774
6775         skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
6776
6777         ieee80211_tx_info_clear_status(tx_info);
6778         tx_info->status.rates[0].idx = -1;
6779         tx_info->status.rates[0].count = 0;
6780
6781         if (!urb->status)
6782                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
6783
6784         ieee80211_tx_status_irqsafe(hw, skb);
6785
6786         rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
6787 }
6788
6789 static void rtl8xxxu_dump_action(struct device *dev,
6790                                  struct ieee80211_hdr *hdr)
6791 {
6792         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
6793         u16 cap, timeout;
6794
6795         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
6796                 return;
6797
6798         switch (mgmt->u.action.u.addba_resp.action_code) {
6799         case WLAN_ACTION_ADDBA_RESP:
6800                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
6801                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
6802                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
6803                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6804                          "status %02x\n",
6805                          timeout,
6806                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6807                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6808                          (cap >> 1) & 0x1,
6809                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
6810                 break;
6811         case WLAN_ACTION_ADDBA_REQ:
6812                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
6813                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
6814                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
6815                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6816                          timeout,
6817                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6818                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6819                          (cap >> 1) & 0x1);
6820                 break;
6821         default:
6822                 dev_info(dev, "action frame %02x\n",
6823                          mgmt->u.action.u.addba_resp.action_code);
6824                 break;
6825         }
6826 }
6827
6828 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
6829                         struct ieee80211_tx_control *control,
6830                         struct sk_buff *skb)
6831 {
6832         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6833         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
6834         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
6835         struct rtl8xxxu_priv *priv = hw->priv;
6836         struct rtl8xxxu_tx_desc *tx_desc;
6837         struct rtl8xxxu_tx_urb *tx_urb;
6838         struct ieee80211_sta *sta = NULL;
6839         struct ieee80211_vif *vif = tx_info->control.vif;
6840         struct device *dev = &priv->udev->dev;
6841         u32 queue, rate;
6842         u16 pktlen = skb->len;
6843         u16 seq_number;
6844         u16 rate_flag = tx_info->control.rates[0].flags;
6845         int ret;
6846
6847         if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
6848                 dev_warn(dev,
6849                          "%s: Not enough headroom (%i) for tx descriptor\n",
6850                          __func__, skb_headroom(skb));
6851                 goto error;
6852         }
6853
6854         if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
6855                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
6856                          __func__, skb->len);
6857                 goto error;
6858         }
6859
6860         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
6861         if (!tx_urb) {
6862                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
6863                 goto error;
6864         }
6865
6866         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
6867                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
6868                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
6869
6870         if (ieee80211_is_action(hdr->frame_control))
6871                 rtl8xxxu_dump_action(dev, hdr);
6872
6873         tx_info->rate_driver_data[0] = hw;
6874
6875         if (control && control->sta)
6876                 sta = control->sta;
6877
6878         tx_desc = (struct rtl8xxxu_tx_desc *)
6879                 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
6880
6881         memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
6882         tx_desc->pkt_size = cpu_to_le16(pktlen);
6883         tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
6884
6885         tx_desc->txdw0 =
6886                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
6887         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
6888             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
6889                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
6890
6891         queue = rtl8xxxu_queue_select(hw, skb);
6892         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
6893
6894         if (tx_info->control.hw_key) {
6895                 switch (tx_info->control.hw_key->cipher) {
6896                 case WLAN_CIPHER_SUITE_WEP40:
6897                 case WLAN_CIPHER_SUITE_WEP104:
6898                 case WLAN_CIPHER_SUITE_TKIP:
6899                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
6900                         break;
6901                 case WLAN_CIPHER_SUITE_CCMP:
6902                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
6903                         break;
6904                 default:
6905                         break;
6906                 }
6907         }
6908
6909         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
6910         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
6911
6912         if (rate_flag & IEEE80211_TX_RC_MCS)
6913                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
6914         else
6915                 rate = tx_rate->hw_value;
6916         tx_desc->txdw5 = cpu_to_le32(rate);
6917
6918         if (ieee80211_is_data(hdr->frame_control))
6919                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
6920
6921         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
6922         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
6923                 if (sta->ht_cap.ht_supported) {
6924                         u32 ampdu, val32;
6925
6926                         ampdu = (u32)sta->ht_cap.ampdu_density;
6927                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
6928                         tx_desc->txdw2 |= cpu_to_le32(val32);
6929                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
6930                 } else
6931                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6932         } else
6933                 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
6934
6935         if (ieee80211_is_data_qos(hdr->frame_control))
6936                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
6937         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
6938             (sta && vif && vif->bss_conf.use_short_preamble))
6939                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
6940         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
6941             (ieee80211_is_data_qos(hdr->frame_control) &&
6942              sta && sta->ht_cap.cap &
6943              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
6944                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
6945         }
6946         if (ieee80211_is_mgmt(hdr->frame_control)) {
6947                 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
6948                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
6949                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
6950                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
6951         }
6952
6953         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
6954                 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
6955                 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
6956                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
6957                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
6958         }
6959
6960         rtl8xxxu_calc_tx_desc_csum(tx_desc);
6961
6962         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
6963                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
6964
6965         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
6966         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
6967         if (ret) {
6968                 usb_unanchor_urb(&tx_urb->urb);
6969                 rtl8xxxu_free_tx_urb(priv, tx_urb);
6970                 goto error;
6971         }
6972         return;
6973 error:
6974         dev_kfree_skb(skb);
6975 }
6976
6977 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
6978                                        struct ieee80211_rx_status *rx_status,
6979                                        struct rtl8xxxu_rx_desc *rx_desc,
6980                                        struct rtl8723au_phy_stats *phy_stats)
6981 {
6982         if (phy_stats->sgi_en)
6983                 rx_status->flag |= RX_FLAG_SHORT_GI;
6984
6985         if (rx_desc->rxmcs < DESC_RATE_6M) {
6986                 /*
6987                  * Handle PHY stats for CCK rates
6988                  */
6989                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
6990
6991                 switch (cck_agc_rpt & 0xc0) {
6992                 case 0xc0:
6993                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
6994                         break;
6995                 case 0x80:
6996                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
6997                         break;
6998                 case 0x40:
6999                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7000                         break;
7001                 case 0x00:
7002                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7003                         break;
7004                 }
7005         } else {
7006                 rx_status->signal =
7007                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7008         }
7009 }
7010
7011 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7012 {
7013         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7014         unsigned long flags;
7015
7016         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7017
7018         list_for_each_entry_safe(rx_urb, tmp,
7019                                  &priv->rx_urb_pending_list, list) {
7020                 list_del(&rx_urb->list);
7021                 priv->rx_urb_pending_count--;
7022                 usb_free_urb(&rx_urb->urb);
7023         }
7024
7025         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7026 }
7027
7028 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7029                                   struct rtl8xxxu_rx_urb *rx_urb)
7030 {
7031         struct sk_buff *skb;
7032         unsigned long flags;
7033         int pending = 0;
7034
7035         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7036
7037         if (!priv->shutdown) {
7038                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7039                 priv->rx_urb_pending_count++;
7040                 pending = priv->rx_urb_pending_count;
7041         } else {
7042                 skb = (struct sk_buff *)rx_urb->urb.context;
7043                 dev_kfree_skb(skb);
7044                 usb_free_urb(&rx_urb->urb);
7045         }
7046
7047         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7048
7049         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7050                 schedule_work(&priv->rx_urb_wq);
7051 }
7052
7053 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7054 {
7055         struct rtl8xxxu_priv *priv;
7056         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7057         struct list_head local;
7058         struct sk_buff *skb;
7059         unsigned long flags;
7060         int ret;
7061
7062         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7063         INIT_LIST_HEAD(&local);
7064
7065         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7066
7067         list_splice_init(&priv->rx_urb_pending_list, &local);
7068         priv->rx_urb_pending_count = 0;
7069
7070         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7071
7072         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7073                 list_del_init(&rx_urb->list);
7074                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7075                 /*
7076                  * If out of memory or temporary error, put it back on the
7077                  * queue and try again. Otherwise the device is dead/gone
7078                  * and we should drop it.
7079                  */
7080                 switch (ret) {
7081                 case 0:
7082                         break;
7083                 case -ENOMEM:
7084                 case -EAGAIN:
7085                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
7086                         break;
7087                 default:
7088                         pr_info("failed to requeue urb %i\n", ret);
7089                         skb = (struct sk_buff *)rx_urb->urb.context;
7090                         dev_kfree_skb(skb);
7091                         usb_free_urb(&rx_urb->urb);
7092                 }
7093         }
7094 }
7095
7096 static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
7097                                    struct sk_buff *skb,
7098                                    struct ieee80211_rx_status *rx_status)
7099 {
7100         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
7101         struct rtl8723au_phy_stats *phy_stats;
7102         int drvinfo_sz, desc_shift;
7103
7104         skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
7105
7106         phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7107
7108         drvinfo_sz = rx_desc->drvinfo_sz * 8;
7109         desc_shift = rx_desc->shift;
7110         skb_pull(skb, drvinfo_sz + desc_shift);
7111
7112         if (rx_desc->phy_stats)
7113                 rtl8xxxu_rx_parse_phystats(priv, rx_status, rx_desc, phy_stats);
7114
7115         rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7116         rx_status->flag |= RX_FLAG_MACTIME_START;
7117
7118         if (!rx_desc->swdec)
7119                 rx_status->flag |= RX_FLAG_DECRYPTED;
7120         if (rx_desc->crc32)
7121                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7122         if (rx_desc->bw)
7123                 rx_status->flag |= RX_FLAG_40MHZ;
7124
7125         if (rx_desc->rxht) {
7126                 rx_status->flag |= RX_FLAG_HT;
7127                 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7128         } else {
7129                 rx_status->rate_idx = rx_desc->rxmcs;
7130         }
7131
7132         return RX_TYPE_DATA_PKT;
7133 }
7134
7135 static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
7136                                    struct sk_buff *skb,
7137                                    struct ieee80211_rx_status *rx_status)
7138 {
7139         struct rtl8723bu_rx_desc *rx_desc =
7140                 (struct rtl8723bu_rx_desc *)skb->data;
7141         struct rtl8723au_phy_stats *phy_stats;
7142         int drvinfo_sz, desc_shift;
7143         int rx_type;
7144
7145         skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
7146
7147         phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7148
7149         drvinfo_sz = rx_desc->drvinfo_sz * 8;
7150         desc_shift = rx_desc->shift;
7151         skb_pull(skb, drvinfo_sz + desc_shift);
7152
7153         rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7154         rx_status->flag |= RX_FLAG_MACTIME_START;
7155
7156         if (!rx_desc->swdec)
7157                 rx_status->flag |= RX_FLAG_DECRYPTED;
7158         if (rx_desc->crc32)
7159                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7160         if (rx_desc->bw)
7161                 rx_status->flag |= RX_FLAG_40MHZ;
7162
7163         if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7164                 rx_status->flag |= RX_FLAG_HT;
7165                 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7166         } else {
7167                 rx_status->rate_idx = rx_desc->rxmcs;
7168         }
7169
7170         if (rx_desc->rpt_sel) {
7171                 struct device *dev = &priv->udev->dev;
7172                 dev_dbg(dev, "%s: C2H packet\n", __func__);
7173                 rx_type = RX_TYPE_C2H;
7174         } else {
7175                 rx_type = RX_TYPE_DATA_PKT;
7176         }
7177
7178         return rx_type;
7179 }
7180
7181 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7182                                  struct sk_buff *skb)
7183 {
7184         struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7185         struct device *dev = &priv->udev->dev;
7186         int len;
7187
7188         len = skb->len - 2;
7189
7190         dev_info(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
7191                  c2h->id, c2h->seq, len, c2h->bt_info.response_source);
7192
7193         switch(c2h->id) {
7194         case C2H_8723B_BT_INFO:
7195                 if (c2h->bt_info.response_source >
7196                     BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
7197                         dev_info(dev, "C2H_BT_INFO WiFi only firmware\n");
7198                 else
7199                         dev_info(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7200
7201                 if (c2h->bt_info.bt_has_reset)
7202                         dev_info(dev, "BT has been reset\n");
7203                 if (c2h->bt_info.tx_rx_mask)
7204                         dev_info(dev, "BT TRx mask\n");
7205
7206                 break;
7207         case C2H_8723B_BT_MP_INFO:
7208                 dev_info(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7209                          c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
7210                 break;
7211         default:
7212                 pr_info("%s: Unhandled C2H event %02x\n", __func__, c2h->id);
7213                 break;
7214         }
7215 }
7216
7217 static void rtl8xxxu_rx_complete(struct urb *urb)
7218 {
7219         struct rtl8xxxu_rx_urb *rx_urb =
7220                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7221         struct ieee80211_hw *hw = rx_urb->hw;
7222         struct rtl8xxxu_priv *priv = hw->priv;
7223         struct sk_buff *skb = (struct sk_buff *)urb->context;
7224         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
7225         struct device *dev = &priv->udev->dev;
7226         __le32 *_rx_desc_le = (__le32 *)skb->data;
7227         u32 *_rx_desc = (u32 *)skb->data;
7228         int rx_type, i;
7229
7230         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
7231                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
7232
7233         skb_put(skb, urb->actual_length);
7234
7235         if (urb->status == 0) {
7236                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7237
7238                 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
7239
7240                 rx_status->freq = hw->conf.chandef.chan->center_freq;
7241                 rx_status->band = hw->conf.chandef.chan->band;
7242
7243                 if (rx_type == RX_TYPE_DATA_PKT)
7244                         ieee80211_rx_irqsafe(hw, skb);
7245                 else {
7246                         rtl8723bu_handle_c2h(priv, skb);
7247                         dev_kfree_skb(skb);
7248                 }
7249
7250                 skb = NULL;
7251                 rx_urb->urb.context = NULL;
7252                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7253         } else {
7254                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7255                 goto cleanup;
7256         }
7257         return;
7258
7259 cleanup:
7260         usb_free_urb(urb);
7261         dev_kfree_skb(skb);
7262         return;
7263 }
7264
7265 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7266                                   struct rtl8xxxu_rx_urb *rx_urb)
7267 {
7268         struct sk_buff *skb;
7269         int skb_size;
7270         int ret;
7271
7272         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
7273         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7274         if (!skb)
7275                 return -ENOMEM;
7276
7277         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
7278         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7279                           skb_size, rtl8xxxu_rx_complete, skb);
7280         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7281         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7282         if (ret)
7283                 usb_unanchor_urb(&rx_urb->urb);
7284         return ret;
7285 }
7286
7287 static void rtl8xxxu_int_complete(struct urb *urb)
7288 {
7289         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7290         struct device *dev = &priv->udev->dev;
7291         int ret;
7292
7293         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7294         if (urb->status == 0) {
7295                 usb_anchor_urb(urb, &priv->int_anchor);
7296                 ret = usb_submit_urb(urb, GFP_ATOMIC);
7297                 if (ret)
7298                         usb_unanchor_urb(urb);
7299         } else {
7300                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7301         }
7302 }
7303
7304
7305 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7306 {
7307         struct rtl8xxxu_priv *priv = hw->priv;
7308         struct urb *urb;
7309         u32 val32;
7310         int ret;
7311
7312         urb = usb_alloc_urb(0, GFP_KERNEL);
7313         if (!urb)
7314                 return -ENOMEM;
7315
7316         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7317                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
7318                          rtl8xxxu_int_complete, priv, 1);
7319         usb_anchor_urb(urb, &priv->int_anchor);
7320         ret = usb_submit_urb(urb, GFP_KERNEL);
7321         if (ret) {
7322                 usb_unanchor_urb(urb);
7323                 goto error;
7324         }
7325
7326         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7327         val32 |= USB_HIMR_CPWM;
7328         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7329
7330 error:
7331         return ret;
7332 }
7333
7334 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7335                                   struct ieee80211_vif *vif)
7336 {
7337         struct rtl8xxxu_priv *priv = hw->priv;
7338         int ret;
7339         u8 val8;
7340
7341         switch (vif->type) {
7342         case NL80211_IFTYPE_STATION:
7343                 rtl8723a_stop_tx_beacon(priv);
7344
7345                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7346                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7347                         BEACON_DISABLE_TSF_UPDATE;
7348                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7349                 ret = 0;
7350                 break;
7351         default:
7352                 ret = -EOPNOTSUPP;
7353         }
7354
7355         rtl8xxxu_set_linktype(priv, vif->type);
7356
7357         return ret;
7358 }
7359
7360 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7361                                       struct ieee80211_vif *vif)
7362 {
7363         struct rtl8xxxu_priv *priv = hw->priv;
7364
7365         dev_dbg(&priv->udev->dev, "%s\n", __func__);
7366 }
7367
7368 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7369 {
7370         struct rtl8xxxu_priv *priv = hw->priv;
7371         struct device *dev = &priv->udev->dev;
7372         u16 val16;
7373         int ret = 0, channel;
7374         bool ht40;
7375
7376         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7377                 dev_info(dev,
7378                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
7379                          __func__, hw->conf.chandef.chan->hw_value,
7380                          changed, hw->conf.chandef.width);
7381
7382         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7383                 val16 = ((hw->conf.long_frame_max_tx_count <<
7384                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7385                         ((hw->conf.short_frame_max_tx_count <<
7386                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7387                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7388         }
7389
7390         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7391                 switch (hw->conf.chandef.width) {
7392                 case NL80211_CHAN_WIDTH_20_NOHT:
7393                 case NL80211_CHAN_WIDTH_20:
7394                         ht40 = false;
7395                         break;
7396                 case NL80211_CHAN_WIDTH_40:
7397                         ht40 = true;
7398                         break;
7399                 default:
7400                         ret = -ENOTSUPP;
7401                         goto exit;
7402                 }
7403
7404                 channel = hw->conf.chandef.chan->hw_value;
7405
7406                 rtl8723a_set_tx_power(priv, channel, ht40);
7407
7408                 priv->fops->config_channel(hw);
7409         }
7410
7411 exit:
7412         return ret;
7413 }
7414
7415 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7416                             struct ieee80211_vif *vif, u16 queue,
7417                             const struct ieee80211_tx_queue_params *param)
7418 {
7419         struct rtl8xxxu_priv *priv = hw->priv;
7420         struct device *dev = &priv->udev->dev;
7421         u32 val32;
7422         u8 aifs, acm_ctrl, acm_bit;
7423
7424         aifs = param->aifs;
7425
7426         val32 = aifs |
7427                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7428                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7429                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7430
7431         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7432         dev_dbg(dev,
7433                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7434                 __func__, queue, val32, param->acm, acm_ctrl);
7435
7436         switch (queue) {
7437         case IEEE80211_AC_VO:
7438                 acm_bit = ACM_HW_CTRL_VO;
7439                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7440                 break;
7441         case IEEE80211_AC_VI:
7442                 acm_bit = ACM_HW_CTRL_VI;
7443                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7444                 break;
7445         case IEEE80211_AC_BE:
7446                 acm_bit = ACM_HW_CTRL_BE;
7447                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7448                 break;
7449         case IEEE80211_AC_BK:
7450                 acm_bit = ACM_HW_CTRL_BK;
7451                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7452                 break;
7453         default:
7454                 acm_bit = 0;
7455                 break;
7456         }
7457
7458         if (param->acm)
7459                 acm_ctrl |= acm_bit;
7460         else
7461                 acm_ctrl &= ~acm_bit;
7462         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7463
7464         return 0;
7465 }
7466
7467 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7468                                       unsigned int changed_flags,
7469                                       unsigned int *total_flags, u64 multicast)
7470 {
7471         struct rtl8xxxu_priv *priv = hw->priv;
7472         u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
7473
7474         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7475                 __func__, changed_flags, *total_flags);
7476
7477         /*
7478          * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7479          */
7480
7481         if (*total_flags & FIF_FCSFAIL)
7482                 rcr |= RCR_ACCEPT_CRC32;
7483         else
7484                 rcr &= ~RCR_ACCEPT_CRC32;
7485
7486         /*
7487          * FIF_PLCPFAIL not supported?
7488          */
7489
7490         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7491                 rcr &= ~RCR_CHECK_BSSID_BEACON;
7492         else
7493                 rcr |= RCR_CHECK_BSSID_BEACON;
7494
7495         if (*total_flags & FIF_CONTROL)
7496                 rcr |= RCR_ACCEPT_CTRL_FRAME;
7497         else
7498                 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7499
7500         if (*total_flags & FIF_OTHER_BSS) {
7501                 rcr |= RCR_ACCEPT_AP;
7502                 rcr &= ~RCR_CHECK_BSSID_MATCH;
7503         } else {
7504                 rcr &= ~RCR_ACCEPT_AP;
7505                 rcr |= RCR_CHECK_BSSID_MATCH;
7506         }
7507
7508         if (*total_flags & FIF_PSPOLL)
7509                 rcr |= RCR_ACCEPT_PM;
7510         else
7511                 rcr &= ~RCR_ACCEPT_PM;
7512
7513         /*
7514          * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7515          */
7516
7517         rtl8xxxu_write32(priv, REG_RCR, rcr);
7518
7519         *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7520                          FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7521                          FIF_PROBE_REQ);
7522 }
7523
7524 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7525 {
7526         if (rts > 2347)
7527                 return -EINVAL;
7528
7529         return 0;
7530 }
7531
7532 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7533                             struct ieee80211_vif *vif,
7534                             struct ieee80211_sta *sta,
7535                             struct ieee80211_key_conf *key)
7536 {
7537         struct rtl8xxxu_priv *priv = hw->priv;
7538         struct device *dev = &priv->udev->dev;
7539         u8 mac_addr[ETH_ALEN];
7540         u8 val8;
7541         u16 val16;
7542         u32 val32;
7543         int retval = -EOPNOTSUPP;
7544
7545         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7546                 __func__, cmd, key->cipher, key->keyidx);
7547
7548         if (vif->type != NL80211_IFTYPE_STATION)
7549                 return -EOPNOTSUPP;
7550
7551         if (key->keyidx > 3)
7552                 return -EOPNOTSUPP;
7553
7554         switch (key->cipher) {
7555         case WLAN_CIPHER_SUITE_WEP40:
7556         case WLAN_CIPHER_SUITE_WEP104:
7557
7558                 break;
7559         case WLAN_CIPHER_SUITE_CCMP:
7560                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7561                 break;
7562         case WLAN_CIPHER_SUITE_TKIP:
7563                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7564         default:
7565                 return -EOPNOTSUPP;
7566         }
7567
7568         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7569                 dev_dbg(dev, "%s: pairwise key\n", __func__);
7570                 ether_addr_copy(mac_addr, sta->addr);
7571         } else {
7572                 dev_dbg(dev, "%s: group key\n", __func__);
7573                 eth_broadcast_addr(mac_addr);
7574         }
7575
7576         val16 = rtl8xxxu_read16(priv, REG_CR);
7577         val16 |= CR_SECURITY_ENABLE;
7578         rtl8xxxu_write16(priv, REG_CR, val16);
7579
7580         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7581                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7582         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7583         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7584
7585         switch (cmd) {
7586         case SET_KEY:
7587                 key->hw_key_idx = key->keyidx;
7588                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7589                 rtl8xxxu_cam_write(priv, key, mac_addr);
7590                 retval = 0;
7591                 break;
7592         case DISABLE_KEY:
7593                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7594                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7595                         key->keyidx << CAM_CMD_KEY_SHIFT;
7596                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7597                 retval = 0;
7598                 break;
7599         default:
7600                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
7601         }
7602
7603         return retval;
7604 }
7605
7606 static int
7607 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7608                       struct ieee80211_ampdu_params *params)
7609 {
7610         struct rtl8xxxu_priv *priv = hw->priv;
7611         struct device *dev = &priv->udev->dev;
7612         u8 ampdu_factor, ampdu_density;
7613         struct ieee80211_sta *sta = params->sta;
7614         enum ieee80211_ampdu_mlme_action action = params->action;
7615
7616         switch (action) {
7617         case IEEE80211_AMPDU_TX_START:
7618                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
7619                 ampdu_factor = sta->ht_cap.ampdu_factor;
7620                 ampdu_density = sta->ht_cap.ampdu_density;
7621                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
7622                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
7623                 dev_dbg(dev,
7624                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7625                         ampdu_factor, ampdu_density);
7626                 break;
7627         case IEEE80211_AMPDU_TX_STOP_FLUSH:
7628                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
7629                 rtl8xxxu_set_ampdu_factor(priv, 0);
7630                 rtl8xxxu_set_ampdu_min_space(priv, 0);
7631                 break;
7632         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7633                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
7634                          __func__);
7635                 rtl8xxxu_set_ampdu_factor(priv, 0);
7636                 rtl8xxxu_set_ampdu_min_space(priv, 0);
7637                 break;
7638         case IEEE80211_AMPDU_RX_START:
7639                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
7640                 break;
7641         case IEEE80211_AMPDU_RX_STOP:
7642                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
7643                 break;
7644         default:
7645                 break;
7646         }
7647         return 0;
7648 }
7649
7650 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7651 {
7652         struct rtl8xxxu_priv *priv = hw->priv;
7653         struct rtl8xxxu_rx_urb *rx_urb;
7654         struct rtl8xxxu_tx_urb *tx_urb;
7655         unsigned long flags;
7656         int ret, i;
7657
7658         ret = 0;
7659
7660         init_usb_anchor(&priv->rx_anchor);
7661         init_usb_anchor(&priv->tx_anchor);
7662         init_usb_anchor(&priv->int_anchor);
7663
7664         rtl8723a_enable_rf(priv);
7665         if (priv->usb_interrupts) {
7666                 ret = rtl8xxxu_submit_int_urb(hw);
7667                 if (ret)
7668                         goto exit;
7669         }
7670
7671         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7672                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7673                 if (!tx_urb) {
7674                         if (!i)
7675                                 ret = -ENOMEM;
7676
7677                         goto error_out;
7678                 }
7679                 usb_init_urb(&tx_urb->urb);
7680                 INIT_LIST_HEAD(&tx_urb->list);
7681                 tx_urb->hw = hw;
7682                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7683                 priv->tx_urb_free_count++;
7684         }
7685
7686         priv->tx_stopped = false;
7687
7688         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7689         priv->shutdown = false;
7690         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7691
7692         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7693                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7694                 if (!rx_urb) {
7695                         if (!i)
7696                                 ret = -ENOMEM;
7697
7698                         goto error_out;
7699                 }
7700                 usb_init_urb(&rx_urb->urb);
7701                 INIT_LIST_HEAD(&rx_urb->list);
7702                 rx_urb->hw = hw;
7703
7704                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7705         }
7706 exit:
7707         /*
7708          * Accept all data and mgmt frames
7709          */
7710         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7711         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7712
7713         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
7714
7715         return ret;
7716
7717 error_out:
7718         rtl8xxxu_free_tx_resources(priv);
7719         /*
7720          * Disable all data and mgmt frames
7721          */
7722         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7723         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7724
7725         return ret;
7726 }
7727
7728 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7729 {
7730         struct rtl8xxxu_priv *priv = hw->priv;
7731         unsigned long flags;
7732
7733         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7734
7735         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7736         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7737
7738         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7739         priv->shutdown = true;
7740         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7741
7742         usb_kill_anchored_urbs(&priv->rx_anchor);
7743         usb_kill_anchored_urbs(&priv->tx_anchor);
7744         if (priv->usb_interrupts)
7745                 usb_kill_anchored_urbs(&priv->int_anchor);
7746
7747         rtl8723a_disable_rf(priv);
7748
7749         /*
7750          * Disable interrupts
7751          */
7752         if (priv->usb_interrupts)
7753                 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7754
7755         rtl8xxxu_free_rx_resources(priv);
7756         rtl8xxxu_free_tx_resources(priv);
7757 }
7758
7759 static const struct ieee80211_ops rtl8xxxu_ops = {
7760         .tx = rtl8xxxu_tx,
7761         .add_interface = rtl8xxxu_add_interface,
7762         .remove_interface = rtl8xxxu_remove_interface,
7763         .config = rtl8xxxu_config,
7764         .conf_tx = rtl8xxxu_conf_tx,
7765         .bss_info_changed = rtl8xxxu_bss_info_changed,
7766         .configure_filter = rtl8xxxu_configure_filter,
7767         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7768         .start = rtl8xxxu_start,
7769         .stop = rtl8xxxu_stop,
7770         .sw_scan_start = rtl8xxxu_sw_scan_start,
7771         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7772         .set_key = rtl8xxxu_set_key,
7773         .ampdu_action = rtl8xxxu_ampdu_action,
7774 };
7775
7776 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7777                               struct usb_interface *interface)
7778 {
7779         struct usb_interface_descriptor *interface_desc;
7780         struct usb_host_interface *host_interface;
7781         struct usb_endpoint_descriptor *endpoint;
7782         struct device *dev = &priv->udev->dev;
7783         int i, j = 0, endpoints;
7784         u8 dir, xtype, num;
7785         int ret = 0;
7786
7787         host_interface = &interface->altsetting[0];
7788         interface_desc = &host_interface->desc;
7789         endpoints = interface_desc->bNumEndpoints;
7790
7791         for (i = 0; i < endpoints; i++) {
7792                 endpoint = &host_interface->endpoint[i].desc;
7793
7794                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7795                 num = usb_endpoint_num(endpoint);
7796                 xtype = usb_endpoint_type(endpoint);
7797                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7798                         dev_dbg(dev,
7799                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7800                                 __func__, dir, num, xtype);
7801                 if (usb_endpoint_dir_in(endpoint) &&
7802                     usb_endpoint_xfer_bulk(endpoint)) {
7803                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7804                                 dev_dbg(dev, "%s: in endpoint num %i\n",
7805                                         __func__, num);
7806
7807                         if (priv->pipe_in) {
7808                                 dev_warn(dev,
7809                                          "%s: Too many IN pipes\n", __func__);
7810                                 ret = -EINVAL;
7811                                 goto exit;
7812                         }
7813
7814                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7815                 }
7816
7817                 if (usb_endpoint_dir_in(endpoint) &&
7818                     usb_endpoint_xfer_int(endpoint)) {
7819                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7820                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7821                                         __func__, num);
7822
7823                         if (priv->pipe_interrupt) {
7824                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7825                                          __func__);
7826                                 ret = -EINVAL;
7827                                 goto exit;
7828                         }
7829
7830                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7831                 }
7832
7833                 if (usb_endpoint_dir_out(endpoint) &&
7834                     usb_endpoint_xfer_bulk(endpoint)) {
7835                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7836                                 dev_dbg(dev, "%s: out endpoint num %i\n",
7837                                         __func__, num);
7838                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7839                                 dev_warn(dev,
7840                                          "%s: Too many OUT pipes\n", __func__);
7841                                 ret = -EINVAL;
7842                                 goto exit;
7843                         }
7844                         priv->out_ep[j++] = num;
7845                 }
7846         }
7847 exit:
7848         priv->nr_out_eps = j;
7849         return ret;
7850 }
7851
7852 static int rtl8xxxu_probe(struct usb_interface *interface,
7853                           const struct usb_device_id *id)
7854 {
7855         struct rtl8xxxu_priv *priv;
7856         struct ieee80211_hw *hw;
7857         struct usb_device *udev;
7858         struct ieee80211_supported_band *sband;
7859         int ret = 0;
7860         int untested = 1;
7861
7862         udev = usb_get_dev(interface_to_usbdev(interface));
7863
7864         switch (id->idVendor) {
7865         case USB_VENDOR_ID_REALTEK:
7866                 switch(id->idProduct) {
7867                 case 0x1724:
7868                 case 0x8176:
7869                 case 0x8178:
7870                 case 0x817f:
7871                         untested = 0;
7872                         break;
7873                 }
7874                 break;
7875         case 0x7392:
7876                 if (id->idProduct == 0x7811)
7877                         untested = 0;
7878                 break;
7879         default:
7880                 break;
7881         }
7882
7883         if (untested) {
7884                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
7885                 dev_info(&udev->dev,
7886                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7887                          id->idVendor, id->idProduct);
7888                 dev_info(&udev->dev,
7889                          "Please report results to Jes.Sorensen@gmail.com\n");
7890         }
7891
7892         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7893         if (!hw) {
7894                 ret = -ENOMEM;
7895                 goto exit;
7896         }
7897
7898         priv = hw->priv;
7899         priv->hw = hw;
7900         priv->udev = udev;
7901         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7902         mutex_init(&priv->usb_buf_mutex);
7903         mutex_init(&priv->h2c_mutex);
7904         INIT_LIST_HEAD(&priv->tx_urb_free_list);
7905         spin_lock_init(&priv->tx_urb_lock);
7906         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7907         spin_lock_init(&priv->rx_urb_lock);
7908         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7909
7910         usb_set_intfdata(interface, hw);
7911
7912         ret = rtl8xxxu_parse_usb(priv, interface);
7913         if (ret)
7914                 goto exit;
7915
7916         ret = rtl8xxxu_identify_chip(priv);
7917         if (ret) {
7918                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7919                 goto exit;
7920         }
7921
7922         ret = rtl8xxxu_read_efuse(priv);
7923         if (ret) {
7924                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7925                 goto exit;
7926         }
7927
7928         ret = priv->fops->parse_efuse(priv);
7929         if (ret) {
7930                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7931                 goto exit;
7932         }
7933
7934         rtl8xxxu_print_chipinfo(priv);
7935
7936         ret = priv->fops->load_firmware(priv);
7937         if (ret) {
7938                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
7939                 goto exit;
7940         }
7941
7942         ret = rtl8xxxu_init_device(hw);
7943
7944         hw->wiphy->max_scan_ssids = 1;
7945         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
7946         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
7947         hw->queues = 4;
7948
7949         sband = &rtl8xxxu_supported_band;
7950         sband->ht_cap.ht_supported = true;
7951         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7952         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7953         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7954         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7955         sband->ht_cap.mcs.rx_mask[0] = 0xff;
7956         sband->ht_cap.mcs.rx_mask[4] = 0x01;
7957         if (priv->rf_paths > 1) {
7958                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
7959                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7960         }
7961         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7962         /*
7963          * Some APs will negotiate HT20_40 in a noisy environment leading
7964          * to miserable performance. Rather than defaulting to this, only
7965          * enable it if explicitly requested at module load time.
7966          */
7967         if (rtl8xxxu_ht40_2g) {
7968                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7969                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7970         }
7971         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
7972
7973         hw->wiphy->rts_threshold = 2347;
7974
7975         SET_IEEE80211_DEV(priv->hw, &interface->dev);
7976         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
7977
7978         hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
7979         ieee80211_hw_set(hw, SIGNAL_DBM);
7980         /*
7981          * The firmware handles rate control
7982          */
7983         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7984         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7985
7986         ret = ieee80211_register_hw(priv->hw);
7987         if (ret) {
7988                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
7989                         __func__, ret);
7990                 goto exit;
7991         }
7992
7993 exit:
7994         if (ret < 0)
7995                 usb_put_dev(udev);
7996         return ret;
7997 }
7998
7999 static void rtl8xxxu_disconnect(struct usb_interface *interface)
8000 {
8001         struct rtl8xxxu_priv *priv;
8002         struct ieee80211_hw *hw;
8003
8004         hw = usb_get_intfdata(interface);
8005         priv = hw->priv;
8006
8007         rtl8xxxu_disable_device(hw);
8008         usb_set_intfdata(interface, NULL);
8009
8010         dev_info(&priv->udev->dev, "disconnecting\n");
8011
8012         ieee80211_unregister_hw(hw);
8013
8014         kfree(priv->fw_data);
8015         mutex_destroy(&priv->usb_buf_mutex);
8016         mutex_destroy(&priv->h2c_mutex);
8017
8018         usb_put_dev(priv->udev);
8019         ieee80211_free_hw(hw);
8020 }
8021
8022 static struct rtl8xxxu_fileops rtl8723au_fops = {
8023         .parse_efuse = rtl8723au_parse_efuse,
8024         .load_firmware = rtl8723au_load_firmware,
8025         .power_on = rtl8723au_power_on,
8026         .llt_init = rtl8xxxu_init_llt_table,
8027         .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8028         .config_channel = rtl8723au_config_channel,
8029         .parse_rx_desc = rtl8723au_parse_rx_desc,
8030         .writeN_block_size = 1024,
8031         .mbox_ext_reg = REG_HMBOX_EXT_0,
8032         .mbox_ext_width = 2,
8033         .adda_1t_init = 0x0b1b25a0,
8034         .adda_1t_path_on = 0x0bdb25a0,
8035         .adda_2t_path_on_a = 0x04db25a4,
8036         .adda_2t_path_on_b = 0x0b1b25a4,
8037 };
8038
8039 static struct rtl8xxxu_fileops rtl8723bu_fops = {
8040         .parse_efuse = rtl8723bu_parse_efuse,
8041         .load_firmware = rtl8723bu_load_firmware,
8042         .power_on = rtl8723bu_power_on,
8043         .llt_init = rtl8xxxu_auto_llt_table,
8044         .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
8045         .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8046         .config_channel = rtl8723bu_config_channel,
8047         .init_bt = rtl8723bu_init_bt,
8048         .parse_rx_desc = rtl8723bu_parse_rx_desc,
8049         .init_aggregation = rtl8723bu_init_aggregation,
8050         .init_statistics = rtl8723bu_init_statistics,
8051         .writeN_block_size = 1024,
8052         .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8053         .mbox_ext_width = 4,
8054         .has_s0s1 = 1,
8055         .adda_1t_init = 0x01c00014,
8056         .adda_1t_path_on = 0x01c00014,
8057         .adda_2t_path_on_a = 0x01c00014,
8058         .adda_2t_path_on_b = 0x01c00014,
8059 };
8060
8061 #ifdef CONFIG_RTL8XXXU_UNTESTED
8062
8063 static struct rtl8xxxu_fileops rtl8192cu_fops = {
8064         .parse_efuse = rtl8192cu_parse_efuse,
8065         .load_firmware = rtl8192cu_load_firmware,
8066         .power_on = rtl8192cu_power_on,
8067         .llt_init = rtl8xxxu_init_llt_table,
8068         .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
8069         .config_channel = rtl8723au_config_channel,
8070         .parse_rx_desc = rtl8723au_parse_rx_desc,
8071         .writeN_block_size = 128,
8072         .mbox_ext_reg = REG_HMBOX_EXT_0,
8073         .mbox_ext_width = 2,
8074         .adda_1t_init = 0x0b1b25a0,
8075         .adda_1t_path_on = 0x0bdb25a0,
8076         .adda_2t_path_on_a = 0x04db25a4,
8077         .adda_2t_path_on_b = 0x0b1b25a4,
8078 };
8079
8080 #endif
8081
8082 static struct rtl8xxxu_fileops rtl8192eu_fops = {
8083         .parse_efuse = rtl8192eu_parse_efuse,
8084         .load_firmware = rtl8192eu_load_firmware,
8085         .power_on = rtl8192eu_power_on,
8086         .llt_init = rtl8xxxu_auto_llt_table,
8087         .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
8088         .config_channel = rtl8723bu_config_channel,
8089         .parse_rx_desc = rtl8723bu_parse_rx_desc,
8090         .writeN_block_size = 128,
8091         .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8092         .mbox_ext_width = 4,
8093         .has_s0s1 = 1,
8094         .adda_1t_init = 0x0fc01616,
8095         .adda_1t_path_on = 0x0fc01616,
8096         .adda_2t_path_on_a = 0x0fc01616,
8097         .adda_2t_path_on_b = 0x0fc01616,
8098 };
8099
8100 static struct usb_device_id dev_table[] = {
8101 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8102         .driver_info = (unsigned long)&rtl8723au_fops},
8103 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8104         .driver_info = (unsigned long)&rtl8723au_fops},
8105 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8106         .driver_info = (unsigned long)&rtl8723au_fops},
8107 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8108         .driver_info = (unsigned long)&rtl8192eu_fops},
8109 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8110         .driver_info = (unsigned long)&rtl8723bu_fops},
8111 #ifdef CONFIG_RTL8XXXU_UNTESTED
8112 /* Still supported by rtlwifi */
8113 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8114         .driver_info = (unsigned long)&rtl8192cu_fops},
8115 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8116         .driver_info = (unsigned long)&rtl8192cu_fops},
8117 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8118         .driver_info = (unsigned long)&rtl8192cu_fops},
8119 /* Tested by Larry Finger */
8120 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8121         .driver_info = (unsigned long)&rtl8192cu_fops},
8122 /* Currently untested 8188 series devices */
8123 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8124         .driver_info = (unsigned long)&rtl8192cu_fops},
8125 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8126         .driver_info = (unsigned long)&rtl8192cu_fops},
8127 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8128         .driver_info = (unsigned long)&rtl8192cu_fops},
8129 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8130         .driver_info = (unsigned long)&rtl8192cu_fops},
8131 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8132         .driver_info = (unsigned long)&rtl8192cu_fops},
8133 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8134         .driver_info = (unsigned long)&rtl8192cu_fops},
8135 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8136         .driver_info = (unsigned long)&rtl8192cu_fops},
8137 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8138         .driver_info = (unsigned long)&rtl8192cu_fops},
8139 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8140         .driver_info = (unsigned long)&rtl8192cu_fops},
8141 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8142         .driver_info = (unsigned long)&rtl8192cu_fops},
8143 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8144         .driver_info = (unsigned long)&rtl8192cu_fops},
8145 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8146         .driver_info = (unsigned long)&rtl8192cu_fops},
8147 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8148         .driver_info = (unsigned long)&rtl8192cu_fops},
8149 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8150         .driver_info = (unsigned long)&rtl8192cu_fops},
8151 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8152         .driver_info = (unsigned long)&rtl8192cu_fops},
8153 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8154         .driver_info = (unsigned long)&rtl8192cu_fops},
8155 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8156         .driver_info = (unsigned long)&rtl8192cu_fops},
8157 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8158         .driver_info = (unsigned long)&rtl8192cu_fops},
8159 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8160         .driver_info = (unsigned long)&rtl8192cu_fops},
8161 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8162         .driver_info = (unsigned long)&rtl8192cu_fops},
8163 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8164         .driver_info = (unsigned long)&rtl8192cu_fops},
8165 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8166         .driver_info = (unsigned long)&rtl8192cu_fops},
8167 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8168         .driver_info = (unsigned long)&rtl8192cu_fops},
8169 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8170         .driver_info = (unsigned long)&rtl8192cu_fops},
8171 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8172         .driver_info = (unsigned long)&rtl8192cu_fops},
8173 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8174         .driver_info = (unsigned long)&rtl8192cu_fops},
8175 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8176         .driver_info = (unsigned long)&rtl8192cu_fops},
8177 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8178         .driver_info = (unsigned long)&rtl8192cu_fops},
8179 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8180         .driver_info = (unsigned long)&rtl8192cu_fops},
8181 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8182         .driver_info = (unsigned long)&rtl8192cu_fops},
8183 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8184         .driver_info = (unsigned long)&rtl8192cu_fops},
8185 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8186         .driver_info = (unsigned long)&rtl8192cu_fops},
8187 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8188         .driver_info = (unsigned long)&rtl8192cu_fops},
8189 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8190         .driver_info = (unsigned long)&rtl8192cu_fops},
8191 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8192         .driver_info = (unsigned long)&rtl8192cu_fops},
8193 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8194         .driver_info = (unsigned long)&rtl8192cu_fops},
8195 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8196         .driver_info = (unsigned long)&rtl8192cu_fops},
8197 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8198         .driver_info = (unsigned long)&rtl8192cu_fops},
8199 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8200         .driver_info = (unsigned long)&rtl8192cu_fops},
8201 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8202         .driver_info = (unsigned long)&rtl8192cu_fops},
8203 /* Currently untested 8192 series devices */
8204 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8205         .driver_info = (unsigned long)&rtl8192cu_fops},
8206 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8207         .driver_info = (unsigned long)&rtl8192cu_fops},
8208 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8209         .driver_info = (unsigned long)&rtl8192cu_fops},
8210 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8211         .driver_info = (unsigned long)&rtl8192cu_fops},
8212 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8213         .driver_info = (unsigned long)&rtl8192cu_fops},
8214 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8215         .driver_info = (unsigned long)&rtl8192cu_fops},
8216 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8217         .driver_info = (unsigned long)&rtl8192cu_fops},
8218 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8219         .driver_info = (unsigned long)&rtl8192cu_fops},
8220 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8221         .driver_info = (unsigned long)&rtl8192cu_fops},
8222 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8223         .driver_info = (unsigned long)&rtl8192cu_fops},
8224 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8225         .driver_info = (unsigned long)&rtl8192cu_fops},
8226 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8227         .driver_info = (unsigned long)&rtl8192cu_fops},
8228 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8229         .driver_info = (unsigned long)&rtl8192cu_fops},
8230 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8231         .driver_info = (unsigned long)&rtl8192cu_fops},
8232 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8233         .driver_info = (unsigned long)&rtl8192cu_fops},
8234 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8235         .driver_info = (unsigned long)&rtl8192cu_fops},
8236 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8237         .driver_info = (unsigned long)&rtl8192cu_fops},
8238 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8239         .driver_info = (unsigned long)&rtl8192cu_fops},
8240 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8241         .driver_info = (unsigned long)&rtl8192cu_fops},
8242 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8243         .driver_info = (unsigned long)&rtl8192cu_fops},
8244 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8245         .driver_info = (unsigned long)&rtl8192cu_fops},
8246 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8247         .driver_info = (unsigned long)&rtl8192cu_fops},
8248 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8249         .driver_info = (unsigned long)&rtl8192cu_fops},
8250 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8251         .driver_info = (unsigned long)&rtl8192cu_fops},
8252 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8253         .driver_info = (unsigned long)&rtl8192cu_fops},
8254 #endif
8255 { }
8256 };
8257
8258 static struct usb_driver rtl8xxxu_driver = {
8259         .name = DRIVER_NAME,
8260         .probe = rtl8xxxu_probe,
8261         .disconnect = rtl8xxxu_disconnect,
8262         .id_table = dev_table,
8263         .disable_hub_initiated_lpm = 1,
8264 };
8265
8266 static int __init rtl8xxxu_module_init(void)
8267 {
8268         int res;
8269
8270         res = usb_register(&rtl8xxxu_driver);
8271         if (res < 0)
8272                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8273
8274         return res;
8275 }
8276
8277 static void __exit rtl8xxxu_module_exit(void)
8278 {
8279         usb_deregister(&rtl8xxxu_driver);
8280 }
8281
8282
8283 MODULE_DEVICE_TABLE(usb, dev_table);
8284
8285 module_init(rtl8xxxu_module_init);
8286 module_exit(rtl8xxxu_module_exit);