drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h

   1 /*
   2  * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of version 2 of the GNU General Public License as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11  * more details.
  12  *
  13  * Register definitions taken from original Realtek rtl8723au driver
  14  */
  15
  16 #include <asm/byteorder.h>
  17
  18 #define RTL8XXXU_DEBUG_REG_WRITE        0x01
  19 #define RTL8XXXU_DEBUG_REG_READ         0x02
  20 #define RTL8XXXU_DEBUG_RFREG_WRITE      0x04
  21 #define RTL8XXXU_DEBUG_RFREG_READ       0x08
  22 #define RTL8XXXU_DEBUG_CHANNEL          0x10
  23 #define RTL8XXXU_DEBUG_TX               0x20
  24 #define RTL8XXXU_DEBUG_TX_DUMP          0x40
  25 #define RTL8XXXU_DEBUG_RX               0x80
  26 #define RTL8XXXU_DEBUG_RX_DUMP          0x100
  27 #define RTL8XXXU_DEBUG_USB              0x200
  28 #define RTL8XXXU_DEBUG_KEY              0x400
  29 #define RTL8XXXU_DEBUG_H2C              0x800
  30 #define RTL8XXXU_DEBUG_ACTION           0x1000
  31 #define RTL8XXXU_DEBUG_EFUSE            0x2000
  32
  33 #define RTW_USB_CONTROL_MSG_TIMEOUT     500
  34 #define RTL8XXXU_MAX_REG_POLL           500
  35 #define USB_INTR_CONTENT_LENGTH         56
  36
  37 #define RTL8XXXU_OUT_ENDPOINTS          4
  38
  39 #define REALTEK_USB_READ                0xc0
  40 #define REALTEK_USB_WRITE               0x40
  41 #define REALTEK_USB_CMD_REQ             0x05
  42 #define REALTEK_USB_CMD_IDX             0x00
  43
  44 #define TX_TOTAL_PAGE_NUM               0xf8
  45 #define TX_TOTAL_PAGE_NUM_8192E         0xf3
  46 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
  47 #define TX_PAGE_NUM_PUBQ                0xe7
  48 #define TX_PAGE_NUM_HI_PQ               0x0c
  49 #define TX_PAGE_NUM_LO_PQ               0x02
  50 #define TX_PAGE_NUM_NORM_PQ             0x02
  51
  52 #define TX_PAGE_NUM_PUBQ_8192E          0xe7
  53 #define TX_PAGE_NUM_HI_PQ_8192E         0x08
  54 #define TX_PAGE_NUM_LO_PQ_8192E         0x0c
  55 #define TX_PAGE_NUM_NORM_PQ_8192E       0x00
  56
  57 #define RTL_FW_PAGE_SIZE                4096
  58 #define RTL8XXXU_FIRMWARE_POLL_MAX      1000
  59
  60 #define RTL8723A_CHANNEL_GROUPS         3
  61 #define RTL8723A_MAX_RF_PATHS           2
  62 #define RTL8723B_CHANNEL_GROUPS         6
  63 #define RTL8723B_TX_COUNT               4
  64 #define RTL8723B_MAX_RF_PATHS           4
  65 #define RTL8XXXU_MAX_CHANNEL_GROUPS     6
  66 #define RF6052_MAX_TX_PWR               0x3f
  67
  68 #define EFUSE_MAP_LEN                   512
  69 #define EFUSE_MAX_SECTION_8723A         64
  70 #define EFUSE_REAL_CONTENT_LEN_8723A    512
  71 #define EFUSE_BT_MAP_LEN_8723A          1024
  72 #define EFUSE_MAX_WORD_UNIT             4
  73
  74 enum rtl8xxxu_rtl_chip {
  75         RTL8192S = 0x81920,
  76         RTL8191S = 0x81910,
  77         RTL8192C = 0x8192c,
  78         RTL8191C = 0x8191c,
  79         RTL8188C = 0x8188c,
  80         RTL8188R = 0x81889,
  81         RTL8192D = 0x8192d,
  82         RTL8723A = 0x8723a,
  83         RTL8188E = 0x8188e,
  84         RTL8812  = 0x88120,
  85         RTL8821  = 0x88210,
  86         RTL8192E = 0x8192e,
  87         RTL8191E = 0x8191e,
  88         RTL8723B = 0x8723b,
  89         RTL8814A = 0x8814a,
  90         RTL8881A = 0x8881a,
  91         RTL8821B = 0x8821b,
  92         RTL8822B = 0x8822b,
  93         RTL8703B = 0x8703b,
  94         RTL8195A = 0x8195a,
  95         RTL8188F = 0x8188f
  96 };
  97
  98 enum rtl8xxxu_rx_type {
  99         RX_TYPE_DATA_PKT = 0,
 100         RX_TYPE_C2H = 1,
 101         RX_TYPE_ERROR = -1
 102 };
 103
 104 struct rtl8xxxu_rxdesc16 {
 105 #ifdef __LITTLE_ENDIAN
 106         u32 pktlen:14;
 107         u32 crc32:1;
 108         u32 icverr:1;
 109         u32 drvinfo_sz:4;
 110         u32 security:3;
 111         u32 qos:1;
 112         u32 shift:2;
 113         u32 phy_stats:1;
 114         u32 swdec:1;
 115         u32 ls:1;
 116         u32 fs:1;
 117         u32 eor:1;
 118         u32 own:1;
 119
 120         u32 macid:5;
 121         u32 tid:4;
 122         u32 hwrsvd:4;
 123         u32 amsdu:1;
 124         u32 paggr:1;
 125         u32 faggr:1;
 126         u32 a1fit:4;
 127         u32 a2fit:4;
 128         u32 pam:1;
 129         u32 pwr:1;
 130         u32 md:1;
 131         u32 mf:1;
 132         u32 type:2;
 133         u32 mc:1;
 134         u32 bc:1;
 135
 136         u32 seq:12;
 137         u32 frag:4;
 138         u32 pkt_cnt:8;
 139         u32 reserved:6;
 140         u32 nextind:1;
 141         u32 reserved0:1;
 142
 143         u32 rxmcs:6;
 144         u32 rxht:1;
 145         u32 gf:1;
 146         u32 splcp:1;
 147         u32 bw:1;
 148         u32 htc:1;
 149         u32 eosp:1;
 150         u32 bssidfit:2;
 151         u32 reserved1:16;
 152         u32 unicastwake:1;
 153         u32 magicwake:1;
 154
 155         u32 pattern0match:1;
 156         u32 pattern1match:1;
 157         u32 pattern2match:1;
 158         u32 pattern3match:1;
 159         u32 pattern4match:1;
 160         u32 pattern5match:1;
 161         u32 pattern6match:1;
 162         u32 pattern7match:1;
 163         u32 pattern8match:1;
 164         u32 pattern9match:1;
 165         u32 patternamatch:1;
 166         u32 patternbmatch:1;
 167         u32 patterncmatch:1;
 168         u32 reserved2:19;
 169 #else
 170         u32 own:1;
 171         u32 eor:1;
 172         u32 fs:1;
 173         u32 ls:1;
 174         u32 swdec:1;
 175         u32 phy_stats:1;
 176         u32 shift:2;
 177         u32 qos:1;
 178         u32 security:3;
 179         u32 drvinfo_sz:4;
 180         u32 icverr:1;
 181         u32 crc32:1;
 182         u32 pktlen:14;
 183
 184         u32 bc:1;
 185         u32 mc:1;
 186         u32 type:2;
 187         u32 mf:1;
 188         u32 md:1;
 189         u32 pwr:1;
 190         u32 pam:1;
 191         u32 a2fit:4;
 192         u32 a1fit:4;
 193         u32 faggr:1;
 194         u32 paggr:1;
 195         u32 amsdu:1;
 196         u32 hwrsvd:4;
 197         u32 tid:4;
 198         u32 macid:5;
 199
 200         u32 reserved0:1;
 201         u32 nextind:1;
 202         u32 reserved:6;
 203         u32 pkt_cnt:8;
 204         u32 frag:4;
 205         u32 seq:12;
 206
 207         u32 magicwake:1;
 208         u32 unicastwake:1;
 209         u32 reserved1:16;
 210         u32 bssidfit:2;
 211         u32 eosp:1;
 212         u32 htc:1;
 213         u32 bw:1;
 214         u32 splcp:1;
 215         u32 gf:1;
 216         u32 rxht:1;
 217         u32 rxmcs:6;
 218
 219         u32 reserved2:19;
 220         u32 patterncmatch:1;
 221         u32 patternbmatch:1;
 222         u32 patternamatch:1;
 223         u32 pattern9match:1;
 224         u32 pattern8match:1;
 225         u32 pattern7match:1;
 226         u32 pattern6match:1;
 227         u32 pattern5match:1;
 228         u32 pattern4match:1;
 229         u32 pattern3match:1;
 230         u32 pattern2match:1;
 231         u32 pattern1match:1;
 232         u32 pattern0match:1;
 233 #endif
 234         __le32 tsfl;
 235 #if 0
 236         u32 bassn:12;
 237         u32 bavld:1;
 238         u32 reserved3:19;
 239 #endif
 240 };
 241
 242 struct rtl8xxxu_rxdesc24 {
 243 #ifdef __LITTLE_ENDIAN
 244         u32 pktlen:14;
 245         u32 crc32:1;
 246         u32 icverr:1;
 247         u32 drvinfo_sz:4;
 248         u32 security:3;
 249         u32 qos:1;
 250         u32 shift:2;
 251         u32 phy_stats:1;
 252         u32 swdec:1;
 253         u32 ls:1;
 254         u32 fs:1;
 255         u32 eor:1;
 256         u32 own:1;
 257
 258         u32 macid:7;
 259         u32 dummy1_0:1;
 260         u32 tid:4;
 261         u32 dummy1_1:1;
 262         u32 amsdu:1;
 263         u32 rxid_match:1;
 264         u32 paggr:1;
 265         u32 a1fit:4;    /* 16 */
 266         u32 chkerr:1;
 267         u32 ipver:1;
 268         u32 tcpudp:1;
 269         u32 chkvld:1;
 270         u32 pam:1;
 271         u32 pwr:1;
 272         u32 more_data:1;
 273         u32 more_frag:1;
 274         u32 type:2;
 275         u32 mc:1;
 276         u32 bc:1;
 277
 278         u32 seq:12;
 279         u32 frag:4;
 280         u32 rx_is_qos:1;        /* 16 */
 281         u32 dummy2_0:1;
 282         u32 wlanhd_iv_len:6;
 283         u32 dummy2_1:4;
 284         u32 rpt_sel:1;
 285         u32 dummy2_2:3;
 286
 287         u32 rxmcs:7;
 288         u32 dummy3_0:3;
 289         u32 htc:1;
 290         u32 eosp:1;
 291         u32 bssidfit:2;
 292         u32 dummy3_1:2;
 293         u32 usb_agg_pktnum:8;   /* 16 */
 294         u32 dummy3_2:5;
 295         u32 pattern_match:1;
 296         u32 unicast_match:1;
 297         u32 magic_match:1;
 298
 299         u32 splcp:1;
 300         u32 ldcp:1;
 301         u32 stbc:1;
 302         u32 dummy4_0:1;
 303         u32 bw:2;
 304         u32 dummy4_1:26;
 305 #else
 306         u32 own:1;
 307         u32 eor:1;
 308         u32 fs:1;
 309         u32 ls:1;
 310         u32 swdec:1;
 311         u32 phy_stats:1;
 312         u32 shift:2;
 313         u32 qos:1;
 314         u32 security:3;
 315         u32 drvinfo_sz:4;
 316         u32 icverr:1;
 317         u32 crc32:1;
 318         u32 pktlen:14;
 319
 320         u32 bc:1;
 321         u32 mc:1;
 322         u32 type:2;
 323         u32 mf:1;
 324         u32 md:1;
 325         u32 pwr:1;
 326         u32 pam:1;
 327         u32 a2fit:4;
 328         u32 a1fit:4;
 329         u32 faggr:1;
 330         u32 paggr:1;
 331         u32 amsdu:1;
 332         u32 hwrsvd:4;
 333         u32 tid:4;
 334         u32 macid:5;
 335
 336         u32 dummy2_2:3;
 337         u32 rpt_sel:1;
 338         u32 dummy2_1:4;
 339         u32 wlanhd_iv_len:6;
 340         u32 dummy2_0:1;
 341         u32 rx_is_qos:1;
 342         u32 frag:4;             /* 16 */
 343         u32 seq:12;
 344
 345         u32 magic_match:1;
 346         u32 unicast_match:1;
 347         u32 pattern_match:1;
 348         u32 dummy3_2:5;
 349         u32 usb_agg_pktnum:8;
 350         u32 dummy3_1:2;         /* 16 */
 351         u32 bssidfit:2;
 352         u32 eosp:1;
 353         u32 htc:1;
 354         u32 dummy3_0:3;
 355         u32 rxmcs:7;
 356
 357         u32 dumm4_1:26;
 358         u32 bw:2;
 359         u32 dummy4_0:1;
 360         u32 stbc:1;
 361         u32 ldcp:1;
 362         u32 splcp:1;
 363 #endif
 364         __le32 tsfl;
 365 };
 366
 367 struct rtl8xxxu_txdesc32 {
 368         __le16 pkt_size;
 369         u8 pkt_offset;
 370         u8 txdw0;
 371         __le32 txdw1;
 372         __le32 txdw2;
 373         __le32 txdw3;
 374         __le32 txdw4;
 375         __le32 txdw5;
 376         __le32 txdw6;
 377         __le16 csum;
 378         __le16 txdw7;
 379 };
 380
 381 struct rtl8xxxu_txdesc40 {
 382         __le16 pkt_size;
 383         u8 pkt_offset;
 384         u8 txdw0;
 385         __le32 txdw1;
 386         __le32 txdw2;
 387         __le32 txdw3;
 388         __le32 txdw4;
 389         __le32 txdw5;
 390         __le32 txdw6;
 391         __le16 csum;
 392         __le16 txdw7;
 393         __le32 txdw8;
 394         __le32 txdw9;
 395 };
 396
 397 /*  CCK Rates, TxHT = 0 */
 398 #define DESC_RATE_1M                    0x00
 399 #define DESC_RATE_2M                    0x01
 400 #define DESC_RATE_5_5M                  0x02
 401 #define DESC_RATE_11M                   0x03
 402
 403 /*  OFDM Rates, TxHT = 0 */
 404 #define DESC_RATE_6M                    0x04
 405 #define DESC_RATE_9M                    0x05
 406 #define DESC_RATE_12M                   0x06
 407 #define DESC_RATE_18M                   0x07
 408 #define DESC_RATE_24M                   0x08
 409 #define DESC_RATE_36M                   0x09
 410 #define DESC_RATE_48M                   0x0a
 411 #define DESC_RATE_54M                   0x0b
 412
 413 /*  MCS Rates, TxHT = 1 */
 414 #define DESC_RATE_MCS0                  0x0c
 415 #define DESC_RATE_MCS1                  0x0d
 416 #define DESC_RATE_MCS2                  0x0e
 417 #define DESC_RATE_MCS3                  0x0f
 418 #define DESC_RATE_MCS4                  0x10
 419 #define DESC_RATE_MCS5                  0x11
 420 #define DESC_RATE_MCS6                  0x12
 421 #define DESC_RATE_MCS7                  0x13
 422 #define DESC_RATE_MCS8                  0x14
 423 #define DESC_RATE_MCS9                  0x15
 424 #define DESC_RATE_MCS10                 0x16
 425 #define DESC_RATE_MCS11                 0x17
 426 #define DESC_RATE_MCS12                 0x18
 427 #define DESC_RATE_MCS13                 0x19
 428 #define DESC_RATE_MCS14                 0x1a
 429 #define DESC_RATE_MCS15                 0x1b
 430 #define DESC_RATE_MCS15_SG              0x1c
 431 #define DESC_RATE_MCS32                 0x20
 432
 433 #define TXDESC_OFFSET_SZ                0
 434 #define TXDESC_OFFSET_SHT               16
 435 #if 0
 436 #define TXDESC_BMC                      BIT(24)
 437 #define TXDESC_LSG                      BIT(26)
 438 #define TXDESC_FSG                      BIT(27)
 439 #define TXDESC_OWN                      BIT(31)
 440 #else
 441 #define TXDESC_BROADMULTICAST           BIT(0)
 442 #define TXDESC_HTC                      BIT(1)
 443 #define TXDESC_LAST_SEGMENT             BIT(2)
 444 #define TXDESC_FIRST_SEGMENT            BIT(3)
 445 #define TXDESC_LINIP                    BIT(4)
 446 #define TXDESC_NO_ACM                   BIT(5)
 447 #define TXDESC_GF                       BIT(6)
 448 #define TXDESC_OWN                      BIT(7)
 449 #endif
 450
 451 /* Word 1 */
 452 /*
 453  * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are
 454  * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid.
 455  */
 456 #define TXDESC_PKT_OFFSET_SZ            0
 457 #define TXDESC32_AGG_ENABLE             BIT(5)
 458 #define TXDESC32_AGG_BREAK              BIT(6)
 459 #define TXDESC40_MACID_SHIFT            0
 460 #define TXDESC40_MACID_MASK             0x00f0
 461 #define TXDESC_QUEUE_SHIFT              8
 462 #define TXDESC_QUEUE_MASK               0x1f00
 463 #define TXDESC_QUEUE_BK                 0x2
 464 #define TXDESC_QUEUE_BE                 0x0
 465 #define TXDESC_QUEUE_VI                 0x5
 466 #define TXDESC_QUEUE_VO                 0x7
 467 #define TXDESC_QUEUE_BEACON             0x10
 468 #define TXDESC_QUEUE_HIGH               0x11
 469 #define TXDESC_QUEUE_MGNT               0x12
 470 #define TXDESC_QUEUE_CMD                0x13
 471 #define TXDESC_QUEUE_MAX                (TXDESC_QUEUE_CMD + 1)
 472 #define TXDESC40_RDG_NAV_EXT            BIT(13)
 473 #define TXDESC40_LSIG_TXOP_ENABLE       BIT(14)
 474 #define TXDESC40_PIFS                   BIT(15)
 475
 476 #define DESC_RATE_ID_SHIFT              16
 477 #define DESC_RATE_ID_MASK               0xf
 478 #define TXDESC_NAVUSEHDR                BIT(20)
 479 #define TXDESC_SEC_RC4                  0x00400000
 480 #define TXDESC_SEC_AES                  0x00c00000
 481 #define TXDESC_PKT_OFFSET_SHIFT         26
 482 #define TXDESC_AGG_EN                   BIT(29)
 483 #define TXDESC_HWPC                     BIT(31)
 484
 485 /* Word 2 */
 486 #define TXDESC40_PAID_SHIFT             0
 487 #define TXDESC40_PAID_MASK              0x1ff
 488 #define TXDESC40_CCA_RTS_SHIFT          10
 489 #define TXDESC40_CCA_RTS_MASK           0xc00
 490 #define TXDESC40_AGG_ENABLE             BIT(12)
 491 #define TXDESC40_RDG_ENABLE             BIT(13)
 492 #define TXDESC40_AGG_BREAK              BIT(16)
 493 #define TXDESC40_MORE_FRAG              BIT(17)
 494 #define TXDESC40_RAW                    BIT(18)
 495 #define TXDESC32_ACK_REPORT             BIT(19)
 496 #define TXDESC40_SPE_RPT                BIT(19)
 497 #define TXDESC_AMPDU_DENSITY_SHIFT      20
 498 #define TXDESC40_BT_INT                 BIT(23)
 499 #define TXDESC40_GID_SHIFT              24
 500
 501 /* Word 3 */
 502 #define TXDESC40_USE_DRIVER_RATE        BIT(8)
 503 #define TXDESC40_CTS_SELF_ENABLE        BIT(11)
 504 #define TXDESC40_RTS_CTS_ENABLE         BIT(12)
 505 #define TXDESC40_HW_RTS_ENABLE          BIT(13)
 506 #define TXDESC32_SEQ_SHIFT              16
 507 #define TXDESC32_SEQ_MASK               0x0fff0000
 508
 509 /* Word 4 */
 510 #define TXDESC32_RTS_RATE_SHIFT         0
 511 #define TXDESC32_RTS_RATE_MASK          0x3f
 512 #define TXDESC32_QOS                    BIT(6)
 513 #define TXDESC32_HW_SEQ_ENABLE          BIT(7)
 514 #define TXDESC32_USE_DRIVER_RATE        BIT(8)
 515 #define TXDESC_DISABLE_DATA_FB          BIT(10)
 516 #define TXDESC32_CTS_SELF_ENABLE        BIT(11)
 517 #define TXDESC32_RTS_CTS_ENABLE         BIT(12)
 518 #define TXDESC32_HW_RTS_ENABLE          BIT(13)
 519 #define TXDESC_PRIME_CH_OFF_LOWER       BIT(20)
 520 #define TXDESC_PRIME_CH_OFF_UPPER       BIT(21)
 521 #define TXDESC32_SHORT_PREAMBLE         BIT(24)
 522 #define TXDESC_DATA_BW                  BIT(25)
 523 #define TXDESC_RTS_DATA_BW              BIT(27)
 524 #define TXDESC_RTS_PRIME_CH_OFF_LOWER   BIT(28)
 525 #define TXDESC_RTS_PRIME_CH_OFF_UPPER   BIT(29)
 526 #define TXDESC40_DATA_RATE_FB_SHIFT     8
 527 #define TXDESC40_DATA_RATE_FB_MASK      0x00001f00
 528 #define TXDESC40_RETRY_LIMIT_ENABLE     BIT(17)
 529 #define TXDESC40_RETRY_LIMIT_SHIFT      18
 530 #define TXDESC40_RETRY_LIMIT_MASK       0x00fc0000
 531 #define TXDESC40_RTS_RATE_SHIFT         24
 532 #define TXDESC40_RTS_RATE_MASK          0x3f000000
 533
 534 /* Word 5 */
 535 #define TXDESC40_SHORT_PREAMBLE         BIT(4)
 536 #define TXDESC32_SHORT_GI               BIT(6)
 537 #define TXDESC_CCX_TAG                  BIT(7)
 538 #define TXDESC32_RETRY_LIMIT_ENABLE     BIT(17)
 539 #define TXDESC32_RETRY_LIMIT_SHIFT      18
 540 #define TXDESC32_RETRY_LIMIT_MASK       0x00fc0000
 541
 542 /* Word 6 */
 543 #define TXDESC_MAX_AGG_SHIFT            11
 544
 545 /* Word 8 */
 546 #define TXDESC40_HW_SEQ_ENABLE          BIT(15)
 547
 548 /* Word 9 */
 549 #define TXDESC40_SEQ_SHIFT              12
 550 #define TXDESC40_SEQ_MASK               0x00fff000
 551
 552 struct phy_rx_agc_info {
 553 #ifdef __LITTLE_ENDIAN
 554         u8      gain:7, trsw:1;
 555 #else
 556         u8      trsw:1, gain:7;
 557 #endif
 558 };
 559
 560 struct rtl8723au_phy_stats {
 561         struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS];
 562         u8      ch_corr[RTL8723A_MAX_RF_PATHS];
 563         u8      cck_sig_qual_ofdm_pwdb_all;
 564         u8      cck_agc_rpt_ofdm_cfosho_a;
 565         u8      cck_rpt_b_ofdm_cfosho_b;
 566         u8      reserved_1;
 567         u8      noise_power_db_msb;
 568         u8      path_cfotail[RTL8723A_MAX_RF_PATHS];
 569         u8      pcts_mask[RTL8723A_MAX_RF_PATHS];
 570         s8      stream_rxevm[RTL8723A_MAX_RF_PATHS];
 571         u8      path_rxsnr[RTL8723A_MAX_RF_PATHS];
 572         u8      noise_power_db_lsb;
 573         u8      reserved_2[3];
 574         u8      stream_csi[RTL8723A_MAX_RF_PATHS];
 575         u8      stream_target_csi[RTL8723A_MAX_RF_PATHS];
 576         s8      sig_evm;
 577         u8      reserved_3;
 578
 579 #ifdef __LITTLE_ENDIAN
 580         u8      antsel_rx_keep_2:1;     /* ex_intf_flg:1; */
 581         u8      sgi_en:1;
 582         u8      rxsc:2;
 583         u8      idle_long:1;
 584         u8      r_ant_train_en:1;
 585         u8      antenna_select_b:1;
 586         u8      antenna_select:1;
 587 #else   /*  _BIG_ENDIAN_ */
 588         u8      antenna_select:1;
 589         u8      antenna_select_b:1;
 590         u8      r_ant_train_en:1;
 591         u8      idle_long:1;
 592         u8      rxsc:2;
 593         u8      sgi_en:1;
 594         u8      antsel_rx_keep_2:1;     /* ex_intf_flg:1; */
 595 #endif
 596 };
 597
 598 /*
 599  * Regs to backup
 600  */
 601 #define RTL8XXXU_ADDA_REGS              16
 602 #define RTL8XXXU_MAC_REGS               4
 603 #define RTL8XXXU_BB_REGS                9
 604
 605 struct rtl8xxxu_firmware_header {
 606         __le16  signature;              /*  92C0: test chip; 92C,
 607                                             88C0: test chip;
 608                                             88C1: MP A-cut;
 609                                             92C1: MP A-cut */
 610         u8      category;               /*  AP/NIC and USB/PCI */
 611         u8      function;
 612
 613         __le16  major_version;          /*  FW Version */
 614         u8      minor_version;          /*  FW Subversion, default 0x00 */
 615         u8      reserved1;
 616
 617         u8      month;                  /*  Release time Month field */
 618         u8      date;                   /*  Release time Date field */
 619         u8      hour;                   /*  Release time Hour field */
 620         u8      minute;                 /*  Release time Minute field */
 621
 622         __le16  ramcodesize;            /*  Size of RAM code */
 623         u16     reserved2;
 624
 625         __le32  svn_idx;                /*  SVN entry index */
 626         u32     reserved3;
 627
 628         u32     reserved4;
 629         u32     reserved5;
 630
 631         u8      data[0];
 632 };
 633
 634 /*
 635  * 8723au/8192cu/8188ru required base power index offset tables.
 636  */
 637 struct rtl8xxxu_power_base {
 638         u32 reg_0e00;
 639         u32 reg_0e04;
 640         u32 reg_0e08;
 641         u32 reg_086c;
 642
 643         u32 reg_0e10;
 644         u32 reg_0e14;
 645         u32 reg_0e18;
 646         u32 reg_0e1c;
 647
 648         u32 reg_0830;
 649         u32 reg_0834;
 650         u32 reg_0838;
 651         u32 reg_086c_2;
 652
 653         u32 reg_083c;
 654         u32 reg_0848;
 655         u32 reg_084c;
 656         u32 reg_0868;
 657 };
 658
 659 /*
 660  * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
 661  */
 662 struct rtl8723au_idx {
 663 #ifdef __LITTLE_ENDIAN
 664         int     a:4;
 665         int     b:4;
 666 #else
 667         int     b:4;
 668         int     a:4;
 669 #endif
 670 } __attribute__((packed));
 671
 672 struct rtl8723au_efuse {
 673         __le16 rtl_id;
 674         u8 res0[0xe];
 675         u8 cck_tx_power_index_A[3];     /* 0x10 */
 676         u8 cck_tx_power_index_B[3];
 677         u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */
 678         u8 ht40_1s_tx_power_index_B[3];
 679         /*
 680          * The following entries are half-bytes split as:
 681          * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
 682          */
 683         struct rtl8723au_idx ht20_tx_power_index_diff[3];
 684         struct rtl8723au_idx ofdm_tx_power_index_diff[3];
 685         struct rtl8723au_idx ht40_max_power_offset[3];
 686         struct rtl8723au_idx ht20_max_power_offset[3];
 687         u8 channel_plan;                /* 0x28 */
 688         u8 tssi_a;
 689         u8 thermal_meter;
 690         u8 rf_regulatory;
 691         u8 rf_option_2;
 692         u8 rf_option_3;
 693         u8 rf_option_4;
 694         u8 res7;
 695         u8 version                      /* 0x30 */;
 696         u8 customer_id_major;
 697         u8 customer_id_minor;
 698         u8 xtal_k;
 699         u8 chipset;                     /* 0x34 */
 700         u8 res8[0x82];
 701         u8 vid;                         /* 0xb7 */
 702         u8 res9;
 703         u8 pid;                         /* 0xb9 */
 704         u8 res10[0x0c];
 705         u8 mac_addr[ETH_ALEN];          /* 0xc6 */
 706         u8 res11[2];
 707         u8 vendor_name[7];
 708         u8 res12[2];
 709         u8 device_name[0x29];           /* 0xd7 */
 710 };
 711
 712 struct rtl8192cu_efuse {
 713         __le16 rtl_id;
 714         __le16 hpon;
 715         u8 res0[2];
 716         __le16 clk;
 717         __le16 testr;
 718         __le16 vid;
 719         __le16 did;
 720         __le16 svid;
 721         __le16 smid;                                            /* 0x10 */
 722         u8 res1[4];
 723         u8 mac_addr[ETH_ALEN];                                  /* 0x16 */
 724         u8 res2[2];
 725         u8 vendor_name[7];
 726         u8 res3[3];
 727         u8 device_name[0x14];                                   /* 0x28 */
 728         u8 res4[0x1e];                                          /* 0x3c */
 729         u8 cck_tx_power_index_A[3];                             /* 0x5a */
 730         u8 cck_tx_power_index_B[3];
 731         u8 ht40_1s_tx_power_index_A[3];                         /* 0x60 */
 732         u8 ht40_1s_tx_power_index_B[3];
 733         /*
 734          * The following entries are half-bytes split as:
 735          * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
 736          */
 737         struct rtl8723au_idx ht40_2s_tx_power_index_diff[3];
 738         struct rtl8723au_idx ht20_tx_power_index_diff[3];       /* 0x69 */
 739         struct rtl8723au_idx ofdm_tx_power_index_diff[3];
 740         struct rtl8723au_idx ht40_max_power_offset[3];          /* 0x6f */
 741         struct rtl8723au_idx ht20_max_power_offset[3];
 742         u8 channel_plan;                                        /* 0x75 */
 743         u8 tssi_a;
 744         u8 tssi_b;
 745         u8 thermal_meter;       /* xtal_k */                    /* 0x78 */
 746         u8 rf_regulatory;
 747         u8 rf_option_2;
 748         u8 rf_option_3;
 749         u8 rf_option_4;
 750         u8 res5[1];                                             /* 0x7d */
 751         u8 version;
 752         u8 customer_id;
 753 };
 754
 755 struct rtl8723bu_pwr_idx {
 756 #ifdef __LITTLE_ENDIAN
 757         int     ht20:4;
 758         int     ht40:4;
 759         int     ofdm:4;
 760         int     cck:4;
 761 #else
 762         int     cck:4;
 763         int     ofdm:4;
 764         int     ht40:4;
 765         int     ht20:4;
 766 #endif
 767 } __attribute__((packed));
 768
 769 struct rtl8723bu_efuse_tx_power {
 770         u8 cck_base[6];
 771         u8 ht40_base[5];
 772         struct rtl8723au_idx ht20_ofdm_1s_diff;
 773         struct rtl8723bu_pwr_idx pwr_diff[3];
 774         u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
 775 };
 776
 777 struct rtl8723bu_efuse {
 778         __le16 rtl_id;
 779         u8 res0[0x0e];
 780         struct rtl8723bu_efuse_tx_power tx_power_index_A;       /* 0x10 */
 781         struct rtl8723bu_efuse_tx_power tx_power_index_B;       /* 0x3a */
 782         struct rtl8723bu_efuse_tx_power tx_power_index_C;       /* 0x64 */
 783         struct rtl8723bu_efuse_tx_power tx_power_index_D;       /* 0x8e */
 784         u8 channel_plan;                /* 0xb8 */
 785         u8 xtal_k;
 786         u8 thermal_meter;
 787         u8 iqk_lck;
 788         u8 pa_type;                     /* 0xbc */
 789         u8 lna_type_2g;                 /* 0xbd */
 790         u8 res2[3];
 791         u8 rf_board_option;
 792         u8 rf_feature_option;
 793         u8 rf_bt_setting;
 794         u8 eeprom_version;
 795         u8 eeprom_customer_id;
 796         u8 res3[2];
 797         u8 tx_pwr_calibrate_rate;
 798         u8 rf_antenna_option;           /* 0xc9 */
 799         u8 rfe_option;
 800         u8 res4[9];
 801         u8 usb_optional_function;
 802         u8 res5[0x1e];
 803         u8 res6[2];
 804         u8 serial[0x0b];                /* 0xf5 */
 805         u8 vid;                         /* 0x100 */
 806         u8 res7;
 807         u8 pid;
 808         u8 res8[4];
 809         u8 mac_addr[ETH_ALEN];          /* 0x107 */
 810         u8 res9[2];
 811         u8 vendor_name[0x07];
 812         u8 res10[2];
 813         u8 device_name[0x14];
 814         u8 res11[0xcf];
 815         u8 package_type;                /* 0x1fb */
 816         u8 res12[0x4];
 817 };
 818
 819 struct rtl8192eu_efuse_tx_power {
 820         u8 cck_base[6];
 821         u8 ht40_base[5];
 822         struct rtl8723au_idx ht20_ofdm_1s_diff;
 823         struct rtl8723bu_pwr_idx pwr_diff[3];
 824         u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
 825 };
 826
 827 struct rtl8192eu_efuse {
 828         __le16 rtl_id;
 829         u8 res0[0x0e];
 830         struct rtl8192eu_efuse_tx_power tx_power_index_A;       /* 0x10 */
 831         struct rtl8192eu_efuse_tx_power tx_power_index_B;       /* 0x3a */
 832         u8 res2[0x54];
 833         u8 channel_plan;                /* 0xb8 */
 834         u8 xtal_k;
 835         u8 thermal_meter;
 836         u8 iqk_lck;
 837         u8 pa_type;                     /* 0xbc */
 838         u8 lna_type_2g;                 /* 0xbd */
 839         u8 res3[1];
 840         u8 lna_type_5g;                 /* 0xbf */
 841         u8 res4[1];
 842         u8 rf_board_option;
 843         u8 rf_feature_option;
 844         u8 rf_bt_setting;
 845         u8 eeprom_version;
 846         u8 eeprom_customer_id;
 847         u8 res5[3];
 848         u8 rf_antenna_option;           /* 0xc9 */
 849         u8 res6[6];
 850         u8 vid;                         /* 0xd0 */
 851         u8 res7[1];
 852         u8 pid;                         /* 0xd2 */
 853         u8 res8[1];
 854         u8 usb_optional_function;
 855         u8 res9[2];
 856         u8 mac_addr[ETH_ALEN];          /* 0xd7 */
 857         u8 res10[2];
 858         u8 vendor_name[7];
 859         u8 res11[2];
 860         u8 device_name[0x0b];           /* 0xe8 */
 861         u8 res12[2];
 862         u8 serial[0x0b];                /* 0xf5 */
 863         u8 res13[0x30];
 864         u8 unknown[0x0d];               /* 0x130 */
 865         u8 res14[0xc3];
 866 };
 867
 868 struct rtl8xxxu_reg8val {
 869         u16 reg;
 870         u8 val;
 871 };
 872
 873 struct rtl8xxxu_reg32val {
 874         u16 reg;
 875         u32 val;
 876 };
 877
 878 struct rtl8xxxu_rfregval {
 879         u8 reg;
 880         u32 val;
 881 };
 882
 883 enum rtl8xxxu_rfpath {
 884         RF_A = 0,
 885         RF_B = 1,
 886 };
 887
 888 struct rtl8xxxu_rfregs {
 889         u16 hssiparm1;
 890         u16 hssiparm2;
 891         u16 lssiparm;
 892         u16 hspiread;
 893         u16 lssiread;
 894         u16 rf_sw_ctrl;
 895 };
 896
 897 #define H2C_MAX_MBOX                    4
 898 #define H2C_EXT                         BIT(7)
 899 #define  H2C_JOIN_BSS_DISCONNECT        0
 900 #define  H2C_JOIN_BSS_CONNECT           1
 901
 902 /*
 903  * H2C (firmware) commands differ between the older generation chips
 904  * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu,
 905  * 8192[de]u, 8192eu, and 8812.
 906  */
 907 enum h2c_cmd_8723a {
 908         H2C_SET_POWER_MODE = 1,
 909         H2C_JOIN_BSS_REPORT = 2,
 910         H2C_SET_RSSI = 5,
 911         H2C_SET_RATE_MASK = (6 | H2C_EXT),
 912 };
 913
 914 enum h2c_cmd_8723b {
 915         /*
 916          * Common Class: 000
 917          */
 918         H2C_8723B_RSVD_PAGE = 0x00,
 919         H2C_8723B_MEDIA_STATUS_RPT = 0x01,
 920         H2C_8723B_SCAN_ENABLE = 0x02,
 921         H2C_8723B_KEEP_ALIVE = 0x03,
 922         H2C_8723B_DISCON_DECISION = 0x04,
 923         H2C_8723B_PSD_OFFLOAD = 0x05,
 924         H2C_8723B_AP_OFFLOAD = 0x08,
 925         H2C_8723B_BCN_RSVDPAGE = 0x09,
 926         H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
 927         H2C_8723B_FCS_RSVDPAGE = 0x10,
 928         H2C_8723B_FCS_INFO = 0x11,
 929         H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
 930
 931         /*
 932          * PoweSave Class: 001
 933          */
 934         H2C_8723B_SET_PWR_MODE = 0x20,
 935         H2C_8723B_PS_TUNING_PARA = 0x21,
 936         H2C_8723B_PS_TUNING_PARA2 = 0x22,
 937         H2C_8723B_P2P_LPS_PARAM = 0x23,
 938         H2C_8723B_P2P_PS_OFFLOAD = 0x24,
 939         H2C_8723B_PS_SCAN_ENABLE = 0x25,
 940         H2C_8723B_SAP_PS_ = 0x26,
 941         H2C_8723B_INACTIVE_PS_ = 0x27,
 942         H2C_8723B_FWLPS_IN_IPS_ = 0x28,
 943
 944         /*
 945          * Dynamic Mechanism Class: 010
 946          */
 947         H2C_8723B_MACID_CFG_RAID = 0x40,
 948         H2C_8723B_TXBF = 0x41,
 949         H2C_8723B_RSSI_SETTING = 0x42,
 950         H2C_8723B_AP_REQ_TXRPT = 0x43,
 951         H2C_8723B_INIT_RATE_COLLECT = 0x44,
 952
 953         /*
 954          * BT Class: 011
 955          */
 956         H2C_8723B_B_TYPE_TDMA = 0x60,
 957         H2C_8723B_BT_INFO = 0x61,
 958         H2C_8723B_FORCE_BT_TXPWR = 0x62,
 959         H2C_8723B_BT_IGNORE_WLANACT = 0x63,
 960         H2C_8723B_DAC_SWING_VALUE = 0x64,
 961         H2C_8723B_ANT_SEL_RSV = 0x65,
 962         H2C_8723B_WL_OPMODE = 0x66,
 963         H2C_8723B_BT_MP_OPER = 0x67,
 964         H2C_8723B_BT_CONTROL = 0x68,
 965         H2C_8723B_BT_WIFI_CTRL = 0x69,
 966         H2C_8723B_BT_FW_PATCH = 0x6a,
 967         H2C_8723B_BT_WLAN_CALIBRATION = 0x6d,
 968         H2C_8723B_BT_GRANT = 0x6e,
 969
 970         /*
 971          * WOWLAN Class: 100
 972          */
 973         H2C_8723B_WOWLAN = 0x80,
 974         H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
 975         H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
 976         H2C_8723B_AOAC_RSVD_PAGE = 0x83,
 977         H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
 978         H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
 979         H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
 980         H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
 981
 982         H2C_8723B_RESET_TSF = 0xC0,
 983 };
 984
 985
 986 struct h2c_cmd {
 987         union {
 988                 struct {
 989                         u8 cmd;
 990                         u8 data[7];
 991                 } __packed cmd;
 992                 struct {
 993                         __le32 data;
 994                         __le16 ext;
 995                 } __packed raw;
 996                 struct {
 997                         __le32 data;
 998                         __le32 ext;
 999                 } __packed raw_wide;
1000                 struct {
1001                         u8 cmd;
1002                         u8 data;
1003                 } __packed joinbss;
1004                 struct {
1005                         u8 cmd;
1006                         __le16 mask_hi;
1007                         u8 arg;
1008                         __le16 mask_lo;
1009                 } __packed ramask;
1010                 struct {
1011                         u8 cmd;
1012                         u8 parm;
1013                         u8 macid;
1014                         u8 macid_end;
1015                 } __packed media_status_rpt;
1016                 struct {
1017                         u8 cmd;
1018                         u8 macid;
1019                         /*
1020                          * [0:4] - RAID
1021                          * [7]   - SGI
1022                          */
1023                         u8 data1;
1024                         /*
1025                          * [0:1] - Bandwidth
1026                          * [3]   - No Update
1027                          * [4:5] - VHT enable
1028                          * [6]   - DISPT
1029                          * [7]   - DISRA
1030                          */
1031                         u8 data2;
1032                         u8 ramask0;
1033                         u8 ramask1;
1034                         u8 ramask2;
1035                         u8 ramask3;
1036                 } __packed b_macid_cfg;
1037                 struct {
1038                         u8 cmd;
1039                         u8 data1;
1040                         u8 data2;
1041                         u8 data3;
1042                         u8 data4;
1043                         u8 data5;
1044                 } __packed b_type_dma;
1045                 struct {
1046                         u8 cmd;
1047                         u8 data;
1048                 } __packed bt_info;
1049                 struct {
1050                         u8 cmd;
1051                         u8 operreq;
1052                         u8 opcode;
1053                         u8 data;
1054                         u8 addr;
1055                 } __packed bt_mp_oper;
1056                 struct {
1057                         u8 cmd;
1058                         u8 data;
1059                 } __packed bt_wlan_calibration;
1060                 struct {
1061                         u8 cmd;
1062                         u8 data;
1063                 } __packed ignore_wlan;
1064                 struct {
1065                         u8 cmd;
1066                         u8 ant_inverse;
1067                         u8 int_switch_type;
1068                 } __packed ant_sel_rsv;
1069                 struct {
1070                         u8 cmd;
1071                         u8 data;
1072                 } __packed bt_grant;
1073         };
1074 };
1075
1076 enum c2h_evt_8723b {
1077         C2H_8723B_DEBUG = 0,
1078         C2H_8723B_TSF = 1,
1079         C2H_8723B_AP_RPT_RSP = 2,
1080         C2H_8723B_CCX_TX_RPT = 3,
1081         C2H_8723B_BT_RSSI = 4,
1082         C2H_8723B_BT_OP_MODE = 5,
1083         C2H_8723B_EXT_RA_RPT = 6,
1084         C2H_8723B_BT_INFO = 9,
1085         C2H_8723B_HW_INFO_EXCH = 0x0a,
1086         C2H_8723B_BT_MP_INFO = 0x0b,
1087         C2H_8723B_RA_REPORT = 0x0c,
1088         C2H_8723B_FW_DEBUG = 0xff,
1089 };
1090
1091 enum bt_info_src_8723b {
1092         BT_INFO_SRC_8723B_WIFI_FW = 0x0,
1093         BT_INFO_SRC_8723B_BT_RSP = 0x1,
1094         BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2,
1095 };
1096
1097 enum bt_mp_oper_opcode_8723b {
1098         BT_MP_OP_GET_BT_VERSION = 0x00,
1099         BT_MP_OP_RESET = 0x01,
1100         BT_MP_OP_TEST_CTRL = 0x02,
1101         BT_MP_OP_SET_BT_MODE = 0x03,
1102         BT_MP_OP_SET_CHNL_TX_GAIN = 0x04,
1103         BT_MP_OP_SET_PKT_TYPE_LEN = 0x05,
1104         BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
1105         BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
1106         BT_MP_OP_SET_PKT_HEADER = 0x08,
1107         BT_MP_OP_SET_WHITENCOEFF = 0x09,
1108         BT_MP_OP_SET_BD_ADDR_L = 0x0a,
1109         BT_MP_OP_SET_BD_ADDR_H = 0x0b,
1110         BT_MP_OP_WRITE_REG_ADDR = 0x0c,
1111         BT_MP_OP_WRITE_REG_VALUE = 0x0d,
1112         BT_MP_OP_GET_BT_STATUS = 0x0e,
1113         BT_MP_OP_GET_BD_ADDR_L = 0x0f,
1114         BT_MP_OP_GET_BD_ADDR_H = 0x10,
1115         BT_MP_OP_READ_REG = 0x11,
1116         BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12,
1117         BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13,
1118         BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14,
1119         BT_MP_OP_GET_RX_PKT_CNT_L = 0x15,
1120         BT_MP_OP_GET_RX_PKT_CNT_H = 0x16,
1121         BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17,
1122         BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18,
1123         BT_MP_OP_GET_RSSI = 0x19,
1124         BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
1125         BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
1126         BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c,
1127         BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d,
1128         BT_MP_OP_GET_AFH_MAP_L = 0x1e,
1129         BT_MP_OP_GET_AFH_MAP_M = 0x1f,
1130         BT_MP_OP_GET_AFH_MAP_H = 0x20,
1131         BT_MP_OP_GET_AFH_STATUS = 0x21,
1132         BT_MP_OP_SET_TRACKING_INTERVAL = 0x22,
1133         BT_MP_OP_SET_THERMAL_METER = 0x23,
1134         BT_MP_OP_ENABLE_CFO_TRACKING = 0x24,
1135 };
1136
1137 struct rtl8723bu_c2h {
1138         u8 id;
1139         u8 seq;
1140         union {
1141                 struct {
1142                         u8 payload[0];
1143                 } __packed raw;
1144                 struct {
1145                         u8 ext_id;
1146                         u8 status:4;
1147                         u8 retlen:4;
1148                         u8 opcode_ver:4;
1149                         u8 req_num:4;
1150                         u8 payload[2];
1151                 } __packed bt_mp_info;
1152                 struct {
1153                         u8 response_source:4;
1154                         u8 dummy0_0:4;
1155
1156                         u8 bt_info;
1157
1158                         u8 retry_count:4;
1159                         u8 dummy2_0:1;
1160                         u8 bt_page:1;
1161                         u8 tx_rx_mask:1;
1162                         u8 dummy2_2:1;
1163
1164                         u8 rssi;
1165
1166                         u8 basic_rate:1;
1167                         u8 bt_has_reset:1;
1168                         u8 dummy4_1:1;;
1169                         u8 ignore_wlan:1;
1170                         u8 auto_report:1;
1171                         u8 dummy4_2:3;
1172
1173                         u8 a4;
1174                         u8 a5;
1175                 } __packed bt_info;
1176                 struct {
1177                         u8 rate:7;
1178                         u8 dummy0_0:1;
1179                         u8 macid;
1180                         u8 ldpc:1;
1181                         u8 txbf:1;
1182                         u8 noisy_state:1;
1183                         u8 dummy2_0:5;
1184                         u8 dummy3_0;
1185                 } __packed ra_report;
1186         };
1187 };
1188
1189 struct rtl8xxxu_fileops;
1190
1191 struct rtl8xxxu_priv {
1192         struct ieee80211_hw *hw;
1193         struct usb_device *udev;
1194         struct rtl8xxxu_fileops *fops;
1195
1196         spinlock_t tx_urb_lock;
1197         struct list_head tx_urb_free_list;
1198         int tx_urb_free_count;
1199         bool tx_stopped;
1200
1201         spinlock_t rx_urb_lock;
1202         struct list_head rx_urb_pending_list;
1203         int rx_urb_pending_count;
1204         bool shutdown;
1205         struct work_struct rx_urb_wq;
1206
1207         u8 mac_addr[ETH_ALEN];
1208         char chip_name[8];
1209         char chip_vendor[8];
1210         u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1211         u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1212         u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1213         u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1214         /*
1215          * The following entries are half-bytes split as:
1216          * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
1217          */
1218         struct rtl8723au_idx ht40_2s_tx_power_index_diff[
1219                 RTL8723A_CHANNEL_GROUPS];
1220         struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1221         struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1222         struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1223         struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1224         /*
1225          * Newer generation chips only keep power diffs per TX count,
1226          * not per channel group.
1227          */
1228         struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT];
1229         struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT];
1230         struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT];
1231         struct rtl8xxxu_power_base *power_base;
1232         u32 chip_cut:4;
1233         u32 rom_rev:4;
1234         u32 is_multi_func:1;
1235         u32 has_wifi:1;
1236         u32 has_bluetooth:1;
1237         u32 enable_bluetooth:1;
1238         u32 has_gps:1;
1239         u32 hi_pa:1;
1240         u32 vendor_umc:1;
1241         u32 vendor_smic:1;
1242         u32 has_polarity_ctrl:1;
1243         u32 has_eeprom:1;
1244         u32 boot_eeprom:1;
1245         u32 usb_interrupts:1;
1246         u32 ep_tx_high_queue:1;
1247         u32 ep_tx_normal_queue:1;
1248         u32 ep_tx_low_queue:1;
1249         u32 has_xtalk:1;
1250         u8 xtalk;
1251         unsigned int pipe_interrupt;
1252         unsigned int pipe_in;
1253         unsigned int pipe_out[TXDESC_QUEUE_MAX];
1254         u8 out_ep[RTL8XXXU_OUT_ENDPOINTS];
1255         u8 ep_tx_count;
1256         u8 rf_paths;
1257         u8 rx_paths;
1258         u8 tx_paths;
1259         u32 rege94;
1260         u32 rege9c;
1261         u32 regeb4;
1262         u32 regebc;
1263         int next_mbox;
1264         int nr_out_eps;
1265
1266         struct mutex h2c_mutex;
1267
1268         struct usb_anchor rx_anchor;
1269         struct usb_anchor tx_anchor;
1270         struct usb_anchor int_anchor;
1271         struct rtl8xxxu_firmware_header *fw_data;
1272         size_t fw_size;
1273         struct mutex usb_buf_mutex;
1274         union {
1275                 __le32 val32;
1276                 __le16 val16;
1277                 u8 val8;
1278         } usb_buf;
1279         union {
1280                 u8 raw[EFUSE_MAP_LEN];
1281                 struct rtl8723au_efuse efuse8723;
1282                 struct rtl8723bu_efuse efuse8723bu;
1283                 struct rtl8192cu_efuse efuse8192;
1284                 struct rtl8192eu_efuse efuse8192eu;
1285         } efuse_wifi;
1286         u32 adda_backup[RTL8XXXU_ADDA_REGS];
1287         u32 mac_backup[RTL8XXXU_MAC_REGS];
1288         u32 bb_backup[RTL8XXXU_BB_REGS];
1289         u32 bb_recovery_backup[RTL8XXXU_BB_REGS];
1290         enum rtl8xxxu_rtl_chip rtl_chip;
1291         u8 pi_enabled:1;
1292         u8 no_pape:1;
1293         u8 int_buf[USB_INTR_CONTENT_LENGTH];
1294 };
1295
1296 struct rtl8xxxu_rx_urb {
1297         struct urb urb;
1298         struct ieee80211_hw *hw;
1299         struct list_head list;
1300 };
1301
1302 struct rtl8xxxu_tx_urb {
1303         struct urb urb;
1304         struct ieee80211_hw *hw;
1305         struct list_head list;
1306 };
1307
1308 struct rtl8xxxu_fileops {
1309         int (*parse_efuse) (struct rtl8xxxu_priv *priv);
1310         int (*load_firmware) (struct rtl8xxxu_priv *priv);
1311         int (*power_on) (struct rtl8xxxu_priv *priv);
1312         void (*power_off) (struct rtl8xxxu_priv *priv);
1313         void (*reset_8051) (struct rtl8xxxu_priv *priv);
1314         int (*llt_init) (struct rtl8xxxu_priv *priv, u8 last_tx_page);
1315         void (*init_phy_bb) (struct rtl8xxxu_priv *priv);
1316         int (*init_phy_rf) (struct rtl8xxxu_priv *priv);
1317         void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);
1318         void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);
1319         void (*config_channel) (struct ieee80211_hw *hw);
1320         int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1321         void (*init_aggregation) (struct rtl8xxxu_priv *priv);
1322         void (*init_statistics) (struct rtl8xxxu_priv *priv);
1323         void (*enable_rf) (struct rtl8xxxu_priv *priv);
1324         void (*disable_rf) (struct rtl8xxxu_priv *priv);
1325         void (*usb_quirks) (struct rtl8xxxu_priv *priv);
1326         void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel,
1327                               bool ht40);
1328         void (*update_rate_mask) (struct rtl8xxxu_priv *priv,
1329                                   u32 ramask, int sgi);
1330         void (*report_connect) (struct rtl8xxxu_priv *priv,
1331                                 u8 macid, bool connect);
1332         int writeN_block_size;
1333         char tx_desc_size;
1334         char rx_desc_size;
1335         char has_s0s1;
1336         u32 adda_1t_init;
1337         u32 adda_1t_path_on;
1338         u32 adda_2t_path_on_a;
1339         u32 adda_2t_path_on_b;
1340         u16 trxff_boundary;
1341         u8 pbp_rx;
1342         u8 pbp_tx;
1343         struct rtl8xxxu_reg8val *mactable;
1344         u8 total_page_num;
1345         u8 page_num_hi;
1346         u8 page_num_lo;
1347         u8 page_num_norm;
1348 };
1349
1350 extern int rtl8xxxu_debug;
1351
1352 extern struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[];
1353 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[];
1354 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr);
1355 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr);
1356 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr);
1357 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val);
1358 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val);
1359 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val);
1360 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1361                         enum rtl8xxxu_rfpath path, u8 reg);
1362 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1363                          enum rtl8xxxu_rfpath path, u8 reg, u32 data);
1364 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
1365                         u32 *backup, int count);
1366 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
1367                            u32 *backup, int count);
1368 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv,
1369                             const u32 *reg, u32 *backup);
1370 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
1371                                const u32 *reg, u32 *backup);
1372 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
1373                            bool path_a_on);
1374 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
1375                               const u32 *regs, u32 *backup);
1376 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
1377                                 int result[][8], int candidate, bool tx_only);
1378 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
1379                                 int result[][8], int candidate, bool tx_only);
1380 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
1381                          struct rtl8xxxu_rfregval *table,
1382                          enum rtl8xxxu_rfpath path);
1383 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
1384                            struct rtl8xxxu_reg32val *array);
1385 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name);
1386 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv);
1387 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv);
1388 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv);
1389 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page);
1390 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start);
1391 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv);
1392 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv,
1393                           struct h2c_cmd *h2c, int len);
1394 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv);
1395 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv);
1396 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page);
1397 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv);
1398 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv);
1399 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv,
1400                                 int channel, bool ht40);
1401 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw);
1402 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw);
1403 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv);
1404 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv);
1405 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
1406                                u32 ramask, int sgi);
1407 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
1408                                     u32 ramask, int sgi);
1409 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
1410                                   u8 macid, bool connect);
1411 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
1412                                   u8 macid, bool connect);
1413 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv);
1414 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv);
1415 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv);
1416 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1417 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1418 int rtl8xxxu_gen2_channel_to_group(int channel);
1419 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
1420                                       int result[][8], int c1, int c2);
1421
1422 extern struct rtl8xxxu_fileops rtl8192cu_fops;
1423 extern struct rtl8xxxu_fileops rtl8192eu_fops;
1424 extern struct rtl8xxxu_fileops rtl8723au_fops;
1425 extern struct rtl8xxxu_fileops rtl8723bu_fops;