drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "sw.h"
  44 #include "hw.h"
  45
  46 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         u32 value;
  50
  51         rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
  52         rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
  53         udelay(10);
  54         value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
  55         return value;
  56 }
  57
  58 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
  59                              u16 offset, u32 value, u8 direct)
  60 {
  61         struct rtl_priv *rtlpriv = rtl_priv(hw);
  62
  63         rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
  64         rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
  65         rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
  66 }
  67
  68 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  69                                       u8 set_bits, u8 clear_bits)
  70 {
  71         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73
  74         rtlpci->reg_bcn_ctrl_val |= set_bits;
  75         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  76         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  77 }
  78
  79 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
  80 {
  81         struct rtl_priv *rtlpriv = rtl_priv(hw);
  82         u8 tmp1byte;
  83
  84         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  85         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  86         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
  87         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  89         tmp1byte &= ~(BIT(0));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  91 }
  92
  93 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
  94 {
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96         u8 tmp1byte;
  97
  98         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  99         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 100         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
 101         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 102         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 103         tmp1byte |= BIT(0);
 104         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 105 }
 106
 107 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
 108 {
 109         _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
 110 }
 111
 112 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
 113 {
 114         _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
 115 }
 116
 117 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 118 {
 119         struct rtl_priv *rtlpriv = rtl_priv(hw);
 120         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 121         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 122
 123         switch (variable) {
 124         case HW_VAR_RCR:
 125                 *((u32 *) (val)) = rtlpci->receive_config;
 126                 break;
 127         case HW_VAR_RF_STATE:
 128                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 129                 break;
 130         case HW_VAR_FWLPS_RF_ON:{
 131                 enum rf_pwrstate rfState;
 132                 u32 val_rcr;
 133
 134                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 135                                               (u8 *) (&rfState));
 136                 if (rfState == ERFOFF) {
 137                         *((bool *) (val)) = true;
 138                 } else {
 139                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 140                         val_rcr &= 0x00070000;
 141                         if (val_rcr)
 142                                 *((bool *) (val)) = false;
 143                         else
 144                                 *((bool *) (val)) = true;
 145                 }
 146                 break;
 147         }
 148         case HW_VAR_FW_PSMODE_STATUS:
 149                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 150                 break;
 151         case HW_VAR_CORRECT_TSF:{
 152                 u64 tsf;
 153                 u32 *ptsf_low = (u32 *)&tsf;
 154                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 155
 156                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 157                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 158                 *((u64 *) (val)) = tsf;
 159                 break;
 160         }
 161         case HW_VAR_INT_MIGRATION:
 162                 *((bool *)(val)) = rtlpriv->dm.interrupt_migration;
 163                 break;
 164         case HW_VAR_INT_AC:
 165                 *((bool *)(val)) = rtlpriv->dm.disable_tx_int;
 166                 break;
 167         case HAL_DEF_WOWLAN:
 168                 break;
 169         default:
 170                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 171                          "switch case %#x not processed\n", variable);
 172                 break;
 173         }
 174 }
 175
 176 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 177 {
 178         struct rtl_priv *rtlpriv = rtl_priv(hw);
 179         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 180         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 181         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 182         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 183         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 184         u8 idx;
 185
 186         switch (variable) {
 187         case HW_VAR_ETHER_ADDR:
 188                 for (idx = 0; idx < ETH_ALEN; idx++) {
 189                         rtl_write_byte(rtlpriv, (REG_MACID + idx),
 190                                        val[idx]);
 191                 }
 192                 break;
 193         case HW_VAR_BASIC_RATE: {
 194                 u16 rate_cfg = ((u16 *) val)[0];
 195                 u8 rate_index = 0;
 196
 197                 rate_cfg = rate_cfg & 0x15f;
 198                 if (mac->vendor == PEER_CISCO &&
 199                     ((rate_cfg & 0x150) == 0))
 200                         rate_cfg |= 0x01;
 201                 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 202                 rtl_write_byte(rtlpriv, REG_RRSR + 1,
 203                                (rate_cfg >> 8) & 0xff);
 204                 while (rate_cfg > 0x1) {
 205                         rate_cfg = (rate_cfg >> 1);
 206                         rate_index++;
 207                 }
 208                 if (rtlhal->fw_version > 0xe)
 209                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 210                                        rate_index);
 211                 break;
 212         }
 213         case HW_VAR_BSSID:
 214                 for (idx = 0; idx < ETH_ALEN; idx++) {
 215                         rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 216                                        val[idx]);
 217                 }
 218                 break;
 219         case HW_VAR_SIFS:
 220                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 221                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 222                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 223                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 224                 if (!mac->ht_enable)
 225                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 226                                        0x0e0e);
 227                 else
 228                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 229                                        *((u16 *) val));
 230                 break;
 231         case HW_VAR_SLOT_TIME: {
 232                 u8 e_aci;
 233
 234                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 235                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 236                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 237                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
 238                         rtlpriv->cfg->ops->set_hw_reg(hw,
 239                                                       HW_VAR_AC_PARAM,
 240                                                       (&e_aci));
 241                 break;
 242         }
 243         case HW_VAR_ACK_PREAMBLE: {
 244                 u8 reg_tmp;
 245                 u8 short_preamble = (bool) (*val);
 246
 247                 reg_tmp = (mac->cur_40_prime_sc) << 5;
 248                 if (short_preamble)
 249                         reg_tmp |= 0x80;
 250                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 251                 break;
 252         }
 253         case HW_VAR_AMPDU_MIN_SPACE: {
 254                 u8 min_spacing_to_set;
 255                 u8 sec_min_space;
 256
 257                 min_spacing_to_set = *val;
 258                 if (min_spacing_to_set <= 7) {
 259                         sec_min_space = 0;
 260                         if (min_spacing_to_set < sec_min_space)
 261                                 min_spacing_to_set = sec_min_space;
 262                         mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
 263                                               min_spacing_to_set);
 264                         *val = min_spacing_to_set;
 265                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 266                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 267                                  mac->min_space_cfg);
 268                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 269                                        mac->min_space_cfg);
 270                 }
 271                 break;
 272         }
 273         case HW_VAR_SHORTGI_DENSITY: {
 274                 u8 density_to_set;
 275
 276                 density_to_set = *val;
 277                 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 278                 mac->min_space_cfg |= (density_to_set << 3);
 279                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 280                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 281                          mac->min_space_cfg);
 282                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 283                                mac->min_space_cfg);
 284                 break;
 285         }
 286         case HW_VAR_AMPDU_FACTOR: {
 287                 u8 factor_toset;
 288                 u32 regtoSet;
 289                 u8 *ptmp_byte = NULL;
 290                 u8 index;
 291
 292                 if (rtlhal->macphymode == DUALMAC_DUALPHY)
 293                         regtoSet = 0xb9726641;
 294                 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
 295                         regtoSet = 0x66626641;
 296                 else
 297                         regtoSet = 0xb972a841;
 298                 factor_toset = *val;
 299                 if (factor_toset <= 3) {
 300                         factor_toset = (1 << (factor_toset + 2));
 301                         if (factor_toset > 0xf)
 302                                 factor_toset = 0xf;
 303                         for (index = 0; index < 4; index++) {
 304                                 ptmp_byte = (u8 *) (&regtoSet) + index;
 305                                 if ((*ptmp_byte & 0xf0) >
 306                                     (factor_toset << 4))
 307                                         *ptmp_byte = (*ptmp_byte & 0x0f)
 308                                                  | (factor_toset << 4);
 309                                 if ((*ptmp_byte & 0x0f) > factor_toset)
 310                                         *ptmp_byte = (*ptmp_byte & 0xf0)
 311                                                      | (factor_toset);
 312                         }
 313                         rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);
 314                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 315                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 316                                  factor_toset);
 317                 }
 318                 break;
 319         }
 320         case HW_VAR_AC_PARAM: {
 321                 u8 e_aci = *val;
 322                 rtl92d_dm_init_edca_turbo(hw);
 323                 if (rtlpci->acm_method != EACMWAY2_SW)
 324                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 325                                                       &e_aci);
 326                 break;
 327         }
 328         case HW_VAR_ACM_CTRL: {
 329                 u8 e_aci = *val;
 330                 union aci_aifsn *p_aci_aifsn =
 331                     (union aci_aifsn *)(&(mac->ac[0].aifs));
 332                 u8 acm = p_aci_aifsn->f.acm;
 333                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 334
 335                 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?  0x0 : 0x1);
 336                 if (acm) {
 337                         switch (e_aci) {
 338                         case AC0_BE:
 339                                 acm_ctrl |= ACMHW_BEQEN;
 340                                 break;
 341                         case AC2_VI:
 342                                 acm_ctrl |= ACMHW_VIQEN;
 343                                 break;
 344                         case AC3_VO:
 345                                 acm_ctrl |= ACMHW_VOQEN;
 346                                 break;
 347                         default:
 348                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 349                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 350                                          acm);
 351                                 break;
 352                         }
 353                 } else {
 354                         switch (e_aci) {
 355                         case AC0_BE:
 356                                 acm_ctrl &= (~ACMHW_BEQEN);
 357                                 break;
 358                         case AC2_VI:
 359                                 acm_ctrl &= (~ACMHW_VIQEN);
 360                                 break;
 361                         case AC3_VO:
 362                                 acm_ctrl &= (~ACMHW_VOQEN);
 363                                 break;
 364                         default:
 365                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 366                                          "switch case %#x not processed\n",
 367                                          e_aci);
 368                                 break;
 369                         }
 370                 }
 371                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 372                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 373                          acm_ctrl);
 374                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 375                 break;
 376         }
 377         case HW_VAR_RCR:
 378                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 379                 rtlpci->receive_config = ((u32 *) (val))[0];
 380                 break;
 381         case HW_VAR_RETRY_LIMIT: {
 382                 u8 retry_limit = val[0];
 383
 384                 rtl_write_word(rtlpriv, REG_RL,
 385                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 386                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 387                 break;
 388         }
 389         case HW_VAR_DUAL_TSF_RST:
 390                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 391                 break;
 392         case HW_VAR_EFUSE_BYTES:
 393                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 394                 break;
 395         case HW_VAR_EFUSE_USAGE:
 396                 rtlefuse->efuse_usedpercentage = *val;
 397                 break;
 398         case HW_VAR_IO_CMD:
 399                 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
 400                 break;
 401         case HW_VAR_WPA_CONFIG:
 402                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 403                 break;
 404         case HW_VAR_SET_RPWM:
 405                 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val));
 406                 break;
 407         case HW_VAR_H2C_FW_PWRMODE:
 408                 break;
 409         case HW_VAR_FW_PSMODE_STATUS:
 410                 ppsc->fw_current_inpsmode = *((bool *) val);
 411                 break;
 412         case HW_VAR_H2C_FW_JOINBSSRPT: {
 413                 u8 mstatus = (*val);
 414                 u8 tmp_regcr, tmp_reg422;
 415                 bool recover = false;
 416
 417                 if (mstatus == RT_MEDIA_CONNECT) {
 418                         rtlpriv->cfg->ops->set_hw_reg(hw,
 419                                                       HW_VAR_AID, NULL);
 420                         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 421                         rtl_write_byte(rtlpriv, REG_CR + 1,
 422                                        (tmp_regcr | BIT(0)));
 423                         _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
 424                         _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
 425                         tmp_reg422 = rtl_read_byte(rtlpriv,
 426                                                  REG_FWHW_TXQ_CTRL + 2);
 427                         if (tmp_reg422 & BIT(6))
 428                                 recover = true;
 429                         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 430                                        tmp_reg422 & (~BIT(6)));
 431                         rtl92d_set_fw_rsvdpagepkt(hw, 0);
 432                         _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
 433                         _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
 434                         if (recover)
 435                                 rtl_write_byte(rtlpriv,
 436                                                REG_FWHW_TXQ_CTRL + 2,
 437                                                tmp_reg422);
 438                         rtl_write_byte(rtlpriv, REG_CR + 1,
 439                                        (tmp_regcr & ~(BIT(0))));
 440                 }
 441                 rtl92d_set_fw_joinbss_report_cmd(hw, (*val));
 442                 break;
 443         }
 444         case HW_VAR_AID: {
 445                 u16 u2btmp;
 446                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 447                 u2btmp &= 0xC000;
 448                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 449                                mac->assoc_id));
 450                 break;
 451         }
 452         case HW_VAR_CORRECT_TSF: {
 453                 u8 btype_ibss = val[0];
 454
 455                 if (btype_ibss)
 456                         _rtl92de_stop_tx_beacon(hw);
 457                 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
 458                 rtl_write_dword(rtlpriv, REG_TSFTR,
 459                                 (u32) (mac->tsf & 0xffffffff));
 460                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 461                                 (u32) ((mac->tsf >> 32) & 0xffffffff));
 462                 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
 463                 if (btype_ibss)
 464                         _rtl92de_resume_tx_beacon(hw);
 465
 466                 break;
 467         }
 468         case HW_VAR_INT_MIGRATION: {
 469                 bool int_migration = *(bool *) (val);
 470
 471                 if (int_migration) {
 472                         /* Set interrupt migration timer and
 473                          * corresponding Tx/Rx counter.
 474                          * timer 25ns*0xfa0=100us for 0xf packets.
 475                          * 0x306:Rx, 0x307:Tx */
 476                         rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
 477                         rtlpriv->dm.interrupt_migration = int_migration;
 478                 } else {
 479                         /* Reset all interrupt migration settings. */
 480                         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 481                         rtlpriv->dm.interrupt_migration = int_migration;
 482                 }
 483                 break;
 484         }
 485         case HW_VAR_INT_AC: {
 486                 bool disable_ac_int = *((bool *) val);
 487
 488                 /* Disable four ACs interrupts. */
 489                 if (disable_ac_int) {
 490                         /* Disable VO, VI, BE and BK four AC interrupts
 491                          * to gain more efficient CPU utilization.
 492                          * When extremely highly Rx OK occurs,
 493                          * we will disable Tx interrupts.
 494                          */
 495                         rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
 496                                                  RT_AC_INT_MASKS);
 497                         rtlpriv->dm.disable_tx_int = disable_ac_int;
 498                 /* Enable four ACs interrupts. */
 499                 } else {
 500                         rtlpriv->cfg->ops->update_interrupt_mask(hw,
 501                                                  RT_AC_INT_MASKS, 0);
 502                         rtlpriv->dm.disable_tx_int = disable_ac_int;
 503                 }
 504                 break;
 505         }
 506         default:
 507                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 508                          "switch case %#x not processed\n", variable);
 509                 break;
 510         }
 511 }
 512
 513 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 514 {
 515         struct rtl_priv *rtlpriv = rtl_priv(hw);
 516         bool status = true;
 517         long count = 0;
 518         u32 value = _LLT_INIT_ADDR(address) |
 519             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 520
 521         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 522         do {
 523                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 524                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 525                         break;
 526                 if (count > POLLING_LLT_THRESHOLD) {
 527                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 528                                  "Failed to polling write LLT done at address %d!\n",
 529                                  address);
 530                         status = false;
 531                         break;
 532                 }
 533         } while (++count);
 534         return status;
 535 }
 536
 537 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
 538 {
 539         struct rtl_priv *rtlpriv = rtl_priv(hw);
 540         unsigned short i;
 541         u8 txpktbuf_bndy;
 542         u8 maxPage;
 543         bool status;
 544         u32 value32; /* High+low page number */
 545         u8 value8;       /* normal page number */
 546
 547         if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
 548                 maxPage = 255;
 549                 txpktbuf_bndy = 246;
 550                 value8 = 0;
 551                 value32 = 0x80bf0d29;
 552         } else {
 553                 maxPage = 127;
 554                 txpktbuf_bndy = 123;
 555                 value8 = 0;
 556                 value32 = 0x80750005;
 557         }
 558
 559         /* Set reserved page for each queue */
 560         /* 11.  RQPN 0x200[31:0] = 0x80BD1C1C */
 561         /* load RQPN */
 562         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
 563         rtl_write_dword(rtlpriv, REG_RQPN, value32);
 564
 565         /* 12.  TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
 566         /* TXRKTBUG_PG_BNDY */
 567         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
 568                         (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
 569                         txpktbuf_bndy));
 570
 571         /* 13.  TDECTRL[15:8] 0x209[7:0] = 0xF6 */
 572         /* Beacon Head for TXDMA */
 573         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 574
 575         /* 14.  BCNQ_PGBNDY 0x424[7:0] =  0xF6 */
 576         /* BCNQ_PGBNDY */
 577         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 578         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 579
 580         /* 15.  WMAC_LBK_BF_HD 0x45D[7:0] =  0xF6 */
 581         /* WMAC_LBK_BF_HD */
 582         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 583
 584         /* Set Tx/Rx page size (Tx must be 128 Bytes, */
 585         /* Rx can be 64,128,256,512,1024 bytes) */
 586         /* 16.  PBP [7:0] = 0x11 */
 587         /* TRX page size */
 588         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 589
 590         /* 17.  DRV_INFO_SZ = 0x04 */
 591         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 592
 593         /* 18.  LLT_table_init(Adapter);  */
 594         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 595                 status = _rtl92de_llt_write(hw, i, i + 1);
 596                 if (true != status)
 597                         return status;
 598         }
 599
 600         /* end of list */
 601         status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 602         if (true != status)
 603                 return status;
 604
 605         /* Make the other pages as ring buffer */
 606         /* This ring buffer is used as beacon buffer if we */
 607         /* config this MAC as two MAC transfer. */
 608         /* Otherwise used as local loopback buffer.  */
 609         for (i = txpktbuf_bndy; i < maxPage; i++) {
 610                 status = _rtl92de_llt_write(hw, i, (i + 1));
 611                 if (true != status)
 612                         return status;
 613         }
 614
 615         /* Let last entry point to the start entry of ring buffer */
 616         status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy);
 617         if (true != status)
 618                 return status;
 619
 620         return true;
 621 }
 622
 623 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
 624 {
 625         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 626         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 627         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 628         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 629
 630         if (rtlpci->up_first_time)
 631                 return;
 632         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 633                 rtl92de_sw_led_on(hw, pLed0);
 634         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 635                 rtl92de_sw_led_on(hw, pLed0);
 636         else
 637                 rtl92de_sw_led_off(hw, pLed0);
 638 }
 639
 640 static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
 641 {
 642         struct rtl_priv *rtlpriv = rtl_priv(hw);
 643         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 644         unsigned char bytetmp;
 645         unsigned short wordtmp;
 646         u16 retry;
 647
 648         rtl92d_phy_set_poweron(hw);
 649         /* Add for resume sequence of power domain according
 650          * to power document V11. Chapter V.11....  */
 651         /* 0.   RSV_CTRL 0x1C[7:0] = 0x00  */
 652         /* unlock ISO/CLK/Power control register */
 653         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 654         rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
 655
 656         /* 1.   AFE_XTAL_CTRL [7:0] = 0x0F  enable XTAL */
 657         /* 2.   SPS0_CTRL 0x11[7:0] = 0x2b  enable SPS into PWM mode  */
 658         /* 3.   delay (1ms) this is not necessary when initially power on */
 659
 660         /* C.   Resume Sequence */
 661         /* a.   SPS0_CTRL 0x11[7:0] = 0x2b */
 662         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 663
 664         /* b.   AFE_XTAL_CTRL [7:0] = 0x0F */
 665         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 666
 667         /* c.   DRV runs power on init flow */
 668
 669         /* auto enable WLAN */
 670         /* 4.   APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0   */
 671         /* Power On Reset for MAC Block */
 672         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 673         udelay(2);
 674         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 675         udelay(2);
 676
 677         /* 5.   Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
 678         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 679         udelay(50);
 680         retry = 0;
 681         while ((bytetmp & BIT(0)) && retry < 1000) {
 682                 retry++;
 683                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 684                 udelay(50);
 685         }
 686
 687         /* Enable Radio off, GPIO, and LED function */
 688         /* 6.   APS_FSMCO 0x04[15:0] = 0x0012  when enable HWPDN */
 689         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 690
 691         /* release RF digital isolation  */
 692         /* 7.  SYS_ISO_CTRL 0x01[1]    = 0x0;  */
 693         /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
 694         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 695         udelay(2);
 696
 697         /* make sure that BB reset OK. */
 698         /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
 699
 700         /* Disable REG_CR before enable it to assure reset */
 701         rtl_write_word(rtlpriv, REG_CR, 0x0);
 702
 703         /* Release MAC IO register reset */
 704         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 705
 706         /* clear stopping tx/rx dma   */
 707         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
 708
 709         /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
 710
 711         /* System init */
 712         /* 18.  LLT_table_init(Adapter);  */
 713         if (!_rtl92de_llt_table_init(hw))
 714                 return false;
 715
 716         /* Clear interrupt and enable interrupt */
 717         /* 19.  HISR 0x124[31:0] = 0xffffffff;  */
 718         /*      HISRE 0x12C[7:0] = 0xFF */
 719         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 720         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 721
 722         /* 20.  HIMR 0x120[31:0] |= [enable INT mask bit map];  */
 723         /* 21.  HIMRE 0x128[7:0] = [enable INT mask bit map] */
 724         /* The IMR should be enabled later after all init sequence
 725          * is finished. */
 726
 727         /* 22.  PCIE configuration space configuration */
 728         /* 23.  Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ),  */
 729         /*      and PCIe gated clock function is enabled.    */
 730         /* PCIE configuration space will be written after
 731          * all init sequence.(Or by BIOS) */
 732
 733         rtl92d_phy_config_maccoexist_rfpage(hw);
 734
 735         /* THe below section is not related to power document Vxx . */
 736         /* This is only useful for driver and OS setting. */
 737         /* -------------------Software Relative Setting---------------------- */
 738         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 739         wordtmp &= 0xf;
 740         wordtmp |= 0xF771;
 741         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 742
 743         /* Reported Tx status from HW for rate adaptive. */
 744         /* This should be realtive to power on step 14. But in document V11  */
 745         /* still not contain the description.!!! */
 746         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 747
 748         /* Set Tx/Rx page size (Tx must be 128 Bytes,
 749          * Rx can be 64,128,256,512,1024 bytes) */
 750         /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
 751
 752         /* Set RCR register */
 753         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 754         /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
 755
 756         /*  Set TCR register */
 757         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 758
 759         /* disable earlymode */
 760         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 761
 762         /* Set TX/RX descriptor physical address(from OS API). */
 763         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 764                         rtlpci->tx_ring[BEACON_QUEUE].dma);
 765         rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 766         rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
 767         rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
 768         rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
 769         rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
 770         rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 771         /* Set RX Desc Address */
 772         rtl_write_dword(rtlpriv, REG_RX_DESA,
 773                         rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 774
 775         /* if we want to support 64 bit DMA, we should set it here,
 776          * but now we do not support 64 bit DMA*/
 777
 778         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
 779
 780         /* Reset interrupt migration setting when initialization */
 781         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 782
 783         /* Reconsider when to do this operation after asking HWSD. */
 784         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 785         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 786         do {
 787                 retry++;
 788                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 789         } while ((retry < 200) && !(bytetmp & BIT(7)));
 790
 791         /* After MACIO reset,we must refresh LED state. */
 792         _rtl92de_gen_refresh_led_state(hw);
 793
 794         /* Reset H2C protection register */
 795         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 796
 797         return true;
 798 }
 799
 800 static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
 801 {
 802         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 803         struct rtl_priv *rtlpriv = rtl_priv(hw);
 804         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 805         u8 reg_bw_opmode = BW_OPMODE_20MHZ;
 806         u32 reg_rrsr;
 807
 808         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 809         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 810         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 811         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 812         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 813         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 814         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 815         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 816         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 817         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 818         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 819         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 820         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 821         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 822         /* Aggregation threshold */
 823         if (rtlhal->macphymode == DUALMAC_DUALPHY)
 824                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
 825         else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
 826                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
 827         else
 828                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 829         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 830         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
 831         rtlpci->reg_bcn_ctrl_val = 0x1f;
 832         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 833         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 834         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 835         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 836         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 837         /* For throughput */
 838         rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
 839         /* ACKTO for IOT issue. */
 840         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 841         /* Set Spec SIFS (used in NAV) */
 842         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 843         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 844         /* Set SIFS for CCK */
 845         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 846         /* Set SIFS for OFDM */
 847         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 848         /* Set Multicast Address. */
 849         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 850         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 851         switch (rtlpriv->phy.rf_type) {
 852         case RF_1T2R:
 853         case RF_1T1R:
 854                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 855                 break;
 856         case RF_2T2R:
 857         case RF_2T2R_GREEN:
 858                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 859                 break;
 860         }
 861 }
 862
 863 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
 864 {
 865         struct rtl_priv *rtlpriv = rtl_priv(hw);
 866         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 867
 868         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 869         rtl_write_word(rtlpriv, 0x350, 0x870c);
 870         rtl_write_byte(rtlpriv, 0x352, 0x1);
 871         if (ppsc->support_backdoor)
 872                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 873         else
 874                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 875         rtl_write_word(rtlpriv, 0x350, 0x2718);
 876         rtl_write_byte(rtlpriv, 0x352, 0x1);
 877 }
 878
 879 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
 880 {
 881         struct rtl_priv *rtlpriv = rtl_priv(hw);
 882         u8 sec_reg_value;
 883
 884         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 885                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 886                  rtlpriv->sec.pairwise_enc_algorithm,
 887                  rtlpriv->sec.group_enc_algorithm);
 888         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 889                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 890                          "not open hw encryption\n");
 891                 return;
 892         }
 893         sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 894         if (rtlpriv->sec.use_defaultkey) {
 895                 sec_reg_value |= SCR_TXUSEDK;
 896                 sec_reg_value |= SCR_RXUSEDK;
 897         }
 898         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 899         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 900         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 901                  "The SECR-value %x\n", sec_reg_value);
 902         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 903 }
 904
 905 int rtl92de_hw_init(struct ieee80211_hw *hw)
 906 {
 907         struct rtl_priv *rtlpriv = rtl_priv(hw);
 908         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 909         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 910         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 911         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 912         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 913         bool rtstatus = true;
 914         u8 tmp_u1b;
 915         int i;
 916         int err;
 917         unsigned long flags;
 918
 919         rtlpci->being_init_adapter = true;
 920         rtlpci->init_ready = false;
 921         spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
 922         /* we should do iqk after disable/enable */
 923         rtl92d_phy_reset_iqk_result(hw);
 924         /* rtlpriv->intf_ops->disable_aspm(hw); */
 925         rtstatus = _rtl92de_init_mac(hw);
 926         if (!rtstatus) {
 927                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
 928                 err = 1;
 929                 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
 930                 return err;
 931         }
 932         err = rtl92d_download_fw(hw);
 933         spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
 934         if (err) {
 935                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 936                          "Failed to download FW. Init HW without FW..\n");
 937                 return 1;
 938         }
 939         rtlhal->last_hmeboxnum = 0;
 940         rtlpriv->psc.fw_current_inpsmode = false;
 941
 942         tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
 943         tmp_u1b = tmp_u1b | 0x30;
 944         rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
 945
 946         if (rtlhal->earlymode_enable) {
 947                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 948                          "EarlyMode Enabled!!!\n");
 949
 950                 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
 951                 tmp_u1b = tmp_u1b | 0x1f;
 952                 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
 953
 954                 rtl_write_byte(rtlpriv, 0x4d3, 0x80);
 955
 956                 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
 957                 tmp_u1b = tmp_u1b | 0x40;
 958                 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
 959         }
 960
 961         if (mac->rdg_en) {
 962                 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
 963                 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
 964                 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
 965         }
 966
 967         rtl92d_phy_mac_config(hw);
 968         /* because last function modify RCR, so we update
 969          * rcr var here, or TP will unstable for receive_config
 970          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
 971          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
 972         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
 973         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
 974
 975         rtl92d_phy_bb_config(hw);
 976
 977         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 978         /* set before initialize RF */
 979         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
 980
 981         /* config RF */
 982         rtl92d_phy_rf_config(hw);
 983
 984         /* After read predefined TXT, we must set BB/MAC/RF
 985          * register as our requirement */
 986         /* After load BB,RF params,we need do more for 92D. */
 987         rtl92d_update_bbrf_configuration(hw);
 988         /* set default value after initialize RF,  */
 989         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
 990         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 991                         RF_CHNLBW, RFREG_OFFSET_MASK);
 992         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 993                         RF_CHNLBW, RFREG_OFFSET_MASK);
 994
 995         /*---- Set CCK and OFDM Block "ON"----*/
 996         if (rtlhal->current_bandtype == BAND_ON_2_4G)
 997                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 998         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 999         if (rtlhal->interfaceindex == 0) {
1000                 /* RFPGA0_ANALOGPARAMETER2: cck clock select,
1001                  *  set to 20MHz by default */
1002                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1003                               BIT(11), 3);
1004         } else {
1005                 /* Mac1 */
1006                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
1007                               BIT(10), 3);
1008         }
1009
1010         _rtl92de_hw_configure(hw);
1011
1012         /* reset hw sec */
1013         rtl_cam_reset_all_entry(hw);
1014         rtl92de_enable_hw_security_config(hw);
1015
1016         /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1017         /* TX power index for different rate set. */
1018         rtl92d_phy_get_hw_reg_originalvalue(hw);
1019         rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
1020
1021         ppsc->rfpwr_state = ERFON;
1022
1023         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1024
1025         _rtl92de_enable_aspm_back_door(hw);
1026         /* rtlpriv->intf_ops->enable_aspm(hw); */
1027
1028         rtl92d_dm_init(hw);
1029         rtlpci->being_init_adapter = false;
1030
1031         if (ppsc->rfpwr_state == ERFON) {
1032                 rtl92d_phy_lc_calibrate(hw);
1033                 /* 5G and 2.4G must wait sometime to let RF LO ready */
1034                 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1035                         u32 tmp_rega;
1036                         for (i = 0; i < 10000; i++) {
1037                                 udelay(MAX_STALL_TIME);
1038
1039                                 tmp_rega = rtl_get_rfreg(hw,
1040                                                   (enum radio_path)RF90_PATH_A,
1041                                                   0x2a, MASKDWORD);
1042
1043                                 if (((tmp_rega & BIT(11)) == BIT(11)))
1044                                         break;
1045                         }
1046                         /* check that loop was successful. If not, exit now */
1047                         if (i == 10000) {
1048                                 rtlpci->init_ready = false;
1049                                 return 1;
1050                         }
1051                 }
1052         }
1053         rtlpci->init_ready = true;
1054         return err;
1055 }
1056
1057 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1058 {
1059         struct rtl_priv *rtlpriv = rtl_priv(hw);
1060         enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1061         u32 value32;
1062
1063         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1064         if (!(value32 & 0x000f0000)) {
1065                 version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1066                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1067         } else {
1068                 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1069                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1070         }
1071         return version;
1072 }
1073
1074 static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1075                                      enum nl80211_iftype type)
1076 {
1077         struct rtl_priv *rtlpriv = rtl_priv(hw);
1078         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1079         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1080         u8 bcnfunc_enable;
1081
1082         bt_msr &= 0xfc;
1083
1084         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1085             type == NL80211_IFTYPE_STATION) {
1086                 _rtl92de_stop_tx_beacon(hw);
1087                 _rtl92de_enable_bcn_sub_func(hw);
1088         } else if (type == NL80211_IFTYPE_ADHOC ||
1089                 type == NL80211_IFTYPE_AP) {
1090                 _rtl92de_resume_tx_beacon(hw);
1091                 _rtl92de_disable_bcn_sub_func(hw);
1092         } else {
1093                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1094                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1095                          type);
1096         }
1097         bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1098         switch (type) {
1099         case NL80211_IFTYPE_UNSPECIFIED:
1100                 bt_msr |= MSR_NOLINK;
1101                 ledaction = LED_CTL_LINK;
1102                 bcnfunc_enable &= 0xF7;
1103                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1104                          "Set Network type to NO LINK!\n");
1105                 break;
1106         case NL80211_IFTYPE_ADHOC:
1107                 bt_msr |= MSR_ADHOC;
1108                 bcnfunc_enable |= 0x08;
1109                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1110                          "Set Network type to Ad Hoc!\n");
1111                 break;
1112         case NL80211_IFTYPE_STATION:
1113                 bt_msr |= MSR_INFRA;
1114                 ledaction = LED_CTL_LINK;
1115                 bcnfunc_enable &= 0xF7;
1116                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1117                          "Set Network type to STA!\n");
1118                 break;
1119         case NL80211_IFTYPE_AP:
1120                 bt_msr |= MSR_AP;
1121                 bcnfunc_enable |= 0x08;
1122                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1123                          "Set Network type to AP!\n");
1124                 break;
1125         default:
1126                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1127                          "Network type %d not supported!\n", type);
1128                 return 1;
1129                 break;
1130
1131         }
1132         rtl_write_byte(rtlpriv, MSR, bt_msr);
1133         rtlpriv->cfg->ops->led_control(hw, ledaction);
1134         if ((bt_msr & MSR_MASK) == MSR_AP)
1135                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1136         else
1137                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1138         return 0;
1139 }
1140
1141 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1142 {
1143         struct rtl_priv *rtlpriv = rtl_priv(hw);
1144         u32 reg_rcr;
1145
1146         if (rtlpriv->psc.rfpwr_state != ERFON)
1147                 return;
1148
1149         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1150
1151         if (check_bssid) {
1152                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1153                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1154                 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1155         } else if (!check_bssid) {
1156                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1157                 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1158                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1159         }
1160 }
1161
1162 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1163 {
1164         struct rtl_priv *rtlpriv = rtl_priv(hw);
1165
1166         if (_rtl92de_set_media_status(hw, type))
1167                 return -EOPNOTSUPP;
1168
1169         /* check bssid */
1170         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1171                 if (type != NL80211_IFTYPE_AP)
1172                         rtl92de_set_check_bssid(hw, true);
1173         } else {
1174                 rtl92de_set_check_bssid(hw, false);
1175         }
1176         return 0;
1177 }
1178
1179 /* do iqk or reload iqk */
1180 /* windows just rtl92d_phy_reload_iqk_setting in set channel,
1181  * but it's very strict for time sequence so we add
1182  * rtl92d_phy_reload_iqk_setting here */
1183 void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1184 {
1185         struct rtl_priv *rtlpriv = rtl_priv(hw);
1186         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1187         u8 indexforchannel;
1188         u8 channel = rtlphy->current_channel;
1189
1190         indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1191         if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {
1192                 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1193                          "Do IQK for channel:%d\n", channel);
1194                 rtl92d_phy_iq_calibrate(hw);
1195         }
1196 }
1197
1198 /* don't set REG_EDCA_BE_PARAM here because
1199  * mac80211 will send pkt when scan */
1200 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1201 {
1202         rtl92d_dm_init_edca_turbo(hw);
1203 }
1204
1205 void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1206 {
1207         struct rtl_priv *rtlpriv = rtl_priv(hw);
1208         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1209
1210         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1211         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1212 }
1213
1214 void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1215 {
1216         struct rtl_priv *rtlpriv = rtl_priv(hw);
1217         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1218
1219         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1220         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1221         synchronize_irq(rtlpci->pdev->irq);
1222 }
1223
1224 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1225 {
1226         struct rtl_priv *rtlpriv = rtl_priv(hw);
1227         u8 u1b_tmp;
1228         unsigned long flags;
1229
1230         rtlpriv->intf_ops->enable_aspm(hw);
1231         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1232         rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1233         rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1234
1235         /* 0x20:value 05-->04 */
1236         rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1237
1238         /*  ==== Reset digital sequence   ====== */
1239         rtl92d_firmware_selfreset(hw);
1240
1241         /* f.   SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1242         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1243
1244         /* g.   MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1245         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1246
1247         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1248
1249         /* h.     GPIO_PIN_CTRL 0x44[31:0]=0x000  */
1250         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1251
1252         /* i.    Value = GPIO_PIN_CTRL[7:0] */
1253         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1254
1255         /* j.    GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1256         /* write external PIN level  */
1257         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1258                         0x00FF0000 | (u1b_tmp << 8));
1259
1260         /* k.   GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1261         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1262
1263         /* l.   LEDCFG 0x4C[15:0] = 0x8080 */
1264         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1265
1266         /*  ==== Disable analog sequence === */
1267
1268         /* m.   AFE_PLL_CTRL[7:0] = 0x80  disable PLL */
1269         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1270
1271         /* n.   SPS0_CTRL 0x11[7:0] = 0x22  enter PFM mode */
1272         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1273
1274         /* o.   AFE_XTAL_CTRL 0x24[7:0] = 0x0E  disable XTAL, if No BT COEX */
1275         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1276
1277         /* p.   RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1278         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1279
1280         /*  ==== interface into suspend === */
1281
1282         /* q.   APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1283         /* According to power document V11, we need to set this */
1284         /* value as 0x18. Otherwise, we may not L0s sometimes. */
1285         /* This indluences power consumption. Bases on SD1's test, */
1286         /* set as 0x00 do not affect power current. And if it */
1287         /* is set as 0x18, they had ever met auto load fail problem. */
1288         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1289
1290         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1291                  "In PowerOff,reg0x%x=%X\n",
1292                  REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1293         /* r.   Note: for PCIe interface, PON will not turn */
1294         /* off m-bias and BandGap in PCIe suspend mode.  */
1295
1296         /* 0x17[7] 1b': power off in process  0b' : power off over */
1297         if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1298                 spin_lock_irqsave(&globalmutex_power, flags);
1299                 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1300                 u1b_tmp &= (~BIT(7));
1301                 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1302                 spin_unlock_irqrestore(&globalmutex_power, flags);
1303         }
1304
1305         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1306 }
1307
1308 void rtl92de_card_disable(struct ieee80211_hw *hw)
1309 {
1310         struct rtl_priv *rtlpriv = rtl_priv(hw);
1311         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1312         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1313         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1314         enum nl80211_iftype opmode;
1315
1316         mac->link_state = MAC80211_NOLINK;
1317         opmode = NL80211_IFTYPE_UNSPECIFIED;
1318         _rtl92de_set_media_status(hw, opmode);
1319
1320         if (rtlpci->driver_is_goingto_unload ||
1321             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1322                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1323         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1324         /* Power sequence for each MAC. */
1325         /* a. stop tx DMA  */
1326         /* b. close RF */
1327         /* c. clear rx buf */
1328         /* d. stop rx DMA */
1329         /* e.  reset MAC */
1330
1331         /* a. stop tx DMA */
1332         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1333         udelay(50);
1334
1335         /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1336
1337         /* c. ========RF OFF sequence==========  */
1338         /* 0x88c[23:20] = 0xf. */
1339         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1340         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1341
1342         /* APSD_CTRL 0x600[7:0] = 0x40 */
1343         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1344
1345         /* Close antenna 0,0xc04,0xd04 */
1346         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
1347         rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1348
1349         /*  SYS_FUNC_EN 0x02[7:0] = 0xE2   reset BB state machine */
1350         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1351
1352         /* Mac0 can not do Global reset. Mac1 can do. */
1353         /* SYS_FUNC_EN 0x02[7:0] = 0xE0  reset BB state machine  */
1354         if (rtlpriv->rtlhal.interfaceindex == 1)
1355                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1356         udelay(50);
1357
1358         /* d.  stop tx/rx dma before disable REG_CR (0x100) to fix */
1359         /* dma hang issue when disable/enable device.  */
1360         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1361         udelay(50);
1362         rtl_write_byte(rtlpriv, REG_CR, 0x0);
1363         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1364         if (rtl92d_phy_check_poweroff(hw))
1365                 _rtl92de_poweroff_adapter(hw);
1366         return;
1367 }
1368
1369 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1370                                   u32 *p_inta, u32 *p_intb)
1371 {
1372         struct rtl_priv *rtlpriv = rtl_priv(hw);
1373         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1374
1375         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1376         rtl_write_dword(rtlpriv, ISR, *p_inta);
1377
1378         /*
1379          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1380          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1381          */
1382 }
1383
1384 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1385 {
1386         struct rtl_priv *rtlpriv = rtl_priv(hw);
1387         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1388         u16 bcn_interval, atim_window;
1389
1390         bcn_interval = mac->beacon_interval;
1391         atim_window = 2;
1392         /*rtl92de_disable_interrupt(hw);  */
1393         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1394         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1395         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1396         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1397         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1398                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1399         else
1400                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1401         rtl_write_byte(rtlpriv, 0x606, 0x30);
1402 }
1403
1404 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1405 {
1406         struct rtl_priv *rtlpriv = rtl_priv(hw);
1407         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1408         u16 bcn_interval = mac->beacon_interval;
1409
1410         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1411                  "beacon_interval:%d\n", bcn_interval);
1412         /* rtl92de_disable_interrupt(hw); */
1413         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1414         /* rtl92de_enable_interrupt(hw); */
1415 }
1416
1417 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1418                                    u32 add_msr, u32 rm_msr)
1419 {
1420         struct rtl_priv *rtlpriv = rtl_priv(hw);
1421         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1422
1423         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1424                  add_msr, rm_msr);
1425         if (add_msr)
1426                 rtlpci->irq_mask[0] |= add_msr;
1427         if (rm_msr)
1428                 rtlpci->irq_mask[0] &= (~rm_msr);
1429         rtl92de_disable_interrupt(hw);
1430         rtl92de_enable_interrupt(hw);
1431 }
1432
1433 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1434                                  u8 *rom_content, bool autoLoadfail)
1435 {
1436         u32 rfpath, eeaddr, group, offset1, offset2;
1437         u8 i;
1438
1439         memset(pwrinfo, 0, sizeof(struct txpower_info));
1440         if (autoLoadfail) {
1441                 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1442                         for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1443                                 if (group < CHANNEL_GROUP_MAX_2G) {
1444                                         pwrinfo->cck_index[rfpath][group] =
1445                                             EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1446                                         pwrinfo->ht40_1sindex[rfpath][group] =
1447                                             EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1448                                 } else {
1449                                         pwrinfo->ht40_1sindex[rfpath][group] =
1450                                             EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1451                                 }
1452                                 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1453                                     EEPROM_DEFAULT_HT40_2SDIFF;
1454                                 pwrinfo->ht20indexdiff[rfpath][group] =
1455                                     EEPROM_DEFAULT_HT20_DIFF;
1456                                 pwrinfo->ofdmindexdiff[rfpath][group] =
1457                                     EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1458                                 pwrinfo->ht40maxoffset[rfpath][group] =
1459                                     EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1460                                 pwrinfo->ht20maxoffset[rfpath][group] =
1461                                     EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1462                         }
1463                 }
1464                 for (i = 0; i < 3; i++) {
1465                         pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1466                         pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1467                 }
1468                 return;
1469         }
1470
1471         /* Maybe autoload OK,buf the tx power index value is not filled.
1472          * If we find it, we set it to default value. */
1473         for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1474                 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1475                         eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1476                                  + group;
1477                         pwrinfo->cck_index[rfpath][group] =
1478                                         (rom_content[eeaddr] == 0xFF) ?
1479                                              (eeaddr > 0x7B ?
1480                                              EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1481                                              EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1482                                              rom_content[eeaddr];
1483                 }
1484         }
1485         for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1486                 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1487                         offset1 = group / 3;
1488                         offset2 = group % 3;
1489                         eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1490                             offset2 + offset1 * 21;
1491                         pwrinfo->ht40_1sindex[rfpath][group] =
1492                             (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1493                                              EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1494                                              EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1495                                                  rom_content[eeaddr];
1496                 }
1497         }
1498         /* These just for 92D efuse offset. */
1499         for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1500                 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1501                         int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1502
1503                         offset1 = group / 3;
1504                         offset2 = group % 3;
1505
1506                         if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1507                                 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1508                                     (rom_content[base1 +
1509                                      offset2 + offset1 * 21] >> (rfpath * 4))
1510                                      & 0xF;
1511                         else
1512                                 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1513                                     EEPROM_DEFAULT_HT40_2SDIFF;
1514                         if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1515                             + offset1 * 21] != 0xFF)
1516                                 pwrinfo->ht20indexdiff[rfpath][group] =
1517                                     (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1518                                     + offset2 + offset1 * 21] >> (rfpath * 4))
1519                                     & 0xF;
1520                         else
1521                                 pwrinfo->ht20indexdiff[rfpath][group] =
1522                                     EEPROM_DEFAULT_HT20_DIFF;
1523                         if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1524                             + offset1 * 21] != 0xFF)
1525                                 pwrinfo->ofdmindexdiff[rfpath][group] =
1526                                     (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1527                                      + offset2 + offset1 * 21] >> (rfpath * 4))
1528                                      & 0xF;
1529                         else
1530                                 pwrinfo->ofdmindexdiff[rfpath][group] =
1531                                     EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1532                         if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1533                             + offset1 * 21] != 0xFF)
1534                                 pwrinfo->ht40maxoffset[rfpath][group] =
1535                                     (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1536                                     + offset2 + offset1 * 21] >> (rfpath * 4))
1537                                     & 0xF;
1538                         else
1539                                 pwrinfo->ht40maxoffset[rfpath][group] =
1540                                     EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1541                         if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1542                             + offset1 * 21] != 0xFF)
1543                                 pwrinfo->ht20maxoffset[rfpath][group] =
1544                                     (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1545                                      offset2 + offset1 * 21] >> (rfpath * 4)) &
1546                                      0xF;
1547                         else
1548                                 pwrinfo->ht20maxoffset[rfpath][group] =
1549                                     EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1550                 }
1551         }
1552         if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1553                 /* 5GL */
1554                 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1555                 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1556                 /* 5GM */
1557                 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1558                 pwrinfo->tssi_b[1] =
1559                     (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1560                     (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1561                 /* 5GH */
1562                 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1563                                       0xF0) >> 4 |
1564                     (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1565                 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1566                                       0xFC) >> 2;
1567         } else {
1568                 for (i = 0; i < 3; i++) {
1569                         pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1570                         pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1571                 }
1572         }
1573 }
1574
1575 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1576                                        bool autoload_fail, u8 *hwinfo)
1577 {
1578         struct rtl_priv *rtlpriv = rtl_priv(hw);
1579         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1580         struct txpower_info pwrinfo;
1581         u8 tempval[2], i, pwr, diff;
1582         u32 ch, rfPath, group;
1583
1584         _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1585         if (!autoload_fail) {
1586                 /* bit0~2 */
1587                 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1588                 rtlefuse->eeprom_thermalmeter =
1589                          hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1590                 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1591                 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1592                 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1593                 rtlefuse->txpwr_fromeprom = true;
1594                 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) ||
1595                     IS_92D_E_CUT(rtlpriv->rtlhal.version)) {
1596                         rtlefuse->internal_pa_5g[0] =
1597                                 !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1598                         rtlefuse->internal_pa_5g[1] =
1599                                 !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1600                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1601                                  "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1602                                  rtlefuse->internal_pa_5g[0],
1603                                  rtlefuse->internal_pa_5g[1]);
1604                 }
1605                 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1606                 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1607         } else {
1608                 rtlefuse->eeprom_regulatory = 0;
1609                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1610                 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1611                 tempval[0] = tempval[1] = 3;
1612         }
1613
1614         /* Use default value to fill parameters if
1615          * efuse is not filled on some place. */
1616
1617         /* ThermalMeter from EEPROM */
1618         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1619             rtlefuse->eeprom_thermalmeter > 0x1c)
1620                 rtlefuse->eeprom_thermalmeter = 0x12;
1621         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1622
1623         /* check XTAL_K */
1624         if (rtlefuse->crystalcap == 0xFF)
1625                 rtlefuse->crystalcap = 0;
1626         if (rtlefuse->eeprom_regulatory > 3)
1627                 rtlefuse->eeprom_regulatory = 0;
1628
1629         for (i = 0; i < 2; i++) {
1630                 switch (tempval[i]) {
1631                 case 0:
1632                         tempval[i] = 5;
1633                         break;
1634                 case 1:
1635                         tempval[i] = 4;
1636                         break;
1637                 case 2:
1638                         tempval[i] = 3;
1639                         break;
1640                 case 3:
1641                 default:
1642                         tempval[i] = 0;
1643                         break;
1644                 }
1645         }
1646
1647         rtlefuse->delta_iqk = tempval[0];
1648         if (tempval[1] > 0)
1649                 rtlefuse->delta_lck = tempval[1] - 1;
1650         if (rtlefuse->eeprom_c9 == 0xFF)
1651                 rtlefuse->eeprom_c9 = 0x00;
1652         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1653                  "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1654         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1655                  "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1656         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1657                  "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1658         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1659                  "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1660                  rtlefuse->delta_iqk, rtlefuse->delta_lck);
1661
1662         for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) {
1663                 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1664                         group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1665                         if (ch < CHANNEL_MAX_NUMBER_2G)
1666                                 rtlefuse->txpwrlevel_cck[rfPath][ch] =
1667                                     pwrinfo.cck_index[rfPath][group];
1668                         rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] =
1669                                     pwrinfo.ht40_1sindex[rfPath][group];
1670                         rtlefuse->txpwr_ht20diff[rfPath][ch] =
1671                                     pwrinfo.ht20indexdiff[rfPath][group];
1672                         rtlefuse->txpwr_legacyhtdiff[rfPath][ch] =
1673                                     pwrinfo.ofdmindexdiff[rfPath][group];
1674                         rtlefuse->pwrgroup_ht20[rfPath][ch] =
1675                                     pwrinfo.ht20maxoffset[rfPath][group];
1676                         rtlefuse->pwrgroup_ht40[rfPath][ch] =
1677                                     pwrinfo.ht40maxoffset[rfPath][group];
1678                         pwr = pwrinfo.ht40_1sindex[rfPath][group];
1679                         diff = pwrinfo.ht40_2sindexdiff[rfPath][group];
1680                         rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] =
1681                                     (pwr > diff) ? (pwr - diff) : 0;
1682                 }
1683         }
1684 }
1685
1686 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1687                                                u8 *content)
1688 {
1689         struct rtl_priv *rtlpriv = rtl_priv(hw);
1690         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1691         u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1692
1693         if (macphy_crvalue & BIT(3)) {
1694                 rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1695                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1696                          "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1697         } else {
1698                 rtlhal->macphymode = DUALMAC_DUALPHY;
1699                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1700                          "MacPhyMode DUALMAC_DUALPHY\n");
1701         }
1702 }
1703
1704 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1705                                                   u8 *content)
1706 {
1707         _rtl92de_read_macphymode_from_prom(hw, content);
1708         rtl92d_phy_config_macphymode(hw);
1709         rtl92d_phy_config_macphymode_info(hw);
1710 }
1711
1712 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1713 {
1714         struct rtl_priv *rtlpriv = rtl_priv(hw);
1715         enum version_8192d chipver = rtlpriv->rtlhal.version;
1716         u8 cutvalue[2];
1717         u16 chipvalue;
1718
1719         rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1720                                            &cutvalue[1]);
1721         rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1722                                            &cutvalue[0]);
1723         chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1724         switch (chipvalue) {
1725         case 0xAA55:
1726                 chipver |= CHIP_92D_C_CUT;
1727                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1728                 break;
1729         case 0x9966:
1730                 chipver |= CHIP_92D_D_CUT;
1731                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1732                 break;
1733         case 0xCC33:
1734                 chipver |= CHIP_92D_E_CUT;
1735                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1736                 break;
1737         default:
1738                 chipver |= CHIP_92D_D_CUT;
1739                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Unknown CUT!\n");
1740                 break;
1741         }
1742         rtlpriv->rtlhal.version = chipver;
1743 }
1744
1745 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1746 {
1747         struct rtl_priv *rtlpriv = rtl_priv(hw);
1748         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1749         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1750         int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1751                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D,
1752                         EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1753                         COUNTRY_CODE_WORLD_WIDE_13};
1754         int i;
1755         u16 usvalue;
1756         u8 *hwinfo;
1757
1758         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1759         if (!hwinfo)
1760                 return;
1761
1762         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1763                 goto exit;
1764
1765         _rtl92de_efuse_update_chip_version(hw);
1766         _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1767
1768         /* Read Permanent MAC address for 2nd interface */
1769         if (rtlhal->interfaceindex != 0) {
1770                 for (i = 0; i < 6; i += 2) {
1771                         usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1772                         *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1773                 }
1774         }
1775         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1776                                       rtlefuse->dev_addr);
1777         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1778         _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1779
1780         /* Read Channel Plan */
1781         switch (rtlhal->bandset) {
1782         case BAND_ON_2_4G:
1783                 rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1784                 break;
1785         case BAND_ON_5G:
1786                 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1787                 break;
1788         case BAND_ON_BOTH:
1789                 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1790                 break;
1791         default:
1792                 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1793                 break;
1794         }
1795         rtlefuse->txpwr_fromeprom = true;
1796 exit:
1797         kfree(hwinfo);
1798 }
1799
1800 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1801 {
1802         struct rtl_priv *rtlpriv = rtl_priv(hw);
1803         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1804         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1805         u8 tmp_u1b;
1806
1807         rtlhal->version = _rtl92de_read_chip_version(hw);
1808         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1809         rtlefuse->autoload_status = tmp_u1b;
1810         if (tmp_u1b & BIT(4)) {
1811                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1812                 rtlefuse->epromtype = EEPROM_93C46;
1813         } else {
1814                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1815                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1816         }
1817         if (tmp_u1b & BIT(5)) {
1818                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1819
1820                 rtlefuse->autoload_failflag = false;
1821                 _rtl92de_read_adapter_info(hw);
1822         } else {
1823                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1824         }
1825         return;
1826 }
1827
1828 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1829                                           struct ieee80211_sta *sta)
1830 {
1831         struct rtl_priv *rtlpriv = rtl_priv(hw);
1832         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1833         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1834         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1835         u32 ratr_value;
1836         u8 ratr_index = 0;
1837         u8 nmode = mac->ht_enable;
1838         u8 mimo_ps = IEEE80211_SMPS_OFF;
1839         u16 shortgi_rate;
1840         u32 tmp_ratr_value;
1841         u8 curtxbw_40mhz = mac->bw_40;
1842         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1843                                                         1 : 0;
1844         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1845                                                         1 : 0;
1846         enum wireless_mode wirelessmode = mac->mode;
1847
1848         if (rtlhal->current_bandtype == BAND_ON_5G)
1849                 ratr_value = sta->supp_rates[1] << 4;
1850         else
1851                 ratr_value = sta->supp_rates[0];
1852         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1853                        sta->ht_cap.mcs.rx_mask[0] << 12);
1854         switch (wirelessmode) {
1855         case WIRELESS_MODE_A:
1856                 ratr_value &= 0x00000FF0;
1857                 break;
1858         case WIRELESS_MODE_B:
1859                 if (ratr_value & 0x0000000c)
1860                         ratr_value &= 0x0000000d;
1861                 else
1862                         ratr_value &= 0x0000000f;
1863                 break;
1864         case WIRELESS_MODE_G:
1865                 ratr_value &= 0x00000FF5;
1866                 break;
1867         case WIRELESS_MODE_N_24G:
1868         case WIRELESS_MODE_N_5G:
1869                 nmode = 1;
1870                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1871                         ratr_value &= 0x0007F005;
1872                 } else {
1873                         u32 ratr_mask;
1874
1875                         if (get_rf_type(rtlphy) == RF_1T2R ||
1876                             get_rf_type(rtlphy) == RF_1T1R) {
1877                                 ratr_mask = 0x000ff005;
1878                         } else {
1879                                 ratr_mask = 0x0f0ff005;
1880                         }
1881
1882                         ratr_value &= ratr_mask;
1883                 }
1884                 break;
1885         default:
1886                 if (rtlphy->rf_type == RF_1T2R)
1887                         ratr_value &= 0x000ff0ff;
1888                 else
1889                         ratr_value &= 0x0f0ff0ff;
1890
1891                 break;
1892         }
1893         ratr_value &= 0x0FFFFFFF;
1894         if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1895             (!curtxbw_40mhz && curshortgi_20mhz))) {
1896                 ratr_value |= 0x10000000;
1897                 tmp_ratr_value = (ratr_value >> 12);
1898                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1899                         if ((1 << shortgi_rate) & tmp_ratr_value)
1900                                 break;
1901                 }
1902                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1903                     (shortgi_rate << 4) | (shortgi_rate);
1904         }
1905         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1906         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1907                  rtl_read_dword(rtlpriv, REG_ARFR0));
1908 }
1909
1910 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1911                 struct ieee80211_sta *sta, u8 rssi_level)
1912 {
1913         struct rtl_priv *rtlpriv = rtl_priv(hw);
1914         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1915         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1916         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1917         struct rtl_sta_info *sta_entry = NULL;
1918         u32 ratr_bitmap;
1919         u8 ratr_index;
1920         u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1921         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1922                                                         1 : 0;
1923         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1924                                                         1 : 0;
1925         enum wireless_mode wirelessmode = 0;
1926         bool shortgi = false;
1927         u32 value[2];
1928         u8 macid = 0;
1929         u8 mimo_ps = IEEE80211_SMPS_OFF;
1930
1931         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1932         mimo_ps = sta_entry->mimo_ps;
1933         wirelessmode = sta_entry->wireless_mode;
1934         if (mac->opmode == NL80211_IFTYPE_STATION)
1935                 curtxbw_40mhz = mac->bw_40;
1936         else if (mac->opmode == NL80211_IFTYPE_AP ||
1937                 mac->opmode == NL80211_IFTYPE_ADHOC)
1938                 macid = sta->aid + 1;
1939
1940         if (rtlhal->current_bandtype == BAND_ON_5G)
1941                 ratr_bitmap = sta->supp_rates[1] << 4;
1942         else
1943                 ratr_bitmap = sta->supp_rates[0];
1944         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1945                         sta->ht_cap.mcs.rx_mask[0] << 12);
1946         switch (wirelessmode) {
1947         case WIRELESS_MODE_B:
1948                 ratr_index = RATR_INX_WIRELESS_B;
1949                 if (ratr_bitmap & 0x0000000c)
1950                         ratr_bitmap &= 0x0000000d;
1951                 else
1952                         ratr_bitmap &= 0x0000000f;
1953                 break;
1954         case WIRELESS_MODE_G:
1955                 ratr_index = RATR_INX_WIRELESS_GB;
1956
1957                 if (rssi_level == 1)
1958                         ratr_bitmap &= 0x00000f00;
1959                 else if (rssi_level == 2)
1960                         ratr_bitmap &= 0x00000ff0;
1961                 else
1962                         ratr_bitmap &= 0x00000ff5;
1963                 break;
1964         case WIRELESS_MODE_A:
1965                 ratr_index = RATR_INX_WIRELESS_G;
1966                 ratr_bitmap &= 0x00000ff0;
1967                 break;
1968         case WIRELESS_MODE_N_24G:
1969         case WIRELESS_MODE_N_5G:
1970                 if (wirelessmode == WIRELESS_MODE_N_24G)
1971                         ratr_index = RATR_INX_WIRELESS_NGB;
1972                 else
1973                         ratr_index = RATR_INX_WIRELESS_NG;
1974                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1975                         if (rssi_level == 1)
1976                                 ratr_bitmap &= 0x00070000;
1977                         else if (rssi_level == 2)
1978                                 ratr_bitmap &= 0x0007f000;
1979                         else
1980                                 ratr_bitmap &= 0x0007f005;
1981                 } else {
1982                         if (rtlphy->rf_type == RF_1T2R ||
1983                             rtlphy->rf_type == RF_1T1R) {
1984                                 if (curtxbw_40mhz) {
1985                                         if (rssi_level == 1)
1986                                                 ratr_bitmap &= 0x000f0000;
1987                                         else if (rssi_level == 2)
1988                                                 ratr_bitmap &= 0x000ff000;
1989                                         else
1990                                                 ratr_bitmap &= 0x000ff015;
1991                                 } else {
1992                                         if (rssi_level == 1)
1993                                                 ratr_bitmap &= 0x000f0000;
1994                                         else if (rssi_level == 2)
1995                                                 ratr_bitmap &= 0x000ff000;
1996                                         else
1997                                                 ratr_bitmap &= 0x000ff005;
1998                                 }
1999                         } else {
2000                                 if (curtxbw_40mhz) {
2001                                         if (rssi_level == 1)
2002                                                 ratr_bitmap &= 0x0f0f0000;
2003                                         else if (rssi_level == 2)
2004                                                 ratr_bitmap &= 0x0f0ff000;
2005                                         else
2006                                                 ratr_bitmap &= 0x0f0ff015;
2007                                 } else {
2008                                         if (rssi_level == 1)
2009                                                 ratr_bitmap &= 0x0f0f0000;
2010                                         else if (rssi_level == 2)
2011                                                 ratr_bitmap &= 0x0f0ff000;
2012                                         else
2013                                                 ratr_bitmap &= 0x0f0ff005;
2014                                 }
2015                         }
2016                 }
2017                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2018                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2019
2020                         if (macid == 0)
2021                                 shortgi = true;
2022                         else if (macid == 1)
2023                                 shortgi = false;
2024                 }
2025                 break;
2026         default:
2027                 ratr_index = RATR_INX_WIRELESS_NGB;
2028
2029                 if (rtlphy->rf_type == RF_1T2R)
2030                         ratr_bitmap &= 0x000ff0ff;
2031                 else
2032                         ratr_bitmap &= 0x0f0ff0ff;
2033                 break;
2034         }
2035
2036         value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2037         value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2038         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2039                  "ratr_bitmap :%x value0:%x value1:%x\n",
2040                  ratr_bitmap, value[0], value[1]);
2041         rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2042         if (macid != 0)
2043                 sta_entry->ratr_index = ratr_index;
2044 }
2045
2046 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2047                 struct ieee80211_sta *sta, u8 rssi_level)
2048 {
2049         struct rtl_priv *rtlpriv = rtl_priv(hw);
2050
2051         if (rtlpriv->dm.useramask)
2052                 rtl92de_update_hal_rate_mask(hw, sta, rssi_level);
2053         else
2054                 rtl92de_update_hal_rate_table(hw, sta);
2055 }
2056
2057 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2058 {
2059         struct rtl_priv *rtlpriv = rtl_priv(hw);
2060         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2061         u16 sifs_timer;
2062
2063         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2064                                       &mac->slot_time);
2065         if (!mac->ht_enable)
2066                 sifs_timer = 0x0a0a;
2067         else
2068                 sifs_timer = 0x1010;
2069         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2070 }
2071
2072 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2073 {
2074         struct rtl_priv *rtlpriv = rtl_priv(hw);
2075         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2076         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2077         enum rf_pwrstate e_rfpowerstate_toset;
2078         u8 u1tmp;
2079         bool actuallyset = false;
2080         unsigned long flag;
2081
2082         if (rtlpci->being_init_adapter)
2083                 return false;
2084         if (ppsc->swrf_processing)
2085                 return false;
2086         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2087         if (ppsc->rfchange_inprogress) {
2088                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2089                 return false;
2090         } else {
2091                 ppsc->rfchange_inprogress = true;
2092                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2093         }
2094         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2095                           REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2096         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2097         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2098         if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2099                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2100                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2101                 e_rfpowerstate_toset = ERFON;
2102                 ppsc->hwradiooff = false;
2103                 actuallyset = true;
2104         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2105                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2106                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2107                 e_rfpowerstate_toset = ERFOFF;
2108                 ppsc->hwradiooff = true;
2109                 actuallyset = true;
2110         }
2111         if (actuallyset) {
2112                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2113                 ppsc->rfchange_inprogress = false;
2114                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2115         } else {
2116                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2117                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2118                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2119                 ppsc->rfchange_inprogress = false;
2120                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2121         }
2122         *valid = 1;
2123         return !ppsc->hwradiooff;
2124 }
2125
2126 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2127                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2128                      bool is_wepkey, bool clear_all)
2129 {
2130         struct rtl_priv *rtlpriv = rtl_priv(hw);
2131         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2132         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2133         u8 *macaddr = p_macaddr;
2134         u32 entry_id;
2135         bool is_pairwise = false;
2136         static u8 cam_const_addr[4][6] = {
2137                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2138                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2139                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2140                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2141         };
2142         static u8 cam_const_broad[] = {
2143                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2144         };
2145
2146         if (clear_all) {
2147                 u8 idx;
2148                 u8 cam_offset = 0;
2149                 u8 clear_number = 5;
2150                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2151                 for (idx = 0; idx < clear_number; idx++) {
2152                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2153                         rtl_cam_empty_entry(hw, cam_offset + idx);
2154
2155                         if (idx < 5) {
2156                                 memset(rtlpriv->sec.key_buf[idx], 0,
2157                                        MAX_KEY_LEN);
2158                                 rtlpriv->sec.key_len[idx] = 0;
2159                         }
2160                 }
2161         } else {
2162                 switch (enc_algo) {
2163                 case WEP40_ENCRYPTION:
2164                         enc_algo = CAM_WEP40;
2165                         break;
2166                 case WEP104_ENCRYPTION:
2167                         enc_algo = CAM_WEP104;
2168                         break;
2169                 case TKIP_ENCRYPTION:
2170                         enc_algo = CAM_TKIP;
2171                         break;
2172                 case AESCCMP_ENCRYPTION:
2173                         enc_algo = CAM_AES;
2174                         break;
2175                 default:
2176                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2177                                  "switch case %#x not processed\n", enc_algo);
2178                         enc_algo = CAM_TKIP;
2179                         break;
2180                 }
2181                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2182                         macaddr = cam_const_addr[key_index];
2183                         entry_id = key_index;
2184                 } else {
2185                         if (is_group) {
2186                                 macaddr = cam_const_broad;
2187                                 entry_id = key_index;
2188                         } else {
2189                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2190                                         entry_id = rtl_cam_get_free_entry(hw,
2191                                                                  p_macaddr);
2192                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2193                                                 RT_TRACE(rtlpriv, COMP_SEC,
2194                                                          DBG_EMERG,
2195                                                          "Can not find free hw security cam entry\n");
2196                                                 return;
2197                                         }
2198                                 } else {
2199                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2200                                 }
2201                                 key_index = PAIRWISE_KEYIDX;
2202                                 is_pairwise = true;
2203                         }
2204                 }
2205                 if (rtlpriv->sec.key_len[key_index] == 0) {
2206                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2207                                  "delete one entry, entry_id is %d\n",
2208                                  entry_id);
2209                         if (mac->opmode == NL80211_IFTYPE_AP)
2210                                 rtl_cam_del_entry(hw, p_macaddr);
2211                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2212                 } else {
2213                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2214                                  "The insert KEY length is %d\n",
2215                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2216                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2217                                  "The insert KEY is %x %x\n",
2218                                  rtlpriv->sec.key_buf[0][0],
2219                                  rtlpriv->sec.key_buf[0][1]);
2220                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2221                                  "add one entry\n");
2222                         if (is_pairwise) {
2223                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2224                                               "Pairwise Key content",
2225                                               rtlpriv->sec.pairwise_key,
2226                                               rtlpriv->
2227                                               sec.key_len[PAIRWISE_KEYIDX]);
2228                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2229                                          "set Pairwise key\n");
2230                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2231                                                       entry_id, enc_algo,
2232                                                       CAM_CONFIG_NO_USEDK,
2233                                                       rtlpriv->
2234                                                       sec.key_buf[key_index]);
2235                         } else {
2236                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2237                                          "set group key\n");
2238                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2239                                         rtl_cam_add_one_entry(hw,
2240                                                 rtlefuse->dev_addr,
2241                                                 PAIRWISE_KEYIDX,
2242                                                 CAM_PAIRWISE_KEY_POSITION,
2243                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2244                                                 rtlpriv->sec.key_buf[entry_id]);
2245                                 }
2246                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2247                                                 entry_id, enc_algo,
2248                                                 CAM_CONFIG_NO_USEDK,
2249                                                 rtlpriv->sec.key_buf
2250                                                 [entry_id]);
2251                         }
2252                 }
2253         }
2254 }
2255
2256 void rtl92de_suspend(struct ieee80211_hw *hw)
2257 {
2258         struct rtl_priv *rtlpriv = rtl_priv(hw);
2259
2260         rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2261                 REG_MAC_PHY_CTRL_NORMAL);
2262 }
2263
2264 void rtl92de_resume(struct ieee80211_hw *hw)
2265 {
2266         struct rtl_priv *rtlpriv = rtl_priv(hw);
2267
2268         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2269                        rtlpriv->rtlhal.macphyctl_reg);
2270 }