drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "../core.h"
  34 #include "reg.h"
  35 #include "def.h"
  36 #include "phy.h"
  37 #include "rf.h"
  38 #include "dm.h"
  39 #include "table.h"
  40 #include "sw.h"
  41 #include "hw.h"
  42
  43 #define MAX_RF_IMR_INDEX                        12
  44 #define MAX_RF_IMR_INDEX_NORMAL                 13
  45 #define RF_REG_NUM_FOR_C_CUT_5G                 6
  46 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA      7
  47 #define RF_REG_NUM_FOR_C_CUT_2G                 5
  48 #define RF_CHNL_NUM_5G                          19
  49 #define RF_CHNL_NUM_5G_40M                      17
  50 #define TARGET_CHNL_NUM_5G                      221
  51 #define TARGET_CHNL_NUM_2G                      14
  52 #define CV_CURVE_CNT                            64
  53
  54 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
  55         0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
  56 };
  57
  58 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
  59         RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
  60 };
  61
  62 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
  63         RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
  64 };
  65
  66 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
  67         0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
  68 };
  69
  70 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
  71         BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
  72         BIT(10) | BIT(9),
  73         BIT(18) | BIT(17) | BIT(16) | BIT(1),
  74         BIT(2) | BIT(1),
  75         BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
  76 };
  77
  78 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
  79         36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
  80         112, 116, 120, 124, 128, 132, 136, 140
  81 };
  82
  83 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
  84         38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
  85         118, 122, 126, 130, 134, 138
  86 };
  87 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
  88         {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
  89         {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
  90         {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
  91         {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
  92         {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
  93 };
  94
  95 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
  96         {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
  97         {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
  98         {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
  99 };
 100
 101 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
 102
 103 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
 104         {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
 105         {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
 106         {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
 107 };
 108
 109 /* [mode][patha+b][reg] */
 110 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
 111         {
 112                 /* channel 1-14. */
 113                 {
 114                         0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
 115                         0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
 116                 },
 117                 /* path 36-64 */
 118                 {
 119                         0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
 120                         0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
 121                         0x32c9a
 122                 },
 123                 /* 100 -165 */
 124                 {
 125                         0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
 126                         0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
 127                 }
 128         }
 129 };
 130
 131 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
 132
 133 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
 134
 135 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
 136         25141, 25116, 25091, 25066, 25041,
 137         25016, 24991, 24966, 24941, 24917,
 138         24892, 24867, 24843, 24818, 24794,
 139         24770, 24765, 24721, 24697, 24672,
 140         24648, 24624, 24600, 24576, 24552,
 141         24528, 24504, 24480, 24457, 24433,
 142         24409, 24385, 24362, 24338, 24315,
 143         24291, 24268, 24245, 24221, 24198,
 144         24175, 24151, 24128, 24105, 24082,
 145         24059, 24036, 24013, 23990, 23967,
 146         23945, 23922, 23899, 23876, 23854,
 147         23831, 23809, 23786, 23764, 23741,
 148         23719, 23697, 23674, 23652, 23630,
 149         23608, 23586, 23564, 23541, 23519,
 150         23498, 23476, 23454, 23432, 23410,
 151         23388, 23367, 23345, 23323, 23302,
 152         23280, 23259, 23237, 23216, 23194,
 153         23173, 23152, 23130, 23109, 23088,
 154         23067, 23046, 23025, 23003, 22982,
 155         22962, 22941, 22920, 22899, 22878,
 156         22857, 22837, 22816, 22795, 22775,
 157         22754, 22733, 22713, 22692, 22672,
 158         22652, 22631, 22611, 22591, 22570,
 159         22550, 22530, 22510, 22490, 22469,
 160         22449, 22429, 22409, 22390, 22370,
 161         22350, 22336, 22310, 22290, 22271,
 162         22251, 22231, 22212, 22192, 22173,
 163         22153, 22134, 22114, 22095, 22075,
 164         22056, 22037, 22017, 21998, 21979,
 165         21960, 21941, 21921, 21902, 21883,
 166         21864, 21845, 21826, 21807, 21789,
 167         21770, 21751, 21732, 21713, 21695,
 168         21676, 21657, 21639, 21620, 21602,
 169         21583, 21565, 21546, 21528, 21509,
 170         21491, 21473, 21454, 21436, 21418,
 171         21400, 21381, 21363, 21345, 21327,
 172         21309, 21291, 21273, 21255, 21237,
 173         21219, 21201, 21183, 21166, 21148,
 174         21130, 21112, 21095, 21077, 21059,
 175         21042, 21024, 21007, 20989, 20972,
 176         25679, 25653, 25627, 25601, 25575,
 177         25549, 25523, 25497, 25471, 25446,
 178         25420, 25394, 25369, 25343, 25318,
 179         25292, 25267, 25242, 25216, 25191,
 180         25166
 181 };
 182
 183 /* channel 1~14 */
 184 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
 185         26084, 26030, 25976, 25923, 25869, 25816, 25764,
 186         25711, 25658, 25606, 25554, 25502, 25451, 25328
 187 };
 188
 189 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
 190 {
 191         u32 i;
 192
 193         for (i = 0; i <= 31; i++) {
 194                 if (((bitmask >> i) & 0x1) == 1)
 195                         break;
 196         }
 197
 198         return i;
 199 }
 200
 201 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
 202 {
 203         struct rtl_priv *rtlpriv = rtl_priv(hw);
 204         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 205         u32 returnvalue, originalvalue, bitshift;
 206
 207         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
 208                  regaddr, bitmask);
 209         if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
 210                 u8 dbi_direct = 0;
 211
 212                 /* mac1 use phy0 read radio_b. */
 213                 /* mac0 use phy1 read radio_b. */
 214                 if (rtlhal->during_mac1init_radioa)
 215                         dbi_direct = BIT(3);
 216                 else if (rtlhal->during_mac0init_radiob)
 217                         dbi_direct = BIT(3) | BIT(2);
 218                 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
 219                         dbi_direct);
 220         } else {
 221                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
 222         }
 223         bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
 224         returnvalue = (originalvalue & bitmask) >> bitshift;
 225         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 226                  "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
 227                  bitmask, regaddr, originalvalue);
 228         return returnvalue;
 229 }
 230
 231 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
 232                            u32 regaddr, u32 bitmask, u32 data)
 233 {
 234         struct rtl_priv *rtlpriv = rtl_priv(hw);
 235         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 236         u8 dbi_direct = 0;
 237         u32 originalvalue, bitshift;
 238
 239         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 240                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 241                  regaddr, bitmask, data);
 242         if (rtlhal->during_mac1init_radioa)
 243                 dbi_direct = BIT(3);
 244         else if (rtlhal->during_mac0init_radiob)
 245                 /* mac0 use phy1 write radio_b. */
 246                 dbi_direct = BIT(3) | BIT(2);
 247         if (bitmask != MASKDWORD) {
 248                 if (rtlhal->during_mac1init_radioa ||
 249                     rtlhal->during_mac0init_radiob)
 250                         originalvalue = rtl92de_read_dword_dbi(hw,
 251                                         (u16) regaddr,
 252                                         dbi_direct);
 253                 else
 254                         originalvalue = rtl_read_dword(rtlpriv, regaddr);
 255                 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
 256                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
 257         }
 258         if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
 259                 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
 260         else
 261                 rtl_write_dword(rtlpriv, regaddr, data);
 262         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 263                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
 264                  regaddr, bitmask, data);
 265 }
 266
 267 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
 268                                       enum radio_path rfpath, u32 offset)
 269 {
 270
 271         struct rtl_priv *rtlpriv = rtl_priv(hw);
 272         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 273         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 274         u32 newoffset;
 275         u32 tmplong, tmplong2;
 276         u8 rfpi_enable = 0;
 277         u32 retvalue;
 278
 279         newoffset = offset;
 280         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 281         if (rfpath == RF90_PATH_A)
 282                 tmplong2 = tmplong;
 283         else
 284                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 285         tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
 286                 (newoffset << 23) | BLSSIREADEDGE;
 287         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 288                 tmplong & (~BLSSIREADEDGE));
 289         udelay(10);
 290         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 291         udelay(50);
 292         udelay(50);
 293         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 294                 tmplong | BLSSIREADEDGE);
 295         udelay(10);
 296         if (rfpath == RF90_PATH_A)
 297                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 298                               BIT(8));
 299         else if (rfpath == RF90_PATH_B)
 300                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 301                               BIT(8));
 302         if (rfpi_enable)
 303                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 304                         BLSSIREADBACKDATA);
 305         else
 306                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 307                         BLSSIREADBACKDATA);
 308         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
 309                  rfpath, pphyreg->rf_rb, retvalue);
 310         return retvalue;
 311 }
 312
 313 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
 314                                         enum radio_path rfpath,
 315                                         u32 offset, u32 data)
 316 {
 317         u32 data_and_addr;
 318         u32 newoffset;
 319         struct rtl_priv *rtlpriv = rtl_priv(hw);
 320         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 321         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 322
 323         newoffset = offset;
 324         /* T65 RF */
 325         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 326         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 327         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 328                  rfpath, pphyreg->rf3wire_offset, data_and_addr);
 329 }
 330
 331 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
 332                             enum radio_path rfpath, u32 regaddr, u32 bitmask)
 333 {
 334         struct rtl_priv *rtlpriv = rtl_priv(hw);
 335         u32 original_value, readback_value, bitshift;
 336         unsigned long flags;
 337
 338         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 339                  "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 340                  regaddr, rfpath, bitmask);
 341         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 342         original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
 343         bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
 344         readback_value = (original_value & bitmask) >> bitshift;
 345         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 346         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 347                  "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 348                  regaddr, rfpath, bitmask, original_value);
 349         return readback_value;
 350 }
 351
 352 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
 353         u32 regaddr, u32 bitmask, u32 data)
 354 {
 355         struct rtl_priv *rtlpriv = rtl_priv(hw);
 356         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 357         u32 original_value, bitshift;
 358         unsigned long flags;
 359
 360         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 361                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 362                  regaddr, bitmask, data, rfpath);
 363         if (bitmask == 0)
 364                 return;
 365         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 366         if (rtlphy->rf_mode != RF_OP_BY_FW) {
 367                 if (bitmask != RFREG_OFFSET_MASK) {
 368                         original_value = _rtl92d_phy_rf_serial_read(hw,
 369                                 rfpath, regaddr);
 370                         bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
 371                         data = ((original_value & (~bitmask)) |
 372                                 (data << bitshift));
 373                 }
 374                 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
 375         }
 376         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 377         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 378                  "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 379                  regaddr, bitmask, data, rfpath);
 380 }
 381
 382 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
 383 {
 384         struct rtl_priv *rtlpriv = rtl_priv(hw);
 385         u32 i;
 386         u32 arraylength;
 387         u32 *ptrarray;
 388
 389         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
 390         arraylength = MAC_2T_ARRAYLENGTH;
 391         ptrarray = rtl8192de_mac_2tarray;
 392         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
 393         for (i = 0; i < arraylength; i = i + 2)
 394                 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 395         if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
 396                 /* improve 2-stream TX EVM */
 397                 /* rtl_write_byte(rtlpriv, 0x14,0x71); */
 398                 /* AMPDU aggregation number 9 */
 399                 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
 400                 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
 401         } else {
 402                 /* 92D need to test to decide the num. */
 403                 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
 404         }
 405         return true;
 406 }
 407
 408 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
 409 {
 410         struct rtl_priv *rtlpriv = rtl_priv(hw);
 411         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 412
 413         /* RF Interface Sowrtware Control */
 414         /* 16 LSBs if read 32-bit from 0x870 */
 415         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 416         /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 417         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 418         /* 16 LSBs if read 32-bit from 0x874 */
 419         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 420         /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 421
 422         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 423         /* RF Interface Readback Value */
 424         /* 16 LSBs if read 32-bit from 0x8E0 */
 425         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 426         /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 427         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 428         /* 16 LSBs if read 32-bit from 0x8E4 */
 429         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 430         /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 431         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 432
 433         /* RF Interface Output (and Enable) */
 434         /* 16 LSBs if read 32-bit from 0x860 */
 435         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 436         /* 16 LSBs if read 32-bit from 0x864 */
 437         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 438
 439         /* RF Interface (Output and)  Enable */
 440         /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 441         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 442         /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 443         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 444
 445         /* Addr of LSSI. Wirte RF register by driver */
 446         /* LSSI Parameter */
 447         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 448                                  RFPGA0_XA_LSSIPARAMETER;
 449         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 450                                  RFPGA0_XB_LSSIPARAMETER;
 451
 452         /* RF parameter */
 453         /* BB Band Select */
 454         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 455         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 456         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 457         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 458
 459         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 460         /* Tx gain stage */
 461         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 462         /* Tx gain stage */
 463         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 464         /* Tx gain stage */
 465         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 466         /* Tx gain stage */
 467         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 468
 469         /* Tranceiver A~D HSSI Parameter-1 */
 470         /* wire control parameter1 */
 471         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 472         /* wire control parameter1 */
 473         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 474
 475         /* Tranceiver A~D HSSI Parameter-2 */
 476         /* wire control parameter2 */
 477         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 478         /* wire control parameter2 */
 479         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 480
 481         /* RF switch Control */
 482         /* TR/Ant switch control */
 483         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 484         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 485         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 486         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 487
 488         /* AGC control 1 */
 489         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 490         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 491         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 492         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 493
 494         /* AGC control 2  */
 495         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 496         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 497         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 498         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 499
 500         /* RX AFE control 1 */
 501         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 502         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 503         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
 504         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 505
 506         /*RX AFE control 1 */
 507         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 508         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 509         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 510         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 511
 512         /* Tx AFE control 1 */
 513         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE;
 514         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE;
 515         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE;
 516         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE;
 517
 518         /* Tx AFE control 2 */
 519         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
 520         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
 521         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
 522         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
 523
 524         /* Tranceiver LSSI Readback SI mode */
 525         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 526         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 527         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 528         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 529
 530         /* Tranceiver LSSI Readback PI mode */
 531         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
 532         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
 533 }
 534
 535 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 536         u8 configtype)
 537 {
 538         int i;
 539         u32 *phy_regarray_table;
 540         u32 *agctab_array_table = NULL;
 541         u32 *agctab_5garray_table;
 542         u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
 543         struct rtl_priv *rtlpriv = rtl_priv(hw);
 544         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 545
 546         /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
 547         if (rtlhal->interfaceindex == 0) {
 548                 agctab_arraylen = AGCTAB_ARRAYLENGTH;
 549                 agctab_array_table = rtl8192de_agctab_array;
 550                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 551                          " ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
 552         } else {
 553                 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
 554                         agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
 555                         agctab_array_table = rtl8192de_agctab_2garray;
 556                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 557                                  " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
 558                 } else {
 559                         agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
 560                         agctab_5garray_table = rtl8192de_agctab_5garray;
 561                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 562                                  " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
 563
 564                 }
 565         }
 566         phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
 567         phy_regarray_table = rtl8192de_phy_reg_2tarray;
 568         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 569                  " ===> phy:Rtl819XPHY_REG_Array_PG\n");
 570         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 571                 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 572                         rtl_addr_delay(phy_regarray_table[i]);
 573                         rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 574                                       phy_regarray_table[i + 1]);
 575                         udelay(1);
 576                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 577                                  "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 578                                  phy_regarray_table[i],
 579                                  phy_regarray_table[i + 1]);
 580                 }
 581         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 582                 if (rtlhal->interfaceindex == 0) {
 583                         for (i = 0; i < agctab_arraylen; i = i + 2) {
 584                                 rtl_set_bbreg(hw, agctab_array_table[i],
 585                                         MASKDWORD,
 586                                         agctab_array_table[i + 1]);
 587                                 /* Add 1us delay between BB/RF register
 588                                  * setting. */
 589                                 udelay(1);
 590                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 591                                          "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
 592                                          agctab_array_table[i],
 593                                          agctab_array_table[i + 1]);
 594                         }
 595                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 596                                  "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
 597                 } else {
 598                         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
 599                                 for (i = 0; i < agctab_arraylen; i = i + 2) {
 600                                         rtl_set_bbreg(hw, agctab_array_table[i],
 601                                                 MASKDWORD,
 602                                                 agctab_array_table[i + 1]);
 603                                         /* Add 1us delay between BB/RF register
 604                                          * setting. */
 605                                         udelay(1);
 606                                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 607                                                  "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
 608                                                  agctab_array_table[i],
 609                                                  agctab_array_table[i + 1]);
 610                                 }
 611                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 612                                          "Load Rtl819XAGCTAB_2GArray\n");
 613                         } else {
 614                                 for (i = 0; i < agctab_5garraylen; i = i + 2) {
 615                                         rtl_set_bbreg(hw,
 616                                                 agctab_5garray_table[i],
 617                                                 MASKDWORD,
 618                                                 agctab_5garray_table[i + 1]);
 619                                         /* Add 1us delay between BB/RF registeri
 620                                          * setting. */
 621                                         udelay(1);
 622                                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 623                                                  "The Rtl819XAGCTAB_5GArray_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
 624                                                  agctab_5garray_table[i],
 625                                                  agctab_5garray_table[i + 1]);
 626                                 }
 627                                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 628                                          "Load Rtl819XAGCTAB_5GArray\n");
 629                         }
 630                 }
 631         }
 632         return true;
 633 }
 634
 635 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
 636                                                    u32 regaddr, u32 bitmask,
 637                                                    u32 data)
 638 {
 639         struct rtl_priv *rtlpriv = rtl_priv(hw);
 640         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 641         int index;
 642
 643         if (regaddr == RTXAGC_A_RATE18_06)
 644                 index = 0;
 645         else if (regaddr == RTXAGC_A_RATE54_24)
 646                 index = 1;
 647         else if (regaddr == RTXAGC_A_CCK1_MCS32)
 648                 index = 6;
 649         else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
 650                 index = 7;
 651         else if (regaddr == RTXAGC_A_MCS03_MCS00)
 652                 index = 2;
 653         else if (regaddr == RTXAGC_A_MCS07_MCS04)
 654                 index = 3;
 655         else if (regaddr == RTXAGC_A_MCS11_MCS08)
 656                 index = 4;
 657         else if (regaddr == RTXAGC_A_MCS15_MCS12)
 658                 index = 5;
 659         else if (regaddr == RTXAGC_B_RATE18_06)
 660                 index = 8;
 661         else if (regaddr == RTXAGC_B_RATE54_24)
 662                 index = 9;
 663         else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
 664                 index = 14;
 665         else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
 666                 index = 15;
 667         else if (regaddr == RTXAGC_B_MCS03_MCS00)
 668                 index = 10;
 669         else if (regaddr == RTXAGC_B_MCS07_MCS04)
 670                 index = 11;
 671         else if (regaddr == RTXAGC_B_MCS11_MCS08)
 672                 index = 12;
 673         else if (regaddr == RTXAGC_B_MCS15_MCS12)
 674                 index = 13;
 675         else
 676                 return;
 677
 678         rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
 679         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 680                  "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
 681                  rtlphy->pwrgroup_cnt, index,
 682                  rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
 683         if (index == 13)
 684                 rtlphy->pwrgroup_cnt++;
 685 }
 686
 687 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 688         u8 configtype)
 689 {
 690         struct rtl_priv *rtlpriv = rtl_priv(hw);
 691         int i;
 692         u32 *phy_regarray_table_pg;
 693         u16 phy_regarray_pg_len;
 694
 695         phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
 696         phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
 697         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 698                 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 699                         rtl_addr_delay(phy_regarray_table_pg[i]);
 700                         _rtl92d_store_pwrindex_diffrate_offset(hw,
 701                                 phy_regarray_table_pg[i],
 702                                 phy_regarray_table_pg[i + 1],
 703                                 phy_regarray_table_pg[i + 2]);
 704                 }
 705         } else {
 706                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 707                          "configtype != BaseBand_Config_PHY_REG\n");
 708         }
 709         return true;
 710 }
 711
 712 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
 713 {
 714         struct rtl_priv *rtlpriv = rtl_priv(hw);
 715         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 716         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 717         bool rtstatus = true;
 718
 719         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
 720         rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
 721                 BASEBAND_CONFIG_PHY_REG);
 722         if (!rtstatus) {
 723                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n");
 724                 return false;
 725         }
 726
 727         /* if (rtlphy->rf_type == RF_1T2R) {
 728          *      _rtl92c_phy_bb_config_1t(hw);
 729          *     RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
 730          *} */
 731
 732         if (rtlefuse->autoload_failflag == false) {
 733                 rtlphy->pwrgroup_cnt = 0;
 734                 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
 735                         BASEBAND_CONFIG_PHY_REG);
 736         }
 737         if (!rtstatus) {
 738                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n");
 739                 return false;
 740         }
 741         rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
 742                 BASEBAND_CONFIG_AGC_TAB);
 743         if (!rtstatus) {
 744                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
 745                 return false;
 746         }
 747         rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
 748                 RFPGA0_XA_HSSIPARAMETER2, 0x200));
 749
 750         return true;
 751 }
 752
 753 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
 754 {
 755         struct rtl_priv *rtlpriv = rtl_priv(hw);
 756         u16 regval;
 757         u32 regvaldw;
 758         u8 value;
 759
 760         _rtl92d_phy_init_bb_rf_register_definition(hw);
 761         regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 762         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
 763                        regval | BIT(13) | BIT(0) | BIT(1));
 764         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 765         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 766         /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
 767         value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
 768         rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
 769                 RF_SDMRSTB);
 770         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
 771                 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
 772         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 773         if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
 774                 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
 775                 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
 776         }
 777
 778         return _rtl92d_phy_bb_config(hw);
 779 }
 780
 781 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
 782 {
 783         return rtl92d_phy_rf6052_config(hw);
 784 }
 785
 786 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 787                                           enum rf_content content,
 788                                           enum radio_path rfpath)
 789 {
 790         int i;
 791         u32 *radioa_array_table;
 792         u32 *radiob_array_table;
 793         u16 radioa_arraylen, radiob_arraylen;
 794         struct rtl_priv *rtlpriv = rtl_priv(hw);
 795
 796         radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
 797         radioa_array_table = rtl8192de_radioa_2tarray;
 798         radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
 799         radiob_array_table = rtl8192de_radiob_2tarray;
 800         if (rtlpriv->efuse.internal_pa_5g[0]) {
 801                 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
 802                 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
 803         }
 804         if (rtlpriv->efuse.internal_pa_5g[1]) {
 805                 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
 806                 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
 807         }
 808         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 809                  "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
 810         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 811                  "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
 812         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
 813
 814         /* this only happens when DMDP, mac0 start on 2.4G,
 815          * mac1 start on 5G, mac 0 has to set phy0&phy1
 816          * pathA or mac1 has to set phy0&phy1 pathA */
 817         if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
 818                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 819                          " ===> althougth Path A, we load radiob.txt\n");
 820                 radioa_arraylen = radiob_arraylen;
 821                 radioa_array_table = radiob_array_table;
 822         }
 823         switch (rfpath) {
 824         case RF90_PATH_A:
 825                 for (i = 0; i < radioa_arraylen; i = i + 2) {
 826                         rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
 827                                         RFREG_OFFSET_MASK,
 828                                         radioa_array_table[i + 1]);
 829                 }
 830                 break;
 831         case RF90_PATH_B:
 832                 for (i = 0; i < radiob_arraylen; i = i + 2) {
 833                         rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
 834                                         RFREG_OFFSET_MASK,
 835                                         radiob_array_table[i + 1]);
 836                 }
 837                 break;
 838         case RF90_PATH_C:
 839                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 840                          "switch case not processed\n");
 841                 break;
 842         case RF90_PATH_D:
 843                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 844                          "switch case not processed\n");
 845                 break;
 846         }
 847         return true;
 848 }
 849
 850 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
 851 {
 852         struct rtl_priv *rtlpriv = rtl_priv(hw);
 853         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 854
 855         rtlphy->default_initialgain[0] =
 856             (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
 857         rtlphy->default_initialgain[1] =
 858             (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
 859         rtlphy->default_initialgain[2] =
 860             (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
 861         rtlphy->default_initialgain[3] =
 862             (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
 863         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 864                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
 865                  rtlphy->default_initialgain[0],
 866                  rtlphy->default_initialgain[1],
 867                  rtlphy->default_initialgain[2],
 868                  rtlphy->default_initialgain[3]);
 869         rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
 870                                               MASKBYTE0);
 871         rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
 872                                               MASKDWORD);
 873         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 874                  "Default framesync (0x%x) = 0x%x\n",
 875                  ROFDM0_RXDETECTOR3, rtlphy->framesync);
 876 }
 877
 878 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
 879         u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 880 {
 881         struct rtl_priv *rtlpriv = rtl_priv(hw);
 882         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 883         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
 884         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 885         u8 index = (channel - 1);
 886
 887         /* 1. CCK */
 888         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
 889                 /* RF-A */
 890                 cckpowerlevel[RF90_PATH_A] =
 891                                  rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
 892                 /* RF-B */
 893                 cckpowerlevel[RF90_PATH_B] =
 894                                  rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
 895         } else {
 896                 cckpowerlevel[RF90_PATH_A] = 0;
 897                 cckpowerlevel[RF90_PATH_B] = 0;
 898         }
 899         /* 2. OFDM for 1S or 2S */
 900         if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
 901                 /*  Read HT 40 OFDM TX power */
 902                 ofdmpowerlevel[RF90_PATH_A] =
 903                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
 904                 ofdmpowerlevel[RF90_PATH_B] =
 905                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
 906         } else if (rtlphy->rf_type == RF_2T2R) {
 907                 /* Read HT 40 OFDM TX power */
 908                 ofdmpowerlevel[RF90_PATH_A] =
 909                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
 910                 ofdmpowerlevel[RF90_PATH_B] =
 911                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
 912         }
 913 }
 914
 915 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
 916         u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 917 {
 918         struct rtl_priv *rtlpriv = rtl_priv(hw);
 919         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 920
 921         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
 922         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
 923 }
 924
 925 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
 926 {
 927         u8 place = chnl;
 928
 929         if (chnl > 14) {
 930                 for (place = 14; place < sizeof(channel5g); place++) {
 931                         if (channel5g[place] == chnl) {
 932                                 place++;
 933                                 break;
 934                         }
 935                 }
 936         }
 937         return place;
 938 }
 939
 940 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
 941 {
 942         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 943         struct rtl_priv *rtlpriv = rtl_priv(hw);
 944         u8 cckpowerlevel[2], ofdmpowerlevel[2];
 945
 946         if (!rtlefuse->txpwr_fromeprom)
 947                 return;
 948         channel = _rtl92c_phy_get_rightchnlplace(channel);
 949         _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
 950                 &ofdmpowerlevel[0]);
 951         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
 952                 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
 953                                 &ofdmpowerlevel[0]);
 954         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
 955                 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
 956         rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
 957 }
 958
 959 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
 960                             enum nl80211_channel_type ch_type)
 961 {
 962         struct rtl_priv *rtlpriv = rtl_priv(hw);
 963         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 964         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 965         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 966         unsigned long flag = 0;
 967         u8 reg_prsr_rsc;
 968         u8 reg_bw_opmode;
 969
 970         if (rtlphy->set_bwmode_inprogress)
 971                 return;
 972         if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
 973                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 974                          "FALSE driver sleep or unload\n");
 975                 return;
 976         }
 977         rtlphy->set_bwmode_inprogress = true;
 978         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 979                  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 980                  "20MHz" : "40MHz");
 981         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 982         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 983         switch (rtlphy->current_chan_bw) {
 984         case HT_CHANNEL_WIDTH_20:
 985                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 986                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 987                 break;
 988         case HT_CHANNEL_WIDTH_20_40:
 989                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 990                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 991
 992                 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
 993                         (mac->cur_40_prime_sc << 5);
 994                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 995                 break;
 996         default:
 997                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 998                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 999                 break;
1000         }
1001         switch (rtlphy->current_chan_bw) {
1002         case HT_CHANNEL_WIDTH_20:
1003                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1004                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1005                 /* SET BIT10 BIT11  for receive cck */
1006                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1007                               BIT(11), 3);
1008                 break;
1009         case HT_CHANNEL_WIDTH_20_40:
1010                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1011                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1012                 /* Set Control channel to upper or lower.
1013                  * These settings are required only for 40MHz */
1014                 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1015                         rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1016                         rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
1017                                 (mac->cur_40_prime_sc >> 1));
1018                         rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1019                 }
1020                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1021                 /* SET BIT10 BIT11  for receive cck */
1022                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1023                               BIT(11), 0);
1024                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1025                         (mac->cur_40_prime_sc ==
1026                         HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1027                 break;
1028         default:
1029                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1030                          "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1031                 break;
1032
1033         }
1034         rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1035         rtlphy->set_bwmode_inprogress = false;
1036         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1037 }
1038
1039 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1040 {
1041         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1042         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1043         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1044         rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1045 }
1046
1047 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1048 {
1049         struct rtl_priv *rtlpriv = rtl_priv(hw);
1050         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1051         u8 value8;
1052
1053         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1054         rtlhal->bandset = band;
1055         rtlhal->current_bandtype = band;
1056         if (IS_92D_SINGLEPHY(rtlhal->version))
1057                 rtlhal->bandset = BAND_ON_BOTH;
1058         /* stop RX/Tx */
1059         _rtl92d_phy_stop_trx_before_changeband(hw);
1060         /* reconfig BB/RF according to wireless mode */
1061         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1062                 /* BB & RF Config */
1063                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1064                 if (rtlhal->interfaceindex == 1)
1065                         _rtl92d_phy_config_bb_with_headerfile(hw,
1066                                 BASEBAND_CONFIG_AGC_TAB);
1067         } else {
1068                 /* 5G band */
1069                 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1070                 if (rtlhal->interfaceindex == 1)
1071                         _rtl92d_phy_config_bb_with_headerfile(hw,
1072                                 BASEBAND_CONFIG_AGC_TAB);
1073         }
1074         rtl92d_update_bbrf_configuration(hw);
1075         if (rtlhal->current_bandtype == BAND_ON_2_4G)
1076                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1077         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1078
1079         /* 20M BW. */
1080         /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1081         rtlhal->reloadtxpowerindex = true;
1082         /* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1083         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1084                 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1085                         0 ? REG_MAC0 : REG_MAC1));
1086                 value8 |= BIT(1);
1087                 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1088                         0 ? REG_MAC0 : REG_MAC1), value8);
1089         } else {
1090                 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1091                         0 ? REG_MAC0 : REG_MAC1));
1092                 value8 &= (~BIT(1));
1093                 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1094                         0 ? REG_MAC0 : REG_MAC1), value8);
1095         }
1096         mdelay(1);
1097         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1098 }
1099
1100 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1101         u8 channel, u8 rfpath)
1102 {
1103         struct rtl_priv *rtlpriv = rtl_priv(hw);
1104         u32 imr_num = MAX_RF_IMR_INDEX;
1105         u32 rfmask = RFREG_OFFSET_MASK;
1106         u8 group, i;
1107         unsigned long flag = 0;
1108
1109         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1110         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1111                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1112                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1113                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1114                 /* fc area 0xd2c */
1115                 if (channel > 99)
1116                         rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1117                                       BIT(14), 2);
1118                 else
1119                         rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1120                                       BIT(14), 1);
1121                 /* leave 0 for channel1-14. */
1122                 group = channel <= 64 ? 1 : 2;
1123                 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1124                 for (i = 0; i < imr_num; i++)
1125                         rtl_set_rfreg(hw, (enum radio_path)rfpath,
1126                                       rf_reg_for_5g_swchnl_normal[i], rfmask,
1127                                       rf_imr_param_normal[0][group][i]);
1128                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1129                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1130         } else {
1131                 /* G band. */
1132                 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1133                          "Load RF IMR parameters for G band. IMR already setting %d\n",
1134                          rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1135                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1136                 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1137                         RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1138                                  "Load RF IMR parameters for G band. %d\n",
1139                                  rfpath);
1140                         rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1141                         rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1142                         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1143                                       0x00f00000, 0xf);
1144                         imr_num = MAX_RF_IMR_INDEX_NORMAL;
1145                         for (i = 0; i < imr_num; i++) {
1146                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1147                                               rf_reg_for_5g_swchnl_normal[i],
1148                                               RFREG_OFFSET_MASK,
1149                                               rf_imr_param_normal[0][0][i]);
1150                         }
1151                         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1152                                       0x00f00000, 0);
1153                         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1154                         rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1155                 }
1156         }
1157         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1158 }
1159
1160 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1161         u8 rfpath, u32 *pu4_regval)
1162 {
1163         struct rtl_priv *rtlpriv = rtl_priv(hw);
1164         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1165         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1166
1167         RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1168         /*----Store original RFENV control type----*/
1169         switch (rfpath) {
1170         case RF90_PATH_A:
1171         case RF90_PATH_C:
1172                 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1173                 break;
1174         case RF90_PATH_B:
1175         case RF90_PATH_D:
1176                 *pu4_regval =
1177                     rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1178                 break;
1179         }
1180         /*----Set RF_ENV enable----*/
1181         rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1182         udelay(1);
1183         /*----Set RF_ENV output high----*/
1184         rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1185         udelay(1);
1186         /* Set bit number of Address and Data for RF register */
1187         /* Set 1 to 4 bits for 8255 */
1188         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1189         udelay(1);
1190         /*Set 0 to 12 bits for 8255 */
1191         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1192         udelay(1);
1193         RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1194 }
1195
1196 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1197                                        u32 *pu4_regval)
1198 {
1199         struct rtl_priv *rtlpriv = rtl_priv(hw);
1200         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1201         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1202
1203         RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1204         /*----Restore RFENV control type----*/
1205         switch (rfpath) {
1206         case RF90_PATH_A:
1207         case RF90_PATH_C:
1208                 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1209                 break;
1210         case RF90_PATH_B:
1211         case RF90_PATH_D:
1212                 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1213                               *pu4_regval);
1214                 break;
1215         }
1216         RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1217 }
1218
1219 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1220 {
1221         struct rtl_priv *rtlpriv = rtl_priv(hw);
1222         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1223         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1224         u8 path = rtlhal->current_bandtype ==
1225             BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1226         u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1227         bool need_pwr_down = false, internal_pa = false;
1228         u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1229
1230         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1231         /* config path A for 5G */
1232         if (rtlhal->current_bandtype == BAND_ON_5G) {
1233                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1234                 u4tmp = curveindex_5g[channel - 1];
1235                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1236                         "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1237                 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1238                         if (channel == rf_chnl_5g[i] && channel <= 140)
1239                                 index = 0;
1240                 }
1241                 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1242                         if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1243                                 index = 1;
1244                 }
1245                 if (channel == 149 || channel == 155 || channel == 161)
1246                         index = 2;
1247                 else if (channel == 151 || channel == 153 || channel == 163
1248                          || channel == 165)
1249                         index = 3;
1250                 else if (channel == 157 || channel == 159)
1251                         index = 4;
1252
1253                 if (rtlhal->macphymode == DUALMAC_DUALPHY
1254                     && rtlhal->interfaceindex == 1) {
1255                         need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1256                         rtlhal->during_mac1init_radioa = true;
1257                         /* asume no this case */
1258                         if (need_pwr_down)
1259                                 _rtl92d_phy_enable_rf_env(hw, path,
1260                                                           &u4regvalue);
1261                 }
1262                 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1263                         if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1264                                 rtl_set_rfreg(hw, (enum radio_path)path,
1265                                               rf_reg_for_c_cut_5g[i],
1266                                               RFREG_OFFSET_MASK, 0xE439D);
1267                         } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1268                                 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1269                                      0x7FF) | (u4tmp << 11);
1270                                 if (channel == 36)
1271                                         u4tmp2 &= ~(BIT(7) | BIT(6));
1272                                 rtl_set_rfreg(hw, (enum radio_path)path,
1273                                               rf_reg_for_c_cut_5g[i],
1274                                               RFREG_OFFSET_MASK, u4tmp2);
1275                         } else {
1276                                 rtl_set_rfreg(hw, (enum radio_path)path,
1277                                               rf_reg_for_c_cut_5g[i],
1278                                               RFREG_OFFSET_MASK,
1279                                               rf_reg_pram_c_5g[index][i]);
1280                         }
1281                         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1282                                  "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1283                                  rf_reg_for_c_cut_5g[i],
1284                                  rf_reg_pram_c_5g[index][i],
1285                                  path, index,
1286                                  rtl_get_rfreg(hw, (enum radio_path)path,
1287                                                rf_reg_for_c_cut_5g[i],
1288                                                RFREG_OFFSET_MASK));
1289                 }
1290                 if (need_pwr_down)
1291                         _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1292                 if (rtlhal->during_mac1init_radioa)
1293                         rtl92d_phy_powerdown_anotherphy(hw, false);
1294                 if (channel < 149)
1295                         value = 0x07;
1296                 else if (channel >= 149)
1297                         value = 0x02;
1298                 if (channel >= 36 && channel <= 64)
1299                         index = 0;
1300                 else if (channel >= 100 && channel <= 140)
1301                         index = 1;
1302                 else
1303                         index = 2;
1304                 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1305                         rfpath++) {
1306                         if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1307                                 rtlhal->interfaceindex == 1)    /* MAC 1 5G */
1308                                 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1309                         else
1310                                 internal_pa =
1311                                          rtlpriv->efuse.internal_pa_5g[rfpath];
1312                         if (internal_pa) {
1313                                 for (i = 0;
1314                                      i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1315                                      i++) {
1316                                         rtl_set_rfreg(hw, rfpath,
1317                                                 rf_for_c_cut_5g_internal_pa[i],
1318                                                 RFREG_OFFSET_MASK,
1319                                                 rf_pram_c_5g_int_pa[index][i]);
1320                                         RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1321                                                  "offset 0x%x value 0x%x path %d index %d\n",
1322                                                  rf_for_c_cut_5g_internal_pa[i],
1323                                                  rf_pram_c_5g_int_pa[index][i],
1324                                                  rfpath, index);
1325                                 }
1326                         } else {
1327                                 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1328                                               mask, value);
1329                         }
1330                 }
1331         } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1332                 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1333                 u4tmp = curveindex_2g[channel - 1];
1334                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1335                         "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1336                 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1337                     || channel == 10 || channel == 11 || channel == 12)
1338                         index = 0;
1339                 else if (channel == 3 || channel == 13 || channel == 14)
1340                         index = 1;
1341                 else if (channel >= 5 && channel <= 8)
1342                         index = 2;
1343                 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1344                         path = RF90_PATH_A;
1345                         if (rtlhal->interfaceindex == 0) {
1346                                 need_pwr_down =
1347                                          rtl92d_phy_enable_anotherphy(hw, true);
1348                                 rtlhal->during_mac0init_radiob = true;
1349
1350                                 if (need_pwr_down)
1351                                         _rtl92d_phy_enable_rf_env(hw, path,
1352                                                                   &u4regvalue);
1353                         }
1354                 }
1355                 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1356                         if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1357                                 rtl_set_rfreg(hw, (enum radio_path)path,
1358                                         rf_reg_for_c_cut_2g[i],
1359                                         RFREG_OFFSET_MASK,
1360                                         (rf_reg_param_for_c_cut_2g[index][i] |
1361                                         BIT(17)));
1362                         else
1363                                 rtl_set_rfreg(hw, (enum radio_path)path,
1364                                               rf_reg_for_c_cut_2g[i],
1365                                               RFREG_OFFSET_MASK,
1366                                               rf_reg_param_for_c_cut_2g
1367                                               [index][i]);
1368                         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1369                                  "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1370                                  rf_reg_for_c_cut_2g[i],
1371                                  rf_reg_param_for_c_cut_2g[index][i],
1372                                  rf_reg_mask_for_c_cut_2g[i], path, index,
1373                                  rtl_get_rfreg(hw, (enum radio_path)path,
1374                                                rf_reg_for_c_cut_2g[i],
1375                                                RFREG_OFFSET_MASK));
1376                 }
1377                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1378                         "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1379                         rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1380
1381                 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1382                               RFREG_OFFSET_MASK,
1383                               rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1384                 if (need_pwr_down)
1385                         _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1386                 if (rtlhal->during_mac0init_radiob)
1387                         rtl92d_phy_powerdown_anotherphy(hw, true);
1388         }
1389         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1390 }
1391
1392 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1393 {
1394         u8 channel_all[59] = {
1395                 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1396                 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1397                 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1398                 114, 116, 118, 120, 122, 124, 126, 128, 130,
1399                 132, 134, 136, 138, 140, 149, 151, 153, 155,
1400                 157, 159, 161, 163, 165
1401         };
1402         u8 place = chnl;
1403
1404         if (chnl > 14) {
1405                 for (place = 14; place < sizeof(channel_all); place++) {
1406                         if (channel_all[place] == chnl)
1407                                 return place - 13;
1408                 }
1409         }
1410
1411         return 0;
1412 }
1413
1414 #define MAX_TOLERANCE           5
1415 #define IQK_DELAY_TIME          1       /* ms */
1416 #define MAX_TOLERANCE_92D       3
1417
1418 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1419 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1420 {
1421         struct rtl_priv *rtlpriv = rtl_priv(hw);
1422         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1423         u32 regeac, rege94, rege9c, regea4;
1424         u8 result = 0;
1425
1426         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1427         /* path-A IQK setting */
1428         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1429         if (rtlhal->interfaceindex == 0) {
1430                 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1431                 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1432         } else {
1433                 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1434                 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1435         }
1436         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1437         rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1438         /* path-B IQK setting */
1439         if (configpathb) {
1440                 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1441                 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1442                 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1443                 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1444         }
1445         /* LO calibration setting */
1446         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1447         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1448         /* One shot, path A LOK & IQK */
1449         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1450         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1451         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1452         /* delay x ms */
1453         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1454                 "Delay %d ms for One shot, path A LOK & IQK\n",
1455                 IQK_DELAY_TIME);
1456         mdelay(IQK_DELAY_TIME);
1457         /* Check failed */
1458         regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1459         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1460         rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1461         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1462         rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1463         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1464         regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1465         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1466         if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1467             (((rege9c & 0x03FF0000) >> 16) != 0x42))
1468                 result |= 0x01;
1469         else                    /* if Tx not OK, ignore Rx */
1470                 return result;
1471         /* if Tx is OK, check whether Rx is OK */
1472         if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1473             (((regeac & 0x03FF0000) >> 16) != 0x36))
1474                 result |= 0x02;
1475         else
1476                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A Rx IQK fail!!\n");
1477         return result;
1478 }
1479
1480 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1481 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1482                                           bool configpathb)
1483 {
1484         struct rtl_priv *rtlpriv = rtl_priv(hw);
1485         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1486         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1487         u32 regeac, rege94, rege9c, regea4;
1488         u8 result = 0;
1489         u8 i;
1490         u8 retrycount = 2;
1491         u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1492
1493         if (rtlhal->interfaceindex == 1) {      /* PHY1 */
1494                 TxOKBit = BIT(31);
1495                 RxOKBit = BIT(30);
1496         }
1497         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1498         /* path-A IQK setting */
1499         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1500         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1501         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1502         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1503         rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1504         /* path-B IQK setting */
1505         if (configpathb) {
1506                 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1507                 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1508                 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1509                 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1510         }
1511         /* LO calibration setting */
1512         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1513         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1514         /* path-A PA on */
1515         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1516         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1517         for (i = 0; i < retrycount; i++) {
1518                 /* One shot, path A LOK & IQK */
1519                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1520                         "One shot, path A LOK & IQK!\n");
1521                 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1522                 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1523                 /* delay x ms */
1524                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1525                         "Delay %d ms for One shot, path A LOK & IQK.\n",
1526                         IQK_DELAY_TIME);
1527                 mdelay(IQK_DELAY_TIME * 10);
1528                 /* Check failed */
1529                 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1530                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1531                 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1532                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1533                 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1534                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1535                 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1536                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1537                 if (!(regeac & TxOKBit) &&
1538                      (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1539                         result |= 0x01;
1540                 } else { /* if Tx not OK, ignore Rx */
1541                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1542                                 "Path A Tx IQK fail!!\n");
1543                         continue;
1544                 }
1545
1546                 /* if Tx is OK, check whether Rx is OK */
1547                 if (!(regeac & RxOKBit) &&
1548                     (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1549                         result |= 0x02;
1550                         break;
1551                 } else {
1552                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1553                                 "Path A Rx IQK fail!!\n");
1554                 }
1555         }
1556         /* path A PA off */
1557         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1558                       rtlphy->iqk_bb_backup[0]);
1559         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1560                       rtlphy->iqk_bb_backup[1]);
1561         return result;
1562 }
1563
1564 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1565 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1566 {
1567         struct rtl_priv *rtlpriv = rtl_priv(hw);
1568         u32 regeac, regeb4, regebc, regec4, regecc;
1569         u8 result = 0;
1570
1571         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1572         /* One shot, path B LOK & IQK */
1573         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1574         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1575         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1576         /* delay x ms  */
1577         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1578                 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1579         mdelay(IQK_DELAY_TIME);
1580         /* Check failed */
1581         regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1582         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1583         regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1584         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1585         regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1586         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1587         regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1588         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1589         regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1590         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1591         if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1592             (((regebc & 0x03FF0000) >> 16) != 0x42))
1593                 result |= 0x01;
1594         else
1595                 return result;
1596         if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1597             (((regecc & 0x03FF0000) >> 16) != 0x36))
1598                 result |= 0x02;
1599         else
1600                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B Rx IQK fail!!\n");
1601         return result;
1602 }
1603
1604 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1605 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1606 {
1607         struct rtl_priv *rtlpriv = rtl_priv(hw);
1608         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1609         u32 regeac, regeb4, regebc, regec4, regecc;
1610         u8 result = 0;
1611         u8 i;
1612         u8 retrycount = 2;
1613
1614         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1615         /* path-A IQK setting */
1616         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1617         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1618         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1619         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1620         rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1621
1622         /* path-B IQK setting */
1623         rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1624         rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1625         rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1626         rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1627
1628         /* LO calibration setting */
1629         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1630         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1631
1632         /* path-B PA on */
1633         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1634         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1635
1636         for (i = 0; i < retrycount; i++) {
1637                 /* One shot, path B LOK & IQK */
1638                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1639                         "One shot, path A LOK & IQK!\n");
1640                 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1641                 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1642
1643                 /* delay x ms */
1644                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1645                         "Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1646                 mdelay(IQK_DELAY_TIME * 10);
1647
1648                 /* Check failed */
1649                 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1650                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1651                 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1652                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1653                 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1654                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1655                 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1656                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1657                 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1658                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1659                 if (!(regeac & BIT(31)) &&
1660                     (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1661                         result |= 0x01;
1662                 else
1663                         continue;
1664                 if (!(regeac & BIT(30)) &&
1665                     (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1666                         result |= 0x02;
1667                         break;
1668                 } else {
1669                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1670                                 "Path B Rx IQK fail!!\n");
1671                 }
1672         }
1673
1674         /* path B PA off */
1675         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1676                       rtlphy->iqk_bb_backup[0]);
1677         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1678                       rtlphy->iqk_bb_backup[2]);
1679         return result;
1680 }
1681
1682 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1683                                             u32 *adda_reg, u32 *adda_backup,
1684                                             u32 regnum)
1685 {
1686         struct rtl_priv *rtlpriv = rtl_priv(hw);
1687         u32 i;
1688
1689         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save ADDA parameters.\n");
1690         for (i = 0; i < regnum; i++)
1691                 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1692 }
1693
1694 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1695         u32 *macreg, u32 *macbackup)
1696 {
1697         struct rtl_priv *rtlpriv = rtl_priv(hw);
1698         u32 i;
1699
1700         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save MAC parameters.\n");
1701         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1702                 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1703         macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1704 }
1705
1706 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1707                                               u32 *adda_reg, u32 *adda_backup,
1708                                               u32 regnum)
1709 {
1710         struct rtl_priv *rtlpriv = rtl_priv(hw);
1711         u32 i;
1712
1713         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1714                 "Reload ADDA power saving parameters !\n");
1715         for (i = 0; i < regnum; i++)
1716                 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1717 }
1718
1719 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1720                                              u32 *macreg, u32 *macbackup)
1721 {
1722         struct rtl_priv *rtlpriv = rtl_priv(hw);
1723         u32 i;
1724
1725         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Reload MAC parameters !\n");
1726         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1727                 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1728         rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1729 }
1730
1731 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1732                 u32 *adda_reg, bool patha_on, bool is2t)
1733 {
1734         struct rtl_priv *rtlpriv = rtl_priv(hw);
1735         u32 pathon;
1736         u32 i;
1737
1738         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "ADDA ON.\n");
1739         pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1740         if (patha_on)
1741                 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1742                     0x04db25a4 : 0x0b1b25a4;
1743         for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1744                 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1745 }
1746
1747 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1748                                                 u32 *macreg, u32 *macbackup)
1749 {
1750         struct rtl_priv *rtlpriv = rtl_priv(hw);
1751         u32 i;
1752
1753         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "MAC settings for Calibration.\n");
1754         rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1755
1756         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1757                 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1758                                (~BIT(3))));
1759         rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1760 }
1761
1762 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1763 {
1764         struct rtl_priv *rtlpriv = rtl_priv(hw);
1765         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A standby mode!\n");
1766
1767         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1768         rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1769         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1770 }
1771
1772 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1773 {
1774         struct rtl_priv *rtlpriv = rtl_priv(hw);
1775         u32 mode;
1776
1777         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1778                 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1779         mode = pi_mode ? 0x01000100 : 0x01000000;
1780         rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1781         rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1782 }
1783
1784 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1785                                      u8 t, bool is2t)
1786 {
1787         struct rtl_priv *rtlpriv = rtl_priv(hw);
1788         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1789         u32 i;
1790         u8 patha_ok, pathb_ok;
1791         static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1792                 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1793                 0xe78, 0xe7c, 0xe80, 0xe84,
1794                 0xe88, 0xe8c, 0xed0, 0xed4,
1795                 0xed8, 0xedc, 0xee0, 0xeec
1796         };
1797         static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1798                 0x522, 0x550, 0x551, 0x040
1799         };
1800         static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1801                 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1802                 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1803                 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1804                 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1805                 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1806         };
1807         const u32 retrycount = 2;
1808         u32 bbvalue;
1809
1810         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 2.4G :Start!!!\n");
1811         if (t == 0) {
1812                 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1813                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1814                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1815                         is2t ? "2T2R" : "1T1R");
1816
1817                 /*  Save ADDA parameters, turn Path A ADDA on */
1818                 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1819                         rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1820                 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1821                         rtlphy->iqk_mac_backup);
1822                 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1823                         rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1824         }
1825         _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1826         if (t == 0)
1827                 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1828                                 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1829
1830         /*  Switch BB to PI mode to do IQ Calibration. */
1831         if (!rtlphy->rfpi_enable)
1832                 _rtl92d_phy_pimode_switch(hw, true);
1833
1834         rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1835         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1836         rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1837         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1838         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1839         if (is2t) {
1840                 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1841                               0x00010000);
1842                 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1843                               0x00010000);
1844         }
1845         /* MAC settings */
1846         _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1847                                             rtlphy->iqk_mac_backup);
1848         /* Page B init */
1849         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1850         if (is2t)
1851                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1852         /* IQ calibration setting */
1853         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1854         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1855         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1856         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1857         for (i = 0; i < retrycount; i++) {
1858                 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1859                 if (patha_ok == 0x03) {
1860                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1861                                 "Path A IQK Success!!\n");
1862                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1863                                         0x3FF0000) >> 16;
1864                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1865                                         0x3FF0000) >> 16;
1866                         result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1867                                         0x3FF0000) >> 16;
1868                         result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1869                                         0x3FF0000) >> 16;
1870                         break;
1871                 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
1872                         /* Tx IQK OK */
1873                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1874                                 "Path A IQK Only  Tx Success!!\n");
1875
1876                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1877                                         0x3FF0000) >> 16;
1878                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1879                                         0x3FF0000) >> 16;
1880                 }
1881         }
1882         if (0x00 == patha_ok)
1883                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK failed!!\n");
1884         if (is2t) {
1885                 _rtl92d_phy_patha_standby(hw);
1886                 /* Turn Path B ADDA on */
1887                 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1888                 for (i = 0; i < retrycount; i++) {
1889                         pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1890                         if (pathb_ok == 0x03) {
1891                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1892                                         "Path B IQK Success!!\n");
1893                                 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1894                                                MASKDWORD) & 0x3FF0000) >> 16;
1895                                 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1896                                                MASKDWORD) & 0x3FF0000) >> 16;
1897                                 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1898                                                MASKDWORD) & 0x3FF0000) >> 16;
1899                                 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1900                                                MASKDWORD) & 0x3FF0000) >> 16;
1901                                 break;
1902                         } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1903                                 /* Tx IQK OK */
1904                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1905                                         "Path B Only Tx IQK Success!!\n");
1906                                 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1907                                                MASKDWORD) & 0x3FF0000) >> 16;
1908                                 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1909                                                MASKDWORD) & 0x3FF0000) >> 16;
1910                         }
1911                 }
1912                 if (0x00 == pathb_ok)
1913                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1914                                 "Path B IQK failed!!\n");
1915         }
1916
1917         /* Back to BB mode, load original value */
1918         RTPRINT(rtlpriv, FINIT, INIT_IQK,
1919                 "IQK:Back to BB mode, load original value!\n");
1920
1921         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1922         if (t != 0) {
1923                 /* Switch back BB to SI mode after finish IQ Calibration. */
1924                 if (!rtlphy->rfpi_enable)
1925                         _rtl92d_phy_pimode_switch(hw, false);
1926                 /* Reload ADDA power saving parameters */
1927                 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
1928                                 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1929                 /* Reload MAC parameters */
1930                 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
1931                                         rtlphy->iqk_mac_backup);
1932                 if (is2t)
1933                         _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1934                                                           rtlphy->iqk_bb_backup,
1935                                                           IQK_BB_REG_NUM);
1936                 else
1937                         _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1938                                                           rtlphy->iqk_bb_backup,
1939                                                           IQK_BB_REG_NUM - 1);
1940                 /* load 0xe30 IQC default value */
1941                 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1942                 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1943         }
1944         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
1945 }
1946
1947 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
1948                                                long result[][8], u8 t)
1949 {
1950         struct rtl_priv *rtlpriv = rtl_priv(hw);
1951         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1952         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1953         u8 patha_ok, pathb_ok;
1954         static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1955                 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1956                 0xe78, 0xe7c, 0xe80, 0xe84,
1957                 0xe88, 0xe8c, 0xed0, 0xed4,
1958                 0xed8, 0xedc, 0xee0, 0xeec
1959         };
1960         static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1961                 0x522, 0x550, 0x551, 0x040
1962         };
1963         static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1964                 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1965                 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1966                 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1967                 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1968                 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1969         };
1970         u32 bbvalue;
1971         bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1972
1973         /* Note: IQ calibration must be performed after loading
1974          * PHY_REG.txt , and radio_a, radio_b.txt */
1975
1976         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 5G NORMAL:Start!!!\n");
1977         mdelay(IQK_DELAY_TIME * 20);
1978         if (t == 0) {
1979                 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1980                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1981                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1982                         is2t ? "2T2R" : "1T1R");
1983                 /* Save ADDA parameters, turn Path A ADDA on */
1984                 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1985                                                 rtlphy->adda_backup,
1986                                                 IQK_ADDA_REG_NUM);
1987                 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1988                                                rtlphy->iqk_mac_backup);
1989                 if (is2t)
1990                         _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1991                                                         rtlphy->iqk_bb_backup,
1992                                                         IQK_BB_REG_NUM);
1993                 else
1994                         _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1995                                                         rtlphy->iqk_bb_backup,
1996                                                         IQK_BB_REG_NUM - 1);
1997         }
1998         _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1999         /* MAC settings */
2000         _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2001                         rtlphy->iqk_mac_backup);
2002         if (t == 0)
2003                 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2004                         RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2005         /*  Switch BB to PI mode to do IQ Calibration. */
2006         if (!rtlphy->rfpi_enable)
2007                 _rtl92d_phy_pimode_switch(hw, true);
2008         rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2009         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
2010         rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
2011         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
2012         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2013
2014         /* Page B init */
2015         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
2016         if (is2t)
2017                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
2018         /* IQ calibration setting  */
2019         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
2020         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2021         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
2022         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
2023         patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2024         if (patha_ok == 0x03) {
2025                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Success!!\n");
2026                 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2027                                 0x3FF0000) >> 16;
2028                 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2029                                 0x3FF0000) >> 16;
2030                 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
2031                                 0x3FF0000) >> 16;
2032                 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
2033                                 0x3FF0000) >> 16;
2034         } else if (patha_ok == 0x01) {  /* Tx IQK OK */
2035                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2036                         "Path A IQK Only  Tx Success!!\n");
2037
2038                 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2039                                 0x3FF0000) >> 16;
2040                 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2041                                 0x3FF0000) >> 16;
2042         } else {
2043                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Fail!!\n");
2044         }
2045         if (is2t) {
2046                 /* _rtl92d_phy_patha_standby(hw); */
2047                 /* Turn Path B ADDA on  */
2048                 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2049                 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2050                 if (pathb_ok == 0x03) {
2051                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2052                                 "Path B IQK Success!!\n");
2053                         result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2054                              0x3FF0000) >> 16;
2055                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2056                              0x3FF0000) >> 16;
2057                         result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2058                              0x3FF0000) >> 16;
2059                         result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2060                              0x3FF0000) >> 16;
2061                 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2062                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2063                                 "Path B Only Tx IQK Success!!\n");
2064                         result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2065                              0x3FF0000) >> 16;
2066                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2067                              0x3FF0000) >> 16;
2068                 } else {
2069                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2070                                 "Path B IQK failed!!\n");
2071                 }
2072         }
2073
2074         /* Back to BB mode, load original value */
2075         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2076                 "IQK:Back to BB mode, load original value!\n");
2077         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2078         if (t != 0) {
2079                 if (is2t)
2080                         _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2081                                                           rtlphy->iqk_bb_backup,
2082                                                           IQK_BB_REG_NUM);
2083                 else
2084                         _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2085                                                           rtlphy->iqk_bb_backup,
2086                                                           IQK_BB_REG_NUM - 1);
2087                 /* Reload MAC parameters */
2088                 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2089                                 rtlphy->iqk_mac_backup);
2090                 /*  Switch back BB to SI mode after finish IQ Calibration. */
2091                 if (!rtlphy->rfpi_enable)
2092                         _rtl92d_phy_pimode_switch(hw, false);
2093                 /* Reload ADDA power saving parameters */
2094                 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2095                                                   rtlphy->adda_backup,
2096                                                   IQK_ADDA_REG_NUM);
2097         }
2098         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
2099 }
2100
2101 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2102         long result[][8], u8 c1, u8 c2)
2103 {
2104         struct rtl_priv *rtlpriv = rtl_priv(hw);
2105         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2106         u32 i, j, diff, sim_bitmap, bound;
2107         u8 final_candidate[2] = {0xFF, 0xFF};   /* for path A and path B */
2108         bool bresult = true;
2109         bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2110
2111         if (is2t)
2112                 bound = 8;
2113         else
2114                 bound = 4;
2115         sim_bitmap = 0;
2116         for (i = 0; i < bound; i++) {
2117                 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2118                        result[c2][i]) : (result[c2][i] - result[c1][i]);
2119                 if (diff > MAX_TOLERANCE_92D) {
2120                         if ((i == 2 || i == 6) && !sim_bitmap) {
2121                                 if (result[c1][i] + result[c1][i + 1] == 0)
2122                                         final_candidate[(i / 4)] = c2;
2123                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2124                                         final_candidate[(i / 4)] = c1;
2125                                 else
2126                                         sim_bitmap = sim_bitmap | (1 << i);
2127                         } else {
2128                                 sim_bitmap = sim_bitmap | (1 << i);
2129                         }
2130                 }
2131         }
2132         if (sim_bitmap == 0) {
2133                 for (i = 0; i < (bound / 4); i++) {
2134                         if (final_candidate[i] != 0xFF) {
2135                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2136                                         result[3][j] =
2137                                                  result[final_candidate[i]][j];
2138                                 bresult = false;
2139                         }
2140                 }
2141                 return bresult;
2142         }
2143         if (!(sim_bitmap & 0x0F)) { /* path A OK */
2144                 for (i = 0; i < 4; i++)
2145                         result[3][i] = result[c1][i];
2146         } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2147                 for (i = 0; i < 2; i++)
2148                         result[3][i] = result[c1][i];
2149         }
2150         if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2151                 for (i = 4; i < 8; i++)
2152                         result[3][i] = result[c1][i];
2153         } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2154                 for (i = 4; i < 6; i++)
2155                         result[3][i] = result[c1][i];
2156         }
2157         return false;
2158 }
2159
2160 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2161                                               bool iqk_ok, long result[][8],
2162                                               u8 final_candidate, bool txonly)
2163 {
2164         struct rtl_priv *rtlpriv = rtl_priv(hw);
2165         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2166         u32 oldval_0, val_x, tx0_a, reg;
2167         long val_y, tx0_c;
2168         bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2169             rtlhal->macphymode == DUALMAC_DUALPHY;
2170
2171         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2172                 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2173         if (final_candidate == 0xFF) {
2174                 return;
2175         } else if (iqk_ok) {
2176                 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2177                         MASKDWORD) >> 22) & 0x3FF;      /* OFDM0_D */
2178                 val_x = result[final_candidate][0];
2179                 if ((val_x & 0x00000200) != 0)
2180                         val_x = val_x | 0xFFFFFC00;
2181                 tx0_a = (val_x * oldval_0) >> 8;
2182                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2183                         "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2184                         val_x, tx0_a, oldval_0);
2185                 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2186                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2187                               ((val_x * oldval_0 >> 7) & 0x1));
2188                 val_y = result[final_candidate][1];
2189                 if ((val_y & 0x00000200) != 0)
2190                         val_y = val_y | 0xFFFFFC00;
2191                 /* path B IQK result + 3 */
2192                 if (rtlhal->interfaceindex == 1 &&
2193                         rtlhal->current_bandtype == BAND_ON_5G)
2194                         val_y += 3;
2195                 tx0_c = (val_y * oldval_0) >> 8;
2196                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2197                         "Y = 0x%lx, tx0_c = 0x%lx\n",
2198                         val_y, tx0_c);
2199                 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2200                               ((tx0_c & 0x3C0) >> 6));
2201                 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2202                               (tx0_c & 0x3F));
2203                 if (is2t)
2204                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2205                                       ((val_y * oldval_0 >> 7) & 0x1));
2206                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2207                         rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2208                                       MASKDWORD));
2209                 if (txonly) {
2210                         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "only Tx OK\n");
2211                         return;
2212                 }
2213                 reg = result[final_candidate][2];
2214                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2215                 reg = result[final_candidate][3] & 0x3F;
2216                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2217                 reg = (result[final_candidate][3] >> 6) & 0xF;
2218                 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2219         }
2220 }
2221
2222 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2223         bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2224 {
2225         struct rtl_priv *rtlpriv = rtl_priv(hw);
2226         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2227         u32 oldval_1, val_x, tx1_a, reg;
2228         long val_y, tx1_c;
2229
2230         RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2231                 iqk_ok ? "Success" : "Failed");
2232         if (final_candidate == 0xFF) {
2233                 return;
2234         } else if (iqk_ok) {
2235                 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2236                                           MASKDWORD) >> 22) & 0x3FF;
2237                 val_x = result[final_candidate][4];
2238                 if ((val_x & 0x00000200) != 0)
2239                         val_x = val_x | 0xFFFFFC00;
2240                 tx1_a = (val_x * oldval_1) >> 8;
2241                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2242                         val_x, tx1_a);
2243                 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2244                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2245                               ((val_x * oldval_1 >> 7) & 0x1));
2246                 val_y = result[final_candidate][5];
2247                 if ((val_y & 0x00000200) != 0)
2248                         val_y = val_y | 0xFFFFFC00;
2249                 if (rtlhal->current_bandtype == BAND_ON_5G)
2250                         val_y += 3;
2251                 tx1_c = (val_y * oldval_1) >> 8;
2252                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2253                         val_y, tx1_c);
2254                 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2255                               ((tx1_c & 0x3C0) >> 6));
2256                 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2257                               (tx1_c & 0x3F));
2258                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2259                               ((val_y * oldval_1 >> 7) & 0x1));
2260                 if (txonly)
2261                         return;
2262                 reg = result[final_candidate][6];
2263                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2264                 reg = result[final_candidate][7] & 0x3F;
2265                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2266                 reg = (result[final_candidate][7] >> 6) & 0xF;
2267                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2268         }
2269 }
2270
2271 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2272 {
2273         struct rtl_priv *rtlpriv = rtl_priv(hw);
2274         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2275         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2276         long result[4][8];
2277         u8 i, final_candidate, indexforchannel;
2278         bool patha_ok, pathb_ok;
2279         long rege94, rege9c, regea4, regeac, regeb4;
2280         long regebc, regec4, regecc, regtmp = 0;
2281         bool is12simular, is13simular, is23simular;
2282         unsigned long flag = 0;
2283
2284         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2285                 "IQK:Start!!!channel %d\n", rtlphy->current_channel);
2286         for (i = 0; i < 8; i++) {
2287                 result[0][i] = 0;
2288                 result[1][i] = 0;
2289                 result[2][i] = 0;
2290                 result[3][i] = 0;
2291         }
2292         final_candidate = 0xff;
2293         patha_ok = false;
2294         pathb_ok = false;
2295         is12simular = false;
2296         is23simular = false;
2297         is13simular = false;
2298         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2299                 "IQK !!!currentband %d\n", rtlhal->current_bandtype);
2300         rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2301         for (i = 0; i < 3; i++) {
2302                 if (rtlhal->current_bandtype == BAND_ON_5G) {
2303                         _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2304                 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2305                         if (IS_92D_SINGLEPHY(rtlhal->version))
2306                                 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2307                         else
2308                                 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2309                 }
2310                 if (i == 1) {
2311                         is12simular = _rtl92d_phy_simularity_compare(hw, result,
2312                                                                      0, 1);
2313                         if (is12simular) {
2314                                 final_candidate = 0;
2315                                 break;
2316                         }
2317                 }
2318                 if (i == 2) {
2319                         is13simular = _rtl92d_phy_simularity_compare(hw, result,
2320                                                                      0, 2);
2321                         if (is13simular) {
2322                                 final_candidate = 0;
2323                                 break;
2324                         }
2325                         is23simular = _rtl92d_phy_simularity_compare(hw, result,
2326                                                                      1, 2);
2327                         if (is23simular) {
2328                                 final_candidate = 1;
2329                         } else {
2330                                 for (i = 0; i < 8; i++)
2331                                         regtmp += result[3][i];
2332
2333                                 if (regtmp != 0)
2334                                         final_candidate = 3;
2335                                 else
2336                                         final_candidate = 0xFF;
2337                         }
2338                 }
2339         }
2340         rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2341         for (i = 0; i < 4; i++) {
2342                 rege94 = result[i][0];
2343                 rege9c = result[i][1];
2344                 regea4 = result[i][2];
2345                 regeac = result[i][3];
2346                 regeb4 = result[i][4];
2347                 regebc = result[i][5];
2348                 regec4 = result[i][6];
2349                 regecc = result[i][7];
2350                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2351                         "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2352                         rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2353                         regecc);
2354         }
2355         if (final_candidate != 0xff) {
2356                 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2357                 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2358                 regea4 = result[final_candidate][2];
2359                 regeac = result[final_candidate][3];
2360                 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2361                 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2362                 regec4 = result[final_candidate][6];
2363                 regecc = result[final_candidate][7];
2364                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2365                         "IQK: final_candidate is %x\n", final_candidate);
2366                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2367                         "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2368                         rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2369                         regecc);
2370                 patha_ok = pathb_ok = true;
2371         } else {
2372                 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2373                 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;   /* Y default value */
2374         }
2375         if ((rege94 != 0) /*&&(regea4 != 0) */)
2376                 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2377                                 final_candidate, (regea4 == 0));
2378         if (IS_92D_SINGLEPHY(rtlhal->version)) {
2379                 if ((regeb4 != 0) /*&&(regec4 != 0) */)
2380                         _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2381                                                 final_candidate, (regec4 == 0));
2382         }
2383         if (final_candidate != 0xFF) {
2384                 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2385                                   rtlphy->current_channel);
2386
2387                 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2388                         rtlphy->iqk_matrix[indexforchannel].
2389                                 value[0][i] = result[final_candidate][i];
2390                 rtlphy->iqk_matrix[indexforchannel].iqk_done =
2391                         true;
2392
2393                 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2394                          "IQK OK indexforchannel %d\n", indexforchannel);
2395         }
2396 }
2397
2398 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2399 {
2400         struct rtl_priv *rtlpriv = rtl_priv(hw);
2401         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2402         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2403         u8 indexforchannel;
2404
2405         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2406         /*------Do IQK for normal chip and test chip 5G band------- */
2407         indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2408         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2409                  indexforchannel,
2410                  rtlphy->iqk_matrix[indexforchannel].iqk_done);
2411         if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
2412                 rtlphy->need_iqk) {
2413                 /* Re Do IQK. */
2414                 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2415                          "Do IQK Matrix reg for channel:%d....\n", channel);
2416                 rtl92d_phy_iq_calibrate(hw);
2417         } else {
2418                 /* Just load the value. */
2419                 /* 2G band just load once. */
2420                 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2421                     indexforchannel == 0) || indexforchannel > 0) {
2422                         RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2423                                  "Just Read IQK Matrix reg for channel:%d....\n",
2424                                  channel);
2425                         if ((rtlphy->iqk_matrix[indexforchannel].
2426                              value[0] != NULL)
2427                                 /*&&(regea4 != 0) */)
2428                                 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2429                                         rtlphy->iqk_matrix[
2430                                         indexforchannel].value, 0,
2431                                         (rtlphy->iqk_matrix[
2432                                         indexforchannel].value[0][2] == 0));
2433                         if (IS_92D_SINGLEPHY(rtlhal->version)) {
2434                                 if ((rtlphy->iqk_matrix[
2435                                         indexforchannel].value[0][4] != 0)
2436                                         /*&&(regec4 != 0) */)
2437                                         _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2438                                                 true,
2439                                                 rtlphy->iqk_matrix[
2440                                                 indexforchannel].value, 0,
2441                                                 (rtlphy->iqk_matrix[
2442                                                 indexforchannel].value[0][6]
2443                                                 == 0));
2444                         }
2445                 }
2446         }
2447         rtlphy->need_iqk = false;
2448         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2449 }
2450
2451 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2452 {
2453         u32 ret;
2454
2455         if (val1 >= val2)
2456                 ret = val1 - val2;
2457         else
2458                 ret = val2 - val1;
2459         return ret;
2460 }
2461
2462 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2463 {
2464
2465         int i;
2466
2467         for (i = 0; i < sizeof(channel5g); i++)
2468                 if (channel == channel5g[i])
2469                         return true;
2470         return false;
2471 }
2472
2473 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2474                                        u32 *targetchnl, u32 * curvecount_val,
2475                                        bool is5g, u32 *curveindex)
2476 {
2477         struct rtl_priv *rtlpriv = rtl_priv(hw);
2478         u32 smallest_abs_val = 0xffffffff, u4tmp;
2479         u8 i, j;
2480         u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2481
2482         for (i = 0; i < chnl_num; i++) {
2483                 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2484                         continue;
2485                 curveindex[i] = 0;
2486                 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2487                         u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2488                                 curvecount_val[j]);
2489
2490                         if (u4tmp < smallest_abs_val) {
2491                                 curveindex[i] = j;
2492                                 smallest_abs_val = u4tmp;
2493                         }
2494                 }
2495                 smallest_abs_val = 0xffffffff;
2496                 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2497                         i, curveindex[i]);
2498         }
2499 }
2500
2501 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2502                 u8 channel)
2503 {
2504         struct rtl_priv *rtlpriv = rtl_priv(hw);
2505         u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2506                 BAND_ON_5G ? RF90_PATH_A :
2507                 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2508                 RF90_PATH_B : RF90_PATH_A;
2509         u32 u4tmp = 0, u4regvalue = 0;
2510         bool bneed_powerdown_radio = false;
2511
2512         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2513         RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2514                 rtlpriv->rtlhal.current_bandtype);
2515         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "channel = %d\n", channel);
2516         if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2517                 u4tmp = curveindex_5g[channel-1];
2518                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2519                         "ver 1 set RF-A, 5G,    0x28 = 0x%x !!\n", u4tmp);
2520                 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2521                         rtlpriv->rtlhal.interfaceindex == 1) {
2522                         bneed_powerdown_radio =
2523                                 rtl92d_phy_enable_anotherphy(hw, false);
2524                         rtlpriv->rtlhal.during_mac1init_radioa = true;
2525                         /* asume no this case */
2526                         if (bneed_powerdown_radio)
2527                                 _rtl92d_phy_enable_rf_env(hw, erfpath,
2528                                                           &u4regvalue);
2529                 }
2530                 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2531                 if (bneed_powerdown_radio)
2532                         _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2533                 if (rtlpriv->rtlhal.during_mac1init_radioa)
2534                         rtl92d_phy_powerdown_anotherphy(hw, false);
2535         } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2536                 u4tmp = curveindex_2g[channel-1];
2537                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2538                         "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
2539                 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2540                         rtlpriv->rtlhal.interfaceindex == 0) {
2541                         bneed_powerdown_radio =
2542                                 rtl92d_phy_enable_anotherphy(hw, true);
2543                         rtlpriv->rtlhal.during_mac0init_radiob = true;
2544                         if (bneed_powerdown_radio)
2545                                 _rtl92d_phy_enable_rf_env(hw, erfpath,
2546                                                           &u4regvalue);
2547                 }
2548                 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2549                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2550                         "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
2551                         rtl_get_rfreg(hw,  erfpath, RF_SYN_G4, 0x3f800));
2552                 if (bneed_powerdown_radio)
2553                         _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2554                 if (rtlpriv->rtlhal.during_mac0init_radiob)
2555                         rtl92d_phy_powerdown_anotherphy(hw, true);
2556         }
2557         RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2558 }
2559
2560 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2561 {
2562         struct rtl_priv *rtlpriv = rtl_priv(hw);
2563         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2564         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2565         u8 tmpreg, index, rf_mode[2];
2566         u8 path = is2t ? 2 : 1;
2567         u8 i;
2568         u32 u4tmp, offset;
2569         u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2570         u16 timeout = 800, timecount = 0;
2571
2572         /* Check continuous TX and Packet TX */
2573         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2574         /* if Deal with contisuous TX case, disable all continuous TX */
2575         /* if Deal with Packet TX case, block all queues */
2576         if ((tmpreg & 0x70) != 0)
2577                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2578         else
2579                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2580         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2581         for (index = 0; index < path; index++) {
2582                 /* 1. Read original RF mode */
2583                 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2584                 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2585                 /* 2. Set RF mode = standby mode */
2586                 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2587                               RFREG_OFFSET_MASK, 0x010000);
2588                 if (rtlpci->init_ready) {
2589                         /* switch CV-curve control by LC-calibration */
2590                         rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2591                                       BIT(17), 0x0);
2592                         /* 4. Set LC calibration begin */
2593                         rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2594                                       0x08000, 0x01);
2595                 }
2596                 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2597                                   RFREG_OFFSET_MASK);
2598                 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2599                         mdelay(50);
2600                         timecount += 50;
2601                         u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2602                                               RF_SYN_G6, RFREG_OFFSET_MASK);
2603                 }
2604                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2605                         "PHY_LCK finish delay for %d ms=2\n", timecount);
2606                 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2607                 if (index == 0 && rtlhal->interfaceindex == 0) {
2608                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2609                                 "path-A / 5G LCK\n");
2610                 } else {
2611                         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2612                                 "path-B / 2.4G LCK\n");
2613                 }
2614                 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2615                 /* Set LC calibration off */
2616                 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2617                               0x08000, 0x0);
2618                 RTPRINT(rtlpriv, FINIT, INIT_IQK,  "set RF 0x18[15] = 0\n");
2619                 /* save Curve-counting number */
2620                 for (i = 0; i < CV_CURVE_CNT; i++) {
2621                         u32 readval = 0, readval2 = 0;
2622                         rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2623                                       0x7f, i);
2624
2625                         rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2626                                 RFREG_OFFSET_MASK, 0x0);
2627                         readval = rtl_get_rfreg(hw, (enum radio_path)index,
2628                                           0x4F, RFREG_OFFSET_MASK);
2629                         curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2630                         /* reg 0x4f [4:0] */
2631                         /* reg 0x50 [19:10] */
2632                         readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2633                                                  0x50, 0xffc00);
2634                         curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2635                                                  readval2);
2636                 }
2637                 if (index == 0 && rtlhal->interfaceindex == 0)
2638                         _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2639                                                    curvecount_val,
2640                                                    true, curveindex_5g);
2641                 else
2642                         _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2643                                                    curvecount_val,
2644                                                    false, curveindex_2g);
2645                 /* switch CV-curve control mode */
2646                 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2647                               BIT(17), 0x1);
2648         }
2649
2650         /* Restore original situation  */
2651         for (index = 0; index < path; index++) {
2652                 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2653                 rtl_write_byte(rtlpriv, offset, 0x50);
2654                 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2655         }
2656         if ((tmpreg & 0x70) != 0)
2657                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2658         else /*Deal with Packet TX case */
2659                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2660         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2661         _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2662 }
2663
2664 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2665 {
2666         struct rtl_priv *rtlpriv = rtl_priv(hw);
2667
2668         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "cosa PHY_LCK ver=2\n");
2669         _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2670 }
2671
2672 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2673 {
2674         struct rtl_priv *rtlpriv = rtl_priv(hw);
2675         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2676         struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2677         u32 timeout = 2000, timecount = 0;
2678
2679         while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2680                 udelay(50);
2681                 timecount += 50;
2682         }
2683
2684         rtlphy->lck_inprogress = true;
2685         RTPRINT(rtlpriv, FINIT, INIT_IQK,
2686                 "LCK:Start!!! currentband %x delay %d ms\n",
2687                 rtlhal->current_bandtype, timecount);
2688         if (IS_92D_SINGLEPHY(rtlhal->version)) {
2689                 _rtl92d_phy_lc_calibrate(hw, true);
2690         } else {
2691                 /* For 1T1R */
2692                 _rtl92d_phy_lc_calibrate(hw, false);
2693         }
2694         rtlphy->lck_inprogress = false;
2695         RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LCK:Finish!!!\n");
2696 }
2697
2698 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
2699 {
2700         return;
2701 }
2702
2703 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2704                 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2705                 u32 para1, u32 para2, u32 msdelay)
2706 {
2707         struct swchnlcmd *pcmd;
2708
2709         if (cmdtable == NULL) {
2710                 RT_ASSERT(false, "cmdtable cannot be NULL\n");
2711                 return false;
2712         }
2713         if (cmdtableidx >= cmdtablesz)
2714                 return false;
2715
2716         pcmd = cmdtable + cmdtableidx;
2717         pcmd->cmdid = cmdid;
2718         pcmd->para1 = para1;
2719         pcmd->para2 = para2;
2720         pcmd->msdelay = msdelay;
2721         return true;
2722 }
2723
2724 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2725 {
2726         struct rtl_priv *rtlpriv = rtl_priv(hw);
2727         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2728         u8 i;
2729
2730         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2731                  "settings regs %d default regs %d\n",
2732                  (int)(sizeof(rtlphy->iqk_matrix) /
2733                        sizeof(struct iqk_matrix_regs)),
2734                  IQK_MATRIX_REG_NUM);
2735         /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2736         for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2737                 rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2738                 rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2739                 rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2740                 rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2741                 rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2742                 rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2743                 rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2744                 rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2745                 rtlphy->iqk_matrix[i].iqk_done = false;
2746         }
2747 }
2748
2749 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2750                                              u8 channel, u8 *stage, u8 *step,
2751                                              u32 *delay)
2752 {
2753         struct rtl_priv *rtlpriv = rtl_priv(hw);
2754         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2755         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2756         u32 precommoncmdcnt;
2757         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2758         u32 postcommoncmdcnt;
2759         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2760         u32 rfdependcmdcnt;
2761         struct swchnlcmd *currentcmd = NULL;
2762         u8 rfpath;
2763         u8 num_total_rfpath = rtlphy->num_total_rfpath;
2764
2765         precommoncmdcnt = 0;
2766         _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2767                                          MAX_PRECMD_CNT,
2768                                          CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2769         _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2770                                          MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2771         postcommoncmdcnt = 0;
2772         _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2773                                          MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2774         rfdependcmdcnt = 0;
2775         _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2776                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2777                                          RF_CHNLBW, channel, 0);
2778         _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2779                                          MAX_RFDEPENDCMD_CNT, CMDID_END,
2780                                          0, 0, 0);
2781
2782         do {
2783                 switch (*stage) {
2784                 case 0:
2785                         currentcmd = &precommoncmd[*step];
2786                         break;
2787                 case 1:
2788                         currentcmd = &rfdependcmd[*step];
2789                         break;
2790                 case 2:
2791                         currentcmd = &postcommoncmd[*step];
2792                         break;
2793                 }
2794                 if (currentcmd->cmdid == CMDID_END) {
2795                         if ((*stage) == 2) {
2796                                 return true;
2797                         } else {
2798                                 (*stage)++;
2799                                 (*step) = 0;
2800                                 continue;
2801                         }
2802                 }
2803                 switch (currentcmd->cmdid) {
2804                 case CMDID_SET_TXPOWEROWER_LEVEL:
2805                         rtl92d_phy_set_txpower_level(hw, channel);
2806                         break;
2807                 case CMDID_WRITEPORT_ULONG:
2808                         rtl_write_dword(rtlpriv, currentcmd->para1,
2809                                         currentcmd->para2);
2810                         break;
2811                 case CMDID_WRITEPORT_USHORT:
2812                         rtl_write_word(rtlpriv, currentcmd->para1,
2813                                        (u16)currentcmd->para2);
2814                         break;
2815                 case CMDID_WRITEPORT_UCHAR:
2816                         rtl_write_byte(rtlpriv, currentcmd->para1,
2817                                        (u8)currentcmd->para2);
2818                         break;
2819                 case CMDID_RF_WRITEREG:
2820                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2821                                 rtlphy->rfreg_chnlval[rfpath] =
2822                                         ((rtlphy->rfreg_chnlval[rfpath] &
2823                                         0xffffff00) | currentcmd->para2);
2824                                 if (rtlpriv->rtlhal.current_bandtype ==
2825                                     BAND_ON_5G) {
2826                                         if (currentcmd->para2 > 99)
2827                                                 rtlphy->rfreg_chnlval[rfpath] =
2828                                                     rtlphy->rfreg_chnlval
2829                                                     [rfpath] | (BIT(18));
2830                                         else
2831                                                 rtlphy->rfreg_chnlval[rfpath] =
2832                                                     rtlphy->rfreg_chnlval
2833                                                     [rfpath] & (~BIT(18));
2834                                         rtlphy->rfreg_chnlval[rfpath] |=
2835                                                  (BIT(16) | BIT(8));
2836                                 } else {
2837                                         rtlphy->rfreg_chnlval[rfpath] &=
2838                                                 ~(BIT(8) | BIT(16) | BIT(18));
2839                                 }
2840                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
2841                                               currentcmd->para1,
2842                                               RFREG_OFFSET_MASK,
2843                                               rtlphy->rfreg_chnlval[rfpath]);
2844                                 _rtl92d_phy_reload_imr_setting(hw, channel,
2845                                                                rfpath);
2846                         }
2847                         _rtl92d_phy_switch_rf_setting(hw, channel);
2848                         /* do IQK when all parameters are ready */
2849                         rtl92d_phy_reload_iqk_setting(hw, channel);
2850                         break;
2851                 default:
2852                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2853                                  "switch case not processed\n");
2854                         break;
2855                 }
2856                 break;
2857         } while (true);
2858         (*delay) = currentcmd->msdelay;
2859         (*step)++;
2860         return false;
2861 }
2862
2863 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2864 {
2865         struct rtl_priv *rtlpriv = rtl_priv(hw);
2866         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2867         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2868         u32 delay;
2869         u32 timeout = 1000, timecount = 0;
2870         u8 channel = rtlphy->current_channel;
2871         u32 ret_value;
2872
2873         if (rtlphy->sw_chnl_inprogress)
2874                 return 0;
2875         if (rtlphy->set_bwmode_inprogress)
2876                 return 0;
2877
2878         if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2879                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
2880                          "sw_chnl_inprogress false driver sleep or unload\n");
2881                 return 0;
2882         }
2883         while (rtlphy->lck_inprogress && timecount < timeout) {
2884                 mdelay(50);
2885                 timecount += 50;
2886         }
2887         if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2888             rtlhal->bandset == BAND_ON_BOTH) {
2889                 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2890                                           MASKDWORD);
2891                 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2892                         rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2893                 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2894                         rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2895         }
2896         switch (rtlhal->current_bandtype) {
2897         case BAND_ON_5G:
2898                 /* Get first channel error when change between
2899                  * 5G and 2.4G band. */
2900                 if (channel <= 14)
2901                         return 0;
2902                 RT_ASSERT((channel > 14), "5G but channel<=14\n");
2903                 break;
2904         case BAND_ON_2_4G:
2905                 /* Get first channel error when change between
2906                  * 5G and 2.4G band. */
2907                 if (channel > 14)
2908                         return 0;
2909                 RT_ASSERT((channel <= 14), "2G but channel>14\n");
2910                 break;
2911         default:
2912                 RT_ASSERT(false, "Invalid WirelessMode(%#x)!!\n",
2913                           rtlpriv->mac80211.mode);
2914                 break;
2915         }
2916         rtlphy->sw_chnl_inprogress = true;
2917         if (channel == 0)
2918                 channel = 1;
2919         rtlphy->sw_chnl_stage = 0;
2920         rtlphy->sw_chnl_step = 0;
2921         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
2922                  "switch to channel%d\n", rtlphy->current_channel);
2923
2924         do {
2925                 if (!rtlphy->sw_chnl_inprogress)
2926                         break;
2927                 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
2928                                                       rtlphy->current_channel,
2929                     &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
2930                         if (delay > 0)
2931                                 mdelay(delay);
2932                         else
2933                                 continue;
2934                 } else {
2935                         rtlphy->sw_chnl_inprogress = false;
2936                 }
2937                 break;
2938         } while (true);
2939         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
2940         rtlphy->sw_chnl_inprogress = false;
2941         return 1;
2942 }
2943
2944 static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
2945 {
2946         struct rtl_priv *rtlpriv = rtl_priv(hw);
2947         struct dig_t *de_digtable = &rtlpriv->dm_digtable;
2948         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2949
2950         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2951                  "--->Cmd(%#x), set_io_inprogress(%d)\n",
2952                  rtlphy->current_io_type, rtlphy->set_io_inprogress);
2953         switch (rtlphy->current_io_type) {
2954         case IO_CMD_RESUME_DM_BY_SCAN:
2955                 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2956                 rtl92d_dm_write_dig(hw);
2957                 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
2958                 break;
2959         case IO_CMD_PAUSE_DM_BY_SCAN:
2960                 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
2961                 de_digtable->cur_igvalue = 0x37;
2962                 rtl92d_dm_write_dig(hw);
2963                 break;
2964         default:
2965                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2966                          "switch case not processed\n");
2967                 break;
2968         }
2969         rtlphy->set_io_inprogress = false;
2970         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2971                  rtlphy->current_io_type);
2972 }
2973
2974 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2975 {
2976         struct rtl_priv *rtlpriv = rtl_priv(hw);
2977         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2978         bool postprocessing = false;
2979
2980         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2981                  "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2982                  iotype, rtlphy->set_io_inprogress);
2983         do {
2984                 switch (iotype) {
2985                 case IO_CMD_RESUME_DM_BY_SCAN:
2986                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2987                                  "[IO CMD] Resume DM after scan\n");
2988                         postprocessing = true;
2989                         break;
2990                 case IO_CMD_PAUSE_DM_BY_SCAN:
2991                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2992                                  "[IO CMD] Pause DM before scan\n");
2993                         postprocessing = true;
2994                         break;
2995                 default:
2996                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2997                                  "switch case not processed\n");
2998                         break;
2999                 }
3000         } while (false);
3001         if (postprocessing && !rtlphy->set_io_inprogress) {
3002                 rtlphy->set_io_inprogress = true;
3003                 rtlphy->current_io_type = iotype;
3004         } else {
3005                 return false;
3006         }
3007         rtl92d_phy_set_io(hw);
3008         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
3009         return true;
3010 }
3011
3012 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
3013 {
3014         struct rtl_priv *rtlpriv = rtl_priv(hw);
3015
3016         /* a.  SYS_CLKR 0x08[11] = 1  restore MAC clock */
3017         /* b.  SPS_CTRL 0x11[7:0] = 0x2b */
3018         if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3019                 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3020         /* c.  For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
3021         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3022         /* RF_ON_EXCEP(d~g): */
3023         /* d.  APSD_CTRL 0x600[7:0] = 0x00 */
3024         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3025         /* e.  SYS_FUNC_EN 0x02[7:0] = 0xE2  reset BB TRX function again */
3026         /* f.  SYS_FUNC_EN 0x02[7:0] = 0xE3  enable BB TRX function*/
3027         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3028         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3029         /* g.   txpause 0x522[7:0] = 0x00  enable mac tx queue */
3030         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3031 }
3032
3033 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3034 {
3035         struct rtl_priv *rtlpriv = rtl_priv(hw);
3036         u32 u4btmp;
3037         u8 delay = 5;
3038
3039         /* a.   TXPAUSE 0x522[7:0] = 0xFF  Pause MAC TX queue  */
3040         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3041         /* b.   RF path 0 offset 0x00 = 0x00  disable RF  */
3042         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3043         /* c.   APSD_CTRL 0x600[7:0] = 0x40 */
3044         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3045         /* d. APSD_CTRL 0x600[7:0] = 0x00
3046          * APSD_CTRL 0x600[7:0] = 0x00
3047          * RF path 0 offset 0x00 = 0x00
3048          * APSD_CTRL 0x600[7:0] = 0x40
3049          * */
3050         u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3051         while (u4btmp != 0 && delay > 0) {
3052                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3053                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3054                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3055                 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3056                 delay--;
3057         }
3058         if (delay == 0) {
3059                 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3060                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3061
3062                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3063                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3064                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3065                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3066                          "Fail !!! Switch RF timeout\n");
3067                 return;
3068         }
3069         /* e.   For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3070         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3071         /* f.   SPS_CTRL 0x11[7:0] = 0x22 */
3072         if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3073                 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3074         /* g.    SYS_CLKR 0x08[11] = 0  gated MAC clock */
3075 }
3076
3077 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3078                                    enum rf_pwrstate rfpwr_state)
3079 {
3080
3081         bool bresult = true;
3082         struct rtl_priv *rtlpriv = rtl_priv(hw);
3083         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3084         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3085         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3086         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3087         u8 i, queue_id;
3088         struct rtl8192_tx_ring *ring = NULL;
3089
3090         if (rfpwr_state == ppsc->rfpwr_state)
3091                 return false;
3092         switch (rfpwr_state) {
3093         case ERFON:
3094                 if ((ppsc->rfpwr_state == ERFOFF) &&
3095                     RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3096                         bool rtstatus;
3097                         u32 InitializeCount = 0;
3098                         do {
3099                                 InitializeCount++;
3100                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3101                                          "IPS Set eRf nic enable\n");
3102                                 rtstatus = rtl_ps_enable_nic(hw);
3103                         } while (!rtstatus && (InitializeCount < 10));
3104
3105                         RT_CLEAR_PS_LEVEL(ppsc,
3106                                           RT_RF_OFF_LEVL_HALT_NIC);
3107                 } else {
3108                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3109                                  "awake, sleeped:%d ms state_inap:%x\n",
3110                                  jiffies_to_msecs(jiffies -
3111                                                   ppsc->last_sleep_jiffies),
3112                                  rtlpriv->psc.state_inap);
3113                         ppsc->last_awake_jiffies = jiffies;
3114                         _rtl92d_phy_set_rfon(hw);
3115                 }
3116
3117                 if (mac->link_state == MAC80211_LINKED)
3118                         rtlpriv->cfg->ops->led_control(hw,
3119                                          LED_CTL_LINK);
3120                 else
3121                         rtlpriv->cfg->ops->led_control(hw,
3122                                          LED_CTL_NO_LINK);
3123                 break;
3124         case ERFOFF:
3125                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3126                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3127                                  "IPS Set eRf nic disable\n");
3128                         rtl_ps_disable_nic(hw);
3129                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3130                 } else {
3131                         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3132                                 rtlpriv->cfg->ops->led_control(hw,
3133                                                  LED_CTL_NO_LINK);
3134                         else
3135                                 rtlpriv->cfg->ops->led_control(hw,
3136                                                  LED_CTL_POWER_OFF);
3137                 }
3138                 break;
3139         case ERFSLEEP:
3140                 if (ppsc->rfpwr_state == ERFOFF)
3141                         return false;
3142
3143                 for (queue_id = 0, i = 0;
3144                      queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3145                         ring = &pcipriv->dev.tx_ring[queue_id];
3146                         if (skb_queue_len(&ring->queue) == 0 ||
3147                             queue_id == BEACON_QUEUE) {
3148                                 queue_id++;
3149                                 continue;
3150                         } else if (rtlpci->pdev->current_state != PCI_D0) {
3151                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3152                                          "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3153                                          i + 1, queue_id);
3154                                 break;
3155                         } else {
3156                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3157                                          "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3158                                          i + 1, queue_id,
3159                                          skb_queue_len(&ring->queue));
3160                                 udelay(10);
3161                                 i++;
3162                         }
3163
3164                         if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3165                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3166                                          "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3167                                          MAX_DOZE_WAITING_TIMES_9x, queue_id,
3168                                          skb_queue_len(&ring->queue));
3169                                 break;
3170                         }
3171                 }
3172                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3173                          "Set rfsleep awaked:%d ms\n",
3174                          jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3175                 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3176                          "sleep awaked:%d ms state_inap:%x\n",
3177                          jiffies_to_msecs(jiffies -
3178                                           ppsc->last_awake_jiffies),
3179                          rtlpriv->psc.state_inap);
3180                 ppsc->last_sleep_jiffies = jiffies;
3181                 _rtl92d_phy_set_rfsleep(hw);
3182                 break;
3183         default:
3184                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3185                          "switch case not processed\n");
3186                 bresult = false;
3187                 break;
3188         }
3189         if (bresult)
3190                 ppsc->rfpwr_state = rfpwr_state;
3191         return bresult;
3192 }
3193
3194 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3195 {
3196         struct rtl_priv *rtlpriv = rtl_priv(hw);
3197         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3198         u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3199
3200         switch (rtlhal->macphymode) {
3201         case DUALMAC_DUALPHY:
3202                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3203                          "MacPhyMode: DUALMAC_DUALPHY\n");
3204                 rtl_write_byte(rtlpriv, offset, 0xF3);
3205                 break;
3206         case SINGLEMAC_SINGLEPHY:
3207                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3208                          "MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3209                 rtl_write_byte(rtlpriv, offset, 0xF4);
3210                 break;
3211         case DUALMAC_SINGLEPHY:
3212                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3213                          "MacPhyMode: DUALMAC_SINGLEPHY\n");
3214                 rtl_write_byte(rtlpriv, offset, 0xF1);
3215                 break;
3216         }
3217 }
3218
3219 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3220 {
3221         struct rtl_priv *rtlpriv = rtl_priv(hw);
3222         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3223         struct rtl_phy *rtlphy = &(rtlpriv->phy);
3224
3225         switch (rtlhal->macphymode) {
3226         case DUALMAC_SINGLEPHY:
3227                 rtlphy->rf_type = RF_2T2R;
3228                 rtlhal->version |= RF_TYPE_2T2R;
3229                 rtlhal->bandset = BAND_ON_BOTH;
3230                 rtlhal->current_bandtype = BAND_ON_2_4G;
3231                 break;
3232
3233         case SINGLEMAC_SINGLEPHY:
3234                 rtlphy->rf_type = RF_2T2R;
3235                 rtlhal->version |= RF_TYPE_2T2R;
3236                 rtlhal->bandset = BAND_ON_BOTH;
3237                 rtlhal->current_bandtype = BAND_ON_2_4G;
3238                 break;
3239
3240         case DUALMAC_DUALPHY:
3241                 rtlphy->rf_type = RF_1T1R;
3242                 rtlhal->version &= RF_TYPE_1T1R;
3243                 /* Now we let MAC0 run on 5G band. */
3244                 if (rtlhal->interfaceindex == 0) {
3245                         rtlhal->bandset = BAND_ON_5G;
3246                         rtlhal->current_bandtype = BAND_ON_5G;
3247                 } else {
3248                         rtlhal->bandset = BAND_ON_2_4G;
3249                         rtlhal->current_bandtype = BAND_ON_2_4G;
3250                 }
3251                 break;
3252         default:
3253                 break;
3254         }
3255 }
3256
3257 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3258 {
3259         u8 group;
3260         u8 channel_info[59] = {
3261                 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3262                 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3263                 58, 60, 62, 64, 100, 102, 104, 106, 108,
3264                 110, 112, 114, 116, 118, 120, 122, 124,
3265                 126, 128, 130, 132, 134, 136, 138, 140,
3266                 149, 151, 153, 155, 157, 159, 161, 163,
3267                 165
3268         };
3269
3270         if (channel_info[chnl] <= 3)
3271                 group = 0;
3272         else if (channel_info[chnl] <= 9)
3273                 group = 1;
3274         else if (channel_info[chnl] <= 14)
3275                 group = 2;
3276         else if (channel_info[chnl] <= 44)
3277                 group = 3;
3278         else if (channel_info[chnl] <= 54)
3279                 group = 4;
3280         else if (channel_info[chnl] <= 64)
3281                 group = 5;
3282         else if (channel_info[chnl] <= 112)
3283                 group = 6;
3284         else if (channel_info[chnl] <= 126)
3285                 group = 7;
3286         else if (channel_info[chnl] <= 140)
3287                 group = 8;
3288         else if (channel_info[chnl] <= 153)
3289                 group = 9;
3290         else if (channel_info[chnl] <= 159)
3291                 group = 10;
3292         else
3293                 group = 11;
3294         return group;
3295 }
3296
3297 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3298 {
3299         struct rtl_priv *rtlpriv = rtl_priv(hw);
3300         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3301         unsigned long flags;
3302         u8 value8;
3303         u16 i;
3304         u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3305
3306         /* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3307         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3308                 value8 = rtl_read_byte(rtlpriv, mac_reg);
3309                 value8 |= BIT(1);
3310                 rtl_write_byte(rtlpriv, mac_reg, value8);
3311         } else {
3312                 value8 = rtl_read_byte(rtlpriv, mac_reg);
3313                 value8 &= (~BIT(1));
3314                 rtl_write_byte(rtlpriv, mac_reg, value8);
3315         }
3316
3317         if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3318                 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3319                 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3320         } else {
3321                 spin_lock_irqsave(&globalmutex_power, flags);
3322                 if (rtlhal->interfaceindex == 0) {
3323                         value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3324                         rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3325                 } else {
3326                         value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3327                         rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3328                 }
3329                 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3330                 spin_unlock_irqrestore(&globalmutex_power, flags);
3331                 for (i = 0; i < 200; i++) {
3332                         if ((value8 & BIT(7)) == 0) {
3333                                 break;
3334                         } else {
3335                                 udelay(500);
3336                                 spin_lock_irqsave(&globalmutex_power, flags);
3337                                 value8 = rtl_read_byte(rtlpriv,
3338                                                     REG_POWER_OFF_IN_PROCESS);
3339                                 spin_unlock_irqrestore(&globalmutex_power,
3340                                                        flags);
3341                         }
3342                 }
3343                 if (i == 200)
3344                         RT_ASSERT(false, "Another mac power off over time\n");
3345         }
3346 }
3347
3348 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3349 {
3350         struct rtl_priv *rtlpriv = rtl_priv(hw);
3351
3352         switch (rtlpriv->rtlhal.macphymode) {
3353         case DUALMAC_DUALPHY:
3354                 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3355                 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3356                 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3357                 break;
3358         case DUALMAC_SINGLEPHY:
3359                 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3360                 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3361                 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3362                 break;
3363         case SINGLEMAC_SINGLEPHY:
3364                 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3365                 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3366                 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3367                 break;
3368         default:
3369                 break;
3370         }
3371 }
3372
3373 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3374 {
3375         struct rtl_priv *rtlpriv = rtl_priv(hw);
3376         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3377         struct rtl_phy *rtlphy = &(rtlpriv->phy);
3378         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3379         u8 rfpath, i;
3380
3381         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3382         /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3383         if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3384                 /* r_select_5G for path_A/B,0x878 */
3385                 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3386                 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3387                 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3388                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3389                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3390                 }
3391                 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3392                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3393                 /* fc_area  0xd2c */
3394                 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3395                 /* 5G LAN ON */
3396                 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3397                 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3398                 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3399                               0x40000100);
3400                 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3401                               0x40000100);
3402                 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3403                         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3404                                       BIT(10) | BIT(6) | BIT(5),
3405                                       ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3406                                       (rtlefuse->eeprom_c9 & BIT(1)) |
3407                                       ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3408                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3409                                       BIT(10) | BIT(6) | BIT(5),
3410                                       ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3411                                       ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3412                                       ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3413                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3414                 } else {
3415                         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3416                                       BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3417                                       BIT(6) | BIT(5),
3418                                       ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3419                                       (rtlefuse->eeprom_c9 & BIT(1)) |
3420                                       ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3421                                       ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3422                                       ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3423                                       ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3424                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3425                                       BIT(10) | BIT(6) | BIT(5),
3426                                       ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3427                                       ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3428                                       ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3429                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3430                                       BIT(10) | BIT(6) | BIT(5),
3431                                       ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3432                                       ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3433                                       ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3434                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3435                                       BIT(31) | BIT(15), 0);
3436                 }
3437                 /* 1.5V_LDO */
3438         } else {
3439                 /* r_select_5G for path_A/B */
3440                 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3441                 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3442                 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3443                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3444                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3445                 }
3446                 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3447                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3448                 /* fc_area */
3449                 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3450                 /* 5G LAN ON */
3451                 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3452                 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3453                 if (rtlefuse->internal_pa_5g[0])
3454                         rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3455                                       0x2d4000b5);
3456                 else
3457                         rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3458                                       0x20000080);
3459                 if (rtlefuse->internal_pa_5g[1])
3460                         rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3461                                       0x2d4000b5);
3462                 else
3463                         rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3464                                       0x20000080);
3465                 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3466                         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3467                                       BIT(10) | BIT(6) | BIT(5),
3468                                       (rtlefuse->eeprom_cc & BIT(5)));
3469                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3470                                       ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3471                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3472                                       (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3473                 } else {
3474                         rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3475                                       BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3476                                       BIT(6) | BIT(5),
3477                                       (rtlefuse->eeprom_cc & BIT(5)) |
3478                                       ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3479                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3480                                       ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3481                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3482                                       ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3483                         rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3484                                       BIT(31) | BIT(15),
3485                                       ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3486                                       ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3487                 }
3488         }
3489         /* update IQK related settings */
3490         rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3491         rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3492         rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3493         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3494                       BIT(26) | BIT(24), 0x00);
3495         rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3496         rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3497         rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3498
3499         /* Update RF */
3500         for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3501              rfpath++) {
3502                 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3503                         /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3504                         rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3505                                       BIT(18), 0);
3506                         /* RF0x0b[16:14] =3b'111 */
3507                         rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3508                                       0x1c000, 0x07);
3509                 } else {
3510                         /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3511                         rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3512                                       BIT(16) | BIT(18),
3513                                       (BIT(16) | BIT(8)) >> 8);
3514                 }
3515         }
3516         /* Update for all band. */
3517         /* DMDP */
3518         if (rtlphy->rf_type == RF_1T1R) {
3519                 /* Use antenna 0,0xc04,0xd04 */
3520                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3521                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3522
3523                 /* enable ad/da clock1 for dual-phy reg0x888 */
3524                 if (rtlhal->interfaceindex == 0) {
3525                         rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3526                                       BIT(13), 0x3);
3527                 } else {
3528                         rtl92d_phy_enable_anotherphy(hw, false);
3529                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3530                                  "MAC1 use DBI to update 0x888\n");
3531                         /* 0x888 */
3532                         rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3533                                                 rtl92de_read_dword_dbi(hw,
3534                                                 RFPGA0_ADDALLOCKEN,
3535                                                 BIT(3)) | BIT(12) | BIT(13),
3536                                                 BIT(3));
3537                         rtl92d_phy_powerdown_anotherphy(hw, false);
3538                 }
3539         } else {
3540                 /* Single PHY */
3541                 /* Use antenna 0 & 1,0xc04,0xd04 */
3542                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3543                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3544                 /* disable ad/da clock1,0x888 */
3545                 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3546         }
3547         for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3548              rfpath++) {
3549                 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3550                                                 RF_CHNLBW, RFREG_OFFSET_MASK);
3551                 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3552                         RFREG_OFFSET_MASK);
3553         }
3554         for (i = 0; i < 2; i++)
3555                 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3556                          rtlphy->rfreg_chnlval[i]);
3557         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3558
3559 }
3560
3561 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3562 {
3563         struct rtl_priv *rtlpriv = rtl_priv(hw);
3564         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3565         u8 u1btmp;
3566         unsigned long flags;
3567
3568         if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3569                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3570                 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3571                 return true;
3572         }
3573         spin_lock_irqsave(&globalmutex_power, flags);
3574         if (rtlhal->interfaceindex == 0) {
3575                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3576                 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3577                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3578                 u1btmp &= MAC1_ON;
3579         } else {
3580                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3581                 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3582                 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3583                 u1btmp &= MAC0_ON;
3584         }
3585         if (u1btmp) {
3586                 spin_unlock_irqrestore(&globalmutex_power, flags);
3587                 return false;
3588         }
3589         u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3590         u1btmp |= BIT(7);
3591         rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3592         spin_unlock_irqrestore(&globalmutex_power, flags);
3593         return true;
3594 }