drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "../rtl8723com/phy_common.h"
  37 #include "dm.h"
  38 #include "../rtl8723com/dm_common.h"
  39 #include "fw.h"
  40 #include "../rtl8723com/fw_common.h"
  41 #include "led.h"
  42 #include "hw.h"
  43 #include "../pwrseqcmd.h"
  44 #include "pwrseq.h"
  45 #include "btc.h"
  46
  47 #define LLT_CONFIG      5
  48
  49 static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  50                                        u8 set_bits, u8 clear_bits)
  51 {
  52         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  53         struct rtl_priv *rtlpriv = rtl_priv(hw);
  54
  55         rtlpci->reg_bcn_ctrl_val |= set_bits;
  56         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  57
  58         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  59 }
  60
  61 static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw *hw)
  62 {
  63         struct rtl_priv *rtlpriv = rtl_priv(hw);
  64         u8 tmp1byte;
  65
  66         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  67         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  68         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  69         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  70         tmp1byte &= ~(BIT(0));
  71         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  72 }
  73
  74 static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw *hw)
  75 {
  76         struct rtl_priv *rtlpriv = rtl_priv(hw);
  77         u8 tmp1byte;
  78
  79         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  80         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  81         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  82         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  83         tmp1byte |= BIT(1);
  84         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  85 }
  86
  87 static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw *hw)
  88 {
  89         _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1));
  90 }
  91
  92 static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw *hw)
  93 {
  94         _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0);
  95 }
  96
  97 void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  98 {
  99         struct rtl_priv *rtlpriv = rtl_priv(hw);
 100         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 101         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 102
 103         switch (variable) {
 104         case HW_VAR_RCR:
 105                 *((u32 *)(val)) = rtlpci->receive_config;
 106                 break;
 107         case HW_VAR_RF_STATE:
 108                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 109                 break;
 110         case HW_VAR_FWLPS_RF_ON:{
 111                         enum rf_pwrstate rfstate;
 112                         u32 val_rcr;
 113
 114                         rtlpriv->cfg->ops->get_hw_reg(hw,
 115                                                       HW_VAR_RF_STATE,
 116                                                       (u8 *)(&rfstate));
 117                         if (rfstate == ERFOFF) {
 118                                 *((bool *)(val)) = true;
 119                         } else {
 120                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 121                                 val_rcr &= 0x00070000;
 122                                 if (val_rcr)
 123                                         *((bool *)(val)) = false;
 124                                 else
 125                                         *((bool *)(val)) = true;
 126                         }
 127                         break;
 128                 }
 129         case HW_VAR_FW_PSMODE_STATUS:
 130                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 131                 break;
 132         case HW_VAR_CORRECT_TSF:{
 133                         u64 tsf;
 134                         u32 *ptsf_low = (u32 *)&tsf;
 135                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
 136
 137                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 138                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 139
 140                         *((u64 *)(val)) = tsf;
 141
 142                         break;
 143                 }
 144         default:
 145                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 146                          "switch case %#x not processed\n", variable);
 147                 break;
 148         }
 149 }
 150
 151 void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 152 {
 153         struct rtl_priv *rtlpriv = rtl_priv(hw);
 154         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 155         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 156         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 157         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 158         u8 idx;
 159
 160         switch (variable) {
 161         case HW_VAR_ETHER_ADDR:{
 162                         for (idx = 0; idx < ETH_ALEN; idx++) {
 163                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 164                                                val[idx]);
 165                         }
 166                         break;
 167                 }
 168         case HW_VAR_BASIC_RATE:{
 169                         u16 b_rate_cfg = ((u16 *)val)[0];
 170                         u8 rate_index = 0;
 171
 172                         b_rate_cfg = b_rate_cfg & 0x15f;
 173                         b_rate_cfg |= 0x01;
 174                         rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 175                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 176                                        (b_rate_cfg >> 8) & 0xff);
 177                         while (b_rate_cfg > 0x1) {
 178                                 b_rate_cfg = (b_rate_cfg >> 1);
 179                                 rate_index++;
 180                         }
 181                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 182                                        rate_index);
 183                         break;
 184                 }
 185         case HW_VAR_BSSID:{
 186                         for (idx = 0; idx < ETH_ALEN; idx++) {
 187                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 188                                                val[idx]);
 189                         }
 190                         break;
 191                 }
 192         case HW_VAR_SIFS:{
 193                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 194                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 195
 196                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 197                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 198
 199                         if (!mac->ht_enable)
 200                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 201                                                0x0e0e);
 202                         else
 203                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 204                                                *((u16 *)val));
 205                         break;
 206                 }
 207         case HW_VAR_SLOT_TIME:{
 208                         u8 e_aci;
 209
 210                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 211                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 212
 213                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 214
 215                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 216                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 217                                                               HW_VAR_AC_PARAM,
 218                                                               (u8 *)(&e_aci));
 219                         }
 220                         break;
 221                 }
 222         case HW_VAR_ACK_PREAMBLE:{
 223                         u8 reg_tmp;
 224                         u8 short_preamble = (bool)(*(u8 *)val);
 225
 226                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 227                         if (short_preamble)
 228                                 reg_tmp |= 0x80;
 229
 230                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 231                         break;
 232                 }
 233         case HW_VAR_AMPDU_MIN_SPACE:{
 234                         u8 min_spacing_to_set;
 235                         u8 sec_min_space;
 236
 237                         min_spacing_to_set = *((u8 *)val);
 238                         if (min_spacing_to_set <= 7) {
 239                                 sec_min_space = 0;
 240
 241                                 if (min_spacing_to_set < sec_min_space)
 242                                         min_spacing_to_set = sec_min_space;
 243
 244                                 mac->min_space_cfg = ((mac->min_space_cfg &
 245                                                        0xf8) |
 246                                                       min_spacing_to_set);
 247
 248                                 *val = min_spacing_to_set;
 249
 250                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 251                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 252                                           mac->min_space_cfg);
 253
 254                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 255                                                mac->min_space_cfg);
 256                         }
 257                         break;
 258                 }
 259         case HW_VAR_SHORTGI_DENSITY:{
 260                         u8 density_to_set;
 261
 262                         density_to_set = *((u8 *)val);
 263                         mac->min_space_cfg |= (density_to_set << 3);
 264
 265                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 266                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 267                                   mac->min_space_cfg);
 268
 269                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 270                                        mac->min_space_cfg);
 271
 272                         break;
 273                 }
 274         case HW_VAR_AMPDU_FACTOR:{
 275                         u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 276                         u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
 277                         u8 factor_toset;
 278                         u8 *p_regtoset = NULL;
 279                         u8 index = 0;
 280
 281                         if ((rtlpriv->btcoexist.bt_coexistence) &&
 282                             (rtlpriv->btcoexist.bt_coexist_type ==
 283                                 BT_CSR_BC4))
 284                                 p_regtoset = regtoset_bt;
 285                         else
 286                                 p_regtoset = regtoset_normal;
 287
 288                         factor_toset = *((u8 *)val);
 289                         if (factor_toset <= 3) {
 290                                 factor_toset = (1 << (factor_toset + 2));
 291                                 if (factor_toset > 0xf)
 292                                         factor_toset = 0xf;
 293
 294                                 for (index = 0; index < 4; index++) {
 295                                         if ((p_regtoset[index] & 0xf0) >
 296                                             (factor_toset << 4))
 297                                                 p_regtoset[index] =
 298                                                     (p_regtoset[index] & 0x0f) |
 299                                                     (factor_toset << 4);
 300
 301                                         if ((p_regtoset[index] & 0x0f) >
 302                                             factor_toset)
 303                                                 p_regtoset[index] =
 304                                                     (p_regtoset[index] & 0xf0) |
 305                                                     (factor_toset);
 306
 307                                         rtl_write_byte(rtlpriv,
 308                                                        (REG_AGGLEN_LMT + index),
 309                                                        p_regtoset[index]);
 310                                 }
 311
 312                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 313                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 314                                           factor_toset);
 315                         }
 316                         break;
 317                 }
 318         case HW_VAR_AC_PARAM:{
 319                         u8 e_aci = *((u8 *)val);
 320
 321                         rtl8723_dm_init_edca_turbo(hw);
 322
 323                         if (rtlpci->acm_method != EACMWAY2_SW)
 324                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 325                                                               HW_VAR_ACM_CTRL,
 326                                                               (u8 *)(&e_aci));
 327                         break;
 328                 }
 329         case HW_VAR_ACM_CTRL:{
 330                         u8 e_aci = *((u8 *)val);
 331                         union aci_aifsn *p_aci_aifsn =
 332                             (union aci_aifsn *)(&mac->ac[0].aifs);
 333                         u8 acm = p_aci_aifsn->f.acm;
 334                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 335
 336                         acm_ctrl =
 337                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 338
 339                         if (acm) {
 340                                 switch (e_aci) {
 341                                 case AC0_BE:
 342                                         acm_ctrl |= ACMHW_BEQEN;
 343                                         break;
 344                                 case AC2_VI:
 345                                         acm_ctrl |= ACMHW_VIQEN;
 346                                         break;
 347                                 case AC3_VO:
 348                                         acm_ctrl |= ACMHW_VOQEN;
 349                                         break;
 350                                 default:
 351                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 352                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 353                                                  acm);
 354                                         break;
 355                                 }
 356                         } else {
 357                                 switch (e_aci) {
 358                                 case AC0_BE:
 359                                         acm_ctrl &= (~ACMHW_BEQEN);
 360                                         break;
 361                                 case AC2_VI:
 362                                         acm_ctrl &= (~ACMHW_VIQEN);
 363                                         break;
 364                                 case AC3_VO:
 365                                         acm_ctrl &= (~ACMHW_VOQEN);
 366                                         break;
 367                                 default:
 368                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 369                                                  "switch case %#x not processed\n",
 370                                                  e_aci);
 371                                         break;
 372                                 }
 373                         }
 374
 375                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 376                                  "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 377                                  acm_ctrl);
 378                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 379                         break;
 380                 }
 381         case HW_VAR_RCR:{
 382                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 383                         rtlpci->receive_config = ((u32 *)(val))[0];
 384                         break;
 385                 }
 386         case HW_VAR_RETRY_LIMIT:{
 387                         u8 retry_limit = ((u8 *)(val))[0];
 388
 389                         rtl_write_word(rtlpriv, REG_RL,
 390                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 391                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 392                         break;
 393                 }
 394         case HW_VAR_DUAL_TSF_RST:
 395                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 396                 break;
 397         case HW_VAR_EFUSE_BYTES:
 398                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 399                 break;
 400         case HW_VAR_EFUSE_USAGE:
 401                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 402                 break;
 403         case HW_VAR_IO_CMD:
 404                 rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val));
 405                 break;
 406         case HW_VAR_WPA_CONFIG:
 407                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 408                 break;
 409         case HW_VAR_SET_RPWM:{
 410                         u8 rpwm_val;
 411
 412                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 413                         udelay(1);
 414
 415                         if (rpwm_val & BIT(7)) {
 416                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 417                                                (*(u8 *)val));
 418                         } else {
 419                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 420                                                ((*(u8 *)val) | BIT(7)));
 421                         }
 422
 423                         break;
 424                 }
 425         case HW_VAR_H2C_FW_PWRMODE:{
 426                         u8 psmode = (*(u8 *)val);
 427
 428                         if (psmode != FW_PS_ACTIVE_MODE)
 429                                 rtl8723e_dm_rf_saving(hw, true);
 430
 431                         rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 432                         break;
 433                 }
 434         case HW_VAR_FW_PSMODE_STATUS:
 435                 ppsc->fw_current_inpsmode = *((bool *)val);
 436                 break;
 437         case HW_VAR_H2C_FW_JOINBSSRPT:{
 438                         u8 mstatus = (*(u8 *)val);
 439                         u8 tmp_regcr, tmp_reg422;
 440                         bool b_recover = false;
 441
 442                         if (mstatus == RT_MEDIA_CONNECT) {
 443                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 444                                                               NULL);
 445
 446                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 447                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 448                                                (tmp_regcr | BIT(0)));
 449
 450                                 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
 451                                 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
 452
 453                                 tmp_reg422 =
 454                                     rtl_read_byte(rtlpriv,
 455                                                   REG_FWHW_TXQ_CTRL + 2);
 456                                 if (tmp_reg422 & BIT(6))
 457                                         b_recover = true;
 458                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 459                                                tmp_reg422 & (~BIT(6)));
 460
 461                                 rtl8723e_set_fw_rsvdpagepkt(hw, 0);
 462
 463                                 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
 464                                 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
 465
 466                                 if (b_recover) {
 467                                         rtl_write_byte(rtlpriv,
 468                                                        REG_FWHW_TXQ_CTRL + 2,
 469                                                        tmp_reg422);
 470                                 }
 471
 472                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 473                                                (tmp_regcr & ~(BIT(0))));
 474                         }
 475                         rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
 476
 477                         break;
 478                 }
 479         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{
 480                 rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 481                 break;
 482         }
 483         case HW_VAR_AID:{
 484                         u16 u2btmp;
 485
 486                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 487                         u2btmp &= 0xC000;
 488                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 489                                        (u2btmp | mac->assoc_id));
 490
 491                         break;
 492                 }
 493         case HW_VAR_CORRECT_TSF:{
 494                         u8 btype_ibss = ((u8 *)(val))[0];
 495
 496                         if (btype_ibss)
 497                                 _rtl8723e_stop_tx_beacon(hw);
 498
 499                         _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
 500
 501                         rtl_write_dword(rtlpriv, REG_TSFTR,
 502                                         (u32)(mac->tsf & 0xffffffff));
 503                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 504                                         (u32)((mac->tsf >> 32) & 0xffffffff));
 505
 506                         _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
 507
 508                         if (btype_ibss)
 509                                 _rtl8723e_resume_tx_beacon(hw);
 510
 511                         break;
 512                 }
 513         case HW_VAR_FW_LPS_ACTION:{
 514                         bool b_enter_fwlps = *((bool *)val);
 515                         u8 rpwm_val, fw_pwrmode;
 516                         bool fw_current_inps;
 517
 518                         if (b_enter_fwlps) {
 519                                 rpwm_val = 0x02;        /* RF off */
 520                                 fw_current_inps = true;
 521                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 522                                                 HW_VAR_FW_PSMODE_STATUS,
 523                                                 (u8 *)(&fw_current_inps));
 524                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 525                                                 HW_VAR_H2C_FW_PWRMODE,
 526                                                 (u8 *)(&ppsc->fwctrl_psmode));
 527
 528                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 529                                                 HW_VAR_SET_RPWM,
 530                                                 (u8 *)(&rpwm_val));
 531                         } else {
 532                                 rpwm_val = 0x0C;        /* RF on */
 533                                 fw_pwrmode = FW_PS_ACTIVE_MODE;
 534                                 fw_current_inps = false;
 535                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 536                                                               HW_VAR_SET_RPWM,
 537                                                               (u8 *)(&rpwm_val));
 538                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 539                                                 HW_VAR_H2C_FW_PWRMODE,
 540                                                 (u8 *)(&fw_pwrmode));
 541
 542                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 543                                                 HW_VAR_FW_PSMODE_STATUS,
 544                                                 (u8 *)(&fw_current_inps));
 545                         }
 546                          break;
 547                 }
 548         default:
 549                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 550                          "switch case %#x not processed\n", variable);
 551                 break;
 552         }
 553 }
 554
 555 static bool _rtl8723e_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 556 {
 557         struct rtl_priv *rtlpriv = rtl_priv(hw);
 558         bool status = true;
 559         long count = 0;
 560         u32 value = _LLT_INIT_ADDR(address) |
 561             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 562
 563         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 564
 565         do {
 566                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 567                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 568                         break;
 569
 570                 if (count > POLLING_LLT_THRESHOLD) {
 571                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 572                                  "Failed to polling write LLT done at address %d!\n",
 573                                  address);
 574                         status = false;
 575                         break;
 576                 }
 577         } while (++count);
 578
 579         return status;
 580 }
 581
 582 static bool _rtl8723e_llt_table_init(struct ieee80211_hw *hw)
 583 {
 584         struct rtl_priv *rtlpriv = rtl_priv(hw);
 585         unsigned short i;
 586         u8 txpktbuf_bndy;
 587         u8 maxpage;
 588         bool status;
 589         u8 ubyte;
 590
 591 #if LLT_CONFIG == 1
 592         maxpage = 255;
 593         txpktbuf_bndy = 252;
 594 #elif LLT_CONFIG == 2
 595         maxpage = 127;
 596         txpktbuf_bndy = 124;
 597 #elif LLT_CONFIG == 3
 598         maxpage = 255;
 599         txpktbuf_bndy = 174;
 600 #elif LLT_CONFIG == 4
 601         maxpage = 255;
 602         txpktbuf_bndy = 246;
 603 #elif LLT_CONFIG == 5
 604         maxpage = 255;
 605         txpktbuf_bndy = 246;
 606 #endif
 607
 608         rtl_write_byte(rtlpriv, REG_CR, 0x8B);
 609
 610 #if LLT_CONFIG == 1
 611         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 612         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 613 #elif LLT_CONFIG == 2
 614         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 615 #elif LLT_CONFIG == 3
 616         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 617 #elif LLT_CONFIG == 4
 618         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 619 #elif LLT_CONFIG == 5
 620         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 621
 622         rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29);
 623         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03);
 624 #endif
 625
 626         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 627         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 628
 629         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 630         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 631
 632         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 633         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 634         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 635
 636         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 637                 status = _rtl8723e_llt_write(hw, i, i + 1);
 638                 if (true != status)
 639                         return status;
 640         }
 641
 642         status = _rtl8723e_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 643         if (true != status)
 644                 return status;
 645
 646         for (i = txpktbuf_bndy; i < maxpage; i++) {
 647                 status = _rtl8723e_llt_write(hw, i, (i + 1));
 648                 if (true != status)
 649                         return status;
 650         }
 651
 652         status = _rtl8723e_llt_write(hw, maxpage, txpktbuf_bndy);
 653         if (true != status)
 654                 return status;
 655
 656         rtl_write_byte(rtlpriv, REG_CR, 0xff);
 657         ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3);
 658         rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7));
 659
 660         return true;
 661 }
 662
 663 static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw)
 664 {
 665         struct rtl_priv *rtlpriv = rtl_priv(hw);
 666         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 667         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 668         struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
 669
 670         if (rtlpriv->rtlhal.up_first_time)
 671                 return;
 672
 673         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 674                 rtl8723e_sw_led_on(hw, pled0);
 675         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 676                 rtl8723e_sw_led_on(hw, pled0);
 677         else
 678                 rtl8723e_sw_led_off(hw, pled0);
 679 }
 680
 681 static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
 682 {
 683         struct rtl_priv *rtlpriv = rtl_priv(hw);
 684         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 685
 686         unsigned char bytetmp;
 687         unsigned short wordtmp;
 688         u16 retry = 0;
 689         u16 tmpu2b;
 690         bool mac_func_enable;
 691
 692         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 693         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 694         if (bytetmp == 0xFF)
 695                 mac_func_enable = true;
 696         else
 697                 mac_func_enable = false;
 698
 699         /* HW Power on sequence */
 700         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 701                 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW))
 702                 return false;
 703
 704         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
 705         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4));
 706
 707         /* eMAC time out function enable, 0x369[7]=1 */
 708         bytetmp = rtl_read_byte(rtlpriv, 0x369);
 709         rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7));
 710
 711         /* ePHY reg 0x1e bit[4]=1 using MDIO interface,
 712          * we should do this before Enabling ASPM backdoor.
 713          */
 714         do {
 715                 rtl_write_word(rtlpriv, 0x358, 0x5e);
 716                 udelay(100);
 717                 rtl_write_word(rtlpriv, 0x356, 0xc280);
 718                 rtl_write_word(rtlpriv, 0x354, 0xc290);
 719                 rtl_write_word(rtlpriv, 0x358, 0x3e);
 720                 udelay(100);
 721                 rtl_write_word(rtlpriv, 0x358, 0x5e);
 722                 udelay(100);
 723                 tmpu2b = rtl_read_word(rtlpriv, 0x356);
 724                 retry++;
 725         } while (tmpu2b != 0xc290 && retry < 100);
 726
 727         if (retry >= 100) {
 728                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 729                          "InitMAC(): ePHY configure fail!!!\n");
 730                 return false;
 731         }
 732
 733         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 734         rtl_write_word(rtlpriv, REG_CR + 1, 0x06);
 735
 736         if (!mac_func_enable) {
 737                 if (!_rtl8723e_llt_table_init(hw))
 738                         return false;
 739         }
 740
 741         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 742         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 743
 744         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 745
 746         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 747         wordtmp &= 0xf;
 748         wordtmp |= 0xF771;
 749         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 750
 751         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 752         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 753         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 754         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 755
 756         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 757
 758         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 759                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 760                         DMA_BIT_MASK(32));
 761         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 762                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 763                         DMA_BIT_MASK(32));
 764         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 765                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 766         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 767                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 768         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 769                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 770         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 771                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 772         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 773                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 774                         DMA_BIT_MASK(32));
 775         rtl_write_dword(rtlpriv, REG_RX_DESA,
 776                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 777                         DMA_BIT_MASK(32));
 778
 779         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74);
 780
 781         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 782
 783         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 784         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 785         do {
 786                 retry++;
 787                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 788         } while ((retry < 200) && (bytetmp & BIT(7)));
 789
 790         _rtl8723e_gen_refresh_led_state(hw);
 791
 792         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 793
 794         return true;
 795 }
 796
 797 static void _rtl8723e_hw_configure(struct ieee80211_hw *hw)
 798 {
 799         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 800         struct rtl_priv *rtlpriv = rtl_priv(hw);
 801         u8 reg_bw_opmode;
 802         u32 reg_ratr, reg_prsr;
 803
 804         reg_bw_opmode = BW_OPMODE_20MHZ;
 805         reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 806             RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 807         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 808
 809         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 810
 811         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 812
 813         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 814
 815         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 816
 817         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 818
 819         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 820
 821         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 822
 823         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 824
 825         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 826
 827         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 828         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 829         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 830         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 831
 832         if ((rtlpriv->btcoexist.bt_coexistence) &&
 833             (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
 834                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
 835         else
 836                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 837
 838         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 839
 840         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 841
 842         rtlpci->reg_bcn_ctrl_val = 0x1f;
 843         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 844
 845         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 846
 847         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 848
 849         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 850         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 851
 852         if ((rtlpriv->btcoexist.bt_coexistence) &&
 853             (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
 854                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 855                 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
 856         } else {
 857                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 858                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 859         }
 860
 861         if ((rtlpriv->btcoexist.bt_coexistence) &&
 862             (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
 863                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 864         else
 865                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 866
 867         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 868
 869         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 870         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 871
 872         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 873
 874         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 875
 876         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 877         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 878
 879         rtl_write_dword(rtlpriv, 0x394, 0x1);
 880 }
 881
 882 static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw *hw)
 883 {
 884         struct rtl_priv *rtlpriv = rtl_priv(hw);
 885         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 886
 887         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 888         rtl_write_word(rtlpriv, 0x350, 0x870c);
 889         rtl_write_byte(rtlpriv, 0x352, 0x1);
 890
 891         if (ppsc->support_backdoor)
 892                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 893         else
 894                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 895
 896         rtl_write_word(rtlpriv, 0x350, 0x2718);
 897         rtl_write_byte(rtlpriv, 0x352, 0x1);
 898 }
 899
 900 void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw)
 901 {
 902         struct rtl_priv *rtlpriv = rtl_priv(hw);
 903         u8 sec_reg_value;
 904
 905         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 906                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 907                   rtlpriv->sec.pairwise_enc_algorithm,
 908                   rtlpriv->sec.group_enc_algorithm);
 909
 910         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 911                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 912                          "not open hw encryption\n");
 913                 return;
 914         }
 915
 916         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
 917
 918         if (rtlpriv->sec.use_defaultkey) {
 919                 sec_reg_value |= SCR_TXUSEDK;
 920                 sec_reg_value |= SCR_RXUSEDK;
 921         }
 922
 923         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 924
 925         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 926
 927         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 928                  "The SECR-value %x\n", sec_reg_value);
 929
 930         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 931
 932 }
 933
 934 int rtl8723e_hw_init(struct ieee80211_hw *hw)
 935 {
 936         struct rtl_priv *rtlpriv = rtl_priv(hw);
 937         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 938         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 939         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 940         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 941         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 942         bool rtstatus = true;
 943         int err;
 944         u8 tmp_u1b;
 945         unsigned long flags;
 946
 947         rtlpriv->rtlhal.being_init_adapter = true;
 948         /* As this function can take a very long time (up to 350 ms)
 949          * and can be called with irqs disabled, reenable the irqs
 950          * to let the other devices continue being serviced.
 951          *
 952          * It is safe doing so since our own interrupts will only be enabled
 953          * in a subsequent step.
 954          */
 955         local_save_flags(flags);
 956         local_irq_enable();
 957         rtlhal->fw_ready = false;
 958
 959         rtlpriv->intf_ops->disable_aspm(hw);
 960         rtstatus = _rtl8712e_init_mac(hw);
 961         if (rtstatus != true) {
 962                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
 963                 err = 1;
 964                 goto exit;
 965         }
 966
 967         err = rtl8723_download_fw(hw, false, FW_8723A_POLLING_TIMEOUT_COUNT);
 968         if (err) {
 969                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 970                          "Failed to download FW. Init HW without FW now..\n");
 971                 err = 1;
 972                 goto exit;
 973         }
 974         rtlhal->fw_ready = true;
 975
 976         rtlhal->last_hmeboxnum = 0;
 977         rtl8723e_phy_mac_config(hw);
 978         /* because last function modify RCR, so we update
 979          * rcr var here, or TP will unstable for receive_config
 980          * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
 981          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
 982          */
 983         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
 984         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
 985         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 986
 987         rtl8723e_phy_bb_config(hw);
 988         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 989         rtl8723e_phy_rf_config(hw);
 990         if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) {
 991                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
 992                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
 993         } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
 994                 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
 995                 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
 996                 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
 997                 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
 998                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
 999                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
1000         }
1001         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1002                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1003         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1004                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1005         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1006         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1007         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1008         _rtl8723e_hw_configure(hw);
1009         rtl_cam_reset_all_entry(hw);
1010         rtl8723e_enable_hw_security_config(hw);
1011
1012         ppsc->rfpwr_state = ERFON;
1013
1014         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1015         _rtl8723e_enable_aspm_back_door(hw);
1016         rtlpriv->intf_ops->enable_aspm(hw);
1017
1018         rtl8723e_bt_hw_init(hw);
1019
1020         if (ppsc->rfpwr_state == ERFON) {
1021                 rtl8723e_phy_set_rfpath_switch(hw, 1);
1022                 if (rtlphy->iqk_initialized) {
1023                         rtl8723e_phy_iq_calibrate(hw, true);
1024                 } else {
1025                         rtl8723e_phy_iq_calibrate(hw, false);
1026                         rtlphy->iqk_initialized = true;
1027                 }
1028
1029                 rtl8723e_dm_check_txpower_tracking(hw);
1030                 rtl8723e_phy_lc_calibrate(hw);
1031         }
1032
1033         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1034         if (!(tmp_u1b & BIT(0))) {
1035                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1036                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1037         }
1038
1039         if (!(tmp_u1b & BIT(4))) {
1040                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1041                 tmp_u1b &= 0x0F;
1042                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1043                 udelay(10);
1044                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1045                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1046         }
1047         rtl8723e_dm_init(hw);
1048 exit:
1049         local_irq_restore(flags);
1050         rtlpriv->rtlhal.being_init_adapter = false;
1051         return err;
1052 }
1053
1054 static enum version_8723e _rtl8723e_read_chip_version(struct ieee80211_hw *hw)
1055 {
1056         struct rtl_priv *rtlpriv = rtl_priv(hw);
1057         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1058         enum version_8723e version = 0x0000;
1059         u32 value32;
1060
1061         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1062         if (value32 & TRP_VAUX_EN) {
1063                 version = (enum version_8723e)(version |
1064                         ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1065                 /* RTL8723 with BT function. */
1066                 version = (enum version_8723e)(version |
1067                         ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1068
1069         } else {
1070                 /* Normal mass production chip. */
1071                 version = (enum version_8723e) NORMAL_CHIP;
1072                 version = (enum version_8723e)(version |
1073                         ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1074                 /* RTL8723 with BT function. */
1075                 version = (enum version_8723e)(version |
1076                         ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1077                 if (IS_CHIP_VENDOR_UMC(version))
1078                         version = (enum version_8723e)(version |
1079                         ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */
1080                 if (IS_8723_SERIES(version)) {
1081                         value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
1082                         /* ROM code version. */
1083                         version = (enum version_8723e)(version |
1084                                 ((value32 & RF_RL_ID)>>20));
1085                 }
1086         }
1087
1088         if (IS_8723_SERIES(version)) {
1089                 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1090                 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ?
1091                                         RT_POLARITY_HIGH_ACT :
1092                                         RT_POLARITY_LOW_ACT);
1093         }
1094         switch (version) {
1095         case VERSION_TEST_UMC_CHIP_8723:
1096                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1097                          "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
1098                         break;
1099         case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
1100                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1101                          "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
1102                 break;
1103         case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT:
1104                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1105                          "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n");
1106                 break;
1107         default:
1108                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1109                          "Chip Version ID: Unknown. Bug?\n");
1110                 break;
1111         }
1112
1113         if (IS_8723_SERIES(version))
1114                 rtlphy->rf_type = RF_1T1R;
1115
1116         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1117                 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1118
1119         return version;
1120 }
1121
1122 static int _rtl8723e_set_media_status(struct ieee80211_hw *hw,
1123                                       enum nl80211_iftype type)
1124 {
1125         struct rtl_priv *rtlpriv = rtl_priv(hw);
1126         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1127         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1128         u8 mode = MSR_NOLINK;
1129
1130         rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1131         RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
1132                 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1133
1134         switch (type) {
1135         case NL80211_IFTYPE_UNSPECIFIED:
1136                 mode = MSR_NOLINK;
1137                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1138                         "Set Network type to NO LINK!\n");
1139                 break;
1140         case NL80211_IFTYPE_ADHOC:
1141                 mode = MSR_ADHOC;
1142                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1143                         "Set Network type to Ad Hoc!\n");
1144                 break;
1145         case NL80211_IFTYPE_STATION:
1146                 mode = MSR_INFRA;
1147                 ledaction = LED_CTL_LINK;
1148                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1149                         "Set Network type to STA!\n");
1150                 break;
1151         case NL80211_IFTYPE_AP:
1152                 mode = MSR_AP;
1153                 ledaction = LED_CTL_LINK;
1154                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1155                         "Set Network type to AP!\n");
1156                 break;
1157         default:
1158                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1159                         "Network type %d not support!\n", type);
1160                 return 1;
1161                 break;
1162         }
1163
1164         /* MSR_INFRA == Link in infrastructure network;
1165          * MSR_ADHOC == Link in ad hoc network;
1166          * Therefore, check link state is necessary.
1167          *
1168          * MSR_AP == AP mode; link state is not cared here.
1169          */
1170         if (mode != MSR_AP &&
1171             rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1172                 mode = MSR_NOLINK;
1173                 ledaction = LED_CTL_NO_LINK;
1174         }
1175         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1176                 _rtl8723e_stop_tx_beacon(hw);
1177                 _rtl8723e_enable_bcn_sub_func(hw);
1178         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1179                 _rtl8723e_resume_tx_beacon(hw);
1180                 _rtl8723e_disable_bcn_sub_func(hw);
1181         } else {
1182                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1183                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1184                          mode);
1185         }
1186
1187         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1188         rtlpriv->cfg->ops->led_control(hw, ledaction);
1189         if (mode == MSR_AP)
1190                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1191         else
1192                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1193         return 0;
1194 }
1195
1196 void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1197 {
1198         struct rtl_priv *rtlpriv = rtl_priv(hw);
1199         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1200         u32 reg_rcr = rtlpci->receive_config;
1201
1202         if (rtlpriv->psc.rfpwr_state != ERFON)
1203                 return;
1204
1205         if (check_bssid) {
1206                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1207                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1208                                               (u8 *)(&reg_rcr));
1209                 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
1210         } else if (!check_bssid) {
1211                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1212                 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
1213                 rtlpriv->cfg->ops->set_hw_reg(hw,
1214                         HW_VAR_RCR, (u8 *)(&reg_rcr));
1215         }
1216 }
1217
1218 int rtl8723e_set_network_type(struct ieee80211_hw *hw,
1219                               enum nl80211_iftype type)
1220 {
1221         struct rtl_priv *rtlpriv = rtl_priv(hw);
1222
1223         if (_rtl8723e_set_media_status(hw, type))
1224                 return -EOPNOTSUPP;
1225
1226         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1227                 if (type != NL80211_IFTYPE_AP)
1228                         rtl8723e_set_check_bssid(hw, true);
1229         } else {
1230                 rtl8723e_set_check_bssid(hw, false);
1231         }
1232
1233         return 0;
1234 }
1235
1236 /* don't set REG_EDCA_BE_PARAM here
1237  * because mac80211 will send pkt when scan
1238  */
1239 void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci)
1240 {
1241         struct rtl_priv *rtlpriv = rtl_priv(hw);
1242
1243         rtl8723_dm_init_edca_turbo(hw);
1244         switch (aci) {
1245         case AC1_BK:
1246                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1247                 break;
1248         case AC0_BE:
1249                 break;
1250         case AC2_VI:
1251                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1252                 break;
1253         case AC3_VO:
1254                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1255                 break;
1256         default:
1257                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1258                 break;
1259         }
1260 }
1261
1262 void rtl8723e_enable_interrupt(struct ieee80211_hw *hw)
1263 {
1264         struct rtl_priv *rtlpriv = rtl_priv(hw);
1265         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1266
1267         rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1268         rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1269         rtlpci->irq_enabled = true;
1270 }
1271
1272 void rtl8723e_disable_interrupt(struct ieee80211_hw *hw)
1273 {
1274         struct rtl_priv *rtlpriv = rtl_priv(hw);
1275         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1276         rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
1277         rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
1278         rtlpci->irq_enabled = false;
1279         /*synchronize_irq(rtlpci->pdev->irq);*/
1280 }
1281
1282 static void _rtl8723e_poweroff_adapter(struct ieee80211_hw *hw)
1283 {
1284         struct rtl_priv *rtlpriv = rtl_priv(hw);
1285         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1286         u8 u1b_tmp;
1287
1288         /* Combo (PCIe + USB) Card and PCIe-MF Card */
1289         /* 1. Run LPS WL RFOFF flow */
1290         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1291                                  PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW);
1292
1293         /* 2. 0x1F[7:0] = 0 */
1294         /* turn off RF */
1295         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1296         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1297             rtlhal->fw_ready) {
1298                 rtl8723ae_firmware_selfreset(hw);
1299         }
1300
1301         /* Reset MCU. Suggested by Filen. */
1302         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1303         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1304
1305         /* g.   MCUFWDL 0x80[1:0]=0      */
1306         /* reset MCU ready status */
1307         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1308
1309         /* HW card disable configuration. */
1310         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1311                 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW);
1312
1313         /* Reset MCU IO Wrapper */
1314         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1315         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1316         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1317         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1318
1319         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1320         /* lock ISO/CLK/Power control register */
1321         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1322 }
1323
1324 void rtl8723e_card_disable(struct ieee80211_hw *hw)
1325 {
1326         struct rtl_priv *rtlpriv = rtl_priv(hw);
1327         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1328         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1329         enum nl80211_iftype opmode;
1330
1331         mac->link_state = MAC80211_NOLINK;
1332         opmode = NL80211_IFTYPE_UNSPECIFIED;
1333         _rtl8723e_set_media_status(hw, opmode);
1334         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1335             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1336                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1337         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1338         _rtl8723e_poweroff_adapter(hw);
1339
1340         /* after power off we should do iqk again */
1341         rtlpriv->phy.iqk_initialized = false;
1342 }
1343
1344 void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw,
1345                                    u32 *p_inta, u32 *p_intb)
1346 {
1347         struct rtl_priv *rtlpriv = rtl_priv(hw);
1348         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1349
1350         *p_inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0];
1351         rtl_write_dword(rtlpriv, 0x3a0, *p_inta);
1352 }
1353
1354 void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw)
1355 {
1356
1357         struct rtl_priv *rtlpriv = rtl_priv(hw);
1358         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1359         u16 bcn_interval, atim_window;
1360
1361         bcn_interval = mac->beacon_interval;
1362         atim_window = 2;        /*FIX MERGE */
1363         rtl8723e_disable_interrupt(hw);
1364         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1365         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1366         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1367         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1368         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1369         rtl_write_byte(rtlpriv, 0x606, 0x30);
1370         rtl8723e_enable_interrupt(hw);
1371 }
1372
1373 void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw)
1374 {
1375         struct rtl_priv *rtlpriv = rtl_priv(hw);
1376         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1377         u16 bcn_interval = mac->beacon_interval;
1378
1379         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1380                  "beacon_interval:%d\n", bcn_interval);
1381         rtl8723e_disable_interrupt(hw);
1382         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1383         rtl8723e_enable_interrupt(hw);
1384 }
1385
1386 void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw,
1387                                     u32 add_msr, u32 rm_msr)
1388 {
1389         struct rtl_priv *rtlpriv = rtl_priv(hw);
1390         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1391
1392         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1393                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1394
1395         if (add_msr)
1396                 rtlpci->irq_mask[0] |= add_msr;
1397         if (rm_msr)
1398                 rtlpci->irq_mask[0] &= (~rm_msr);
1399         rtl8723e_disable_interrupt(hw);
1400         rtl8723e_enable_interrupt(hw);
1401 }
1402
1403 static u8 _rtl8723e_get_chnl_group(u8 chnl)
1404 {
1405         u8 group;
1406
1407         if (chnl < 3)
1408                 group = 0;
1409         else if (chnl < 9)
1410                 group = 1;
1411         else
1412                 group = 2;
1413         return group;
1414 }
1415
1416 static void _rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1417                                                   bool autoload_fail,
1418                                                   u8 *hwinfo)
1419 {
1420         struct rtl_priv *rtlpriv = rtl_priv(hw);
1421         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1422         u8 rf_path, index, tempval;
1423         u16 i;
1424
1425         for (rf_path = 0; rf_path < 1; rf_path++) {
1426                 for (i = 0; i < 3; i++) {
1427                         if (!autoload_fail) {
1428                                 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1429                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1430                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1431                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i];
1432                         } else {
1433                                 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1434                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1435                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1436                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1437                         }
1438                 }
1439         }
1440
1441         for (i = 0; i < 3; i++) {
1442                 if (!autoload_fail)
1443                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1444                 else
1445                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1446                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1447                     (tempval & 0xf);
1448                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1449                     ((tempval & 0xf0) >> 4);
1450         }
1451
1452         for (rf_path = 0; rf_path < 2; rf_path++)
1453                 for (i = 0; i < 3; i++)
1454                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1455                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1456                                  i, rtlefuse->eeprom_chnlarea_txpwr_cck
1457                                         [rf_path][i]);
1458         for (rf_path = 0; rf_path < 2; rf_path++)
1459                 for (i = 0; i < 3; i++)
1460                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1461                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1462                                 rf_path, i,
1463                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1464                                         [rf_path][i]);
1465         for (rf_path = 0; rf_path < 2; rf_path++)
1466                 for (i = 0; i < 3; i++)
1467                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1468                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1469                                  rf_path, i,
1470                                  rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1471                                         [rf_path][i]);
1472
1473         for (rf_path = 0; rf_path < 2; rf_path++) {
1474                 for (i = 0; i < 14; i++) {
1475                         index = _rtl8723e_get_chnl_group((u8)i);
1476
1477                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1478                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1479                                         [rf_path][index];
1480                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1481                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1482                                         [rf_path][index];
1483
1484                         if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1485                                         [rf_path][index] -
1486                              rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1487                                         [rf_path][index]) > 0) {
1488                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1489                                   rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1490                                   [rf_path][index] -
1491                                   rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1492                                   [rf_path][index];
1493                         } else {
1494                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1495                         }
1496                 }
1497
1498                 for (i = 0; i < 14; i++) {
1499                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1500                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1501                                 rf_path, i,
1502                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1503                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1504                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1505                 }
1506         }
1507
1508         for (i = 0; i < 3; i++) {
1509                 if (!autoload_fail) {
1510                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1511                             hwinfo[EEPROM_TXPWR_GROUP + i];
1512                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1513                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1514                 } else {
1515                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1516                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1517                 }
1518         }
1519
1520         for (rf_path = 0; rf_path < 2; rf_path++) {
1521                 for (i = 0; i < 14; i++) {
1522                         index = _rtl8723e_get_chnl_group((u8)i);
1523
1524                         if (rf_path == RF90_PATH_A) {
1525                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1526                                   (rtlefuse->eeprom_pwrlimit_ht20[index] & 0xf);
1527                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1528                                   (rtlefuse->eeprom_pwrlimit_ht40[index] & 0xf);
1529                         } else if (rf_path == RF90_PATH_B) {
1530                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1531                                   ((rtlefuse->eeprom_pwrlimit_ht20[index] &
1532                                    0xf0) >> 4);
1533                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1534                                   ((rtlefuse->eeprom_pwrlimit_ht40[index] &
1535                                    0xf0) >> 4);
1536                         }
1537
1538                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1539                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i,
1540                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1541                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1542                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i,
1543                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1544                 }
1545         }
1546
1547         for (i = 0; i < 14; i++) {
1548                 index = _rtl8723e_get_chnl_group((u8)i);
1549
1550                 if (!autoload_fail)
1551                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1552                 else
1553                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1554
1555                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1556                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1557                     ((tempval >> 4) & 0xF);
1558
1559                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1560                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1561
1562                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1563                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1564
1565                 index = _rtl8723e_get_chnl_group((u8)i);
1566
1567                 if (!autoload_fail)
1568                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1569                 else
1570                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1571
1572                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1573                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1574                     ((tempval >> 4) & 0xF);
1575         }
1576
1577         rtlefuse->legacy_ht_txpowerdiff =
1578             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1579
1580         for (i = 0; i < 14; i++)
1581                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1582                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1583                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1584         for (i = 0; i < 14; i++)
1585                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1586                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1587                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1588         for (i = 0; i < 14; i++)
1589                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1590                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1591                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1592         for (i = 0; i < 14; i++)
1593                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1594                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1595                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1596
1597         if (!autoload_fail)
1598                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1599         else
1600                 rtlefuse->eeprom_regulatory = 0;
1601         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1602                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1603
1604         if (!autoload_fail)
1605                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1606         else
1607                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1608
1609         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1610                 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1611                  rtlefuse->eeprom_tssi[RF90_PATH_A],
1612                  rtlefuse->eeprom_tssi[RF90_PATH_B]);
1613
1614         if (!autoload_fail)
1615                 tempval = hwinfo[EEPROM_THERMAL_METER];
1616         else
1617                 tempval = EEPROM_DEFAULT_THERMALMETER;
1618         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1619
1620         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1621                 rtlefuse->apk_thermalmeterignore = true;
1622
1623         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1624         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1625                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1626 }
1627
1628 static void _rtl8723e_read_adapter_info(struct ieee80211_hw *hw,
1629                                         bool b_pseudo_test)
1630 {
1631         struct rtl_priv *rtlpriv = rtl_priv(hw);
1632         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1633         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1634         int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1635                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1636                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1637                         COUNTRY_CODE_WORLD_WIDE_13};
1638         u8 *hwinfo;
1639
1640         if (b_pseudo_test) {
1641                 /* need add */
1642                 return;
1643         }
1644         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1645         if (!hwinfo)
1646                 return;
1647
1648         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1649                 goto exit;
1650
1651         _rtl8723e_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1652                                               hwinfo);
1653
1654         rtl8723e_read_bt_coexist_info_from_hwpg(hw,
1655                         rtlefuse->autoload_failflag, hwinfo);
1656
1657         if (rtlhal->oem_id != RT_CID_DEFAULT)
1658                 goto exit;
1659
1660         switch (rtlefuse->eeprom_oemid) {
1661         case EEPROM_CID_DEFAULT:
1662                 switch (rtlefuse->eeprom_did) {
1663                 case 0x8176:
1664                         switch (rtlefuse->eeprom_svid) {
1665                         case 0x10EC:
1666                                 switch (rtlefuse->eeprom_smid) {
1667                                 case 0x6151 ... 0x6152:
1668                                 case 0x6154 ... 0x6155:
1669                                 case 0x6177 ... 0x6180:
1670                                 case 0x7151 ... 0x7152:
1671                                 case 0x7154 ... 0x7155:
1672                                 case 0x7177 ... 0x7180:
1673                                 case 0x8151 ... 0x8152:
1674                                 case 0x8154 ... 0x8155:
1675                                 case 0x8181 ... 0x8182:
1676                                 case 0x8184 ... 0x8185:
1677                                 case 0x9151 ... 0x9152:
1678                                 case 0x9154 ... 0x9155:
1679                                 case 0x9181 ... 0x9182:
1680                                 case 0x9184 ... 0x9185:
1681                                         rtlhal->oem_id = RT_CID_TOSHIBA;
1682                                         break;
1683                                 case 0x6191 ... 0x6193:
1684                                 case 0x7191 ... 0x7193:
1685                                 case 0x8191 ... 0x8193:
1686                                 case 0x9191 ... 0x9193:
1687                                         rtlhal->oem_id = RT_CID_819X_SAMSUNG;
1688                                         break;
1689                                 case 0x8197:
1690                                 case 0x9196:
1691                                         rtlhal->oem_id = RT_CID_819X_CLEVO;
1692                                         break;
1693                                 case 0x8203:
1694                                         rtlhal->oem_id = RT_CID_819X_PRONETS;
1695                                         break;
1696                                 case 0x8195:
1697                                 case 0x9195:
1698                                 case 0x7194:
1699                                 case 0x8200 ... 0x8202:
1700                                 case 0x9200:
1701                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
1702                                         break;
1703                                 }
1704                         case 0x1025:
1705                                 rtlhal->oem_id = RT_CID_819X_ACER;
1706                                 break;
1707                         case 0x1028:
1708                                 switch (rtlefuse->eeprom_smid) {
1709                                 case 0x8194:
1710                                 case 0x8198:
1711                                 case 0x9197 ... 0x9198:
1712                                         rtlhal->oem_id = RT_CID_819X_DELL;
1713                                         break;
1714                                 }
1715                                 break;
1716                         case 0x103C:
1717                                 switch (rtlefuse->eeprom_smid) {
1718                                 case 0x1629:
1719                                         rtlhal->oem_id = RT_CID_819X_HP;
1720                                 }
1721                                 break;
1722                         case 0x1A32:
1723                                 switch (rtlefuse->eeprom_smid) {
1724                                 case 0x2315:
1725                                         rtlhal->oem_id = RT_CID_819X_QMI;
1726                                         break;
1727                                 }
1728                                 break;
1729                         case 0x1043:
1730                                 switch (rtlefuse->eeprom_smid) {
1731                                 case 0x84B5:
1732                                         rtlhal->oem_id =
1733                                                 RT_CID_819X_EDIMAX_ASUS;
1734                                 }
1735                                 break;
1736                         }
1737                         break;
1738                 case 0x8178:
1739                         switch (rtlefuse->eeprom_svid) {
1740                         case 0x10ec:
1741                                 switch (rtlefuse->eeprom_smid) {
1742                                 case 0x6181 ... 0x6182:
1743                                 case 0x6184 ... 0x6185:
1744                                 case 0x7181 ... 0x7182:
1745                                 case 0x7184 ... 0x7185:
1746                                 case 0x8181 ... 0x8182:
1747                                 case 0x8184 ... 0x8185:
1748                                 case 0x9181 ... 0x9182:
1749                                 case 0x9184 ... 0x9185:
1750                                         rtlhal->oem_id = RT_CID_TOSHIBA;
1751                                         break;
1752                                 case 0x8186:
1753                                         rtlhal->oem_id =
1754                                                 RT_CID_819X_PRONETS;
1755                                         break;
1756                                 }
1757                                 break;
1758                         case 0x1025:
1759                                 rtlhal->oem_id = RT_CID_819X_ACER;
1760                                 break;
1761                         case 0x1043:
1762                                 switch (rtlefuse->eeprom_smid) {
1763                                 case 0x8486:
1764                                         rtlhal->oem_id =
1765                                              RT_CID_819X_EDIMAX_ASUS;
1766                                 }
1767                                 break;
1768                         }
1769                         break;
1770                 }
1771                 break;
1772         case EEPROM_CID_TOSHIBA:
1773                 rtlhal->oem_id = RT_CID_TOSHIBA;
1774                 break;
1775         case EEPROM_CID_CCX:
1776                 rtlhal->oem_id = RT_CID_CCX;
1777                 break;
1778         case EEPROM_CID_QMI:
1779                 rtlhal->oem_id = RT_CID_819X_QMI;
1780                 break;
1781         case EEPROM_CID_WHQL:
1782                 break;
1783         default:
1784                 rtlhal->oem_id = RT_CID_DEFAULT;
1785                 break;
1786         }
1787 exit:
1788         kfree(hwinfo);
1789 }
1790
1791 static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw *hw)
1792 {
1793         struct rtl_priv *rtlpriv = rtl_priv(hw);
1794         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1795         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1796
1797         pcipriv->ledctl.led_opendrain = true;
1798         switch (rtlhal->oem_id) {
1799         case RT_CID_819X_HP:
1800                 pcipriv->ledctl.led_opendrain = true;
1801                 break;
1802         case RT_CID_819X_LENOVO:
1803         case RT_CID_DEFAULT:
1804         case RT_CID_TOSHIBA:
1805         case RT_CID_CCX:
1806         case RT_CID_819X_ACER:
1807         case RT_CID_WHQL:
1808         default:
1809                 break;
1810         }
1811         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1812                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1813 }
1814
1815 void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw)
1816 {
1817         struct rtl_priv *rtlpriv = rtl_priv(hw);
1818         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1819         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1820         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1821         u8 tmp_u1b;
1822         u32 value32;
1823
1824         value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]);
1825         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1826         rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32);
1827
1828         rtlhal->version = _rtl8723e_read_chip_version(hw);
1829
1830         if (get_rf_type(rtlphy) == RF_1T1R)
1831                 rtlpriv->dm.rfpath_rxenable[0] = true;
1832         else
1833                 rtlpriv->dm.rfpath_rxenable[0] =
1834                     rtlpriv->dm.rfpath_rxenable[1] = true;
1835         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1836                                                 rtlhal->version);
1837
1838         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1839         if (tmp_u1b & BIT(4)) {
1840                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1841                 rtlefuse->epromtype = EEPROM_93C46;
1842         } else {
1843                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1844                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1845         }
1846         if (tmp_u1b & BIT(5)) {
1847                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1848                 rtlefuse->autoload_failflag = false;
1849                 _rtl8723e_read_adapter_info(hw, false);
1850         } else {
1851                 rtlefuse->autoload_failflag = true;
1852                 _rtl8723e_read_adapter_info(hw, false);
1853                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1854         }
1855         _rtl8723e_hal_customized_behavior(hw);
1856 }
1857
1858 static void rtl8723e_update_hal_rate_table(struct ieee80211_hw *hw,
1859                                            struct ieee80211_sta *sta)
1860 {
1861         struct rtl_priv *rtlpriv = rtl_priv(hw);
1862         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1863         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1864         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1865         u32 ratr_value;
1866         u8 ratr_index = 0;
1867         u8 b_nmode = mac->ht_enable;
1868         u16 shortgi_rate;
1869         u32 tmp_ratr_value;
1870         u8 curtxbw_40mhz = mac->bw_40;
1871         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1872                                 1 : 0;
1873         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1874                                 1 : 0;
1875         enum wireless_mode wirelessmode = mac->mode;
1876         u32 ratr_mask;
1877
1878         if (rtlhal->current_bandtype == BAND_ON_5G)
1879                 ratr_value = sta->supp_rates[1] << 4;
1880         else
1881                 ratr_value = sta->supp_rates[0];
1882         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1883                 ratr_value = 0xfff;
1884         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1885                         sta->ht_cap.mcs.rx_mask[0] << 12);
1886         switch (wirelessmode) {
1887         case WIRELESS_MODE_B:
1888                 if (ratr_value & 0x0000000c)
1889                         ratr_value &= 0x0000000d;
1890                 else
1891                         ratr_value &= 0x0000000f;
1892                 break;
1893         case WIRELESS_MODE_G:
1894                 ratr_value &= 0x00000FF5;
1895                 break;
1896         case WIRELESS_MODE_N_24G:
1897         case WIRELESS_MODE_N_5G:
1898                 b_nmode = 1;
1899                 if (get_rf_type(rtlphy) == RF_1T2R ||
1900                     get_rf_type(rtlphy) == RF_1T1R)
1901                         ratr_mask = 0x000ff005;
1902                 else
1903                         ratr_mask = 0x0f0ff005;
1904
1905                 ratr_value &= ratr_mask;
1906                 break;
1907         default:
1908                 if (rtlphy->rf_type == RF_1T2R)
1909                         ratr_value &= 0x000ff0ff;
1910                 else
1911                         ratr_value &= 0x0f0ff0ff;
1912
1913                 break;
1914         }
1915
1916         if ((rtlpriv->btcoexist.bt_coexistence) &&
1917             (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1918             (rtlpriv->btcoexist.bt_cur_state) &&
1919             (rtlpriv->btcoexist.bt_ant_isolation) &&
1920             ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1921             (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1922                 ratr_value &= 0x0fffcfc0;
1923         else
1924                 ratr_value &= 0x0FFFFFFF;
1925
1926         if (b_nmode &&
1927             ((curtxbw_40mhz && curshortgi_40mhz) ||
1928              (!curtxbw_40mhz && curshortgi_20mhz))) {
1929                 ratr_value |= 0x10000000;
1930                 tmp_ratr_value = (ratr_value >> 12);
1931
1932                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1933                         if ((1 << shortgi_rate) & tmp_ratr_value)
1934                                 break;
1935                 }
1936
1937                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1938                     (shortgi_rate << 4) | (shortgi_rate);
1939         }
1940
1941         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1942
1943         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1944                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
1945 }
1946
1947 static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw *hw,
1948                                           struct ieee80211_sta *sta,
1949                                           u8 rssi_level)
1950 {
1951         struct rtl_priv *rtlpriv = rtl_priv(hw);
1952         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1953         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1954         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1955         struct rtl_sta_info *sta_entry = NULL;
1956         u32 ratr_bitmap;
1957         u8 ratr_index;
1958         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1959                                 ? 1 : 0;
1960         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1961                                 1 : 0;
1962         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1963                                 1 : 0;
1964         enum wireless_mode wirelessmode = 0;
1965         bool shortgi = false;
1966         u8 rate_mask[5];
1967         u8 macid = 0;
1968         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
1969
1970         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1971         wirelessmode = sta_entry->wireless_mode;
1972         if (mac->opmode == NL80211_IFTYPE_STATION)
1973                 curtxbw_40mhz = mac->bw_40;
1974         else if (mac->opmode == NL80211_IFTYPE_AP ||
1975                 mac->opmode == NL80211_IFTYPE_ADHOC)
1976                 macid = sta->aid + 1;
1977
1978         if (rtlhal->current_bandtype == BAND_ON_5G)
1979                 ratr_bitmap = sta->supp_rates[1] << 4;
1980         else
1981                 ratr_bitmap = sta->supp_rates[0];
1982         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1983                 ratr_bitmap = 0xfff;
1984         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1985                         sta->ht_cap.mcs.rx_mask[0] << 12);
1986         switch (wirelessmode) {
1987         case WIRELESS_MODE_B:
1988                 ratr_index = RATR_INX_WIRELESS_B;
1989                 if (ratr_bitmap & 0x0000000c)
1990                         ratr_bitmap &= 0x0000000d;
1991                 else
1992                         ratr_bitmap &= 0x0000000f;
1993                 break;
1994         case WIRELESS_MODE_G:
1995                 ratr_index = RATR_INX_WIRELESS_GB;
1996
1997                 if (rssi_level == 1)
1998                         ratr_bitmap &= 0x00000f00;
1999                 else if (rssi_level == 2)
2000                         ratr_bitmap &= 0x00000ff0;
2001                 else
2002                         ratr_bitmap &= 0x00000ff5;
2003                 break;
2004         case WIRELESS_MODE_A:
2005                 ratr_index = RATR_INX_WIRELESS_G;
2006                 ratr_bitmap &= 0x00000ff0;
2007                 break;
2008         case WIRELESS_MODE_N_24G:
2009         case WIRELESS_MODE_N_5G:
2010                 ratr_index = RATR_INX_WIRELESS_NGB;
2011                 if (rtlphy->rf_type == RF_1T2R ||
2012                     rtlphy->rf_type == RF_1T1R) {
2013                         if (curtxbw_40mhz) {
2014                                 if (rssi_level == 1)
2015                                         ratr_bitmap &= 0x000f0000;
2016                                 else if (rssi_level == 2)
2017                                         ratr_bitmap &= 0x000ff000;
2018                                 else
2019                                         ratr_bitmap &= 0x000ff015;
2020                         } else {
2021                                 if (rssi_level == 1)
2022                                         ratr_bitmap &= 0x000f0000;
2023                                 else if (rssi_level == 2)
2024                                         ratr_bitmap &= 0x000ff000;
2025                                 else
2026                                         ratr_bitmap &= 0x000ff005;
2027                         }
2028                 } else {
2029                         if (curtxbw_40mhz) {
2030                                 if (rssi_level == 1)
2031                                         ratr_bitmap &= 0x0f0f0000;
2032                                 else if (rssi_level == 2)
2033                                         ratr_bitmap &= 0x0f0ff000;
2034                                 else
2035                                         ratr_bitmap &= 0x0f0ff015;
2036                         } else {
2037                                 if (rssi_level == 1)
2038                                         ratr_bitmap &= 0x0f0f0000;
2039                                 else if (rssi_level == 2)
2040                                         ratr_bitmap &= 0x0f0ff000;
2041                                 else
2042                                         ratr_bitmap &= 0x0f0ff005;
2043                         }
2044                 }
2045
2046                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2047                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2048                         if (macid == 0)
2049                                 shortgi = true;
2050                         else if (macid == 1)
2051                                 shortgi = false;
2052                 }
2053                 break;
2054         default:
2055                 ratr_index = RATR_INX_WIRELESS_NGB;
2056
2057                 if (rtlphy->rf_type == RF_1T2R)
2058                         ratr_bitmap &= 0x000ff0ff;
2059                 else
2060                         ratr_bitmap &= 0x0f0ff0ff;
2061                 break;
2062         }
2063         sta_entry->ratr_index = ratr_index;
2064
2065         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2066                  "ratr_bitmap :%x\n", ratr_bitmap);
2067         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2068                              (ratr_index << 28);
2069         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2070         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2071                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2072                   ratr_index, ratr_bitmap,
2073                   rate_mask[0], rate_mask[1],
2074                   rate_mask[2], rate_mask[3],
2075                   rate_mask[4]);
2076         rtl8723e_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2077 }
2078
2079 void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw,
2080                                   struct ieee80211_sta *sta, u8 rssi_level)
2081 {
2082         struct rtl_priv *rtlpriv = rtl_priv(hw);
2083
2084         if (rtlpriv->dm.useramask)
2085                 rtl8723e_update_hal_rate_mask(hw, sta, rssi_level);
2086         else
2087                 rtl8723e_update_hal_rate_table(hw, sta);
2088 }
2089
2090 void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw)
2091 {
2092         struct rtl_priv *rtlpriv = rtl_priv(hw);
2093         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2094         u16 sifs_timer;
2095
2096         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2097         if (!mac->ht_enable)
2098                 sifs_timer = 0x0a0a;
2099         else
2100                 sifs_timer = 0x1010;
2101         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2102 }
2103
2104 bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2105 {
2106         struct rtl_priv *rtlpriv = rtl_priv(hw);
2107         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2108         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2109         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2110         u8 u1tmp;
2111         bool b_actuallyset = false;
2112
2113         if (rtlpriv->rtlhal.being_init_adapter)
2114                 return false;
2115
2116         if (ppsc->swrf_processing)
2117                 return false;
2118
2119         spin_lock(&rtlpriv->locks.rf_ps_lock);
2120         if (ppsc->rfchange_inprogress) {
2121                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2122                 return false;
2123         } else {
2124                 ppsc->rfchange_inprogress = true;
2125                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2126         }
2127
2128         cur_rfstate = ppsc->rfpwr_state;
2129
2130         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2131                        rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1)));
2132
2133         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2134
2135         if (rtlphy->polarity_ctl)
2136                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2137         else
2138                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2139
2140         if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2141                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2142                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2143
2144                 e_rfpowerstate_toset = ERFON;
2145                 ppsc->hwradiooff = false;
2146                 b_actuallyset = true;
2147         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2148                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2149                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2150
2151                 e_rfpowerstate_toset = ERFOFF;
2152                 ppsc->hwradiooff = true;
2153                 b_actuallyset = true;
2154         }
2155
2156         if (b_actuallyset) {
2157                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2158                 ppsc->rfchange_inprogress = false;
2159                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2160         } else {
2161                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2162                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2163
2164                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2165                 ppsc->rfchange_inprogress = false;
2166                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2167         }
2168
2169         *valid = 1;
2170         return !ppsc->hwradiooff;
2171
2172 }
2173
2174 void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index,
2175                       u8 *p_macaddr, bool is_group, u8 enc_algo,
2176                       bool is_wepkey, bool clear_all)
2177 {
2178         struct rtl_priv *rtlpriv = rtl_priv(hw);
2179         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2180         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2181         u8 *macaddr = p_macaddr;
2182         u32 entry_id = 0;
2183         bool is_pairwise = false;
2184
2185         static u8 cam_const_addr[4][6] = {
2186                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2187                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2188                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2189                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2190         };
2191         static u8 cam_const_broad[] = {
2192                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2193         };
2194
2195         if (clear_all) {
2196                 u8 idx = 0;
2197                 u8 cam_offset = 0;
2198                 u8 clear_number = 5;
2199
2200                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2201
2202                 for (idx = 0; idx < clear_number; idx++) {
2203                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2204                         rtl_cam_empty_entry(hw, cam_offset + idx);
2205
2206                         if (idx < 5) {
2207                                 memset(rtlpriv->sec.key_buf[idx], 0,
2208                                        MAX_KEY_LEN);
2209                                 rtlpriv->sec.key_len[idx] = 0;
2210                         }
2211                 }
2212
2213         } else {
2214                 switch (enc_algo) {
2215                 case WEP40_ENCRYPTION:
2216                         enc_algo = CAM_WEP40;
2217                         break;
2218                 case WEP104_ENCRYPTION:
2219                         enc_algo = CAM_WEP104;
2220                         break;
2221                 case TKIP_ENCRYPTION:
2222                         enc_algo = CAM_TKIP;
2223                         break;
2224                 case AESCCMP_ENCRYPTION:
2225                         enc_algo = CAM_AES;
2226                         break;
2227                 default:
2228                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2229                                  "switch case %#x not processed\n", enc_algo);
2230                         enc_algo = CAM_TKIP;
2231                         break;
2232                 }
2233
2234                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2235                         macaddr = cam_const_addr[key_index];
2236                         entry_id = key_index;
2237                 } else {
2238                         if (is_group) {
2239                                 macaddr = cam_const_broad;
2240                                 entry_id = key_index;
2241                         } else {
2242                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2243                                         entry_id =
2244                                           rtl_cam_get_free_entry(hw, p_macaddr);
2245                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2246                                                 RT_TRACE(rtlpriv, COMP_SEC,
2247                                                          DBG_EMERG,
2248                                                          "Can not find free hw security cam entry\n");
2249                                                 return;
2250                                         }
2251                                 } else {
2252                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2253                                 }
2254
2255                                 key_index = PAIRWISE_KEYIDX;
2256                                 is_pairwise = true;
2257                         }
2258                 }
2259
2260                 if (rtlpriv->sec.key_len[key_index] == 0) {
2261                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2262                                  "delete one entry, entry_id is %d\n",
2263                                  entry_id);
2264                         if (mac->opmode == NL80211_IFTYPE_AP)
2265                                 rtl_cam_del_entry(hw, p_macaddr);
2266                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2267                 } else {
2268                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2269                                  "add one entry\n");
2270                         if (is_pairwise) {
2271                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2272                                          "set Pairwiase key\n");
2273
2274                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2275                                                       entry_id, enc_algo,
2276                                                       CAM_CONFIG_NO_USEDK,
2277                                                       rtlpriv->sec.key_buf[key_index]);
2278                         } else {
2279                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2280                                          "set group key\n");
2281
2282                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2283                                         rtl_cam_add_one_entry(hw,
2284                                                         rtlefuse->dev_addr,
2285                                                         PAIRWISE_KEYIDX,
2286                                                         CAM_PAIRWISE_KEY_POSITION,
2287                                                         enc_algo,
2288                                                         CAM_CONFIG_NO_USEDK,
2289                                                         rtlpriv->sec.key_buf
2290                                                         [entry_id]);
2291                                 }
2292
2293                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2294                                                 entry_id, enc_algo,
2295                                                 CAM_CONFIG_NO_USEDK,
2296                                                 rtlpriv->sec.key_buf[entry_id]);
2297                         }
2298
2299                 }
2300         }
2301 }
2302
2303 static void rtl8723e_bt_var_init(struct ieee80211_hw *hw)
2304 {
2305         struct rtl_priv *rtlpriv = rtl_priv(hw);
2306
2307         rtlpriv->btcoexist.bt_coexistence =
2308                 rtlpriv->btcoexist.eeprom_bt_coexist;
2309         rtlpriv->btcoexist.bt_ant_num =
2310                 rtlpriv->btcoexist.eeprom_bt_ant_num;
2311         rtlpriv->btcoexist.bt_coexist_type =
2312                 rtlpriv->btcoexist.eeprom_bt_type;
2313
2314         rtlpriv->btcoexist.bt_ant_isolation =
2315                 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2316
2317         rtlpriv->btcoexist.bt_radio_shared_type =
2318                 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2319
2320         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2321                  "BT Coexistance = 0x%x\n",
2322                  rtlpriv->btcoexist.bt_coexistence);
2323
2324         if (rtlpriv->btcoexist.bt_coexistence) {
2325                 rtlpriv->btcoexist.bt_busy_traffic = false;
2326                 rtlpriv->btcoexist.bt_traffic_mode_set = false;
2327                 rtlpriv->btcoexist.bt_non_traffic_mode_set = false;
2328
2329                 rtlpriv->btcoexist.cstate = 0;
2330                 rtlpriv->btcoexist.previous_state = 0;
2331
2332                 if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) {
2333                         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2334                                  "BlueTooth BT_Ant_Num = Antx2\n");
2335                 } else if (rtlpriv->btcoexist.bt_ant_num == ANT_X1) {
2336                         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2337                                  "BlueTooth BT_Ant_Num = Antx1\n");
2338                 }
2339                 switch (rtlpriv->btcoexist.bt_coexist_type) {
2340                 case BT_2WIRE:
2341                         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2342                                  "BlueTooth BT_CoexistType = BT_2Wire\n");
2343                         break;
2344                 case BT_ISSC_3WIRE:
2345                         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2346                                  "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
2347                         break;
2348                 case BT_ACCEL:
2349                         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2350                                  "BlueTooth BT_CoexistType = BT_ACCEL\n");
2351                         break;
2352                 case BT_CSR_BC4:
2353                         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2354                                  "BlueTooth BT_CoexistType = BT_CSR_BC4\n");
2355                         break;
2356                 case BT_CSR_BC8:
2357                         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2358                                  "BlueTooth BT_CoexistType = BT_CSR_BC8\n");
2359                         break;
2360                 case BT_RTL8756:
2361                         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2362                                  "BlueTooth BT_CoexistType = BT_RTL8756\n");
2363                         break;
2364                 default:
2365                         RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2366                                  "BlueTooth BT_CoexistType = Unknown\n");
2367                         break;
2368                 }
2369                 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2370                          "BlueTooth BT_Ant_isolation = %d\n",
2371                          rtlpriv->btcoexist.bt_ant_isolation);
2372                 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2373                          "BT_RadioSharedType = 0x%x\n",
2374                          rtlpriv->btcoexist.bt_radio_shared_type);
2375                 rtlpriv->btcoexist.bt_active_zero_cnt = 0;
2376                 rtlpriv->btcoexist.cur_bt_disabled = false;
2377                 rtlpriv->btcoexist.pre_bt_disabled = false;
2378         }
2379 }
2380
2381 void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2382                                              bool auto_load_fail, u8 *hwinfo)
2383 {
2384         struct rtl_priv *rtlpriv = rtl_priv(hw);
2385         u8 value;
2386         u32 tmpu_32;
2387
2388         if (!auto_load_fail) {
2389                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2390                 if (tmpu_32 & BIT(18))
2391                         rtlpriv->btcoexist.eeprom_bt_coexist = 1;
2392                 else
2393                         rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2394                 value = hwinfo[RF_OPTION4];
2395                 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2396                 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2397                 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2398                 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2399                   ((value & 0x20) >> 5);
2400         } else {
2401                 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2402                 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2403                 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2404                 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2405                 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2406         }
2407
2408         rtl8723e_bt_var_init(hw);
2409 }
2410
2411 void rtl8723e_bt_reg_init(struct ieee80211_hw *hw)
2412 {
2413         struct rtl_priv *rtlpriv = rtl_priv(hw);
2414
2415         /* 0:Low, 1:High, 2:From Efuse. */
2416         rtlpriv->btcoexist.reg_bt_iso = 2;
2417         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2418         rtlpriv->btcoexist.reg_bt_sco = 3;
2419         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2420         rtlpriv->btcoexist.reg_bt_sco = 0;
2421 }
2422
2423 void rtl8723e_bt_hw_init(struct ieee80211_hw *hw)
2424 {
2425         struct rtl_priv *rtlpriv = rtl_priv(hw);
2426
2427         if (rtlpriv->cfg->ops->get_btc_status())
2428                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2429 }
2430
2431 void rtl8723e_suspend(struct ieee80211_hw *hw)
2432 {
2433 }
2434
2435 void rtl8723e_resume(struct ieee80211_hw *hw)
2436 {
2437 }