1 /******************************************************************************
3 * Copyright(c) 2009-2014 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
36 #include "../rtl8723com/phy_common.h"
38 #include "../rtl8723com/dm_common.h"
40 #include "../rtl8723com/fw_common.h"
43 #include "../pwrseqcmd.h"
45 #include "../btcoexist/rtl_btc.h"
49 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
53 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
56 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
57 while (skb_queue_len(&ring->queue)) {
58 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
59 struct sk_buff *skb = __skb_dequeue(&ring->queue);
61 pci_unmap_single(rtlpci->pdev,
62 rtlpriv->cfg->ops->get_desc(
63 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
64 skb->len, PCI_DMA_TODEVICE);
66 ring->idx = (ring->idx + 1) % ring->entries;
68 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
71 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
72 u8 set_bits, u8 clear_bits)
74 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
75 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 rtlpci->reg_bcn_ctrl_val |= set_bits;
78 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
80 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
83 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
85 struct rtl_priv *rtlpriv = rtl_priv(hw);
88 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
89 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
91 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
92 tmp1byte &= ~(BIT(0));
93 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
96 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
98 struct rtl_priv *rtlpriv = rtl_priv(hw);
101 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
102 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
103 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
104 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
106 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
109 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
111 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
114 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
116 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
119 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
120 bool b_need_turn_off_ckk)
122 struct rtl_priv *rtlpriv = rtl_priv(hw);
123 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
124 bool b_support_remote_wake_up;
125 u32 count = 0, isr_regaddr, content;
126 bool b_schedule_timer = b_need_turn_off_ckk;
127 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
128 (u8 *)(&b_support_remote_wake_up));
130 if (!rtlhal->fw_ready)
132 if (!rtlpriv->psc.fw_current_inpsmode)
136 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
137 if (rtlhal->fw_clk_change_in_progress) {
138 while (rtlhal->fw_clk_change_in_progress) {
139 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
144 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
146 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
148 rtlhal->fw_clk_change_in_progress = false;
149 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
154 if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
155 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
157 if (FW_PS_IS_ACK(rpwm_val)) {
158 isr_regaddr = REG_HISR;
159 content = rtl_read_dword(rtlpriv, isr_regaddr);
160 while (!(content & IMR_CPWM) && (count < 500)) {
163 content = rtl_read_dword(rtlpriv, isr_regaddr);
166 if (content & IMR_CPWM) {
167 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
168 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
169 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
170 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
171 rtlhal->fw_ps_state);
175 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
176 rtlhal->fw_clk_change_in_progress = false;
177 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
178 if (b_schedule_timer)
179 mod_timer(&rtlpriv->works.fw_clockoff_timer,
180 jiffies + MSECS(10));
182 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
183 rtlhal->fw_clk_change_in_progress = false;
184 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
188 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
190 struct rtl_priv *rtlpriv = rtl_priv(hw);
191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
193 struct rtl8192_tx_ring *ring;
194 enum rf_pwrstate rtstate;
195 bool b_schedule_timer = false;
198 if (!rtlhal->fw_ready)
200 if (!rtlpriv->psc.fw_current_inpsmode)
202 if (!rtlhal->allow_sw_to_change_hwclc)
204 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
205 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
208 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
209 ring = &rtlpci->tx_ring[queue];
210 if (skb_queue_len(&ring->queue)) {
211 b_schedule_timer = true;
216 if (b_schedule_timer) {
217 mod_timer(&rtlpriv->works.fw_clockoff_timer,
218 jiffies + MSECS(10));
222 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
224 if (!rtlhal->fw_clk_change_in_progress) {
225 rtlhal->fw_clk_change_in_progress = true;
226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
228 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
232 rtlhal->fw_clk_change_in_progress = false;
233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
236 mod_timer(&rtlpriv->works.fw_clockoff_timer,
237 jiffies + MSECS(10));
243 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
246 rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
247 _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
250 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
255 bool fw_current_inps = false;
256 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
258 if (ppsc->low_power_enable) {
259 rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
260 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
261 rtlhal->allow_sw_to_change_hwclc = false;
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
263 (u8 *)(&fw_pwrmode));
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
265 (u8 *)(&fw_current_inps));
267 rpwm_val = FW_PS_STATE_ALL_ON; /* RF on */
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
271 (u8 *)(&fw_pwrmode));
272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
273 (u8 *)(&fw_current_inps));
278 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
280 struct rtl_priv *rtlpriv = rtl_priv(hw);
281 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
282 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
283 bool fw_current_inps = true;
286 if (ppsc->low_power_enable) {
287 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */
288 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
289 (u8 *)(&fw_current_inps));
290 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
291 (u8 *)(&ppsc->fwctrl_psmode));
292 rtlhal->allow_sw_to_change_hwclc = true;
293 _rtl8723be_set_fw_clock_off(hw, rpwm_val);
295 rpwm_val = FW_PS_STATE_RF_OFF; /* RF off */
296 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
297 (u8 *)(&fw_current_inps));
298 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
299 (u8 *)(&ppsc->fwctrl_psmode));
300 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
306 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
308 struct rtl_priv *rtlpriv = rtl_priv(hw);
309 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
310 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
314 *((u32 *)(val)) = rtlpci->receive_config;
316 case HW_VAR_RF_STATE:
317 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
319 case HW_VAR_FWLPS_RF_ON:{
320 enum rf_pwrstate rfState;
323 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
325 if (rfState == ERFOFF) {
326 *((bool *)(val)) = true;
328 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
329 val_rcr &= 0x00070000;
331 *((bool *)(val)) = false;
333 *((bool *)(val)) = true;
337 case HW_VAR_FW_PSMODE_STATUS:
338 *((bool *)(val)) = ppsc->fw_current_inpsmode;
340 case HW_VAR_CORRECT_TSF:{
342 u32 *ptsf_low = (u32 *)&tsf;
343 u32 *ptsf_high = ((u32 *)&tsf) + 1;
345 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
346 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
348 *((u64 *)(val)) = tsf;
352 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
353 "switch case not process %x\n", variable);
358 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
360 struct rtl_priv *rtlpriv = rtl_priv(hw);
361 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
362 u8 count = 0, dlbcn_count = 0;
363 bool b_recover = false;
365 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
366 rtl_write_byte(rtlpriv, REG_CR + 1,
367 (tmp_regcr | BIT(0)));
369 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
370 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
372 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
373 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
374 if (tmp_reg422 & BIT(6))
378 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
379 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
380 (bcnvalid_reg | BIT(0)));
381 _rtl8723be_return_beacon_queue_skb(hw);
383 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
384 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
386 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
389 bcnvalid_reg = rtl_read_byte(rtlpriv,
393 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
395 if (bcnvalid_reg & BIT(0))
396 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
398 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
399 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
402 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
404 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
405 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
408 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
410 struct rtl_priv *rtlpriv = rtl_priv(hw);
411 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
412 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
413 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
414 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
418 case HW_VAR_ETHER_ADDR:
419 for (idx = 0; idx < ETH_ALEN; idx++)
420 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
422 case HW_VAR_BASIC_RATE:{
423 u16 b_rate_cfg = ((u16 *)val)[0];
425 b_rate_cfg = b_rate_cfg & 0x15f;
427 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
428 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
429 while (b_rate_cfg > 0x1) {
430 b_rate_cfg = (b_rate_cfg >> 1);
433 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
437 for (idx = 0; idx < ETH_ALEN; idx++)
438 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
442 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
443 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
445 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
446 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
449 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
451 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
454 case HW_VAR_SLOT_TIME:{
457 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
458 "HW_VAR_SLOT_TIME %x\n", val[0]);
460 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
462 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
463 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
468 case HW_VAR_ACK_PREAMBLE:{
470 u8 short_preamble = (bool)(*(u8 *)val);
471 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
472 if (short_preamble) {
474 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
477 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
481 case HW_VAR_WPA_CONFIG:
482 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
484 case HW_VAR_AMPDU_MIN_SPACE:{
485 u8 min_spacing_to_set;
488 min_spacing_to_set = *((u8 *)val);
489 if (min_spacing_to_set <= 7) {
492 if (min_spacing_to_set < sec_min_space)
493 min_spacing_to_set = sec_min_space;
495 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
498 *val = min_spacing_to_set;
500 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
501 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
504 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
509 case HW_VAR_SHORTGI_DENSITY:{
512 density_to_set = *((u8 *)val);
513 mac->min_space_cfg |= (density_to_set << 3);
515 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
516 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
519 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
523 case HW_VAR_AMPDU_FACTOR:{
524 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
526 u8 *p_regtoset = NULL;
529 p_regtoset = regtoset_normal;
531 factor_toset = *((u8 *)val);
532 if (factor_toset <= 3) {
533 factor_toset = (1 << (factor_toset + 2));
534 if (factor_toset > 0xf)
537 for (index = 0; index < 4; index++) {
538 if ((p_regtoset[index] & 0xf0) >
541 (p_regtoset[index] & 0x0f) |
544 if ((p_regtoset[index] & 0x0f) > factor_toset)
546 (p_regtoset[index] & 0xf0) |
549 rtl_write_byte(rtlpriv,
550 (REG_AGGLEN_LMT + index),
555 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
556 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
561 case HW_VAR_AC_PARAM:{
562 u8 e_aci = *((u8 *)val);
563 rtl8723_dm_init_edca_turbo(hw);
565 if (rtlpci->acm_method != EACMWAY2_SW)
566 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
570 case HW_VAR_ACM_CTRL:{
571 u8 e_aci = *((u8 *)val);
572 union aci_aifsn *p_aci_aifsn =
573 (union aci_aifsn *)(&(mac->ac[0].aifs));
574 u8 acm = p_aci_aifsn->f.acm;
575 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
578 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
583 acm_ctrl |= ACMHW_BEQEN;
586 acm_ctrl |= ACMHW_VIQEN;
589 acm_ctrl |= ACMHW_VOQEN;
592 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
593 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
600 acm_ctrl &= (~ACMHW_BEQEN);
603 acm_ctrl &= (~ACMHW_VIQEN);
606 acm_ctrl &= (~ACMHW_VOQEN);
609 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
610 "switch case not process\n");
615 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
616 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
618 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
622 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
623 rtlpci->receive_config = ((u32 *)(val))[0];
625 case HW_VAR_RETRY_LIMIT:{
626 u8 retry_limit = ((u8 *)(val))[0];
628 rtl_write_word(rtlpriv, REG_RL,
629 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
630 retry_limit << RETRY_LIMIT_LONG_SHIFT);
633 case HW_VAR_DUAL_TSF_RST:
634 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
636 case HW_VAR_EFUSE_BYTES:
637 rtlefuse->efuse_usedbytes = *((u16 *)val);
639 case HW_VAR_EFUSE_USAGE:
640 rtlefuse->efuse_usedpercentage = *((u8 *)val);
643 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
645 case HW_VAR_SET_RPWM:{
648 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
651 if (rpwm_val & BIT(7)) {
652 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
654 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
655 ((*(u8 *)val) | BIT(7)));
659 case HW_VAR_H2C_FW_PWRMODE:
660 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
662 case HW_VAR_FW_PSMODE_STATUS:
663 ppsc->fw_current_inpsmode = *((bool *)val);
665 case HW_VAR_RESUME_CLK_ON:
666 _rtl8723be_set_fw_ps_rf_on(hw);
668 case HW_VAR_FW_LPS_ACTION:{
669 bool b_enter_fwlps = *((bool *)val);
672 _rtl8723be_fwlps_enter(hw);
674 _rtl8723be_fwlps_leave(hw);
677 case HW_VAR_H2C_FW_JOINBSSRPT:{
678 u8 mstatus = (*(u8 *)val);
680 if (mstatus == RT_MEDIA_CONNECT) {
681 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
682 _rtl8723be_download_rsvd_page(hw);
684 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
687 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
688 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
692 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
694 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
695 (u2btmp | mac->assoc_id));
698 case HW_VAR_CORRECT_TSF:{
699 u8 btype_ibss = ((u8 *)(val))[0];
702 _rtl8723be_stop_tx_beacon(hw);
704 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
706 rtl_write_dword(rtlpriv, REG_TSFTR,
707 (u32) (mac->tsf & 0xffffffff));
708 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
709 (u32) ((mac->tsf >> 32) & 0xffffffff));
711 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
714 _rtl8723be_resume_tx_beacon(hw);
717 case HW_VAR_KEEP_ALIVE:{
720 array[1] = *((u8 *)val);
721 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
725 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
726 "switch case not process %x\n",
732 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
734 struct rtl_priv *rtlpriv = rtl_priv(hw);
737 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
738 _LLT_OP(_LLT_WRITE_ACCESS);
740 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
743 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
744 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
747 if (count > POLLING_LLT_THRESHOLD) {
748 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
749 "Failed to polling write LLT done at address %d!\n",
759 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
761 struct rtl_priv *rtlpriv = rtl_priv(hw);
770 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
771 (0x27FF0000 | txpktbuf_bndy));
772 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
774 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
775 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
777 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
778 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
779 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
781 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
782 status = _rtl8723be_llt_write(hw, i, i + 1);
787 status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
792 for (i = txpktbuf_bndy; i < maxPage; i++) {
793 status = _rtl8723be_llt_write(hw, i, (i + 1));
798 status = _rtl8723be_llt_write(hw, maxPage, txpktbuf_bndy);
802 rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
803 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
808 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
810 struct rtl_priv *rtlpriv = rtl_priv(hw);
811 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
812 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
813 struct rtl_led *pled0 = &(pcipriv->ledctl.sw_led0);
815 if (rtlpriv->rtlhal.up_first_time)
818 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
819 rtl8723be_sw_led_on(hw, pled0);
820 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
821 rtl8723be_sw_led_on(hw, pled0);
823 rtl8723be_sw_led_off(hw, pled0);
826 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
828 struct rtl_priv *rtlpriv = rtl_priv(hw);
829 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
830 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
831 unsigned char bytetmp;
832 unsigned short wordtmp;
834 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
836 /*Auto Power Down to CHIP-off State*/
837 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
838 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
840 /* HW Power on sequence */
841 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
842 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
843 RTL8723_NIC_ENABLE_FLOW)) {
844 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
845 "init MAC Fail as power on failure\n");
849 bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
850 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
852 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
853 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
855 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
857 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
860 bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
862 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
865 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
866 if (bytetmp & BIT(0)) {
867 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
868 rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
871 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
872 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
873 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
874 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
876 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
878 if (!rtlhal->mac_func_enable) {
879 if (_rtl8723be_llt_table_init(hw) == false)
883 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
884 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
886 /* Enable FW Beamformer Interrupt */
887 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
888 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
890 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
893 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
895 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
896 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
897 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
898 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
900 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
901 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
903 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
904 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
906 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
907 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
908 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
909 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
910 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
911 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
912 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
913 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
914 rtl_write_dword(rtlpriv, REG_HQ_DESA,
915 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
917 rtl_write_dword(rtlpriv, REG_RX_DESA,
918 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
921 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
922 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
924 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
926 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
928 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
930 /* <20130114, Kordan> The following setting is
931 * only for DPDT and Fixed board type.
932 * TODO: A better solution is configure it
933 * according EFUSE during the run-time.
935 rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
936 rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
937 rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
938 rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
939 rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
940 rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
941 rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
942 rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
944 bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
945 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
947 _rtl8723be_gen_refresh_led_state(hw);
951 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
953 struct rtl_priv *rtlpriv = rtl_priv(hw);
954 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
957 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
958 /* Init value for RRSR. */
959 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
961 /* ARFB table 9 for 11ac 5G 2SS */
962 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
964 /* ARFB table 10 for 11ac 5G 1SS */
965 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
967 /* CF-End setting. */
968 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
970 /* 0x456 = 0x70, sugguested by Zhilin */
971 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
973 /* Set retry limit */
974 rtl_write_word(rtlpriv, REG_RL, 0x0707);
976 /* Set Data / Response auto rate fallack retry count */
977 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
978 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
979 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
980 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
982 rtlpci->reg_bcn_ctrl_val = 0x1d;
983 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
985 /* TBTT prohibit hold time. Suggested by designer TimChen. */
986 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
988 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
990 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
991 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
993 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
995 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
997 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
1000 static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1002 u16 read_addr = addr & 0xfffc;
1003 u8 ret = 0, tmp = 0, count = 0;
1005 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1006 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1007 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1009 while (tmp && count < 20) {
1011 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1015 read_addr = REG_DBI_RDATA + addr % 4;
1016 ret = rtl_read_byte(rtlpriv, read_addr);
1022 static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1024 u8 tmp = 0, count = 0;
1025 u16 write_addr = 0, remainder = addr % 4;
1027 /* Write DBI 1Byte Data */
1028 write_addr = REG_DBI_WDATA + remainder;
1029 rtl_write_byte(rtlpriv, write_addr, data);
1031 /* Write DBI 2Byte Address & Write Enable */
1032 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1033 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1035 /* Write DBI Write Flag */
1036 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1038 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1040 while (tmp && count < 20) {
1042 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1047 static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1050 u8 tmp = 0, count = 0;
1052 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1053 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1055 while (tmp && count < 20) {
1057 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1062 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1067 static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1069 u8 tmp = 0, count = 0;
1071 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1072 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1073 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1075 while (tmp && count < 20) {
1077 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1082 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
1084 struct rtl_priv *rtlpriv = rtl_priv(hw);
1088 /* <Roger_Notes> Overwrite following ePHY parameter for
1089 * some platform compatibility issue,
1090 * especially when CLKReq is enabled, 2012.11.09.
1092 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
1093 if (tmp16 != 0x0663)
1094 _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
1096 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
1097 if (tmp16 != 0x7544)
1098 _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
1100 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
1101 if (tmp16 != 0xB880)
1102 _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
1104 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
1105 if (tmp16 != 0x4000)
1106 _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
1108 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
1109 if (tmp16 != 0x9003)
1110 _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
1112 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
1113 if (tmp16 != 0x0D03)
1114 _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
1116 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
1117 if (tmp16 != 0x4037)
1118 _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
1120 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
1121 if (tmp16 != 0x0070)
1122 _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
1124 /* Configuration Space offset 0x70f BIT7 is used to control L0S */
1125 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
1126 _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7));
1128 /* Configuration Space offset 0x719 Bit3 is for L1
1129 * BIT4 is for clock request
1131 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
1132 _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
1135 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
1137 struct rtl_priv *rtlpriv = rtl_priv(hw);
1140 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1141 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1142 rtlpriv->sec.pairwise_enc_algorithm,
1143 rtlpriv->sec.group_enc_algorithm);
1145 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1146 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1147 "not open hw encryption\n");
1151 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1153 if (rtlpriv->sec.use_defaultkey) {
1154 sec_reg_value |= SCR_TXUSEDK;
1155 sec_reg_value |= SCR_RXUSEDK;
1158 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1160 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1162 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1163 "The SECR-value %x\n", sec_reg_value);
1165 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1168 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1170 struct rtl_priv *rtlpriv = rtl_priv(hw);
1171 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1174 rtlhal->mac_func_enable = false;
1175 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1176 /* 1. Run LPS WL RFOFF flow */
1177 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1178 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1180 /* 2. 0x1F[7:0] = 0 */
1182 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1183 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1185 rtl8723be_firmware_selfreset(hw);
1188 /* Reset MCU. Suggested by Filen. */
1189 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1190 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1192 /* g. MCUFWDL 0x80[1:0]=0 */
1193 /* reset MCU ready status */
1194 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1196 /* HW card disable configuration. */
1197 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1198 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1200 /* Reset MCU IO Wrapper */
1201 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1202 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1203 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1204 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1206 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1207 /* lock ISO/CLK/Power control register */
1208 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1211 static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1215 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1216 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1217 if (!(tmp & BIT(2))) {
1218 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1219 mdelay(100); /* Suggested by DD Justin_tsai. */
1222 /* read reg 0x350 Bit[25] if 1 : RX hang
1223 * read reg 0x350 Bit[24] if 1 : TX hang
1225 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1226 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1227 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1228 "CheckPcieDMAHang8723BE(): true!!\n");
1234 static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1238 bool release_mac_rx_pause;
1239 u8 backup_pcie_dma_pause;
1241 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1242 "ResetPcieInterfaceDMA8723BE()\n");
1244 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1245 * released by SD1 Alan.
1246 * 2013.05.07, by tynli.
1249 /* 1. disable register write lock
1250 * write 0x1C bit[1:0] = 2'h0
1251 * write 0xCC bit[2] = 1'b1
1253 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1254 tmp &= ~(BIT(1) | BIT(0));
1255 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1256 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1258 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1260 /* 2. Check and pause TRX DMA
1261 * write 0x284 bit[18] = 1'b1
1262 * write 0x301 = 0xFF
1264 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1266 /* Already pause before the function for another purpose. */
1267 release_mac_rx_pause = false;
1269 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1270 release_mac_rx_pause = true;
1273 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1274 if (backup_pcie_dma_pause != 0xFF)
1275 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1278 /* 3. reset TRX function
1279 * write 0x100 = 0x00
1281 rtl_write_byte(rtlpriv, REG_CR, 0);
1284 /* 4. Reset PCIe DMA
1285 * write 0x003 bit[0] = 0
1287 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1289 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1291 /* 5. Enable PCIe DMA
1292 * write 0x003 bit[0] = 1
1294 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1296 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1299 /* 6. enable TRX function
1300 * write 0x100 = 0xFF
1302 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1304 /* We should init LLT & RQPN and
1305 * prepare Tx/Rx descrptor address later
1306 * because MAC function is reset.
1310 /* 7. Restore PCIe autoload down bit
1311 * write 0xF8 bit[17] = 1'b1
1313 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1315 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1317 /* In MAC power on state, BB and RF maybe in ON state,
1318 * if we release TRx DMA here
1319 * it will cause packets to be started to Tx/Rx,
1320 * so we release Tx/Rx DMA later.
1322 if (!mac_power_on) {
1323 /* 8. release TRX DMA
1324 * write 0x284 bit[18] = 1'b0
1325 * write 0x301 = 0x00
1327 if (release_mac_rx_pause) {
1328 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1329 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1332 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1333 backup_pcie_dma_pause);
1336 /* 9. lock system register
1337 * write 0xCC bit[2] = 1'b0
1339 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1341 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1344 int rtl8723be_hw_init(struct ieee80211_hw *hw)
1346 struct rtl_priv *rtlpriv = rtl_priv(hw);
1347 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1348 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1349 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1350 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1351 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1352 bool rtstatus = true;
1355 unsigned long flags;
1357 /* reenable interrupts to not interfere with other devices */
1358 local_save_flags(flags);
1361 rtlhal->fw_ready = false;
1362 rtlpriv->rtlhal.being_init_adapter = true;
1363 rtlpriv->intf_ops->disable_aspm(hw);
1365 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1366 if (tmp_u1b != 0 && tmp_u1b != 0xea) {
1367 rtlhal->mac_func_enable = true;
1369 rtlhal->mac_func_enable = false;
1370 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
1373 if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
1374 _rtl8723be_reset_pcie_interface_dma(rtlpriv,
1375 rtlhal->mac_func_enable);
1376 rtlhal->mac_func_enable = false;
1378 if (rtlhal->mac_func_enable) {
1379 _rtl8723be_poweroff_adapter(hw);
1380 rtlhal->mac_func_enable = false;
1382 rtstatus = _rtl8723be_init_mac(hw);
1384 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1389 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1390 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
1392 err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
1394 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1395 "Failed to download FW. Init HW without FW now..\n");
1399 rtlhal->fw_ready = true;
1401 rtlhal->last_hmeboxnum = 0;
1402 rtl8723be_phy_mac_config(hw);
1403 /* because last function modify RCR, so we update
1404 * rcr var here, or TP will unstable for receive_config
1405 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1406 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1408 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1409 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1410 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1412 rtl8723be_phy_bb_config(hw);
1413 rtl8723be_phy_rf_config(hw);
1415 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1416 RF_CHNLBW, RFREG_OFFSET_MASK);
1417 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1418 RF_CHNLBW, RFREG_OFFSET_MASK);
1419 rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1420 rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1422 _rtl8723be_hw_configure(hw);
1423 rtlhal->mac_func_enable = true;
1424 rtl_cam_reset_all_entry(hw);
1425 rtl8723be_enable_hw_security_config(hw);
1427 ppsc->rfpwr_state = ERFON;
1429 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1430 _rtl8723be_enable_aspm_back_door(hw);
1431 rtlpriv->intf_ops->enable_aspm(hw);
1433 rtl8723be_bt_hw_init(hw);
1435 if (ppsc->rfpwr_state == ERFON) {
1436 rtl8723be_phy_set_rfpath_switch(hw, 1);
1437 /* when use 1ant NIC, iqk will disturb BT music
1438 * root cause is not clear now, is something
1439 * related with 'mdelay' and Reg[0x948]
1441 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
1442 !rtlpriv->cfg->ops->get_btc_status()) {
1443 rtl8723be_phy_iq_calibrate(hw, false);
1444 rtlphy->iqk_initialized = true;
1446 rtl8723be_dm_check_txpower_tracking(hw);
1447 rtl8723be_phy_lc_calibrate(hw);
1449 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1451 /* Release Rx DMA. */
1452 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1453 if (tmp_u1b & BIT(2)) {
1454 /* Release Rx DMA if needed */
1455 tmp_u1b &= (~BIT(2));
1456 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1458 /* Release Tx/Rx PCIE DMA. */
1459 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1461 rtl8723be_dm_init(hw);
1463 local_irq_restore(flags);
1464 rtlpriv->rtlhal.being_init_adapter = false;
1468 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1470 struct rtl_priv *rtlpriv = rtl_priv(hw);
1471 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1472 enum version_8723e version = VERSION_UNKNOWN;
1475 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1476 if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1477 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n");
1479 version = (enum version_8723e)CHIP_8723B;
1481 rtlphy->rf_type = RF_1T1R;
1483 /* treat rtl8723be chip as MP version in default */
1484 version = (enum version_8723e)(version | NORMAL_CHIP);
1486 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1488 version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
1490 if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
1491 version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
1493 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1494 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1495 "RF_2T2R" : "RF_1T1R");
1500 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1501 enum nl80211_iftype type)
1503 struct rtl_priv *rtlpriv = rtl_priv(hw);
1504 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1505 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1506 u8 mode = MSR_NOLINK;
1509 case NL80211_IFTYPE_UNSPECIFIED:
1511 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1512 "Set Network type to NO LINK!\n");
1514 case NL80211_IFTYPE_ADHOC:
1515 case NL80211_IFTYPE_MESH_POINT:
1517 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1518 "Set Network type to Ad Hoc!\n");
1520 case NL80211_IFTYPE_STATION:
1522 ledaction = LED_CTL_LINK;
1523 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1524 "Set Network type to STA!\n");
1526 case NL80211_IFTYPE_AP:
1528 ledaction = LED_CTL_LINK;
1529 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1530 "Set Network type to AP!\n");
1533 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1534 "Network type %d not support!\n", type);
1538 /* MSR_INFRA == Link in infrastructure network;
1539 * MSR_ADHOC == Link in ad hoc network;
1540 * Therefore, check link state is necessary.
1542 * MSR_AP == AP mode; link state is not cared here.
1544 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1546 ledaction = LED_CTL_NO_LINK;
1549 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1550 _rtl8723be_stop_tx_beacon(hw);
1551 _rtl8723be_enable_bcn_sub_func(hw);
1552 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1553 _rtl8723be_resume_tx_beacon(hw);
1554 _rtl8723be_disable_bcn_sub_func(hw);
1556 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1557 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1561 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1562 rtlpriv->cfg->ops->led_control(hw, ledaction);
1564 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1566 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1570 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1572 struct rtl_priv *rtlpriv = rtl_priv(hw);
1573 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1574 u32 reg_rcr = rtlpci->receive_config;
1576 if (rtlpriv->psc.rfpwr_state != ERFON)
1580 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1581 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1583 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1584 } else if (!check_bssid) {
1585 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1586 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1587 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1593 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1594 enum nl80211_iftype type)
1596 struct rtl_priv *rtlpriv = rtl_priv(hw);
1598 if (_rtl8723be_set_media_status(hw, type))
1601 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1602 if (type != NL80211_IFTYPE_AP)
1603 rtl8723be_set_check_bssid(hw, true);
1605 rtl8723be_set_check_bssid(hw, false);
1611 /* don't set REG_EDCA_BE_PARAM here
1612 * because mac80211 will send pkt when scan
1614 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1616 struct rtl_priv *rtlpriv = rtl_priv(hw);
1618 rtl8723_dm_init_edca_turbo(hw);
1621 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1626 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1629 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1632 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1637 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1639 struct rtl_priv *rtlpriv = rtl_priv(hw);
1640 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1642 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1643 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1644 rtlpci->irq_enabled = true;
1646 /*enable system interrupt*/
1647 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1650 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1652 struct rtl_priv *rtlpriv = rtl_priv(hw);
1653 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1655 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1656 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1657 rtlpci->irq_enabled = false;
1658 /*synchronize_irq(rtlpci->pdev->irq);*/
1661 void rtl8723be_card_disable(struct ieee80211_hw *hw)
1663 struct rtl_priv *rtlpriv = rtl_priv(hw);
1664 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1665 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1666 enum nl80211_iftype opmode;
1668 mac->link_state = MAC80211_NOLINK;
1669 opmode = NL80211_IFTYPE_UNSPECIFIED;
1670 _rtl8723be_set_media_status(hw, opmode);
1671 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1672 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1673 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1674 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1675 _rtl8723be_poweroff_adapter(hw);
1677 /* after power off we should do iqk again */
1678 rtlpriv->phy.iqk_initialized = false;
1681 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
1682 u32 *p_inta, u32 *p_intb)
1684 struct rtl_priv *rtlpriv = rtl_priv(hw);
1685 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1687 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1688 rtl_write_dword(rtlpriv, ISR, *p_inta);
1690 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) &
1691 rtlpci->irq_mask[1];
1692 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1695 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
1697 struct rtl_priv *rtlpriv = rtl_priv(hw);
1698 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1699 u16 bcn_interval, atim_window;
1701 bcn_interval = mac->beacon_interval;
1702 atim_window = 2; /*FIX MERGE */
1703 rtl8723be_disable_interrupt(hw);
1704 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1705 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1706 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1707 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1708 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1709 rtl_write_byte(rtlpriv, 0x606, 0x30);
1710 rtl8723be_enable_interrupt(hw);
1713 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
1715 struct rtl_priv *rtlpriv = rtl_priv(hw);
1716 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1717 u16 bcn_interval = mac->beacon_interval;
1719 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1720 "beacon_interval:%d\n", bcn_interval);
1721 rtl8723be_disable_interrupt(hw);
1722 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1723 rtl8723be_enable_interrupt(hw);
1726 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
1727 u32 add_msr, u32 rm_msr)
1729 struct rtl_priv *rtlpriv = rtl_priv(hw);
1730 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1732 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1733 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1736 rtlpci->irq_mask[0] |= add_msr;
1738 rtlpci->irq_mask[0] &= (~rm_msr);
1739 rtl8723be_disable_interrupt(hw);
1740 rtl8723be_enable_interrupt(hw);
1743 static u8 _rtl8723be_get_chnl_group(u8 chnl)
1756 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1757 struct txpower_info_2g *pw2g,
1758 struct txpower_info_5g *pw5g,
1759 bool autoload_fail, u8 *hwinfo)
1761 struct rtl_priv *rtlpriv = rtl_priv(hw);
1762 u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1764 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1765 "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1766 (addr + 1), hwinfo[addr + 1]);
1767 if (0xFF == hwinfo[addr + 1]) /*YJ,add,120316*/
1768 autoload_fail = true;
1770 if (autoload_fail) {
1771 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1772 "auto load fail : Use Default value!\n");
1773 for (path = 0; path < MAX_RF_PATH; path++) {
1774 /* 2.4G default value */
1775 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1776 pw2g->index_cck_base[path][group] = 0x2D;
1777 pw2g->index_bw40_base[path][group] = 0x2D;
1779 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1781 pw2g->bw20_diff[path][0] = 0x02;
1782 pw2g->ofdm_diff[path][0] = 0x04;
1784 pw2g->bw20_diff[path][cnt] = 0xFE;
1785 pw2g->bw40_diff[path][cnt] = 0xFE;
1786 pw2g->cck_diff[path][cnt] = 0xFE;
1787 pw2g->ofdm_diff[path][cnt] = 0xFE;
1794 for (path = 0; path < MAX_RF_PATH; path++) {
1795 /*2.4G default value*/
1796 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1797 pw2g->index_cck_base[path][group] = hwinfo[addr++];
1798 if (pw2g->index_cck_base[path][group] == 0xFF)
1799 pw2g->index_cck_base[path][group] = 0x2D;
1802 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1803 pw2g->index_bw40_base[path][group] = hwinfo[addr++];
1804 if (pw2g->index_bw40_base[path][group] == 0xFF)
1805 pw2g->index_bw40_base[path][group] = 0x2D;
1807 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1809 pw2g->bw40_diff[path][cnt] = 0;
1810 if (hwinfo[addr] == 0xFF) {
1811 pw2g->bw20_diff[path][cnt] = 0x02;
1813 pw2g->bw20_diff[path][cnt] =
1814 (hwinfo[addr] & 0xf0) >> 4;
1815 /*bit sign number to 8 bit sign number*/
1816 if (pw2g->bw20_diff[path][cnt] & BIT(3))
1817 pw2g->bw20_diff[path][cnt] |=
1821 if (hwinfo[addr] == 0xFF) {
1822 pw2g->ofdm_diff[path][cnt] = 0x04;
1824 pw2g->ofdm_diff[path][cnt] =
1825 (hwinfo[addr] & 0x0f);
1826 /*bit sign number to 8 bit sign number*/
1827 if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1828 pw2g->ofdm_diff[path][cnt] |=
1831 pw2g->cck_diff[path][cnt] = 0;
1834 if (hwinfo[addr] == 0xFF) {
1835 pw2g->bw40_diff[path][cnt] = 0xFE;
1837 pw2g->bw40_diff[path][cnt] =
1838 (hwinfo[addr] & 0xf0) >> 4;
1839 if (pw2g->bw40_diff[path][cnt] & BIT(3))
1840 pw2g->bw40_diff[path][cnt] |=
1844 if (hwinfo[addr] == 0xFF) {
1845 pw2g->bw20_diff[path][cnt] = 0xFE;
1847 pw2g->bw20_diff[path][cnt] =
1848 (hwinfo[addr] & 0x0f);
1849 if (pw2g->bw20_diff[path][cnt] & BIT(3))
1850 pw2g->bw20_diff[path][cnt] |=
1855 if (hwinfo[addr] == 0xFF) {
1856 pw2g->ofdm_diff[path][cnt] = 0xFE;
1858 pw2g->ofdm_diff[path][cnt] =
1859 (hwinfo[addr] & 0xf0) >> 4;
1860 if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1861 pw2g->ofdm_diff[path][cnt] |=
1865 if (hwinfo[addr] == 0xFF)
1866 pw2g->cck_diff[path][cnt] = 0xFE;
1868 pw2g->cck_diff[path][cnt] =
1869 (hwinfo[addr] & 0x0f);
1870 if (pw2g->cck_diff[path][cnt] & BIT(3))
1871 pw2g->cck_diff[path][cnt] |=
1878 /*5G default value*/
1879 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1880 pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1881 if (pw5g->index_bw40_base[path][group] == 0xFF)
1882 pw5g->index_bw40_base[path][group] = 0xFE;
1885 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1887 pw5g->bw40_diff[path][cnt] = 0;
1889 if (hwinfo[addr] == 0xFF) {
1890 pw5g->bw20_diff[path][cnt] = 0;
1892 pw5g->bw20_diff[path][0] =
1893 (hwinfo[addr] & 0xf0) >> 4;
1894 if (pw5g->bw20_diff[path][cnt] & BIT(3))
1895 pw5g->bw20_diff[path][cnt] |=
1899 if (hwinfo[addr] == 0xFF)
1900 pw5g->ofdm_diff[path][cnt] = 0x04;
1902 pw5g->ofdm_diff[path][0] =
1903 (hwinfo[addr] & 0x0f);
1904 if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1905 pw5g->ofdm_diff[path][cnt] |=
1910 if (hwinfo[addr] == 0xFF) {
1911 pw5g->bw40_diff[path][cnt] = 0xFE;
1913 pw5g->bw40_diff[path][cnt] =
1914 (hwinfo[addr] & 0xf0) >> 4;
1915 if (pw5g->bw40_diff[path][cnt] & BIT(3))
1916 pw5g->bw40_diff[path][cnt] |= 0xF0;
1919 if (hwinfo[addr] == 0xFF) {
1920 pw5g->bw20_diff[path][cnt] = 0xFE;
1922 pw5g->bw20_diff[path][cnt] =
1923 (hwinfo[addr] & 0x0f);
1924 if (pw5g->bw20_diff[path][cnt] & BIT(3))
1925 pw5g->bw20_diff[path][cnt] |= 0xF0;
1931 if (hwinfo[addr] == 0xFF) {
1932 pw5g->ofdm_diff[path][1] = 0xFE;
1933 pw5g->ofdm_diff[path][2] = 0xFE;
1935 pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
1936 pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
1940 if (hwinfo[addr] == 0xFF)
1941 pw5g->ofdm_diff[path][3] = 0xFE;
1943 pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
1946 for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
1947 if (pw5g->ofdm_diff[path][cnt] == 0xFF)
1948 pw5g->ofdm_diff[path][cnt] = 0xFE;
1949 else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1950 pw5g->ofdm_diff[path][cnt] |= 0xF0;
1955 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1959 struct rtl_priv *rtlpriv = rtl_priv(hw);
1960 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1961 struct txpower_info_2g pw2g;
1962 struct txpower_info_5g pw5g;
1966 _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
1969 for (rf_path = 0; rf_path < 2; rf_path++) {
1970 for (i = 0; i < 14; i++) {
1971 index = _rtl8723be_get_chnl_group(i+1);
1973 rtlefuse->txpwrlevel_cck[rf_path][i] =
1974 pw2g.index_cck_base[rf_path][index];
1975 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1976 pw2g.index_bw40_base[rf_path][index];
1978 for (i = 0; i < MAX_TX_COUNT; i++) {
1979 rtlefuse->txpwr_ht20diff[rf_path][i] =
1980 pw2g.bw20_diff[rf_path][i];
1981 rtlefuse->txpwr_ht40diff[rf_path][i] =
1982 pw2g.bw40_diff[rf_path][i];
1983 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1984 pw2g.ofdm_diff[rf_path][i];
1987 for (i = 0; i < 14; i++) {
1988 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1989 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1991 rtlefuse->txpwrlevel_cck[rf_path][i],
1992 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1997 rtlefuse->eeprom_thermalmeter =
1998 hwinfo[EEPROM_THERMAL_METER_88E];
2000 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2002 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
2003 rtlefuse->apk_thermalmeterignore = true;
2004 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2007 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2008 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2009 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
2011 if (!autoload_fail) {
2012 rtlefuse->eeprom_regulatory =
2013 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
2014 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2015 rtlefuse->eeprom_regulatory = 0;
2017 rtlefuse->eeprom_regulatory = 0;
2019 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2020 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2023 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
2026 struct rtl_priv *rtlpriv = rtl_priv(hw);
2027 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2028 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2029 int params[] = {RTL8723BE_EEPROM_ID, EEPROM_VID, EEPROM_DID,
2030 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
2031 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
2032 COUNTRY_CODE_WORLD_WIDE_13};
2035 bool is_toshiba_smid1 = false;
2036 bool is_toshiba_smid2 = false;
2037 bool is_samsung_smid = false;
2038 bool is_lenovo_smid = false;
2039 u16 toshiba_smid1[] = {
2040 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
2041 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
2042 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
2043 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
2045 u16 toshiba_smid2[] = {
2046 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
2047 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
2049 u16 samsung_smid[] = {
2050 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
2051 0x8193, 0x9191, 0x9192, 0x9193
2053 u16 lenovo_smid[] = {
2054 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
2058 /* needs to be added */
2062 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
2066 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
2070 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
2071 if (rtlefuse->crystalcap == 0xFF)
2072 rtlefuse->crystalcap = 0x20;
2074 _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2077 rtl8723be_read_bt_coexist_info_from_hwpg(hw,
2078 rtlefuse->autoload_failflag,
2081 /* set channel plan from efuse */
2082 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
2084 if (rtlhal->oem_id == RT_CID_DEFAULT) {
2085 /* Does this one have a Toshiba SMID from group 1? */
2086 for (i = 0; i < sizeof(toshiba_smid1) / sizeof(u16); i++) {
2087 if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
2088 is_toshiba_smid1 = true;
2092 /* Does this one have a Toshiba SMID from group 2? */
2093 for (i = 0; i < sizeof(toshiba_smid2) / sizeof(u16); i++) {
2094 if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
2095 is_toshiba_smid2 = true;
2099 /* Does this one have a Samsung SMID? */
2100 for (i = 0; i < sizeof(samsung_smid) / sizeof(u16); i++) {
2101 if (rtlefuse->eeprom_smid == samsung_smid[i]) {
2102 is_samsung_smid = true;
2106 /* Does this one have a Lenovo SMID? */
2107 for (i = 0; i < sizeof(lenovo_smid) / sizeof(u16); i++) {
2108 if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
2109 is_lenovo_smid = true;
2113 switch (rtlefuse->eeprom_oemid) {
2114 case EEPROM_CID_DEFAULT:
2115 if (rtlefuse->eeprom_did == 0x8176) {
2116 if (rtlefuse->eeprom_svid == 0x10EC &&
2118 rtlhal->oem_id = RT_CID_TOSHIBA;
2119 } else if (rtlefuse->eeprom_svid == 0x1025) {
2120 rtlhal->oem_id = RT_CID_819X_ACER;
2121 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2123 rtlhal->oem_id = RT_CID_819X_SAMSUNG;
2124 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2126 rtlhal->oem_id = RT_CID_819X_LENOVO;
2127 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2128 rtlefuse->eeprom_smid == 0x8197) ||
2129 (rtlefuse->eeprom_svid == 0x10EC &&
2130 rtlefuse->eeprom_smid == 0x9196)) {
2131 rtlhal->oem_id = RT_CID_819X_CLEVO;
2132 } else if ((rtlefuse->eeprom_svid == 0x1028 &&
2133 rtlefuse->eeprom_smid == 0x8194) ||
2134 (rtlefuse->eeprom_svid == 0x1028 &&
2135 rtlefuse->eeprom_smid == 0x8198) ||
2136 (rtlefuse->eeprom_svid == 0x1028 &&
2137 rtlefuse->eeprom_smid == 0x9197) ||
2138 (rtlefuse->eeprom_svid == 0x1028 &&
2139 rtlefuse->eeprom_smid == 0x9198)) {
2140 rtlhal->oem_id = RT_CID_819X_DELL;
2141 } else if ((rtlefuse->eeprom_svid == 0x103C &&
2142 rtlefuse->eeprom_smid == 0x1629)) {
2143 rtlhal->oem_id = RT_CID_819X_HP;
2144 } else if ((rtlefuse->eeprom_svid == 0x1A32 &&
2145 rtlefuse->eeprom_smid == 0x2315)) {
2146 rtlhal->oem_id = RT_CID_819X_QMI;
2147 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2148 rtlefuse->eeprom_smid == 0x8203)) {
2149 rtlhal->oem_id = RT_CID_819X_PRONETS;
2150 } else if ((rtlefuse->eeprom_svid == 0x1043 &&
2151 rtlefuse->eeprom_smid == 0x84B5)) {
2152 rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
2154 rtlhal->oem_id = RT_CID_DEFAULT;
2156 } else if (rtlefuse->eeprom_did == 0x8178) {
2157 if (rtlefuse->eeprom_svid == 0x10EC &&
2159 rtlhal->oem_id = RT_CID_TOSHIBA;
2160 else if (rtlefuse->eeprom_svid == 0x1025)
2161 rtlhal->oem_id = RT_CID_819X_ACER;
2162 else if ((rtlefuse->eeprom_svid == 0x10EC &&
2163 rtlefuse->eeprom_smid == 0x8186))
2164 rtlhal->oem_id = RT_CID_819X_PRONETS;
2165 else if ((rtlefuse->eeprom_svid == 0x1043 &&
2166 rtlefuse->eeprom_smid == 0x84B6))
2168 RT_CID_819X_EDIMAX_ASUS;
2170 rtlhal->oem_id = RT_CID_DEFAULT;
2172 rtlhal->oem_id = RT_CID_DEFAULT;
2175 case EEPROM_CID_TOSHIBA:
2176 rtlhal->oem_id = RT_CID_TOSHIBA;
2178 case EEPROM_CID_CCX:
2179 rtlhal->oem_id = RT_CID_CCX;
2181 case EEPROM_CID_QMI:
2182 rtlhal->oem_id = RT_CID_819X_QMI;
2184 case EEPROM_CID_WHQL:
2187 rtlhal->oem_id = RT_CID_DEFAULT;
2195 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
2197 struct rtl_priv *rtlpriv = rtl_priv(hw);
2198 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2201 pcipriv->ledctl.led_opendrain = true;
2202 switch (rtlhal->oem_id) {
2203 case RT_CID_819X_HP:
2204 pcipriv->ledctl.led_opendrain = true;
2206 case RT_CID_819X_LENOVO:
2207 case RT_CID_DEFAULT:
2208 case RT_CID_TOSHIBA:
2210 case RT_CID_819X_ACER:
2215 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2216 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2219 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
2221 struct rtl_priv *rtlpriv = rtl_priv(hw);
2222 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2223 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2224 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2227 rtlhal->version = _rtl8723be_read_chip_version(hw);
2228 if (get_rf_type(rtlphy) == RF_1T1R)
2229 rtlpriv->dm.rfpath_rxenable[0] = true;
2231 rtlpriv->dm.rfpath_rxenable[0] =
2232 rtlpriv->dm.rfpath_rxenable[1] = true;
2233 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2235 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2236 if (tmp_u1b & BIT(4)) {
2237 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2238 rtlefuse->epromtype = EEPROM_93C46;
2240 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2241 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2243 if (tmp_u1b & BIT(5)) {
2244 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2245 rtlefuse->autoload_failflag = false;
2246 _rtl8723be_read_adapter_info(hw, false);
2248 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2250 _rtl8723be_hal_customized_behavior(hw);
2253 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2257 switch (rate_index) {
2258 case RATR_INX_WIRELESS_NGB:
2261 case RATR_INX_WIRELESS_N:
2262 case RATR_INX_WIRELESS_NG:
2265 case RATR_INX_WIRELESS_NB:
2268 case RATR_INX_WIRELESS_GB:
2271 case RATR_INX_WIRELESS_G:
2274 case RATR_INX_WIRELESS_B:
2284 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2285 struct ieee80211_sta *sta,
2288 struct rtl_priv *rtlpriv = rtl_priv(hw);
2289 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2290 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2291 struct rtl_sta_info *sta_entry = NULL;
2294 u8 curtxbw_40mhz = (sta->ht_cap.cap &
2295 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2296 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2298 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2300 enum wireless_mode wirelessmode = 0;
2301 bool shortgi = false;
2305 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2306 wirelessmode = sta_entry->wireless_mode;
2307 if (mac->opmode == NL80211_IFTYPE_STATION ||
2308 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2309 curtxbw_40mhz = mac->bw_40;
2310 else if (mac->opmode == NL80211_IFTYPE_AP ||
2311 mac->opmode == NL80211_IFTYPE_ADHOC)
2312 macid = sta->aid + 1;
2314 ratr_bitmap = sta->supp_rates[0];
2316 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2317 ratr_bitmap = 0xfff;
2319 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2320 sta->ht_cap.mcs.rx_mask[0] << 12);
2321 switch (wirelessmode) {
2322 case WIRELESS_MODE_B:
2323 ratr_index = RATR_INX_WIRELESS_B;
2324 if (ratr_bitmap & 0x0000000c)
2325 ratr_bitmap &= 0x0000000d;
2327 ratr_bitmap &= 0x0000000f;
2329 case WIRELESS_MODE_G:
2330 ratr_index = RATR_INX_WIRELESS_GB;
2332 if (rssi_level == 1)
2333 ratr_bitmap &= 0x00000f00;
2334 else if (rssi_level == 2)
2335 ratr_bitmap &= 0x00000ff0;
2337 ratr_bitmap &= 0x00000ff5;
2339 case WIRELESS_MODE_N_24G:
2340 case WIRELESS_MODE_N_5G:
2341 ratr_index = RATR_INX_WIRELESS_NGB;
2342 if (rtlphy->rf_type == RF_1T1R) {
2343 if (curtxbw_40mhz) {
2344 if (rssi_level == 1)
2345 ratr_bitmap &= 0x000f0000;
2346 else if (rssi_level == 2)
2347 ratr_bitmap &= 0x000ff000;
2349 ratr_bitmap &= 0x000ff015;
2351 if (rssi_level == 1)
2352 ratr_bitmap &= 0x000f0000;
2353 else if (rssi_level == 2)
2354 ratr_bitmap &= 0x000ff000;
2356 ratr_bitmap &= 0x000ff005;
2359 if (curtxbw_40mhz) {
2360 if (rssi_level == 1)
2361 ratr_bitmap &= 0x0f8f0000;
2362 else if (rssi_level == 2)
2363 ratr_bitmap &= 0x0f8ff000;
2365 ratr_bitmap &= 0x0f8ff015;
2367 if (rssi_level == 1)
2368 ratr_bitmap &= 0x0f8f0000;
2369 else if (rssi_level == 2)
2370 ratr_bitmap &= 0x0f8ff000;
2372 ratr_bitmap &= 0x0f8ff005;
2375 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2376 (!curtxbw_40mhz && curshortgi_20mhz)) {
2379 else if (macid == 1)
2384 ratr_index = RATR_INX_WIRELESS_NGB;
2386 if (rtlphy->rf_type == RF_1T2R)
2387 ratr_bitmap &= 0x000ff0ff;
2389 ratr_bitmap &= 0x0f0ff0ff;
2393 sta_entry->ratr_index = ratr_index;
2395 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2396 "ratr_bitmap :%x\n", ratr_bitmap);
2397 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2399 rate_mask[0] = macid;
2400 rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2401 (shortgi ? 0x80 : 0x00);
2402 rate_mask[2] = curtxbw_40mhz;
2404 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2405 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2406 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2407 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2409 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2410 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2411 ratr_index, ratr_bitmap,
2412 rate_mask[0], rate_mask[1],
2413 rate_mask[2], rate_mask[3],
2414 rate_mask[4], rate_mask[5],
2416 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
2417 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2420 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2421 struct ieee80211_sta *sta,
2424 struct rtl_priv *rtlpriv = rtl_priv(hw);
2425 if (rtlpriv->dm.useramask)
2426 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level);
2429 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
2431 struct rtl_priv *rtlpriv = rtl_priv(hw);
2432 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2435 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2436 if (!mac->ht_enable)
2437 sifs_timer = 0x0a0a;
2439 sifs_timer = 0x0e0e;
2440 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2443 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2445 struct rtl_priv *rtlpriv = rtl_priv(hw);
2446 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2447 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2448 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2450 bool b_actuallyset = false;
2452 if (rtlpriv->rtlhal.being_init_adapter)
2455 if (ppsc->swrf_processing)
2458 spin_lock(&rtlpriv->locks.rf_ps_lock);
2459 if (ppsc->rfchange_inprogress) {
2460 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2463 ppsc->rfchange_inprogress = true;
2464 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2467 cur_rfstate = ppsc->rfpwr_state;
2469 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2470 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
2472 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2474 if (rtlphy->polarity_ctl)
2475 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2477 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2479 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2480 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2481 "GPIOChangeRF - HW Radio ON, RF ON\n");
2483 e_rfpowerstate_toset = ERFON;
2484 ppsc->hwradiooff = false;
2485 b_actuallyset = true;
2486 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2487 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2488 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2490 e_rfpowerstate_toset = ERFOFF;
2491 ppsc->hwradiooff = true;
2492 b_actuallyset = true;
2495 if (b_actuallyset) {
2496 spin_lock(&rtlpriv->locks.rf_ps_lock);
2497 ppsc->rfchange_inprogress = false;
2498 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2500 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2501 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2503 spin_lock(&rtlpriv->locks.rf_ps_lock);
2504 ppsc->rfchange_inprogress = false;
2505 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2509 return !ppsc->hwradiooff;
2513 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2514 u8 *p_macaddr, bool is_group, u8 enc_algo,
2515 bool is_wepkey, bool clear_all)
2517 struct rtl_priv *rtlpriv = rtl_priv(hw);
2518 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2519 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2520 u8 *macaddr = p_macaddr;
2522 bool is_pairwise = false;
2524 static u8 cam_const_addr[4][6] = {
2525 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2526 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2527 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2528 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2530 static u8 cam_const_broad[] = {
2531 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2537 u8 clear_number = 5;
2539 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2541 for (idx = 0; idx < clear_number; idx++) {
2542 rtl_cam_mark_invalid(hw, cam_offset + idx);
2543 rtl_cam_empty_entry(hw, cam_offset + idx);
2546 memset(rtlpriv->sec.key_buf[idx], 0,
2548 rtlpriv->sec.key_len[idx] = 0;
2554 case WEP40_ENCRYPTION:
2555 enc_algo = CAM_WEP40;
2557 case WEP104_ENCRYPTION:
2558 enc_algo = CAM_WEP104;
2560 case TKIP_ENCRYPTION:
2561 enc_algo = CAM_TKIP;
2563 case AESCCMP_ENCRYPTION:
2567 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2568 "switch case not process\n");
2569 enc_algo = CAM_TKIP;
2573 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2574 macaddr = cam_const_addr[key_index];
2575 entry_id = key_index;
2578 macaddr = cam_const_broad;
2579 entry_id = key_index;
2581 if (mac->opmode == NL80211_IFTYPE_AP) {
2582 entry_id = rtl_cam_get_free_entry(hw,
2584 if (entry_id >= TOTAL_CAM_ENTRY) {
2585 RT_TRACE(rtlpriv, COMP_SEC,
2587 "Can not find free hw security cam entry\n");
2591 entry_id = CAM_PAIRWISE_KEY_POSITION;
2594 key_index = PAIRWISE_KEYIDX;
2599 if (rtlpriv->sec.key_len[key_index] == 0) {
2600 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2601 "delete one entry, entry_id is %d\n",
2603 if (mac->opmode == NL80211_IFTYPE_AP)
2604 rtl_cam_del_entry(hw, p_macaddr);
2605 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2607 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2610 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2611 "set Pairwiase key\n");
2613 rtl_cam_add_one_entry(hw, macaddr, key_index,
2615 CAM_CONFIG_NO_USEDK,
2616 rtlpriv->sec.key_buf[key_index]);
2618 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2621 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2622 rtl_cam_add_one_entry(hw,
2625 CAM_PAIRWISE_KEY_POSITION,
2627 CAM_CONFIG_NO_USEDK,
2628 rtlpriv->sec.key_buf
2632 rtl_cam_add_one_entry(hw, macaddr, key_index,
2634 CAM_CONFIG_NO_USEDK,
2635 rtlpriv->sec.key_buf[entry_id]);
2641 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2642 bool auto_load_fail, u8 *hwinfo)
2644 struct rtl_priv *rtlpriv = rtl_priv(hw);
2645 struct rtl_mod_params *mod_params = rtlpriv->cfg->mod_params;
2649 if (!auto_load_fail) {
2650 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2651 if (tmpu_32 & BIT(18))
2652 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2654 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2655 value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2656 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2657 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2659 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2660 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2661 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2664 /* override ant_num / ant_path */
2665 if (mod_params->ant_sel)
2666 rtlpriv->btcoexist.btc_info.ant_num =
2667 (mod_params->ant_sel == 1 ? ANT_X2 : ANT_X1);
2670 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
2672 struct rtl_priv *rtlpriv = rtl_priv(hw);
2674 /* 0:Low, 1:High, 2:From Efuse. */
2675 rtlpriv->btcoexist.reg_bt_iso = 2;
2676 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2677 rtlpriv->btcoexist.reg_bt_sco = 3;
2678 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2679 rtlpriv->btcoexist.reg_bt_sco = 0;
2682 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2684 struct rtl_priv *rtlpriv = rtl_priv(hw);
2686 if (rtlpriv->cfg->ops->get_btc_status())
2687 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2691 void rtl8723be_suspend(struct ieee80211_hw *hw)
2695 void rtl8723be_resume(struct ieee80211_hw *hw)