drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 299 {
 300         u16 fw_crc;
 301         u16 crc;
 302
 303         /*
 304          * The last 2 bytes in the firmware array are the crc checksum itself,
 305          * this means that we should never pass those 2 bytes to the crc
 306          * algorithm.
 307          */
 308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 309
 310         /*
 311          * Use the crc ccitt algorithm.
 312          * This will return the same value as the legacy driver which
 313          * used bit ordering reversion on the both the firmware bytes
 314          * before input input as well as on the final output.
 315          * Obviously using crc ccitt directly is much more efficient.
 316          */
 317         crc = crc_ccitt(~0, data, len - 2);
 318
 319         /*
 320          * There is a small difference between the crc-itu-t + bitrev and
 321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 322          * will be swapped, use swab16 to convert the crc to the correct
 323          * value.
 324          */
 325         crc = swab16(crc);
 326
 327         return fw_crc == crc;
 328 }
 329
 330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 331                           const u8 *data, const size_t len)
 332 {
 333         size_t offset = 0;
 334         size_t fw_len;
 335         bool multiple;
 336
 337         /*
 338          * PCI(e) & SOC devices require firmware with a length
 339          * of 8kb. USB devices require firmware files with a length
 340          * of 4kb. Certain USB chipsets however require different firmware,
 341          * which Ralink only provides attached to the original firmware
 342          * file. Thus for USB devices, firmware files have a length
 343          * which is a multiple of 4kb.
 344          */
 345         if (rt2x00_is_usb(rt2x00dev)) {
 346                 fw_len = 4096;
 347                 multiple = true;
 348         } else {
 349                 fw_len = 8192;
 350                 multiple = true;
 351         }
 352
 353         /*
 354          * Validate the firmware length
 355          */
 356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 357                 return FW_BAD_LENGTH;
 358
 359         /*
 360          * Check if the chipset requires one of the upper parts
 361          * of the firmware.
 362          */
 363         if (rt2x00_is_usb(rt2x00dev) &&
 364             !rt2x00_rt(rt2x00dev, RT2860) &&
 365             !rt2x00_rt(rt2x00dev, RT2872) &&
 366             !rt2x00_rt(rt2x00dev, RT3070) &&
 367             ((len / fw_len) == 1))
 368                 return FW_BAD_VERSION;
 369
 370         /*
 371          * 8kb firmware files must be checked as if it were
 372          * 2 separate firmware files.
 373          */
 374         while (offset < len) {
 375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 376                         return FW_BAD_CRC;
 377
 378                 offset += fw_len;
 379         }
 380
 381         return FW_OK;
 382 }
 383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 384
 385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 386                          const u8 *data, const size_t len)
 387 {
 388         unsigned int i;
 389         u32 reg;
 390
 391         /*
 392          * If driver doesn't wake up firmware here,
 393          * rt2800_load_firmware will hang forever when interface is up again.
 394          */
 395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 396
 397         /*
 398          * Wait for stable hardware.
 399          */
 400         if (rt2800_wait_csr_ready(rt2x00dev))
 401                 return -EBUSY;
 402
 403         if (rt2x00_is_pci(rt2x00dev)) {
 404                 if (rt2x00_rt(rt2x00dev, RT5390)) {
 405                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 406                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 407                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 408                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 409                 }
 410                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 411         }
 412
 413         /*
 414          * Disable DMA, will be reenabled later when enabling
 415          * the radio.
 416          */
 417         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 418         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 423         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 424
 425         /*
 426          * Write firmware to the device.
 427          */
 428         rt2800_drv_write_firmware(rt2x00dev, data, len);
 429
 430         /*
 431          * Wait for device to stabilize.
 432          */
 433         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 434                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 435                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 436                         break;
 437                 msleep(1);
 438         }
 439
 440         if (i == REGISTER_BUSY_COUNT) {
 441                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 442                 return -EBUSY;
 443         }
 444
 445         /*
 446          * Initialize firmware.
 447          */
 448         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 449         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 450         msleep(1);
 451
 452         return 0;
 453 }
 454 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 455
 456 void rt2800_write_tx_data(struct queue_entry *entry,
 457                           struct txentry_desc *txdesc)
 458 {
 459         __le32 *txwi = rt2800_drv_get_txwi(entry);
 460         u32 word;
 461
 462         /*
 463          * Initialize TX Info descriptor
 464          */
 465         rt2x00_desc_read(txwi, 0, &word);
 466         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 467                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 468         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 469                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 470         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 471         rt2x00_set_field32(&word, TXWI_W0_TS,
 472                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 473         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 474                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 475         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 476                            txdesc->u.ht.mpdu_density);
 477         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 478         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 479         rt2x00_set_field32(&word, TXWI_W0_BW,
 480                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 481         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 482                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 483         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 484         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 485         rt2x00_desc_write(txwi, 0, word);
 486
 487         rt2x00_desc_read(txwi, 1, &word);
 488         rt2x00_set_field32(&word, TXWI_W1_ACK,
 489                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 490         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 491                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 492         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 493         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 494                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 495                            txdesc->key_idx : 0xff);
 496         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 497                            txdesc->length);
 498         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 500         rt2x00_desc_write(txwi, 1, word);
 501
 502         /*
 503          * Always write 0 to IV/EIV fields, hardware will insert the IV
 504          * from the IVEIV register when TXD_W3_WIV is set to 0.
 505          * When TXD_W3_WIV is set to 1 it will use the IV data
 506          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 507          * crypto entry in the registers should be used to encrypt the frame.
 508          */
 509         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 510         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 511 }
 512 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 513
 514 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 515 {
 516         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 517         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 518         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 519         u16 eeprom;
 520         u8 offset0;
 521         u8 offset1;
 522         u8 offset2;
 523
 524         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 525                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 526                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 527                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 528                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 529                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 530         } else {
 531                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 532                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 533                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 534                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 535                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 536         }
 537
 538         /*
 539          * Convert the value from the descriptor into the RSSI value
 540          * If the value in the descriptor is 0, it is considered invalid
 541          * and the default (extremely low) rssi value is assumed
 542          */
 543         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 544         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 545         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 546
 547         /*
 548          * mac80211 only accepts a single RSSI value. Calculating the
 549          * average doesn't deliver a fair answer either since -60:-60 would
 550          * be considered equally good as -50:-70 while the second is the one
 551          * which gives less energy...
 552          */
 553         rssi0 = max(rssi0, rssi1);
 554         return max(rssi0, rssi2);
 555 }
 556
 557 void rt2800_process_rxwi(struct queue_entry *entry,
 558                          struct rxdone_entry_desc *rxdesc)
 559 {
 560         __le32 *rxwi = (__le32 *) entry->skb->data;
 561         u32 word;
 562
 563         rt2x00_desc_read(rxwi, 0, &word);
 564
 565         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 566         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 567
 568         rt2x00_desc_read(rxwi, 1, &word);
 569
 570         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 571                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 572
 573         if (rt2x00_get_field32(word, RXWI_W1_BW))
 574                 rxdesc->flags |= RX_FLAG_40MHZ;
 575
 576         /*
 577          * Detect RX rate, always use MCS as signal type.
 578          */
 579         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 580         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 581         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 582
 583         /*
 584          * Mask of 0x8 bit to remove the short preamble flag.
 585          */
 586         if (rxdesc->rate_mode == RATE_MODE_CCK)
 587                 rxdesc->signal &= ~0x8;
 588
 589         rt2x00_desc_read(rxwi, 2, &word);
 590
 591         /*
 592          * Convert descriptor AGC value to RSSI value.
 593          */
 594         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 595
 596         /*
 597          * Remove RXWI descriptor from start of buffer.
 598          */
 599         skb_pull(entry->skb, RXWI_DESC_SIZE);
 600 }
 601 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 602
 603 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
 604 {
 605         __le32 *txwi;
 606         u32 word;
 607         int wcid, ack, pid;
 608         int tx_wcid, tx_ack, tx_pid;
 609
 610         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 611         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 612         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 613
 614         /*
 615          * This frames has returned with an IO error,
 616          * so the status report is not intended for this
 617          * frame.
 618          */
 619         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
 620                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
 621                 return false;
 622         }
 623
 624         /*
 625          * Validate if this TX status report is intended for
 626          * this entry by comparing the WCID/ACK/PID fields.
 627          */
 628         txwi = rt2800_drv_get_txwi(entry);
 629
 630         rt2x00_desc_read(txwi, 1, &word);
 631         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 632         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 633         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 634
 635         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
 636                 WARNING(entry->queue->rt2x00dev,
 637                         "TX status report missed for queue %d entry %d\n",
 638                 entry->queue->qid, entry->entry_idx);
 639                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
 640                 return false;
 641         }
 642
 643         return true;
 644 }
 645
 646 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
 647 {
 648         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 649         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 650         struct txdone_entry_desc txdesc;
 651         u32 word;
 652         u16 mcs, real_mcs;
 653         int aggr, ampdu;
 654         __le32 *txwi;
 655
 656         /*
 657          * Obtain the status about this packet.
 658          */
 659         txdesc.flags = 0;
 660         txwi = rt2800_drv_get_txwi(entry);
 661         rt2x00_desc_read(txwi, 0, &word);
 662
 663         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 664         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 665
 666         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 667         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 668
 669         /*
 670          * If a frame was meant to be sent as a single non-aggregated MPDU
 671          * but ended up in an aggregate the used tx rate doesn't correlate
 672          * with the one specified in the TXWI as the whole aggregate is sent
 673          * with the same rate.
 674          *
 675          * For example: two frames are sent to rt2x00, the first one sets
 676          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 677          * and requests MCS15. If the hw aggregates both frames into one
 678          * AMDPU the tx status for both frames will contain MCS7 although
 679          * the frame was sent successfully.
 680          *
 681          * Hence, replace the requested rate with the real tx rate to not
 682          * confuse the rate control algortihm by providing clearly wrong
 683          * data.
 684          */
 685         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 686                 skbdesc->tx_rate_idx = real_mcs;
 687                 mcs = real_mcs;
 688         }
 689
 690         if (aggr == 1 || ampdu == 1)
 691                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 692
 693         /*
 694          * Ralink has a retry mechanism using a global fallback
 695          * table. We setup this fallback table to try the immediate
 696          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 697          * always contains the MCS used for the last transmission, be
 698          * it successful or not.
 699          */
 700         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 701                 /*
 702                  * Transmission succeeded. The number of retries is
 703                  * mcs - real_mcs
 704                  */
 705                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 706                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 707         } else {
 708                 /*
 709                  * Transmission failed. The number of retries is
 710                  * always 7 in this case (for a total number of 8
 711                  * frames sent).
 712                  */
 713                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 714                 txdesc.retry = rt2x00dev->long_retry;
 715         }
 716
 717         /*
 718          * the frame was retried at least once
 719          * -> hw used fallback rates
 720          */
 721         if (txdesc.retry)
 722                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 723
 724         rt2x00lib_txdone(entry, &txdesc);
 725 }
 726 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 727
 728 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
 729 {
 730         struct data_queue *queue;
 731         struct queue_entry *entry;
 732         u32 reg;
 733         u8 qid;
 734
 735         while (kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
 736
 737                 /* TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus
 738                  * qid is guaranteed to be one of the TX QIDs
 739                  */
 740                 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
 741                 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
 742                 if (unlikely(!queue)) {
 743                         WARNING(rt2x00dev, "Got TX status for an unavailable "
 744                                            "queue %u, dropping\n", qid);
 745                         continue;
 746                 }
 747
 748                 /*
 749                  * Inside each queue, we process each entry in a chronological
 750                  * order. We first check that the queue is not empty.
 751                  */
 752                 entry = NULL;
 753                 while (!rt2x00queue_empty(queue)) {
 754                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 755                         if (rt2800_txdone_entry_check(entry, reg))
 756                                 break;
 757                 }
 758
 759                 if (!entry || rt2x00queue_empty(queue))
 760                         break;
 761
 762                 rt2800_txdone_entry(entry, reg);
 763         }
 764 }
 765 EXPORT_SYMBOL_GPL(rt2800_txdone);
 766
 767 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 768 {
 769         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 770         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 771         unsigned int beacon_base;
 772         unsigned int padding_len;
 773         u32 orig_reg, reg;
 774
 775         /*
 776          * Disable beaconing while we are reloading the beacon data,
 777          * otherwise we might be sending out invalid data.
 778          */
 779         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 780         orig_reg = reg;
 781         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 782         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 783
 784         /*
 785          * Add space for the TXWI in front of the skb.
 786          */
 787         skb_push(entry->skb, TXWI_DESC_SIZE);
 788         memset(entry->skb, 0, TXWI_DESC_SIZE);
 789
 790         /*
 791          * Register descriptor details in skb frame descriptor.
 792          */
 793         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 794         skbdesc->desc = entry->skb->data;
 795         skbdesc->desc_len = TXWI_DESC_SIZE;
 796
 797         /*
 798          * Add the TXWI for the beacon to the skb.
 799          */
 800         rt2800_write_tx_data(entry, txdesc);
 801
 802         /*
 803          * Dump beacon to userspace through debugfs.
 804          */
 805         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 806
 807         /*
 808          * Write entire beacon with TXWI and padding to register.
 809          */
 810         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 811         if (padding_len && skb_pad(entry->skb, padding_len)) {
 812                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 813                 /* skb freed by skb_pad() on failure */
 814                 entry->skb = NULL;
 815                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 816                 return;
 817         }
 818
 819         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 820         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 821                                    entry->skb->len + padding_len);
 822
 823         /*
 824          * Enable beaconing again.
 825          */
 826         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 827         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 828
 829         /*
 830          * Clean up beacon skb.
 831          */
 832         dev_kfree_skb_any(entry->skb);
 833         entry->skb = NULL;
 834 }
 835 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 836
 837 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 838                                                 unsigned int beacon_base)
 839 {
 840         int i;
 841
 842         /*
 843          * For the Beacon base registers we only need to clear
 844          * the whole TXWI which (when set to 0) will invalidate
 845          * the entire beacon.
 846          */
 847         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 848                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 849 }
 850
 851 void rt2800_clear_beacon(struct queue_entry *entry)
 852 {
 853         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 854         u32 reg;
 855
 856         /*
 857          * Disable beaconing while we are reloading the beacon data,
 858          * otherwise we might be sending out invalid data.
 859          */
 860         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 861         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 862         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 863
 864         /*
 865          * Clear beacon.
 866          */
 867         rt2800_clear_beacon_register(rt2x00dev,
 868                                      HW_BEACON_OFFSET(entry->entry_idx));
 869
 870         /*
 871          * Enabled beaconing again.
 872          */
 873         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 874         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 875 }
 876 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 877
 878 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 879 const struct rt2x00debug rt2800_rt2x00debug = {
 880         .owner  = THIS_MODULE,
 881         .csr    = {
 882                 .read           = rt2800_register_read,
 883                 .write          = rt2800_register_write,
 884                 .flags          = RT2X00DEBUGFS_OFFSET,
 885                 .word_base      = CSR_REG_BASE,
 886                 .word_size      = sizeof(u32),
 887                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 888         },
 889         .eeprom = {
 890                 .read           = rt2x00_eeprom_read,
 891                 .write          = rt2x00_eeprom_write,
 892                 .word_base      = EEPROM_BASE,
 893                 .word_size      = sizeof(u16),
 894                 .word_count     = EEPROM_SIZE / sizeof(u16),
 895         },
 896         .bbp    = {
 897                 .read           = rt2800_bbp_read,
 898                 .write          = rt2800_bbp_write,
 899                 .word_base      = BBP_BASE,
 900                 .word_size      = sizeof(u8),
 901                 .word_count     = BBP_SIZE / sizeof(u8),
 902         },
 903         .rf     = {
 904                 .read           = rt2x00_rf_read,
 905                 .write          = rt2800_rf_write,
 906                 .word_base      = RF_BASE,
 907                 .word_size      = sizeof(u32),
 908                 .word_count     = RF_SIZE / sizeof(u32),
 909         },
 910 };
 911 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 912 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 913
 914 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 915 {
 916         u32 reg;
 917
 918         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 919         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 920 }
 921 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 922
 923 #ifdef CONFIG_RT2X00_LIB_LEDS
 924 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 925                                   enum led_brightness brightness)
 926 {
 927         struct rt2x00_led *led =
 928             container_of(led_cdev, struct rt2x00_led, led_dev);
 929         unsigned int enabled = brightness != LED_OFF;
 930         unsigned int bg_mode =
 931             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 932         unsigned int polarity =
 933                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 934                                    EEPROM_FREQ_LED_POLARITY);
 935         unsigned int ledmode =
 936                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 937                                    EEPROM_FREQ_LED_MODE);
 938         u32 reg;
 939
 940         /* Check for SoC (SOC devices don't support MCU requests) */
 941         if (rt2x00_is_soc(led->rt2x00dev)) {
 942                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 943
 944                 /* Set LED Polarity */
 945                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 946
 947                 /* Set LED Mode */
 948                 if (led->type == LED_TYPE_RADIO) {
 949                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 950                                            enabled ? 3 : 0);
 951                 } else if (led->type == LED_TYPE_ASSOC) {
 952                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 953                                            enabled ? 3 : 0);
 954                 } else if (led->type == LED_TYPE_QUALITY) {
 955                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 956                                            enabled ? 3 : 0);
 957                 }
 958
 959                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 960
 961         } else {
 962                 if (led->type == LED_TYPE_RADIO) {
 963                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 964                                               enabled ? 0x20 : 0);
 965                 } else if (led->type == LED_TYPE_ASSOC) {
 966                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 967                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 968                 } else if (led->type == LED_TYPE_QUALITY) {
 969                         /*
 970                          * The brightness is divided into 6 levels (0 - 5),
 971                          * The specs tell us the following levels:
 972                          *      0, 1 ,3, 7, 15, 31
 973                          * to determine the level in a simple way we can simply
 974                          * work with bitshifting:
 975                          *      (1 << level) - 1
 976                          */
 977                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 978                                               (1 << brightness / (LED_FULL / 6)) - 1,
 979                                               polarity);
 980                 }
 981         }
 982 }
 983
 984 static int rt2800_blink_set(struct led_classdev *led_cdev,
 985                             unsigned long *delay_on, unsigned long *delay_off)
 986 {
 987         struct rt2x00_led *led =
 988             container_of(led_cdev, struct rt2x00_led, led_dev);
 989         u32 reg;
 990
 991         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 992         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 993         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 994         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 995
 996         return 0;
 997 }
 998
 999 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1000                      struct rt2x00_led *led, enum led_type type)
1001 {
1002         led->rt2x00dev = rt2x00dev;
1003         led->type = type;
1004         led->led_dev.brightness_set = rt2800_brightness_set;
1005         led->led_dev.blink_set = rt2800_blink_set;
1006         led->flags = LED_INITIALIZED;
1007 }
1008 #endif /* CONFIG_RT2X00_LIB_LEDS */
1009
1010 /*
1011  * Configuration handlers.
1012  */
1013 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
1014                                     struct rt2x00lib_crypto *crypto,
1015                                     struct ieee80211_key_conf *key)
1016 {
1017         struct mac_wcid_entry wcid_entry;
1018         struct mac_iveiv_entry iveiv_entry;
1019         u32 offset;
1020         u32 reg;
1021
1022         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1023
1024         if (crypto->cmd == SET_KEY) {
1025                 rt2800_register_read(rt2x00dev, offset, &reg);
1026                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1027                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1028                 /*
1029                  * Both the cipher as the BSS Idx numbers are split in a main
1030                  * value of 3 bits, and a extended field for adding one additional
1031                  * bit to the value.
1032                  */
1033                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1034                                    (crypto->cipher & 0x7));
1035                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1036                                    (crypto->cipher & 0x8) >> 3);
1037                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1038                                    (crypto->bssidx & 0x7));
1039                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1040                                    (crypto->bssidx & 0x8) >> 3);
1041                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1042                 rt2800_register_write(rt2x00dev, offset, reg);
1043         } else {
1044                 rt2800_register_write(rt2x00dev, offset, 0);
1045         }
1046
1047         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1048
1049         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1050         if ((crypto->cipher == CIPHER_TKIP) ||
1051             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1052             (crypto->cipher == CIPHER_AES))
1053                 iveiv_entry.iv[3] |= 0x20;
1054         iveiv_entry.iv[3] |= key->keyidx << 6;
1055         rt2800_register_multiwrite(rt2x00dev, offset,
1056                                       &iveiv_entry, sizeof(iveiv_entry));
1057
1058         offset = MAC_WCID_ENTRY(key->hw_key_idx);
1059
1060         memset(&wcid_entry, 0, sizeof(wcid_entry));
1061         if (crypto->cmd == SET_KEY)
1062                 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
1063         rt2800_register_multiwrite(rt2x00dev, offset,
1064                                       &wcid_entry, sizeof(wcid_entry));
1065 }
1066
1067 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1068                              struct rt2x00lib_crypto *crypto,
1069                              struct ieee80211_key_conf *key)
1070 {
1071         struct hw_key_entry key_entry;
1072         struct rt2x00_field32 field;
1073         u32 offset;
1074         u32 reg;
1075
1076         if (crypto->cmd == SET_KEY) {
1077                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1078
1079                 memcpy(key_entry.key, crypto->key,
1080                        sizeof(key_entry.key));
1081                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1082                        sizeof(key_entry.tx_mic));
1083                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1084                        sizeof(key_entry.rx_mic));
1085
1086                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1087                 rt2800_register_multiwrite(rt2x00dev, offset,
1088                                               &key_entry, sizeof(key_entry));
1089         }
1090
1091         /*
1092          * The cipher types are stored over multiple registers
1093          * starting with SHARED_KEY_MODE_BASE each word will have
1094          * 32 bits and contains the cipher types for 2 bssidx each.
1095          * Using the correct defines correctly will cause overhead,
1096          * so just calculate the correct offset.
1097          */
1098         field.bit_offset = 4 * (key->hw_key_idx % 8);
1099         field.bit_mask = 0x7 << field.bit_offset;
1100
1101         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1102
1103         rt2800_register_read(rt2x00dev, offset, &reg);
1104         rt2x00_set_field32(&reg, field,
1105                            (crypto->cmd == SET_KEY) * crypto->cipher);
1106         rt2800_register_write(rt2x00dev, offset, reg);
1107
1108         /*
1109          * Update WCID information
1110          */
1111         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1112
1113         return 0;
1114 }
1115 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1116
1117 static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1118 {
1119         int idx;
1120         u32 offset, reg;
1121
1122         /*
1123          * Search for the first free pairwise key entry and return the
1124          * corresponding index.
1125          *
1126          * Make sure the WCID starts _after_ the last possible shared key
1127          * entry (>32).
1128          *
1129          * Since parts of the pairwise key table might be shared with
1130          * the beacon frame buffers 6 & 7 we should only write into the
1131          * first 222 entries.
1132          */
1133         for (idx = 33; idx <= 222; idx++) {
1134                 offset = MAC_WCID_ATTR_ENTRY(idx);
1135                 rt2800_register_read(rt2x00dev, offset, &reg);
1136                 if (!reg)
1137                         return idx;
1138         }
1139         return -1;
1140 }
1141
1142 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1143                                struct rt2x00lib_crypto *crypto,
1144                                struct ieee80211_key_conf *key)
1145 {
1146         struct hw_key_entry key_entry;
1147         u32 offset;
1148         int idx;
1149
1150         if (crypto->cmd == SET_KEY) {
1151                 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
1152                 if (idx < 0)
1153                         return -ENOSPC;
1154                 key->hw_key_idx = idx;
1155
1156                 memcpy(key_entry.key, crypto->key,
1157                        sizeof(key_entry.key));
1158                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1159                        sizeof(key_entry.tx_mic));
1160                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1161                        sizeof(key_entry.rx_mic));
1162
1163                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1164                 rt2800_register_multiwrite(rt2x00dev, offset,
1165                                               &key_entry, sizeof(key_entry));
1166         }
1167
1168         /*
1169          * Update WCID information
1170          */
1171         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1172
1173         return 0;
1174 }
1175 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1176
1177 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1178                           const unsigned int filter_flags)
1179 {
1180         u32 reg;
1181
1182         /*
1183          * Start configuration steps.
1184          * Note that the version error will always be dropped
1185          * and broadcast frames will always be accepted since
1186          * there is no filter for it at this time.
1187          */
1188         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1189         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1190                            !(filter_flags & FIF_FCSFAIL));
1191         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1192                            !(filter_flags & FIF_PLCPFAIL));
1193         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1194                            !(filter_flags & FIF_PROMISC_IN_BSS));
1195         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1196         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1197         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1198                            !(filter_flags & FIF_ALLMULTI));
1199         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1200         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1201         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1202                            !(filter_flags & FIF_CONTROL));
1203         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1204                            !(filter_flags & FIF_CONTROL));
1205         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1206                            !(filter_flags & FIF_CONTROL));
1207         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1208                            !(filter_flags & FIF_CONTROL));
1209         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1210                            !(filter_flags & FIF_CONTROL));
1211         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1212                            !(filter_flags & FIF_PSPOLL));
1213         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1214         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1215         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1216                            !(filter_flags & FIF_CONTROL));
1217         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1218 }
1219 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1220
1221 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1222                         struct rt2x00intf_conf *conf, const unsigned int flags)
1223 {
1224         u32 reg;
1225         bool update_bssid = false;
1226
1227         if (flags & CONFIG_UPDATE_TYPE) {
1228                 /*
1229                  * Enable synchronisation.
1230                  */
1231                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1232                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1233                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1234
1235                 if (conf->sync == TSF_SYNC_AP_NONE) {
1236                         /*
1237                          * Tune beacon queue transmit parameters for AP mode
1238                          */
1239                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1240                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1241                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1242                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1243                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1244                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1245                 } else {
1246                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1247                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1248                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1249                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1250                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1251                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1252                 }
1253         }
1254
1255         if (flags & CONFIG_UPDATE_MAC) {
1256                 if (flags & CONFIG_UPDATE_TYPE &&
1257                     conf->sync == TSF_SYNC_AP_NONE) {
1258                         /*
1259                          * The BSSID register has to be set to our own mac
1260                          * address in AP mode.
1261                          */
1262                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1263                         update_bssid = true;
1264                 }
1265
1266                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1267                         reg = le32_to_cpu(conf->mac[1]);
1268                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1269                         conf->mac[1] = cpu_to_le32(reg);
1270                 }
1271
1272                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1273                                               conf->mac, sizeof(conf->mac));
1274         }
1275
1276         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1277                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1278                         reg = le32_to_cpu(conf->bssid[1]);
1279                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1280                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1281                         conf->bssid[1] = cpu_to_le32(reg);
1282                 }
1283
1284                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1285                                               conf->bssid, sizeof(conf->bssid));
1286         }
1287 }
1288 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1289
1290 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1291                                     struct rt2x00lib_erp *erp)
1292 {
1293         bool any_sta_nongf = !!(erp->ht_opmode &
1294                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1295         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1296         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1297         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1298         u32 reg;
1299
1300         /* default protection rate for HT20: OFDM 24M */
1301         mm20_rate = gf20_rate = 0x4004;
1302
1303         /* default protection rate for HT40: duplicate OFDM 24M */
1304         mm40_rate = gf40_rate = 0x4084;
1305
1306         switch (protection) {
1307         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1308                 /*
1309                  * All STAs in this BSS are HT20/40 but there might be
1310                  * STAs not supporting greenfield mode.
1311                  * => Disable protection for HT transmissions.
1312                  */
1313                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1314
1315                 break;
1316         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1317                 /*
1318                  * All STAs in this BSS are HT20 or HT20/40 but there
1319                  * might be STAs not supporting greenfield mode.
1320                  * => Protect all HT40 transmissions.
1321                  */
1322                 mm20_mode = gf20_mode = 0;
1323                 mm40_mode = gf40_mode = 2;
1324
1325                 break;
1326         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1327                 /*
1328                  * Nonmember protection:
1329                  * According to 802.11n we _should_ protect all
1330                  * HT transmissions (but we don't have to).
1331                  *
1332                  * But if cts_protection is enabled we _shall_ protect
1333                  * all HT transmissions using a CCK rate.
1334                  *
1335                  * And if any station is non GF we _shall_ protect
1336                  * GF transmissions.
1337                  *
1338                  * We decide to protect everything
1339                  * -> fall through to mixed mode.
1340                  */
1341         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1342                 /*
1343                  * Legacy STAs are present
1344                  * => Protect all HT transmissions.
1345                  */
1346                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1347
1348                 /*
1349                  * If erp protection is needed we have to protect HT
1350                  * transmissions with CCK 11M long preamble.
1351                  */
1352                 if (erp->cts_protection) {
1353                         /* don't duplicate RTS/CTS in CCK mode */
1354                         mm20_rate = mm40_rate = 0x0003;
1355                         gf20_rate = gf40_rate = 0x0003;
1356                 }
1357                 break;
1358         };
1359
1360         /* check for STAs not supporting greenfield mode */
1361         if (any_sta_nongf)
1362                 gf20_mode = gf40_mode = 2;
1363
1364         /* Update HT protection config */
1365         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1366         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1367         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1368         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1369
1370         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1371         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1372         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1373         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1374
1375         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1376         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1377         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1378         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1379
1380         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1381         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1382         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1383         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1384 }
1385
1386 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1387                        u32 changed)
1388 {
1389         u32 reg;
1390
1391         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1392                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1393                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1394                                    !!erp->short_preamble);
1395                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1396                                    !!erp->short_preamble);
1397                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1398         }
1399
1400         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1401                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1402                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1403                                    erp->cts_protection ? 2 : 0);
1404                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1405         }
1406
1407         if (changed & BSS_CHANGED_BASIC_RATES) {
1408                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1409                                          erp->basic_rates);
1410                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1411         }
1412
1413         if (changed & BSS_CHANGED_ERP_SLOT) {
1414                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1415                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1416                                    erp->slot_time);
1417                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1418
1419                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1420                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1421                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1422         }
1423
1424         if (changed & BSS_CHANGED_BEACON_INT) {
1425                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1426                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1427                                    erp->beacon_int * 16);
1428                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1429         }
1430
1431         if (changed & BSS_CHANGED_HT)
1432                 rt2800_config_ht_opmode(rt2x00dev, erp);
1433 }
1434 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1435
1436 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1437                                      enum antenna ant)
1438 {
1439         u32 reg;
1440         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1441         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1442
1443         if (rt2x00_is_pci(rt2x00dev)) {
1444                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1445                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1446                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1447         } else if (rt2x00_is_usb(rt2x00dev))
1448                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1449                                    eesk_pin, 0);
1450
1451         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1452         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1453         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1454         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1455 }
1456
1457 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1458 {
1459         u8 r1;
1460         u8 r3;
1461         u16 eeprom;
1462
1463         rt2800_bbp_read(rt2x00dev, 1, &r1);
1464         rt2800_bbp_read(rt2x00dev, 3, &r3);
1465
1466         /*
1467          * Configure the TX antenna.
1468          */
1469         switch (ant->tx_chain_num) {
1470         case 1:
1471                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1472                 break;
1473         case 2:
1474                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1475                 break;
1476         case 3:
1477                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1478                 break;
1479         }
1480
1481         /*
1482          * Configure the RX antenna.
1483          */
1484         switch (ant->rx_chain_num) {
1485         case 1:
1486                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1487                     rt2x00_rt(rt2x00dev, RT3090) ||
1488                     rt2x00_rt(rt2x00dev, RT3390)) {
1489                         rt2x00_eeprom_read(rt2x00dev,
1490                                            EEPROM_NIC_CONF1, &eeprom);
1491                         if (rt2x00_get_field16(eeprom,
1492                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1493                                 rt2800_set_ant_diversity(rt2x00dev,
1494                                                 rt2x00dev->default_ant.rx);
1495                 }
1496                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1497                 break;
1498         case 2:
1499                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1500                 break;
1501         case 3:
1502                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1503                 break;
1504         }
1505
1506         rt2800_bbp_write(rt2x00dev, 3, r3);
1507         rt2800_bbp_write(rt2x00dev, 1, r1);
1508 }
1509 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1510
1511 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1512                                    struct rt2x00lib_conf *libconf)
1513 {
1514         u16 eeprom;
1515         short lna_gain;
1516
1517         if (libconf->rf.channel <= 14) {
1518                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1519                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1520         } else if (libconf->rf.channel <= 64) {
1521                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1522                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1523         } else if (libconf->rf.channel <= 128) {
1524                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1525                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1526         } else {
1527                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1528                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1529         }
1530
1531         rt2x00dev->lna_gain = lna_gain;
1532 }
1533
1534 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1535                                          struct ieee80211_conf *conf,
1536                                          struct rf_channel *rf,
1537                                          struct channel_info *info)
1538 {
1539         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1540
1541         if (rt2x00dev->default_ant.tx_chain_num == 1)
1542                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1543
1544         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1545                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1546                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1547         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1548                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1549
1550         if (rf->channel > 14) {
1551                 /*
1552                  * When TX power is below 0, we should increase it by 7 to
1553                  * make it a positive value (Minimum value is -7).
1554                  * However this means that values between 0 and 7 have
1555                  * double meaning, and we should set a 7DBm boost flag.
1556                  */
1557                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1558                                    (info->default_power1 >= 0));
1559
1560                 if (info->default_power1 < 0)
1561                         info->default_power1 += 7;
1562
1563                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1564
1565                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1566                                    (info->default_power2 >= 0));
1567
1568                 if (info->default_power2 < 0)
1569                         info->default_power2 += 7;
1570
1571                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1572         } else {
1573                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1574                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1575         }
1576
1577         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1578
1579         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1580         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1581         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1582         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1583
1584         udelay(200);
1585
1586         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1587         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1588         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1589         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1590
1591         udelay(200);
1592
1593         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1594         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1595         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1596         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1597 }
1598
1599 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1600                                          struct ieee80211_conf *conf,
1601                                          struct rf_channel *rf,
1602                                          struct channel_info *info)
1603 {
1604         u8 rfcsr;
1605
1606         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1607         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1608
1609         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1610         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1611         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1612
1613         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1614         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1615         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1616
1617         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1618         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1619         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1620
1621         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1622         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1623         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1624
1625         rt2800_rfcsr_write(rt2x00dev, 24,
1626                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1627
1628         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1629         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1630         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1631 }
1632
1633
1634 #define RT5390_POWER_BOUND     0x27
1635 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1636
1637 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1638                                          struct ieee80211_conf *conf,
1639                                          struct rf_channel *rf,
1640                                          struct channel_info *info)
1641 {
1642         u8 rfcsr;
1643         u16 eeprom;
1644
1645         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1646         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1647         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1648         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1649         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1650
1651         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1652         if (info->default_power1 > RT5390_POWER_BOUND)
1653                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1654         else
1655                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1656         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1657
1658         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1659         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1660         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1661         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1662         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1663         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1664
1665         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1666         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1667                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1668                                   RT5390_FREQ_OFFSET_BOUND);
1669         else
1670                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1671         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1672
1673         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1674         if (rf->channel <= 14) {
1675                 int idx = rf->channel-1;
1676
1677                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1678                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1679                                 /* r55/r59 value array of channel 1~14 */
1680                                 static const char r55_bt_rev[] = {0x83, 0x83,
1681                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1682                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1683                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1684                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1685                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1686
1687                                 rt2800_rfcsr_write(rt2x00dev, 55,
1688                                                    r55_bt_rev[idx]);
1689                                 rt2800_rfcsr_write(rt2x00dev, 59,
1690                                                    r59_bt_rev[idx]);
1691                         } else {
1692                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1693                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1694                                         0x88, 0x88, 0x86, 0x85, 0x84};
1695
1696                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1697                         }
1698                 } else {
1699                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1700                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1701                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1702                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1703                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1704                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1705                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1706
1707                                 rt2800_rfcsr_write(rt2x00dev, 55,
1708                                                    r55_nonbt_rev[idx]);
1709                                 rt2800_rfcsr_write(rt2x00dev, 59,
1710                                                    r59_nonbt_rev[idx]);
1711                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1712                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1713                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1714                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1715
1716                                 rt2800_rfcsr_write(rt2x00dev, 59,
1717                                                    r59_non_bt[idx]);
1718                         }
1719                 }
1720         }
1721
1722         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1723         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1724         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1725         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1726
1727         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1728         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1729         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1730 }
1731
1732 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1733                                   struct ieee80211_conf *conf,
1734                                   struct rf_channel *rf,
1735                                   struct channel_info *info)
1736 {
1737         u32 reg;
1738         unsigned int tx_pin;
1739         u8 bbp;
1740
1741         if (rf->channel <= 14) {
1742                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1743                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1744         } else {
1745                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1746                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1747         }
1748
1749         if (rt2x00_rf(rt2x00dev, RF2020) ||
1750             rt2x00_rf(rt2x00dev, RF3020) ||
1751             rt2x00_rf(rt2x00dev, RF3021) ||
1752             rt2x00_rf(rt2x00dev, RF3022) ||
1753             rt2x00_rf(rt2x00dev, RF3052) ||
1754             rt2x00_rf(rt2x00dev, RF3320))
1755                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1756         else if (rt2x00_rf(rt2x00dev, RF5390))
1757                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1758         else
1759                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1760
1761         /*
1762          * Change BBP settings
1763          */
1764         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1765         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1766         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1767         rt2800_bbp_write(rt2x00dev, 86, 0);
1768
1769         if (rf->channel <= 14) {
1770                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1771                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1772                                      &rt2x00dev->cap_flags)) {
1773                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1774                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1775                         } else {
1776                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1777                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1778                         }
1779                 }
1780         } else {
1781                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1782
1783                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1784                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1785                 else
1786                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1787         }
1788
1789         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1790         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1791         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1792         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1793         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1794
1795         tx_pin = 0;
1796
1797         /* Turn on unused PA or LNA when not using 1T or 1R */
1798         if (rt2x00dev->default_ant.tx_chain_num == 2) {
1799                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1800                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1801         }
1802
1803         /* Turn on unused PA or LNA when not using 1T or 1R */
1804         if (rt2x00dev->default_ant.rx_chain_num == 2) {
1805                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1806                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1807         }
1808
1809         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1810         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1811         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1812         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1813         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1814         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1815
1816         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1817
1818         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1819         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1820         rt2800_bbp_write(rt2x00dev, 4, bbp);
1821
1822         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1823         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1824         rt2800_bbp_write(rt2x00dev, 3, bbp);
1825
1826         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1827                 if (conf_is_ht40(conf)) {
1828                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1829                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1830                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1831                 } else {
1832                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1833                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1834                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1835                 }
1836         }
1837
1838         msleep(1);
1839
1840         /*
1841          * Clear channel statistic counters
1842          */
1843         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1844         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1845         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1846 }
1847
1848 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
1849 {
1850         u8 tssi_bounds[9];
1851         u8 current_tssi;
1852         u16 eeprom;
1853         u8 step;
1854         int i;
1855
1856         /*
1857          * Read TSSI boundaries for temperature compensation from
1858          * the EEPROM.
1859          *
1860          * Array idx               0    1    2    3    4    5    6    7    8
1861          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
1862          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
1863          */
1864         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1865                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
1866                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1867                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
1868                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1869                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
1870
1871                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
1872                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1873                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
1874                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1875                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
1876
1877                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
1878                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1879                                         EEPROM_TSSI_BOUND_BG3_REF);
1880                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1881                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
1882
1883                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
1884                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1885                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
1886                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1887                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
1888
1889                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
1890                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1891                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
1892
1893                 step = rt2x00_get_field16(eeprom,
1894                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
1895         } else {
1896                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
1897                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1898                                         EEPROM_TSSI_BOUND_A1_MINUS4);
1899                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1900                                         EEPROM_TSSI_BOUND_A1_MINUS3);
1901
1902                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
1903                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1904                                         EEPROM_TSSI_BOUND_A2_MINUS2);
1905                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1906                                         EEPROM_TSSI_BOUND_A2_MINUS1);
1907
1908                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
1909                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1910                                         EEPROM_TSSI_BOUND_A3_REF);
1911                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1912                                         EEPROM_TSSI_BOUND_A3_PLUS1);
1913
1914                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
1915                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1916                                         EEPROM_TSSI_BOUND_A4_PLUS2);
1917                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1918                                         EEPROM_TSSI_BOUND_A4_PLUS3);
1919
1920                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
1921                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1922                                         EEPROM_TSSI_BOUND_A5_PLUS4);
1923
1924                 step = rt2x00_get_field16(eeprom,
1925                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
1926         }
1927
1928         /*
1929          * Check if temperature compensation is supported.
1930          */
1931         if (tssi_bounds[4] == 0xff)
1932                 return 0;
1933
1934         /*
1935          * Read current TSSI (BBP 49).
1936          */
1937         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
1938
1939         /*
1940          * Compare TSSI value (BBP49) with the compensation boundaries
1941          * from the EEPROM and increase or decrease tx power.
1942          */
1943         for (i = 0; i <= 3; i++) {
1944                 if (current_tssi > tssi_bounds[i])
1945                         break;
1946         }
1947
1948         if (i == 4) {
1949                 for (i = 8; i >= 5; i--) {
1950                         if (current_tssi < tssi_bounds[i])
1951                                 break;
1952                 }
1953         }
1954
1955         return (i - 4) * step;
1956 }
1957
1958 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1959                                       enum ieee80211_band band)
1960 {
1961         u16 eeprom;
1962         u8 comp_en;
1963         u8 comp_type;
1964         int comp_value = 0;
1965
1966         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1967
1968         /*
1969          * HT40 compensation not required.
1970          */
1971         if (eeprom == 0xffff ||
1972             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1973                 return 0;
1974
1975         if (band == IEEE80211_BAND_2GHZ) {
1976                 comp_en = rt2x00_get_field16(eeprom,
1977                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
1978                 if (comp_en) {
1979                         comp_type = rt2x00_get_field16(eeprom,
1980                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
1981                         comp_value = rt2x00_get_field16(eeprom,
1982                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
1983                         if (!comp_type)
1984                                 comp_value = -comp_value;
1985                 }
1986         } else {
1987                 comp_en = rt2x00_get_field16(eeprom,
1988                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
1989                 if (comp_en) {
1990                         comp_type = rt2x00_get_field16(eeprom,
1991                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
1992                         comp_value = rt2x00_get_field16(eeprom,
1993                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
1994                         if (!comp_type)
1995                                 comp_value = -comp_value;
1996                 }
1997         }
1998
1999         return comp_value;
2000 }
2001
2002 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2003                                    enum ieee80211_band band, int power_level,
2004                                    u8 txpower, int delta)
2005 {
2006         u32 reg;
2007         u16 eeprom;
2008         u8 criterion;
2009         u8 eirp_txpower;
2010         u8 eirp_txpower_criterion;
2011         u8 reg_limit;
2012
2013         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2014                 return txpower;
2015
2016         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2017                 /*
2018                  * Check if eirp txpower exceed txpower_limit.
2019                  * We use OFDM 6M as criterion and its eirp txpower
2020                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2021                  * .11b data rate need add additional 4dbm
2022                  * when calculating eirp txpower.
2023                  */
2024                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2025                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2026
2027                 rt2x00_eeprom_read(rt2x00dev,
2028                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2029
2030                 if (band == IEEE80211_BAND_2GHZ)
2031                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2032                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2033                 else
2034                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2035                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2036
2037                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2038                                (is_rate_b ? 4 : 0) + delta;
2039
2040                 reg_limit = (eirp_txpower > power_level) ?
2041                                         (eirp_txpower - power_level) : 0;
2042         } else
2043                 reg_limit = 0;
2044
2045         return txpower + delta - reg_limit;
2046 }
2047
2048 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2049                                   enum ieee80211_band band,
2050                                   int power_level)
2051 {
2052         u8 txpower;
2053         u16 eeprom;
2054         int i, is_rate_b;
2055         u32 reg;
2056         u8 r1;
2057         u32 offset;
2058         int delta;
2059
2060         /*
2061          * Calculate HT40 compensation delta
2062          */
2063         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2064
2065         /*
2066          * calculate temperature compensation delta
2067          */
2068         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2069
2070         /*
2071          * set to normal bbp tx power control mode: +/- 0dBm
2072          */
2073         rt2800_bbp_read(rt2x00dev, 1, &r1);
2074         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2075         rt2800_bbp_write(rt2x00dev, 1, r1);
2076         offset = TX_PWR_CFG_0;
2077
2078         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2079                 /* just to be safe */
2080                 if (offset > TX_PWR_CFG_4)
2081                         break;
2082
2083                 rt2800_register_read(rt2x00dev, offset, &reg);
2084
2085                 /* read the next four txpower values */
2086                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2087                                    &eeprom);
2088
2089                 is_rate_b = i ? 0 : 1;
2090                 /*
2091                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2092                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2093                  * TX_PWR_CFG_4: unknown
2094                  */
2095                 txpower = rt2x00_get_field16(eeprom,
2096                                              EEPROM_TXPOWER_BYRATE_RATE0);
2097                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2098                                              power_level, txpower, delta);
2099                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2100
2101                 /*
2102                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2103                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2104                  * TX_PWR_CFG_4: unknown
2105                  */
2106                 txpower = rt2x00_get_field16(eeprom,
2107                                              EEPROM_TXPOWER_BYRATE_RATE1);
2108                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2109                                              power_level, txpower, delta);
2110                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2111
2112                 /*
2113                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2114                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2115                  * TX_PWR_CFG_4: unknown
2116                  */
2117                 txpower = rt2x00_get_field16(eeprom,
2118                                              EEPROM_TXPOWER_BYRATE_RATE2);
2119                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2120                                              power_level, txpower, delta);
2121                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2122
2123                 /*
2124                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2125                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2126                  * TX_PWR_CFG_4: unknown
2127                  */
2128                 txpower = rt2x00_get_field16(eeprom,
2129                                              EEPROM_TXPOWER_BYRATE_RATE3);
2130                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2131                                              power_level, txpower, delta);
2132                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2133
2134                 /* read the next four txpower values */
2135                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2136                                    &eeprom);
2137
2138                 is_rate_b = 0;
2139                 /*
2140                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2141                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2142                  * TX_PWR_CFG_4: unknown
2143                  */
2144                 txpower = rt2x00_get_field16(eeprom,
2145                                              EEPROM_TXPOWER_BYRATE_RATE0);
2146                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2147                                              power_level, txpower, delta);
2148                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2149
2150                 /*
2151                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2152                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2153                  * TX_PWR_CFG_4: unknown
2154                  */
2155                 txpower = rt2x00_get_field16(eeprom,
2156                                              EEPROM_TXPOWER_BYRATE_RATE1);
2157                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2158                                              power_level, txpower, delta);
2159                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2160
2161                 /*
2162                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2163                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2164                  * TX_PWR_CFG_4: unknown
2165                  */
2166                 txpower = rt2x00_get_field16(eeprom,
2167                                              EEPROM_TXPOWER_BYRATE_RATE2);
2168                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2169                                              power_level, txpower, delta);
2170                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2171
2172                 /*
2173                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2174                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2175                  * TX_PWR_CFG_4: unknown
2176                  */
2177                 txpower = rt2x00_get_field16(eeprom,
2178                                              EEPROM_TXPOWER_BYRATE_RATE3);
2179                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2180                                              power_level, txpower, delta);
2181                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2182
2183                 rt2800_register_write(rt2x00dev, offset, reg);
2184
2185                 /* next TX_PWR_CFG register */
2186                 offset += 4;
2187         }
2188 }
2189
2190 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2191 {
2192         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2193                               rt2x00dev->tx_power);
2194 }
2195 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2196
2197 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2198                                       struct rt2x00lib_conf *libconf)
2199 {
2200         u32 reg;
2201
2202         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2203         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2204                            libconf->conf->short_frame_max_tx_count);
2205         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2206                            libconf->conf->long_frame_max_tx_count);
2207         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2208 }
2209
2210 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2211                              struct rt2x00lib_conf *libconf)
2212 {
2213         enum dev_state state =
2214             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2215                 STATE_SLEEP : STATE_AWAKE;
2216         u32 reg;
2217
2218         if (state == STATE_SLEEP) {
2219                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2220
2221                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2222                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2223                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2224                                    libconf->conf->listen_interval - 1);
2225                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2226                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2227
2228                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2229         } else {
2230                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2231                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2232                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2233                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2234                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2235
2236                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2237         }
2238 }
2239
2240 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2241                    struct rt2x00lib_conf *libconf,
2242                    const unsigned int flags)
2243 {
2244         /* Always recalculate LNA gain before changing configuration */
2245         rt2800_config_lna_gain(rt2x00dev, libconf);
2246
2247         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2248                 rt2800_config_channel(rt2x00dev, libconf->conf,
2249                                       &libconf->rf, &libconf->channel);
2250                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2251                                       libconf->conf->power_level);
2252         }
2253         if (flags & IEEE80211_CONF_CHANGE_POWER)
2254                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2255                                       libconf->conf->power_level);
2256         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2257                 rt2800_config_retry_limit(rt2x00dev, libconf);
2258         if (flags & IEEE80211_CONF_CHANGE_PS)
2259                 rt2800_config_ps(rt2x00dev, libconf);
2260 }
2261 EXPORT_SYMBOL_GPL(rt2800_config);
2262
2263 /*
2264  * Link tuning
2265  */
2266 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2267 {
2268         u32 reg;
2269
2270         /*
2271          * Update FCS error count from register.
2272          */
2273         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2274         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2275 }
2276 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2277
2278 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2279 {
2280         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2281                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2282                     rt2x00_rt(rt2x00dev, RT3071) ||
2283                     rt2x00_rt(rt2x00dev, RT3090) ||
2284                     rt2x00_rt(rt2x00dev, RT3390) ||
2285                     rt2x00_rt(rt2x00dev, RT5390))
2286                         return 0x1c + (2 * rt2x00dev->lna_gain);
2287                 else
2288                         return 0x2e + rt2x00dev->lna_gain;
2289         }
2290
2291         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2292                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2293         else
2294                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2295 }
2296
2297 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2298                                   struct link_qual *qual, u8 vgc_level)
2299 {
2300         if (qual->vgc_level != vgc_level) {
2301                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2302                 qual->vgc_level = vgc_level;
2303                 qual->vgc_level_reg = vgc_level;
2304         }
2305 }
2306
2307 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2308 {
2309         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2310 }
2311 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2312
2313 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2314                        const u32 count)
2315 {
2316         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2317                 return;
2318
2319         /*
2320          * When RSSI is better then -80 increase VGC level with 0x10
2321          */
2322         rt2800_set_vgc(rt2x00dev, qual,
2323                        rt2800_get_default_vgc(rt2x00dev) +
2324                        ((qual->rssi > -80) * 0x10));
2325 }
2326 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2327
2328 /*
2329  * Initialization functions.
2330  */
2331 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2332 {
2333         u32 reg;
2334         u16 eeprom;
2335         unsigned int i;
2336         int ret;
2337
2338         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2339         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2340         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2341         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2342         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2343         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2344         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2345
2346         ret = rt2800_drv_init_registers(rt2x00dev);
2347         if (ret)
2348                 return ret;
2349
2350         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2351         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2352         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2353         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2354         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2355         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2356
2357         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2358         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2359         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2360         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2361         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2362         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2363
2364         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2365         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2366
2367         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2368
2369         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2370         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2371         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2372         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2373         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2374         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2375         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2376         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2377
2378         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2379
2380         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2381         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2382         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2383         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2384
2385         if (rt2x00_rt(rt2x00dev, RT3071) ||
2386             rt2x00_rt(rt2x00dev, RT3090) ||
2387             rt2x00_rt(rt2x00dev, RT3390)) {
2388                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2389                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2390                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2391                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2392                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2393                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2394                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2395                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2396                                                       0x0000002c);
2397                         else
2398                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2399                                                       0x0000000f);
2400                 } else {
2401                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2402                 }
2403         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2404                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2405
2406                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2407                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2408                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2409                 } else {
2410                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2411                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2412                 }
2413         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2414                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2415                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2416                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2417         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2418                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2419                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2420                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2421         } else {
2422                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2423                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2424         }
2425
2426         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2427         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2428         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2429         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2430         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2431         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2432         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2433         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2434         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2435         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2436
2437         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2438         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2439         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2440         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2441         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2442
2443         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2444         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2445         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2446             rt2x00_rt(rt2x00dev, RT2883) ||
2447             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2448                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2449         else
2450                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2451         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2452         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2453         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2454
2455         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2456         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2457         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2458         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2459         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2460         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2461         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2462         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2463         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2464
2465         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2466
2467         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2468         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2469         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2470         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2471         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2472         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2473         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2474         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2475
2476         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2477         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2478         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2479         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2480         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2481         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2482         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2483         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2484         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2485
2486         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2487         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2488         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2489         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2490         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2491         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2492         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2493         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2494         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2495         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2496         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2497         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2498
2499         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2500         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2501         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2502         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2503         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2504         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2505         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2506         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2507         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2508         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2509         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2510         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2511
2512         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2513         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2514         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2515         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2516         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2517         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2518         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2519         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2520         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2521         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2522         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2523         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2524
2525         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2526         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2527         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2528         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2529         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2530         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2531         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2532         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2533         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2534         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2535         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2536         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2537
2538         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2539         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2540         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2541         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2542         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2543         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2544         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2545         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2546         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2547         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2548         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2549         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2550
2551         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2552         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2553         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2554         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2555         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2556         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2557         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2558         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2559         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2560         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2561         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2562         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2563
2564         if (rt2x00_is_usb(rt2x00dev)) {
2565                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2566
2567                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2568                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2569                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2570                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2571                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2572                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2573                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2574                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2575                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2576                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2577                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2578         }
2579
2580         /*
2581          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2582          * although it is reserved.
2583          */
2584         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2585         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2586         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2587         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2588         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2589         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2590         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2591         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2592         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2593         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2594         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2595         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2596
2597         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2598
2599         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2600         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2601         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2602                            IEEE80211_MAX_RTS_THRESHOLD);
2603         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2604         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2605
2606         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2607
2608         /*
2609          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2610          * time should be set to 16. However, the original Ralink driver uses
2611          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2612          * connection problems with 11g + CTS protection. Hence, use the same
2613          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2614          */
2615         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2616         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2617         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2618         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2619         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2620         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2621         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2622
2623         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2624
2625         /*
2626          * ASIC will keep garbage value after boot, clear encryption keys.
2627          */
2628         for (i = 0; i < 4; i++)
2629                 rt2800_register_write(rt2x00dev,
2630                                          SHARED_KEY_MODE_ENTRY(i), 0);
2631
2632         for (i = 0; i < 256; i++) {
2633                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2634                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2635                                               wcid, sizeof(wcid));
2636
2637                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
2638                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2639         }
2640
2641         /*
2642          * Clear all beacons
2643          */
2644         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2645         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2646         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2647         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2648         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2649         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2650         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2651         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2652
2653         if (rt2x00_is_usb(rt2x00dev)) {
2654                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2655                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2656                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2657         } else if (rt2x00_is_pcie(rt2x00dev)) {
2658                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2659                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2660                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2661         }
2662
2663         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2664         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2665         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2666         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2667         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2668         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2669         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2670         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2671         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2672         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2673
2674         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2675         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2676         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2677         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2678         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2679         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2680         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2681         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2682         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2683         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2684
2685         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2686         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2687         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2688         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2689         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2690         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2691         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2692         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2693         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2694         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2695
2696         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2697         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2698         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2699         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2700         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2701         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2702
2703         /*
2704          * Do not force the BA window size, we use the TXWI to set it
2705          */
2706         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2707         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2708         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2709         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2710
2711         /*
2712          * We must clear the error counters.
2713          * These registers are cleared on read,
2714          * so we may pass a useless variable to store the value.
2715          */
2716         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2717         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2718         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2719         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2720         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2721         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2722
2723         /*
2724          * Setup leadtime for pre tbtt interrupt to 6ms
2725          */
2726         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2727         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2728         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2729
2730         /*
2731          * Set up channel statistics timer
2732          */
2733         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2734         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2735         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2736         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2737         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2738         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2739         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2740
2741         return 0;
2742 }
2743
2744 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2745 {
2746         unsigned int i;
2747         u32 reg;
2748
2749         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2750                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2751                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2752                         return 0;
2753
2754                 udelay(REGISTER_BUSY_DELAY);
2755         }
2756
2757         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2758         return -EACCES;
2759 }
2760
2761 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2762 {
2763         unsigned int i;
2764         u8 value;
2765
2766         /*
2767          * BBP was enabled after firmware was loaded,
2768          * but we need to reactivate it now.
2769          */
2770         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2771         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2772         msleep(1);
2773
2774         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2775                 rt2800_bbp_read(rt2x00dev, 0, &value);
2776                 if ((value != 0xff) && (value != 0x00))
2777                         return 0;
2778                 udelay(REGISTER_BUSY_DELAY);
2779         }
2780
2781         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2782         return -EACCES;
2783 }
2784
2785 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2786 {
2787         unsigned int i;
2788         u16 eeprom;
2789         u8 reg_id;
2790         u8 value;
2791
2792         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2793                      rt2800_wait_bbp_ready(rt2x00dev)))
2794                 return -EACCES;
2795
2796         if (rt2x00_rt(rt2x00dev, RT5390)) {
2797                 rt2800_bbp_read(rt2x00dev, 4, &value);
2798                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2799                 rt2800_bbp_write(rt2x00dev, 4, value);
2800         }
2801
2802         if (rt2800_is_305x_soc(rt2x00dev) ||
2803             rt2x00_rt(rt2x00dev, RT5390))
2804                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2805
2806         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2807         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2808
2809         if (rt2x00_rt(rt2x00dev, RT5390))
2810                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2811
2812         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2813                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2814                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2815         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2816                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2817                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2818                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2819                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2820                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2821         } else {
2822                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2823                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2824         }
2825
2826         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2827
2828         if (rt2x00_rt(rt2x00dev, RT3070) ||
2829             rt2x00_rt(rt2x00dev, RT3071) ||
2830             rt2x00_rt(rt2x00dev, RT3090) ||
2831             rt2x00_rt(rt2x00dev, RT3390) ||
2832             rt2x00_rt(rt2x00dev, RT5390)) {
2833                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2834                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2835                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2836         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2837                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2838                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2839         } else {
2840                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2841         }
2842
2843         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2844         if (rt2x00_rt(rt2x00dev, RT5390))
2845                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2846         else
2847                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2848
2849         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2850                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2851         else if (rt2x00_rt(rt2x00dev, RT5390))
2852                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2853         else
2854                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2855
2856         if (rt2x00_rt(rt2x00dev, RT5390))
2857                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2858         else
2859                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2860
2861         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2862
2863         if (rt2x00_rt(rt2x00dev, RT5390))
2864                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2865         else
2866                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2867
2868         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2869             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2870             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2871             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2872             rt2x00_rt(rt2x00dev, RT5390) ||
2873             rt2800_is_305x_soc(rt2x00dev))
2874                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2875         else
2876                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2877
2878         if (rt2x00_rt(rt2x00dev, RT5390))
2879                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2880
2881         if (rt2800_is_305x_soc(rt2x00dev))
2882                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2883         else if (rt2x00_rt(rt2x00dev, RT5390))
2884                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2885         else
2886                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2887
2888         if (rt2x00_rt(rt2x00dev, RT5390))
2889                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2890         else
2891                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2892
2893         if (rt2x00_rt(rt2x00dev, RT5390))
2894                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2895
2896         if (rt2x00_rt(rt2x00dev, RT3071) ||
2897             rt2x00_rt(rt2x00dev, RT3090) ||
2898             rt2x00_rt(rt2x00dev, RT3390) ||
2899             rt2x00_rt(rt2x00dev, RT5390)) {
2900                 rt2800_bbp_read(rt2x00dev, 138, &value);
2901
2902                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2903                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2904                         value |= 0x20;
2905                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2906                         value &= ~0x02;
2907
2908                 rt2800_bbp_write(rt2x00dev, 138, value);
2909         }
2910
2911         if (rt2x00_rt(rt2x00dev, RT5390)) {
2912                 int ant, div_mode;
2913
2914                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2915                 div_mode = rt2x00_get_field16(eeprom,
2916                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
2917                 ant = (div_mode == 3) ? 1 : 0;
2918
2919                 /* check if this is a Bluetooth combo card */
2920                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2921                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2922                         u32 reg;
2923
2924                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2925                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2926                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2927                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2928                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2929                         if (ant == 0)
2930                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2931                         else if (ant == 1)
2932                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2933                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2934                 }
2935
2936                 rt2800_bbp_read(rt2x00dev, 152, &value);
2937                 if (ant == 0)
2938                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2939                 else
2940                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2941                 rt2800_bbp_write(rt2x00dev, 152, value);
2942
2943                 /* Init frequency calibration */
2944                 rt2800_bbp_write(rt2x00dev, 142, 1);
2945                 rt2800_bbp_write(rt2x00dev, 143, 57);
2946         }
2947
2948         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2949                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2950
2951                 if (eeprom != 0xffff && eeprom != 0x0000) {
2952                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2953                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2954                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2955                 }
2956         }
2957
2958         return 0;
2959 }
2960
2961 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2962                                 bool bw40, u8 rfcsr24, u8 filter_target)
2963 {
2964         unsigned int i;
2965         u8 bbp;
2966         u8 rfcsr;
2967         u8 passband;
2968         u8 stopband;
2969         u8 overtuned = 0;
2970
2971         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2972
2973         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2974         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2975         rt2800_bbp_write(rt2x00dev, 4, bbp);
2976
2977         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2978         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2979         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2980
2981         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2982         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2983         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2984
2985         /*
2986          * Set power & frequency of passband test tone
2987          */
2988         rt2800_bbp_write(rt2x00dev, 24, 0);
2989
2990         for (i = 0; i < 100; i++) {
2991                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2992                 msleep(1);
2993
2994                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2995                 if (passband)
2996                         break;
2997         }
2998
2999         /*
3000          * Set power & frequency of stopband test tone
3001          */
3002         rt2800_bbp_write(rt2x00dev, 24, 0x06);
3003
3004         for (i = 0; i < 100; i++) {
3005                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3006                 msleep(1);
3007
3008                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3009
3010                 if ((passband - stopband) <= filter_target) {
3011                         rfcsr24++;
3012                         overtuned += ((passband - stopband) == filter_target);
3013                 } else
3014                         break;
3015
3016                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3017         }
3018
3019         rfcsr24 -= !!overtuned;
3020
3021         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3022         return rfcsr24;
3023 }
3024
3025 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3026 {
3027         u8 rfcsr;
3028         u8 bbp;
3029         u32 reg;
3030         u16 eeprom;
3031
3032         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3033             !rt2x00_rt(rt2x00dev, RT3071) &&
3034             !rt2x00_rt(rt2x00dev, RT3090) &&
3035             !rt2x00_rt(rt2x00dev, RT3390) &&
3036             !rt2x00_rt(rt2x00dev, RT5390) &&
3037             !rt2800_is_305x_soc(rt2x00dev))
3038                 return 0;
3039
3040         /*
3041          * Init RF calibration.
3042          */
3043         if (rt2x00_rt(rt2x00dev, RT5390)) {
3044                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3045                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3046                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3047                 msleep(1);
3048                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3049                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3050         } else {
3051                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3052                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3053                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3054                 msleep(1);
3055                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3056                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3057         }
3058
3059         if (rt2x00_rt(rt2x00dev, RT3070) ||
3060             rt2x00_rt(rt2x00dev, RT3071) ||
3061             rt2x00_rt(rt2x00dev, RT3090)) {
3062                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3063                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3064                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3065                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3066                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3067                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3068                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3069                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3070                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3071                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3072                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3073                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3074                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3075                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3076                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3077                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3078                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3079                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3080                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3081         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3082                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3083                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3084                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3085                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3086                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3087                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3088                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3089                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3090                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3091                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3092                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3093                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3094                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3095                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3096                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3097                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3098                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3099                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3100                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3101                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3102                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3103                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3104                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3105                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3106                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3107                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3108                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3109                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3110                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3111                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3112                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3113                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3114         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3115                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3116                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3117                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3118                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3119                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3120                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3121                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3122                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3123                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3124                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3125                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3126                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3127                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3128                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3129                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3130                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3131                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3132                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3133                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3134                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3135                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3136                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3137                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3138                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3139                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3140                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3141                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3142                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3143                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3144                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3145                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3146                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3147                 return 0;
3148         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3149                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3150                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3151                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3152                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3153                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3154                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3155                 else
3156                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3157                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3158                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3159                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3160                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3161                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3162                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3163                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3164                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3165                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3166                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3167
3168                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3169                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3170                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3171                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3172                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3173                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3174                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3175                 else
3176                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3177                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3178                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3179                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3180                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3181
3182                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3183                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3184                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3185                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3186                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3187                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3188                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3189                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3190                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3191                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3192
3193                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3194                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3195                 else
3196                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3197                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3198                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3199                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3200                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3201                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3202                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3203                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3204                 else
3205                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3206                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3207                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3208                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3209
3210                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3211                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3212                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3213                 else
3214                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3215                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3216                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3217                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3218                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3219                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3220                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3221
3222                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3223                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3224                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3225                 else
3226                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3227                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3228                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3229         }
3230
3231         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3232                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3233                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3234                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3235                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3236         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3237                    rt2x00_rt(rt2x00dev, RT3090)) {
3238                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3239
3240                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3241                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3242                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3243
3244                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3245                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3246                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3247                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3248                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3249                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3250                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3251                         else
3252                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3253                 }
3254                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3255
3256                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3257                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3258                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3259         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3260                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3261                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3262                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3263         }
3264
3265         /*
3266          * Set RX Filter calibration for 20MHz and 40MHz
3267          */
3268         if (rt2x00_rt(rt2x00dev, RT3070)) {
3269                 rt2x00dev->calibration[0] =
3270                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3271                 rt2x00dev->calibration[1] =
3272                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3273         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3274                    rt2x00_rt(rt2x00dev, RT3090) ||
3275                    rt2x00_rt(rt2x00dev, RT3390)) {
3276                 rt2x00dev->calibration[0] =
3277                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3278                 rt2x00dev->calibration[1] =
3279                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3280         }
3281
3282         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3283                 /*
3284                  * Set back to initial state
3285                  */
3286                 rt2800_bbp_write(rt2x00dev, 24, 0);
3287
3288                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3289                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3290                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3291
3292                 /*
3293                  * Set BBP back to BW20
3294                  */
3295                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3296                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3297                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3298         }
3299
3300         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3301             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3302             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3303             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3304                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3305
3306         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3307         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3308         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3309
3310         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3311                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3312                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3313                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3314                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3315                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3316                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3317                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3318                                       &rt2x00dev->cap_flags))
3319                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3320                 }
3321                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3322                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3323                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3324                                         rt2x00_get_field16(eeprom,
3325                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3326                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3327         }
3328
3329         if (rt2x00_rt(rt2x00dev, RT3090)) {
3330                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3331
3332                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3333                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3334                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3335                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3336                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3337                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3338
3339                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3340         }
3341
3342         if (rt2x00_rt(rt2x00dev, RT3071) ||
3343             rt2x00_rt(rt2x00dev, RT3090) ||
3344             rt2x00_rt(rt2x00dev, RT3390)) {
3345                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3346                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3347                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3348                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3349                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3350                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3351                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3352
3353                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3354                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3355                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3356
3357                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3358                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3359                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3360
3361                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3362                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3363                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3364         }
3365
3366         if (rt2x00_rt(rt2x00dev, RT3070)) {
3367                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3368                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3369                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3370                 else
3371                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3372                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3373                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3374                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3375                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3376         }
3377
3378         if (rt2x00_rt(rt2x00dev, RT5390)) {
3379                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3380                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3381                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3382
3383                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3384                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3385                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3386
3387                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3388                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3389                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3390         }
3391
3392         return 0;
3393 }
3394
3395 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3396 {
3397         u32 reg;
3398         u16 word;
3399
3400         /*
3401          * Initialize all registers.
3402          */
3403         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3404                      rt2800_init_registers(rt2x00dev) ||
3405                      rt2800_init_bbp(rt2x00dev) ||
3406                      rt2800_init_rfcsr(rt2x00dev)))
3407                 return -EIO;
3408
3409         /*
3410          * Send signal to firmware during boot time.
3411          */
3412         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3413
3414         if (rt2x00_is_usb(rt2x00dev) &&
3415             (rt2x00_rt(rt2x00dev, RT3070) ||
3416              rt2x00_rt(rt2x00dev, RT3071) ||
3417              rt2x00_rt(rt2x00dev, RT3572))) {
3418                 udelay(200);
3419                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3420                 udelay(10);
3421         }
3422
3423         /*
3424          * Enable RX.
3425          */
3426         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3427         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3428         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3429         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3430
3431         udelay(50);
3432
3433         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3434         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3435         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3436         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3437         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3438         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3439
3440         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3441         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3442         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3443         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3444
3445         /*
3446          * Initialize LED control
3447          */
3448         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3449         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3450                            word & 0xff, (word >> 8) & 0xff);
3451
3452         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3453         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3454                            word & 0xff, (word >> 8) & 0xff);
3455
3456         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3457         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3458                            word & 0xff, (word >> 8) & 0xff);
3459
3460         return 0;
3461 }
3462 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3463
3464 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3465 {
3466         u32 reg;
3467
3468         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3469         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3470         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3471         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3472
3473         /* Wait for DMA, ignore error */
3474         rt2800_wait_wpdma_ready(rt2x00dev);
3475
3476         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3477         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3478         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3479         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3480 }
3481 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3482
3483 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3484 {
3485         u32 reg;
3486
3487         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3488
3489         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3490 }
3491 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3492
3493 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3494 {
3495         u32 reg;
3496
3497         mutex_lock(&rt2x00dev->csr_mutex);
3498
3499         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3500         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3501         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3502         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3503         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3504
3505         /* Wait until the EEPROM has been loaded */
3506         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3507
3508         /* Apparently the data is read from end to start */
3509         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3510                                         (u32 *)&rt2x00dev->eeprom[i]);
3511         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3512                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
3513         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3514                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
3515         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3516                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
3517
3518         mutex_unlock(&rt2x00dev->csr_mutex);
3519 }
3520
3521 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3522 {
3523         unsigned int i;
3524
3525         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3526                 rt2800_efuse_read(rt2x00dev, i);
3527 }
3528 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3529
3530 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3531 {
3532         u16 word;
3533         u8 *mac;
3534         u8 default_lna_gain;
3535
3536         /*
3537          * Start validation of the data that has been read.
3538          */
3539         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3540         if (!is_valid_ether_addr(mac)) {
3541                 random_ether_addr(mac);
3542                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3543         }
3544
3545         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3546         if (word == 0xffff) {
3547                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3548                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3549                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3550                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3551                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3552         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3553                    rt2x00_rt(rt2x00dev, RT2872)) {
3554                 /*
3555                  * There is a max of 2 RX streams for RT28x0 series
3556                  */
3557                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3558                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3559                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3560         }
3561
3562         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3563         if (word == 0xffff) {
3564                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3565                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3566                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3567                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3568                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3569                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3570                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3571                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3572                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3573                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3574                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3575                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3576                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3577                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3578                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3579                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3580                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3581         }
3582
3583         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3584         if ((word & 0x00ff) == 0x00ff) {
3585                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3586                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3587                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3588         }
3589         if ((word & 0xff00) == 0xff00) {
3590                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3591                                    LED_MODE_TXRX_ACTIVITY);
3592                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3593                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3594                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3595                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3596                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3597                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3598         }
3599
3600         /*
3601          * During the LNA validation we are going to use
3602          * lna0 as correct value. Note that EEPROM_LNA
3603          * is never validated.
3604          */
3605         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3606         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3607
3608         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3609         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3610                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3611         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3612                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3613         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3614
3615         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3616         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3617                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3618         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3619             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3620                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3621                                    default_lna_gain);
3622         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3623
3624         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3625         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3626                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3627         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3628                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3629         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3630
3631         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3632         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3633                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3634         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3635             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3636                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3637                                    default_lna_gain);
3638         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3639
3640         return 0;
3641 }
3642 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3643
3644 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3645 {
3646         u32 reg;
3647         u16 value;
3648         u16 eeprom;
3649
3650         /*
3651          * Read EEPROM word for configuration.
3652          */
3653         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3654
3655         /*
3656          * Identify RF chipset by EEPROM value
3657          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3658          * RT53xx: defined in "EEPROM_CHIP_ID" field
3659          */
3660         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3661         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3662                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3663         else
3664                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3665
3666         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3667                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3668
3669         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3670             !rt2x00_rt(rt2x00dev, RT2872) &&
3671             !rt2x00_rt(rt2x00dev, RT2883) &&
3672             !rt2x00_rt(rt2x00dev, RT3070) &&
3673             !rt2x00_rt(rt2x00dev, RT3071) &&
3674             !rt2x00_rt(rt2x00dev, RT3090) &&
3675             !rt2x00_rt(rt2x00dev, RT3390) &&
3676             !rt2x00_rt(rt2x00dev, RT3572) &&
3677             !rt2x00_rt(rt2x00dev, RT5390)) {
3678                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3679                 return -ENODEV;
3680         }
3681
3682         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3683             !rt2x00_rf(rt2x00dev, RF2850) &&
3684             !rt2x00_rf(rt2x00dev, RF2720) &&
3685             !rt2x00_rf(rt2x00dev, RF2750) &&
3686             !rt2x00_rf(rt2x00dev, RF3020) &&
3687             !rt2x00_rf(rt2x00dev, RF2020) &&
3688             !rt2x00_rf(rt2x00dev, RF3021) &&
3689             !rt2x00_rf(rt2x00dev, RF3022) &&
3690             !rt2x00_rf(rt2x00dev, RF3052) &&
3691             !rt2x00_rf(rt2x00dev, RF3320) &&
3692             !rt2x00_rf(rt2x00dev, RF5390)) {
3693                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3694                 return -ENODEV;
3695         }
3696
3697         /*
3698          * Identify default antenna configuration.
3699          */
3700         rt2x00dev->default_ant.tx_chain_num =
3701             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3702         rt2x00dev->default_ant.rx_chain_num =
3703             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3704
3705         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3706
3707         if (rt2x00_rt(rt2x00dev, RT3070) ||
3708             rt2x00_rt(rt2x00dev, RT3090) ||
3709             rt2x00_rt(rt2x00dev, RT3390)) {
3710                 value = rt2x00_get_field16(eeprom,
3711                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3712                 switch (value) {
3713                 case 0:
3714                 case 1:
3715                 case 2:
3716                         rt2x00dev->default_ant.tx = ANTENNA_A;
3717                         rt2x00dev->default_ant.rx = ANTENNA_A;
3718                         break;
3719                 case 3:
3720                         rt2x00dev->default_ant.tx = ANTENNA_A;
3721                         rt2x00dev->default_ant.rx = ANTENNA_B;
3722                         break;
3723                 }
3724         } else {
3725                 rt2x00dev->default_ant.tx = ANTENNA_A;
3726                 rt2x00dev->default_ant.rx = ANTENNA_A;
3727         }
3728
3729         /*
3730          * Read frequency offset and RF programming sequence.
3731          */
3732         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3733         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3734
3735         /*
3736          * Read external LNA informations.
3737          */
3738         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3739
3740         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3741                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
3742         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3743                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
3744
3745         /*
3746          * Detect if this device has an hardware controlled radio.
3747          */
3748         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3749                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
3750
3751         /*
3752          * Store led settings, for correct led behaviour.
3753          */
3754 #ifdef CONFIG_RT2X00_LIB_LEDS
3755         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3756         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3757         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3758
3759         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3760 #endif /* CONFIG_RT2X00_LIB_LEDS */
3761
3762         /*
3763          * Check if support EIRP tx power limit feature.
3764          */
3765         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3766
3767         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3768                                         EIRP_MAX_TX_POWER_LIMIT)
3769                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
3770
3771         return 0;
3772 }
3773 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3774
3775 /*
3776  * RF value list for rt28xx
3777  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3778  */
3779 static const struct rf_channel rf_vals[] = {
3780         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3781         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3782         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3783         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3784         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3785         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3786         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3787         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3788         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3789         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3790         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3791         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3792         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3793         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3794
3795         /* 802.11 UNI / HyperLan 2 */
3796         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3797         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3798         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3799         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3800         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3801         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3802         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3803         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3804         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3805         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3806         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3807         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3808
3809         /* 802.11 HyperLan 2 */
3810         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3811         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3812         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3813         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3814         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3815         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3816         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3817         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3818         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3819         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3820         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3821         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3822         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3823         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3824         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3825         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3826
3827         /* 802.11 UNII */
3828         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3829         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3830         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3831         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3832         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3833         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3834         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3835         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3836         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3837         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3838         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3839
3840         /* 802.11 Japan */
3841         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3842         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3843         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3844         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3845         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3846         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3847         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3848 };
3849
3850 /*
3851  * RF value list for rt3xxx
3852  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3853  */
3854 static const struct rf_channel rf_vals_3x[] = {
3855         {1,  241, 2, 2 },
3856         {2,  241, 2, 7 },
3857         {3,  242, 2, 2 },
3858         {4,  242, 2, 7 },
3859         {5,  243, 2, 2 },
3860         {6,  243, 2, 7 },
3861         {7,  244, 2, 2 },
3862         {8,  244, 2, 7 },
3863         {9,  245, 2, 2 },
3864         {10, 245, 2, 7 },
3865         {11, 246, 2, 2 },
3866         {12, 246, 2, 7 },
3867         {13, 247, 2, 2 },
3868         {14, 248, 2, 4 },
3869
3870         /* 802.11 UNI / HyperLan 2 */
3871         {36, 0x56, 0, 4},
3872         {38, 0x56, 0, 6},
3873         {40, 0x56, 0, 8},
3874         {44, 0x57, 0, 0},
3875         {46, 0x57, 0, 2},
3876         {48, 0x57, 0, 4},
3877         {52, 0x57, 0, 8},
3878         {54, 0x57, 0, 10},
3879         {56, 0x58, 0, 0},
3880         {60, 0x58, 0, 4},
3881         {62, 0x58, 0, 6},
3882         {64, 0x58, 0, 8},
3883
3884         /* 802.11 HyperLan 2 */
3885         {100, 0x5b, 0, 8},
3886         {102, 0x5b, 0, 10},
3887         {104, 0x5c, 0, 0},
3888         {108, 0x5c, 0, 4},
3889         {110, 0x5c, 0, 6},
3890         {112, 0x5c, 0, 8},
3891         {116, 0x5d, 0, 0},
3892         {118, 0x5d, 0, 2},
3893         {120, 0x5d, 0, 4},
3894         {124, 0x5d, 0, 8},
3895         {126, 0x5d, 0, 10},
3896         {128, 0x5e, 0, 0},
3897         {132, 0x5e, 0, 4},
3898         {134, 0x5e, 0, 6},
3899         {136, 0x5e, 0, 8},
3900         {140, 0x5f, 0, 0},
3901
3902         /* 802.11 UNII */
3903         {149, 0x5f, 0, 9},
3904         {151, 0x5f, 0, 11},
3905         {153, 0x60, 0, 1},
3906         {157, 0x60, 0, 5},
3907         {159, 0x60, 0, 7},
3908         {161, 0x60, 0, 9},
3909         {165, 0x61, 0, 1},
3910         {167, 0x61, 0, 3},
3911         {169, 0x61, 0, 5},
3912         {171, 0x61, 0, 7},
3913         {173, 0x61, 0, 9},
3914 };
3915
3916 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3917 {
3918         struct hw_mode_spec *spec = &rt2x00dev->spec;
3919         struct channel_info *info;
3920         char *default_power1;
3921         char *default_power2;
3922         unsigned int i;
3923         u16 eeprom;
3924
3925         /*
3926          * Disable powersaving as default on PCI devices.
3927          */
3928         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3929                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3930
3931         /*
3932          * Initialize all hw fields.
3933          */
3934         rt2x00dev->hw->flags =
3935             IEEE80211_HW_SIGNAL_DBM |
3936             IEEE80211_HW_SUPPORTS_PS |
3937             IEEE80211_HW_PS_NULLFUNC_STACK |
3938             IEEE80211_HW_AMPDU_AGGREGATION;
3939         /*
3940          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3941          * unless we are capable of sending the buffered frames out after the
3942          * DTIM transmission using rt2x00lib_beacondone. This will send out
3943          * multicast and broadcast traffic immediately instead of buffering it
3944          * infinitly and thus dropping it after some time.
3945          */
3946         if (!rt2x00_is_usb(rt2x00dev))
3947                 rt2x00dev->hw->flags |=
3948                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3949
3950         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3951         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3952                                 rt2x00_eeprom_addr(rt2x00dev,
3953                                                    EEPROM_MAC_ADDR_0));
3954
3955         /*
3956          * As rt2800 has a global fallback table we cannot specify
3957          * more then one tx rate per frame but since the hw will
3958          * try several rates (based on the fallback table) we should
3959          * initialize max_report_rates to the maximum number of rates
3960          * we are going to try. Otherwise mac80211 will truncate our
3961          * reported tx rates and the rc algortihm will end up with
3962          * incorrect data.
3963          */
3964         rt2x00dev->hw->max_rates = 1;
3965         rt2x00dev->hw->max_report_rates = 7;
3966         rt2x00dev->hw->max_rate_tries = 1;
3967
3968         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3969
3970         /*
3971          * Initialize hw_mode information.
3972          */
3973         spec->supported_bands = SUPPORT_BAND_2GHZ;
3974         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3975
3976         if (rt2x00_rf(rt2x00dev, RF2820) ||
3977             rt2x00_rf(rt2x00dev, RF2720)) {
3978                 spec->num_channels = 14;
3979                 spec->channels = rf_vals;
3980         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3981                    rt2x00_rf(rt2x00dev, RF2750)) {
3982                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3983                 spec->num_channels = ARRAY_SIZE(rf_vals);
3984                 spec->channels = rf_vals;
3985         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3986                    rt2x00_rf(rt2x00dev, RF2020) ||
3987                    rt2x00_rf(rt2x00dev, RF3021) ||
3988                    rt2x00_rf(rt2x00dev, RF3022) ||
3989                    rt2x00_rf(rt2x00dev, RF3320) ||
3990                    rt2x00_rf(rt2x00dev, RF5390)) {
3991                 spec->num_channels = 14;
3992                 spec->channels = rf_vals_3x;
3993         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3994                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3995                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3996                 spec->channels = rf_vals_3x;
3997         }
3998
3999         /*
4000          * Initialize HT information.
4001          */
4002         if (!rt2x00_rf(rt2x00dev, RF2020))
4003                 spec->ht.ht_supported = true;
4004         else
4005                 spec->ht.ht_supported = false;
4006
4007         spec->ht.cap =
4008             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4009             IEEE80211_HT_CAP_GRN_FLD |
4010             IEEE80211_HT_CAP_SGI_20 |
4011             IEEE80211_HT_CAP_SGI_40;
4012
4013         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4014                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4015
4016         spec->ht.cap |=
4017             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4018                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4019
4020         spec->ht.ampdu_factor = 3;
4021         spec->ht.ampdu_density = 4;
4022         spec->ht.mcs.tx_params =
4023             IEEE80211_HT_MCS_TX_DEFINED |
4024             IEEE80211_HT_MCS_TX_RX_DIFF |
4025             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4026                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4027
4028         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4029         case 3:
4030                 spec->ht.mcs.rx_mask[2] = 0xff;
4031         case 2:
4032                 spec->ht.mcs.rx_mask[1] = 0xff;
4033         case 1:
4034                 spec->ht.mcs.rx_mask[0] = 0xff;
4035                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4036                 break;
4037         }
4038
4039         /*
4040          * Create channel information array
4041          */
4042         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4043         if (!info)
4044                 return -ENOMEM;
4045
4046         spec->channels_info = info;
4047
4048         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4049         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4050
4051         for (i = 0; i < 14; i++) {
4052                 info[i].default_power1 = default_power1[i];
4053                 info[i].default_power2 = default_power2[i];
4054         }
4055
4056         if (spec->num_channels > 14) {
4057                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4058                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4059
4060                 for (i = 14; i < spec->num_channels; i++) {
4061                         info[i].default_power1 = default_power1[i];
4062                         info[i].default_power2 = default_power2[i];
4063                 }
4064         }
4065
4066         return 0;
4067 }
4068 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4069
4070 /*
4071  * IEEE80211 stack callback functions.
4072  */
4073 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4074                          u16 *iv16)
4075 {
4076         struct rt2x00_dev *rt2x00dev = hw->priv;
4077         struct mac_iveiv_entry iveiv_entry;
4078         u32 offset;
4079
4080         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4081         rt2800_register_multiread(rt2x00dev, offset,
4082                                       &iveiv_entry, sizeof(iveiv_entry));
4083
4084         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4085         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4086 }
4087 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4088
4089 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4090 {
4091         struct rt2x00_dev *rt2x00dev = hw->priv;
4092         u32 reg;
4093         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4094
4095         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4096         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4097         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4098
4099         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4100         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4101         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4102
4103         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4104         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4105         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4106
4107         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4108         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4109         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4110
4111         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4112         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4113         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4114
4115         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4116         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4117         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4118
4119         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4120         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4121         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4122
4123         return 0;
4124 }
4125 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4126
4127 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
4128                    const struct ieee80211_tx_queue_params *params)
4129 {
4130         struct rt2x00_dev *rt2x00dev = hw->priv;
4131         struct data_queue *queue;
4132         struct rt2x00_field32 field;
4133         int retval;
4134         u32 reg;
4135         u32 offset;
4136
4137         /*
4138          * First pass the configuration through rt2x00lib, that will
4139          * update the queue settings and validate the input. After that
4140          * we are free to update the registers based on the value
4141          * in the queue parameter.
4142          */
4143         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
4144         if (retval)
4145                 return retval;
4146
4147         /*
4148          * We only need to perform additional register initialization
4149          * for WMM queues/
4150          */
4151         if (queue_idx >= 4)
4152                 return 0;
4153
4154         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4155
4156         /* Update WMM TXOP register */
4157         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4158         field.bit_offset = (queue_idx & 1) * 16;
4159         field.bit_mask = 0xffff << field.bit_offset;
4160
4161         rt2800_register_read(rt2x00dev, offset, &reg);
4162         rt2x00_set_field32(&reg, field, queue->txop);
4163         rt2800_register_write(rt2x00dev, offset, reg);
4164
4165         /* Update WMM registers */
4166         field.bit_offset = queue_idx * 4;
4167         field.bit_mask = 0xf << field.bit_offset;
4168
4169         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4170         rt2x00_set_field32(&reg, field, queue->aifs);
4171         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4172
4173         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4174         rt2x00_set_field32(&reg, field, queue->cw_min);
4175         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4176
4177         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4178         rt2x00_set_field32(&reg, field, queue->cw_max);
4179         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4180
4181         /* Update EDCA registers */
4182         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4183
4184         rt2800_register_read(rt2x00dev, offset, &reg);
4185         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4186         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4187         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4188         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4189         rt2800_register_write(rt2x00dev, offset, reg);
4190
4191         return 0;
4192 }
4193 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4194
4195 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
4196 {
4197         struct rt2x00_dev *rt2x00dev = hw->priv;
4198         u64 tsf;
4199         u32 reg;
4200
4201         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4202         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4203         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4204         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4205
4206         return tsf;
4207 }
4208 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4209
4210 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4211                         enum ieee80211_ampdu_mlme_action action,
4212                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4213                         u8 buf_size)
4214 {
4215         int ret = 0;
4216
4217         switch (action) {
4218         case IEEE80211_AMPDU_RX_START:
4219         case IEEE80211_AMPDU_RX_STOP:
4220                 /*
4221                  * The hw itself takes care of setting up BlockAck mechanisms.
4222                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4223                  * agreement. Once that is done, the hw will BlockAck incoming
4224                  * AMPDUs without further setup.
4225                  */
4226                 break;
4227         case IEEE80211_AMPDU_TX_START:
4228                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4229                 break;
4230         case IEEE80211_AMPDU_TX_STOP:
4231                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4232                 break;
4233         case IEEE80211_AMPDU_TX_OPERATIONAL:
4234                 break;
4235         default:
4236                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4237         }
4238
4239         return ret;
4240 }
4241 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4242
4243 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4244                       struct survey_info *survey)
4245 {
4246         struct rt2x00_dev *rt2x00dev = hw->priv;
4247         struct ieee80211_conf *conf = &hw->conf;
4248         u32 idle, busy, busy_ext;
4249
4250         if (idx != 0)
4251                 return -ENOENT;
4252
4253         survey->channel = conf->channel;
4254
4255         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4256         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4257         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4258
4259         if (idle || busy) {
4260                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4261                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4262                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4263
4264                 survey->channel_time = (idle + busy) / 1000;
4265                 survey->channel_time_busy = busy / 1000;
4266                 survey->channel_time_ext_busy = busy_ext / 1000;
4267         }
4268
4269         return 0;
4270
4271 }
4272 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4273
4274 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4275 MODULE_VERSION(DRV_VERSION);
4276 MODULE_DESCRIPTION("Ralink RT2800 library");
4277 MODULE_LICENSE("GPL");