2 * Linux device driver for RTL8187
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
10 * The driver was extended to the RTL8187B in 2008 by:
11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
23 #include <linux/init.h>
24 #include <linux/usb.h>
25 #include <linux/delay.h>
26 #include <linux/etherdevice.h>
27 #include <linux/eeprom_93cx6.h>
28 #include <net/mac80211.h>
31 #include "rtl8187_rtl8225.h"
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
35 MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
36 MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
37 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
38 MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
39 MODULE_LICENSE("GPL");
41 static struct usb_device_id rtl8187_table[] __devinitdata = {
43 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
45 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
47 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
48 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
49 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
50 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
52 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
53 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
54 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
56 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
58 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
59 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
61 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
65 MODULE_DEVICE_TABLE(usb, rtl8187_table);
67 static const struct ieee80211_rate rtl818x_rates[] = {
68 { .bitrate = 10, .hw_value = 0, },
69 { .bitrate = 20, .hw_value = 1, },
70 { .bitrate = 55, .hw_value = 2, },
71 { .bitrate = 110, .hw_value = 3, },
72 { .bitrate = 60, .hw_value = 4, },
73 { .bitrate = 90, .hw_value = 5, },
74 { .bitrate = 120, .hw_value = 6, },
75 { .bitrate = 180, .hw_value = 7, },
76 { .bitrate = 240, .hw_value = 8, },
77 { .bitrate = 360, .hw_value = 9, },
78 { .bitrate = 480, .hw_value = 10, },
79 { .bitrate = 540, .hw_value = 11, },
82 static const struct ieee80211_channel rtl818x_channels[] = {
83 { .center_freq = 2412 },
84 { .center_freq = 2417 },
85 { .center_freq = 2422 },
86 { .center_freq = 2427 },
87 { .center_freq = 2432 },
88 { .center_freq = 2437 },
89 { .center_freq = 2442 },
90 { .center_freq = 2447 },
91 { .center_freq = 2452 },
92 { .center_freq = 2457 },
93 { .center_freq = 2462 },
94 { .center_freq = 2467 },
95 { .center_freq = 2472 },
96 { .center_freq = 2484 },
99 static void rtl8187_iowrite_async_cb(struct urb *urb)
104 static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
107 struct usb_ctrlrequest *dr;
109 struct rtl8187_async_write_data {
111 struct usb_ctrlrequest dr;
115 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
119 urb = usb_alloc_urb(0, GFP_ATOMIC);
127 dr->bRequestType = RTL8187_REQT_WRITE;
128 dr->bRequest = RTL8187_REQ_SET_REG;
131 dr->wLength = cpu_to_le16(len);
133 memcpy(buf, data, len);
135 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
136 (unsigned char *)dr, buf, len,
137 rtl8187_iowrite_async_cb, buf);
138 usb_anchor_urb(urb, &priv->anchored);
139 rc = usb_submit_urb(urb, GFP_ATOMIC);
142 usb_unanchor_urb(urb);
147 static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
148 __le32 *addr, u32 val)
150 __le32 buf = cpu_to_le32(val);
152 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
156 void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
158 struct rtl8187_priv *priv = dev->priv;
163 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
164 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
165 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
166 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
169 static void rtl8187_tx_cb(struct urb *urb)
171 struct sk_buff *skb = (struct sk_buff *)urb->context;
172 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
173 struct ieee80211_hw *hw = info->rate_driver_data[0];
174 struct rtl8187_priv *priv = hw->priv;
176 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
177 sizeof(struct rtl8187_tx_hdr));
178 ieee80211_tx_info_clear_status(info);
181 !(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
183 skb_queue_tail(&priv->b_tx_status.queue, skb);
185 /* queue is "full", discard last items */
186 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
187 struct sk_buff *old_skb;
189 dev_dbg(&priv->udev->dev,
190 "transmit status queue full\n");
192 old_skb = skb_dequeue(&priv->b_tx_status.queue);
193 ieee80211_tx_status_irqsafe(hw, old_skb);
196 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) && !urb->status)
197 info->flags |= IEEE80211_TX_STAT_ACK;
198 ieee80211_tx_status_irqsafe(hw, skb);
202 static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
204 struct rtl8187_priv *priv = dev->priv;
205 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
213 urb = usb_alloc_urb(0, GFP_ATOMIC);
220 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
222 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
223 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
224 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
225 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
226 flags |= RTL818X_TX_DESC_FLAG_RTS;
227 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
228 rts_dur = ieee80211_rts_duration(dev, priv->vif,
230 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
231 flags |= RTL818X_TX_DESC_FLAG_CTS;
232 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
235 if (!priv->is_rtl8187b) {
236 struct rtl8187_tx_hdr *hdr =
237 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
238 hdr->flags = cpu_to_le32(flags);
240 hdr->rts_duration = rts_dur;
241 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
246 /* fc needs to be calculated before skb_push() */
247 unsigned int epmap[4] = { 6, 7, 5, 4 };
248 struct ieee80211_hdr *tx_hdr =
249 (struct ieee80211_hdr *)(skb->data);
250 u16 fc = le16_to_cpu(tx_hdr->frame_control);
252 struct rtl8187b_tx_hdr *hdr =
253 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
254 struct ieee80211_rate *txrate =
255 ieee80211_get_tx_rate(dev, info);
256 memset(hdr, 0, sizeof(*hdr));
257 hdr->flags = cpu_to_le32(flags);
258 hdr->rts_duration = rts_dur;
259 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
261 ieee80211_generic_frame_duration(dev, priv->vif,
265 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
268 ep = epmap[skb_get_queue_mapping(skb)];
271 info->rate_driver_data[0] = dev;
272 info->rate_driver_data[1] = urb;
274 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
275 buf, skb->len, rtl8187_tx_cb, skb);
276 usb_anchor_urb(urb, &priv->anchored);
277 rc = usb_submit_urb(urb, GFP_ATOMIC);
279 usb_unanchor_urb(urb);
287 static void rtl8187_rx_cb(struct urb *urb)
289 struct sk_buff *skb = (struct sk_buff *)urb->context;
290 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
291 struct ieee80211_hw *dev = info->dev;
292 struct rtl8187_priv *priv = dev->priv;
293 struct ieee80211_rx_status rx_status = { 0 };
298 spin_lock(&priv->rx_queue.lock);
300 __skb_unlink(skb, &priv->rx_queue);
302 spin_unlock(&priv->rx_queue.lock);
305 spin_unlock(&priv->rx_queue.lock);
306 skb_put(skb, urb->actual_length);
308 if (unlikely(urb->status)) {
309 dev_kfree_skb_irq(skb);
313 if (!priv->is_rtl8187b) {
314 struct rtl8187_rx_hdr *hdr =
315 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
316 flags = le32_to_cpu(hdr->flags);
317 /* As with the RTL8187B below, the AGC is used to calculate
318 * signal strength and quality. In this case, the scaling
319 * constants are derived from the output of p54usb.
321 quality = 130 - ((41 * hdr->agc) >> 6);
322 signal = -4 - ((27 * hdr->agc) >> 6);
323 rx_status.antenna = (hdr->signal >> 7) & 1;
324 rx_status.mactime = le64_to_cpu(hdr->mac_time);
326 struct rtl8187b_rx_hdr *hdr =
327 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
328 /* The Realtek datasheet for the RTL8187B shows that the RX
329 * header contains the following quantities: signal quality,
330 * RSSI, AGC, the received power in dB, and the measured SNR.
331 * In testing, none of these quantities show qualitative
332 * agreement with AP signal strength, except for the AGC,
333 * which is inversely proportional to the strength of the
334 * signal. In the following, the quality and signal strength
335 * are derived from the AGC. The arbitrary scaling constants
336 * are chosen to make the results close to the values obtained
337 * for a BCM4312 using b43 as the driver. The noise is ignored
340 flags = le32_to_cpu(hdr->flags);
341 quality = 170 - hdr->agc;
342 signal = 14 - hdr->agc / 2;
343 rx_status.antenna = (hdr->rssi >> 7) & 1;
344 rx_status.mactime = le64_to_cpu(hdr->mac_time);
349 rx_status.qual = quality;
350 priv->quality = quality;
351 rx_status.signal = signal;
352 priv->signal = signal;
353 rate = (flags >> 20) & 0xF;
354 skb_trim(skb, flags & 0x0FFF);
355 rx_status.rate_idx = rate;
356 rx_status.freq = dev->conf.channel->center_freq;
357 rx_status.band = dev->conf.channel->band;
358 rx_status.flag |= RX_FLAG_TSFT;
359 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
360 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
361 ieee80211_rx_irqsafe(dev, skb, &rx_status);
363 skb = dev_alloc_skb(RTL8187_MAX_RX);
364 if (unlikely(!skb)) {
365 /* TODO check rx queue length and refill *somewhere* */
369 info = (struct rtl8187_rx_info *)skb->cb;
372 urb->transfer_buffer = skb_tail_pointer(skb);
374 skb_queue_tail(&priv->rx_queue, skb);
376 usb_anchor_urb(urb, &priv->anchored);
377 if (usb_submit_urb(urb, GFP_ATOMIC)) {
378 usb_unanchor_urb(urb);
379 skb_unlink(skb, &priv->rx_queue);
380 dev_kfree_skb_irq(skb);
384 static int rtl8187_init_urbs(struct ieee80211_hw *dev)
386 struct rtl8187_priv *priv = dev->priv;
387 struct urb *entry = NULL;
389 struct rtl8187_rx_info *info;
392 while (skb_queue_len(&priv->rx_queue) < 8) {
393 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
398 entry = usb_alloc_urb(0, GFP_KERNEL);
403 usb_fill_bulk_urb(entry, priv->udev,
404 usb_rcvbulkpipe(priv->udev,
405 priv->is_rtl8187b ? 3 : 1),
406 skb_tail_pointer(skb),
407 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
408 info = (struct rtl8187_rx_info *)skb->cb;
411 skb_queue_tail(&priv->rx_queue, skb);
412 usb_anchor_urb(entry, &priv->anchored);
413 ret = usb_submit_urb(entry, GFP_KERNEL);
415 skb_unlink(skb, &priv->rx_queue);
416 usb_unanchor_urb(entry);
426 usb_kill_anchored_urbs(&priv->anchored);
430 static void rtl8187b_status_cb(struct urb *urb)
432 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
433 struct rtl8187_priv *priv = hw->priv;
435 unsigned int cmd_type;
437 if (unlikely(urb->status))
441 * Read from status buffer:
443 * bits [30:31] = cmd type:
444 * - 0 indicates tx beacon interrupt
445 * - 1 indicates tx close descriptor
447 * In the case of tx beacon interrupt:
448 * [0:9] = Last Beacon CW
451 * [32:63] = Last Beacon TSF
453 * If it's tx close descriptor:
454 * [0:7] = Packet Retry Count
455 * [8:14] = RTS Retry Count
457 * [16:27] = Sequence No
461 * [32:47] = unused (reserved?)
462 * [48:63] = MAC Used Time
464 val = le64_to_cpu(priv->b_tx_status.buf);
466 cmd_type = (val >> 30) & 0x3;
468 unsigned int pkt_rc, seq_no;
471 struct ieee80211_hdr *ieee80211hdr;
475 tok = val & (1 << 15);
476 seq_no = (val >> 16) & 0xFFF;
478 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
479 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
480 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
483 * While testing, it was discovered that the seq_no
484 * doesn't actually contains the sequence number.
485 * Instead of returning just the 12 bits of sequence
486 * number, hardware is returning entire sequence control
487 * (fragment number plus sequence number) in a 12 bit
488 * only field overflowing after some time. As a
489 * workaround, just consider the lower bits, and expect
490 * it's unlikely we wrongly ack some sent data
492 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
496 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
497 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
499 __skb_unlink(skb, &priv->b_tx_status.queue);
501 info->flags |= IEEE80211_TX_STAT_ACK;
502 info->status.rates[0].count = pkt_rc + 1;
504 ieee80211_tx_status_irqsafe(hw, skb);
506 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
509 usb_anchor_urb(urb, &priv->anchored);
510 if (usb_submit_urb(urb, GFP_ATOMIC))
511 usb_unanchor_urb(urb);
514 static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
516 struct rtl8187_priv *priv = dev->priv;
520 entry = usb_alloc_urb(0, GFP_KERNEL);
524 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
525 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
526 rtl8187b_status_cb, dev);
528 usb_anchor_urb(entry, &priv->anchored);
529 ret = usb_submit_urb(entry, GFP_KERNEL);
531 usb_unanchor_urb(entry);
537 static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
539 struct rtl8187_priv *priv = dev->priv;
543 reg = rtl818x_ioread8(priv, &priv->map->CMD);
545 reg |= RTL818X_CMD_RESET;
546 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
551 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
557 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
561 /* reload registers from eeprom */
562 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
567 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
568 RTL818X_EEPROM_CMD_CONFIG))
573 printk(KERN_ERR "%s: eeprom reset timeout!\n",
574 wiphy_name(dev->wiphy));
581 static int rtl8187_init_hw(struct ieee80211_hw *dev)
583 struct rtl8187_priv *priv = dev->priv;
588 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
589 RTL818X_EEPROM_CMD_CONFIG);
590 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
591 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
592 RTL818X_CONFIG3_ANAPARAM_WRITE);
593 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
594 RTL8187_RTL8225_ANAPARAM_ON);
595 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
596 RTL8187_RTL8225_ANAPARAM2_ON);
597 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
598 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
599 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
600 RTL818X_EEPROM_CMD_NORMAL);
602 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
605 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
606 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
607 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
610 res = rtl8187_cmd_reset(dev);
614 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
615 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
616 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
617 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
618 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
619 RTL8187_RTL8225_ANAPARAM_ON);
620 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
621 RTL8187_RTL8225_ANAPARAM2_ON);
622 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
623 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
624 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
627 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
628 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
630 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
631 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
632 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
634 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
636 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
637 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
640 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
642 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
644 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
645 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
646 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
648 // TODO: set RESP_RATE and BRSR properly
649 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
650 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
653 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
654 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
655 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
656 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
657 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
658 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
659 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
660 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
661 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
662 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
665 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
666 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
667 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
668 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
669 RTL818X_EEPROM_CMD_CONFIG);
670 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
671 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
672 RTL818X_EEPROM_CMD_NORMAL);
673 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
678 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
679 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
680 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
681 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
682 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
683 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
684 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
689 static const u8 rtl8187b_reg_table[][3] = {
690 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
691 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
692 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
693 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
695 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
696 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
697 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
698 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
699 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
700 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
702 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
703 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
704 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
705 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
706 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
707 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
708 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
711 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
712 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
713 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
714 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
715 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
717 {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
718 {0x8E, 0x08, 0}, {0x8F, 0x00, 0}
721 static int rtl8187b_init_hw(struct ieee80211_hw *dev)
723 struct rtl8187_priv *priv = dev->priv;
727 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
728 RTL818X_EEPROM_CMD_CONFIG);
730 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
731 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
732 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
733 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
734 RTL8187B_RTL8225_ANAPARAM2_ON);
735 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
736 RTL8187B_RTL8225_ANAPARAM_ON);
737 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
738 RTL8187B_RTL8225_ANAPARAM3_ON);
740 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
741 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
742 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
743 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
745 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
746 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
747 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
749 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
750 RTL818X_EEPROM_CMD_NORMAL);
752 res = rtl8187_cmd_reset(dev);
756 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
757 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
758 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
759 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
760 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
761 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
762 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
763 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
765 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
766 reg = rtl818x_ioread8(priv, &priv->map->RATE_FALLBACK);
767 reg |= RTL818X_RATE_FALLBACK_ENABLE;
768 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, reg);
770 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
771 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
772 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
774 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
775 RTL818X_EEPROM_CMD_CONFIG);
776 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
777 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
778 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
779 RTL818X_EEPROM_CMD_NORMAL);
781 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
782 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
783 rtl818x_iowrite8_idx(priv,
785 (rtl8187b_reg_table[i][0] | 0xFF00),
786 rtl8187b_reg_table[i][1],
787 rtl8187b_reg_table[i][2]);
790 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
791 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
793 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
794 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
795 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
797 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
799 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
801 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
802 RTL818X_EEPROM_CMD_CONFIG);
803 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
804 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
805 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
806 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
807 RTL818X_EEPROM_CMD_NORMAL);
809 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
810 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
811 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
816 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
817 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
818 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
820 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
821 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
822 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
823 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
824 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
825 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
826 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
828 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
829 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
830 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
831 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
832 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
833 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
834 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
835 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
836 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
837 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
838 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
839 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
840 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
842 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
844 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
846 priv->slot_time = 0x9;
847 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
848 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
849 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
850 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
851 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
856 static int rtl8187_start(struct ieee80211_hw *dev)
858 struct rtl8187_priv *priv = dev->priv;
862 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
863 rtl8187b_init_hw(dev);
867 mutex_lock(&priv->conf_mutex);
869 init_usb_anchor(&priv->anchored);
871 if (priv->is_rtl8187b) {
872 reg = RTL818X_RX_CONF_MGMT |
873 RTL818X_RX_CONF_DATA |
874 RTL818X_RX_CONF_BROADCAST |
875 RTL818X_RX_CONF_NICMAC |
876 RTL818X_RX_CONF_BSSID |
877 (7 << 13 /* RX FIFO threshold NONE */) |
878 (7 << 10 /* MAX RX DMA */) |
879 RTL818X_RX_CONF_RX_AUTORESETPHY |
880 RTL818X_RX_CONF_ONLYERLPKT |
881 RTL818X_RX_CONF_MULTICAST;
883 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
885 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
886 RTL818X_TX_CONF_HW_SEQNUM |
887 RTL818X_TX_CONF_DISREQQSIZE |
888 (7 << 8 /* short retry limit */) |
889 (7 << 0 /* long retry limit */) |
890 (7 << 21 /* MAX TX DMA */));
891 rtl8187_init_urbs(dev);
892 rtl8187b_init_status_urb(dev);
893 mutex_unlock(&priv->conf_mutex);
897 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
899 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
900 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
902 rtl8187_init_urbs(dev);
904 reg = RTL818X_RX_CONF_ONLYERLPKT |
905 RTL818X_RX_CONF_RX_AUTORESETPHY |
906 RTL818X_RX_CONF_BSSID |
907 RTL818X_RX_CONF_MGMT |
908 RTL818X_RX_CONF_DATA |
909 (7 << 13 /* RX FIFO threshold NONE */) |
910 (7 << 10 /* MAX RX DMA */) |
911 RTL818X_RX_CONF_BROADCAST |
912 RTL818X_RX_CONF_NICMAC;
915 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
917 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
918 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
919 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
920 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
922 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
923 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
924 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
925 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
926 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
928 reg = RTL818X_TX_CONF_CW_MIN |
929 (7 << 21 /* MAX TX DMA */) |
930 RTL818X_TX_CONF_NO_ICV;
931 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
933 reg = rtl818x_ioread8(priv, &priv->map->CMD);
934 reg |= RTL818X_CMD_TX_ENABLE;
935 reg |= RTL818X_CMD_RX_ENABLE;
936 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
937 mutex_unlock(&priv->conf_mutex);
942 static void rtl8187_stop(struct ieee80211_hw *dev)
944 struct rtl8187_priv *priv = dev->priv;
945 struct rtl8187_rx_info *info;
949 mutex_lock(&priv->conf_mutex);
950 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
952 reg = rtl818x_ioread8(priv, &priv->map->CMD);
953 reg &= ~RTL818X_CMD_TX_ENABLE;
954 reg &= ~RTL818X_CMD_RX_ENABLE;
955 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
959 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
960 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
961 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
962 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
964 while ((skb = skb_dequeue(&priv->rx_queue))) {
965 info = (struct rtl8187_rx_info *)skb->cb;
968 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
969 dev_kfree_skb_any(skb);
971 usb_kill_anchored_urbs(&priv->anchored);
972 mutex_unlock(&priv->conf_mutex);
975 static int rtl8187_add_interface(struct ieee80211_hw *dev,
976 struct ieee80211_if_init_conf *conf)
978 struct rtl8187_priv *priv = dev->priv;
981 if (priv->mode != NL80211_IFTYPE_MONITOR)
984 switch (conf->type) {
985 case NL80211_IFTYPE_STATION:
986 priv->mode = conf->type;
992 mutex_lock(&priv->conf_mutex);
993 priv->vif = conf->vif;
995 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
996 for (i = 0; i < ETH_ALEN; i++)
997 rtl818x_iowrite8(priv, &priv->map->MAC[i],
998 ((u8 *)conf->mac_addr)[i]);
999 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1001 mutex_unlock(&priv->conf_mutex);
1005 static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1006 struct ieee80211_if_init_conf *conf)
1008 struct rtl8187_priv *priv = dev->priv;
1009 mutex_lock(&priv->conf_mutex);
1010 priv->mode = NL80211_IFTYPE_MONITOR;
1012 mutex_unlock(&priv->conf_mutex);
1015 static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
1017 struct rtl8187_priv *priv = dev->priv;
1018 struct ieee80211_conf *conf = &dev->conf;
1021 mutex_lock(&priv->conf_mutex);
1022 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1023 /* Enable TX loopback on MAC level to avoid TX during channel
1024 * changes, as this has be seen to causes problems and the
1025 * card will stop work until next reset
1027 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1028 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
1029 priv->rf->set_chan(dev, conf);
1031 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1033 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1034 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1035 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1036 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
1037 mutex_unlock(&priv->conf_mutex);
1041 static int rtl8187_config_interface(struct ieee80211_hw *dev,
1042 struct ieee80211_vif *vif,
1043 struct ieee80211_if_conf *conf)
1045 struct rtl8187_priv *priv = dev->priv;
1049 mutex_lock(&priv->conf_mutex);
1050 for (i = 0; i < ETH_ALEN; i++)
1051 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
1053 if (is_valid_ether_addr(conf->bssid)) {
1054 reg = RTL818X_MSR_INFRA;
1055 if (priv->is_rtl8187b)
1056 reg |= RTL818X_MSR_ENEDCA;
1057 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1059 reg = RTL818X_MSR_NO_LINK;
1060 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1063 mutex_unlock(&priv->conf_mutex);
1068 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1069 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1071 static __le32 *rtl8187b_ac_addr[4] = {
1072 (__le32 *) 0xFFF0, /* AC_VO */
1073 (__le32 *) 0xFFF4, /* AC_VI */
1074 (__le32 *) 0xFFFC, /* AC_BK */
1075 (__le32 *) 0xFFF8, /* AC_BE */
1078 #define SIFS_TIME 0xa
1080 static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1081 bool use_short_preamble)
1083 if (priv->is_rtl8187b) {
1088 if (use_short_slot) {
1089 priv->slot_time = 0x9;
1093 priv->slot_time = 0x14;
1097 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1098 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1099 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1102 * BRSR+1 on 8187B is in fact EIFS register
1103 * Value in units of 4 us
1105 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1108 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1109 * register. In units of 4 us like eifs register
1110 * ack_timeout = ack duration + plcp + difs + preamble
1112 ack_timeout = 112 + 48 + difs;
1113 if (use_short_preamble)
1117 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1118 DIV_ROUND_UP(ack_timeout, 4));
1120 for (queue = 0; queue < 4; queue++)
1121 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1122 priv->aifsn[queue] * priv->slot_time +
1125 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1126 if (use_short_slot) {
1127 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1128 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1129 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
1131 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1132 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1133 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
1138 static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1139 struct ieee80211_vif *vif,
1140 struct ieee80211_bss_conf *info,
1143 struct rtl8187_priv *priv = dev->priv;
1145 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1146 rtl8187_conf_erp(priv, info->use_short_slot,
1147 info->use_short_preamble);
1150 static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1151 unsigned int changed_flags,
1152 unsigned int *total_flags,
1153 int mc_count, struct dev_addr_list *mclist)
1155 struct rtl8187_priv *priv = dev->priv;
1157 if (changed_flags & FIF_FCSFAIL)
1158 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1159 if (changed_flags & FIF_CONTROL)
1160 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1161 if (changed_flags & FIF_OTHER_BSS)
1162 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1163 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
1164 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1166 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1170 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1171 *total_flags |= FIF_FCSFAIL;
1172 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1173 *total_flags |= FIF_CONTROL;
1174 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1175 *total_flags |= FIF_OTHER_BSS;
1176 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1177 *total_flags |= FIF_ALLMULTI;
1179 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1182 static int rtl8187_conf_tx(struct ieee80211_hw *dev, u16 queue,
1183 const struct ieee80211_tx_queue_params *params)
1185 struct rtl8187_priv *priv = dev->priv;
1191 cw_min = fls(params->cw_min);
1192 cw_max = fls(params->cw_max);
1194 if (priv->is_rtl8187b) {
1195 priv->aifsn[queue] = params->aifs;
1198 * This is the structure of AC_*_PARAM registers in 8187B:
1199 * - TXOP limit field, bit offset = 16
1200 * - ECWmax, bit offset = 12
1201 * - ECWmin, bit offset = 8
1202 * - AIFS, bit offset = 0
1204 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1205 (params->txop << 16) | (cw_max << 12) |
1206 (cw_min << 8) | (params->aifs *
1207 priv->slot_time + SIFS_TIME));
1212 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1213 cw_min | (cw_max << 4));
1218 static const struct ieee80211_ops rtl8187_ops = {
1220 .start = rtl8187_start,
1221 .stop = rtl8187_stop,
1222 .add_interface = rtl8187_add_interface,
1223 .remove_interface = rtl8187_remove_interface,
1224 .config = rtl8187_config,
1225 .config_interface = rtl8187_config_interface,
1226 .bss_info_changed = rtl8187_bss_info_changed,
1227 .configure_filter = rtl8187_configure_filter,
1228 .conf_tx = rtl8187_conf_tx
1231 static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1233 struct ieee80211_hw *dev = eeprom->data;
1234 struct rtl8187_priv *priv = dev->priv;
1235 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1237 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1238 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1239 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1240 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1243 static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1245 struct ieee80211_hw *dev = eeprom->data;
1246 struct rtl8187_priv *priv = dev->priv;
1247 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1249 if (eeprom->reg_data_in)
1250 reg |= RTL818X_EEPROM_CMD_WRITE;
1251 if (eeprom->reg_data_out)
1252 reg |= RTL818X_EEPROM_CMD_READ;
1253 if (eeprom->reg_data_clock)
1254 reg |= RTL818X_EEPROM_CMD_CK;
1255 if (eeprom->reg_chip_select)
1256 reg |= RTL818X_EEPROM_CMD_CS;
1258 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1262 static int __devinit rtl8187_probe(struct usb_interface *intf,
1263 const struct usb_device_id *id)
1265 struct usb_device *udev = interface_to_usbdev(intf);
1266 struct ieee80211_hw *dev;
1267 struct rtl8187_priv *priv;
1268 struct eeprom_93cx6 eeprom;
1269 struct ieee80211_channel *channel;
1270 const char *chip_name;
1274 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1276 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1281 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
1283 SET_IEEE80211_DEV(dev, &intf->dev);
1284 usb_set_intfdata(intf, dev);
1289 skb_queue_head_init(&priv->rx_queue);
1291 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1292 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1294 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1295 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1296 priv->map = (struct rtl818x_csr *)0xFF00;
1298 priv->band.band = IEEE80211_BAND_2GHZ;
1299 priv->band.channels = priv->channels;
1300 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1301 priv->band.bitrates = priv->rates;
1302 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1303 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1306 priv->mode = NL80211_IFTYPE_MONITOR;
1307 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1308 IEEE80211_HW_SIGNAL_DBM |
1309 IEEE80211_HW_RX_INCLUDES_FCS;
1312 eeprom.register_read = rtl8187_eeprom_register_read;
1313 eeprom.register_write = rtl8187_eeprom_register_write;
1314 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1315 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1317 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1319 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1322 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1323 (__le16 __force *)dev->wiphy->perm_addr, 3);
1324 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1325 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1326 "generated MAC address\n");
1327 random_ether_addr(dev->wiphy->perm_addr);
1330 channel = priv->channels;
1331 for (i = 0; i < 3; i++) {
1332 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1334 (*channel++).hw_value = txpwr & 0xFF;
1335 (*channel++).hw_value = txpwr >> 8;
1337 for (i = 0; i < 2; i++) {
1338 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1340 (*channel++).hw_value = txpwr & 0xFF;
1341 (*channel++).hw_value = txpwr >> 8;
1344 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1347 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1348 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
1349 /* 0 means asic B-cut, we should use SW 3 wire
1350 * bit-by-bit banging for radio. 1 means we can use
1351 * USB specific request to write radio registers */
1352 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
1353 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
1354 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1356 if (!priv->is_rtl8187b) {
1358 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1359 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1361 case RTL818X_TX_CONF_R8187vD_B:
1362 /* Some RTL8187B devices have a USB ID of 0x8187
1363 * detect them here */
1364 chip_name = "RTL8187BvB(early)";
1365 priv->is_rtl8187b = 1;
1366 priv->hw_rev = RTL8187BvB;
1368 case RTL818X_TX_CONF_R8187vD:
1369 chip_name = "RTL8187vD";
1372 chip_name = "RTL8187vB (default)";
1376 * Force USB request to write radio registers for 8187B, Realtek
1377 * only uses it in their sources
1379 /*if (priv->asic_rev == 0) {
1380 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1381 "requests to write to radio registers\n");
1384 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1385 case RTL818X_R8187B_B:
1386 chip_name = "RTL8187BvB";
1387 priv->hw_rev = RTL8187BvB;
1389 case RTL818X_R8187B_D:
1390 chip_name = "RTL8187BvD";
1391 priv->hw_rev = RTL8187BvD;
1393 case RTL818X_R8187B_E:
1394 chip_name = "RTL8187BvE";
1395 priv->hw_rev = RTL8187BvE;
1398 chip_name = "RTL8187BvB (default)";
1399 priv->hw_rev = RTL8187BvB;
1403 if (!priv->is_rtl8187b) {
1404 for (i = 0; i < 2; i++) {
1405 eeprom_93cx6_read(&eeprom,
1406 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1408 (*channel++).hw_value = txpwr & 0xFF;
1409 (*channel++).hw_value = txpwr >> 8;
1412 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1414 (*channel++).hw_value = txpwr & 0xFF;
1416 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1417 (*channel++).hw_value = txpwr & 0xFF;
1419 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1420 (*channel++).hw_value = txpwr & 0xFF;
1421 (*channel++).hw_value = txpwr >> 8;
1424 if (priv->is_rtl8187b)
1425 printk(KERN_WARNING "rtl8187: 8187B chip detected.\n");
1428 * XXX: Once this driver supports anything that requires
1429 * beacons it must implement IEEE80211_TX_CTL_ASSIGN_SEQ.
1431 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1433 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1434 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1437 priv->rf = rtl8187_detect_rf(dev);
1438 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1439 sizeof(struct rtl8187_tx_hdr) :
1440 sizeof(struct rtl8187b_tx_hdr);
1441 if (!priv->is_rtl8187b)
1446 err = ieee80211_register_hw(dev);
1448 printk(KERN_ERR "rtl8187: Cannot register device\n");
1451 mutex_init(&priv->conf_mutex);
1452 skb_queue_head_init(&priv->b_tx_status.queue);
1454 printk(KERN_INFO "%s: hwaddr %pM, %s V%d + %s\n",
1455 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
1456 chip_name, priv->asic_rev, priv->rf->name);
1461 ieee80211_free_hw(dev);
1462 usb_set_intfdata(intf, NULL);
1467 static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1469 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1470 struct rtl8187_priv *priv;
1475 ieee80211_unregister_hw(dev);
1478 usb_put_dev(interface_to_usbdev(intf));
1479 ieee80211_free_hw(dev);
1482 static struct usb_driver rtl8187_driver = {
1483 .name = KBUILD_MODNAME,
1484 .id_table = rtl8187_table,
1485 .probe = rtl8187_probe,
1486 .disconnect = __devexit_p(rtl8187_disconnect),
1489 static int __init rtl8187_init(void)
1491 return usb_register(&rtl8187_driver);
1494 static void __exit rtl8187_exit(void)
1496 usb_deregister(&rtl8187_driver);
1499 module_init(rtl8187_init);
1500 module_exit(rtl8187_exit);