drivers/net/wireless/rtlwifi/rtl8192cu/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include "../wifi.h"
  33 #include "../efuse.h"
  34 #include "../base.h"
  35 #include "../cam.h"
  36 #include "../ps.h"
  37 #include "../usb.h"
  38 #include "reg.h"
  39 #include "def.h"
  40 #include "phy.h"
  41 #include "mac.h"
  42 #include "dm.h"
  43 #include "hw.h"
  44 #include "../rtl8192ce/hw.h"
  45 #include "trx.h"
  46 #include "led.h"
  47 #include "table.h"
  48
  49 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
  50 {
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  53         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
  54
  55         rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
  56         rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
  57         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  58                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  59                         RTL8192CUPHY_REG_Array_PG_HPLength;
  60                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  61                         RTL8192CUPHY_REG_Array_PG_HP;
  62         } else {
  63                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  64                         RTL8192CUPHY_REG_ARRAY_PGLENGTH;
  65                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  66                         RTL8192CUPHY_REG_ARRAY_PG;
  67         }
  68         /* 2T */
  69         rtlphy->hwparam_tables[PHY_REG_2T].length =
  70                         RTL8192CUPHY_REG_2TARRAY_LENGTH;
  71         rtlphy->hwparam_tables[PHY_REG_2T].pdata =
  72                         RTL8192CUPHY_REG_2TARRAY;
  73         rtlphy->hwparam_tables[RADIOA_2T].length =
  74                         RTL8192CURADIOA_2TARRAYLENGTH;
  75         rtlphy->hwparam_tables[RADIOA_2T].pdata =
  76                         RTL8192CURADIOA_2TARRAY;
  77         rtlphy->hwparam_tables[RADIOB_2T].length =
  78                         RTL8192CURADIOB_2TARRAYLENGTH;
  79         rtlphy->hwparam_tables[RADIOB_2T].pdata =
  80                         RTL8192CU_RADIOB_2TARRAY;
  81         rtlphy->hwparam_tables[AGCTAB_2T].length =
  82                         RTL8192CUAGCTAB_2TARRAYLENGTH;
  83         rtlphy->hwparam_tables[AGCTAB_2T].pdata =
  84                         RTL8192CUAGCTAB_2TARRAY;
  85         /* 1T */
  86         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  87                 rtlphy->hwparam_tables[PHY_REG_1T].length =
  88                         RTL8192CUPHY_REG_1T_HPArrayLength;
  89                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
  90                         RTL8192CUPHY_REG_1T_HPArray;
  91                 rtlphy->hwparam_tables[RADIOA_1T].length =
  92                         RTL8192CURadioA_1T_HPArrayLength;
  93                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
  94                         RTL8192CURadioA_1T_HPArray;
  95                 rtlphy->hwparam_tables[RADIOB_1T].length =
  96                         RTL8192CURADIOB_1TARRAYLENGTH;
  97                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
  98                         RTL8192CU_RADIOB_1TARRAY;
  99                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 100                         RTL8192CUAGCTAB_1T_HPArrayLength;
 101                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 102                         Rtl8192CUAGCTAB_1T_HPArray;
 103         } else {
 104                 rtlphy->hwparam_tables[PHY_REG_1T].length =
 105                          RTL8192CUPHY_REG_1TARRAY_LENGTH;
 106                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
 107                         RTL8192CUPHY_REG_1TARRAY;
 108                 rtlphy->hwparam_tables[RADIOA_1T].length =
 109                         RTL8192CURADIOA_1TARRAYLENGTH;
 110                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
 111                         RTL8192CU_RADIOA_1TARRAY;
 112                 rtlphy->hwparam_tables[RADIOB_1T].length =
 113                         RTL8192CURADIOB_1TARRAYLENGTH;
 114                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
 115                         RTL8192CU_RADIOB_1TARRAY;
 116                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 117                         RTL8192CUAGCTAB_1TARRAYLENGTH;
 118                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 119                         RTL8192CUAGCTAB_1TARRAY;
 120         }
 121 }
 122
 123 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
 124                                                  bool autoload_fail,
 125                                                  u8 *hwinfo)
 126 {
 127         struct rtl_priv *rtlpriv = rtl_priv(hw);
 128         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 129         u8 rf_path, index, tempval;
 130         u16 i;
 131
 132         for (rf_path = 0; rf_path < 2; rf_path++) {
 133                 for (i = 0; i < 3; i++) {
 134                         if (!autoload_fail) {
 135                                 rtlefuse->
 136                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 137                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
 138                                 rtlefuse->
 139                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 140                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
 141                                            i];
 142                         } else {
 143                                 rtlefuse->
 144                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 145                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 146                                 rtlefuse->
 147                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 148                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 149                         }
 150                 }
 151         }
 152         for (i = 0; i < 3; i++) {
 153                 if (!autoload_fail)
 154                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
 155                 else
 156                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
 157                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
 158                     (tempval & 0xf);
 159                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
 160                     ((tempval & 0xf0) >> 4);
 161         }
 162         for (rf_path = 0; rf_path < 2; rf_path++)
 163                 for (i = 0; i < 3; i++)
 164                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 165                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
 166                                  i, rtlefuse->
 167                                  eeprom_chnlarea_txpwr_cck[rf_path][i]));
 168         for (rf_path = 0; rf_path < 2; rf_path++)
 169                 for (i = 0; i < 3; i++)
 170                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 171                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
 172                                  rf_path, i,
 173                                  rtlefuse->
 174                                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
 175         for (rf_path = 0; rf_path < 2; rf_path++)
 176                 for (i = 0; i < 3; i++)
 177                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 178                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
 179                                  rf_path, i,
 180                                  rtlefuse->
 181                                  eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
 182                                  [i]));
 183         for (rf_path = 0; rf_path < 2; rf_path++) {
 184                 for (i = 0; i < 14; i++) {
 185                         index = _rtl92c_get_chnl_group((u8) i);
 186                         rtlefuse->txpwrlevel_cck[rf_path][i] =
 187                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
 188                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
 189                             rtlefuse->
 190                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
 191                         if ((rtlefuse->
 192                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
 193                              rtlefuse->
 194                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
 195                             > 0) {
 196                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
 197                                     rtlefuse->
 198                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
 199                                     [index] - rtlefuse->
 200                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
 201                                     [index];
 202                         } else {
 203                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
 204                         }
 205                 }
 206                 for (i = 0; i < 14; i++) {
 207                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 208                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
 209                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
 210                                  rtlefuse->txpwrlevel_cck[rf_path][i],
 211                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
 212                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
 213                 }
 214         }
 215         for (i = 0; i < 3; i++) {
 216                 if (!autoload_fail) {
 217                         rtlefuse->eeprom_pwrlimit_ht40[i] =
 218                             hwinfo[EEPROM_TXPWR_GROUP + i];
 219                         rtlefuse->eeprom_pwrlimit_ht20[i] =
 220                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
 221                 } else {
 222                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
 223                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
 224                 }
 225         }
 226         for (rf_path = 0; rf_path < 2; rf_path++) {
 227                 for (i = 0; i < 14; i++) {
 228                         index = _rtl92c_get_chnl_group((u8) i);
 229                         if (rf_path == RF90_PATH_A) {
 230                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 231                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
 232                                      & 0xf);
 233                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 234                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
 235                                      & 0xf);
 236                         } else if (rf_path == RF90_PATH_B) {
 237                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 238                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
 239                                       & 0xf0) >> 4);
 240                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 241                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
 242                                       & 0xf0) >> 4);
 243                         }
 244                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 245                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
 246                                  rf_path, i,
 247                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
 248                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 249                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
 250                                  rf_path, i,
 251                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
 252                 }
 253         }
 254         for (i = 0; i < 14; i++) {
 255                 index = _rtl92c_get_chnl_group((u8) i);
 256                 if (!autoload_fail)
 257                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
 258                 else
 259                         tempval = EEPROM_DEFAULT_HT20_DIFF;
 260                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
 261                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
 262                     ((tempval >> 4) & 0xF);
 263                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
 264                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
 265                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
 266                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
 267                 index = _rtl92c_get_chnl_group((u8) i);
 268                 if (!autoload_fail)
 269                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
 270                 else
 271                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
 272                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
 273                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
 274                     ((tempval >> 4) & 0xF);
 275         }
 276         rtlefuse->legacy_ht_txpowerdiff =
 277             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
 278         for (i = 0; i < 14; i++)
 279                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 280                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
 281                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
 282         for (i = 0; i < 14; i++)
 283                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 284                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
 285                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
 286         for (i = 0; i < 14; i++)
 287                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 288                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
 289                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
 290         for (i = 0; i < 14; i++)
 291                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 292                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
 293                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
 294         if (!autoload_fail)
 295                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
 296         else
 297                 rtlefuse->eeprom_regulatory = 0;
 298         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 299                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
 300         if (!autoload_fail) {
 301                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
 302                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
 303         } else {
 304                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
 305                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
 306         }
 307         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 308                 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
 309                  rtlefuse->eeprom_tssi[RF90_PATH_A],
 310                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
 311         if (!autoload_fail)
 312                 tempval = hwinfo[EEPROM_THERMAL_METER];
 313         else
 314                 tempval = EEPROM_DEFAULT_THERMALMETER;
 315         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
 316         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
 317             rtlefuse->eeprom_thermalmeter > 0x1c)
 318                 rtlefuse->eeprom_thermalmeter = 0x12;
 319         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
 320                 rtlefuse->apk_thermalmeterignore = true;
 321         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
 322         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 323                 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
 324 }
 325
 326 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
 327 {
 328         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 329         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 330         u8 boardType;
 331
 332         if (IS_NORMAL_CHIP(rtlhal->version)) {
 333                 boardType = ((contents[EEPROM_RF_OPT1]) &
 334                             BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
 335         } else {
 336                 boardType = contents[EEPROM_RF_OPT4];
 337                 boardType &= BOARD_TYPE_TEST_MASK;
 338         }
 339         rtlefuse->board_type = boardType;
 340         if (IS_HIGHT_PA(rtlefuse->board_type))
 341                 rtlefuse->external_pa = 1;
 342         pr_info("Board Type %x\n", rtlefuse->board_type);
 343
 344 #ifdef CONFIG_ANTENNA_DIVERSITY
 345         /* Antenna Diversity setting. */
 346         if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
 347                 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
 348         else
 349                 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
 350
 351         pr_info("Antenna Config %x\n", rtl_efuse->antenna_cfg);
 352 #endif
 353 }
 354
 355 #ifdef CONFIG_BT_COEXIST
 356 static void _update_bt_param(_adapter *padapter)
 357 {
 358         struct btcoexist_priv    *pbtpriv = &(padapter->halpriv.bt_coexist);
 359         struct registry_priv    *registry_par = &padapter->registrypriv;
 360         if (2 != registry_par->bt_iso) {
 361                 /* 0:Low, 1:High, 2:From Efuse */
 362                 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
 363         }
 364         if (registry_par->bt_sco == 1) {
 365                 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
 366                  * 5.OtherBusy */
 367                 pbtpriv->BT_Service = BT_OtherAction;
 368         } else if (registry_par->bt_sco == 2) {
 369                 pbtpriv->BT_Service = BT_SCO;
 370         } else if (registry_par->bt_sco == 4) {
 371                 pbtpriv->BT_Service = BT_Busy;
 372         } else if (registry_par->bt_sco == 5) {
 373                 pbtpriv->BT_Service = BT_OtherBusy;
 374         } else {
 375                 pbtpriv->BT_Service = BT_Idle;
 376         }
 377         pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
 378         pbtpriv->bCOBT = _TRUE;
 379         pbtpriv->BtEdcaUL = 0;
 380         pbtpriv->BtEdcaDL = 0;
 381         pbtpriv->BtRssiState = 0xff;
 382         pbtpriv->bInitSet = _FALSE;
 383         pbtpriv->bBTBusyTraffic = _FALSE;
 384         pbtpriv->bBTTrafficModeSet = _FALSE;
 385         pbtpriv->bBTNonTrafficModeSet = _FALSE;
 386         pbtpriv->CurrentState = 0;
 387         pbtpriv->PreviousState = 0;
 388         pr_info("BT Coexistance = %s\n",
 389                 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
 390         if (pbtpriv->BT_Coexist) {
 391                 if (pbtpriv->BT_Ant_Num == Ant_x2)
 392                         pr_info("BlueTooth BT_Ant_Num = Antx2\n");
 393                 else if (pbtpriv->BT_Ant_Num == Ant_x1)
 394                         pr_info("BlueTooth BT_Ant_Num = Antx1\n");
 395                 switch (pbtpriv->BT_CoexistType) {
 396                 case BT_2Wire:
 397                         pr_info("BlueTooth BT_CoexistType = BT_2Wire\n");
 398                         break;
 399                 case BT_ISSC_3Wire:
 400                         pr_info("BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
 401                         break;
 402                 case BT_Accel:
 403                         pr_info("BlueTooth BT_CoexistType = BT_Accel\n");
 404                         break;
 405                 case BT_CSR_BC4:
 406                         pr_info("BlueTooth BT_CoexistType = BT_CSR_BC4\n");
 407                         break;
 408                 case BT_CSR_BC8:
 409                         pr_info("BlueTooth BT_CoexistType = BT_CSR_BC8\n");
 410                         break;
 411                 case BT_RTL8756:
 412                         pr_info("BlueTooth BT_CoexistType = BT_RTL8756\n");
 413                         break;
 414                 default:
 415                         pr_info("BlueTooth BT_CoexistType = Unknown\n");
 416                         break;
 417                 }
 418                 pr_info("BlueTooth BT_Ant_isolation = %d\n",
 419                         pbtpriv->BT_Ant_isolation);
 420                 switch (pbtpriv->BT_Service) {
 421                 case BT_OtherAction:
 422                         pr_info("BlueTooth BT_Service = BT_OtherAction\n");
 423                         break;
 424                 case BT_SCO:
 425                         pr_info("BlueTooth BT_Service = BT_SCO\n");
 426                         break;
 427                 case BT_Busy:
 428                         pr_info("BlueTooth BT_Service = BT_Busy\n");
 429                         break;
 430                 case BT_OtherBusy:
 431                         pr_info("BlueTooth BT_Service = BT_OtherBusy\n");
 432                         break;
 433                 default:
 434                         pr_info("BlueTooth BT_Service = BT_Idle\n");
 435                         break;
 436                 }
 437                 pr_info("BT_RadioSharedType = 0x%x\n",
 438                         pbtpriv->BT_RadioSharedType);
 439         }
 440 }
 441
 442 #define GET_BT_COEXIST(priv) (&priv->bt_coexist)
 443
 444 static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
 445                                                 u8 *contents,
 446                                                 bool bautoloadfailed);
 447 {
 448         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 449         bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
 450         struct btcoexist_priv    *pbtpriv = &pHalData->bt_coexist;
 451         u8      rf_opt4;
 452
 453         _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
 454         if (AutoloadFail) {
 455                 pbtpriv->BT_Coexist = _FALSE;
 456                 pbtpriv->BT_CoexistType = BT_2Wire;
 457                 pbtpriv->BT_Ant_Num = Ant_x2;
 458                 pbtpriv->BT_Ant_isolation = 0;
 459                 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
 460                 return;
 461         }
 462         if (isNormal) {
 463                 if (pHalData->BoardType == BOARD_USB_COMBO)
 464                         pbtpriv->BT_Coexist = _TRUE;
 465                 else
 466                         pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
 467                                               0x20) >> 5); /* bit[5] */
 468                 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
 469                 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
 470                 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
 471                 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
 472                 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
 473         } else {
 474                 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
 475                                        _TRUE : _FALSE;
 476         }
 477         _update_bt_param(Adapter);
 478 }
 479 #endif
 480
 481 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
 482 {
 483         struct rtl_priv *rtlpriv = rtl_priv(hw);
 484         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 485         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 486         u16 i, usvalue;
 487         u8 hwinfo[HWSET_MAX_SIZE] = {0};
 488         u16 eeprom_id;
 489
 490         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 491                 rtl_efuse_shadow_map_update(hw);
 492                 memcpy((void *)hwinfo,
 493                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
 494                        HWSET_MAX_SIZE);
 495         } else if (rtlefuse->epromtype == EEPROM_93C46) {
 496                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 497                          "RTL819X Not boot from eeprom, check it !!\n");
 498         }
 499         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP",
 500                       hwinfo, HWSET_MAX_SIZE);
 501         eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
 502         if (eeprom_id != RTL8190_EEPROM_ID) {
 503                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 504                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
 505                 rtlefuse->autoload_failflag = true;
 506         } else {
 507                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
 508                 rtlefuse->autoload_failflag = false;
 509         }
 510         if (rtlefuse->autoload_failflag)
 511                 return;
 512         for (i = 0; i < 6; i += 2) {
 513                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
 514                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
 515         }
 516         pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
 517         _rtl92cu_read_txpower_info_from_hwpg(hw,
 518                                            rtlefuse->autoload_failflag, hwinfo);
 519         rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
 520         rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
 521         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, " VID = 0x%02x PID = 0x%02x\n",
 522                  rtlefuse->eeprom_vid, rtlefuse->eeprom_did);
 523         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
 524         rtlefuse->eeprom_version =
 525                          le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
 526         rtlefuse->txpwr_fromeprom = true;
 527         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
 528         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
 529                  rtlefuse->eeprom_oemid);
 530         if (rtlhal->oem_id == RT_CID_DEFAULT) {
 531                 switch (rtlefuse->eeprom_oemid) {
 532                 case EEPROM_CID_DEFAULT:
 533                         if (rtlefuse->eeprom_did == 0x8176) {
 534                                 if ((rtlefuse->eeprom_svid == 0x103C &&
 535                                      rtlefuse->eeprom_smid == 0x1629))
 536                                         rtlhal->oem_id = RT_CID_819x_HP;
 537                                 else
 538                                         rtlhal->oem_id = RT_CID_DEFAULT;
 539                         } else {
 540                                 rtlhal->oem_id = RT_CID_DEFAULT;
 541                         }
 542                         break;
 543                 case EEPROM_CID_TOSHIBA:
 544                         rtlhal->oem_id = RT_CID_TOSHIBA;
 545                         break;
 546                 case EEPROM_CID_QMI:
 547                         rtlhal->oem_id = RT_CID_819x_QMI;
 548                         break;
 549                 case EEPROM_CID_WHQL:
 550                 default:
 551                         rtlhal->oem_id = RT_CID_DEFAULT;
 552                         break;
 553                 }
 554         }
 555         _rtl92cu_read_board_type(hw, hwinfo);
 556 #ifdef CONFIG_BT_COEXIST
 557         _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
 558                                             rtlefuse->autoload_failflag);
 559 #endif
 560 }
 561
 562 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
 563 {
 564         struct rtl_priv *rtlpriv = rtl_priv(hw);
 565         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 566         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 567
 568         switch (rtlhal->oem_id) {
 569         case RT_CID_819x_HP:
 570                 usb_priv->ledctl.led_opendrain = true;
 571                 break;
 572         case RT_CID_819x_Lenovo:
 573         case RT_CID_DEFAULT:
 574         case RT_CID_TOSHIBA:
 575         case RT_CID_CCX:
 576         case RT_CID_819x_Acer:
 577         case RT_CID_WHQL:
 578         default:
 579                 break;
 580         }
 581         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
 582                  rtlhal->oem_id);
 583 }
 584
 585 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
 586 {
 587
 588         struct rtl_priv *rtlpriv = rtl_priv(hw);
 589         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 590         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 591         u8 tmp_u1b;
 592
 593         if (!IS_NORMAL_CHIP(rtlhal->version))
 594                 return;
 595         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
 596         rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
 597                                EEPROM_93C46 : EEPROM_BOOT_EFUSE;
 598         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
 599                  tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
 600         rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
 601         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
 602                  tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
 603         _rtl92cu_read_adapter_info(hw);
 604         _rtl92cu_hal_customized_behavior(hw);
 605         return;
 606 }
 607
 608 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
 609 {
 610         struct rtl_priv *rtlpriv = rtl_priv(hw);
 611         int             status = 0;
 612         u16             value16;
 613         u8              value8;
 614         /*  polling autoload done. */
 615         u32     pollingCount = 0;
 616
 617         do {
 618                 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
 619                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 620                                  "Autoload Done!\n");
 621                         break;
 622                 }
 623                 if (pollingCount++ > 100) {
 624                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 625                                  "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
 626                         return -ENODEV;
 627                 }
 628         } while (true);
 629         /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
 630         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 631         /* Power on when re-enter from IPS/Radio off/card disable */
 632         /* enable SPS into PWM mode */
 633         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 634         udelay(100);
 635         value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
 636         if (0 == (value8 & LDV12_EN)) {
 637                 value8 |= LDV12_EN;
 638                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
 639                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 640                          " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
 641                          value8);
 642                 udelay(100);
 643                 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 644                 value8 &= ~ISO_MD2PP;
 645                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
 646         }
 647         /*  auto enable WLAN */
 648         pollingCount = 0;
 649         value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
 650         value16 |= APFM_ONMAC;
 651         rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
 652         do {
 653                 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
 654                         pr_info("MAC auto ON okay!\n");
 655                         break;
 656                 }
 657                 if (pollingCount++ > 100) {
 658                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 659                                  "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
 660                         return -ENODEV;
 661                 }
 662         } while (true);
 663         /* Enable Radio ,GPIO ,and LED function */
 664         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
 665         /* release RF digital isolation */
 666         value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 667         value16 &= ~ISO_DIOR;
 668         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
 669         /* Reconsider when to do this operation after asking HWSD. */
 670         pollingCount = 0;
 671         rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
 672                                                 REG_APSD_CTRL) & ~BIT(6)));
 673         do {
 674                 pollingCount++;
 675         } while ((pollingCount < 200) &&
 676                  (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
 677         /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 678         value16 = rtl_read_word(rtlpriv,  REG_CR);
 679         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 680                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
 681         rtl_write_word(rtlpriv, REG_CR, value16);
 682         return status;
 683 }
 684
 685 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
 686                                               bool wmm_enable,
 687                                               u8 out_ep_num,
 688                                               u8 queue_sel)
 689 {
 690         struct rtl_priv *rtlpriv = rtl_priv(hw);
 691         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 692         bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
 693         u32 outEPNum = (u32)out_ep_num;
 694         u32 numHQ = 0;
 695         u32 numLQ = 0;
 696         u32 numNQ = 0;
 697         u32 numPubQ;
 698         u32 value32;
 699         u8 value8;
 700         u32 txQPageNum, txQPageUnit, txQRemainPage;
 701
 702         if (!wmm_enable) {
 703                 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
 704                           CHIP_A_PAGE_NUM_PUBQ;
 705                 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
 706
 707                 txQPageUnit = txQPageNum/outEPNum;
 708                 txQRemainPage = txQPageNum % outEPNum;
 709                 if (queue_sel & TX_SELE_HQ)
 710                         numHQ = txQPageUnit;
 711                 if (queue_sel & TX_SELE_LQ)
 712                         numLQ = txQPageUnit;
 713                 /* HIGH priority queue always present in the configuration of
 714                  * 2 out-ep. Remainder pages have assigned to High queue */
 715                 if ((outEPNum > 1) && (txQRemainPage))
 716                         numHQ += txQRemainPage;
 717                 /* NOTE: This step done before writting REG_RQPN. */
 718                 if (isChipN) {
 719                         if (queue_sel & TX_SELE_NQ)
 720                                 numNQ = txQPageUnit;
 721                         value8 = (u8)_NPQ(numNQ);
 722                         rtl_write_byte(rtlpriv,  REG_RQPN_NPQ, value8);
 723                 }
 724         } else {
 725                 /* for WMM ,number of out-ep must more than or equal to 2! */
 726                 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
 727                           WMM_CHIP_A_PAGE_NUM_PUBQ;
 728                 if (queue_sel & TX_SELE_HQ) {
 729                         numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
 730                                 WMM_CHIP_A_PAGE_NUM_HPQ;
 731                 }
 732                 if (queue_sel & TX_SELE_LQ) {
 733                         numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
 734                                 WMM_CHIP_A_PAGE_NUM_LPQ;
 735                 }
 736                 /* NOTE: This step done before writting REG_RQPN. */
 737                 if (isChipN) {
 738                         if (queue_sel & TX_SELE_NQ)
 739                                 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
 740                         value8 = (u8)_NPQ(numNQ);
 741                         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
 742                 }
 743         }
 744         /* TX DMA */
 745         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 746         rtl_write_dword(rtlpriv, REG_RQPN, value32);
 747 }
 748
 749 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
 750 {
 751         struct rtl_priv *rtlpriv = rtl_priv(hw);
 752         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 753         u8      txpktbuf_bndy;
 754         u8      value8;
 755
 756         if (!wmm_enable)
 757                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 758         else /* for WMM */
 759                 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
 760                                                 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 761                                                 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 762         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 763         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 764         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 765         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 766         rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
 767         rtl_write_word(rtlpriv,  (REG_TRXFF_BNDY + 2), 0x27FF);
 768         value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
 769         rtl_write_byte(rtlpriv, REG_PBP, value8);
 770 }
 771
 772 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
 773                                             u16 bkQ, u16 viQ, u16 voQ,
 774                                             u16 mgtQ, u16 hiQ)
 775 {
 776         struct rtl_priv *rtlpriv = rtl_priv(hw);
 777         u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
 778
 779         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 780                    _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 781                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 782         rtl_write_word(rtlpriv,  REG_TRXDMA_CTRL, value16);
 783 }
 784
 785 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
 786                                                     bool wmm_enable,
 787                                                     u8 queue_sel)
 788 {
 789         u16 uninitialized_var(value);
 790
 791         switch (queue_sel) {
 792         case TX_SELE_HQ:
 793                 value = QUEUE_HIGH;
 794                 break;
 795         case TX_SELE_LQ:
 796                 value = QUEUE_LOW;
 797                 break;
 798         case TX_SELE_NQ:
 799                 value = QUEUE_NORMAL;
 800                 break;
 801         default:
 802                 WARN_ON(1); /* Shall not reach here! */
 803                 break;
 804         }
 805         _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
 806                                         value, value);
 807         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 808 }
 809
 810 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
 811                                                                 bool wmm_enable,
 812                                                                 u8 queue_sel)
 813 {
 814         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 815         u16 uninitialized_var(valueHi);
 816         u16 uninitialized_var(valueLow);
 817
 818         switch (queue_sel) {
 819         case (TX_SELE_HQ | TX_SELE_LQ):
 820                 valueHi = QUEUE_HIGH;
 821                 valueLow = QUEUE_LOW;
 822                 break;
 823         case (TX_SELE_NQ | TX_SELE_LQ):
 824                 valueHi = QUEUE_NORMAL;
 825                 valueLow = QUEUE_LOW;
 826                 break;
 827         case (TX_SELE_HQ | TX_SELE_NQ):
 828                 valueHi = QUEUE_HIGH;
 829                 valueLow = QUEUE_NORMAL;
 830                 break;
 831         default:
 832                 WARN_ON(1);
 833                 break;
 834         }
 835         if (!wmm_enable) {
 836                 beQ = valueLow;
 837                 bkQ = valueLow;
 838                 viQ = valueHi;
 839                 voQ = valueHi;
 840                 mgtQ = valueHi;
 841                 hiQ = valueHi;
 842         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 843                 beQ = valueHi;
 844                 bkQ = valueLow;
 845                 viQ = valueLow;
 846                 voQ = valueHi;
 847                 mgtQ = valueHi;
 848                 hiQ = valueHi;
 849         }
 850         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 851         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 852 }
 853
 854 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
 855                                                       bool wmm_enable,
 856                                                       u8 queue_sel)
 857 {
 858         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 859         struct rtl_priv *rtlpriv = rtl_priv(hw);
 860
 861         if (!wmm_enable) { /* typical setting */
 862                 beQ     = QUEUE_LOW;
 863                 bkQ     = QUEUE_LOW;
 864                 viQ     = QUEUE_NORMAL;
 865                 voQ     = QUEUE_HIGH;
 866                 mgtQ    = QUEUE_HIGH;
 867                 hiQ     = QUEUE_HIGH;
 868         } else { /* for WMM */
 869                 beQ     = QUEUE_LOW;
 870                 bkQ     = QUEUE_NORMAL;
 871                 viQ     = QUEUE_NORMAL;
 872                 voQ     = QUEUE_HIGH;
 873                 mgtQ    = QUEUE_HIGH;
 874                 hiQ     = QUEUE_HIGH;
 875         }
 876         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 877         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
 878                  queue_sel);
 879 }
 880
 881 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
 882                                                bool wmm_enable,
 883                                                u8 out_ep_num,
 884                                                u8 queue_sel)
 885 {
 886         switch (out_ep_num) {
 887         case 1:
 888                 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
 889                                                         queue_sel);
 890                 break;
 891         case 2:
 892                 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
 893                                                         queue_sel);
 894                 break;
 895         case 3:
 896                 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
 897                                                           queue_sel);
 898                 break;
 899         default:
 900                 WARN_ON(1); /* Shall not reach here! */
 901                 break;
 902         }
 903 }
 904
 905 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
 906                                                bool wmm_enable,
 907                                                u8 out_ep_num,
 908                                                u8 queue_sel)
 909 {
 910         u8 hq_sele = 0;
 911         struct rtl_priv *rtlpriv = rtl_priv(hw);
 912
 913         switch (out_ep_num) {
 914         case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
 915                 if (!wmm_enable) /* typical setting */
 916                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
 917                                    HQSEL_HIQ;
 918                 else    /* for WMM */
 919                         hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
 920                                   HQSEL_HIQ;
 921                 break;
 922         case 1:
 923                 if (TX_SELE_LQ == queue_sel) {
 924                         /* map all endpoint to Low queue */
 925                         hq_sele = 0;
 926                 } else if (TX_SELE_HQ == queue_sel) {
 927                         /* map all endpoint to High queue */
 928                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
 929                                    HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
 930                 }
 931                 break;
 932         default:
 933                 WARN_ON(1); /* Shall not reach here! */
 934                 break;
 935         }
 936         rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
 937         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
 938                  hq_sele);
 939 }
 940
 941 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
 942                                                 bool wmm_enable,
 943                                                 u8 out_ep_num,
 944                                                 u8 queue_sel)
 945 {
 946         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 947         if (IS_NORMAL_CHIP(rtlhal->version))
 948                 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
 949                                                    queue_sel);
 950         else
 951                 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
 952                                                    queue_sel);
 953 }
 954
 955 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
 956 {
 957 }
 958
 959 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
 960 {
 961         u16                     value16;
 962
 963         struct rtl_priv *rtlpriv = rtl_priv(hw);
 964         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 965
 966         mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
 967                       RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 968                       RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
 969         rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
 970         /* Accept all multicast address */
 971         rtl_write_dword(rtlpriv,  REG_MAR, 0xFFFFFFFF);
 972         rtl_write_dword(rtlpriv,  REG_MAR + 4, 0xFFFFFFFF);
 973         /* Accept all management frames */
 974         value16 = 0xFFFF;
 975         rtl92c_set_mgt_filter(hw, value16);
 976         /* Reject all control frame - default value is 0 */
 977         rtl92c_set_ctrl_filter(hw, 0x0);
 978         /* Accept all data frames */
 979         value16 = 0xFFFF;
 980         rtl92c_set_data_filter(hw, value16);
 981 }
 982
 983 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
 984 {
 985         struct rtl_priv *rtlpriv = rtl_priv(hw);
 986         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 987         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 988         struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
 989         int err = 0;
 990         u32     boundary = 0;
 991         u8 wmm_enable = false; /* TODO */
 992         u8 out_ep_nums = rtlusb->out_ep_nums;
 993         u8 queue_sel = rtlusb->out_queue_sel;
 994         err = _rtl92cu_init_power_on(hw);
 995
 996         if (err) {
 997                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 998                          "Failed to init power on!\n");
 999                 return err;
1000         }
1001         if (!wmm_enable) {
1002                 boundary = TX_PAGE_BOUNDARY;
1003         } else { /* for WMM */
1004                 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1005                                         ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1006                                         : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1007         }
1008         if (false == rtl92c_init_llt_table(hw, boundary)) {
1009                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1010                          "Failed to init LLT Table!\n");
1011                 return -EINVAL;
1012         }
1013         _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1014                                           queue_sel);
1015         _rtl92c_init_trx_buffer(hw, wmm_enable);
1016         _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1017                                      queue_sel);
1018         /* Get Rx PHY status in order to report RSSI and others. */
1019         rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1020         rtl92c_init_interrupt(hw);
1021         rtl92c_init_network_type(hw);
1022         _rtl92cu_init_wmac_setting(hw);
1023         rtl92c_init_adaptive_ctrl(hw);
1024         rtl92c_init_edca(hw);
1025         rtl92c_init_rate_fallback(hw);
1026         rtl92c_init_retry_function(hw);
1027         _rtl92cu_init_usb_aggregation(hw);
1028         rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1029         rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1030         rtl92c_init_beacon_parameters(hw, rtlhal->version);
1031         rtl92c_init_ampdu_aggregation(hw);
1032         rtl92c_init_beacon_max_error(hw, true);
1033         return err;
1034 }
1035
1036 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1037 {
1038         struct rtl_priv *rtlpriv = rtl_priv(hw);
1039         u8 sec_reg_value = 0x0;
1040         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1041
1042         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1043                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1044                  rtlpriv->sec.pairwise_enc_algorithm,
1045                  rtlpriv->sec.group_enc_algorithm);
1046         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1047                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1048                          "not open sw encryption\n");
1049                 return;
1050         }
1051         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1052         if (rtlpriv->sec.use_defaultkey) {
1053                 sec_reg_value |= SCR_TxUseDK;
1054                 sec_reg_value |= SCR_RxUseDK;
1055         }
1056         if (IS_NORMAL_CHIP(rtlhal->version))
1057                 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1058         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1059         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
1060                  sec_reg_value);
1061         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1062 }
1063
1064 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1065 {
1066         struct rtl_priv *rtlpriv = rtl_priv(hw);
1067         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1068
1069         /* To Fix MAC loopback mode fail. */
1070         rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1071         rtl_write_byte(rtlpriv, 0x15, 0xe9);
1072         /* HW SEQ CTRL */
1073         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1074         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1075         /* fixed USB interface interference issue */
1076         rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1077         rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1078         rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1079         rtlusb->reg_bcn_ctrl_val = 0x18;
1080         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1081 }
1082
1083 static void _InitPABias(struct ieee80211_hw *hw)
1084 {
1085         struct rtl_priv *rtlpriv = rtl_priv(hw);
1086         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1087         u8 pa_setting;
1088
1089         /* FIXED PA current issue */
1090         pa_setting = efuse_read_1byte(hw, 0x1FA);
1091         if (!(pa_setting & BIT(0))) {
1092                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1093                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1094                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1095                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1096         }
1097         if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1098             IS_92C_SERIAL(rtlhal->version)) {
1099                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1100                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1101                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1102                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1103         }
1104         if (!(pa_setting & BIT(4))) {
1105                 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1106                 pa_setting &= 0x0F;
1107                 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1108         }
1109 }
1110
1111 static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1112 {
1113 #ifdef CONFIG_ANTENNA_DIVERSITY
1114         struct rtl_priv *rtlpriv = rtl_priv(hw);
1115         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1116         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1117
1118         if (pHalData->AntDivCfg == 0)
1119                 return;
1120
1121         if (rtlphy->rf_type == RF_1T1R) {
1122                 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1123                                 rtl_read_dword(rtlpriv,
1124                                 REG_LEDCFG0)|BIT(23));
1125                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1126                 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1127                     Antenna_A)
1128                         pHalData->CurAntenna = Antenna_A;
1129                 else
1130                         pHalData->CurAntenna = Antenna_B;
1131         }
1132 #endif
1133 }
1134
1135 static void _dump_registers(struct ieee80211_hw *hw)
1136 {
1137 }
1138
1139 static void _update_mac_setting(struct ieee80211_hw *hw)
1140 {
1141         struct rtl_priv *rtlpriv = rtl_priv(hw);
1142         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1143
1144         mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1145         mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1146         mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1147         mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1148 }
1149
1150 int rtl92cu_hw_init(struct ieee80211_hw *hw)
1151 {
1152         struct rtl_priv *rtlpriv = rtl_priv(hw);
1153         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1154         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1155         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1156         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1157         int err = 0;
1158         static bool iqk_initialized;
1159
1160         rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1161         err = _rtl92cu_init_mac(hw);
1162         if (err) {
1163                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
1164                 return err;
1165         }
1166         err = rtl92c_download_fw(hw);
1167         if (err) {
1168                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1169                          "Failed to download FW. Init HW without FW now..\n");
1170                 err = 1;
1171                 rtlhal->fw_ready = false;
1172                 return err;
1173         } else {
1174                 rtlhal->fw_ready = true;
1175         }
1176         rtlhal->last_hmeboxnum = 0; /* h2c */
1177         _rtl92cu_phy_param_tab_init(hw);
1178         rtl92cu_phy_mac_config(hw);
1179         rtl92cu_phy_bb_config(hw);
1180         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1181         rtl92c_phy_rf_config(hw);
1182         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1183             !IS_92C_SERIAL(rtlhal->version)) {
1184                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1185                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1186         }
1187         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1188                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1189         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1190                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1191         rtl92cu_bb_block_on(hw);
1192         rtl_cam_reset_all_entry(hw);
1193         rtl92cu_enable_hw_security_config(hw);
1194         ppsc->rfpwr_state = ERFON;
1195         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1196         if (ppsc->rfpwr_state == ERFON) {
1197                 rtl92c_phy_set_rfpath_switch(hw, 1);
1198                 if (iqk_initialized) {
1199                         rtl92c_phy_iq_calibrate(hw, false);
1200                 } else {
1201                         rtl92c_phy_iq_calibrate(hw, false);
1202                         iqk_initialized = true;
1203                 }
1204                 rtl92c_dm_check_txpower_tracking(hw);
1205                 rtl92c_phy_lc_calibrate(hw);
1206         }
1207         _rtl92cu_hw_configure(hw);
1208         _InitPABias(hw);
1209         _InitAntenna_Selection(hw);
1210         _update_mac_setting(hw);
1211         rtl92c_dm_init(hw);
1212         _dump_registers(hw);
1213         return err;
1214 }
1215
1216 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1217 {
1218         struct rtl_priv *rtlpriv = rtl_priv(hw);
1219 /**************************************
1220 a.      TXPAUSE 0x522[7:0] = 0xFF       Pause MAC TX queue
1221 b.      RF path 0 offset 0x00 = 0x00    disable RF
1222 c.      APSD_CTRL 0x600[7:0] = 0x40
1223 d.      SYS_FUNC_EN 0x02[7:0] = 0x16    reset BB state machine
1224 e.      SYS_FUNC_EN 0x02[7:0] = 0x14    reset BB state machine
1225 ***************************************/
1226         u8 eRFPath = 0, value8 = 0;
1227         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1228         rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1229
1230         value8 |= APSDOFF;
1231         rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1232         value8 = 0;
1233         value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1234         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1235         value8 &= (~FEN_BB_GLB_RSTn);
1236         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1237 }
1238
1239 static void  _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1240 {
1241         struct rtl_priv *rtlpriv = rtl_priv(hw);
1242         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1243
1244         if (rtlhal->fw_version <=  0x20) {
1245                 /*****************************
1246                 f. MCUFWDL 0x80[7:0]=0          reset MCU ready status
1247                 g. SYS_FUNC_EN 0x02[10]= 0      reset MCU reg, (8051 reset)
1248                 h. SYS_FUNC_EN 0x02[15-12]= 5   reset MAC reg, DCORE
1249                 i. SYS_FUNC_EN 0x02[10]= 1      enable MCU reg, (8051 enable)
1250                 ******************************/
1251                 u16 valu16 = 0;
1252
1253                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1254                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1255                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1256                                (~FEN_CPUEN))); /* reset MCU ,8051 */
1257                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1258                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1259                               (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1260                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1261                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1262                                FEN_CPUEN)); /* enable MCU ,8051 */
1263         } else {
1264                 u8 retry_cnts = 0;
1265
1266                 /* IF fw in RAM code, do reset */
1267                 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1268                         /* reset MCU ready status */
1269                         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1270                         if (rtlhal->fw_ready) {
1271                                 /* 8051 reset by self */
1272                                 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1273                                 while ((retry_cnts++ < 100) &&
1274                                        (FEN_CPUEN & rtl_read_word(rtlpriv,
1275                                        REG_SYS_FUNC_EN))) {
1276                                         udelay(50);
1277                                 }
1278                                 if (retry_cnts >= 100) {
1279                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1280                                                  "#####=> 8051 reset failed!.........................\n");
1281                                         /* if 8051 reset fail, reset MAC. */
1282                                         rtl_write_byte(rtlpriv,
1283                                                        REG_SYS_FUNC_EN + 1,
1284                                                        0x50);
1285                                         udelay(100);
1286                                 }
1287                         }
1288                 }
1289                 /* Reset MAC and Enable 8051 */
1290                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1291                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1292         }
1293         if (bWithoutHWSM) {
1294                 /*****************************
1295                   Without HW auto state machine
1296                 g.SYS_CLKR 0x08[15:0] = 0x30A3          disable MAC clock
1297                 h.AFE_PLL_CTRL 0x28[7:0] = 0x80         disable AFE PLL
1298                 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F     gated AFE DIG_CLOCK
1299                 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9         isolated digital to PON
1300                 ******************************/
1301                 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1302                 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1303                 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1304                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1305         }
1306 }
1307
1308 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1309 {
1310         struct rtl_priv *rtlpriv = rtl_priv(hw);
1311 /*****************************
1312 k. SYS_FUNC_EN 0x03[7:0] = 0x44         disable ELDR runction
1313 l. SYS_CLKR 0x08[15:0] = 0x3083         disable ELDR clock
1314 m. SYS_ISO_CTRL 0x01[7:0] = 0x83        isolated ELDR to PON
1315 ******************************/
1316         rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1317         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1318 }
1319
1320 static void _DisableGPIO(struct ieee80211_hw *hw)
1321 {
1322         struct rtl_priv *rtlpriv = rtl_priv(hw);
1323 /***************************************
1324 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1325 k. Value = GPIO_PIN_CTRL[7:0]
1326 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1327 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1328 n. LEDCFG 0x4C[15:0] = 0x8080
1329 ***************************************/
1330         u8      value8;
1331         u16     value16;
1332         u32     value32;
1333
1334         /* 1. Disable GPIO[7:0] */
1335         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1336         value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1337         value8 = (u8) (value32&0x000000FF);
1338         value32 |= ((value8<<8) | 0x00FF0000);
1339         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1340         /* 2. Disable GPIO[10:8] */
1341         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1342         value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1343         value8 = (u8) (value16&0x000F);
1344         value16 |= ((value8<<4) | 0x0780);
1345         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1346         /* 3. Disable LED0 & 1 */
1347         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1348 }
1349
1350 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1351 {
1352         struct rtl_priv *rtlpriv = rtl_priv(hw);
1353         u16 value16 = 0;
1354         u8 value8 = 0;
1355
1356         if (bWithoutHWSM) {
1357                 /*****************************
1358                 n. LDOA15_CTRL 0x20[7:0] = 0x04  disable A15 power
1359                 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1360                 r. When driver call disable, the ASIC will turn off remaining
1361                    clock automatically
1362                 ******************************/
1363                 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1364                 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1365                 value8 &= (~LDV12_EN);
1366                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1367         }
1368
1369 /*****************************
1370 h. SPS0_CTRL 0x11[7:0] = 0x23           enter PFM mode
1371 i. APS_FSMCO 0x04[15:0] = 0x4802        set USB suspend
1372 ******************************/
1373         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1374         value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1375         rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1376         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1377 }
1378
1379 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1380 {
1381         /* ==== RF Off Sequence ==== */
1382         _DisableRFAFEAndResetBB(hw);
1383         /* ==== Reset digital sequence   ====== */
1384         _ResetDigitalProcedure1(hw, false);
1385         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1386         _DisableGPIO(hw);
1387         /* ==== Disable analog sequence === */
1388         _DisableAnalog(hw, false);
1389 }
1390
1391 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1392 {
1393         /*==== RF Off Sequence ==== */
1394         _DisableRFAFEAndResetBB(hw);
1395         /*  ==== Reset digital sequence   ====== */
1396         _ResetDigitalProcedure1(hw, true);
1397         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1398         _DisableGPIO(hw);
1399         /*  ==== Reset digital sequence   ====== */
1400         _ResetDigitalProcedure2(hw);
1401         /*  ==== Disable analog sequence === */
1402         _DisableAnalog(hw, true);
1403 }
1404
1405 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1406                                       u8 set_bits, u8 clear_bits)
1407 {
1408         struct rtl_priv *rtlpriv = rtl_priv(hw);
1409         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1410
1411         rtlusb->reg_bcn_ctrl_val |= set_bits;
1412         rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1413         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1414 }
1415
1416 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1417 {
1418         struct rtl_priv *rtlpriv = rtl_priv(hw);
1419         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1420         u8 tmp1byte = 0;
1421         if (IS_NORMAL_CHIP(rtlhal->version)) {
1422                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1423                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1424                                tmp1byte & (~BIT(6)));
1425                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1426                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1427                 tmp1byte &= ~(BIT(0));
1428                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1429         } else {
1430                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1431                                rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1432         }
1433 }
1434
1435 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1436 {
1437         struct rtl_priv *rtlpriv = rtl_priv(hw);
1438         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1439         u8 tmp1byte = 0;
1440
1441         if (IS_NORMAL_CHIP(rtlhal->version)) {
1442                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1443                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1444                                tmp1byte | BIT(6));
1445                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1446                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1447                 tmp1byte |= BIT(0);
1448                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1449         } else {
1450                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1451                                rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1452         }
1453 }
1454
1455 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1456 {
1457         struct rtl_priv *rtlpriv = rtl_priv(hw);
1458         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1459
1460         if (IS_NORMAL_CHIP(rtlhal->version))
1461                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1462         else
1463                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1464 }
1465
1466 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1467 {
1468         struct rtl_priv *rtlpriv = rtl_priv(hw);
1469         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1470
1471         if (IS_NORMAL_CHIP(rtlhal->version))
1472                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1473         else
1474                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1475 }
1476
1477 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1478                                      enum nl80211_iftype type)
1479 {
1480         struct rtl_priv *rtlpriv = rtl_priv(hw);
1481         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1482         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1483
1484         bt_msr &= 0xfc;
1485         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1486         if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1487             NL80211_IFTYPE_STATION) {
1488                 _rtl92cu_stop_tx_beacon(hw);
1489                 _rtl92cu_enable_bcn_sub_func(hw);
1490         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1491                 _rtl92cu_resume_tx_beacon(hw);
1492                 _rtl92cu_disable_bcn_sub_func(hw);
1493         } else {
1494                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1495                          "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1496                          type);
1497         }
1498         switch (type) {
1499         case NL80211_IFTYPE_UNSPECIFIED:
1500                 bt_msr |= MSR_NOLINK;
1501                 ledaction = LED_CTL_LINK;
1502                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1503                          "Set Network type to NO LINK!\n");
1504                 break;
1505         case NL80211_IFTYPE_ADHOC:
1506                 bt_msr |= MSR_ADHOC;
1507                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1508                          "Set Network type to Ad Hoc!\n");
1509                 break;
1510         case NL80211_IFTYPE_STATION:
1511                 bt_msr |= MSR_INFRA;
1512                 ledaction = LED_CTL_LINK;
1513                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1514                          "Set Network type to STA!\n");
1515                 break;
1516         case NL80211_IFTYPE_AP:
1517                 bt_msr |= MSR_AP;
1518                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1519                          "Set Network type to AP!\n");
1520                 break;
1521         default:
1522                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1523                          "Network type %d not supported!\n", type);
1524                 goto error_out;
1525         }
1526         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1527         rtlpriv->cfg->ops->led_control(hw, ledaction);
1528         if ((bt_msr & 0xfc) == MSR_AP)
1529                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1530         else
1531                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1532         return 0;
1533 error_out:
1534         return 1;
1535 }
1536
1537 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1538 {
1539         struct rtl_priv *rtlpriv = rtl_priv(hw);
1540         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1541         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1542         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1543         enum nl80211_iftype opmode;
1544
1545         mac->link_state = MAC80211_NOLINK;
1546         opmode = NL80211_IFTYPE_UNSPECIFIED;
1547         _rtl92cu_set_media_status(hw, opmode);
1548         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1549         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1550         if (rtlusb->disableHWSM)
1551                 _CardDisableHWSM(hw);
1552         else
1553                 _CardDisableWithoutHWSM(hw);
1554 }
1555
1556 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1557 {
1558         /* dummy routine needed for callback from rtl_op_configure_filter() */
1559 }
1560
1561 /*========================================================================== */
1562
1563 static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1564                               enum nl80211_iftype type)
1565 {
1566         struct rtl_priv *rtlpriv = rtl_priv(hw);
1567         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1568         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1569         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1570         u8 filterout_non_associated_bssid = false;
1571
1572         switch (type) {
1573         case NL80211_IFTYPE_ADHOC:
1574         case NL80211_IFTYPE_STATION:
1575                 filterout_non_associated_bssid = true;
1576                 break;
1577         case NL80211_IFTYPE_UNSPECIFIED:
1578         case NL80211_IFTYPE_AP:
1579         default:
1580                 break;
1581         }
1582         if (filterout_non_associated_bssid) {
1583                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1584                         switch (rtlphy->current_io_type) {
1585                         case IO_CMD_RESUME_DM_BY_SCAN:
1586                                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1587                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1588                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1589                                 /* enable update TSF */
1590                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1591                                 break;
1592                         case IO_CMD_PAUSE_DM_BY_SCAN:
1593                                 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1594                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1595                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1596                                 /* disable update TSF */
1597                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1598                                 break;
1599                         }
1600                 } else {
1601                         reg_rcr |= (RCR_CBSSID);
1602                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1603                                                       (u8 *)(&reg_rcr));
1604                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1605                 }
1606         } else if (filterout_non_associated_bssid == false) {
1607                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1608                         reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1609                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1610                                                       (u8 *)(&reg_rcr));
1611                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1612                 } else {
1613                         reg_rcr &= (~RCR_CBSSID);
1614                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1615                                                       (u8 *)(&reg_rcr));
1616                         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1617                 }
1618         }
1619 }
1620
1621 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1622 {
1623         if (_rtl92cu_set_media_status(hw, type))
1624                 return -EOPNOTSUPP;
1625         _rtl92cu_set_check_bssid(hw, type);
1626         return 0;
1627 }
1628
1629 static void _InitBeaconParameters(struct ieee80211_hw *hw)
1630 {
1631         struct rtl_priv *rtlpriv = rtl_priv(hw);
1632         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1633
1634         rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1635
1636         /* TODO: Remove these magic number */
1637         rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1638         rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1639         rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1640         /* Change beacon AIFS to the largest number
1641          * beacause test chip does not contension before sending beacon. */
1642         if (IS_NORMAL_CHIP(rtlhal->version))
1643                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1644         else
1645                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1646 }
1647
1648 static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1649                                     bool Linked)
1650 {
1651         struct rtl_priv *rtlpriv = rtl_priv(hw);
1652
1653         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1654         rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1655 }
1656
1657 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1658 {
1659
1660         struct rtl_priv *rtlpriv = rtl_priv(hw);
1661         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1662         u16 bcn_interval, atim_window;
1663         u32 value32;
1664
1665         bcn_interval = mac->beacon_interval;
1666         atim_window = 2;        /*FIX MERGE */
1667         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1668         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1669         _InitBeaconParameters(hw);
1670         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1671         /*
1672          * Force beacon frame transmission even after receiving beacon frame
1673          * from other ad hoc STA
1674          *
1675          *
1676          * Reset TSF Timer to zero, added by Roger. 2008.06.24
1677          */
1678         value32 = rtl_read_dword(rtlpriv, REG_TCR);
1679         value32 &= ~TSFRST;
1680         rtl_write_dword(rtlpriv, REG_TCR, value32);
1681         value32 |= TSFRST;
1682         rtl_write_dword(rtlpriv, REG_TCR, value32);
1683         RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1684                  "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1685                  value32);
1686         /* TODO: Modify later (Find the right parameters)
1687          * NOTE: Fix test chip's bug (about contention windows's randomness) */
1688         if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1689             (mac->opmode == NL80211_IFTYPE_AP)) {
1690                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1691                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1692         }
1693         _beacon_function_enable(hw, true, true);
1694 }
1695
1696 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1697 {
1698         struct rtl_priv *rtlpriv = rtl_priv(hw);
1699         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1700         u16 bcn_interval = mac->beacon_interval;
1701
1702         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1703                  bcn_interval);
1704         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1705 }
1706
1707 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1708                                    u32 add_msr, u32 rm_msr)
1709 {
1710 }
1711
1712 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1713 {
1714         struct rtl_priv *rtlpriv = rtl_priv(hw);
1715         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1716         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1717
1718         switch (variable) {
1719         case HW_VAR_RCR:
1720                 *((u32 *)(val)) = mac->rx_conf;
1721                 break;
1722         case HW_VAR_RF_STATE:
1723                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1724                 break;
1725         case HW_VAR_FWLPS_RF_ON:{
1726                         enum rf_pwrstate rfState;
1727                         u32 val_rcr;
1728
1729                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1730                                                       (u8 *)(&rfState));
1731                         if (rfState == ERFOFF) {
1732                                 *((bool *) (val)) = true;
1733                         } else {
1734                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1735                                 val_rcr &= 0x00070000;
1736                                 if (val_rcr)
1737                                         *((bool *) (val)) = false;
1738                                 else
1739                                         *((bool *) (val)) = true;
1740                         }
1741                         break;
1742                 }
1743         case HW_VAR_FW_PSMODE_STATUS:
1744                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1745                 break;
1746         case HW_VAR_CORRECT_TSF:{
1747                         u64 tsf;
1748                         u32 *ptsf_low = (u32 *)&tsf;
1749                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
1750
1751                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1752                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1753                         *((u64 *)(val)) = tsf;
1754                         break;
1755                 }
1756         case HW_VAR_MGT_FILTER:
1757                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1758                 break;
1759         case HW_VAR_CTRL_FILTER:
1760                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1761                 break;
1762         case HW_VAR_DATA_FILTER:
1763                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1764                 break;
1765         default:
1766                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1767                          "switch case not processed\n");
1768                 break;
1769         }
1770 }
1771
1772 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1773 {
1774         struct rtl_priv *rtlpriv = rtl_priv(hw);
1775         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1776         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1777         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1778         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1779         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1780         enum wireless_mode wirelessmode = mac->mode;
1781         u8 idx = 0;
1782
1783         switch (variable) {
1784         case HW_VAR_ETHER_ADDR:{
1785                         for (idx = 0; idx < ETH_ALEN; idx++) {
1786                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1787                                                val[idx]);
1788                         }
1789                         break;
1790                 }
1791         case HW_VAR_BASIC_RATE:{
1792                         u16 rate_cfg = ((u16 *) val)[0];
1793                         u8 rate_index = 0;
1794
1795                         rate_cfg &= 0x15f;
1796                         /* TODO */
1797                         /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1798                          *     && ((rate_cfg & 0x150) == 0)) {
1799                          *        rate_cfg |= 0x010;
1800                          * } */
1801                         rate_cfg |= 0x01;
1802                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1803                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
1804                                        (rate_cfg >> 8) & 0xff);
1805                         while (rate_cfg > 0x1) {
1806                                 rate_cfg >>= 1;
1807                                 rate_index++;
1808                         }
1809                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1810                                        rate_index);
1811                         break;
1812                 }
1813         case HW_VAR_BSSID:{
1814                         for (idx = 0; idx < ETH_ALEN; idx++) {
1815                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1816                                                val[idx]);
1817                         }
1818                         break;
1819                 }
1820         case HW_VAR_SIFS:{
1821                         rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1822                         rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1823                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1824                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1825                         rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1826                         rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1827                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1828                         break;
1829                 }
1830         case HW_VAR_SLOT_TIME:{
1831                         u8 e_aci;
1832                         u8 QOS_MODE = 1;
1833
1834                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1835                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1836                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
1837                         if (QOS_MODE) {
1838                                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1839                                         rtlpriv->cfg->ops->set_hw_reg(hw,
1840                                                                 HW_VAR_AC_PARAM,
1841                                                                 (u8 *)(&e_aci));
1842                         } else {
1843                                 u8 sifstime = 0;
1844                                 u8      u1bAIFS;
1845
1846                                 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1847                                     IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1848                                     IS_WIRELESS_MODE_N_5G(wirelessmode))
1849                                         sifstime = 16;
1850                                 else
1851                                         sifstime = 10;
1852                                 u1bAIFS = sifstime + (2 *  val[0]);
1853                                 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1854                                                u1bAIFS);
1855                                 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1856                                                u1bAIFS);
1857                                 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1858                                                u1bAIFS);
1859                                 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1860                                                u1bAIFS);
1861                         }
1862                         break;
1863                 }
1864         case HW_VAR_ACK_PREAMBLE:{
1865                         u8 reg_tmp;
1866                         u8 short_preamble = (bool) (*(u8 *) val);
1867                         reg_tmp = 0;
1868                         if (short_preamble)
1869                                 reg_tmp |= 0x80;
1870                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1871                         break;
1872                 }
1873         case HW_VAR_AMPDU_MIN_SPACE:{
1874                         u8 min_spacing_to_set;
1875                         u8 sec_min_space;
1876
1877                         min_spacing_to_set = *((u8 *) val);
1878                         if (min_spacing_to_set <= 7) {
1879                                 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1880                                 case NO_ENCRYPTION:
1881                                 case AESCCMP_ENCRYPTION:
1882                                         sec_min_space = 0;
1883                                         break;
1884                                 case WEP40_ENCRYPTION:
1885                                 case WEP104_ENCRYPTION:
1886                                 case TKIP_ENCRYPTION:
1887                                         sec_min_space = 6;
1888                                         break;
1889                                 default:
1890                                         sec_min_space = 7;
1891                                         break;
1892                                 }
1893                                 if (min_spacing_to_set < sec_min_space)
1894                                         min_spacing_to_set = sec_min_space;
1895                                 mac->min_space_cfg = ((mac->min_space_cfg &
1896                                                      0xf8) |
1897                                                      min_spacing_to_set);
1898                                 *val = min_spacing_to_set;
1899                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1900                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1901                                          mac->min_space_cfg);
1902                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1903                                                mac->min_space_cfg);
1904                         }
1905                         break;
1906                 }
1907         case HW_VAR_SHORTGI_DENSITY:{
1908                         u8 density_to_set;
1909
1910                         density_to_set = *((u8 *) val);
1911                         density_to_set &= 0x1f;
1912                         mac->min_space_cfg &= 0x07;
1913                         mac->min_space_cfg |= (density_to_set << 3);
1914                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1915                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1916                                  mac->min_space_cfg);
1917                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1918                                        mac->min_space_cfg);
1919                         break;
1920                 }
1921         case HW_VAR_AMPDU_FACTOR:{
1922                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1923                         u8 factor_toset;
1924                         u8 *p_regtoset = NULL;
1925                         u8 index = 0;
1926
1927                         p_regtoset = regtoset_normal;
1928                         factor_toset = *((u8 *) val);
1929                         if (factor_toset <= 3) {
1930                                 factor_toset = (1 << (factor_toset + 2));
1931                                 if (factor_toset > 0xf)
1932                                         factor_toset = 0xf;
1933                                 for (index = 0; index < 4; index++) {
1934                                         if ((p_regtoset[index] & 0xf0) >
1935                                             (factor_toset << 4))
1936                                                 p_regtoset[index] =
1937                                                      (p_regtoset[index] & 0x0f)
1938                                                      | (factor_toset << 4);
1939                                         if ((p_regtoset[index] & 0x0f) >
1940                                              factor_toset)
1941                                                 p_regtoset[index] =
1942                                                      (p_regtoset[index] & 0xf0)
1943                                                      | (factor_toset);
1944                                         rtl_write_byte(rtlpriv,
1945                                                        (REG_AGGLEN_LMT + index),
1946                                                        p_regtoset[index]);
1947                                 }
1948                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1949                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1950                                          factor_toset);
1951                         }
1952                         break;
1953                 }
1954         case HW_VAR_AC_PARAM:{
1955                         u8 e_aci = *((u8 *) val);
1956                         u32 u4b_ac_param;
1957                         u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1958                         u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1959                         u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1960
1961                         u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1962                         u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1963                                          AC_PARAM_ECW_MIN_OFFSET);
1964                         u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1965                                          AC_PARAM_ECW_MAX_OFFSET);
1966                         u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1967                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1968                                  "queue:%x, ac_param:%x\n",
1969                                  e_aci, u4b_ac_param);
1970                         switch (e_aci) {
1971                         case AC1_BK:
1972                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1973                                                 u4b_ac_param);
1974                                 break;
1975                         case AC0_BE:
1976                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1977                                                 u4b_ac_param);
1978                                 break;
1979                         case AC2_VI:
1980                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1981                                                 u4b_ac_param);
1982                                 break;
1983                         case AC3_VO:
1984                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1985                                                 u4b_ac_param);
1986                                 break;
1987                         default:
1988                                 RT_ASSERT(false, ("SetHwReg8185(): invalid"
1989                                           " aci: %d !\n", e_aci));
1990                                 break;
1991                         }
1992                         if (rtlusb->acm_method != eAcmWay2_SW)
1993                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1994                                          HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
1995                         break;
1996                 }
1997         case HW_VAR_ACM_CTRL:{
1998                         u8 e_aci = *((u8 *) val);
1999                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
2000                                                         (&(mac->ac[0].aifs));
2001                         u8 acm = p_aci_aifsn->f.acm;
2002                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2003
2004                         acm_ctrl =
2005                             acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2006                         if (acm) {
2007                                 switch (e_aci) {
2008                                 case AC0_BE:
2009                                         acm_ctrl |= AcmHw_BeqEn;
2010                                         break;
2011                                 case AC2_VI:
2012                                         acm_ctrl |= AcmHw_ViqEn;
2013                                         break;
2014                                 case AC3_VO:
2015                                         acm_ctrl |= AcmHw_VoqEn;
2016                                         break;
2017                                 default:
2018                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2019                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
2020                                                  acm);
2021                                         break;
2022                                 }
2023                         } else {
2024                                 switch (e_aci) {
2025                                 case AC0_BE:
2026                                         acm_ctrl &= (~AcmHw_BeqEn);
2027                                         break;
2028                                 case AC2_VI:
2029                                         acm_ctrl &= (~AcmHw_ViqEn);
2030                                         break;
2031                                 case AC3_VO:
2032                                         acm_ctrl &= (~AcmHw_BeqEn);
2033                                         break;
2034                                 default:
2035                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2036                                                  "switch case not processed\n");
2037                                         break;
2038                                 }
2039                         }
2040                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2041                                  "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
2042                                  acm_ctrl);
2043                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2044                         break;
2045                 }
2046         case HW_VAR_RCR:{
2047                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2048                         mac->rx_conf = ((u32 *) (val))[0];
2049                         RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2050                                  "### Set RCR(0x%08x) ###\n", mac->rx_conf);
2051                         break;
2052                 }
2053         case HW_VAR_RETRY_LIMIT:{
2054                         u8 retry_limit = ((u8 *) (val))[0];
2055
2056                         rtl_write_word(rtlpriv, REG_RL,
2057                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2058                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
2059                         RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
2060                                  "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
2061                                  retry_limit);
2062                         break;
2063                 }
2064         case HW_VAR_DUAL_TSF_RST:
2065                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2066                 break;
2067         case HW_VAR_EFUSE_BYTES:
2068                 rtlefuse->efuse_usedbytes = *((u16 *) val);
2069                 break;
2070         case HW_VAR_EFUSE_USAGE:
2071                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2072                 break;
2073         case HW_VAR_IO_CMD:
2074                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2075                 break;
2076         case HW_VAR_WPA_CONFIG:
2077                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2078                 break;
2079         case HW_VAR_SET_RPWM:{
2080                         u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2081
2082                         if (rpwm_val & BIT(7))
2083                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2084                                                (*(u8 *)val));
2085                         else
2086                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2087                                                ((*(u8 *)val) | BIT(7)));
2088                         break;
2089                 }
2090         case HW_VAR_H2C_FW_PWRMODE:{
2091                         u8 psmode = (*(u8 *) val);
2092
2093                         if ((psmode != FW_PS_ACTIVE_MODE) &&
2094                            (!IS_92C_SERIAL(rtlhal->version)))
2095                                 rtl92c_dm_rf_saving(hw, true);
2096                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2097                         break;
2098                 }
2099         case HW_VAR_FW_PSMODE_STATUS:
2100                 ppsc->fw_current_inpsmode = *((bool *) val);
2101                 break;
2102         case HW_VAR_H2C_FW_JOINBSSRPT:{
2103                         u8 mstatus = (*(u8 *) val);
2104                         u8 tmp_reg422;
2105                         bool recover = false;
2106
2107                         if (mstatus == RT_MEDIA_CONNECT) {
2108                                 rtlpriv->cfg->ops->set_hw_reg(hw,
2109                                                          HW_VAR_AID, NULL);
2110                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2111                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2112                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2113                                 tmp_reg422 = rtl_read_byte(rtlpriv,
2114                                                         REG_FWHW_TXQ_CTRL + 2);
2115                                 if (tmp_reg422 & BIT(6))
2116                                         recover = true;
2117                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2118                                                tmp_reg422 & (~BIT(6)));
2119                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2120                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2121                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2122                                 if (recover)
2123                                         rtl_write_byte(rtlpriv,
2124                                                  REG_FWHW_TXQ_CTRL + 2,
2125                                                 tmp_reg422 | BIT(6));
2126                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2127                         }
2128                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2129                         break;
2130                 }
2131         case HW_VAR_AID:{
2132                         u16 u2btmp;
2133
2134                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2135                         u2btmp &= 0xC000;
2136                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2137                                        (u2btmp | mac->assoc_id));
2138                         break;
2139                 }
2140         case HW_VAR_CORRECT_TSF:{
2141                         u8 btype_ibss = ((u8 *) (val))[0];
2142
2143                         if (btype_ibss)
2144                                 _rtl92cu_stop_tx_beacon(hw);
2145                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2146                         rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2147                                         0xffffffff));
2148                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2149                                         (u32)((mac->tsf >> 32) & 0xffffffff));
2150                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2151                         if (btype_ibss)
2152                                 _rtl92cu_resume_tx_beacon(hw);
2153                         break;
2154                 }
2155         case HW_VAR_MGT_FILTER:
2156                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2157                 break;
2158         case HW_VAR_CTRL_FILTER:
2159                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2160                 break;
2161         case HW_VAR_DATA_FILTER:
2162                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2163                 break;
2164         default:
2165                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2166                          "switch case not processed\n");
2167                 break;
2168         }
2169 }
2170
2171 void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
2172                                    struct ieee80211_sta *sta,
2173                                    u8 rssi_level)
2174 {
2175         struct rtl_priv *rtlpriv = rtl_priv(hw);
2176         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2177         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2178         u32 ratr_value = (u32) mac->basic_rates;
2179         u8 *mcsrate = mac->mcs;
2180         u8 ratr_index = 0;
2181         u8 nmode = mac->ht_enable;
2182         u8 mimo_ps = 1;
2183         u16 shortgi_rate = 0;
2184         u32 tmp_ratr_value = 0;
2185         u8 curtxbw_40mhz = mac->bw_40;
2186         u8 curshortgi_40mhz = mac->sgi_40;
2187         u8 curshortgi_20mhz = mac->sgi_20;
2188         enum wireless_mode wirelessmode = mac->mode;
2189
2190         ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2191         switch (wirelessmode) {
2192         case WIRELESS_MODE_B:
2193                 if (ratr_value & 0x0000000c)
2194                         ratr_value &= 0x0000000d;
2195                 else
2196                         ratr_value &= 0x0000000f;
2197                 break;
2198         case WIRELESS_MODE_G:
2199                 ratr_value &= 0x00000FF5;
2200                 break;
2201         case WIRELESS_MODE_N_24G:
2202         case WIRELESS_MODE_N_5G:
2203                 nmode = 1;
2204                 if (mimo_ps == 0) {
2205                         ratr_value &= 0x0007F005;
2206                 } else {
2207                         u32 ratr_mask;
2208
2209                         if (get_rf_type(rtlphy) == RF_1T2R ||
2210                             get_rf_type(rtlphy) == RF_1T1R)
2211                                 ratr_mask = 0x000ff005;
2212                         else
2213                                 ratr_mask = 0x0f0ff005;
2214                         if (curtxbw_40mhz)
2215                                 ratr_mask |= 0x00000010;
2216                         ratr_value &= ratr_mask;
2217                 }
2218                 break;
2219         default:
2220                 if (rtlphy->rf_type == RF_1T2R)
2221                         ratr_value &= 0x000ff0ff;
2222                 else
2223                         ratr_value &= 0x0f0ff0ff;
2224                 break;
2225         }
2226         ratr_value &= 0x0FFFFFFF;
2227         if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2228             (!curtxbw_40mhz && curshortgi_20mhz))) {
2229                 ratr_value |= 0x10000000;
2230                 tmp_ratr_value = (ratr_value >> 12);
2231                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2232                         if ((1 << shortgi_rate) & tmp_ratr_value)
2233                                 break;
2234                 }
2235                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2236                                (shortgi_rate << 4) | (shortgi_rate);
2237         }
2238         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2239         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2240                  rtl_read_dword(rtlpriv, REG_ARFR0));
2241 }
2242
2243 void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2244 {
2245         struct rtl_priv *rtlpriv = rtl_priv(hw);
2246         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2247         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2248         u32 ratr_bitmap = (u32) mac->basic_rates;
2249         u8 *p_mcsrate = mac->mcs;
2250         u8 ratr_index = 0;
2251         u8 curtxbw_40mhz = mac->bw_40;
2252         u8 curshortgi_40mhz = mac->sgi_40;
2253         u8 curshortgi_20mhz = mac->sgi_20;
2254         enum wireless_mode wirelessmode = mac->mode;
2255         bool shortgi = false;
2256         u8 rate_mask[5];
2257         u8 macid = 0;
2258         u8 mimops = 1;
2259
2260         ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2261         switch (wirelessmode) {
2262         case WIRELESS_MODE_B:
2263                 ratr_index = RATR_INX_WIRELESS_B;
2264                 if (ratr_bitmap & 0x0000000c)
2265                         ratr_bitmap &= 0x0000000d;
2266                 else
2267                         ratr_bitmap &= 0x0000000f;
2268                 break;
2269         case WIRELESS_MODE_G:
2270                 ratr_index = RATR_INX_WIRELESS_GB;
2271                 if (rssi_level == 1)
2272                         ratr_bitmap &= 0x00000f00;
2273                 else if (rssi_level == 2)
2274                         ratr_bitmap &= 0x00000ff0;
2275                 else
2276                         ratr_bitmap &= 0x00000ff5;
2277                 break;
2278         case WIRELESS_MODE_A:
2279                 ratr_index = RATR_INX_WIRELESS_A;
2280                 ratr_bitmap &= 0x00000ff0;
2281                 break;
2282         case WIRELESS_MODE_N_24G:
2283         case WIRELESS_MODE_N_5G:
2284                 ratr_index = RATR_INX_WIRELESS_NGB;
2285                 if (mimops == 0) {
2286                         if (rssi_level == 1)
2287                                 ratr_bitmap &= 0x00070000;
2288                         else if (rssi_level == 2)
2289                                 ratr_bitmap &= 0x0007f000;
2290                         else
2291                                 ratr_bitmap &= 0x0007f005;
2292                 } else {
2293                         if (rtlphy->rf_type == RF_1T2R ||
2294                             rtlphy->rf_type == RF_1T1R) {
2295                                 if (curtxbw_40mhz) {
2296                                         if (rssi_level == 1)
2297                                                 ratr_bitmap &= 0x000f0000;
2298                                         else if (rssi_level == 2)
2299                                                 ratr_bitmap &= 0x000ff000;
2300                                         else
2301                                                 ratr_bitmap &= 0x000ff015;
2302                                 } else {
2303                                         if (rssi_level == 1)
2304                                                 ratr_bitmap &= 0x000f0000;
2305                                         else if (rssi_level == 2)
2306                                                 ratr_bitmap &= 0x000ff000;
2307                                         else
2308                                                 ratr_bitmap &= 0x000ff005;
2309                                 }
2310                         } else {
2311                                 if (curtxbw_40mhz) {
2312                                         if (rssi_level == 1)
2313                                                 ratr_bitmap &= 0x0f0f0000;
2314                                         else if (rssi_level == 2)
2315                                                 ratr_bitmap &= 0x0f0ff000;
2316                                         else
2317                                                 ratr_bitmap &= 0x0f0ff015;
2318                                 } else {
2319                                         if (rssi_level == 1)
2320                                                 ratr_bitmap &= 0x0f0f0000;
2321                                         else if (rssi_level == 2)
2322                                                 ratr_bitmap &= 0x0f0ff000;
2323                                         else
2324                                                 ratr_bitmap &= 0x0f0ff005;
2325                                 }
2326                         }
2327                 }
2328                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2329                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2330                         if (macid == 0)
2331                                 shortgi = true;
2332                         else if (macid == 1)
2333                                 shortgi = false;
2334                 }
2335                 break;
2336         default:
2337                 ratr_index = RATR_INX_WIRELESS_NGB;
2338                 if (rtlphy->rf_type == RF_1T2R)
2339                         ratr_bitmap &= 0x000ff0ff;
2340                 else
2341                         ratr_bitmap &= 0x0f0ff0ff;
2342                 break;
2343         }
2344         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "ratr_bitmap :%x\n",
2345                  ratr_bitmap);
2346         *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2347                                       ratr_index << 28);
2348         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2349         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2350                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2351                  ratr_index, ratr_bitmap,
2352                  rate_mask[0], rate_mask[1], rate_mask[2], rate_mask[3],
2353                  rate_mask[4]);
2354         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2355 }
2356
2357 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2358 {
2359         struct rtl_priv *rtlpriv = rtl_priv(hw);
2360         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2361         u16 sifs_timer;
2362
2363         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2364                                       (u8 *)&mac->slot_time);
2365         if (!mac->ht_enable)
2366                 sifs_timer = 0x0a0a;
2367         else
2368                 sifs_timer = 0x0e0e;
2369         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2370 }
2371
2372 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2373 {
2374         struct rtl_priv *rtlpriv = rtl_priv(hw);
2375         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2376         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2377         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2378         u8 u1tmp = 0;
2379         bool actuallyset = false;
2380         unsigned long flag = 0;
2381         /* to do - usb autosuspend */
2382         u8 usb_autosuspend = 0;
2383
2384         if (ppsc->swrf_processing)
2385                 return false;
2386         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2387         if (ppsc->rfchange_inprogress) {
2388                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2389                 return false;
2390         } else {
2391                 ppsc->rfchange_inprogress = true;
2392                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2393         }
2394         cur_rfstate = ppsc->rfpwr_state;
2395         if (usb_autosuspend) {
2396                 /* to do................... */
2397         } else {
2398                 if (ppsc->pwrdown_mode) {
2399                         u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2400                         e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2401                                                ERFOFF : ERFON;
2402                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2403                                  "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2404                 } else {
2405                         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2406                                        rtl_read_byte(rtlpriv,
2407                                        REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2408                         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2409                         e_rfpowerstate_toset  = (u1tmp & BIT(3)) ?
2410                                                  ERFON : ERFOFF;
2411                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2412                                  "GPIO_IN=%02x\n", u1tmp);
2413                 }
2414                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2415                          e_rfpowerstate_toset);
2416         }
2417         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2418                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2419                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2420                 ppsc->hwradiooff = false;
2421                 actuallyset = true;
2422         } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset  ==
2423                     ERFOFF)) {
2424                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2425                          "GPIOChangeRF  - HW Radio OFF\n");
2426                 ppsc->hwradiooff = true;
2427                 actuallyset = true;
2428         } else {
2429                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2430                          "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2431                          ppsc->hwradiooff, e_rfpowerstate_toset);
2432         }
2433         if (actuallyset) {
2434                 ppsc->hwradiooff = true;
2435                 if (e_rfpowerstate_toset == ERFON) {
2436                         if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM) &&
2437                              RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2438                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2439                         else if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2440                                  && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2441                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2442                 }
2443                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2444                 ppsc->rfchange_inprogress = false;
2445                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2446                 /* For power down module, we need to enable register block
2447                  * contrl reg at 0x1c. Then enable power down control bit
2448                  * of register 0x04 BIT4 and BIT15 as 1.
2449                  */
2450                 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2451                         /* Enable register area 0x0-0xc. */
2452                         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2453                         if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2454                                 /*
2455                                  * We should configure HW PDn source for WiFi
2456                                  * ONLY, and then our HW will be set in
2457                                  * power-down mode if PDn source from all
2458                                  * functions are configured.
2459                                  */
2460                                 u1tmp = rtl_read_byte(rtlpriv,
2461                                                       REG_MULTI_FUNC_CTRL);
2462                                 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2463                                                (u1tmp|WL_HWPDN_EN));
2464                         } else {
2465                                 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2466                         }
2467                 }
2468                 if (e_rfpowerstate_toset == ERFOFF) {
2469                         if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2470                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2471                         else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2472                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2473                 }
2474         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2475                 /* Enter D3 or ASPM after GPIO had been done. */
2476                 if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2477                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2478                 else if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2479                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2480                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2481                 ppsc->rfchange_inprogress = false;
2482                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2483         } else {
2484                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2485                 ppsc->rfchange_inprogress = false;
2486                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2487         }
2488         *valid = 1;
2489         return !ppsc->hwradiooff;
2490 }