drivers/net/wireless/rtlwifi/rtl8192se/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include "../wifi.h"
  33 #include "../efuse.h"
  34 #include "../base.h"
  35 #include "../regd.h"
  36 #include "../cam.h"
  37 #include "../ps.h"
  38 #include "../pci.h"
  39 #include "reg.h"
  40 #include "def.h"
  41 #include "phy.h"
  42 #include "dm.h"
  43 #include "fw.h"
  44 #include "led.h"
  45 #include "hw.h"
  46
  47 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  48 {
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  51         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  52
  53         switch (variable) {
  54         case HW_VAR_RCR: {
  55                         *((u32 *) (val)) = rtlpci->receive_config;
  56                         break;
  57                 }
  58         case HW_VAR_RF_STATE: {
  59                         *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
  60                         break;
  61                 }
  62         case HW_VAR_FW_PSMODE_STATUS: {
  63                         *((bool *) (val)) = ppsc->fw_current_inpsmode;
  64                         break;
  65                 }
  66         case HW_VAR_CORRECT_TSF: {
  67                         u64 tsf;
  68                         u32 *ptsf_low = (u32 *)&tsf;
  69                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
  70
  71                         *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
  72                         *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
  73
  74                         *((u64 *) (val)) = tsf;
  75
  76                         break;
  77                 }
  78         case HW_VAR_MRC: {
  79                         *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
  80                         break;
  81                 }
  82         default: {
  83                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  84                          "switch case not processed\n");
  85                         break;
  86                 }
  87         }
  88 }
  89
  90 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  91 {
  92         struct rtl_priv *rtlpriv = rtl_priv(hw);
  93         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  94         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  95         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  96         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  97         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  98
  99         switch (variable) {
 100         case HW_VAR_ETHER_ADDR:{
 101                         rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
 102                         rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
 103                         break;
 104                 }
 105         case HW_VAR_BASIC_RATE:{
 106                         u16 rate_cfg = ((u16 *) val)[0];
 107                         u8 rate_index = 0;
 108
 109                         if (rtlhal->version == VERSION_8192S_ACUT)
 110                                 rate_cfg = rate_cfg & 0x150;
 111                         else
 112                                 rate_cfg = rate_cfg & 0x15f;
 113
 114                         rate_cfg |= 0x01;
 115
 116                         rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
 117                         rtl_write_byte(rtlpriv, RRSR + 1,
 118                                        (rate_cfg >> 8) & 0xff);
 119
 120                         while (rate_cfg > 0x1) {
 121                                 rate_cfg = (rate_cfg >> 1);
 122                                 rate_index++;
 123                         }
 124                         rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
 125
 126                         break;
 127                 }
 128         case HW_VAR_BSSID:{
 129                         rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
 130                         rtl_write_word(rtlpriv, BSSIDR + 4,
 131                                        ((u16 *)(val + 4))[0]);
 132                         break;
 133                 }
 134         case HW_VAR_SIFS:{
 135                         rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
 136                         rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
 137                         break;
 138                 }
 139         case HW_VAR_SLOT_TIME:{
 140                         u8 e_aci;
 141
 142                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 143                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 144
 145                         rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
 146
 147                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 148                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 149                                                 HW_VAR_AC_PARAM,
 150                                                 (u8 *)(&e_aci));
 151                         }
 152                         break;
 153                 }
 154         case HW_VAR_ACK_PREAMBLE:{
 155                         u8 reg_tmp;
 156                         u8 short_preamble = (bool) (*(u8 *) val);
 157                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 158                         if (short_preamble)
 159                                 reg_tmp |= 0x80;
 160
 161                         rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
 162                         break;
 163                 }
 164         case HW_VAR_AMPDU_MIN_SPACE:{
 165                         u8 min_spacing_to_set;
 166                         u8 sec_min_space;
 167
 168                         min_spacing_to_set = *((u8 *)val);
 169                         if (min_spacing_to_set <= 7) {
 170                                 if (rtlpriv->sec.pairwise_enc_algorithm ==
 171                                     NO_ENCRYPTION)
 172                                         sec_min_space = 0;
 173                                 else
 174                                         sec_min_space = 1;
 175
 176                                 if (min_spacing_to_set < sec_min_space)
 177                                         min_spacing_to_set = sec_min_space;
 178                                 if (min_spacing_to_set > 5)
 179                                         min_spacing_to_set = 5;
 180
 181                                 mac->min_space_cfg =
 182                                                 ((mac->min_space_cfg & 0xf8) |
 183                                                 min_spacing_to_set);
 184
 185                                 *val = min_spacing_to_set;
 186
 187                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 188                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 189                                          mac->min_space_cfg);
 190
 191                                 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 192                                                mac->min_space_cfg);
 193                         }
 194                         break;
 195                 }
 196         case HW_VAR_SHORTGI_DENSITY:{
 197                         u8 density_to_set;
 198
 199                         density_to_set = *((u8 *) val);
 200                         mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 201                         mac->min_space_cfg |= (density_to_set << 3);
 202
 203                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 204                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 205                                  mac->min_space_cfg);
 206
 207                         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 208                                        mac->min_space_cfg);
 209
 210                         break;
 211                 }
 212         case HW_VAR_AMPDU_FACTOR:{
 213                         u8 factor_toset;
 214                         u8 regtoset;
 215                         u8 factorlevel[18] = {
 216                                 2, 4, 4, 7, 7, 13, 13,
 217                                 13, 2, 7, 7, 13, 13,
 218                                 15, 15, 15, 15, 0};
 219                         u8 index = 0;
 220
 221                         factor_toset = *((u8 *) val);
 222                         if (factor_toset <= 3) {
 223                                 factor_toset = (1 << (factor_toset + 2));
 224                                 if (factor_toset > 0xf)
 225                                         factor_toset = 0xf;
 226
 227                                 for (index = 0; index < 17; index++) {
 228                                         if (factorlevel[index] > factor_toset)
 229                                                 factorlevel[index] =
 230                                                                  factor_toset;
 231                                 }
 232
 233                                 for (index = 0; index < 8; index++) {
 234                                         regtoset = ((factorlevel[index * 2]) |
 235                                                     (factorlevel[index *
 236                                                     2 + 1] << 4));
 237                                         rtl_write_byte(rtlpriv,
 238                                                        AGGLEN_LMT_L + index,
 239                                                        regtoset);
 240                                 }
 241
 242                                 regtoset = ((factorlevel[16]) |
 243                                             (factorlevel[17] << 4));
 244                                 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
 245
 246                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 247                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 248                                          factor_toset);
 249                         }
 250                         break;
 251                 }
 252         case HW_VAR_AC_PARAM:{
 253                         u8 e_aci = *((u8 *) val);
 254                         rtl92s_dm_init_edca_turbo(hw);
 255
 256                         if (rtlpci->acm_method != eAcmWay2_SW)
 257                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 258                                                  HW_VAR_ACM_CTRL,
 259                                                  (u8 *)(&e_aci));
 260                         break;
 261                 }
 262         case HW_VAR_ACM_CTRL:{
 263                         u8 e_aci = *((u8 *) val);
 264                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
 265                                                         mac->ac[0].aifs));
 266                         u8 acm = p_aci_aifsn->f.acm;
 267                         u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
 268
 269                         acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
 270                                    0x0 : 0x1);
 271
 272                         if (acm) {
 273                                 switch (e_aci) {
 274                                 case AC0_BE:
 275                                         acm_ctrl |= AcmHw_BeqEn;
 276                                         break;
 277                                 case AC2_VI:
 278                                         acm_ctrl |= AcmHw_ViqEn;
 279                                         break;
 280                                 case AC3_VO:
 281                                         acm_ctrl |= AcmHw_VoqEn;
 282                                         break;
 283                                 default:
 284                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 285                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 286                                                  acm);
 287                                         break;
 288                                 }
 289                         } else {
 290                                 switch (e_aci) {
 291                                 case AC0_BE:
 292                                         acm_ctrl &= (~AcmHw_BeqEn);
 293                                         break;
 294                                 case AC2_VI:
 295                                         acm_ctrl &= (~AcmHw_ViqEn);
 296                                         break;
 297                                 case AC3_VO:
 298                                         acm_ctrl &= (~AcmHw_BeqEn);
 299                                         break;
 300                                 default:
 301                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 302                                                  "switch case not processed\n");
 303                                         break;
 304                                 }
 305                         }
 306
 307                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 308                                  "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
 309                         rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
 310                         break;
 311                 }
 312         case HW_VAR_RCR:{
 313                         rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
 314                         rtlpci->receive_config = ((u32 *) (val))[0];
 315                         break;
 316                 }
 317         case HW_VAR_RETRY_LIMIT:{
 318                         u8 retry_limit = ((u8 *) (val))[0];
 319
 320                         rtl_write_word(rtlpriv, RETRY_LIMIT,
 321                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 322                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 323                         break;
 324                 }
 325         case HW_VAR_DUAL_TSF_RST: {
 326                         break;
 327                 }
 328         case HW_VAR_EFUSE_BYTES: {
 329                         rtlefuse->efuse_usedbytes = *((u16 *) val);
 330                         break;
 331                 }
 332         case HW_VAR_EFUSE_USAGE: {
 333                         rtlefuse->efuse_usedpercentage = *((u8 *) val);
 334                         break;
 335                 }
 336         case HW_VAR_IO_CMD: {
 337                         break;
 338                 }
 339         case HW_VAR_WPA_CONFIG: {
 340                         rtl_write_byte(rtlpriv, REG_SECR, *((u8 *) val));
 341                         break;
 342                 }
 343         case HW_VAR_SET_RPWM:{
 344                         break;
 345                 }
 346         case HW_VAR_H2C_FW_PWRMODE:{
 347                         break;
 348                 }
 349         case HW_VAR_FW_PSMODE_STATUS: {
 350                         ppsc->fw_current_inpsmode = *((bool *) val);
 351                         break;
 352                 }
 353         case HW_VAR_H2C_FW_JOINBSSRPT:{
 354                         break;
 355                 }
 356         case HW_VAR_AID:{
 357                         break;
 358                 }
 359         case HW_VAR_CORRECT_TSF:{
 360                         break;
 361                 }
 362         case HW_VAR_MRC: {
 363                         bool bmrc_toset = *((bool *)val);
 364                         u8 u1bdata = 0;
 365
 366                         if (bmrc_toset) {
 367                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 368                                               MASKBYTE0, 0x33);
 369                                 u1bdata = (u8)rtl_get_bbreg(hw,
 370                                                 ROFDM1_TRXPATHENABLE,
 371                                                 MASKBYTE0);
 372                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 373                                               MASKBYTE0,
 374                                               ((u1bdata & 0xf0) | 0x03));
 375                                 u1bdata = (u8)rtl_get_bbreg(hw,
 376                                                 ROFDM0_TRXPATHENABLE,
 377                                                 MASKBYTE1);
 378                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 379                                               MASKBYTE1,
 380                                               (u1bdata | 0x04));
 381
 382                                 /* Update current settings. */
 383                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 384                         } else {
 385                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 386                                               MASKBYTE0, 0x13);
 387                                 u1bdata = (u8)rtl_get_bbreg(hw,
 388                                                  ROFDM1_TRXPATHENABLE,
 389                                                  MASKBYTE0);
 390                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 391                                               MASKBYTE0,
 392                                               ((u1bdata & 0xf0) | 0x01));
 393                                 u1bdata = (u8)rtl_get_bbreg(hw,
 394                                                 ROFDM0_TRXPATHENABLE,
 395                                                 MASKBYTE1);
 396                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 397                                               MASKBYTE1, (u1bdata & 0xfb));
 398
 399                                 /* Update current settings. */
 400                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 401                         }
 402
 403                         break;
 404                 }
 405         default:
 406                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 407                          "switch case not processed\n");
 408                 break;
 409         }
 410
 411 }
 412
 413 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
 414 {
 415         struct rtl_priv *rtlpriv = rtl_priv(hw);
 416         u8 sec_reg_value = 0x0;
 417
 418         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 419                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 420                  rtlpriv->sec.pairwise_enc_algorithm,
 421                  rtlpriv->sec.group_enc_algorithm);
 422
 423         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 424                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 425                          "not open hw encryption\n");
 426                 return;
 427         }
 428
 429         sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 430
 431         if (rtlpriv->sec.use_defaultkey) {
 432                 sec_reg_value |= SCR_TXUSEDK;
 433                 sec_reg_value |= SCR_RXUSEDK;
 434         }
 435
 436         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
 437                  sec_reg_value);
 438
 439         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 440
 441 }
 442
 443 static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
 444 {
 445         struct rtl_priv *rtlpriv = rtl_priv(hw);
 446         u8 waitcount = 100;
 447         bool bresult = false;
 448         u8 tmpvalue;
 449
 450         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
 451
 452         /* Wait the MAC synchronized. */
 453         udelay(400);
 454
 455         /* Check if it is set ready. */
 456         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 457         bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
 458
 459         if ((data & (BIT(6) | BIT(7))) == false) {
 460                 waitcount = 100;
 461                 tmpvalue = 0;
 462
 463                 while (1) {
 464                         waitcount--;
 465
 466                         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 467                         if ((tmpvalue & BIT(6)))
 468                                 break;
 469
 470                         pr_err("wait for BIT(6) return value %x\n", tmpvalue);
 471                         if (waitcount == 0)
 472                                 break;
 473
 474                         udelay(10);
 475                 }
 476
 477                 if (waitcount == 0)
 478                         bresult = false;
 479                 else
 480                         bresult = true;
 481         }
 482
 483         return bresult;
 484 }
 485
 486 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
 487 {
 488         struct rtl_priv *rtlpriv = rtl_priv(hw);
 489         u8 u1tmp;
 490
 491         /* The following config GPIO function */
 492         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 493         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 494
 495         /* config GPIO3 to input */
 496         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 497         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 498
 499 }
 500
 501 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
 502 {
 503         struct rtl_priv *rtlpriv = rtl_priv(hw);
 504         u8 u1tmp;
 505         u8 retval = ERFON;
 506
 507         /* The following config GPIO function */
 508         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 509         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 510
 511         /* config GPIO3 to input */
 512         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 513         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 514
 515         /* On some of the platform, driver cannot read correct
 516          * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
 517         mdelay(10);
 518
 519         /* check GPIO3 */
 520         u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
 521         retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
 522
 523         return retval;
 524 }
 525
 526 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
 527 {
 528         struct rtl_priv *rtlpriv = rtl_priv(hw);
 529         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 530         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 531
 532         u8 i;
 533         u8 tmpu1b;
 534         u16 tmpu2b;
 535         u8 pollingcnt = 20;
 536
 537         if (rtlpci->first_init) {
 538                 /* Reset PCIE Digital */
 539                 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 540                 tmpu1b &= 0xFE;
 541                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 542                 udelay(1);
 543                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
 544         }
 545
 546         /* Switch to SW IO control */
 547         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 548         if (tmpu1b & BIT(7)) {
 549                 tmpu1b &= ~(BIT(6) | BIT(7));
 550
 551                 /* Set failed, return to prevent hang. */
 552                 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 553                         return;
 554         }
 555
 556         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
 557         udelay(50);
 558         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 559         udelay(50);
 560
 561         /* Clear FW RPWM for FW control LPS.*/
 562         rtl_write_byte(rtlpriv, RPWM, 0x0);
 563
 564         /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
 565         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 566         tmpu1b &= 0x73;
 567         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 568         /* wait for BIT 10/11/15 to pull high automatically!! */
 569         mdelay(1);
 570
 571         rtl_write_byte(rtlpriv, CMDR, 0);
 572         rtl_write_byte(rtlpriv, TCR, 0);
 573
 574         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
 575         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
 576         tmpu1b |= 0x08;
 577         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 578         tmpu1b &= ~(BIT(3));
 579         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 580
 581         /* Enable AFE clock source */
 582         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
 583         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
 584         /* Delay 1.5ms */
 585         mdelay(2);
 586         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
 587         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
 588
 589         /* Enable AFE Macro Block's Bandgap */
 590         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 591         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
 592         mdelay(1);
 593
 594         /* Enable AFE Mbias */
 595         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 596         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
 597         mdelay(1);
 598
 599         /* Enable LDOA15 block  */
 600         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
 601         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
 602
 603         /* Set Digital Vdd to Retention isolation Path. */
 604         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 605         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
 606
 607         /* For warm reboot NIC disappera bug. */
 608         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 609         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
 610
 611         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
 612
 613         /* Enable AFE PLL Macro Block */
 614         /* We need to delay 100u before enabling PLL. */
 615         udelay(200);
 616         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
 617         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 618
 619         /* for divider reset  */
 620         udelay(100);
 621         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
 622                        BIT(4) | BIT(6)));
 623         udelay(10);
 624         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 625         udelay(10);
 626
 627         /* Enable MAC 80MHZ clock  */
 628         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
 629         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
 630         mdelay(1);
 631
 632         /* Release isolation AFE PLL & MD */
 633         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
 634
 635         /* Enable MAC clock */
 636         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 637         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
 638
 639         /* Enable Core digital and enable IOREG R/W */
 640         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 641         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
 642
 643         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 644         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
 645
 646         /* enable REG_EN */
 647         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
 648
 649         /* Switch the control path. */
 650         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 651         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
 652
 653         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 654         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
 655         if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 656                 return; /* Set failed, return to prevent hang. */
 657
 658         rtl_write_word(rtlpriv, CMDR, 0x07FC);
 659
 660         /* MH We must enable the section of code to prevent load IMEM fail. */
 661         /* Load MAC register from WMAc temporarily We simulate macreg. */
 662         /* txt HW will provide MAC txt later  */
 663         rtl_write_byte(rtlpriv, 0x6, 0x30);
 664         rtl_write_byte(rtlpriv, 0x49, 0xf0);
 665
 666         rtl_write_byte(rtlpriv, 0x4b, 0x81);
 667
 668         rtl_write_byte(rtlpriv, 0xb5, 0x21);
 669
 670         rtl_write_byte(rtlpriv, 0xdc, 0xff);
 671         rtl_write_byte(rtlpriv, 0xdd, 0xff);
 672         rtl_write_byte(rtlpriv, 0xde, 0xff);
 673         rtl_write_byte(rtlpriv, 0xdf, 0xff);
 674
 675         rtl_write_byte(rtlpriv, 0x11a, 0x00);
 676         rtl_write_byte(rtlpriv, 0x11b, 0x00);
 677
 678         for (i = 0; i < 32; i++)
 679                 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
 680
 681         rtl_write_byte(rtlpriv, 0x236, 0xff);
 682
 683         rtl_write_byte(rtlpriv, 0x503, 0x22);
 684
 685         if (ppsc->support_aspm && !ppsc->support_backdoor)
 686                 rtl_write_byte(rtlpriv, 0x560, 0x40);
 687         else
 688                 rtl_write_byte(rtlpriv, 0x560, 0x00);
 689
 690         rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
 691
 692         /* Set RX Desc Address */
 693         rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 694         rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
 695
 696         /* Set TX Desc Address */
 697         rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
 698         rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
 699         rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
 700         rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
 701         rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
 702         rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
 703         rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 704         rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 705         rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
 706
 707         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 708
 709         /* To make sure that TxDMA can ready to download FW. */
 710         /* We should reset TxDMA if IMEM RPT was not ready. */
 711         do {
 712                 tmpu1b = rtl_read_byte(rtlpriv, TCR);
 713                 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
 714                         break;
 715
 716                 udelay(5);
 717         } while (pollingcnt--);
 718
 719         if (pollingcnt <= 0) {
 720                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 721                          "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
 722                          tmpu1b);
 723                 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
 724                 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
 725                 udelay(2);
 726                 /* Reset TxDMA */
 727                 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
 728         }
 729
 730         /* After MACIO reset,we must refresh LED state. */
 731         if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
 732            (ppsc->rfoff_reason == 0)) {
 733                 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 734                 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 735                 enum rf_pwrstate rfpwr_state_toset;
 736                 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
 737
 738                 if (rfpwr_state_toset == ERFON)
 739                         rtl92se_sw_led_on(hw, pLed0);
 740         }
 741 }
 742
 743 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
 744 {
 745         struct rtl_priv *rtlpriv = rtl_priv(hw);
 746         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 747         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 748         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 749         u8 i;
 750         u16 tmpu2b;
 751
 752         /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
 753
 754         /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
 755         /* Turn on 0x40 Command register */
 756         rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
 757                         SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
 758                         RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
 759
 760         /* Set TCR TX DMA pre 2 FULL enable bit */
 761         rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
 762                         TXDMAPRE2FULL);
 763
 764         /* Set RCR      */
 765         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
 766
 767         /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
 768
 769         /* 4. Timing Control Register  (Offset: 0x0080 - 0x009F) */
 770         /* Set CCK/OFDM SIFS */
 771         /* CCK SIFS shall always be 10us. */
 772         rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
 773         rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
 774
 775         /* Set AckTimeout */
 776         rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
 777
 778         /* Beacon related */
 779         rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
 780         rtl_write_word(rtlpriv, ATIMWND, 2);
 781
 782         /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
 783         /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
 784         /* Firmware allocate now, associate with FW internal setting.!!! */
 785
 786         /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
 787         /* 5.3 Set driver info, we only accept PHY status now. */
 788         /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO  */
 789         rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
 790
 791         /* 6. Adaptive Control Register  (Offset: 0x0160 - 0x01CF) */
 792         /* Set RRSR to all legacy rate and HT rate
 793          * CCK rate is supported by default.
 794          * CCK rate will be filtered out only when associated
 795          * AP does not support it.
 796          * Only enable ACK rate to OFDM 24M
 797          * Disable RRSR for CCK rate in A-Cut   */
 798
 799         if (rtlhal->version == VERSION_8192S_ACUT)
 800                 rtl_write_byte(rtlpriv, RRSR, 0xf0);
 801         else if (rtlhal->version == VERSION_8192S_BCUT)
 802                 rtl_write_byte(rtlpriv, RRSR, 0xff);
 803         rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
 804         rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
 805
 806         /* A-Cut IC do not support CCK rate. We forbid ARFR to */
 807         /* fallback to CCK rate */
 808         for (i = 0; i < 8; i++) {
 809                 /*Disable RRSR for CCK rate in A-Cut */
 810                 if (rtlhal->version == VERSION_8192S_ACUT)
 811                         rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
 812         }
 813
 814         /* Different rate use different AMPDU size */
 815         /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
 816         rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
 817         /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
 818         rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
 819         /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
 820         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
 821         /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
 822         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
 823         /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
 824         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
 825
 826         /* Set Data / Response auto rate fallack retry count */
 827         rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
 828         rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
 829         rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
 830         rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
 831
 832         /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
 833         /* Set all rate to support SG */
 834         rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
 835
 836         /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
 837         /* Set NAV protection length */
 838         rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
 839         /* CF-END Threshold */
 840         rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
 841         /* Set AMPDU minimum space */
 842         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
 843         /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
 844         rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
 845
 846         /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
 847         /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
 848         /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
 849         /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
 850         /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
 851
 852         /* 14. Set driver info, we only accept PHY status now. */
 853         rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
 854
 855         /* 15. For EEPROM R/W Workaround */
 856         /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
 857         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 858         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
 859         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 860         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
 861
 862         /* 17. For EFUSE */
 863         /* We may R/W EFUSE in EEPROM mode */
 864         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 865                 u8      tempval;
 866
 867                 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
 868                 tempval &= 0xFE;
 869                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
 870
 871                 /* Change Program timing */
 872                 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
 873                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
 874         }
 875
 876         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
 877
 878 }
 879
 880 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
 881 {
 882         struct rtl_priv *rtlpriv = rtl_priv(hw);
 883         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 884         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 885         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 886
 887         u8 reg_bw_opmode = 0;
 888         u32 reg_rrsr = 0;
 889         u8 regtmp = 0;
 890
 891         reg_bw_opmode = BW_OPMODE_20MHZ;
 892         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 893
 894         regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
 895         reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
 896         rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
 897         rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 898
 899         /* Set Retry Limit here */
 900         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
 901                         (u8 *)(&rtlpci->shortretry_limit));
 902
 903         rtl_write_byte(rtlpriv, MLT, 0x8f);
 904
 905         /* For Min Spacing configuration. */
 906         switch (rtlphy->rf_type) {
 907         case RF_1T2R:
 908         case RF_1T1R:
 909                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 910                 break;
 911         case RF_2T2R:
 912         case RF_2T2R_GREEN:
 913                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 914                 break;
 915         }
 916         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
 917 }
 918
 919 int rtl92se_hw_init(struct ieee80211_hw *hw)
 920 {
 921         struct rtl_priv *rtlpriv = rtl_priv(hw);
 922         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 923         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 924         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 925         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 926         u8 tmp_byte = 0;
 927
 928         bool rtstatus = true;
 929         u8 tmp_u1b;
 930         int err = false;
 931         u8 i;
 932         int wdcapra_add[] = {
 933                 EDCAPARA_BE, EDCAPARA_BK,
 934                 EDCAPARA_VI, EDCAPARA_VO};
 935         u8 secr_value = 0x0;
 936
 937         rtlpci->being_init_adapter = true;
 938
 939         rtlpriv->intf_ops->disable_aspm(hw);
 940
 941         /* 1. MAC Initialize */
 942         /* Before FW download, we have to set some MAC register */
 943         _rtl92se_macconfig_before_fwdownload(hw);
 944
 945         rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
 946                         PMC_FSM) >> 16) & 0xF);
 947
 948         rtl8192se_gpiobit3_cfg_inputmode(hw);
 949
 950         /* 2. download firmware */
 951         rtstatus = rtl92s_download_fw(hw);
 952         if (!rtstatus) {
 953                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 954                          "Failed to download FW. Init HW without FW now... Please copy FW into /lib/firmware/rtlwifi\n");
 955                 rtlhal->fw_ready = false;
 956         } else {
 957                 rtlhal->fw_ready = true;
 958         }
 959
 960         /* After FW download, we have to reset MAC register */
 961         _rtl92se_macconfig_after_fwdownload(hw);
 962
 963         /*Retrieve default FW Cmd IO map. */
 964         rtlhal->fwcmd_iomap =   rtl_read_word(rtlpriv, LBUS_MON_ADDR);
 965         rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
 966
 967         /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
 968         if (rtl92s_phy_mac_config(hw) != true) {
 969                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
 970                 return rtstatus;
 971         }
 972
 973         /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
 974         /* We must set flag avoid BB/RF config period later!! */
 975         rtl_write_dword(rtlpriv, CMDR, 0x37FC);
 976
 977         /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
 978         if (rtl92s_phy_bb_config(hw) != true) {
 979                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
 980                 return rtstatus;
 981         }
 982
 983         /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
 984         /* Before initalizing RF. We can not use FW to do RF-R/W. */
 985
 986         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 987
 988         /* RF Power Save */
 989 #if 0
 990         /* H/W or S/W RF OFF before sleep. */
 991         if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
 992                 u32 rfoffreason = rtlpriv->psc.rfoff_reason;
 993
 994                 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
 995                 rtlpriv->psc.rfpwr_state = ERFON;
 996                 /* FIXME: check spinlocks if this block is uncommented */
 997                 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason);
 998         } else {
 999                 /* gpio radio on/off is out of adapter start */
1000                 if (rtlpriv->psc.hwradiooff == false) {
1001                         rtlpriv->psc.rfpwr_state = ERFON;
1002                         rtlpriv->psc.rfoff_reason = 0;
1003                 }
1004         }
1005 #endif
1006
1007         /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1008         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1009         if (rtlhal->version == VERSION_8192S_ACUT)
1010                 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1011         else
1012                 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1013
1014         if (rtl92s_phy_rf_config(hw) != true) {
1015                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1016                 return rtstatus;
1017         }
1018
1019         /* After read predefined TXT, we must set BB/MAC/RF
1020          * register as our requirement */
1021
1022         rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1023                                                            (enum radio_path)0,
1024                                                            RF_CHNLBW,
1025                                                            RFREG_OFFSET_MASK);
1026         rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1027                                                            (enum radio_path)1,
1028                                                            RF_CHNLBW,
1029                                                            RFREG_OFFSET_MASK);
1030
1031         /*---- Set CCK and OFDM Block "ON"----*/
1032         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1033         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1034
1035         /*3 Set Hardware(Do nothing now) */
1036         _rtl92se_hw_configure(hw);
1037
1038         /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1039         /* TX power index for different rate set. */
1040         /* Get original hw reg values */
1041         rtl92s_phy_get_hw_reg_originalvalue(hw);
1042         /* Write correct tx power index */
1043         rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1044
1045         /* We must set MAC address after firmware download. */
1046         for (i = 0; i < 6; i++)
1047                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1048
1049         /* EEPROM R/W workaround */
1050         tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1051         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1052
1053         rtl_write_byte(rtlpriv, 0x4d, 0x0);
1054
1055         if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1056                 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1057                 tmp_byte = tmp_byte | BIT(5);
1058                 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1059                 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1060         }
1061
1062         /* We enable high power and RA related mechanism after NIC
1063          * initialized. */
1064         rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1065
1066         /* Add to prevent ASPM bug. */
1067         /* Always enable hst and NIC clock request. */
1068         rtl92s_phy_switch_ephy_parameter(hw);
1069
1070         /* Security related
1071          * 1. Clear all H/W keys.
1072          * 2. Enable H/W encryption/decryption. */
1073         rtl_cam_reset_all_entry(hw);
1074         secr_value |= SCR_TXENCENABLE;
1075         secr_value |= SCR_RXENCENABLE;
1076         secr_value |= SCR_NOSKMC;
1077         rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1078
1079         for (i = 0; i < 4; i++)
1080                 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1081
1082         if (rtlphy->rf_type == RF_1T2R) {
1083                 bool mrc2set = true;
1084                 /* Turn on B-Path */
1085                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1086         }
1087
1088         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1089         rtl92s_dm_init(hw);
1090         rtlpci->being_init_adapter = false;
1091
1092         return err;
1093 }
1094
1095 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 * addr)
1096 {
1097 }
1098
1099 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1100 {
1101         struct rtl_priv *rtlpriv = rtl_priv(hw);
1102         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1103         u32 reg_rcr = rtlpci->receive_config;
1104
1105         if (rtlpriv->psc.rfpwr_state != ERFON)
1106                 return;
1107
1108         if (check_bssid) {
1109                 reg_rcr |= (RCR_CBSSID);
1110                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1111         } else if (check_bssid == false) {
1112                 reg_rcr &= (~RCR_CBSSID);
1113                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1114         }
1115
1116 }
1117
1118 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1119                                      enum nl80211_iftype type)
1120 {
1121         struct rtl_priv *rtlpriv = rtl_priv(hw);
1122         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1123         u32 temp;
1124         bt_msr &= ~MSR_LINK_MASK;
1125
1126         switch (type) {
1127         case NL80211_IFTYPE_UNSPECIFIED:
1128                 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1129                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1130                          "Set Network type to NO LINK!\n");
1131                 break;
1132         case NL80211_IFTYPE_ADHOC:
1133                 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1134                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1135                          "Set Network type to Ad Hoc!\n");
1136                 break;
1137         case NL80211_IFTYPE_STATION:
1138                 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1139                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1140                          "Set Network type to STA!\n");
1141                 break;
1142         case NL80211_IFTYPE_AP:
1143                 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1144                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1145                          "Set Network type to AP!\n");
1146                 break;
1147         default:
1148                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1149                          "Network type %d not supported!\n", type);
1150                 return 1;
1151                 break;
1152
1153         }
1154
1155         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1156
1157         temp = rtl_read_dword(rtlpriv, TCR);
1158         rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1159         rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1160
1161
1162         return 0;
1163 }
1164
1165 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1166 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1167 {
1168         struct rtl_priv *rtlpriv = rtl_priv(hw);
1169
1170         if (_rtl92se_set_media_status(hw, type))
1171                 return -EOPNOTSUPP;
1172
1173         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1174                 if (type != NL80211_IFTYPE_AP)
1175                         rtl92se_set_check_bssid(hw, true);
1176         } else {
1177                 rtl92se_set_check_bssid(hw, false);
1178         }
1179
1180         return 0;
1181 }
1182
1183 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1184 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1185 {
1186         struct rtl_priv *rtlpriv = rtl_priv(hw);
1187         rtl92s_dm_init_edca_turbo(hw);
1188
1189         switch (aci) {
1190         case AC1_BK:
1191                 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1192                 break;
1193         case AC0_BE:
1194                 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1195                 break;
1196         case AC2_VI:
1197                 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1198                 break;
1199         case AC3_VO:
1200                 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1201                 break;
1202         default:
1203                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1204                 break;
1205         }
1206 }
1207
1208 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1209 {
1210         struct rtl_priv *rtlpriv = rtl_priv(hw);
1211         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1212
1213         rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1214         /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1215         rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1216 }
1217
1218 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1219 {
1220         struct rtl_priv *rtlpriv = rtl_priv(hw);
1221         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1222
1223         rtl_write_dword(rtlpriv, INTA_MASK, 0);
1224         rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1225
1226         synchronize_irq(rtlpci->pdev->irq);
1227 }
1228
1229
1230 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1231 {
1232         struct rtl_priv *rtlpriv = rtl_priv(hw);
1233         u8 waitcnt = 100;
1234         bool result = false;
1235         u8 tmp;
1236
1237         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1238
1239         /* Wait the MAC synchronized. */
1240         udelay(400);
1241
1242         /* Check if it is set ready. */
1243         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1244         result = ((tmp & BIT(7)) == (data & BIT(7)));
1245
1246         if ((data & (BIT(6) | BIT(7))) == false) {
1247                 waitcnt = 100;
1248                 tmp = 0;
1249
1250                 while (1) {
1251                         waitcnt--;
1252                         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1253
1254                         if ((tmp & BIT(6)))
1255                                 break;
1256
1257                         pr_err("wait for BIT(6) return value %x\n", tmp);
1258
1259                         if (waitcnt == 0)
1260                                 break;
1261                         udelay(10);
1262                 }
1263
1264                 if (waitcnt == 0)
1265                         result = false;
1266                 else
1267                         result = true;
1268         }
1269
1270         return result;
1271 }
1272
1273 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1274 {
1275         struct rtl_priv *rtlpriv = rtl_priv(hw);
1276         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1277         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1278         u8 u1btmp;
1279
1280         if (rtlhal->driver_going2unload)
1281                 rtl_write_byte(rtlpriv, 0x560, 0x0);
1282
1283         /* Power save for BB/RF */
1284         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1285         u1btmp |= BIT(0);
1286         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1287         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1288         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1289         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1290         udelay(100);
1291         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1292         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1293         udelay(10);
1294         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1295         udelay(10);
1296         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1297         udelay(10);
1298         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1299         rtl_write_word(rtlpriv, CMDR, 0x0000);
1300
1301         if (rtlhal->driver_going2unload) {
1302                 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1303                 u1btmp &= ~(BIT(0));
1304                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1305         }
1306
1307         u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1308
1309         /* Add description. After switch control path. register
1310          * after page1 will be invisible. We can not do any IO
1311          * for register>0x40. After resume&MACIO reset, we need
1312          * to remember previous reg content. */
1313         if (u1btmp & BIT(7)) {
1314                 u1btmp &= ~(BIT(6) | BIT(7));
1315                 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1316                         pr_err("Switch ctrl path fail\n");
1317                         return;
1318                 }
1319         }
1320
1321         /* Power save for MAC */
1322         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS  &&
1323                 !rtlhal->driver_going2unload) {
1324                 /* enable LED function */
1325                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1326         /* SW/HW radio off or halt adapter!! For example S3/S4 */
1327         } else {
1328                 /* LED function disable. Power range is about 8mA now. */
1329                 /* if write 0xF1 disconnet_pci power
1330                  *       ifconfig wlan0 down power are both high 35:70 */
1331                 /* if write oxF9 disconnet_pci power
1332                  * ifconfig wlan0 down power are both low  12:45*/
1333                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1334         }
1335
1336         rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1337         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1338         rtl_write_byte(rtlpriv,  AFE_PLL_CTRL, 0x00);
1339         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1340         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1341         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1342
1343 }
1344
1345 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1346 {
1347         struct rtl_priv *rtlpriv = rtl_priv(hw);
1348         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1349         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1350         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1351
1352         if (rtlpci->up_first_time == 1)
1353                 return;
1354
1355         if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1356                 rtl92se_sw_led_on(hw, pLed0);
1357         else
1358                 rtl92se_sw_led_off(hw, pLed0);
1359 }
1360
1361
1362 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1363 {
1364         struct rtl_priv *rtlpriv = rtl_priv(hw);
1365         u16 tmpu2b;
1366         u8 tmpu1b;
1367
1368         rtlpriv->psc.pwrdomain_protect = true;
1369
1370         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1371         if (tmpu1b & BIT(7)) {
1372                 tmpu1b &= ~(BIT(6) | BIT(7));
1373                 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1374                         rtlpriv->psc.pwrdomain_protect = false;
1375                         return;
1376                 }
1377         }
1378
1379         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1380         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1381
1382         /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1383         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1384
1385         /* If IPS we need to turn LED on. So we not
1386          * not disable BIT 3/7 of reg3. */
1387         if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1388                 tmpu1b &= 0xFB;
1389         else
1390                 tmpu1b &= 0x73;
1391
1392         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1393         /* wait for BIT 10/11/15 to pull high automatically!! */
1394         mdelay(1);
1395
1396         rtl_write_byte(rtlpriv, CMDR, 0);
1397         rtl_write_byte(rtlpriv, TCR, 0);
1398
1399         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1400         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1401         tmpu1b |= 0x08;
1402         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1403         tmpu1b &= ~(BIT(3));
1404         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1405
1406         /* Enable AFE clock source */
1407         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1408         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1409         /* Delay 1.5ms */
1410         udelay(1500);
1411         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1412         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1413
1414         /* Enable AFE Macro Block's Bandgap */
1415         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1416         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1417         mdelay(1);
1418
1419         /* Enable AFE Mbias */
1420         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1421         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1422         mdelay(1);
1423
1424         /* Enable LDOA15 block */
1425         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1426         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1427
1428         /* Set Digital Vdd to Retention isolation Path. */
1429         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1430         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1431
1432
1433         /* For warm reboot NIC disappera bug. */
1434         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1435         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1436
1437         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1438
1439         /* Enable AFE PLL Macro Block */
1440         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1441         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1442         /* Enable MAC 80MHZ clock */
1443         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1444         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1445         mdelay(1);
1446
1447         /* Release isolation AFE PLL & MD */
1448         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1449
1450         /* Enable MAC clock */
1451         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1452         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1453
1454         /* Enable Core digital and enable IOREG R/W */
1455         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1456         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1457         /* enable REG_EN */
1458         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1459
1460         /* Switch the control path. */
1461         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1462         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1463
1464         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1465         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1466         if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1467                 rtlpriv->psc.pwrdomain_protect = false;
1468                 return;
1469         }
1470
1471         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1472
1473         /* After MACIO reset,we must refresh LED state. */
1474         _rtl92se_gen_refreshledstate(hw);
1475
1476         rtlpriv->psc.pwrdomain_protect = false;
1477 }
1478
1479 void rtl92se_card_disable(struct ieee80211_hw *hw)
1480 {
1481         struct rtl_priv *rtlpriv = rtl_priv(hw);
1482         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1483         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1484         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1485         enum nl80211_iftype opmode;
1486         u8 wait = 30;
1487
1488         rtlpriv->intf_ops->enable_aspm(hw);
1489
1490         if (rtlpci->driver_is_goingto_unload ||
1491                 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1492                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1493
1494         /* we should chnge GPIO to input mode
1495          * this will drop away current about 25mA*/
1496         rtl8192se_gpiobit3_cfg_inputmode(hw);
1497
1498         /* this is very important for ips power save */
1499         while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1500                 if (rtlpriv->psc.pwrdomain_protect)
1501                         mdelay(20);
1502                 else
1503                         break;
1504         }
1505
1506         mac->link_state = MAC80211_NOLINK;
1507         opmode = NL80211_IFTYPE_UNSPECIFIED;
1508         _rtl92se_set_media_status(hw, opmode);
1509
1510         _rtl92s_phy_set_rfhalt(hw);
1511         udelay(100);
1512 }
1513
1514 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1515                              u32 *p_intb)
1516 {
1517         struct rtl_priv *rtlpriv = rtl_priv(hw);
1518         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1519
1520         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1521         rtl_write_dword(rtlpriv, ISR, *p_inta);
1522
1523         *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1524         rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1525 }
1526
1527 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1528 {
1529         struct rtl_priv *rtlpriv = rtl_priv(hw);
1530         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1531         u16 bcntime_cfg = 0;
1532         u16 bcn_cw = 6, bcn_ifs = 0xf;
1533         u16 atim_window = 2;
1534
1535         /* ATIM Window (in unit of TU). */
1536         rtl_write_word(rtlpriv, ATIMWND, atim_window);
1537
1538         /* Beacon interval (in unit of TU). */
1539         rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1540
1541         /* DrvErlyInt (in unit of TU). (Time to send
1542          * interrupt to notify driver to change
1543          * beacon content) */
1544         rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1545
1546         /* BcnDMATIM(in unit of us). Indicates the
1547          * time before TBTT to perform beacon queue DMA  */
1548         rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1549
1550         /* Force beacon frame transmission even
1551          * after receiving beacon frame from
1552          * other ad hoc STA */
1553         rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1554
1555         /* Beacon Time Configuration */
1556         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1557                 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1558
1559         /* TODO: bcn_ifs may required to be changed on ASIC */
1560         bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1561
1562         /*for beacon changed */
1563         rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1564 }
1565
1566 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1567 {
1568         struct rtl_priv *rtlpriv = rtl_priv(hw);
1569         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1570         u16 bcn_interval = mac->beacon_interval;
1571
1572         /* Beacon interval (in unit of TU). */
1573         rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1574         /* 2008.10.24 added by tynli for beacon changed. */
1575         rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1576 }
1577
1578 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1579                 u32 add_msr, u32 rm_msr)
1580 {
1581         struct rtl_priv *rtlpriv = rtl_priv(hw);
1582         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1583
1584         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1585                  add_msr, rm_msr);
1586
1587         if (add_msr)
1588                 rtlpci->irq_mask[0] |= add_msr;
1589
1590         if (rm_msr)
1591                 rtlpci->irq_mask[0] &= (~rm_msr);
1592
1593         rtl92se_disable_interrupt(hw);
1594         rtl92se_enable_interrupt(hw);
1595 }
1596
1597 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1598 {
1599         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1600         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1601         u8 efuse_id;
1602
1603         rtlhal->ic_class = IC_INFERIORITY_A;
1604
1605         /* Only retrieving while using EFUSE. */
1606         if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1607                 !rtlefuse->autoload_failflag) {
1608                 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1609
1610                 if (efuse_id == 0xfe)
1611                         rtlhal->ic_class = IC_INFERIORITY_B;
1612         }
1613 }
1614
1615 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1616 {
1617         struct rtl_priv *rtlpriv = rtl_priv(hw);
1618         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1619         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1620         u16 i, usvalue;
1621         u16     eeprom_id;
1622         u8 tempval;
1623         u8 hwinfo[HWSET_MAX_SIZE_92S];
1624         u8 rf_path, index;
1625
1626         if (rtlefuse->epromtype == EEPROM_93C46) {
1627                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1628                          "RTL819X Not boot from eeprom, check it !!\n");
1629         } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1630                 rtl_efuse_shadow_map_update(hw);
1631
1632                 memcpy((void *)hwinfo, (void *)
1633                         &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1634                         HWSET_MAX_SIZE_92S);
1635         }
1636
1637         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1638                       hwinfo, HWSET_MAX_SIZE_92S);
1639
1640         eeprom_id = *((u16 *)&hwinfo[0]);
1641         if (eeprom_id != RTL8190_EEPROM_ID) {
1642                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1643                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1644                 rtlefuse->autoload_failflag = true;
1645         } else {
1646                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1647                 rtlefuse->autoload_failflag = false;
1648         }
1649
1650         if (rtlefuse->autoload_failflag)
1651                 return;
1652
1653         _rtl8192se_get_IC_Inferiority(hw);
1654
1655         /* Read IC Version && Channel Plan */
1656         /* VID, DID      SE     0xA-D */
1657         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1658         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1659         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1660         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1661         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1662
1663         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1664                  "EEPROMId = 0x%4x\n", eeprom_id);
1665         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1666                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1667         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1668                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1669         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1670                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1671         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1672                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1673
1674         for (i = 0; i < 6; i += 2) {
1675                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1676                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1677         }
1678
1679         for (i = 0; i < 6; i++)
1680                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1681
1682         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1683
1684         /* Get Tx Power Level by Channel */
1685         /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1686         /* 92S suupport RF A & B */
1687         for (rf_path = 0; rf_path < 2; rf_path++) {
1688                 for (i = 0; i < 3; i++) {
1689                         /* Read CCK RF A & B Tx power  */
1690                         rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1691                         hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1692
1693                         /* Read OFDM RF A & B Tx power for 1T */
1694                         rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1695                         hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1696
1697                         /* Read OFDM RF A & B Tx power for 2T */
1698                         rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]
1699                                  = hwinfo[EEPROM_TXPOWERBASE + 12 +
1700                                    rf_path * 3 + i];
1701                 }
1702         }
1703
1704         for (rf_path = 0; rf_path < 2; rf_path++)
1705                 for (i = 0; i < 3; i++)
1706                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1707                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1708                                 rf_path, i,
1709                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1710                                 [rf_path][i]);
1711         for (rf_path = 0; rf_path < 2; rf_path++)
1712                 for (i = 0; i < 3; i++)
1713                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1714                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1715                                 rf_path, i,
1716                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1717                                 [rf_path][i]);
1718         for (rf_path = 0; rf_path < 2; rf_path++)
1719                 for (i = 0; i < 3; i++)
1720                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1721                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1722                                 rf_path, i,
1723                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1724                                 [rf_path][i]);
1725
1726         for (rf_path = 0; rf_path < 2; rf_path++) {
1727
1728                 /* Assign dedicated channel tx power */
1729                 for (i = 0; i < 14; i++)        {
1730                         /* channel 1~3 use the same Tx Power Level. */
1731                         if (i < 3)
1732                                 index = 0;
1733                         /* Channel 4-8 */
1734                         else if (i < 8)
1735                                 index = 1;
1736                         /* Channel 9-14 */
1737                         else
1738                                 index = 2;
1739
1740                         /* Record A & B CCK /OFDM - 1T/2T Channel area
1741                          * tx power */
1742                         rtlefuse->txpwrlevel_cck[rf_path][i]  =
1743                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1744                                                         [rf_path][index];
1745                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i]  =
1746                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1747                                                         [rf_path][index];
1748                         rtlefuse->txpwrlevel_ht40_2s[rf_path][i]  =
1749                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1750                                                         [rf_path][index];
1751                 }
1752
1753                 for (i = 0; i < 14; i++) {
1754                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1755                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1756                                 rf_path, i,
1757                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1758                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1759                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1760                 }
1761         }
1762
1763         for (rf_path = 0; rf_path < 2; rf_path++) {
1764                 for (i = 0; i < 3; i++) {
1765                         /* Read Power diff limit. */
1766                         rtlefuse->eeprom_pwrgroup[rf_path][i] =
1767                                 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1768                 }
1769         }
1770
1771         for (rf_path = 0; rf_path < 2; rf_path++) {
1772                 /* Fill Pwr group */
1773                 for (i = 0; i < 14; i++) {
1774                         /* Chanel 1-3 */
1775                         if (i < 3)
1776                                 index = 0;
1777                         /* Channel 4-8 */
1778                         else if (i < 8)
1779                                 index = 1;
1780                         /* Channel 9-13 */
1781                         else
1782                                 index = 2;
1783
1784                         rtlefuse->pwrgroup_ht20[rf_path][i] =
1785                                 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1786                                 0xf);
1787                         rtlefuse->pwrgroup_ht40[rf_path][i] =
1788                                 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1789                                 0xf0) >> 4);
1790
1791                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1792                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1793                                 rf_path, i,
1794                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1795                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1796                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1797                                 rf_path, i,
1798                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1799                         }
1800         }
1801
1802         for (i = 0; i < 14; i++) {
1803                 /* Read tx power difference between HT OFDM 20/40 MHZ */
1804                 /* channel 1-3 */
1805                 if (i < 3)
1806                         index = 0;
1807                 /* Channel 4-8 */
1808                 else if (i < 8)
1809                         index = 1;
1810                 /* Channel 9-14 */
1811                 else
1812                         index = 2;
1813
1814                 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF +
1815                            index]) & 0xff;
1816                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1817                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1818                                                  ((tempval >> 4) & 0xF);
1819
1820                 /* Read OFDM<->HT tx power diff */
1821                 /* Channel 1-3 */
1822                 if (i < 3)
1823                         index = 0;
1824                 /* Channel 4-8 */
1825                 else if (i < 8)
1826                         index = 0x11;
1827                 /* Channel 9-14 */
1828                 else
1829                         index = 1;
1830
1831                 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index])
1832                                   & 0xff;
1833                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1834                                  (tempval & 0xF);
1835                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1836                                  ((tempval >> 4) & 0xF);
1837
1838                 tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]);
1839                 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1840         }
1841
1842         rtlefuse->eeprom_regulatory = 0;
1843         if (rtlefuse->eeprom_version >= 2) {
1844                 /* BIT(0)~2 */
1845                 if (rtlefuse->eeprom_version >= 4)
1846                         rtlefuse->eeprom_regulatory =
1847                                  (hwinfo[EEPROM_REGULATORY] & 0x7);
1848                 else /* BIT(0) */
1849                         rtlefuse->eeprom_regulatory =
1850                                  (hwinfo[EEPROM_REGULATORY] & 0x1);
1851         }
1852         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1853                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1854
1855         for (i = 0; i < 14; i++)
1856                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1857                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1858                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1859         for (i = 0; i < 14; i++)
1860                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1861                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1862                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1863         for (i = 0; i < 14; i++)
1864                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1865                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1866                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1867         for (i = 0; i < 14; i++)
1868                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1869                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1870                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1871
1872         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1873                 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1874
1875         /* Read RF-indication and Tx Power gain
1876          * index diff of legacy to HT OFDM rate. */
1877         tempval = (*(u8 *)&hwinfo[EEPROM_RFIND_POWERDIFF]) & 0xff;
1878         rtlefuse->eeprom_txpowerdiff = tempval;
1879         rtlefuse->legacy_httxpowerdiff =
1880                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1881
1882         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1883                 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1884
1885         /* Get TSSI value for each path. */
1886         usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1887         rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1888         usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
1889         rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1890
1891         RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1892                 rtlefuse->eeprom_tssi[RF90_PATH_A],
1893                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1894
1895         /* Read antenna tx power offset of B/C/D to A  from EEPROM */
1896         /* and read ThermalMeter from EEPROM */
1897         tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
1898         rtlefuse->eeprom_thermalmeter = tempval;
1899         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1900                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1901
1902         /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1903         rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1904         rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1905
1906         /* Read CrystalCap from EEPROM */
1907         tempval = (*(u8 *)&hwinfo[EEPROM_CRYSTALCAP]) >> 4;
1908         rtlefuse->eeprom_crystalcap = tempval;
1909         /* CrystalCap, BIT(12)~15 */
1910         rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1911
1912         /* Read IC Version && Channel Plan */
1913         /* Version ID, Channel plan */
1914         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1915         rtlefuse->txpwr_fromeprom = true;
1916         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1917                 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1918
1919         /* Read Customer ID or Board Type!!! */
1920         tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
1921         /* Change RF type definition */
1922         if (tempval == 0)
1923                 rtlphy->rf_type = RF_2T2R;
1924         else if (tempval == 1)
1925                 rtlphy->rf_type = RF_1T2R;
1926         else if (tempval == 2)
1927                 rtlphy->rf_type = RF_1T2R;
1928         else if (tempval == 3)
1929                 rtlphy->rf_type = RF_1T1R;
1930
1931         /* 1T2R but 1SS (1x1 receive combining) */
1932         rtlefuse->b1x1_recvcombine = false;
1933         if (rtlphy->rf_type == RF_1T2R) {
1934                 tempval = rtl_read_byte(rtlpriv, 0x07);
1935                 if (!(tempval & BIT(0))) {
1936                         rtlefuse->b1x1_recvcombine = true;
1937                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1938                                  "RF_TYPE=1T2R but only 1SS\n");
1939                 }
1940         }
1941         rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1942         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMID];
1943
1944         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x",
1945                  rtlefuse->eeprom_oemid);
1946
1947         /* set channel paln to world wide 13 */
1948         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1949 }
1950
1951 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1952 {
1953         struct rtl_priv *rtlpriv = rtl_priv(hw);
1954         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1955         u8 tmp_u1b = 0;
1956
1957         tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1958
1959         if (tmp_u1b & BIT(4)) {
1960                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1961                 rtlefuse->epromtype = EEPROM_93C46;
1962         } else {
1963                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1964                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1965         }
1966
1967         if (tmp_u1b & BIT(5)) {
1968                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1969                 rtlefuse->autoload_failflag = false;
1970                 _rtl92se_read_adapter_info(hw);
1971         } else {
1972                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1973                 rtlefuse->autoload_failflag = true;
1974         }
1975 }
1976
1977 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
1978                                           struct ieee80211_sta *sta)
1979 {
1980         struct rtl_priv *rtlpriv = rtl_priv(hw);
1981         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1982         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1983         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1984         u32 ratr_value;
1985         u8 ratr_index = 0;
1986         u8 nmode = mac->ht_enable;
1987         u8 mimo_ps = IEEE80211_SMPS_OFF;
1988         u16 shortgi_rate = 0;
1989         u32 tmp_ratr_value = 0;
1990         u8 curtxbw_40mhz = mac->bw_40;
1991         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1992                                 1 : 0;
1993         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1994                                 1 : 0;
1995         enum wireless_mode wirelessmode = mac->mode;
1996
1997         if (rtlhal->current_bandtype == BAND_ON_5G)
1998                 ratr_value = sta->supp_rates[1] << 4;
1999         else
2000                 ratr_value = sta->supp_rates[0];
2001         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2002                         sta->ht_cap.mcs.rx_mask[0] << 12);
2003         switch (wirelessmode) {
2004         case WIRELESS_MODE_B:
2005                 ratr_value &= 0x0000000D;
2006                 break;
2007         case WIRELESS_MODE_G:
2008                 ratr_value &= 0x00000FF5;
2009                 break;
2010         case WIRELESS_MODE_N_24G:
2011         case WIRELESS_MODE_N_5G:
2012                 nmode = 1;
2013                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2014                         ratr_value &= 0x0007F005;
2015                 } else {
2016                         u32 ratr_mask;
2017
2018                         if (get_rf_type(rtlphy) == RF_1T2R ||
2019                             get_rf_type(rtlphy) == RF_1T1R) {
2020                                 if (curtxbw_40mhz)
2021                                         ratr_mask = 0x000ff015;
2022                                 else
2023                                         ratr_mask = 0x000ff005;
2024                         } else {
2025                                 if (curtxbw_40mhz)
2026                                         ratr_mask = 0x0f0ff015;
2027                                 else
2028                                         ratr_mask = 0x0f0ff005;
2029                         }
2030
2031                         ratr_value &= ratr_mask;
2032                 }
2033                 break;
2034         default:
2035                 if (rtlphy->rf_type == RF_1T2R)
2036                         ratr_value &= 0x000ff0ff;
2037                 else
2038                         ratr_value &= 0x0f0ff0ff;
2039
2040                 break;
2041         }
2042
2043         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2044                 ratr_value &= 0x0FFFFFFF;
2045         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2046                 ratr_value &= 0x0FFFFFF0;
2047
2048         if (nmode && ((curtxbw_40mhz &&
2049                          curshortgi_40mhz) || (!curtxbw_40mhz &&
2050                                                  curshortgi_20mhz))) {
2051
2052                 ratr_value |= 0x10000000;
2053                 tmp_ratr_value = (ratr_value >> 12);
2054
2055                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2056                         if ((1 << shortgi_rate) & tmp_ratr_value)
2057                                 break;
2058                 }
2059
2060                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2061                     (shortgi_rate << 4) | (shortgi_rate);
2062
2063                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2064         }
2065
2066         rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2067         if (ratr_value & 0xfffff000)
2068                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2069         else
2070                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2071
2072         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2073                  rtl_read_dword(rtlpriv, ARFR0));
2074 }
2075
2076 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2077                                          struct ieee80211_sta *sta,
2078                                          u8 rssi_level)
2079 {
2080         struct rtl_priv *rtlpriv = rtl_priv(hw);
2081         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2082         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2083         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2084         struct rtl_sta_info *sta_entry = NULL;
2085         u32 ratr_bitmap;
2086         u8 ratr_index = 0;
2087         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2088                                 ? 1 : 0;
2089         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2090                                 1 : 0;
2091         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2092                                 1 : 0;
2093         enum wireless_mode wirelessmode = 0;
2094         bool shortgi = false;
2095         u32 ratr_value = 0;
2096         u8 shortgi_rate = 0;
2097         u32 mask = 0;
2098         u32 band = 0;
2099         bool bmulticast = false;
2100         u8 macid = 0;
2101         u8 mimo_ps = IEEE80211_SMPS_OFF;
2102
2103         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2104         wirelessmode = sta_entry->wireless_mode;
2105         if (mac->opmode == NL80211_IFTYPE_STATION)
2106                 curtxbw_40mhz = mac->bw_40;
2107         else if (mac->opmode == NL80211_IFTYPE_AP ||
2108                 mac->opmode == NL80211_IFTYPE_ADHOC)
2109                 macid = sta->aid + 1;
2110
2111         if (rtlhal->current_bandtype == BAND_ON_5G)
2112                 ratr_bitmap = sta->supp_rates[1] << 4;
2113         else
2114                 ratr_bitmap = sta->supp_rates[0];
2115         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2116                         sta->ht_cap.mcs.rx_mask[0] << 12);
2117         switch (wirelessmode) {
2118         case WIRELESS_MODE_B:
2119                 band |= WIRELESS_11B;
2120                 ratr_index = RATR_INX_WIRELESS_B;
2121                 if (ratr_bitmap & 0x0000000c)
2122                         ratr_bitmap &= 0x0000000d;
2123                 else
2124                         ratr_bitmap &= 0x0000000f;
2125                 break;
2126         case WIRELESS_MODE_G:
2127                 band |= (WIRELESS_11G | WIRELESS_11B);
2128                 ratr_index = RATR_INX_WIRELESS_GB;
2129
2130                 if (rssi_level == 1)
2131                         ratr_bitmap &= 0x00000f00;
2132                 else if (rssi_level == 2)
2133                         ratr_bitmap &= 0x00000ff0;
2134                 else
2135                         ratr_bitmap &= 0x00000ff5;
2136                 break;
2137         case WIRELESS_MODE_A:
2138                 band |= WIRELESS_11A;
2139                 ratr_index = RATR_INX_WIRELESS_A;
2140                 ratr_bitmap &= 0x00000ff0;
2141                 break;
2142         case WIRELESS_MODE_N_24G:
2143         case WIRELESS_MODE_N_5G:
2144                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2145                 ratr_index = RATR_INX_WIRELESS_NGB;
2146
2147                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2148                         if (rssi_level == 1)
2149                                 ratr_bitmap &= 0x00070000;
2150                         else if (rssi_level == 2)
2151                                 ratr_bitmap &= 0x0007f000;
2152                         else
2153                                 ratr_bitmap &= 0x0007f005;
2154                 } else {
2155                         if (rtlphy->rf_type == RF_1T2R ||
2156                                 rtlphy->rf_type == RF_1T1R) {
2157                                 if (rssi_level == 1) {
2158                                                 ratr_bitmap &= 0x000f0000;
2159                                 } else if (rssi_level == 3) {
2160                                         ratr_bitmap &= 0x000fc000;
2161                                 } else if (rssi_level == 5) {
2162                                                 ratr_bitmap &= 0x000ff000;
2163                                 } else {
2164                                         if (curtxbw_40mhz)
2165                                                 ratr_bitmap &= 0x000ff015;
2166                                         else
2167                                                 ratr_bitmap &= 0x000ff005;
2168                                 }
2169                         } else {
2170                                 if (rssi_level == 1) {
2171                                         ratr_bitmap &= 0x0f8f0000;
2172                                 } else if (rssi_level == 3) {
2173                                         ratr_bitmap &= 0x0f8fc000;
2174                                 } else if (rssi_level == 5) {
2175                                         ratr_bitmap &= 0x0f8ff000;
2176                                 } else {
2177                                         if (curtxbw_40mhz)
2178                                                 ratr_bitmap &= 0x0f8ff015;
2179                                         else
2180                                                 ratr_bitmap &= 0x0f8ff005;
2181                                 }
2182                         }
2183                 }
2184
2185                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2186                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2187                         if (macid == 0)
2188                                 shortgi = true;
2189                         else if (macid == 1)
2190                                 shortgi = false;
2191                 }
2192                 break;
2193         default:
2194                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2195                 ratr_index = RATR_INX_WIRELESS_NGB;
2196
2197                 if (rtlphy->rf_type == RF_1T2R)
2198                         ratr_bitmap &= 0x000ff0ff;
2199                 else
2200                         ratr_bitmap &= 0x0f8ff0ff;
2201                 break;
2202         }
2203
2204         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2205                 ratr_bitmap &= 0x0FFFFFFF;
2206         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2207                 ratr_bitmap &= 0x0FFFFFF0;
2208
2209         if (shortgi) {
2210                 ratr_bitmap |= 0x10000000;
2211                 /* Get MAX MCS available. */
2212                 ratr_value = (ratr_bitmap >> 12);
2213                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2214                         if ((1 << shortgi_rate) & ratr_value)
2215                                 break;
2216                 }
2217
2218                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2219                         (shortgi_rate << 4) | (shortgi_rate);
2220                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2221         }
2222
2223         mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2224
2225         RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2226                  mask, ratr_bitmap);
2227         rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2228         rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2229
2230         if (macid != 0)
2231                 sta_entry->ratr_index = ratr_index;
2232 }
2233
2234 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2235                 struct ieee80211_sta *sta, u8 rssi_level)
2236 {
2237         struct rtl_priv *rtlpriv = rtl_priv(hw);
2238
2239         if (rtlpriv->dm.useramask)
2240                 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2241         else
2242                 rtl92se_update_hal_rate_table(hw, sta);
2243 }
2244
2245 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2246 {
2247         struct rtl_priv *rtlpriv = rtl_priv(hw);
2248         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2249         u16 sifs_timer;
2250
2251         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2252                                       (u8 *)&mac->slot_time);
2253         sifs_timer = 0x0e0e;
2254         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2255
2256 }
2257
2258 /* this ifunction is for RFKILL, it's different with windows,
2259  * because UI will disable wireless when GPIO Radio Off.
2260  * And here we not check or Disable/Enable ASPM like windows*/
2261 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2262 {
2263         struct rtl_priv *rtlpriv = rtl_priv(hw);
2264         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2265         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2266         enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2267         unsigned long flag = 0;
2268         bool actuallyset = false;
2269         bool turnonbypowerdomain = false;
2270
2271         /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2272         if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2273                 return false;
2274
2275         if (ppsc->swrf_processing)
2276                 return false;
2277
2278         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2279         if (ppsc->rfchange_inprogress) {
2280                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2281                 return false;
2282         } else {
2283                 ppsc->rfchange_inprogress = true;
2284                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2285         }
2286
2287         /* cur_rfstate = ppsc->rfpwr_state;*/
2288
2289         /* because after _rtl92s_phy_set_rfhalt, all power
2290          * closed, so we must open some power for GPIO check,
2291          * or we will always check GPIO RFOFF here,
2292          * And we should close power after GPIO check */
2293         if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2294                 _rtl92se_power_domain_init(hw);
2295                 turnonbypowerdomain = true;
2296         }
2297
2298         rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2299
2300         if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2301                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2302                          "RFKILL-HW Radio ON, RF ON\n");
2303
2304                 rfpwr_toset = ERFON;
2305                 ppsc->hwradiooff = false;
2306                 actuallyset = true;
2307         } else if ((ppsc->hwradiooff == false) && (rfpwr_toset == ERFOFF)) {
2308                 RT_TRACE(rtlpriv, COMP_RF,
2309                          DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2310
2311                 rfpwr_toset = ERFOFF;
2312                 ppsc->hwradiooff = true;
2313                 actuallyset = true;
2314         }
2315
2316         if (actuallyset) {
2317                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2318                 ppsc->rfchange_inprogress = false;
2319                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2320
2321         /* this not include ifconfig wlan0 down case */
2322         /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2323         } else {
2324                 /* because power_domain_init may be happen when
2325                  * _rtl92s_phy_set_rfhalt, this will open some powers
2326                  * and cause current increasing about 40 mA for ips,
2327                  * rfoff and ifconfig down, so we set
2328                  * _rtl92s_phy_set_rfhalt again here */
2329                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2330                         turnonbypowerdomain) {
2331                         _rtl92s_phy_set_rfhalt(hw);
2332                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2333                 }
2334
2335                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2336                 ppsc->rfchange_inprogress = false;
2337                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2338         }
2339
2340         *valid = 1;
2341         return !ppsc->hwradiooff;
2342
2343 }
2344
2345 /* Is_wepkey just used for WEP used as group & pairwise key
2346  * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2347 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2348         bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2349 {
2350         struct rtl_priv *rtlpriv = rtl_priv(hw);
2351         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2352         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2353         u8 *macaddr = p_macaddr;
2354
2355         u32 entry_id = 0;
2356         bool is_pairwise = false;
2357
2358         static u8 cam_const_addr[4][6] = {
2359                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2360                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2361                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2362                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2363         };
2364         static u8 cam_const_broad[] = {
2365                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2366         };
2367
2368         if (clear_all) {
2369                 u8 idx = 0;
2370                 u8 cam_offset = 0;
2371                 u8 clear_number = 5;
2372
2373                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2374
2375                 for (idx = 0; idx < clear_number; idx++) {
2376                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2377                         rtl_cam_empty_entry(hw, cam_offset + idx);
2378
2379                         if (idx < 5) {
2380                                 memset(rtlpriv->sec.key_buf[idx], 0,
2381                                        MAX_KEY_LEN);
2382                                 rtlpriv->sec.key_len[idx] = 0;
2383                         }
2384                 }
2385
2386         } else {
2387                 switch (enc_algo) {
2388                 case WEP40_ENCRYPTION:
2389                         enc_algo = CAM_WEP40;
2390                         break;
2391                 case WEP104_ENCRYPTION:
2392                         enc_algo = CAM_WEP104;
2393                         break;
2394                 case TKIP_ENCRYPTION:
2395                         enc_algo = CAM_TKIP;
2396                         break;
2397                 case AESCCMP_ENCRYPTION:
2398                         enc_algo = CAM_AES;
2399                         break;
2400                 default:
2401                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2402                                  "switch case not processed\n");
2403                         enc_algo = CAM_TKIP;
2404                         break;
2405                 }
2406
2407                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2408                         macaddr = cam_const_addr[key_index];
2409                         entry_id = key_index;
2410                 } else {
2411                         if (is_group) {
2412                                 macaddr = cam_const_broad;
2413                                 entry_id = key_index;
2414                         } else {
2415                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2416                                         entry_id = rtl_cam_get_free_entry(hw,
2417                                                                  p_macaddr);
2418                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2419                                                 RT_TRACE(rtlpriv,
2420                                                          COMP_SEC, DBG_EMERG,
2421                                                          "Can not find free hw security cam entry\n");
2422                                                 return;
2423                                         }
2424                                 } else {
2425                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2426                                 }
2427
2428                                 key_index = PAIRWISE_KEYIDX;
2429                                 is_pairwise = true;
2430                         }
2431                 }
2432
2433                 if (rtlpriv->sec.key_len[key_index] == 0) {
2434                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2435                                  "delete one entry, entry_id is %d\n",
2436                                  entry_id);
2437                         if (mac->opmode == NL80211_IFTYPE_AP)
2438                                 rtl_cam_del_entry(hw, p_macaddr);
2439                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2440                 } else {
2441                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2442                                  "The insert KEY length is %d\n",
2443                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2444                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2445                                  "The insert KEY is %x %x\n",
2446                                  rtlpriv->sec.key_buf[0][0],
2447                                  rtlpriv->sec.key_buf[0][1]);
2448
2449                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2450                                  "add one entry\n");
2451                         if (is_pairwise) {
2452                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2453                                               "Pairwise Key content",
2454                                               rtlpriv->sec.pairwise_key,
2455                                               rtlpriv->sec.
2456                                               key_len[PAIRWISE_KEYIDX]);
2457
2458                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2459                                          "set Pairwise key\n");
2460
2461                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2462                                         entry_id, enc_algo,
2463                                         CAM_CONFIG_NO_USEDK,
2464                                         rtlpriv->sec.key_buf[key_index]);
2465                         } else {
2466                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2467                                          "set group key\n");
2468
2469                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2470                                         rtl_cam_add_one_entry(hw,
2471                                                 rtlefuse->dev_addr,
2472                                                 PAIRWISE_KEYIDX,
2473                                                 CAM_PAIRWISE_KEY_POSITION,
2474                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2475                                                 rtlpriv->sec.key_buf[entry_id]);
2476                                 }
2477
2478                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2479                                               entry_id, enc_algo,
2480                                               CAM_CONFIG_NO_USEDK,
2481                                               rtlpriv->sec.key_buf[entry_id]);
2482                         }
2483
2484                 }
2485         }
2486 }
2487
2488 void rtl92se_suspend(struct ieee80211_hw *hw)
2489 {
2490         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2491
2492         rtlpci->up_first_time = true;
2493 }
2494
2495 void rtl92se_resume(struct ieee80211_hw *hw)
2496 {
2497         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2498         u32 val;
2499
2500         pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2501         if ((val & 0x0000ff00) != 0)
2502                 pci_write_config_dword(rtlpci->pdev, 0x40,
2503                         val & 0xffff00ff);
2504 }