drivers/net/wireless/ti/wl18xx/main.c

   1 /*
   2  * This file is part of wl18xx
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ip.h>
  25
  26 #include "../wlcore/wlcore.h"
  27 #include "../wlcore/debug.h"
  28 #include "../wlcore/io.h"
  29 #include "../wlcore/acx.h"
  30 #include "../wlcore/tx.h"
  31 #include "../wlcore/rx.h"
  32 #include "../wlcore/io.h"
  33 #include "../wlcore/boot.h"
  34
  35 #include "reg.h"
  36 #include "conf.h"
  37 #include "acx.h"
  38 #include "tx.h"
  39 #include "wl18xx.h"
  40 #include "io.h"
  41
  42
  43 #define WL18XX_RX_CHECKSUM_MASK      0x40
  44
  45 static char *ht_mode_param;
  46 static char *board_type_param = "hdk";
  47 static bool dc2dc_param = false;
  48 static int n_antennas_2_param = 1;
  49 static int n_antennas_5_param = 1;
  50 static bool checksum_param = true;
  51 static bool enable_11a_param = true;
  52
  53 static const u8 wl18xx_rate_to_idx_2ghz[] = {
  54         /* MCS rates are used only with 11n */
  55         15,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  56         14,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  57         13,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  58         12,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  59         11,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  60         10,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  61         9,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  62         8,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
  63         7,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
  64         6,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
  65         5,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
  66         4,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
  67         3,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
  68         2,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
  69         1,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
  70         0,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
  71
  72         11,                            /* WL18XX_CONF_HW_RXTX_RATE_54   */
  73         10,                            /* WL18XX_CONF_HW_RXTX_RATE_48   */
  74         9,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
  75         8,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
  76
  77         /* TI-specific rate */
  78         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
  79
  80         7,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
  81         6,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
  82         3,                             /* WL18XX_CONF_HW_RXTX_RATE_11   */
  83         5,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
  84         4,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
  85         2,                             /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
  86         1,                             /* WL18XX_CONF_HW_RXTX_RATE_2    */
  87         0                              /* WL18XX_CONF_HW_RXTX_RATE_1    */
  88 };
  89
  90 static const u8 wl18xx_rate_to_idx_5ghz[] = {
  91         /* MCS rates are used only with 11n */
  92         15,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  93         14,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  94         13,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  95         12,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  96         11,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  97         10,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  98         9,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  99         8,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
 100         7,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
 101         6,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
 102         5,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
 103         4,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
 104         3,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
 105         2,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
 106         1,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
 107         0,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
 108
 109         7,                             /* WL18XX_CONF_HW_RXTX_RATE_54   */
 110         6,                             /* WL18XX_CONF_HW_RXTX_RATE_48   */
 111         5,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
 112         4,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
 113
 114         /* TI-specific rate */
 115         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
 116
 117         3,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
 118         2,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
 119         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11   */
 120         1,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
 121         0,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
 122         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
 123         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2    */
 124         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1    */
 125 };
 126
 127 static const u8 *wl18xx_band_rate_to_idx[] = {
 128         [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
 129         [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
 130 };
 131
 132 enum wl18xx_hw_rates {
 133         WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
 134         WL18XX_CONF_HW_RXTX_RATE_MCS14,
 135         WL18XX_CONF_HW_RXTX_RATE_MCS13,
 136         WL18XX_CONF_HW_RXTX_RATE_MCS12,
 137         WL18XX_CONF_HW_RXTX_RATE_MCS11,
 138         WL18XX_CONF_HW_RXTX_RATE_MCS10,
 139         WL18XX_CONF_HW_RXTX_RATE_MCS9,
 140         WL18XX_CONF_HW_RXTX_RATE_MCS8,
 141         WL18XX_CONF_HW_RXTX_RATE_MCS7,
 142         WL18XX_CONF_HW_RXTX_RATE_MCS6,
 143         WL18XX_CONF_HW_RXTX_RATE_MCS5,
 144         WL18XX_CONF_HW_RXTX_RATE_MCS4,
 145         WL18XX_CONF_HW_RXTX_RATE_MCS3,
 146         WL18XX_CONF_HW_RXTX_RATE_MCS2,
 147         WL18XX_CONF_HW_RXTX_RATE_MCS1,
 148         WL18XX_CONF_HW_RXTX_RATE_MCS0,
 149         WL18XX_CONF_HW_RXTX_RATE_54,
 150         WL18XX_CONF_HW_RXTX_RATE_48,
 151         WL18XX_CONF_HW_RXTX_RATE_36,
 152         WL18XX_CONF_HW_RXTX_RATE_24,
 153         WL18XX_CONF_HW_RXTX_RATE_22,
 154         WL18XX_CONF_HW_RXTX_RATE_18,
 155         WL18XX_CONF_HW_RXTX_RATE_12,
 156         WL18XX_CONF_HW_RXTX_RATE_11,
 157         WL18XX_CONF_HW_RXTX_RATE_9,
 158         WL18XX_CONF_HW_RXTX_RATE_6,
 159         WL18XX_CONF_HW_RXTX_RATE_5_5,
 160         WL18XX_CONF_HW_RXTX_RATE_2,
 161         WL18XX_CONF_HW_RXTX_RATE_1,
 162         WL18XX_CONF_HW_RXTX_RATE_MAX,
 163 };
 164
 165 static struct wlcore_conf wl18xx_conf = {
 166         .sg = {
 167                 .params = {
 168                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
 169                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
 170                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
 171                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
 172                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
 173                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
 174                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
 175                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
 176                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
 177                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
 178                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
 179                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
 180                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
 181                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
 182                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
 183                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
 184                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
 185                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
 186                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
 187                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
 188                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
 189                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
 190                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
 191                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
 192                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
 193                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
 194                         /* active scan params */
 195                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
 196                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
 197                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
 198                         /* passive scan params */
 199                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
 200                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
 201                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
 202                         /* passive scan in dual antenna params */
 203                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
 204                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
 205                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
 206                         /* general params */
 207                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
 208                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
 209                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
 210                         [CONF_SG_DHCP_TIME] = 5000,
 211                         [CONF_SG_RXT] = 1200,
 212                         [CONF_SG_TXT] = 1000,
 213                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
 214                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
 215                         [CONF_SG_HV3_MAX_SERVED] = 6,
 216                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
 217                         [CONF_SG_UPSD_TIMEOUT] = 10,
 218                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 219                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 220                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 221                         /* AP params */
 222                         [CONF_AP_BEACON_MISS_TX] = 3,
 223                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 224                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 225                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 226                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 227                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 228                         /* CTS Diluting params */
 229                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 230                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 231                 },
 232                 .state = CONF_SG_PROTECTIVE,
 233         },
 234         .rx = {
 235                 .rx_msdu_life_time           = 512000,
 236                 .packet_detection_threshold  = 0,
 237                 .ps_poll_timeout             = 15,
 238                 .upsd_timeout                = 15,
 239                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 240                 .rx_cca_threshold            = 0,
 241                 .irq_blk_threshold           = 0xFFFF,
 242                 .irq_pkt_threshold           = 0,
 243                 .irq_timeout                 = 600,
 244                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 245         },
 246         .tx = {
 247                 .tx_energy_detection         = 0,
 248                 .sta_rc_conf                 = {
 249                         .enabled_rates       = 0,
 250                         .short_retry_limit   = 10,
 251                         .long_retry_limit    = 10,
 252                         .aflags              = 0,
 253                 },
 254                 .ac_conf_count               = 4,
 255                 .ac_conf                     = {
 256                         [CONF_TX_AC_BE] = {
 257                                 .ac          = CONF_TX_AC_BE,
 258                                 .cw_min      = 15,
 259                                 .cw_max      = 63,
 260                                 .aifsn       = 3,
 261                                 .tx_op_limit = 0,
 262                         },
 263                         [CONF_TX_AC_BK] = {
 264                                 .ac          = CONF_TX_AC_BK,
 265                                 .cw_min      = 15,
 266                                 .cw_max      = 63,
 267                                 .aifsn       = 7,
 268                                 .tx_op_limit = 0,
 269                         },
 270                         [CONF_TX_AC_VI] = {
 271                                 .ac          = CONF_TX_AC_VI,
 272                                 .cw_min      = 15,
 273                                 .cw_max      = 63,
 274                                 .aifsn       = CONF_TX_AIFS_PIFS,
 275                                 .tx_op_limit = 3008,
 276                         },
 277                         [CONF_TX_AC_VO] = {
 278                                 .ac          = CONF_TX_AC_VO,
 279                                 .cw_min      = 15,
 280                                 .cw_max      = 63,
 281                                 .aifsn       = CONF_TX_AIFS_PIFS,
 282                                 .tx_op_limit = 1504,
 283                         },
 284                 },
 285                 .max_tx_retries = 100,
 286                 .ap_aging_period = 300,
 287                 .tid_conf_count = 4,
 288                 .tid_conf = {
 289                         [CONF_TX_AC_BE] = {
 290                                 .queue_id    = CONF_TX_AC_BE,
 291                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 292                                 .tsid        = CONF_TX_AC_BE,
 293                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 294                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 295                                 .apsd_conf   = {0, 0},
 296                         },
 297                         [CONF_TX_AC_BK] = {
 298                                 .queue_id    = CONF_TX_AC_BK,
 299                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 300                                 .tsid        = CONF_TX_AC_BK,
 301                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 302                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 303                                 .apsd_conf   = {0, 0},
 304                         },
 305                         [CONF_TX_AC_VI] = {
 306                                 .queue_id    = CONF_TX_AC_VI,
 307                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 308                                 .tsid        = CONF_TX_AC_VI,
 309                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 310                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 311                                 .apsd_conf   = {0, 0},
 312                         },
 313                         [CONF_TX_AC_VO] = {
 314                                 .queue_id    = CONF_TX_AC_VO,
 315                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 316                                 .tsid        = CONF_TX_AC_VO,
 317                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 318                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 319                                 .apsd_conf   = {0, 0},
 320                         },
 321                 },
 322                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 323                 .tx_compl_timeout            = 350,
 324                 .tx_compl_threshold          = 10,
 325                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 326                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 327                 .tmpl_short_retry_limit      = 10,
 328                 .tmpl_long_retry_limit       = 10,
 329                 .tx_watchdog_timeout         = 5000,
 330         },
 331         .conn = {
 332                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 333                 .listen_interval             = 1,
 334                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 335                 .suspend_listen_interval     = 3,
 336                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 337                 .bcn_filt_ie_count           = 2,
 338                 .bcn_filt_ie = {
 339                         [0] = {
 340                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 341                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 342                         },
 343                         [1] = {
 344                                 .ie          = WLAN_EID_HT_OPERATION,
 345                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 346                         },
 347                 },
 348                 .synch_fail_thold            = 10,
 349                 .bss_lose_timeout            = 100,
 350                 .beacon_rx_timeout           = 10000,
 351                 .broadcast_timeout           = 20000,
 352                 .rx_broadcast_in_ps          = 1,
 353                 .ps_poll_threshold           = 10,
 354                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 355                 .bet_max_consecutive         = 50,
 356                 .psm_entry_retries           = 8,
 357                 .psm_exit_retries            = 16,
 358                 .psm_entry_nullfunc_retries  = 3,
 359                 .dynamic_ps_timeout          = 40,
 360                 .forced_ps                   = false,
 361                 .keep_alive_interval         = 55000,
 362                 .max_listen_interval         = 20,
 363         },
 364         .itrim = {
 365                 .enable = false,
 366                 .timeout = 50000,
 367         },
 368         .pm_config = {
 369                 .host_clk_settling_time = 5000,
 370                 .host_fast_wakeup_support = false
 371         },
 372         .roam_trigger = {
 373                 .trigger_pacing               = 1,
 374                 .avg_weight_rssi_beacon       = 20,
 375                 .avg_weight_rssi_data         = 10,
 376                 .avg_weight_snr_beacon        = 20,
 377                 .avg_weight_snr_data          = 10,
 378         },
 379         .scan = {
 380                 .min_dwell_time_active        = 7500,
 381                 .max_dwell_time_active        = 30000,
 382                 .min_dwell_time_passive       = 100000,
 383                 .max_dwell_time_passive       = 100000,
 384                 .num_probe_reqs               = 2,
 385                 .split_scan_timeout           = 50000,
 386         },
 387         .sched_scan = {
 388                 /*
 389                  * Values are in TU/1000 but since sched scan FW command
 390                  * params are in TUs rounding up may occur.
 391                  */
 392                 .base_dwell_time                = 7500,
 393                 .max_dwell_time_delta           = 22500,
 394                 /* based on 250bits per probe @1Mbps */
 395                 .dwell_time_delta_per_probe     = 2000,
 396                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 397                 .dwell_time_delta_per_probe_5   = 350,
 398                 .dwell_time_passive             = 100000,
 399                 .dwell_time_dfs                 = 150000,
 400                 .num_probe_reqs                 = 2,
 401                 .rssi_threshold                 = -90,
 402                 .snr_threshold                  = 0,
 403         },
 404         .ht = {
 405                 .rx_ba_win_size = 10,
 406                 .tx_ba_win_size = 10,
 407                 .inactivity_timeout = 10000,
 408                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 409         },
 410         .mem = {
 411                 .num_stations                 = 1,
 412                 .ssid_profiles                = 1,
 413                 .rx_block_num                 = 40,
 414                 .tx_min_block_num             = 40,
 415                 .dynamic_memory               = 1,
 416                 .min_req_tx_blocks            = 45,
 417                 .min_req_rx_blocks            = 22,
 418                 .tx_min                       = 27,
 419         },
 420         .fm_coex = {
 421                 .enable                       = true,
 422                 .swallow_period               = 5,
 423                 .n_divider_fref_set_1         = 0xff,       /* default */
 424                 .n_divider_fref_set_2         = 12,
 425                 .m_divider_fref_set_1         = 148,
 426                 .m_divider_fref_set_2         = 0xffff,     /* default */
 427                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 428                 .ldo_stabilization_time       = 0xffff,     /* default */
 429                 .fm_disturbed_band_margin     = 0xff,       /* default */
 430                 .swallow_clk_diff             = 0xff,       /* default */
 431         },
 432         .rx_streaming = {
 433                 .duration                      = 150,
 434                 .queues                        = 0x1,
 435                 .interval                      = 20,
 436                 .always                        = 0,
 437         },
 438         .fwlog = {
 439                 .mode                         = WL12XX_FWLOG_ON_DEMAND,
 440                 .mem_blocks                   = 2,
 441                 .severity                     = 0,
 442                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 443                 .output                       = WL12XX_FWLOG_OUTPUT_HOST,
 444                 .threshold                    = 0,
 445         },
 446         .rate = {
 447                 .rate_retry_score = 32000,
 448                 .per_add = 8192,
 449                 .per_th1 = 2048,
 450                 .per_th2 = 4096,
 451                 .max_per = 8100,
 452                 .inverse_curiosity_factor = 5,
 453                 .tx_fail_low_th = 4,
 454                 .tx_fail_high_th = 10,
 455                 .per_alpha_shift = 4,
 456                 .per_add_shift = 13,
 457                 .per_beta1_shift = 10,
 458                 .per_beta2_shift = 8,
 459                 .rate_check_up = 2,
 460                 .rate_check_down = 12,
 461                 .rate_retry_policy = {
 462                         0x00, 0x00, 0x00, 0x00, 0x00,
 463                         0x00, 0x00, 0x00, 0x00, 0x00,
 464                         0x00, 0x00, 0x00,
 465                 },
 466         },
 467         .hangover = {
 468                 .recover_time               = 0,
 469                 .hangover_period            = 20,
 470                 .dynamic_mode               = 1,
 471                 .early_termination_mode     = 1,
 472                 .max_period                 = 20,
 473                 .min_period                 = 1,
 474                 .increase_delta             = 1,
 475                 .decrease_delta             = 2,
 476                 .quiet_time                 = 4,
 477                 .increase_time              = 1,
 478                 .window_size                = 16,
 479         },
 480 };
 481
 482 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
 483         .phy = {
 484                 .phy_standalone                 = 0x00,
 485                 .primary_clock_setting_time     = 0x05,
 486                 .clock_valid_on_wake_up         = 0x00,
 487                 .secondary_clock_setting_time   = 0x05,
 488                 .rdl                            = 0x01,
 489                 .auto_detect                    = 0x00,
 490                 .dedicated_fem                  = FEM_NONE,
 491                 .low_band_component             = COMPONENT_2_WAY_SWITCH,
 492                 .low_band_component_type        = 0x05,
 493                 .high_band_component            = COMPONENT_2_WAY_SWITCH,
 494                 .high_band_component_type       = 0x09,
 495                 .tcxo_ldo_voltage               = 0x00,
 496                 .xtal_itrim_val                 = 0x04,
 497                 .srf_state                      = 0x00,
 498                 .io_configuration               = 0x01,
 499                 .sdio_configuration             = 0x00,
 500                 .settings                       = 0x00,
 501                 .enable_clpc                    = 0x00,
 502                 .enable_tx_low_pwr_on_siso_rdl  = 0x00,
 503                 .rx_profile                     = 0x00,
 504         },
 505 };
 506
 507 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
 508         [PART_TOP_PRCM_ELP_SOC] = {
 509                 .mem  = { .start = 0x00A02000, .size  = 0x00010000 },
 510                 .reg  = { .start = 0x00807000, .size  = 0x00005000 },
 511                 .mem2 = { .start = 0x00800000, .size  = 0x0000B000 },
 512                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 513         },
 514         [PART_DOWN] = {
 515                 .mem  = { .start = 0x00000000, .size  = 0x00014000 },
 516                 .reg  = { .start = 0x00810000, .size  = 0x0000BFFF },
 517                 .mem2 = { .start = 0x00000000, .size  = 0x00000000 },
 518                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 519         },
 520         [PART_BOOT] = {
 521                 .mem  = { .start = 0x00700000, .size = 0x0000030c },
 522                 .reg  = { .start = 0x00802000, .size = 0x00014578 },
 523                 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
 524                 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
 525         },
 526         [PART_WORK] = {
 527                 .mem  = { .start = 0x00800000, .size  = 0x000050FC },
 528                 .reg  = { .start = 0x00B00404, .size  = 0x00001000 },
 529                 .mem2 = { .start = 0x00C00000, .size  = 0x00000400 },
 530                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 531         },
 532         [PART_PHY_INIT] = {
 533                 /* TODO: use the phy_conf struct size here */
 534                 .mem  = { .start = 0x80926000, .size = 252 },
 535                 .reg  = { .start = 0x00000000, .size = 0x00000000 },
 536                 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
 537                 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
 538         },
 539 };
 540
 541 static const int wl18xx_rtable[REG_TABLE_LEN] = {
 542         [REG_ECPU_CONTROL]              = WL18XX_REG_ECPU_CONTROL,
 543         [REG_INTERRUPT_NO_CLEAR]        = WL18XX_REG_INTERRUPT_NO_CLEAR,
 544         [REG_INTERRUPT_ACK]             = WL18XX_REG_INTERRUPT_ACK,
 545         [REG_COMMAND_MAILBOX_PTR]       = WL18XX_REG_COMMAND_MAILBOX_PTR,
 546         [REG_EVENT_MAILBOX_PTR]         = WL18XX_REG_EVENT_MAILBOX_PTR,
 547         [REG_INTERRUPT_TRIG]            = WL18XX_REG_INTERRUPT_TRIG_H,
 548         [REG_INTERRUPT_MASK]            = WL18XX_REG_INTERRUPT_MASK,
 549         [REG_PC_ON_RECOVERY]            = WL18XX_SCR_PAD4,
 550         [REG_CHIP_ID_B]                 = WL18XX_REG_CHIP_ID_B,
 551         [REG_CMD_MBOX_ADDRESS]          = WL18XX_CMD_MBOX_ADDRESS,
 552
 553         /* data access memory addresses, used with partition translation */
 554         [REG_SLV_MEM_DATA]              = WL18XX_SLV_MEM_DATA,
 555         [REG_SLV_REG_DATA]              = WL18XX_SLV_REG_DATA,
 556
 557         /* raw data access memory addresses */
 558         [REG_RAW_FW_STATUS_ADDR]        = WL18XX_FW_STATUS_ADDR,
 559 };
 560
 561 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
 562         [CLOCK_CONFIG_16_2_M]   = { 7,  104,  801, 4,  true },
 563         [CLOCK_CONFIG_16_368_M] = { 9,  132, 3751, 4,  true },
 564         [CLOCK_CONFIG_16_8_M]   = { 7,  100,    0, 0, false },
 565         [CLOCK_CONFIG_19_2_M]   = { 8,  100,    0, 0, false },
 566         [CLOCK_CONFIG_26_M]     = { 13, 120,    0, 0, false },
 567         [CLOCK_CONFIG_32_736_M] = { 9,  132, 3751, 4,  true },
 568         [CLOCK_CONFIG_33_6_M]   = { 7,  100,    0, 0, false },
 569         [CLOCK_CONFIG_38_468_M] = { 8,  100,    0, 0, false },
 570         [CLOCK_CONFIG_52_M]     = { 13, 120,    0, 0, false },
 571 };
 572
 573 /* TODO: maybe move to a new header file? */
 574 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
 575
 576 static int wl18xx_identify_chip(struct wl1271 *wl)
 577 {
 578         int ret = 0;
 579
 580         switch (wl->chip.id) {
 581         case CHIP_ID_185x_PG10:
 582                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
 583                              wl->chip.id);
 584                 wl->sr_fw_name = WL18XX_FW_NAME;
 585                 /* wl18xx uses the same firmware for PLT */
 586                 wl->plt_fw_name = WL18XX_FW_NAME;
 587                 wl->quirks |= WLCORE_QUIRK_NO_ELP |
 588                               WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
 589                               WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
 590
 591                 /* PG 1.0 has some problems with MCS_13, so disable it */
 592                 wl->ht_cap.mcs.rx_mask[1] &= ~BIT(5);
 593
 594                 /* TODO: need to blocksize alignment for RX/TX separately? */
 595                 break;
 596         default:
 597                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 598                 ret = -ENODEV;
 599                 goto out;
 600         }
 601
 602 out:
 603         return ret;
 604 }
 605
 606 static void wl18xx_set_clk(struct wl1271 *wl)
 607 {
 608         u32 clk_freq;
 609
 610         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 611
 612         /* TODO: PG2: apparently we need to read the clk type */
 613
 614         clk_freq = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT);
 615         wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
 616                      wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
 617                      wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
 618                      wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
 619
 620         wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, wl18xx_clk_table[clk_freq].n);
 621         wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, wl18xx_clk_table[clk_freq].m);
 622
 623         if (wl18xx_clk_table[clk_freq].swallow) {
 624                 /* first the 16 lower bits */
 625                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
 626                                      wl18xx_clk_table[clk_freq].q &
 627                                      PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
 628                 /* then the 16 higher bits, masked out */
 629                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
 630                                      (wl18xx_clk_table[clk_freq].q >> 16) &
 631                                      PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
 632
 633                 /* first the 16 lower bits */
 634                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
 635                                      wl18xx_clk_table[clk_freq].p &
 636                                      PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
 637                 /* then the 16 higher bits, masked out */
 638                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
 639                                      (wl18xx_clk_table[clk_freq].p >> 16) &
 640                                      PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
 641         } else {
 642                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
 643                                      PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
 644         }
 645 }
 646
 647 static void wl18xx_boot_soft_reset(struct wl1271 *wl)
 648 {
 649         /* disable Rx/Tx */
 650         wl1271_write32(wl, WL18XX_ENABLE, 0x0);
 651
 652         /* disable auto calibration on start*/
 653         wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff);
 654 }
 655
 656 static int wl18xx_pre_boot(struct wl1271 *wl)
 657 {
 658         wl18xx_set_clk(wl);
 659
 660         /* Continue the ELP wake up sequence */
 661         wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 662         udelay(500);
 663
 664         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 665
 666         /* Disable interrupts */
 667         wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 668
 669         wl18xx_boot_soft_reset(wl);
 670
 671         return 0;
 672 }
 673
 674 static void wl18xx_pre_upload(struct wl1271 *wl)
 675 {
 676         u32 tmp;
 677
 678         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 679
 680         /* TODO: check if this is all needed */
 681         wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
 682
 683         tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
 684
 685         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 686
 687         tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
 688 }
 689
 690 static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
 691 {
 692         struct wl18xx_priv *priv = wl->priv;
 693         struct wl18xx_conf_phy *phy = &priv->conf.phy;
 694         struct wl18xx_mac_and_phy_params params;
 695
 696         memset(&params, 0, sizeof(params));
 697
 698         params.phy_standalone = phy->phy_standalone;
 699         params.rdl = phy->rdl;
 700         params.enable_clpc = phy->enable_clpc;
 701         params.enable_tx_low_pwr_on_siso_rdl =
 702                 phy->enable_tx_low_pwr_on_siso_rdl;
 703         params.auto_detect = phy->auto_detect;
 704         params.dedicated_fem = phy->dedicated_fem;
 705         params.low_band_component = phy->low_band_component;
 706         params.low_band_component_type =
 707                 phy->low_band_component_type;
 708         params.high_band_component = phy->high_band_component;
 709         params.high_band_component_type =
 710                 phy->high_band_component_type;
 711         params.number_of_assembled_ant2_4 =
 712                 n_antennas_2_param;
 713         params.number_of_assembled_ant5 =
 714                 n_antennas_5_param;
 715         params.external_pa_dc2dc = dc2dc_param;
 716         params.tcxo_ldo_voltage = phy->tcxo_ldo_voltage;
 717         params.xtal_itrim_val = phy->xtal_itrim_val;
 718         params.srf_state = phy->srf_state;
 719         params.io_configuration = phy->io_configuration;
 720         params.sdio_configuration = phy->sdio_configuration;
 721         params.settings = phy->settings;
 722         params.rx_profile = phy->rx_profile;
 723         params.primary_clock_setting_time =
 724                 phy->primary_clock_setting_time;
 725         params.clock_valid_on_wake_up =
 726                 phy->clock_valid_on_wake_up;
 727         params.secondary_clock_setting_time =
 728                 phy->secondary_clock_setting_time;
 729
 730         params.board_type = priv->board_type;
 731
 732         wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
 733         wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&params,
 734                      sizeof(params), false);
 735 }
 736
 737 static void wl18xx_enable_interrupts(struct wl1271 *wl)
 738 {
 739         wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
 740
 741         wlcore_enable_interrupts(wl);
 742         wlcore_write_reg(wl, REG_INTERRUPT_MASK,
 743                          WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 744 }
 745
 746 static int wl18xx_boot(struct wl1271 *wl)
 747 {
 748         int ret;
 749
 750         ret = wl18xx_pre_boot(wl);
 751         if (ret < 0)
 752                 goto out;
 753
 754         wl18xx_pre_upload(wl);
 755
 756         ret = wlcore_boot_upload_firmware(wl);
 757         if (ret < 0)
 758                 goto out;
 759
 760         wl18xx_set_mac_and_phy(wl);
 761
 762         ret = wlcore_boot_run_firmware(wl);
 763         if (ret < 0)
 764                 goto out;
 765
 766         wl18xx_enable_interrupts(wl);
 767
 768 out:
 769         return ret;
 770 }
 771
 772 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
 773                                void *buf, size_t len)
 774 {
 775         struct wl18xx_priv *priv = wl->priv;
 776
 777         memcpy(priv->cmd_buf, buf, len);
 778         memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
 779
 780         wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE,
 781                      false);
 782 }
 783
 784 static void wl18xx_ack_event(struct wl1271 *wl)
 785 {
 786         wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK);
 787 }
 788
 789 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
 790 {
 791         u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
 792         return (len + blk_size - 1) / blk_size + spare_blks;
 793 }
 794
 795 static void
 796 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 797                           u32 blks, u32 spare_blks)
 798 {
 799         desc->wl18xx_mem.total_mem_blocks = blks;
 800         desc->wl18xx_mem.reserved = 0;
 801 }
 802
 803 static void
 804 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 805                             struct sk_buff *skb)
 806 {
 807         desc->length = cpu_to_le16(skb->len);
 808
 809         wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
 810                      "len: %d life: %d mem: %d", desc->hlid,
 811                      le16_to_cpu(desc->length),
 812                      le16_to_cpu(desc->life_time),
 813                      desc->wl18xx_mem.total_mem_blocks);
 814 }
 815
 816 static enum wl_rx_buf_align
 817 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
 818 {
 819         if (rx_desc & RX_BUF_PADDED_PAYLOAD)
 820                 return WLCORE_RX_BUF_PADDED;
 821
 822         return WLCORE_RX_BUF_ALIGNED;
 823 }
 824
 825 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
 826                                     u32 data_len)
 827 {
 828         struct wl1271_rx_descriptor *desc = rx_data;
 829
 830         /* invalid packet */
 831         if (data_len < sizeof(*desc))
 832                 return 0;
 833
 834         return data_len - sizeof(*desc);
 835 }
 836
 837 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
 838 {
 839         wl18xx_tx_immediate_complete(wl);
 840 }
 841
 842 static int wl18xx_hw_init(struct wl1271 *wl)
 843 {
 844         int ret;
 845         struct wl18xx_priv *priv = wl->priv;
 846         u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
 847                 HOST_IF_CFG_ADD_RX_ALIGNMENT;
 848
 849         u32 sdio_align_size = 0;
 850
 851         /* (re)init private structures. Relevant on recovery as well. */
 852         priv->last_fw_rls_idx = 0;
 853
 854         /* Enable Tx SDIO padding */
 855         if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
 856                 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
 857                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 858         }
 859
 860         /* Enable Rx SDIO padding */
 861         if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
 862                 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
 863                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 864         }
 865
 866         ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
 867                                             sdio_align_size,
 868                                             WL18XX_TX_HW_BLOCK_SPARE,
 869                                             WL18XX_HOST_IF_LEN_SIZE_FIELD);
 870         if (ret < 0)
 871                 return ret;
 872
 873         if (checksum_param) {
 874                 ret = wl18xx_acx_set_checksum_state(wl);
 875                 if (ret != 0)
 876                         return ret;
 877         }
 878
 879         return ret;
 880 }
 881
 882 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
 883                                     struct wl1271_tx_hw_descr *desc,
 884                                     struct sk_buff *skb)
 885 {
 886         u32 ip_hdr_offset;
 887         struct iphdr *ip_hdr;
 888
 889         if (!checksum_param) {
 890                 desc->wl18xx_checksum_data = 0;
 891                 return;
 892         }
 893
 894         if (skb->ip_summed != CHECKSUM_PARTIAL) {
 895                 desc->wl18xx_checksum_data = 0;
 896                 return;
 897         }
 898
 899         ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
 900         if (WARN_ON(ip_hdr_offset >= (1<<7))) {
 901                 desc->wl18xx_checksum_data = 0;
 902                 return;
 903         }
 904
 905         desc->wl18xx_checksum_data = ip_hdr_offset << 1;
 906
 907         /* FW is interested only in the LSB of the protocol  TCP=0 UDP=1 */
 908         ip_hdr = (void *)skb_network_header(skb);
 909         desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
 910 }
 911
 912 static void wl18xx_set_rx_csum(struct wl1271 *wl,
 913                                struct wl1271_rx_descriptor *desc,
 914                                struct sk_buff *skb)
 915 {
 916         if (desc->status & WL18XX_RX_CHECKSUM_MASK)
 917                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 918 }
 919
 920 /*
 921  * TODO: instead of having these two functions to get the rate mask,
 922  * we should modify the wlvif->rate_set instead
 923  */
 924 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
 925                                        struct wl12xx_vif *wlvif)
 926 {
 927         u32 hw_rate_set = wlvif->rate_set;
 928
 929         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
 930             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
 931                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
 932                 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
 933
 934                 /* we don't support MIMO in wide-channel mode */
 935                 hw_rate_set &= ~CONF_TX_MIMO_RATES;
 936         }
 937
 938         return hw_rate_set;
 939 }
 940
 941 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
 942                                              struct wl12xx_vif *wlvif)
 943 {
 944         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
 945             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
 946                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
 947                 return CONF_TX_RATE_USE_WIDE_CHAN;
 948         } else {
 949                 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
 950
 951                 /*
 952                  * PG 1.0 has some problems with MCS_13, so disable it
 953                  *
 954                  * TODO: instead of hacking this in here, we should
 955                  * make it more general and change a bit in the
 956                  * wlvif->rate_set instead.
 957                  */
 958                 if (wl->chip.id == CHIP_ID_185x_PG10)
 959                         return CONF_TX_MIMO_RATES & ~CONF_HW_BIT_RATE_MCS_13;
 960
 961                 return CONF_TX_MIMO_RATES;
 962         }
 963 }
 964
 965 static s8 wl18xx_get_pg_ver(struct wl1271 *wl)
 966 {
 967         u32 fuse;
 968
 969         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 970
 971         fuse = wl1271_read32(wl, WL18XX_REG_FUSE_DATA_1_3);
 972         fuse = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
 973
 974         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 975
 976         return (s8)fuse;
 977 }
 978
 979 static void wl18xx_conf_init(struct wl1271 *wl)
 980 {
 981         struct wl18xx_priv *priv = wl->priv;
 982
 983         /* apply driver default configuration */
 984         memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
 985
 986         /* apply default private configuration */
 987         memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
 988 }
 989
 990 static int wl18xx_plt_init(struct wl1271 *wl)
 991 {
 992         wl1271_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
 993
 994         return wl->ops->boot(wl);
 995 }
 996
 997 static void wl18xx_get_mac(struct wl1271 *wl)
 998 {
 999         u32 mac1, mac2;
1000
1001         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1002
1003         mac1 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1);
1004         mac2 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2);
1005
1006         /* these are the two parts of the BD_ADDR */
1007         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1008                 ((mac1 & 0xff000000) >> 24);
1009         wl->fuse_nic_addr = (mac1 & 0xffffff);
1010
1011         wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1012 }
1013
1014 static struct wlcore_ops wl18xx_ops = {
1015         .identify_chip  = wl18xx_identify_chip,
1016         .boot           = wl18xx_boot,
1017         .plt_init       = wl18xx_plt_init,
1018         .trigger_cmd    = wl18xx_trigger_cmd,
1019         .ack_event      = wl18xx_ack_event,
1020         .calc_tx_blocks = wl18xx_calc_tx_blocks,
1021         .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1022         .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1023         .get_rx_buf_align = wl18xx_get_rx_buf_align,
1024         .get_rx_packet_len = wl18xx_get_rx_packet_len,
1025         .tx_immediate_compl = wl18xx_tx_immediate_completion,
1026         .tx_delayed_compl = NULL,
1027         .hw_init        = wl18xx_hw_init,
1028         .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1029         .get_pg_ver     = wl18xx_get_pg_ver,
1030         .set_rx_csum = wl18xx_set_rx_csum,
1031         .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1032         .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1033         .get_mac        = wl18xx_get_mac,
1034 };
1035
1036 /* HT cap appropriate for wide channels */
1037 static struct ieee80211_sta_ht_cap wl18xx_ht_cap = {
1038         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1039                IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
1040         .ht_supported = true,
1041         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1042         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1043         .mcs = {
1044                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1045                 .rx_highest = cpu_to_le16(150),
1046                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1047                 },
1048 };
1049
1050 /* HT cap appropriate for MIMO rates in 20mhz channel */
1051 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap = {
1052         .cap = IEEE80211_HT_CAP_SGI_20,
1053         .ht_supported = true,
1054         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1055         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1056         .mcs = {
1057                 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1058                 .rx_highest = cpu_to_le16(144),
1059                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1060                 },
1061 };
1062
1063 int __devinit wl18xx_probe(struct platform_device *pdev)
1064 {
1065         struct wl1271 *wl;
1066         struct ieee80211_hw *hw;
1067         struct wl18xx_priv *priv;
1068
1069         hw = wlcore_alloc_hw(sizeof(*priv));
1070         if (IS_ERR(hw)) {
1071                 wl1271_error("can't allocate hw");
1072                 return PTR_ERR(hw);
1073         }
1074
1075         wl = hw->priv;
1076         priv = wl->priv;
1077         wl->ops = &wl18xx_ops;
1078         wl->ptable = wl18xx_ptable;
1079         wl->rtable = wl18xx_rtable;
1080         wl->num_tx_desc = 32;
1081         wl->num_rx_desc = 16;
1082         wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE;
1083         wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE;
1084         wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1085         wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1086         wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1087         wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1088         memcpy(&wl->ht_cap, &wl18xx_ht_cap, sizeof(wl18xx_ht_cap));
1089         if (ht_mode_param && !strcmp(ht_mode_param, "mimo"))
1090                 memcpy(&wl->ht_cap, &wl18xx_mimo_ht_cap,
1091                        sizeof(wl18xx_mimo_ht_cap));
1092
1093         wl18xx_conf_init(wl);
1094
1095         if (!strcmp(board_type_param, "fpga")) {
1096                 priv->board_type = BOARD_TYPE_FPGA_18XX;
1097         } else if (!strcmp(board_type_param, "hdk")) {
1098                 priv->board_type = BOARD_TYPE_HDK_18XX;
1099                 /* HACK! Just for now we hardcode HDK to 0x06 */
1100                 priv->conf.phy.low_band_component_type = 0x06;
1101         } else if (!strcmp(board_type_param, "dvp")) {
1102                 priv->board_type = BOARD_TYPE_DVP_18XX;
1103         } else if (!strcmp(board_type_param, "evb")) {
1104                 priv->board_type = BOARD_TYPE_EVB_18XX;
1105         } else if (!strcmp(board_type_param, "com8")) {
1106                 priv->board_type = BOARD_TYPE_COM8_18XX;
1107                 /* HACK! Just for now we hardcode COM8 to 0x06 */
1108                 priv->conf.phy.low_band_component_type = 0x06;
1109         } else {
1110                 wl1271_error("invalid board type '%s'", board_type_param);
1111                 wlcore_free_hw(wl);
1112                 return -EINVAL;
1113         }
1114
1115         if (!checksum_param) {
1116                 wl18xx_ops.set_rx_csum = NULL;
1117                 wl18xx_ops.init_vif = NULL;
1118         }
1119
1120         wl->enable_11a = enable_11a_param;
1121
1122         return wlcore_probe(wl, pdev);
1123 }
1124
1125 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1126         { "wl18xx", 0 },
1127         {  } /* Terminating Entry */
1128 };
1129 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1130
1131 static struct platform_driver wl18xx_driver = {
1132         .probe          = wl18xx_probe,
1133         .remove         = __devexit_p(wlcore_remove),
1134         .id_table       = wl18xx_id_table,
1135         .driver = {
1136                 .name   = "wl18xx_driver",
1137                 .owner  = THIS_MODULE,
1138         }
1139 };
1140
1141 static int __init wl18xx_init(void)
1142 {
1143         return platform_driver_register(&wl18xx_driver);
1144 }
1145 module_init(wl18xx_init);
1146
1147 static void __exit wl18xx_exit(void)
1148 {
1149         platform_driver_unregister(&wl18xx_driver);
1150 }
1151 module_exit(wl18xx_exit);
1152
1153 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1154 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or mimo");
1155
1156 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1157 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1158                  "dvp");
1159
1160 module_param_named(dc2dc, dc2dc_param, bool, S_IRUSR);
1161 MODULE_PARM_DESC(dc2dc, "External DC2DC: boolean (defaults to false)");
1162
1163 module_param_named(n_antennas_2, n_antennas_2_param, uint, S_IRUSR);
1164 MODULE_PARM_DESC(n_antennas_2, "Number of installed 2.4GHz antennas: 1 (default) or 2");
1165
1166 module_param_named(n_antennas_5, n_antennas_5_param, uint, S_IRUSR);
1167 MODULE_PARM_DESC(n_antennas_5, "Number of installed 5GHz antennas: 1 (default) or 2");
1168
1169 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1170 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to true)");
1171
1172 module_param_named(enable_11a, enable_11a_param, bool, S_IRUSR);
1173 MODULE_PARM_DESC(enable_11a, "Enable 11a (5GHz): boolean (defaults to true)");
1174
1175 MODULE_LICENSE("GPL v2");
1176 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1177 MODULE_FIRMWARE(WL18XX_FW_NAME);