2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
15 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Intel PCIe NTB Linux driver
45 * Contact Information:
46 * Jon Mason <jon.mason@intel.com>
48 #include <linux/debugfs.h>
49 #include <linux/init.h>
50 #include <linux/interrupt.h>
51 #include <linux/module.h>
52 #include <linux/pci.h>
53 #include <linux/slab.h>
57 #define NTB_NAME "Intel(R) PCI-E Non-Transparent Bridge Driver"
58 #define NTB_VER "0.25"
60 MODULE_DESCRIPTION(NTB_NAME);
61 MODULE_VERSION(NTB_VER);
62 MODULE_LICENSE("Dual BSD/GPL");
63 MODULE_AUTHOR("Intel Corporation");
65 static bool xeon_errata_workaround = true;
66 module_param(xeon_errata_workaround, bool, 0644);
67 MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
85 static struct dentry *debugfs_dir;
87 /* Translate memory window 0,1 to BAR 2,4 */
88 #define MW_TO_BAR(mw) (mw * NTB_MAX_NUM_MW + 2)
90 static DEFINE_PCI_DEVICE_TABLE(ntb_pci_tbl) = {
91 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
92 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
93 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_CLASSIC_JSF)},
94 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_RP_JSF)},
95 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_RP_SNB)},
96 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
97 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_CLASSIC_SNB)},
100 MODULE_DEVICE_TABLE(pci, ntb_pci_tbl);
103 * ntb_register_event_callback() - register event callback
104 * @ndev: pointer to ntb_device instance
105 * @func: callback function to register
107 * This function registers a callback for any HW driver events such as link
108 * up/down, power management notices and etc.
110 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
112 int ntb_register_event_callback(struct ntb_device *ndev,
113 void (*func)(void *handle, enum ntb_hw_event event))
118 ndev->event_cb = func;
124 * ntb_unregister_event_callback() - unregisters the event callback
125 * @ndev: pointer to ntb_device instance
127 * This function unregisters the existing callback from transport
129 void ntb_unregister_event_callback(struct ntb_device *ndev)
131 ndev->event_cb = NULL;
135 * ntb_register_db_callback() - register a callback for doorbell interrupt
136 * @ndev: pointer to ntb_device instance
137 * @idx: doorbell index to register callback, zero based
138 * @func: callback function to register
140 * This function registers a callback function for the doorbell interrupt
141 * on the primary side. The function will unmask the doorbell as well to
144 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
146 int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
147 void *data, void (*func)(void *data, int db_num))
151 if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) {
152 dev_warn(&ndev->pdev->dev, "Invalid Index.\n");
156 ndev->db_cb[idx].callback = func;
157 ndev->db_cb[idx].data = data;
159 /* unmask interrupt */
160 mask = readw(ndev->reg_ofs.pdb_mask);
161 clear_bit(idx * ndev->bits_per_vector, &mask);
162 writew(mask, ndev->reg_ofs.pdb_mask);
168 * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
169 * @ndev: pointer to ntb_device instance
170 * @idx: doorbell index to register callback, zero based
172 * This function unregisters a callback function for the doorbell interrupt
173 * on the primary side. The function will also mask the said doorbell.
175 void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
179 if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback)
182 mask = readw(ndev->reg_ofs.pdb_mask);
183 set_bit(idx * ndev->bits_per_vector, &mask);
184 writew(mask, ndev->reg_ofs.pdb_mask);
186 ndev->db_cb[idx].callback = NULL;
190 * ntb_find_transport() - find the transport pointer
191 * @transport: pointer to pci device
193 * Given the pci device pointer, return the transport pointer passed in when
194 * the transport attached when it was inited.
196 * RETURNS: pointer to transport.
198 void *ntb_find_transport(struct pci_dev *pdev)
200 struct ntb_device *ndev = pci_get_drvdata(pdev);
201 return ndev->ntb_transport;
205 * ntb_register_transport() - Register NTB transport with NTB HW driver
206 * @transport: transport identifier
208 * This function allows a transport to reserve the hardware driver for
211 * RETURNS: pointer to ntb_device, NULL on error.
213 struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport)
215 struct ntb_device *ndev = pci_get_drvdata(pdev);
217 if (ndev->ntb_transport)
220 ndev->ntb_transport = transport;
225 * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
226 * @ndev - ntb_device of the transport to be freed
228 * This function unregisters the transport from the HW driver and performs any
229 * necessary cleanups.
231 void ntb_unregister_transport(struct ntb_device *ndev)
235 if (!ndev->ntb_transport)
238 for (i = 0; i < ndev->max_cbs; i++)
239 ntb_unregister_db_callback(ndev, i);
241 ntb_unregister_event_callback(ndev);
242 ndev->ntb_transport = NULL;
246 * ntb_write_local_spad() - write to the secondary scratchpad register
247 * @ndev: pointer to ntb_device instance
248 * @idx: index to the scratchpad register, 0 based
249 * @val: the data value to put into the register
251 * This function allows writing of a 32bit value to the indexed scratchpad
252 * register. This writes over the data mirrored to the local scratchpad register
253 * by the remote system.
255 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
257 int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
259 if (idx >= ndev->limits.max_spads)
262 dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n",
264 writel(val, ndev->reg_ofs.spad_read + idx * 4);
270 * ntb_read_local_spad() - read from the primary scratchpad register
271 * @ndev: pointer to ntb_device instance
272 * @idx: index to scratchpad register, 0 based
273 * @val: pointer to 32bit integer for storing the register value
275 * This function allows reading of the 32bit scratchpad register on
276 * the primary (internal) side. This allows the local system to read data
277 * written and mirrored to the scratchpad register by the remote system.
279 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
281 int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
283 if (idx >= ndev->limits.max_spads)
286 *val = readl(ndev->reg_ofs.spad_write + idx * 4);
287 dev_dbg(&ndev->pdev->dev,
288 "Reading %x from local scratch pad index %d\n", *val, idx);
294 * ntb_write_remote_spad() - write to the secondary scratchpad register
295 * @ndev: pointer to ntb_device instance
296 * @idx: index to the scratchpad register, 0 based
297 * @val: the data value to put into the register
299 * This function allows writing of a 32bit value to the indexed scratchpad
300 * register. The register resides on the secondary (external) side. This allows
301 * the local system to write data to be mirrored to the remote systems
302 * scratchpad register.
304 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
306 int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
308 if (idx >= ndev->limits.max_spads)
311 dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n",
313 writel(val, ndev->reg_ofs.spad_write + idx * 4);
319 * ntb_read_remote_spad() - read from the primary scratchpad register
320 * @ndev: pointer to ntb_device instance
321 * @idx: index to scratchpad register, 0 based
322 * @val: pointer to 32bit integer for storing the register value
324 * This function allows reading of the 32bit scratchpad register on
325 * the primary (internal) side. This alloows the local system to read the data
326 * it wrote to be mirrored on the remote system.
328 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
330 int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
332 if (idx >= ndev->limits.max_spads)
335 *val = readl(ndev->reg_ofs.spad_read + idx * 4);
336 dev_dbg(&ndev->pdev->dev,
337 "Reading %x from remote scratch pad index %d\n", *val, idx);
343 * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
344 * @ndev: pointer to ntb_device instance
345 * @mw: memory window number
347 * This function provides the base virtual address of the memory window
350 * RETURNS: pointer to virtual address, or NULL on error.
352 void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw)
354 if (mw >= ntb_max_mw(ndev))
357 return ndev->mw[mw].vbase;
361 * ntb_get_mw_size() - return size of NTB memory window
362 * @ndev: pointer to ntb_device instance
363 * @mw: memory window number
365 * This function provides the physical size of the memory window specified
367 * RETURNS: the size of the memory window or zero on error
369 resource_size_t ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)
371 if (mw >= ntb_max_mw(ndev))
374 return ndev->mw[mw].bar_sz;
378 * ntb_set_mw_addr - set the memory window address
379 * @ndev: pointer to ntb_device instance
380 * @mw: memory window number
381 * @addr: base address for data
383 * This function sets the base physical address of the memory window. This
384 * memory address is where data from the remote system will be transfered into
385 * or out of depending on how the transport is configured.
387 void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
389 if (mw >= ntb_max_mw(ndev))
392 dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr,
395 ndev->mw[mw].phys_addr = addr;
397 switch (MW_TO_BAR(mw)) {
399 writeq(addr, ndev->reg_ofs.sbar2_xlat);
402 writeq(addr, ndev->reg_ofs.sbar4_xlat);
408 * ntb_ring_sdb() - Set the doorbell on the secondary/external side
409 * @ndev: pointer to ntb_device instance
410 * @db: doorbell to ring
412 * This function allows triggering of a doorbell on the secondary/external
413 * side that will initiate an interrupt on the remote host
415 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
417 void ntb_ring_sdb(struct ntb_device *ndev, unsigned int db)
419 dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db);
421 if (ndev->hw_type == BWD_HW)
422 writeq((u64) 1 << db, ndev->reg_ofs.sdb);
424 writew(((1 << ndev->bits_per_vector) - 1) <<
425 (db * ndev->bits_per_vector), ndev->reg_ofs.sdb);
428 static void ntb_link_event(struct ntb_device *ndev, int link_state)
432 if (ndev->link_status == link_state)
435 if (link_state == NTB_LINK_UP) {
438 dev_info(&ndev->pdev->dev, "Link Up\n");
439 ndev->link_status = NTB_LINK_UP;
440 event = NTB_EVENT_HW_LINK_UP;
442 if (ndev->hw_type == BWD_HW)
443 status = readw(ndev->reg_ofs.lnk_stat);
445 int rc = pci_read_config_word(ndev->pdev,
446 SNB_LINK_STATUS_OFFSET,
451 dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n",
452 (status & NTB_LINK_WIDTH_MASK) >> 4,
453 (status & NTB_LINK_SPEED_MASK));
455 dev_info(&ndev->pdev->dev, "Link Down\n");
456 ndev->link_status = NTB_LINK_DOWN;
457 event = NTB_EVENT_HW_LINK_DOWN;
460 /* notify the upper layer if we have an event change */
462 ndev->event_cb(ndev->ntb_transport, event);
465 static int ntb_link_status(struct ntb_device *ndev)
469 if (ndev->hw_type == BWD_HW) {
472 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
473 if (ntb_cntl & BWD_CNTL_LINK_DOWN)
474 link_state = NTB_LINK_DOWN;
476 link_state = NTB_LINK_UP;
481 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
486 if (status & NTB_LINK_STATUS_ACTIVE)
487 link_state = NTB_LINK_UP;
489 link_state = NTB_LINK_DOWN;
492 ntb_link_event(ndev, link_state);
497 /* BWD doesn't have link status interrupt, poll on that platform */
498 static void bwd_link_poll(struct work_struct *work)
500 struct ntb_device *ndev = container_of(work, struct ntb_device,
502 unsigned long ts = jiffies;
504 /* If we haven't gotten an interrupt in a while, check the BWD link
507 if (ts > ndev->last_ts + NTB_HB_TIMEOUT) {
508 int rc = ntb_link_status(ndev);
510 dev_err(&ndev->pdev->dev,
511 "Error determining link status\n");
514 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
517 static int ntb_xeon_setup(struct ntb_device *ndev)
522 ndev->hw_type = SNB_HW;
524 rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &val);
528 switch (val & SNB_PPD_CONN_TYPE) {
530 ndev->conn_type = NTB_CONN_B2B;
532 case NTB_CONN_CLASSIC:
535 dev_err(&ndev->pdev->dev, "Only B2B supported at this time\n");
539 if (val & SNB_PPD_DEV_TYPE)
540 ndev->dev_type = NTB_DEV_USD;
542 ndev->dev_type = NTB_DEV_DSD;
544 ndev->reg_ofs.pdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
545 ndev->reg_ofs.pdb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
546 ndev->reg_ofs.sbar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
547 ndev->reg_ofs.sbar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
548 ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
549 ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_LINK_STATUS_OFFSET;
550 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
551 ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
553 /* There is a Xeon hardware errata related to writes to
554 * SDOORBELL or B2BDOORBELL in conjunction with inbound access
555 * to NTB MMIO Space, which may hang the system. To workaround
556 * this use the second memory window to access the interrupt and
557 * scratch pad registers on the remote system.
559 if (xeon_errata_workaround) {
560 if (!ndev->mw[1].bar_sz)
563 ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
564 ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
566 ndev->reg_ofs.sdb = ndev->mw[1].vbase +
567 SNB_PDOORBELL_OFFSET;
569 /* Set the Limit register to 4k, the minimum size, to
570 * prevent an illegal access
572 writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
573 SNB_PBAR4LMT_OFFSET);
575 ndev->limits.max_mw = SNB_MAX_MW;
576 ndev->reg_ofs.spad_write = ndev->reg_base +
578 ndev->reg_ofs.sdb = ndev->reg_base +
579 SNB_B2B_DOORBELL_OFFSET;
581 /* Disable the Limit register, just incase it is set to
584 writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
587 /* The Xeon errata workaround requires setting SBAR Base
588 * addresses to known values, so that the PBAR XLAT can be
589 * pointed at SBAR0 of the remote system.
591 if (ndev->dev_type == NTB_DEV_USD) {
592 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
593 SNB_PBAR2XLAT_OFFSET);
594 if (xeon_errata_workaround)
595 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
596 SNB_PBAR4XLAT_OFFSET);
598 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
599 SNB_PBAR4XLAT_OFFSET);
600 /* B2B_XLAT_OFFSET is a 64bit register, but can
601 * only take 32bit writes
603 writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
604 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
605 writel(SNB_MBAR01_DSD_ADDR >> 32,
606 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
609 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
610 SNB_SBAR0BASE_OFFSET);
611 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
612 SNB_SBAR2BASE_OFFSET);
613 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
614 SNB_SBAR4BASE_OFFSET);
616 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
617 SNB_PBAR2XLAT_OFFSET);
618 if (xeon_errata_workaround)
619 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
620 SNB_PBAR4XLAT_OFFSET);
622 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
623 SNB_PBAR4XLAT_OFFSET);
624 /* B2B_XLAT_OFFSET is a 64bit register, but can
625 * only take 32bit writes
627 writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
628 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
629 writel(SNB_MBAR01_USD_ADDR >> 32,
630 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
632 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
633 SNB_SBAR0BASE_OFFSET);
634 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
635 SNB_SBAR2BASE_OFFSET);
636 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
637 SNB_SBAR4BASE_OFFSET);
640 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
641 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
642 ndev->limits.msix_cnt = SNB_MSIX_CNT;
643 ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
648 static int ntb_bwd_setup(struct ntb_device *ndev)
653 ndev->hw_type = BWD_HW;
655 rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val);
659 switch ((val & BWD_PPD_CONN_TYPE) >> 8) {
661 ndev->conn_type = NTB_CONN_B2B;
665 dev_err(&ndev->pdev->dev, "Only B2B supported at this time\n");
669 if (val & BWD_PPD_DEV_TYPE)
670 ndev->dev_type = NTB_DEV_DSD;
672 ndev->dev_type = NTB_DEV_USD;
674 /* Initiate PCI-E link training */
675 rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET,
676 val | BWD_PPD_INIT_LINK);
680 ndev->reg_ofs.pdb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
681 ndev->reg_ofs.pdb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
682 ndev->reg_ofs.sbar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
683 ndev->reg_ofs.sbar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
684 ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
685 ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
686 ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
687 ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
689 if (ndev->conn_type == NTB_CONN_B2B) {
690 ndev->reg_ofs.sdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
691 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
692 ndev->limits.max_spads = BWD_MAX_SPADS;
694 ndev->reg_ofs.sdb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
695 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_SPAD_OFFSET;
696 ndev->limits.max_spads = BWD_MAX_COMPAT_SPADS;
699 ndev->limits.max_mw = BWD_MAX_MW;
700 ndev->limits.max_db_bits = BWD_MAX_DB_BITS;
701 ndev->limits.msix_cnt = BWD_MSIX_CNT;
702 ndev->bits_per_vector = BWD_DB_BITS_PER_VEC;
704 /* Since bwd doesn't have a link interrupt, setup a poll timer */
705 INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll);
706 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
711 static int ntb_device_setup(struct ntb_device *ndev)
715 switch (ndev->pdev->device) {
716 case PCI_DEVICE_ID_INTEL_NTB_2ND_SNB:
717 case PCI_DEVICE_ID_INTEL_NTB_RP_JSF:
718 case PCI_DEVICE_ID_INTEL_NTB_RP_SNB:
719 case PCI_DEVICE_ID_INTEL_NTB_CLASSIC_JSF:
720 case PCI_DEVICE_ID_INTEL_NTB_CLASSIC_SNB:
721 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
722 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
723 rc = ntb_xeon_setup(ndev);
725 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
726 rc = ntb_bwd_setup(ndev);
735 dev_info(&ndev->pdev->dev, "Device Type = %s\n",
736 ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
738 /* Enable Bus Master and Memory Space on the secondary side */
739 writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, ndev->reg_ofs.spci_cmd);
744 static void ntb_device_free(struct ntb_device *ndev)
746 if (ndev->hw_type == BWD_HW)
747 cancel_delayed_work_sync(&ndev->hb_timer);
750 static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
752 struct ntb_db_cb *db_cb = data;
753 struct ntb_device *ndev = db_cb->ndev;
755 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
759 db_cb->callback(db_cb->data, db_cb->db_num);
761 /* No need to check for the specific HB irq, any interrupt means
764 ndev->last_ts = jiffies;
766 writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.pdb);
771 static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
773 struct ntb_db_cb *db_cb = data;
774 struct ntb_device *ndev = db_cb->ndev;
776 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
780 db_cb->callback(db_cb->data, db_cb->db_num);
782 /* On Sandybridge, there are 16 bits in the interrupt register
783 * but only 4 vectors. So, 5 bits are assigned to the first 3
784 * vectors, with the 4th having a single bit for link
787 writew(((1 << ndev->bits_per_vector) - 1) <<
788 (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.pdb);
793 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
794 static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
796 struct ntb_device *ndev = dev;
799 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq);
801 rc = ntb_link_status(ndev);
803 dev_err(&ndev->pdev->dev, "Error determining link status\n");
805 /* bit 15 is always the link bit */
806 writew(1 << ndev->limits.max_db_bits, ndev->reg_ofs.pdb);
811 static irqreturn_t ntb_interrupt(int irq, void *dev)
813 struct ntb_device *ndev = dev;
816 if (ndev->hw_type == BWD_HW) {
817 u64 pdb = readq(ndev->reg_ofs.pdb);
819 dev_dbg(&ndev->pdev->dev, "irq %d - pdb = %Lx\n", irq, pdb);
824 bwd_callback_msix_irq(irq, &ndev->db_cb[i]);
827 u16 pdb = readw(ndev->reg_ofs.pdb);
829 dev_dbg(&ndev->pdev->dev, "irq %d - pdb = %x sdb %x\n", irq,
830 pdb, readw(ndev->reg_ofs.sdb));
832 if (pdb & SNB_DB_HW_LINK) {
833 xeon_event_msix_irq(irq, dev);
834 pdb &= ~SNB_DB_HW_LINK;
840 xeon_callback_msix_irq(irq, &ndev->db_cb[i]);
847 static int ntb_setup_msix(struct ntb_device *ndev)
849 struct pci_dev *pdev = ndev->pdev;
850 struct msix_entry *msix;
855 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
861 rc = pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &val);
865 msix_entries = msix_table_size(val);
866 if (msix_entries > ndev->limits.msix_cnt) {
871 ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries,
873 if (!ndev->msix_entries) {
878 for (i = 0; i < msix_entries; i++)
879 ndev->msix_entries[i].entry = i;
881 rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
885 /* On SNB, the link interrupt is always tied to 4th vector. If
886 * we can't get all 4, then we can't use MSI-X.
888 if (ndev->hw_type != BWD_HW) {
894 "Only %d MSI-X vectors. Limiting the number of queues to that number.\n",
899 for (i = 0; i < msix_entries; i++) {
900 msix = &ndev->msix_entries[i];
901 WARN_ON(!msix->vector);
903 /* Use the last MSI-X vector for Link status */
904 if (ndev->hw_type == BWD_HW) {
905 rc = request_irq(msix->vector, bwd_callback_msix_irq, 0,
906 "ntb-callback-msix", &ndev->db_cb[i]);
910 if (i == msix_entries - 1) {
911 rc = request_irq(msix->vector,
912 xeon_event_msix_irq, 0,
913 "ntb-event-msix", ndev);
917 rc = request_irq(msix->vector,
918 xeon_callback_msix_irq, 0,
927 ndev->num_msix = msix_entries;
928 if (ndev->hw_type == BWD_HW)
929 ndev->max_cbs = msix_entries;
931 ndev->max_cbs = msix_entries - 1;
937 msix = &ndev->msix_entries[i];
938 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
939 free_irq(msix->vector, ndev);
941 free_irq(msix->vector, &ndev->db_cb[i]);
943 pci_disable_msix(pdev);
945 kfree(ndev->msix_entries);
946 dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n");
952 static int ntb_setup_msi(struct ntb_device *ndev)
954 struct pci_dev *pdev = ndev->pdev;
957 rc = pci_enable_msi(pdev);
961 rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev);
963 pci_disable_msi(pdev);
964 dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
971 static int ntb_setup_intx(struct ntb_device *ndev)
973 struct pci_dev *pdev = ndev->pdev;
978 /* Verify intx is enabled */
981 rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx",
989 static int ntb_setup_interrupts(struct ntb_device *ndev)
993 /* On BWD, disable all interrupts. On SNB, disable all but Link
994 * Interrupt. The rest will be unmasked as callbacks are registered.
996 if (ndev->hw_type == BWD_HW)
997 writeq(~0, ndev->reg_ofs.pdb_mask);
999 writew(~(1 << ndev->limits.max_db_bits),
1000 ndev->reg_ofs.pdb_mask);
1002 rc = ntb_setup_msix(ndev);
1006 ndev->bits_per_vector = 1;
1007 ndev->max_cbs = ndev->limits.max_db_bits;
1009 rc = ntb_setup_msi(ndev);
1013 rc = ntb_setup_intx(ndev);
1015 dev_err(&ndev->pdev->dev, "no usable interrupts\n");
1023 static void ntb_free_interrupts(struct ntb_device *ndev)
1025 struct pci_dev *pdev = ndev->pdev;
1027 /* mask interrupts */
1028 if (ndev->hw_type == BWD_HW)
1029 writeq(~0, ndev->reg_ofs.pdb_mask);
1031 writew(~0, ndev->reg_ofs.pdb_mask);
1033 if (ndev->num_msix) {
1034 struct msix_entry *msix;
1037 for (i = 0; i < ndev->num_msix; i++) {
1038 msix = &ndev->msix_entries[i];
1039 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1040 free_irq(msix->vector, ndev);
1042 free_irq(msix->vector, &ndev->db_cb[i]);
1044 pci_disable_msix(pdev);
1046 free_irq(pdev->irq, ndev);
1048 if (pci_dev_msi_enabled(pdev))
1049 pci_disable_msi(pdev);
1053 static int ntb_create_callbacks(struct ntb_device *ndev)
1057 /* Checken-egg issue. We won't know how many callbacks are necessary
1058 * until we see how many MSI-X vectors we get, but these pointers need
1059 * to be passed into the MSI-X register fucntion. So, we allocate the
1060 * max, knowing that they might not all be used, to work around this.
1062 ndev->db_cb = kcalloc(ndev->limits.max_db_bits,
1063 sizeof(struct ntb_db_cb),
1068 for (i = 0; i < ndev->limits.max_db_bits; i++) {
1069 ndev->db_cb[i].db_num = i;
1070 ndev->db_cb[i].ndev = ndev;
1076 static void ntb_free_callbacks(struct ntb_device *ndev)
1080 for (i = 0; i < ndev->limits.max_db_bits; i++)
1081 ntb_unregister_db_callback(ndev, i);
1086 static void ntb_setup_debugfs(struct ntb_device *ndev)
1088 if (!debugfs_initialized())
1092 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
1094 ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev),
1098 static void ntb_free_debugfs(struct ntb_device *ndev)
1100 debugfs_remove_recursive(ndev->debugfs_dir);
1102 if (debugfs_dir && simple_empty(debugfs_dir)) {
1103 debugfs_remove_recursive(debugfs_dir);
1108 static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1110 struct ntb_device *ndev;
1113 ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL);
1118 ndev->link_status = NTB_LINK_DOWN;
1119 pci_set_drvdata(pdev, ndev);
1120 ntb_setup_debugfs(ndev);
1122 rc = pci_enable_device(pdev);
1126 pci_set_master(ndev->pdev);
1128 rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
1132 ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1133 if (!ndev->reg_base) {
1134 dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
1139 for (i = 0; i < NTB_MAX_NUM_MW; i++) {
1140 ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
1142 ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
1143 ndev->mw[i].bar_sz);
1144 dev_info(&pdev->dev, "MW %d size %llu\n", i,
1145 pci_resource_len(pdev, MW_TO_BAR(i)));
1146 if (!ndev->mw[i].vbase) {
1147 dev_warn(&pdev->dev, "Cannot remap BAR %d\n",
1154 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1156 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1160 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
1163 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1165 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1169 dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
1172 rc = ntb_device_setup(ndev);
1176 rc = ntb_create_callbacks(ndev);
1180 rc = ntb_setup_interrupts(ndev);
1184 /* The scratchpad registers keep the values between rmmod/insmod,
1187 for (i = 0; i < ndev->limits.max_spads; i++) {
1188 ntb_write_local_spad(ndev, i, 0);
1189 ntb_write_remote_spad(ndev, i, 0);
1192 rc = ntb_transport_init(pdev);
1196 /* Let's bring the NTB link up */
1197 writel(NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP,
1198 ndev->reg_ofs.lnk_cntl);
1203 ntb_free_interrupts(ndev);
1205 ntb_free_callbacks(ndev);
1207 ntb_device_free(ndev);
1209 for (i--; i >= 0; i--)
1210 iounmap(ndev->mw[i].vbase);
1211 iounmap(ndev->reg_base);
1213 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1215 pci_disable_device(pdev);
1217 ntb_free_debugfs(ndev);
1220 dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME);
1224 static void ntb_pci_remove(struct pci_dev *pdev)
1226 struct ntb_device *ndev = pci_get_drvdata(pdev);
1230 /* Bring NTB link down */
1231 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1232 ntb_cntl |= NTB_LINK_DISABLE;
1233 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1235 ntb_transport_free(ndev->ntb_transport);
1237 ntb_free_interrupts(ndev);
1238 ntb_free_callbacks(ndev);
1239 ntb_device_free(ndev);
1241 for (i = 0; i < NTB_MAX_NUM_MW; i++)
1242 iounmap(ndev->mw[i].vbase);
1244 iounmap(ndev->reg_base);
1245 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1246 pci_disable_device(pdev);
1247 ntb_free_debugfs(ndev);
1251 static struct pci_driver ntb_pci_driver = {
1252 .name = KBUILD_MODNAME,
1253 .id_table = ntb_pci_tbl,
1254 .probe = ntb_pci_probe,
1255 .remove = ntb_pci_remove,
1257 module_pci_driver(ntb_pci_driver);