drivers/ntb/ntb_hw.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  *   redistributing this file, you may do so under either license.
   4  *
   5  *   GPL LICENSE SUMMARY
   6  *
   7  *   Copyright(c) 2012 Intel Corporation. All rights reserved.
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of version 2 of the GNU General Public License as
  11  *   published by the Free Software Foundation.
  12  *
  13  *   BSD LICENSE
  14  *
  15  *   Copyright(c) 2012 Intel Corporation. All rights reserved.
  16  *
  17  *   Redistribution and use in source and binary forms, with or without
  18  *   modification, are permitted provided that the following conditions
  19  *   are met:
  20  *
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copy
  24  *       notice, this list of conditions and the following disclaimer in
  25  *       the documentation and/or other materials provided with the
  26  *       distribution.
  27  *     * Neither the name of Intel Corporation nor the names of its
  28  *       contributors may be used to endorse or promote products derived
  29  *       from this software without specific prior written permission.
  30  *
  31  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  32  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  33  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  34  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  35  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  36  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  37  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  39  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  * Intel PCIe NTB Linux driver
  44  *
  45  * Contact Information:
  46  * Jon Mason <jon.mason@intel.com>
  47  */
  48 #include <linux/debugfs.h>
  49 #include <linux/delay.h>
  50 #include <linux/init.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/module.h>
  53 #include <linux/pci.h>
  54 #include <linux/random.h>
  55 #include <linux/slab.h>
  56 #include "ntb_hw.h"
  57 #include "ntb_regs.h"
  58
  59 #define NTB_NAME        "Intel(R) PCI-E Non-Transparent Bridge Driver"
  60 #define NTB_VER         "1.0"
  61
  62 MODULE_DESCRIPTION(NTB_NAME);
  63 MODULE_VERSION(NTB_VER);
  64 MODULE_LICENSE("Dual BSD/GPL");
  65 MODULE_AUTHOR("Intel Corporation");
  66
  67 static bool xeon_errata_workaround = true;
  68 module_param(xeon_errata_workaround, bool, 0644);
  69 MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
  70
  71 enum {
  72         NTB_CONN_TRANSPARENT = 0,
  73         NTB_CONN_B2B,
  74         NTB_CONN_RP,
  75 };
  76
  77 enum {
  78         NTB_DEV_USD = 0,
  79         NTB_DEV_DSD,
  80 };
  81
  82 enum {
  83         SNB_HW = 0,
  84         BWD_HW,
  85 };
  86
  87 static struct dentry *debugfs_dir;
  88
  89 #define BWD_LINK_RECOVERY_TIME  500
  90
  91 /* Translate memory window 0,1 to BAR 2,4 */
  92 #define MW_TO_BAR(mw)   (mw * NTB_MAX_NUM_MW + 2)
  93
  94 static const struct pci_device_id ntb_pci_tbl[] = {
  95         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
  96         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
  97         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
  98         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
  99         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)},
 100         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)},
 101         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)},
 102         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)},
 103         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)},
 104         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)},
 105         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)},
 106         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
 107         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
 108         {0}
 109 };
 110 MODULE_DEVICE_TABLE(pci, ntb_pci_tbl);
 111
 112 static int is_ntb_xeon(struct ntb_device *ndev)
 113 {
 114         switch (ndev->pdev->device) {
 115         case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
 116         case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
 117         case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
 118         case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
 119         case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
 120         case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
 121         case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
 122         case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
 123         case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
 124         case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
 125         case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
 126         case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
 127                 return 1;
 128         default:
 129                 return 0;
 130         }
 131
 132         return 0;
 133 }
 134
 135 static int is_ntb_atom(struct ntb_device *ndev)
 136 {
 137         switch (ndev->pdev->device) {
 138         case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
 139                 return 1;
 140         default:
 141                 return 0;
 142         }
 143
 144         return 0;
 145 }
 146
 147 /**
 148  * ntb_register_event_callback() - register event callback
 149  * @ndev: pointer to ntb_device instance
 150  * @func: callback function to register
 151  *
 152  * This function registers a callback for any HW driver events such as link
 153  * up/down, power management notices and etc.
 154  *
 155  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 156  */
 157 int ntb_register_event_callback(struct ntb_device *ndev,
 158                                 void (*func)(void *handle,
 159                                              enum ntb_hw_event event))
 160 {
 161         if (ndev->event_cb)
 162                 return -EINVAL;
 163
 164         ndev->event_cb = func;
 165
 166         return 0;
 167 }
 168
 169 /**
 170  * ntb_unregister_event_callback() - unregisters the event callback
 171  * @ndev: pointer to ntb_device instance
 172  *
 173  * This function unregisters the existing callback from transport
 174  */
 175 void ntb_unregister_event_callback(struct ntb_device *ndev)
 176 {
 177         ndev->event_cb = NULL;
 178 }
 179
 180 static void ntb_irq_work(unsigned long data)
 181 {
 182         struct ntb_db_cb *db_cb = (struct ntb_db_cb *)data;
 183         int rc;
 184
 185         rc = db_cb->callback(db_cb->data, db_cb->db_num);
 186         if (rc)
 187                 tasklet_schedule(&db_cb->irq_work);
 188         else {
 189                 struct ntb_device *ndev = db_cb->ndev;
 190                 unsigned long mask;
 191
 192                 mask = readw(ndev->reg_ofs.ldb_mask);
 193                 clear_bit(db_cb->db_num * ndev->bits_per_vector, &mask);
 194                 writew(mask, ndev->reg_ofs.ldb_mask);
 195         }
 196 }
 197
 198 /**
 199  * ntb_register_db_callback() - register a callback for doorbell interrupt
 200  * @ndev: pointer to ntb_device instance
 201  * @idx: doorbell index to register callback, zero based
 202  * @data: pointer to be returned to caller with every callback
 203  * @func: callback function to register
 204  *
 205  * This function registers a callback function for the doorbell interrupt
 206  * on the primary side. The function will unmask the doorbell as well to
 207  * allow interrupt.
 208  *
 209  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 210  */
 211 int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
 212                              void *data, int (*func)(void *data, int db_num))
 213 {
 214         unsigned long mask;
 215
 216         if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) {
 217                 dev_warn(&ndev->pdev->dev, "Invalid Index.\n");
 218                 return -EINVAL;
 219         }
 220
 221         ndev->db_cb[idx].callback = func;
 222         ndev->db_cb[idx].data = data;
 223         ndev->db_cb[idx].ndev = ndev;
 224
 225         tasklet_init(&ndev->db_cb[idx].irq_work, ntb_irq_work,
 226                      (unsigned long) &ndev->db_cb[idx]);
 227
 228         /* unmask interrupt */
 229         mask = readw(ndev->reg_ofs.ldb_mask);
 230         clear_bit(idx * ndev->bits_per_vector, &mask);
 231         writew(mask, ndev->reg_ofs.ldb_mask);
 232
 233         return 0;
 234 }
 235
 236 /**
 237  * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
 238  * @ndev: pointer to ntb_device instance
 239  * @idx: doorbell index to register callback, zero based
 240  *
 241  * This function unregisters a callback function for the doorbell interrupt
 242  * on the primary side. The function will also mask the said doorbell.
 243  */
 244 void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
 245 {
 246         unsigned long mask;
 247
 248         if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback)
 249                 return;
 250
 251         mask = readw(ndev->reg_ofs.ldb_mask);
 252         set_bit(idx * ndev->bits_per_vector, &mask);
 253         writew(mask, ndev->reg_ofs.ldb_mask);
 254
 255         tasklet_disable(&ndev->db_cb[idx].irq_work);
 256
 257         ndev->db_cb[idx].callback = NULL;
 258 }
 259
 260 /**
 261  * ntb_find_transport() - find the transport pointer
 262  * @transport: pointer to pci device
 263  *
 264  * Given the pci device pointer, return the transport pointer passed in when
 265  * the transport attached when it was inited.
 266  *
 267  * RETURNS: pointer to transport.
 268  */
 269 void *ntb_find_transport(struct pci_dev *pdev)
 270 {
 271         struct ntb_device *ndev = pci_get_drvdata(pdev);
 272         return ndev->ntb_transport;
 273 }
 274
 275 /**
 276  * ntb_register_transport() - Register NTB transport with NTB HW driver
 277  * @transport: transport identifier
 278  *
 279  * This function allows a transport to reserve the hardware driver for
 280  * NTB usage.
 281  *
 282  * RETURNS: pointer to ntb_device, NULL on error.
 283  */
 284 struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport)
 285 {
 286         struct ntb_device *ndev = pci_get_drvdata(pdev);
 287
 288         if (ndev->ntb_transport)
 289                 return NULL;
 290
 291         ndev->ntb_transport = transport;
 292         return ndev;
 293 }
 294
 295 /**
 296  * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
 297  * @ndev - ntb_device of the transport to be freed
 298  *
 299  * This function unregisters the transport from the HW driver and performs any
 300  * necessary cleanups.
 301  */
 302 void ntb_unregister_transport(struct ntb_device *ndev)
 303 {
 304         int i;
 305
 306         if (!ndev->ntb_transport)
 307                 return;
 308
 309         for (i = 0; i < ndev->max_cbs; i++)
 310                 ntb_unregister_db_callback(ndev, i);
 311
 312         ntb_unregister_event_callback(ndev);
 313         ndev->ntb_transport = NULL;
 314 }
 315
 316 /**
 317  * ntb_write_local_spad() - write to the secondary scratchpad register
 318  * @ndev: pointer to ntb_device instance
 319  * @idx: index to the scratchpad register, 0 based
 320  * @val: the data value to put into the register
 321  *
 322  * This function allows writing of a 32bit value to the indexed scratchpad
 323  * register. This writes over the data mirrored to the local scratchpad register
 324  * by the remote system.
 325  *
 326  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 327  */
 328 int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
 329 {
 330         if (idx >= ndev->limits.max_spads)
 331                 return -EINVAL;
 332
 333         dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n",
 334                 val, idx);
 335         writel(val, ndev->reg_ofs.spad_read + idx * 4);
 336
 337         return 0;
 338 }
 339
 340 /**
 341  * ntb_read_local_spad() - read from the primary scratchpad register
 342  * @ndev: pointer to ntb_device instance
 343  * @idx: index to scratchpad register, 0 based
 344  * @val: pointer to 32bit integer for storing the register value
 345  *
 346  * This function allows reading of the 32bit scratchpad register on
 347  * the primary (internal) side.  This allows the local system to read data
 348  * written and mirrored to the scratchpad register by the remote system.
 349  *
 350  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 351  */
 352 int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
 353 {
 354         if (idx >= ndev->limits.max_spads)
 355                 return -EINVAL;
 356
 357         *val = readl(ndev->reg_ofs.spad_write + idx * 4);
 358         dev_dbg(&ndev->pdev->dev,
 359                 "Reading %x from local scratch pad index %d\n", *val, idx);
 360
 361         return 0;
 362 }
 363
 364 /**
 365  * ntb_write_remote_spad() - write to the secondary scratchpad register
 366  * @ndev: pointer to ntb_device instance
 367  * @idx: index to the scratchpad register, 0 based
 368  * @val: the data value to put into the register
 369  *
 370  * This function allows writing of a 32bit value to the indexed scratchpad
 371  * register. The register resides on the secondary (external) side.  This allows
 372  * the local system to write data to be mirrored to the remote systems
 373  * scratchpad register.
 374  *
 375  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 376  */
 377 int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
 378 {
 379         if (idx >= ndev->limits.max_spads)
 380                 return -EINVAL;
 381
 382         dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n",
 383                 val, idx);
 384         writel(val, ndev->reg_ofs.spad_write + idx * 4);
 385
 386         return 0;
 387 }
 388
 389 /**
 390  * ntb_read_remote_spad() - read from the primary scratchpad register
 391  * @ndev: pointer to ntb_device instance
 392  * @idx: index to scratchpad register, 0 based
 393  * @val: pointer to 32bit integer for storing the register value
 394  *
 395  * This function allows reading of the 32bit scratchpad register on
 396  * the primary (internal) side.  This alloows the local system to read the data
 397  * it wrote to be mirrored on the remote system.
 398  *
 399  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 400  */
 401 int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
 402 {
 403         if (idx >= ndev->limits.max_spads)
 404                 return -EINVAL;
 405
 406         *val = readl(ndev->reg_ofs.spad_read + idx * 4);
 407         dev_dbg(&ndev->pdev->dev,
 408                 "Reading %x from remote scratch pad index %d\n", *val, idx);
 409
 410         return 0;
 411 }
 412
 413 /**
 414  * ntb_get_mw_base() - get addr for the NTB memory window
 415  * @ndev: pointer to ntb_device instance
 416  * @mw: memory window number
 417  *
 418  * This function provides the base address of the memory window specified.
 419  *
 420  * RETURNS: address, or NULL on error.
 421  */
 422 resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw)
 423 {
 424         if (mw >= ntb_max_mw(ndev))
 425                 return 0;
 426
 427         return pci_resource_start(ndev->pdev, MW_TO_BAR(mw));
 428 }
 429
 430 /**
 431  * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
 432  * @ndev: pointer to ntb_device instance
 433  * @mw: memory window number
 434  *
 435  * This function provides the base virtual address of the memory window
 436  * specified.
 437  *
 438  * RETURNS: pointer to virtual address, or NULL on error.
 439  */
 440 void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw)
 441 {
 442         if (mw >= ntb_max_mw(ndev))
 443                 return NULL;
 444
 445         return ndev->mw[mw].vbase;
 446 }
 447
 448 /**
 449  * ntb_get_mw_size() - return size of NTB memory window
 450  * @ndev: pointer to ntb_device instance
 451  * @mw: memory window number
 452  *
 453  * This function provides the physical size of the memory window specified
 454  *
 455  * RETURNS: the size of the memory window or zero on error
 456  */
 457 u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)
 458 {
 459         if (mw >= ntb_max_mw(ndev))
 460                 return 0;
 461
 462         return ndev->mw[mw].bar_sz;
 463 }
 464
 465 /**
 466  * ntb_set_mw_addr - set the memory window address
 467  * @ndev: pointer to ntb_device instance
 468  * @mw: memory window number
 469  * @addr: base address for data
 470  *
 471  * This function sets the base physical address of the memory window.  This
 472  * memory address is where data from the remote system will be transfered into
 473  * or out of depending on how the transport is configured.
 474  */
 475 void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
 476 {
 477         if (mw >= ntb_max_mw(ndev))
 478                 return;
 479
 480         dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr,
 481                 MW_TO_BAR(mw));
 482
 483         ndev->mw[mw].phys_addr = addr;
 484
 485         switch (MW_TO_BAR(mw)) {
 486         case NTB_BAR_23:
 487                 writeq(addr, ndev->reg_ofs.bar2_xlat);
 488                 break;
 489         case NTB_BAR_45:
 490                 writeq(addr, ndev->reg_ofs.bar4_xlat);
 491                 break;
 492         }
 493 }
 494
 495 /**
 496  * ntb_ring_doorbell() - Set the doorbell on the secondary/external side
 497  * @ndev: pointer to ntb_device instance
 498  * @db: doorbell to ring
 499  *
 500  * This function allows triggering of a doorbell on the secondary/external
 501  * side that will initiate an interrupt on the remote host
 502  *
 503  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 504  */
 505 void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int db)
 506 {
 507         dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db);
 508
 509         if (ndev->hw_type == BWD_HW)
 510                 writeq((u64) 1 << db, ndev->reg_ofs.rdb);
 511         else
 512                 writew(((1 << ndev->bits_per_vector) - 1) <<
 513                        (db * ndev->bits_per_vector), ndev->reg_ofs.rdb);
 514 }
 515
 516 static void bwd_recover_link(struct ntb_device *ndev)
 517 {
 518         u32 status;
 519
 520         /* Driver resets the NTB ModPhy lanes - magic! */
 521         writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6);
 522         writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4);
 523         writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4);
 524         writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6);
 525
 526         /* Driver waits 100ms to allow the NTB ModPhy to settle */
 527         msleep(100);
 528
 529         /* Clear AER Errors, write to clear */
 530         status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET);
 531         dev_dbg(&ndev->pdev->dev, "ERRCORSTS = %x\n", status);
 532         status &= PCI_ERR_COR_REP_ROLL;
 533         writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET);
 534
 535         /* Clear unexpected electrical idle event in LTSSM, write to clear */
 536         status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
 537         dev_dbg(&ndev->pdev->dev, "LTSSMERRSTS0 = %x\n", status);
 538         status |= BWD_LTSSMERRSTS0_UNEXPECTEDEI;
 539         writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
 540
 541         /* Clear DeSkew Buffer error, write to clear */
 542         status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET);
 543         dev_dbg(&ndev->pdev->dev, "DESKEWSTS = %x\n", status);
 544         status |= BWD_DESKEWSTS_DBERR;
 545         writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET);
 546
 547         status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
 548         dev_dbg(&ndev->pdev->dev, "IBSTERRRCRVSTS0 = %x\n", status);
 549         status &= BWD_IBIST_ERR_OFLOW;
 550         writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
 551
 552         /* Releases the NTB state machine to allow the link to retrain */
 553         status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
 554         dev_dbg(&ndev->pdev->dev, "LTSSMSTATEJMP = %x\n", status);
 555         status &= ~BWD_LTSSMSTATEJMP_FORCEDETECT;
 556         writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
 557 }
 558
 559 static void ntb_link_event(struct ntb_device *ndev, int link_state)
 560 {
 561         unsigned int event;
 562
 563         if (ndev->link_status == link_state)
 564                 return;
 565
 566         if (link_state == NTB_LINK_UP) {
 567                 u16 status;
 568
 569                 dev_info(&ndev->pdev->dev, "Link Up\n");
 570                 ndev->link_status = NTB_LINK_UP;
 571                 event = NTB_EVENT_HW_LINK_UP;
 572
 573                 if (is_ntb_atom(ndev) ||
 574                     ndev->conn_type == NTB_CONN_TRANSPARENT)
 575                         status = readw(ndev->reg_ofs.lnk_stat);
 576                 else {
 577                         int rc = pci_read_config_word(ndev->pdev,
 578                                                       SNB_LINK_STATUS_OFFSET,
 579                                                       &status);
 580                         if (rc)
 581                                 return;
 582                 }
 583
 584                 ndev->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4;
 585                 ndev->link_speed = (status & NTB_LINK_SPEED_MASK);
 586                 dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n",
 587                          ndev->link_width, ndev->link_speed);
 588         } else {
 589                 dev_info(&ndev->pdev->dev, "Link Down\n");
 590                 ndev->link_status = NTB_LINK_DOWN;
 591                 event = NTB_EVENT_HW_LINK_DOWN;
 592                 /* Don't modify link width/speed, we need it in link recovery */
 593         }
 594
 595         /* notify the upper layer if we have an event change */
 596         if (ndev->event_cb)
 597                 ndev->event_cb(ndev->ntb_transport, event);
 598 }
 599
 600 static int ntb_link_status(struct ntb_device *ndev)
 601 {
 602         int link_state;
 603
 604         if (is_ntb_atom(ndev)) {
 605                 u32 ntb_cntl;
 606
 607                 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
 608                 if (ntb_cntl & BWD_CNTL_LINK_DOWN)
 609                         link_state = NTB_LINK_DOWN;
 610                 else
 611                         link_state = NTB_LINK_UP;
 612         } else {
 613                 u16 status;
 614                 int rc;
 615
 616                 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
 617                                           &status);
 618                 if (rc)
 619                         return rc;
 620
 621                 if (status & NTB_LINK_STATUS_ACTIVE)
 622                         link_state = NTB_LINK_UP;
 623                 else
 624                         link_state = NTB_LINK_DOWN;
 625         }
 626
 627         ntb_link_event(ndev, link_state);
 628
 629         return 0;
 630 }
 631
 632 static void bwd_link_recovery(struct work_struct *work)
 633 {
 634         struct ntb_device *ndev = container_of(work, struct ntb_device,
 635                                                lr_timer.work);
 636         u32 status32;
 637
 638         bwd_recover_link(ndev);
 639         /* There is a potential race between the 2 NTB devices recovering at the
 640          * same time.  If the times are the same, the link will not recover and
 641          * the driver will be stuck in this loop forever.  Add a random interval
 642          * to the recovery time to prevent this race.
 643          */
 644         msleep(BWD_LINK_RECOVERY_TIME + prandom_u32() % BWD_LINK_RECOVERY_TIME);
 645
 646         status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
 647         if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT)
 648                 goto retry;
 649
 650         status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
 651         if (status32 & BWD_IBIST_ERR_OFLOW)
 652                 goto retry;
 653
 654         status32 = readl(ndev->reg_ofs.lnk_cntl);
 655         if (!(status32 & BWD_CNTL_LINK_DOWN)) {
 656                 unsigned char speed, width;
 657                 u16 status16;
 658
 659                 status16 = readw(ndev->reg_ofs.lnk_stat);
 660                 width = (status16 & NTB_LINK_WIDTH_MASK) >> 4;
 661                 speed = (status16 & NTB_LINK_SPEED_MASK);
 662                 if (ndev->link_width != width || ndev->link_speed != speed)
 663                         goto retry;
 664         }
 665
 666         schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
 667         return;
 668
 669 retry:
 670         schedule_delayed_work(&ndev->lr_timer, NTB_HB_TIMEOUT);
 671 }
 672
 673 /* BWD doesn't have link status interrupt, poll on that platform */
 674 static void bwd_link_poll(struct work_struct *work)
 675 {
 676         struct ntb_device *ndev = container_of(work, struct ntb_device,
 677                                                hb_timer.work);
 678         unsigned long ts = jiffies;
 679
 680         /* If we haven't gotten an interrupt in a while, check the BWD link
 681          * status bit
 682          */
 683         if (ts > ndev->last_ts + NTB_HB_TIMEOUT) {
 684                 int rc = ntb_link_status(ndev);
 685                 if (rc)
 686                         dev_err(&ndev->pdev->dev,
 687                                 "Error determining link status\n");
 688
 689                 /* Check to see if a link error is the cause of the link down */
 690                 if (ndev->link_status == NTB_LINK_DOWN) {
 691                         u32 status32 = readl(ndev->reg_base +
 692                                              BWD_LTSSMSTATEJMP_OFFSET);
 693                         if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) {
 694                                 schedule_delayed_work(&ndev->lr_timer, 0);
 695                                 return;
 696                         }
 697                 }
 698         }
 699
 700         schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
 701 }
 702
 703 static int ntb_xeon_setup(struct ntb_device *ndev)
 704 {
 705         int rc;
 706         u8 val;
 707
 708         ndev->hw_type = SNB_HW;
 709
 710         rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &val);
 711         if (rc)
 712                 return rc;
 713
 714         if (val & SNB_PPD_DEV_TYPE)
 715                 ndev->dev_type = NTB_DEV_USD;
 716         else
 717                 ndev->dev_type = NTB_DEV_DSD;
 718
 719         switch (val & SNB_PPD_CONN_TYPE) {
 720         case NTB_CONN_B2B:
 721                 dev_info(&ndev->pdev->dev, "Conn Type = B2B\n");
 722                 ndev->conn_type = NTB_CONN_B2B;
 723                 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
 724                 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
 725                 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
 726                 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
 727                 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
 728                 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
 729
 730                 /* There is a Xeon hardware errata related to writes to
 731                  * SDOORBELL or B2BDOORBELL in conjunction with inbound access
 732                  * to NTB MMIO Space, which may hang the system.  To workaround
 733                  * this use the second memory window to access the interrupt and
 734                  * scratch pad registers on the remote system.
 735                  */
 736                 if (xeon_errata_workaround) {
 737                         if (!ndev->mw[1].bar_sz)
 738                                 return -EINVAL;
 739
 740                         ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
 741                         ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
 742                         ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
 743                                                    SNB_SPAD_OFFSET;
 744                         ndev->reg_ofs.rdb = ndev->mw[1].vbase +
 745                                             SNB_PDOORBELL_OFFSET;
 746
 747                         /* Set the Limit register to 4k, the minimum size, to
 748                          * prevent an illegal access
 749                          */
 750                         writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
 751                                SNB_PBAR4LMT_OFFSET);
 752                         /* HW errata on the Limit registers.  They can only be
 753                          * written when the base register is 4GB aligned and
 754                          * < 32bit.  This should already be the case based on
 755                          * the driver defaults, but write the Limit registers
 756                          * first just in case.
 757                          */
 758                 } else {
 759                         ndev->limits.max_mw = SNB_MAX_MW;
 760
 761                         /* HW Errata on bit 14 of b2bdoorbell register.  Writes
 762                          * will not be mirrored to the remote system.  Shrink
 763                          * the number of bits by one, since bit 14 is the last
 764                          * bit.
 765                          */
 766                         ndev->limits.max_db_bits = SNB_MAX_DB_BITS - 1;
 767                         ndev->reg_ofs.spad_write = ndev->reg_base +
 768                                                    SNB_B2B_SPAD_OFFSET;
 769                         ndev->reg_ofs.rdb = ndev->reg_base +
 770                                             SNB_B2B_DOORBELL_OFFSET;
 771
 772                         /* Disable the Limit register, just incase it is set to
 773                          * something silly
 774                          */
 775                         writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
 776                         /* HW errata on the Limit registers.  They can only be
 777                          * written when the base register is 4GB aligned and
 778                          * < 32bit.  This should already be the case based on
 779                          * the driver defaults, but write the Limit registers
 780                          * first just in case.
 781                          */
 782                 }
 783
 784                 /* The Xeon errata workaround requires setting SBAR Base
 785                  * addresses to known values, so that the PBAR XLAT can be
 786                  * pointed at SBAR0 of the remote system.
 787                  */
 788                 if (ndev->dev_type == NTB_DEV_USD) {
 789                         writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
 790                                SNB_PBAR2XLAT_OFFSET);
 791                         if (xeon_errata_workaround)
 792                                 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
 793                                        SNB_PBAR4XLAT_OFFSET);
 794                         else {
 795                                 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
 796                                        SNB_PBAR4XLAT_OFFSET);
 797                                 /* B2B_XLAT_OFFSET is a 64bit register, but can
 798                                  * only take 32bit writes
 799                                  */
 800                                 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
 801                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
 802                                 writel(SNB_MBAR01_DSD_ADDR >> 32,
 803                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
 804                         }
 805
 806                         writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
 807                                SNB_SBAR0BASE_OFFSET);
 808                         writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
 809                                SNB_SBAR2BASE_OFFSET);
 810                         writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
 811                                SNB_SBAR4BASE_OFFSET);
 812                 } else {
 813                         writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
 814                                SNB_PBAR2XLAT_OFFSET);
 815                         if (xeon_errata_workaround)
 816                                 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
 817                                        SNB_PBAR4XLAT_OFFSET);
 818                         else {
 819                                 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
 820                                        SNB_PBAR4XLAT_OFFSET);
 821                                 /* B2B_XLAT_OFFSET is a 64bit register, but can
 822                                  * only take 32bit writes
 823                                  */
 824                                 writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
 825                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
 826                                 writel(SNB_MBAR01_USD_ADDR >> 32,
 827                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
 828                         }
 829                         writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
 830                                SNB_SBAR0BASE_OFFSET);
 831                         writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
 832                                SNB_SBAR2BASE_OFFSET);
 833                         writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
 834                                SNB_SBAR4BASE_OFFSET);
 835                 }
 836                 break;
 837         case NTB_CONN_RP:
 838                 dev_info(&ndev->pdev->dev, "Conn Type = RP\n");
 839                 ndev->conn_type = NTB_CONN_RP;
 840
 841                 if (xeon_errata_workaround) {
 842                         dev_err(&ndev->pdev->dev,
 843                                 "NTB-RP disabled due to hardware errata.  To disregard this warning and potentially lock-up the system, add the parameter 'xeon_errata_workaround=0'.\n");
 844                         return -EINVAL;
 845                 }
 846
 847                 /* Scratch pads need to have exclusive access from the primary
 848                  * or secondary side.  Halve the num spads so that each side can
 849                  * have an equal amount.
 850                  */
 851                 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
 852                 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
 853                 /* Note: The SDOORBELL is the cause of the errata.  You REALLY
 854                  * don't want to touch it.
 855                  */
 856                 ndev->reg_ofs.rdb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
 857                 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
 858                 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
 859                 /* Offset the start of the spads to correspond to whether it is
 860                  * primary or secondary
 861                  */
 862                 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET +
 863                                            ndev->limits.max_spads * 4;
 864                 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
 865                 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
 866                 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
 867                 ndev->limits.max_mw = SNB_MAX_MW;
 868                 break;
 869         case NTB_CONN_TRANSPARENT:
 870                 dev_info(&ndev->pdev->dev, "Conn Type = TRANSPARENT\n");
 871                 ndev->conn_type = NTB_CONN_TRANSPARENT;
 872                 /* Scratch pads need to have exclusive access from the primary
 873                  * or secondary side.  Halve the num spads so that each side can
 874                  * have an equal amount.
 875                  */
 876                 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
 877                 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
 878                 ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
 879                 ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
 880                 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET;
 881                 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET;
 882                 /* Offset the start of the spads to correspond to whether it is
 883                  * primary or secondary
 884                  */
 885                 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET +
 886                                           ndev->limits.max_spads * 4;
 887                 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET;
 888                 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET;
 889
 890                 ndev->limits.max_mw = SNB_MAX_MW;
 891                 break;
 892         default:
 893                 /* Most likely caused by the remote NTB-RP device not being
 894                  * configured
 895                  */
 896                 dev_err(&ndev->pdev->dev, "Unknown PPD %x\n", val);
 897                 return -EINVAL;
 898         }
 899
 900         ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
 901         ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET;
 902         ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
 903
 904         ndev->limits.msix_cnt = SNB_MSIX_CNT;
 905         ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
 906
 907         return 0;
 908 }
 909
 910 static int ntb_bwd_setup(struct ntb_device *ndev)
 911 {
 912         int rc;
 913         u32 val;
 914
 915         ndev->hw_type = BWD_HW;
 916
 917         rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val);
 918         if (rc)
 919                 return rc;
 920
 921         switch ((val & BWD_PPD_CONN_TYPE) >> 8) {
 922         case NTB_CONN_B2B:
 923                 ndev->conn_type = NTB_CONN_B2B;
 924                 break;
 925         case NTB_CONN_RP:
 926         default:
 927                 dev_err(&ndev->pdev->dev, "Unsupported NTB configuration\n");
 928                 return -EINVAL;
 929         }
 930
 931         if (val & BWD_PPD_DEV_TYPE)
 932                 ndev->dev_type = NTB_DEV_DSD;
 933         else
 934                 ndev->dev_type = NTB_DEV_USD;
 935
 936         /* Initiate PCI-E link training */
 937         rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET,
 938                                     val | BWD_PPD_INIT_LINK);
 939         if (rc)
 940                 return rc;
 941
 942         ndev->reg_ofs.ldb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
 943         ndev->reg_ofs.ldb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
 944         ndev->reg_ofs.rdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
 945         ndev->reg_ofs.bar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
 946         ndev->reg_ofs.bar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
 947         ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
 948         ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
 949         ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
 950         ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
 951         ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
 952         ndev->limits.max_mw = BWD_MAX_MW;
 953         ndev->limits.max_spads = BWD_MAX_SPADS;
 954         ndev->limits.max_db_bits = BWD_MAX_DB_BITS;
 955         ndev->limits.msix_cnt = BWD_MSIX_CNT;
 956         ndev->bits_per_vector = BWD_DB_BITS_PER_VEC;
 957
 958         /* Since bwd doesn't have a link interrupt, setup a poll timer */
 959         INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll);
 960         INIT_DELAYED_WORK(&ndev->lr_timer, bwd_link_recovery);
 961         schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
 962
 963         return 0;
 964 }
 965
 966 static int ntb_device_setup(struct ntb_device *ndev)
 967 {
 968         int rc;
 969
 970         if (is_ntb_xeon(ndev))
 971                 rc = ntb_xeon_setup(ndev);
 972         else if (is_ntb_atom(ndev))
 973                 rc = ntb_bwd_setup(ndev);
 974         else
 975                 rc = -ENODEV;
 976
 977         if (rc)
 978                 return rc;
 979
 980         dev_info(&ndev->pdev->dev, "Device Type = %s\n",
 981                  ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
 982
 983         if (ndev->conn_type == NTB_CONN_B2B)
 984                 /* Enable Bus Master and Memory Space on the secondary side */
 985                 writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
 986                        ndev->reg_ofs.spci_cmd);
 987
 988         return 0;
 989 }
 990
 991 static void ntb_device_free(struct ntb_device *ndev)
 992 {
 993         if (is_ntb_atom(ndev)) {
 994                 cancel_delayed_work_sync(&ndev->hb_timer);
 995                 cancel_delayed_work_sync(&ndev->lr_timer);
 996         }
 997 }
 998
 999 static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
1000 {
1001         struct ntb_db_cb *db_cb = data;
1002         struct ntb_device *ndev = db_cb->ndev;
1003         unsigned long mask;
1004
1005         dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
1006                 db_cb->db_num);
1007
1008         mask = readw(ndev->reg_ofs.ldb_mask);
1009         set_bit(db_cb->db_num * ndev->bits_per_vector, &mask);
1010         writew(mask, ndev->reg_ofs.ldb_mask);
1011
1012         tasklet_schedule(&db_cb->irq_work);
1013
1014         /* No need to check for the specific HB irq, any interrupt means
1015          * we're connected.
1016          */
1017         ndev->last_ts = jiffies;
1018
1019         writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.ldb);
1020
1021         return IRQ_HANDLED;
1022 }
1023
1024 static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
1025 {
1026         struct ntb_db_cb *db_cb = data;
1027         struct ntb_device *ndev = db_cb->ndev;
1028         unsigned long mask;
1029
1030         dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
1031                 db_cb->db_num);
1032
1033         mask = readw(ndev->reg_ofs.ldb_mask);
1034         set_bit(db_cb->db_num * ndev->bits_per_vector, &mask);
1035         writew(mask, ndev->reg_ofs.ldb_mask);
1036
1037         tasklet_schedule(&db_cb->irq_work);
1038
1039         /* On Sandybridge, there are 16 bits in the interrupt register
1040          * but only 4 vectors.  So, 5 bits are assigned to the first 3
1041          * vectors, with the 4th having a single bit for link
1042          * interrupts.
1043          */
1044         writew(((1 << ndev->bits_per_vector) - 1) <<
1045                (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.ldb);
1046
1047         return IRQ_HANDLED;
1048 }
1049
1050 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
1051 static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
1052 {
1053         struct ntb_device *ndev = dev;
1054         int rc;
1055
1056         dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq);
1057
1058         rc = ntb_link_status(ndev);
1059         if (rc)
1060                 dev_err(&ndev->pdev->dev, "Error determining link status\n");
1061
1062         /* bit 15 is always the link bit */
1063         writew(1 << SNB_LINK_DB, ndev->reg_ofs.ldb);
1064
1065         return IRQ_HANDLED;
1066 }
1067
1068 static irqreturn_t ntb_interrupt(int irq, void *dev)
1069 {
1070         struct ntb_device *ndev = dev;
1071         unsigned int i = 0;
1072
1073         if (is_ntb_atom(ndev)) {
1074                 u64 ldb = readq(ndev->reg_ofs.ldb);
1075
1076                 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %Lx\n", irq, ldb);
1077
1078                 while (ldb) {
1079                         i = __ffs(ldb);
1080                         ldb &= ldb - 1;
1081                         bwd_callback_msix_irq(irq, &ndev->db_cb[i]);
1082                 }
1083         } else {
1084                 u16 ldb = readw(ndev->reg_ofs.ldb);
1085
1086                 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %x\n", irq, ldb);
1087
1088                 if (ldb & SNB_DB_HW_LINK) {
1089                         xeon_event_msix_irq(irq, dev);
1090                         ldb &= ~SNB_DB_HW_LINK;
1091                 }
1092
1093                 while (ldb) {
1094                         i = __ffs(ldb);
1095                         ldb &= ldb - 1;
1096                         xeon_callback_msix_irq(irq, &ndev->db_cb[i]);
1097                 }
1098         }
1099
1100         return IRQ_HANDLED;
1101 }
1102
1103 static int ntb_setup_snb_msix(struct ntb_device *ndev, int msix_entries)
1104 {
1105         struct pci_dev *pdev = ndev->pdev;
1106         struct msix_entry *msix;
1107         int rc, i;
1108
1109         if (msix_entries < ndev->limits.msix_cnt)
1110                 return -ENOSPC;
1111
1112         rc = pci_enable_msix_exact(pdev, ndev->msix_entries, msix_entries);
1113         if (rc < 0)
1114                 return rc;
1115
1116         for (i = 0; i < msix_entries; i++) {
1117                 msix = &ndev->msix_entries[i];
1118                 WARN_ON(!msix->vector);
1119
1120                 if (i == msix_entries - 1) {
1121                         rc = request_irq(msix->vector,
1122                                          xeon_event_msix_irq, 0,
1123                                          "ntb-event-msix", ndev);
1124                         if (rc)
1125                                 goto err;
1126                 } else {
1127                         rc = request_irq(msix->vector,
1128                                          xeon_callback_msix_irq, 0,
1129                                          "ntb-callback-msix",
1130                                          &ndev->db_cb[i]);
1131                         if (rc)
1132                                 goto err;
1133                 }
1134         }
1135
1136         ndev->num_msix = msix_entries;
1137         ndev->max_cbs = msix_entries - 1;
1138
1139         return 0;
1140
1141 err:
1142         while (--i >= 0) {
1143                 /* Code never reaches here for entry nr 'ndev->num_msix - 1' */
1144                 msix = &ndev->msix_entries[i];
1145                 free_irq(msix->vector, &ndev->db_cb[i]);
1146         }
1147
1148         pci_disable_msix(pdev);
1149         ndev->num_msix = 0;
1150
1151         return rc;
1152 }
1153
1154 static int ntb_setup_bwd_msix(struct ntb_device *ndev, int msix_entries)
1155 {
1156         struct pci_dev *pdev = ndev->pdev;
1157         struct msix_entry *msix;
1158         int rc, i;
1159
1160         msix_entries = pci_enable_msix_range(pdev, ndev->msix_entries,
1161                                              1, msix_entries);
1162         if (msix_entries < 0)
1163                 return msix_entries;
1164
1165         for (i = 0; i < msix_entries; i++) {
1166                 msix = &ndev->msix_entries[i];
1167                 WARN_ON(!msix->vector);
1168
1169                 rc = request_irq(msix->vector, bwd_callback_msix_irq, 0,
1170                                  "ntb-callback-msix", &ndev->db_cb[i]);
1171                 if (rc)
1172                         goto err;
1173         }
1174
1175         ndev->num_msix = msix_entries;
1176         ndev->max_cbs = msix_entries;
1177
1178         return 0;
1179
1180 err:
1181         while (--i >= 0)
1182                 free_irq(msix->vector, &ndev->db_cb[i]);
1183
1184         pci_disable_msix(pdev);
1185         ndev->num_msix = 0;
1186
1187         return rc;
1188 }
1189
1190 static int ntb_setup_msix(struct ntb_device *ndev)
1191 {
1192         struct pci_dev *pdev = ndev->pdev;
1193         int msix_entries;
1194         int rc, i;
1195
1196         msix_entries = pci_msix_vec_count(pdev);
1197         if (msix_entries < 0) {
1198                 rc = msix_entries;
1199                 goto err;
1200         } else if (msix_entries > ndev->limits.msix_cnt) {
1201                 rc = -EINVAL;
1202                 goto err;
1203         }
1204
1205         ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries,
1206                                      GFP_KERNEL);
1207         if (!ndev->msix_entries) {
1208                 rc = -ENOMEM;
1209                 goto err;
1210         }
1211
1212         for (i = 0; i < msix_entries; i++)
1213                 ndev->msix_entries[i].entry = i;
1214
1215         if (is_ntb_atom(ndev))
1216                 rc = ntb_setup_bwd_msix(ndev, msix_entries);
1217         else
1218                 rc = ntb_setup_snb_msix(ndev, msix_entries);
1219         if (rc)
1220                 goto err1;
1221
1222         return 0;
1223
1224 err1:
1225         kfree(ndev->msix_entries);
1226 err:
1227         dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n");
1228         return rc;
1229 }
1230
1231 static int ntb_setup_msi(struct ntb_device *ndev)
1232 {
1233         struct pci_dev *pdev = ndev->pdev;
1234         int rc;
1235
1236         rc = pci_enable_msi(pdev);
1237         if (rc)
1238                 return rc;
1239
1240         rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev);
1241         if (rc) {
1242                 pci_disable_msi(pdev);
1243                 dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
1244                 return rc;
1245         }
1246
1247         return 0;
1248 }
1249
1250 static int ntb_setup_intx(struct ntb_device *ndev)
1251 {
1252         struct pci_dev *pdev = ndev->pdev;
1253         int rc;
1254
1255         pci_msi_off(pdev);
1256
1257         /* Verify intx is enabled */
1258         pci_intx(pdev, 1);
1259
1260         rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx",
1261                          ndev);
1262         if (rc)
1263                 return rc;
1264
1265         return 0;
1266 }
1267
1268 static int ntb_setup_interrupts(struct ntb_device *ndev)
1269 {
1270         int rc;
1271
1272         /* On BWD, disable all interrupts.  On SNB, disable all but Link
1273          * Interrupt.  The rest will be unmasked as callbacks are registered.
1274          */
1275         if (is_ntb_atom(ndev))
1276                 writeq(~0, ndev->reg_ofs.ldb_mask);
1277         else {
1278                 u16 var = 1 << SNB_LINK_DB;
1279                 writew(~var, ndev->reg_ofs.ldb_mask);
1280         }
1281
1282         rc = ntb_setup_msix(ndev);
1283         if (!rc)
1284                 goto done;
1285
1286         ndev->bits_per_vector = 1;
1287         ndev->max_cbs = ndev->limits.max_db_bits;
1288
1289         rc = ntb_setup_msi(ndev);
1290         if (!rc)
1291                 goto done;
1292
1293         rc = ntb_setup_intx(ndev);
1294         if (rc) {
1295                 dev_err(&ndev->pdev->dev, "no usable interrupts\n");
1296                 return rc;
1297         }
1298
1299 done:
1300         return 0;
1301 }
1302
1303 static void ntb_free_interrupts(struct ntb_device *ndev)
1304 {
1305         struct pci_dev *pdev = ndev->pdev;
1306
1307         /* mask interrupts */
1308         if (is_ntb_atom(ndev))
1309                 writeq(~0, ndev->reg_ofs.ldb_mask);
1310         else
1311                 writew(~0, ndev->reg_ofs.ldb_mask);
1312
1313         if (ndev->num_msix) {
1314                 struct msix_entry *msix;
1315                 u32 i;
1316
1317                 for (i = 0; i < ndev->num_msix; i++) {
1318                         msix = &ndev->msix_entries[i];
1319                         if (is_ntb_xeon(ndev) && i == ndev->num_msix - 1)
1320                                 free_irq(msix->vector, ndev);
1321                         else
1322                                 free_irq(msix->vector, &ndev->db_cb[i]);
1323                 }
1324                 pci_disable_msix(pdev);
1325                 kfree(ndev->msix_entries);
1326         } else {
1327                 free_irq(pdev->irq, ndev);
1328
1329                 if (pci_dev_msi_enabled(pdev))
1330                         pci_disable_msi(pdev);
1331         }
1332 }
1333
1334 static int ntb_create_callbacks(struct ntb_device *ndev)
1335 {
1336         int i;
1337
1338         /* Chicken-egg issue.  We won't know how many callbacks are necessary
1339          * until we see how many MSI-X vectors we get, but these pointers need
1340          * to be passed into the MSI-X register function.  So, we allocate the
1341          * max, knowing that they might not all be used, to work around this.
1342          */
1343         ndev->db_cb = kcalloc(ndev->limits.max_db_bits,
1344                               sizeof(struct ntb_db_cb),
1345                               GFP_KERNEL);
1346         if (!ndev->db_cb)
1347                 return -ENOMEM;
1348
1349         for (i = 0; i < ndev->limits.max_db_bits; i++) {
1350                 ndev->db_cb[i].db_num = i;
1351                 ndev->db_cb[i].ndev = ndev;
1352         }
1353
1354         return 0;
1355 }
1356
1357 static void ntb_free_callbacks(struct ntb_device *ndev)
1358 {
1359         int i;
1360
1361         for (i = 0; i < ndev->limits.max_db_bits; i++)
1362                 ntb_unregister_db_callback(ndev, i);
1363
1364         kfree(ndev->db_cb);
1365 }
1366
1367 static ssize_t ntb_debugfs_read(struct file *filp, char __user *ubuf,
1368                                 size_t count, loff_t *offp)
1369 {
1370         struct ntb_device *ndev;
1371         char *buf;
1372         ssize_t ret, offset, out_count;
1373
1374         out_count = 500;
1375
1376         buf = kmalloc(out_count, GFP_KERNEL);
1377         if (!buf)
1378                 return -ENOMEM;
1379
1380         ndev = filp->private_data;
1381         offset = 0;
1382         offset += snprintf(buf + offset, out_count - offset,
1383                            "NTB Device Information:\n");
1384         offset += snprintf(buf + offset, out_count - offset,
1385                            "Connection Type - \t\t%s\n",
1386                            ndev->conn_type == NTB_CONN_TRANSPARENT ?
1387                            "Transparent" : (ndev->conn_type == NTB_CONN_B2B) ?
1388                            "Back to back" : "Root Port");
1389         offset += snprintf(buf + offset, out_count - offset,
1390                            "Device Type - \t\t\t%s\n",
1391                            ndev->dev_type == NTB_DEV_USD ?
1392                            "DSD/USP" : "USD/DSP");
1393         offset += snprintf(buf + offset, out_count - offset,
1394                            "Max Number of Callbacks - \t%u\n",
1395                            ntb_max_cbs(ndev));
1396         offset += snprintf(buf + offset, out_count - offset,
1397                            "Link Status - \t\t\t%s\n",
1398                            ntb_hw_link_status(ndev) ? "Up" : "Down");
1399         if (ntb_hw_link_status(ndev)) {
1400                 offset += snprintf(buf + offset, out_count - offset,
1401                                    "Link Speed - \t\t\tPCI-E Gen %u\n",
1402                                    ndev->link_speed);
1403                 offset += snprintf(buf + offset, out_count - offset,
1404                                    "Link Width - \t\t\tx%u\n",
1405                                    ndev->link_width);
1406         }
1407
1408         if (is_ntb_xeon(ndev)) {
1409                 u32 status32;
1410                 u16 status16;
1411                 int rc;
1412
1413                 offset += snprintf(buf + offset, out_count - offset,
1414                                    "\nNTB Device Statistics:\n");
1415                 offset += snprintf(buf + offset, out_count - offset,
1416                                    "Upstream Memory Miss - \t%u\n",
1417                                    readw(ndev->reg_base +
1418                                          SNB_USMEMMISS_OFFSET));
1419
1420                 offset += snprintf(buf + offset, out_count - offset,
1421                                    "\nNTB Hardware Errors:\n");
1422
1423                 rc = pci_read_config_word(ndev->pdev, SNB_DEVSTS_OFFSET,
1424                                           &status16);
1425                 if (!rc)
1426                         offset += snprintf(buf + offset, out_count - offset,
1427                                            "DEVSTS - \t%#06x\n", status16);
1428
1429                 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
1430                                           &status16);
1431                 if (!rc)
1432                         offset += snprintf(buf + offset, out_count - offset,
1433                                            "LNKSTS - \t%#06x\n", status16);
1434
1435                 rc = pci_read_config_dword(ndev->pdev, SNB_UNCERRSTS_OFFSET,
1436                                            &status32);
1437                 if (!rc)
1438                         offset += snprintf(buf + offset, out_count - offset,
1439                                            "UNCERRSTS - \t%#010x\n", status32);
1440
1441                 rc = pci_read_config_dword(ndev->pdev, SNB_CORERRSTS_OFFSET,
1442                                            &status32);
1443                 if (!rc)
1444                         offset += snprintf(buf + offset, out_count - offset,
1445                                            "CORERRSTS - \t%#010x\n", status32);
1446         }
1447
1448         if (offset > out_count)
1449                 offset = out_count;
1450
1451         ret = simple_read_from_buffer(ubuf, count, offp, buf, offset);
1452         kfree(buf);
1453         return ret;
1454 }
1455
1456 static const struct file_operations ntb_debugfs_info = {
1457         .owner = THIS_MODULE,
1458         .open = simple_open,
1459         .read = ntb_debugfs_read,
1460 };
1461
1462 static void ntb_setup_debugfs(struct ntb_device *ndev)
1463 {
1464         if (!debugfs_initialized())
1465                 return;
1466
1467         if (!debugfs_dir)
1468                 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
1469
1470         ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev),
1471                                                debugfs_dir);
1472         if (ndev->debugfs_dir)
1473                 ndev->debugfs_info = debugfs_create_file("info", S_IRUSR,
1474                                                          ndev->debugfs_dir,
1475                                                          ndev,
1476                                                          &ntb_debugfs_info);
1477 }
1478
1479 static void ntb_free_debugfs(struct ntb_device *ndev)
1480 {
1481         debugfs_remove_recursive(ndev->debugfs_dir);
1482
1483         if (debugfs_dir && simple_empty(debugfs_dir)) {
1484                 debugfs_remove_recursive(debugfs_dir);
1485                 debugfs_dir = NULL;
1486         }
1487 }
1488
1489 static void ntb_hw_link_up(struct ntb_device *ndev)
1490 {
1491         if (ndev->conn_type == NTB_CONN_TRANSPARENT)
1492                 ntb_link_event(ndev, NTB_LINK_UP);
1493         else {
1494                 u32 ntb_cntl;
1495
1496                 /* Let's bring the NTB link up */
1497                 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1498                 ntb_cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK);
1499                 ntb_cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP;
1500                 ntb_cntl |= NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP;
1501                 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1502         }
1503 }
1504
1505 static void ntb_hw_link_down(struct ntb_device *ndev)
1506 {
1507         u32 ntb_cntl;
1508
1509         if (ndev->conn_type == NTB_CONN_TRANSPARENT) {
1510                 ntb_link_event(ndev, NTB_LINK_DOWN);
1511                 return;
1512         }
1513
1514         /* Bring NTB link down */
1515         ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1516         ntb_cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP);
1517         ntb_cntl &= ~(NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP);
1518         ntb_cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK;
1519         writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1520 }
1521
1522 static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1523 {
1524         struct ntb_device *ndev;
1525         int rc, i;
1526
1527         ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL);
1528         if (!ndev)
1529                 return -ENOMEM;
1530
1531         ndev->pdev = pdev;
1532         ndev->link_status = NTB_LINK_DOWN;
1533         pci_set_drvdata(pdev, ndev);
1534         ntb_setup_debugfs(ndev);
1535
1536         rc = pci_enable_device(pdev);
1537         if (rc)
1538                 goto err;
1539
1540         pci_set_master(ndev->pdev);
1541
1542         rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
1543         if (rc)
1544                 goto err1;
1545
1546         ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1547         if (!ndev->reg_base) {
1548                 dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
1549                 rc = -EIO;
1550                 goto err2;
1551         }
1552
1553         for (i = 0; i < NTB_MAX_NUM_MW; i++) {
1554                 ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
1555                 ndev->mw[i].vbase =
1556                     ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
1557                                ndev->mw[i].bar_sz);
1558                 dev_info(&pdev->dev, "MW %d size %llu\n", i,
1559                          (unsigned long long) ndev->mw[i].bar_sz);
1560                 if (!ndev->mw[i].vbase) {
1561                         dev_warn(&pdev->dev, "Cannot remap BAR %d\n",
1562                                  MW_TO_BAR(i));
1563                         rc = -EIO;
1564                         goto err3;
1565                 }
1566         }
1567
1568         rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1569         if (rc) {
1570                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1571                 if (rc)
1572                         goto err3;
1573
1574                 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
1575         }
1576
1577         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1578         if (rc) {
1579                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1580                 if (rc)
1581                         goto err3;
1582
1583                 dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
1584         }
1585
1586         rc = ntb_device_setup(ndev);
1587         if (rc)
1588                 goto err3;
1589
1590         rc = ntb_create_callbacks(ndev);
1591         if (rc)
1592                 goto err4;
1593
1594         rc = ntb_setup_interrupts(ndev);
1595         if (rc)
1596                 goto err5;
1597
1598         /* The scratchpad registers keep the values between rmmod/insmod,
1599          * blast them now
1600          */
1601         for (i = 0; i < ndev->limits.max_spads; i++) {
1602                 ntb_write_local_spad(ndev, i, 0);
1603                 ntb_write_remote_spad(ndev, i, 0);
1604         }
1605
1606         rc = ntb_transport_init(pdev);
1607         if (rc)
1608                 goto err6;
1609
1610         ntb_hw_link_up(ndev);
1611
1612         return 0;
1613
1614 err6:
1615         ntb_free_interrupts(ndev);
1616 err5:
1617         ntb_free_callbacks(ndev);
1618 err4:
1619         ntb_device_free(ndev);
1620 err3:
1621         for (i--; i >= 0; i--)
1622                 iounmap(ndev->mw[i].vbase);
1623         iounmap(ndev->reg_base);
1624 err2:
1625         pci_release_selected_regions(pdev, NTB_BAR_MASK);
1626 err1:
1627         pci_disable_device(pdev);
1628 err:
1629         ntb_free_debugfs(ndev);
1630         kfree(ndev);
1631
1632         dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME);
1633         return rc;
1634 }
1635
1636 static void ntb_pci_remove(struct pci_dev *pdev)
1637 {
1638         struct ntb_device *ndev = pci_get_drvdata(pdev);
1639         int i;
1640
1641         ntb_hw_link_down(ndev);
1642
1643         ntb_transport_free(ndev->ntb_transport);
1644
1645         ntb_free_interrupts(ndev);
1646         ntb_free_callbacks(ndev);
1647         ntb_device_free(ndev);
1648
1649         for (i = 0; i < NTB_MAX_NUM_MW; i++)
1650                 iounmap(ndev->mw[i].vbase);
1651
1652         iounmap(ndev->reg_base);
1653         pci_release_selected_regions(pdev, NTB_BAR_MASK);
1654         pci_disable_device(pdev);
1655         ntb_free_debugfs(ndev);
1656         kfree(ndev);
1657 }
1658
1659 static struct pci_driver ntb_pci_driver = {
1660         .name = KBUILD_MODNAME,
1661         .id_table = ntb_pci_tbl,
1662         .probe = ntb_pci_probe,
1663         .remove = ntb_pci_remove,
1664 };
1665
1666 module_pci_driver(ntb_pci_driver);