drivers/pci/host/pci-dra7xx.c

   1 /*
   2  * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
   3  *
   4  * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Kishon Vijay Abraham I <kishon@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/pci.h>
  21 #include <linux/phy/phy.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/resource.h>
  25 #include <linux/types.h>
  26
  27 #include "pcie-designware.h"
  28
  29 /* PCIe controller wrapper DRA7XX configuration registers */
  30
  31 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN             0x0024
  32 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN         0x0028
  33 #define ERR_SYS                                         BIT(0)
  34 #define ERR_FATAL                                       BIT(1)
  35 #define ERR_NONFATAL                                    BIT(2)
  36 #define ERR_COR                                         BIT(3)
  37 #define ERR_AXI                                         BIT(4)
  38 #define ERR_ECRC                                        BIT(5)
  39 #define PME_TURN_OFF                                    BIT(8)
  40 #define PME_TO_ACK                                      BIT(9)
  41 #define PM_PME                                          BIT(10)
  42 #define LINK_REQ_RST                                    BIT(11)
  43 #define LINK_UP_EVT                                     BIT(12)
  44 #define CFG_BME_EVT                                     BIT(13)
  45 #define CFG_MSE_EVT                                     BIT(14)
  46 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
  47                         ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
  48                         LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
  49
  50 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI              0x0034
  51 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI          0x0038
  52 #define INTA                                            BIT(0)
  53 #define INTB                                            BIT(1)
  54 #define INTC                                            BIT(2)
  55 #define INTD                                            BIT(3)
  56 #define MSI                                             BIT(4)
  57 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
  58
  59 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD                 0x0104
  60 #define LTSSM_EN                                        0x1
  61
  62 #define PCIECTRL_DRA7XX_CONF_PHY_CS                     0x010C
  63 #define LINK_UP                                         BIT(16)
  64 #define DRA7XX_CPU_TO_BUS_ADDR                          0x0FFFFFFF
  65
  66 struct dra7xx_pcie {
  67         struct pcie_port        pp;
  68         void __iomem            *base;          /* DT ti_conf */
  69         int                     phy_count;      /* DT phy-names count */
  70         struct phy              **phy;
  71 };
  72
  73 #define to_dra7xx_pcie(x)       container_of((x), struct dra7xx_pcie, pp)
  74
  75 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
  76 {
  77         return readl(pcie->base + offset);
  78 }
  79
  80 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
  81                                       u32 value)
  82 {
  83         writel(value, pcie->base + offset);
  84 }
  85
  86 static int dra7xx_pcie_link_up(struct pcie_port *pp)
  87 {
  88         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
  89         u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
  90
  91         return !!(reg & LINK_UP);
  92 }
  93
  94 static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
  95 {
  96         struct pcie_port *pp = &dra7xx->pp;
  97         struct device *dev = pp->dev;
  98         u32 reg;
  99
 100         if (dw_pcie_link_up(pp)) {
 101                 dev_err(dev, "link is already up\n");
 102                 return 0;
 103         }
 104
 105         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
 106         reg |= LTSSM_EN;
 107         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 108
 109         return dw_pcie_wait_for_link(pp);
 110 }
 111
 112 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
 113 {
 114         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
 115                            ~INTERRUPTS);
 116         dra7xx_pcie_writel(dra7xx,
 117                            PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
 118         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
 119                            ~LEG_EP_INTERRUPTS & ~MSI);
 120
 121         if (IS_ENABLED(CONFIG_PCI_MSI))
 122                 dra7xx_pcie_writel(dra7xx,
 123                                    PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
 124         else
 125                 dra7xx_pcie_writel(dra7xx,
 126                                    PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
 127                                    LEG_EP_INTERRUPTS);
 128 }
 129
 130 static void dra7xx_pcie_host_init(struct pcie_port *pp)
 131 {
 132         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
 133
 134         pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
 135         pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
 136         pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
 137         pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
 138
 139         dw_pcie_setup_rc(pp);
 140
 141         dra7xx_pcie_establish_link(dra7xx);
 142         if (IS_ENABLED(CONFIG_PCI_MSI))
 143                 dw_pcie_msi_init(pp);
 144         dra7xx_pcie_enable_interrupts(dra7xx);
 145 }
 146
 147 static struct pcie_host_ops dra7xx_pcie_host_ops = {
 148         .link_up = dra7xx_pcie_link_up,
 149         .host_init = dra7xx_pcie_host_init,
 150 };
 151
 152 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 153                                 irq_hw_number_t hwirq)
 154 {
 155         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 156         irq_set_chip_data(irq, domain->host_data);
 157
 158         return 0;
 159 }
 160
 161 static const struct irq_domain_ops intx_domain_ops = {
 162         .map = dra7xx_pcie_intx_map,
 163 };
 164
 165 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
 166 {
 167         struct device *dev = pp->dev;
 168         struct device_node *node = dev->of_node;
 169         struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);
 170
 171         if (!pcie_intc_node) {
 172                 dev_err(dev, "No PCIe Intc node found\n");
 173                 return -ENODEV;
 174         }
 175
 176         pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
 177                                                &intx_domain_ops, pp);
 178         if (!pp->irq_domain) {
 179                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 180                 return -ENODEV;
 181         }
 182
 183         return 0;
 184 }
 185
 186 static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
 187 {
 188         struct dra7xx_pcie *dra7xx = arg;
 189         struct pcie_port *pp = &dra7xx->pp;
 190         u32 reg;
 191
 192         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
 193
 194         switch (reg) {
 195         case MSI:
 196                 dw_handle_msi_irq(pp);
 197                 break;
 198         case INTA:
 199         case INTB:
 200         case INTC:
 201         case INTD:
 202                 generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
 203                 break;
 204         }
 205
 206         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
 207
 208         return IRQ_HANDLED;
 209 }
 210
 211
 212 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
 213 {
 214         struct dra7xx_pcie *dra7xx = arg;
 215         struct device *dev = dra7xx->pp.dev;
 216         u32 reg;
 217
 218         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
 219
 220         if (reg & ERR_SYS)
 221                 dev_dbg(dev, "System Error\n");
 222
 223         if (reg & ERR_FATAL)
 224                 dev_dbg(dev, "Fatal Error\n");
 225
 226         if (reg & ERR_NONFATAL)
 227                 dev_dbg(dev, "Non Fatal Error\n");
 228
 229         if (reg & ERR_COR)
 230                 dev_dbg(dev, "Correctable Error\n");
 231
 232         if (reg & ERR_AXI)
 233                 dev_dbg(dev, "AXI tag lookup fatal Error\n");
 234
 235         if (reg & ERR_ECRC)
 236                 dev_dbg(dev, "ECRC Error\n");
 237
 238         if (reg & PME_TURN_OFF)
 239                 dev_dbg(dev,
 240                         "Power Management Event Turn-Off message received\n");
 241
 242         if (reg & PME_TO_ACK)
 243                 dev_dbg(dev,
 244                         "Power Management Turn-Off Ack message received\n");
 245
 246         if (reg & PM_PME)
 247                 dev_dbg(dev, "PM Power Management Event message received\n");
 248
 249         if (reg & LINK_REQ_RST)
 250                 dev_dbg(dev, "Link Request Reset\n");
 251
 252         if (reg & LINK_UP_EVT)
 253                 dev_dbg(dev, "Link-up state change\n");
 254
 255         if (reg & CFG_BME_EVT)
 256                 dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
 257
 258         if (reg & CFG_MSE_EVT)
 259                 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
 260
 261         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
 262
 263         return IRQ_HANDLED;
 264 }
 265
 266 static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
 267                                        struct platform_device *pdev)
 268 {
 269         int ret;
 270         struct pcie_port *pp = &dra7xx->pp;
 271         struct device *dev = pp->dev;
 272         struct resource *res;
 273
 274         pp->irq = platform_get_irq(pdev, 1);
 275         if (pp->irq < 0) {
 276                 dev_err(dev, "missing IRQ resource\n");
 277                 return -EINVAL;
 278         }
 279
 280         ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
 281                                IRQF_SHARED | IRQF_NO_THREAD,
 282                                "dra7-pcie-msi", dra7xx);
 283         if (ret) {
 284                 dev_err(dev, "failed to request irq\n");
 285                 return ret;
 286         }
 287
 288         if (!IS_ENABLED(CONFIG_PCI_MSI)) {
 289                 ret = dra7xx_pcie_init_irq_domain(pp);
 290                 if (ret < 0)
 291                         return ret;
 292         }
 293
 294         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
 295         pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
 296         if (!pp->dbi_base)
 297                 return -ENOMEM;
 298
 299         ret = dw_pcie_host_init(pp);
 300         if (ret) {
 301                 dev_err(dev, "failed to initialize host\n");
 302                 return ret;
 303         }
 304
 305         return 0;
 306 }
 307
 308 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 309 {
 310         u32 reg;
 311         int ret;
 312         int irq;
 313         int i;
 314         int phy_count;
 315         struct phy **phy;
 316         void __iomem *base;
 317         struct resource *res;
 318         struct dra7xx_pcie *dra7xx;
 319         struct pcie_port *pp;
 320         struct device *dev = &pdev->dev;
 321         struct device_node *np = dev->of_node;
 322         char name[10];
 323         int gpio_sel;
 324         enum of_gpio_flags flags;
 325         unsigned long gpio_flags;
 326
 327         dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
 328         if (!dra7xx)
 329                 return -ENOMEM;
 330
 331         pp = &dra7xx->pp;
 332         pp->dev = dev;
 333         pp->ops = &dra7xx_pcie_host_ops;
 334
 335         irq = platform_get_irq(pdev, 0);
 336         if (irq < 0) {
 337                 dev_err(dev, "missing IRQ resource\n");
 338                 return -EINVAL;
 339         }
 340
 341         ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
 342                                IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
 343         if (ret) {
 344                 dev_err(dev, "failed to request irq\n");
 345                 return ret;
 346         }
 347
 348         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
 349         base = devm_ioremap_nocache(dev, res->start, resource_size(res));
 350         if (!base)
 351                 return -ENOMEM;
 352
 353         phy_count = of_property_count_strings(np, "phy-names");
 354         if (phy_count < 0) {
 355                 dev_err(dev, "unable to find the strings\n");
 356                 return phy_count;
 357         }
 358
 359         phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
 360         if (!phy)
 361                 return -ENOMEM;
 362
 363         for (i = 0; i < phy_count; i++) {
 364                 snprintf(name, sizeof(name), "pcie-phy%d", i);
 365                 phy[i] = devm_phy_get(dev, name);
 366                 if (IS_ERR(phy[i]))
 367                         return PTR_ERR(phy[i]);
 368
 369                 ret = phy_init(phy[i]);
 370                 if (ret < 0)
 371                         goto err_phy;
 372
 373                 ret = phy_power_on(phy[i]);
 374                 if (ret < 0) {
 375                         phy_exit(phy[i]);
 376                         goto err_phy;
 377                 }
 378         }
 379
 380         dra7xx->base = base;
 381         dra7xx->phy = phy;
 382         dra7xx->phy_count = phy_count;
 383
 384         pm_runtime_enable(dev);
 385         ret = pm_runtime_get_sync(dev);
 386         if (ret < 0) {
 387                 dev_err(dev, "pm_runtime_get_sync failed\n");
 388                 goto err_get_sync;
 389         }
 390
 391         gpio_sel = of_get_gpio_flags(dev->of_node, 0, &flags);
 392         if (gpio_is_valid(gpio_sel)) {
 393                 gpio_flags = (flags & OF_GPIO_ACTIVE_LOW) ?
 394                                 GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
 395                 ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags,
 396                                             "pcie_reset");
 397                 if (ret) {
 398                         dev_err(dev, "gpio%d request failed, ret %d\n",
 399                                 gpio_sel, ret);
 400                         goto err_gpio;
 401                 }
 402         } else if (gpio_sel == -EPROBE_DEFER) {
 403                 ret = -EPROBE_DEFER;
 404                 goto err_gpio;
 405         }
 406
 407         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
 408         reg &= ~LTSSM_EN;
 409         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 410
 411         ret = dra7xx_add_pcie_port(dra7xx, pdev);
 412         if (ret < 0)
 413                 goto err_gpio;
 414
 415         platform_set_drvdata(pdev, dra7xx);
 416         return 0;
 417
 418 err_gpio:
 419         pm_runtime_put(dev);
 420
 421 err_get_sync:
 422         pm_runtime_disable(dev);
 423
 424 err_phy:
 425         while (--i >= 0) {
 426                 phy_power_off(phy[i]);
 427                 phy_exit(phy[i]);
 428         }
 429
 430         return ret;
 431 }
 432
 433 #ifdef CONFIG_PM_SLEEP
 434 static int dra7xx_pcie_suspend(struct device *dev)
 435 {
 436         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 437         struct pcie_port *pp = &dra7xx->pp;
 438         u32 val;
 439
 440         /* clear MSE */
 441         val = dw_pcie_readl_rc(pp, PCI_COMMAND);
 442         val &= ~PCI_COMMAND_MEMORY;
 443         dw_pcie_writel_rc(pp, PCI_COMMAND, val);
 444
 445         return 0;
 446 }
 447
 448 static int dra7xx_pcie_resume(struct device *dev)
 449 {
 450         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 451         struct pcie_port *pp = &dra7xx->pp;
 452         u32 val;
 453
 454         /* set MSE */
 455         val = dw_pcie_readl_rc(pp, PCI_COMMAND);
 456         val |= PCI_COMMAND_MEMORY;
 457         dw_pcie_writel_rc(pp, PCI_COMMAND, val);
 458
 459         return 0;
 460 }
 461
 462 static int dra7xx_pcie_suspend_noirq(struct device *dev)
 463 {
 464         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 465         int count = dra7xx->phy_count;
 466
 467         while (count--) {
 468                 phy_power_off(dra7xx->phy[count]);
 469                 phy_exit(dra7xx->phy[count]);
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int dra7xx_pcie_resume_noirq(struct device *dev)
 476 {
 477         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 478         int phy_count = dra7xx->phy_count;
 479         int ret;
 480         int i;
 481
 482         for (i = 0; i < phy_count; i++) {
 483                 ret = phy_init(dra7xx->phy[i]);
 484                 if (ret < 0)
 485                         goto err_phy;
 486
 487                 ret = phy_power_on(dra7xx->phy[i]);
 488                 if (ret < 0) {
 489                         phy_exit(dra7xx->phy[i]);
 490                         goto err_phy;
 491                 }
 492         }
 493
 494         return 0;
 495
 496 err_phy:
 497         while (--i >= 0) {
 498                 phy_power_off(dra7xx->phy[i]);
 499                 phy_exit(dra7xx->phy[i]);
 500         }
 501
 502         return ret;
 503 }
 504 #endif
 505
 506 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
 507         SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
 508         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
 509                                       dra7xx_pcie_resume_noirq)
 510 };
 511
 512 static const struct of_device_id of_dra7xx_pcie_match[] = {
 513         { .compatible = "ti,dra7-pcie", },
 514         {},
 515 };
 516
 517 static struct platform_driver dra7xx_pcie_driver = {
 518         .driver = {
 519                 .name   = "dra7-pcie",
 520                 .of_match_table = of_dra7xx_pcie_match,
 521                 .suppress_bind_attrs = true,
 522                 .pm     = &dra7xx_pcie_pm_ops,
 523         },
 524 };
 525 builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);