2 * PCIe host controller driver for Freescale i.MX6 SoCs
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
7 * Author: Sean Cross <xobs@kosagi.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/module.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_device.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/resource.h>
27 #include <linux/signal.h>
28 #include <linux/types.h>
29 #include <linux/interrupt.h>
31 #include "pcie-designware.h"
33 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
35 enum imx6_pcie_variants {
43 bool gpio_active_high;
46 struct clk *pcie_inbound_axi;
49 struct regmap *iomuxc_gpr;
50 enum imx6_pcie_variants variant;
52 u32 tx_deemph_gen2_3p5db;
53 u32 tx_deemph_gen2_6db;
59 /* PCIe Root Complex registers (memory-mapped) */
60 #define PCIE_RC_LCR 0x7c
61 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
62 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
63 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
65 #define PCIE_RC_LCSR 0x80
67 /* PCIe Port Logic registers (memory-mapped) */
68 #define PL_OFFSET 0x700
69 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
70 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
71 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
72 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
73 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
74 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
75 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
77 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
78 #define PCIE_PHY_CTRL_DATA_LOC 0
79 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
80 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
81 #define PCIE_PHY_CTRL_WR_LOC 18
82 #define PCIE_PHY_CTRL_RD_LOC 19
84 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
85 #define PCIE_PHY_STAT_ACK_LOC 16
87 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
88 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
90 /* PHY registers (not memory-mapped) */
91 #define PCIE_PHY_RX_ASIC_OUT 0x100D
92 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
94 #define PHY_RX_OVRD_IN_LO 0x1005
95 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
96 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
98 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
100 void __iomem *dbi_base = imx6_pcie->pp.dbi_base;
102 u32 max_iterations = 10;
103 u32 wait_counter = 0;
106 val = readl(dbi_base + PCIE_PHY_STAT);
107 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
114 } while (wait_counter < max_iterations);
119 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
121 void __iomem *dbi_base = imx6_pcie->pp.dbi_base;
125 val = addr << PCIE_PHY_CTRL_DATA_LOC;
126 writel(val, dbi_base + PCIE_PHY_CTRL);
128 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
129 writel(val, dbi_base + PCIE_PHY_CTRL);
131 ret = pcie_phy_poll_ack(imx6_pcie, 1);
135 val = addr << PCIE_PHY_CTRL_DATA_LOC;
136 writel(val, dbi_base + PCIE_PHY_CTRL);
138 return pcie_phy_poll_ack(imx6_pcie, 0);
141 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
142 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
144 void __iomem *dbi_base = imx6_pcie->pp.dbi_base;
148 ret = pcie_phy_wait_ack(imx6_pcie, addr);
152 /* assert Read signal */
153 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
154 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
156 ret = pcie_phy_poll_ack(imx6_pcie, 1);
160 val = readl(dbi_base + PCIE_PHY_STAT);
161 *data = val & 0xffff;
163 /* deassert Read signal */
164 writel(0x00, dbi_base + PCIE_PHY_CTRL);
166 return pcie_phy_poll_ack(imx6_pcie, 0);
169 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
171 void __iomem *dbi_base = imx6_pcie->pp.dbi_base;
177 ret = pcie_phy_wait_ack(imx6_pcie, addr);
181 var = data << PCIE_PHY_CTRL_DATA_LOC;
182 writel(var, dbi_base + PCIE_PHY_CTRL);
185 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
186 writel(var, dbi_base + PCIE_PHY_CTRL);
188 ret = pcie_phy_poll_ack(imx6_pcie, 1);
192 /* deassert cap data */
193 var = data << PCIE_PHY_CTRL_DATA_LOC;
194 writel(var, dbi_base + PCIE_PHY_CTRL);
196 /* wait for ack de-assertion */
197 ret = pcie_phy_poll_ack(imx6_pcie, 0);
201 /* assert wr signal */
202 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
203 writel(var, dbi_base + PCIE_PHY_CTRL);
206 ret = pcie_phy_poll_ack(imx6_pcie, 1);
210 /* deassert wr signal */
211 var = data << PCIE_PHY_CTRL_DATA_LOC;
212 writel(var, dbi_base + PCIE_PHY_CTRL);
214 /* wait for ack de-assertion */
215 ret = pcie_phy_poll_ack(imx6_pcie, 0);
219 writel(0x0, dbi_base + PCIE_PHY_CTRL);
224 static void imx6_pcie_reset_phy(struct pcie_port *pp)
226 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
229 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
230 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
231 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
232 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
234 usleep_range(2000, 3000);
236 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
237 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
238 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
239 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
242 /* Added for PCI abort handling */
243 static int imx6q_pcie_abort_handler(unsigned long addr,
244 unsigned int fsr, struct pt_regs *regs)
249 static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
251 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
252 u32 val, gpr1, gpr12;
254 switch (imx6_pcie->variant) {
256 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
257 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
258 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
259 /* Force PCIe PHY reset */
260 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
261 IMX6SX_GPR5_PCIE_BTNRST_RESET,
262 IMX6SX_GPR5_PCIE_BTNRST_RESET);
265 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
266 IMX6Q_GPR1_PCIE_SW_RST,
267 IMX6Q_GPR1_PCIE_SW_RST);
271 * If the bootloader already enabled the link we need some
272 * special handling to get the core back into a state where
273 * it is safe to touch it for configuration. As there is
274 * no dedicated reset signal wired up for MX6QDL, we need
275 * to manually force LTSSM into "detect" state before
276 * completely disabling LTSSM, which is a prerequisite for
277 * core configuration.
279 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we
280 * have a strong indication that the bootloader activated
283 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
284 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
286 if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
287 (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
288 val = readl(pp->dbi_base + PCIE_PL_PFLR);
289 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
290 val |= PCIE_PL_PFLR_FORCE_LINK;
291 writel(val, pp->dbi_base + PCIE_PL_PFLR);
293 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
294 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
297 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
298 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
299 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
300 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
307 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
309 struct pcie_port *pp = &imx6_pcie->pp;
310 struct device *dev = pp->dev;
313 switch (imx6_pcie->variant) {
315 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
317 dev_err(dev, "unable to enable pcie_axi clock\n");
321 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
322 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
324 case IMX6QP: /* FALLTHROUGH */
326 /* power up core phy and enable ref clock */
327 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
328 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
330 * the async reset input need ref clock to sync internally,
331 * when the ref clock comes after reset, internal synced
332 * reset time is too short, cannot meet the requirement.
333 * add one ~10us delay here.
336 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
337 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
344 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
346 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
347 struct device *dev = pp->dev;
350 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
352 dev_err(dev, "unable to enable pcie_phy clock\n");
356 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
358 dev_err(dev, "unable to enable pcie_bus clock\n");
362 ret = clk_prepare_enable(imx6_pcie->pcie);
364 dev_err(dev, "unable to enable pcie clock\n");
368 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
370 dev_err(dev, "unable to enable pcie ref clock\n");
374 /* allow the clocks to stabilize */
375 usleep_range(200, 500);
377 /* Some boards don't have PCIe reset GPIO. */
378 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
379 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
380 imx6_pcie->gpio_active_high);
382 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
383 !imx6_pcie->gpio_active_high);
386 switch (imx6_pcie->variant) {
388 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
389 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
392 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
393 IMX6Q_GPR1_PCIE_SW_RST, 0);
395 usleep_range(200, 500);
397 case IMX6Q: /* Nothing to do */
404 clk_disable_unprepare(imx6_pcie->pcie);
406 clk_disable_unprepare(imx6_pcie->pcie_bus);
408 clk_disable_unprepare(imx6_pcie->pcie_phy);
413 static void imx6_pcie_init_phy(struct pcie_port *pp)
415 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
417 if (imx6_pcie->variant == IMX6SX)
418 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
419 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
420 IMX6SX_GPR12_PCIE_RX_EQ_2);
422 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
423 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
425 /* configure constant input signal to the pcie ctrl and phy */
426 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
427 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
428 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
429 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
431 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
432 IMX6Q_GPR8_TX_DEEMPH_GEN1,
433 imx6_pcie->tx_deemph_gen1 << 0);
434 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
435 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
436 imx6_pcie->tx_deemph_gen2_3p5db << 6);
437 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
438 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
439 imx6_pcie->tx_deemph_gen2_6db << 12);
440 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
441 IMX6Q_GPR8_TX_SWING_FULL,
442 imx6_pcie->tx_swing_full << 18);
443 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
444 IMX6Q_GPR8_TX_SWING_LOW,
445 imx6_pcie->tx_swing_low << 25);
448 static int imx6_pcie_wait_for_link(struct pcie_port *pp)
450 struct device *dev = pp->dev;
452 /* check if the link is up or not */
453 if (!dw_pcie_wait_for_link(pp))
456 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
457 readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
458 readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
462 static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
464 struct device *dev = pp->dev;
466 unsigned int retries;
468 for (retries = 0; retries < 200; retries++) {
469 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
470 /* Test if the speed change finished. */
471 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
473 usleep_range(100, 1000);
476 dev_err(dev, "Speed change timeout\n");
480 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
482 struct pcie_port *pp = arg;
484 return dw_handle_msi_irq(pp);
487 static int imx6_pcie_establish_link(struct pcie_port *pp)
489 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
490 struct device *dev = pp->dev;
495 * Force Gen1 operation when starting the link. In case the link is
496 * started in Gen2 mode, there is a possibility the devices on the
497 * bus will not be detected at all. This happens with PCIe switches.
499 tmp = readl(pp->dbi_base + PCIE_RC_LCR);
500 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
501 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
502 writel(tmp, pp->dbi_base + PCIE_RC_LCR);
505 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
506 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
508 ret = imx6_pcie_wait_for_link(pp);
510 dev_info(dev, "Link never came up\n");
514 if (imx6_pcie->link_gen == 2) {
515 /* Allow Gen2 mode after the link is up. */
516 tmp = readl(pp->dbi_base + PCIE_RC_LCR);
517 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
518 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
519 writel(tmp, pp->dbi_base + PCIE_RC_LCR);
521 dev_info(dev, "Link: Gen2 disabled\n");
525 * Start Directed Speed Change so the best possible speed both link
526 * partners support can be negotiated.
528 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
529 tmp |= PORT_LOGIC_SPEED_CHANGE;
530 writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
532 ret = imx6_pcie_wait_for_speed_change(pp);
534 dev_err(dev, "Failed to bring link up!\n");
538 /* Make sure link training is finished as well! */
539 ret = imx6_pcie_wait_for_link(pp);
541 dev_err(dev, "Failed to bring link up!\n");
545 tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
546 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
550 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
551 readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
552 readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
553 imx6_pcie_reset_phy(pp);
558 static void imx6_pcie_host_init(struct pcie_port *pp)
560 imx6_pcie_assert_core_reset(pp);
562 imx6_pcie_init_phy(pp);
564 imx6_pcie_deassert_core_reset(pp);
566 dw_pcie_setup_rc(pp);
568 imx6_pcie_establish_link(pp);
570 if (IS_ENABLED(CONFIG_PCI_MSI))
571 dw_pcie_msi_init(pp);
574 static int imx6_pcie_link_up(struct pcie_port *pp)
576 return readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) &
577 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
580 static struct pcie_host_ops imx6_pcie_host_ops = {
581 .link_up = imx6_pcie_link_up,
582 .host_init = imx6_pcie_host_init,
585 static int __init imx6_add_pcie_port(struct pcie_port *pp,
586 struct platform_device *pdev)
588 struct device *dev = pp->dev;
591 if (IS_ENABLED(CONFIG_PCI_MSI)) {
592 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
593 if (pp->msi_irq <= 0) {
594 dev_err(dev, "failed to get MSI irq\n");
598 ret = devm_request_irq(dev, pp->msi_irq,
599 imx6_pcie_msi_handler,
600 IRQF_SHARED | IRQF_NO_THREAD,
603 dev_err(dev, "failed to request MSI irq\n");
608 pp->root_bus_nr = -1;
609 pp->ops = &imx6_pcie_host_ops;
611 ret = dw_pcie_host_init(pp);
613 dev_err(dev, "failed to initialize host\n");
620 static int __init imx6_pcie_probe(struct platform_device *pdev)
622 struct device *dev = &pdev->dev;
623 struct imx6_pcie *imx6_pcie;
624 struct pcie_port *pp;
625 struct resource *dbi_base;
626 struct device_node *node = dev->of_node;
629 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
637 (enum imx6_pcie_variants)of_device_get_match_data(dev);
639 /* Added for PCI abort handling */
640 hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
641 "imprecise external abort");
643 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
644 pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
645 if (IS_ERR(pp->dbi_base))
646 return PTR_ERR(pp->dbi_base);
649 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
650 imx6_pcie->gpio_active_high = of_property_read_bool(node,
651 "reset-gpio-active-high");
652 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
653 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
654 imx6_pcie->gpio_active_high ?
655 GPIOF_OUT_INIT_HIGH :
659 dev_err(dev, "unable to get reset gpio\n");
665 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
666 if (IS_ERR(imx6_pcie->pcie_phy)) {
667 dev_err(dev, "pcie_phy clock source missing or invalid\n");
668 return PTR_ERR(imx6_pcie->pcie_phy);
671 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
672 if (IS_ERR(imx6_pcie->pcie_bus)) {
673 dev_err(dev, "pcie_bus clock source missing or invalid\n");
674 return PTR_ERR(imx6_pcie->pcie_bus);
677 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
678 if (IS_ERR(imx6_pcie->pcie)) {
679 dev_err(dev, "pcie clock source missing or invalid\n");
680 return PTR_ERR(imx6_pcie->pcie);
683 if (imx6_pcie->variant == IMX6SX) {
684 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
686 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
688 "pcie_incbound_axi clock missing or invalid\n");
689 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
693 /* Grab GPR config register range */
694 imx6_pcie->iomuxc_gpr =
695 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
696 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
697 dev_err(dev, "unable to find iomuxc registers\n");
698 return PTR_ERR(imx6_pcie->iomuxc_gpr);
701 /* Grab PCIe PHY Tx Settings */
702 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
703 &imx6_pcie->tx_deemph_gen1))
704 imx6_pcie->tx_deemph_gen1 = 0;
706 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
707 &imx6_pcie->tx_deemph_gen2_3p5db))
708 imx6_pcie->tx_deemph_gen2_3p5db = 0;
710 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
711 &imx6_pcie->tx_deemph_gen2_6db))
712 imx6_pcie->tx_deemph_gen2_6db = 20;
714 if (of_property_read_u32(node, "fsl,tx-swing-full",
715 &imx6_pcie->tx_swing_full))
716 imx6_pcie->tx_swing_full = 127;
718 if (of_property_read_u32(node, "fsl,tx-swing-low",
719 &imx6_pcie->tx_swing_low))
720 imx6_pcie->tx_swing_low = 127;
722 /* Limit link speed */
723 ret = of_property_read_u32(node, "fsl,max-link-speed",
724 &imx6_pcie->link_gen);
726 imx6_pcie->link_gen = 1;
728 ret = imx6_add_pcie_port(pp, pdev);
732 platform_set_drvdata(pdev, imx6_pcie);
736 static void imx6_pcie_shutdown(struct platform_device *pdev)
738 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
740 /* bring down link, so bootloader gets clean state in case of reboot */
741 imx6_pcie_assert_core_reset(&imx6_pcie->pp);
744 static const struct of_device_id imx6_pcie_of_match[] = {
745 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
746 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
747 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
751 static struct platform_driver imx6_pcie_driver = {
753 .name = "imx6q-pcie",
754 .of_match_table = imx6_pcie_of_match,
756 .shutdown = imx6_pcie_shutdown,
759 static int __init imx6_pcie_init(void)
761 return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
763 device_initcall(imx6_pcie_init);