drivers/pci/host/pci-thunder-ecam.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2015, 2016 Cavium, Inc.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/ioport.h>
  12 #include <linux/of_pci.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15
  16 #include "../ecam.h"
  17
  18 static void set_val(u32 v, int where, int size, u32 *val)
  19 {
  20         int shift = (where & 3) * 8;
  21
  22         pr_debug("set_val %04x: %08x\n", (unsigned)(where & ~3), v);
  23         v >>= shift;
  24         if (size == 1)
  25                 v &= 0xff;
  26         else if (size == 2)
  27                 v &= 0xffff;
  28         *val = v;
  29 }
  30
  31 static int handle_ea_bar(u32 e0, int bar, struct pci_bus *bus,
  32                          unsigned int devfn, int where, int size, u32 *val)
  33 {
  34         void __iomem *addr;
  35         u32 v;
  36
  37         /* Entries are 16-byte aligned; bits[2,3] select word in entry */
  38         int where_a = where & 0xc;
  39
  40         if (where_a == 0) {
  41                 set_val(e0, where, size, val);
  42                 return PCIBIOS_SUCCESSFUL;
  43         }
  44         if (where_a == 0x4) {
  45                 addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
  46                 if (!addr) {
  47                         *val = ~0;
  48                         return PCIBIOS_DEVICE_NOT_FOUND;
  49                 }
  50                 v = readl(addr);
  51                 v &= ~0xf;
  52                 v |= 2; /* EA entry-1. Base-L */
  53                 set_val(v, where, size, val);
  54                 return PCIBIOS_SUCCESSFUL;
  55         }
  56         if (where_a == 0x8) {
  57                 u32 barl_orig;
  58                 u32 barl_rb;
  59
  60                 addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
  61                 if (!addr) {
  62                         *val = ~0;
  63                         return PCIBIOS_DEVICE_NOT_FOUND;
  64                 }
  65                 barl_orig = readl(addr + 0);
  66                 writel(0xffffffff, addr + 0);
  67                 barl_rb = readl(addr + 0);
  68                 writel(barl_orig, addr + 0);
  69                 /* zeros in unsettable bits */
  70                 v = ~barl_rb & ~3;
  71                 v |= 0xc; /* EA entry-2. Offset-L */
  72                 set_val(v, where, size, val);
  73                 return PCIBIOS_SUCCESSFUL;
  74         }
  75         if (where_a == 0xc) {
  76                 addr = bus->ops->map_bus(bus, devfn, bar + 4); /* BAR 1 */
  77                 if (!addr) {
  78                         *val = ~0;
  79                         return PCIBIOS_DEVICE_NOT_FOUND;
  80                 }
  81                 v = readl(addr); /* EA entry-3. Base-H */
  82                 set_val(v, where, size, val);
  83                 return PCIBIOS_SUCCESSFUL;
  84         }
  85         return PCIBIOS_DEVICE_NOT_FOUND;
  86 }
  87
  88 static int thunder_ecam_p2_config_read(struct pci_bus *bus, unsigned int devfn,
  89                                        int where, int size, u32 *val)
  90 {
  91         struct pci_config_window *cfg = bus->sysdata;
  92         int where_a = where & ~3;
  93         void __iomem *addr;
  94         u32 node_bits;
  95         u32 v;
  96
  97         /* EA Base[63:32] may be missing some bits ... */
  98         switch (where_a) {
  99         case 0xa8:
 100         case 0xbc:
 101         case 0xd0:
 102         case 0xe4:
 103                 break;
 104         default:
 105                 return pci_generic_config_read(bus, devfn, where, size, val);
 106         }
 107
 108         addr = bus->ops->map_bus(bus, devfn, where_a);
 109         if (!addr) {
 110                 *val = ~0;
 111                 return PCIBIOS_DEVICE_NOT_FOUND;
 112         }
 113
 114         v = readl(addr);
 115
 116         /*
 117          * Bit 44 of the 64-bit Base must match the same bit in
 118          * the config space access window.  Since we are working with
 119          * the high-order 32 bits, shift everything down by 32 bits.
 120          */
 121         node_bits = (cfg->res.start >> 32) & (1 << 12);
 122
 123         v |= node_bits;
 124         set_val(v, where, size, val);
 125
 126         return PCIBIOS_SUCCESSFUL;
 127 }
 128
 129 static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
 130                                     int where, int size, u32 *val)
 131 {
 132         u32 v;
 133         u32 vendor_device;
 134         u32 class_rev;
 135         void __iomem *addr;
 136         int cfg_type;
 137         int where_a = where & ~3;
 138
 139         addr = bus->ops->map_bus(bus, devfn, 0xc);
 140         if (!addr) {
 141                 *val = ~0;
 142                 return PCIBIOS_DEVICE_NOT_FOUND;
 143         }
 144
 145         v = readl(addr);
 146
 147         /* Check for non type-00 header */
 148         cfg_type = (v >> 16) & 0x7f;
 149
 150         addr = bus->ops->map_bus(bus, devfn, 8);
 151         if (!addr) {
 152                 *val = ~0;
 153                 return PCIBIOS_DEVICE_NOT_FOUND;
 154         }
 155
 156         class_rev = readl(addr);
 157         if (class_rev == 0xffffffff)
 158                 goto no_emulation;
 159
 160         if ((class_rev & 0xff) >= 8) {
 161                 /* Pass-2 handling */
 162                 if (cfg_type)
 163                         goto no_emulation;
 164                 return thunder_ecam_p2_config_read(bus, devfn, where,
 165                                                    size, val);
 166         }
 167
 168         /*
 169          * All BARs have fixed addresses specified by the EA
 170          * capability; they must return zero on read.
 171          */
 172         if (cfg_type == 0 &&
 173             ((where >= 0x10 && where < 0x2c) ||
 174              (where >= 0x1a4 && where < 0x1bc))) {
 175                 /* BAR or SR-IOV BAR */
 176                 *val = 0;
 177                 return PCIBIOS_SUCCESSFUL;
 178         }
 179
 180         addr = bus->ops->map_bus(bus, devfn, 0);
 181         if (!addr) {
 182                 *val = ~0;
 183                 return PCIBIOS_DEVICE_NOT_FOUND;
 184         }
 185
 186         vendor_device = readl(addr);
 187         if (vendor_device == 0xffffffff)
 188                 goto no_emulation;
 189
 190         pr_debug("%04x:%04x - Fix pass#: %08x, where: %03x, devfn: %03x\n",
 191                  vendor_device & 0xffff, vendor_device >> 16, class_rev,
 192                  (unsigned) where, devfn);
 193
 194         /* Check for non type-00 header */
 195         if (cfg_type == 0) {
 196                 bool has_msix;
 197                 bool is_nic = (vendor_device == 0xa01e177d);
 198                 bool is_tns = (vendor_device == 0xa01f177d);
 199
 200                 addr = bus->ops->map_bus(bus, devfn, 0x70);
 201                 if (!addr) {
 202                         *val = ~0;
 203                         return PCIBIOS_DEVICE_NOT_FOUND;
 204                 }
 205                 /* E_CAP */
 206                 v = readl(addr);
 207                 has_msix = (v & 0xff00) != 0;
 208
 209                 if (!has_msix && where_a == 0x70) {
 210                         v |= 0xbc00; /* next capability is EA at 0xbc */
 211                         set_val(v, where, size, val);
 212                         return PCIBIOS_SUCCESSFUL;
 213                 }
 214                 if (where_a == 0xb0) {
 215                         addr = bus->ops->map_bus(bus, devfn, where_a);
 216                         if (!addr) {
 217                                 *val = ~0;
 218                                 return PCIBIOS_DEVICE_NOT_FOUND;
 219                         }
 220                         v = readl(addr);
 221                         if (v & 0xff00)
 222                                 pr_err("Bad MSIX cap header: %08x\n", v);
 223                         v |= 0xbc00; /* next capability is EA at 0xbc */
 224                         set_val(v, where, size, val);
 225                         return PCIBIOS_SUCCESSFUL;
 226                 }
 227                 if (where_a == 0xbc) {
 228                         if (is_nic)
 229                                 v = 0x40014; /* EA last in chain, 4 entries */
 230                         else if (is_tns)
 231                                 v = 0x30014; /* EA last in chain, 3 entries */
 232                         else if (has_msix)
 233                                 v = 0x20014; /* EA last in chain, 2 entries */
 234                         else
 235                                 v = 0x10014; /* EA last in chain, 1 entry */
 236                         set_val(v, where, size, val);
 237                         return PCIBIOS_SUCCESSFUL;
 238                 }
 239                 if (where_a >= 0xc0 && where_a < 0xd0)
 240                         /* EA entry-0. PP=0, BAR0 Size:3 */
 241                         return handle_ea_bar(0x80ff0003,
 242                                              0x10, bus, devfn, where,
 243                                              size, val);
 244                 if (where_a >= 0xd0 && where_a < 0xe0 && has_msix)
 245                          /* EA entry-1. PP=0, BAR4 Size:3 */
 246                         return handle_ea_bar(0x80ff0043,
 247                                              0x20, bus, devfn, where,
 248                                              size, val);
 249                 if (where_a >= 0xe0 && where_a < 0xf0 && is_tns)
 250                         /* EA entry-2. PP=0, BAR2, Size:3 */
 251                         return handle_ea_bar(0x80ff0023,
 252                                              0x18, bus, devfn, where,
 253                                              size, val);
 254                 if (where_a >= 0xe0 && where_a < 0xf0 && is_nic)
 255                         /* EA entry-2. PP=4, VF_BAR0 (9), Size:3 */
 256                         return handle_ea_bar(0x80ff0493,
 257                                              0x1a4, bus, devfn, where,
 258                                              size, val);
 259                 if (where_a >= 0xf0 && where_a < 0x100 && is_nic)
 260                         /* EA entry-3. PP=4, VF_BAR4 (d), Size:3 */
 261                         return handle_ea_bar(0x80ff04d3,
 262                                              0x1b4, bus, devfn, where,
 263                                              size, val);
 264         } else if (cfg_type == 1) {
 265                 bool is_rsl_bridge = devfn == 0x08;
 266                 bool is_rad_bridge = devfn == 0xa0;
 267                 bool is_zip_bridge = devfn == 0xa8;
 268                 bool is_dfa_bridge = devfn == 0xb0;
 269                 bool is_nic_bridge = devfn == 0x10;
 270
 271                 if (where_a == 0x70) {
 272                         addr = bus->ops->map_bus(bus, devfn, where_a);
 273                         if (!addr) {
 274                                 *val = ~0;
 275                                 return PCIBIOS_DEVICE_NOT_FOUND;
 276                         }
 277                         v = readl(addr);
 278                         if (v & 0xff00)
 279                                 pr_err("Bad PCIe cap header: %08x\n", v);
 280                         v |= 0xbc00; /* next capability is EA at 0xbc */
 281                         set_val(v, where, size, val);
 282                         return PCIBIOS_SUCCESSFUL;
 283                 }
 284                 if (where_a == 0xbc) {
 285                         if (is_nic_bridge)
 286                                 v = 0x10014; /* EA last in chain, 1 entry */
 287                         else
 288                                 v = 0x00014; /* EA last in chain, no entries */
 289                         set_val(v, where, size, val);
 290                         return PCIBIOS_SUCCESSFUL;
 291                 }
 292                 if (where_a == 0xc0) {
 293                         if (is_rsl_bridge || is_nic_bridge)
 294                                 v = 0x0101; /* subordinate:secondary = 1:1 */
 295                         else if (is_rad_bridge)
 296                                 v = 0x0202; /* subordinate:secondary = 2:2 */
 297                         else if (is_zip_bridge)
 298                                 v = 0x0303; /* subordinate:secondary = 3:3 */
 299                         else if (is_dfa_bridge)
 300                                 v = 0x0404; /* subordinate:secondary = 4:4 */
 301                         set_val(v, where, size, val);
 302                         return PCIBIOS_SUCCESSFUL;
 303                 }
 304                 if (where_a == 0xc4 && is_nic_bridge) {
 305                         /* Enabled, not-Write, SP=ff, PP=05, BEI=6, ES=4 */
 306                         v = 0x80ff0564;
 307                         set_val(v, where, size, val);
 308                         return PCIBIOS_SUCCESSFUL;
 309                 }
 310                 if (where_a == 0xc8 && is_nic_bridge) {
 311                         v = 0x00000002; /* Base-L 64-bit */
 312                         set_val(v, where, size, val);
 313                         return PCIBIOS_SUCCESSFUL;
 314                 }
 315                 if (where_a == 0xcc && is_nic_bridge) {
 316                         v = 0xfffffffe; /* MaxOffset-L 64-bit */
 317                         set_val(v, where, size, val);
 318                         return PCIBIOS_SUCCESSFUL;
 319                 }
 320                 if (where_a == 0xd0 && is_nic_bridge) {
 321                         v = 0x00008430; /* NIC Base-H */
 322                         set_val(v, where, size, val);
 323                         return PCIBIOS_SUCCESSFUL;
 324                 }
 325                 if (where_a == 0xd4 && is_nic_bridge) {
 326                         v = 0x0000000f; /* MaxOffset-H */
 327                         set_val(v, where, size, val);
 328                         return PCIBIOS_SUCCESSFUL;
 329                 }
 330         }
 331 no_emulation:
 332         return pci_generic_config_read(bus, devfn, where, size, val);
 333 }
 334
 335 static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn,
 336                                      int where, int size, u32 val)
 337 {
 338         /*
 339          * All BARs have fixed addresses; ignore BAR writes so they
 340          * don't get corrupted.
 341          */
 342         if ((where >= 0x10 && where < 0x2c) ||
 343             (where >= 0x1a4 && where < 0x1bc))
 344                 /* BAR or SR-IOV BAR */
 345                 return PCIBIOS_SUCCESSFUL;
 346
 347         return pci_generic_config_write(bus, devfn, where, size, val);
 348 }
 349
 350 static struct pci_ecam_ops pci_thunder_ecam_ops = {
 351         .bus_shift      = 20,
 352         .pci_ops        = {
 353                 .map_bus        = pci_ecam_map_bus,
 354                 .read           = thunder_ecam_config_read,
 355                 .write          = thunder_ecam_config_write,
 356         }
 357 };
 358
 359 static const struct of_device_id thunder_ecam_of_match[] = {
 360         { .compatible = "cavium,pci-host-thunder-ecam" },
 361         { },
 362 };
 363 MODULE_DEVICE_TABLE(of, thunder_ecam_of_match);
 364
 365 static int thunder_ecam_probe(struct platform_device *pdev)
 366 {
 367         return pci_host_common_probe(pdev, &pci_thunder_ecam_ops);
 368 }
 369
 370 static struct platform_driver thunder_ecam_driver = {
 371         .driver = {
 372                 .name = KBUILD_MODNAME,
 373                 .of_match_table = thunder_ecam_of_match,
 374         },
 375         .probe = thunder_ecam_probe,
 376 };
 377 module_platform_driver(thunder_ecam_driver);
 378
 379 MODULE_DESCRIPTION("Thunder ECAM PCI host driver");
 380 MODULE_LICENSE("GPL v2");