2 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
4 * Author: Ley Foon Tan <lftan@altera.com>
5 * Description: Altera PCIe host controller driver
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/init.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
31 #define RP_TX_REG0 0x2000
32 #define RP_TX_REG1 0x2004
33 #define RP_TX_CNTRL 0x2008
36 #define RP_RXCPL_STATUS 0x2010
37 #define RP_RXCPL_EOP 0x2
38 #define RP_RXCPL_SOP 0x1
39 #define RP_RXCPL_REG0 0x2014
40 #define RP_RXCPL_REG1 0x2018
41 #define P2A_INT_STATUS 0x3060
42 #define P2A_INT_STS_ALL 0xf
43 #define P2A_INT_ENABLE 0x3070
44 #define P2A_INT_ENA_ALL 0xf
45 #define RP_LTSSM 0x3c64
46 #define RP_LTSSM_MASK 0x1f
49 #define PCIE_CAP_OFFSET 0x80
50 /* TLP configuration type 0 and 1 */
51 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
52 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
53 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
54 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
55 #define TLP_PAYLOAD_SIZE 0x01
56 #define TLP_READ_TAG 0x1d
57 #define TLP_WRITE_TAG 0x10
58 #define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
59 #define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be))
60 #define TLP_CFG_DW2(bus, devfn, offset) \
61 (((bus) << 24) | ((devfn) << 16) | (offset))
62 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
63 #define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
64 #define TLP_HDR_SIZE 3
68 #define LINK_UP_TIMEOUT HZ
69 #define LINK_RETRAIN_TIMEOUT HZ
76 struct platform_device *pdev;
77 void __iomem *cra_base;
80 struct irq_domain *irq_domain;
81 struct resource bus_range;
82 struct list_head resources;
85 struct tlp_rp_regpair_t {
91 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
94 writel_relaxed(value, pcie->cra_base + reg);
97 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
99 return readl_relaxed(pcie->cra_base + reg);
102 static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
104 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
108 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
109 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
110 * using these registers, so it can be reached by DMA from EP devices.
111 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
112 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
113 * should be hidden during enumeration to avoid the sizing and resource
114 * allocation by PCIe core.
116 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
119 if (pci_is_root_bus(bus) && (devfn == 0) &&
120 (offset == PCI_BASE_ADDRESS_0))
126 static void tlp_write_tx(struct altera_pcie *pcie,
127 struct tlp_rp_regpair_t *tlp_rp_regdata)
129 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
130 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
131 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
134 static bool altera_pcie_valid_config(struct altera_pcie *pcie,
135 struct pci_bus *bus, int dev)
137 /* If there is no link, then there is no device */
138 if (bus->number != pcie->root_bus_nr) {
139 if (!altera_pcie_link_is_up(pcie))
143 /* access only one slot on each root port */
144 if (bus->number == pcie->root_bus_nr && dev > 0)
150 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
159 * Minimum 2 loops to read TLP headers and 1 loop to read data
162 for (i = 0; i < TLP_LOOP; i++) {
163 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
164 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
165 reg0 = cra_readl(pcie, RP_RXCPL_REG0);
166 reg1 = cra_readl(pcie, RP_RXCPL_REG1);
168 if (ctrl & RP_RXCPL_SOP) {
170 comp_status = TLP_COMP_STATUS(reg1);
173 if (ctrl & RP_RXCPL_EOP) {
175 return PCIBIOS_DEVICE_NOT_FOUND;
180 return PCIBIOS_SUCCESSFUL;
186 return PCIBIOS_DEVICE_NOT_FOUND;
189 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
190 u32 data, bool align)
192 struct tlp_rp_regpair_t tlp_rp_regdata;
194 tlp_rp_regdata.reg0 = headers[0];
195 tlp_rp_regdata.reg1 = headers[1];
196 tlp_rp_regdata.ctrl = RP_TX_SOP;
197 tlp_write_tx(pcie, &tlp_rp_regdata);
200 tlp_rp_regdata.reg0 = headers[2];
201 tlp_rp_regdata.reg1 = 0;
202 tlp_rp_regdata.ctrl = 0;
203 tlp_write_tx(pcie, &tlp_rp_regdata);
205 tlp_rp_regdata.reg0 = data;
206 tlp_rp_regdata.reg1 = 0;
208 tlp_rp_regdata.reg0 = headers[2];
209 tlp_rp_regdata.reg1 = data;
212 tlp_rp_regdata.ctrl = RP_TX_EOP;
213 tlp_write_tx(pcie, &tlp_rp_regdata);
216 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
217 int where, u8 byte_en, u32 *value)
219 u32 headers[TLP_HDR_SIZE];
221 if (bus == pcie->root_bus_nr)
222 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
224 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
226 headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
227 TLP_READ_TAG, byte_en);
228 headers[2] = TLP_CFG_DW2(bus, devfn, where);
230 tlp_write_packet(pcie, headers, 0, false);
232 return tlp_read_packet(pcie, value);
235 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
236 int where, u8 byte_en, u32 value)
238 u32 headers[TLP_HDR_SIZE];
241 if (bus == pcie->root_bus_nr)
242 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
244 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
246 headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
247 TLP_WRITE_TAG, byte_en);
248 headers[2] = TLP_CFG_DW2(bus, devfn, where);
250 /* check alignment to Qword */
251 if ((where & 0x7) == 0)
252 tlp_write_packet(pcie, headers, value, true);
254 tlp_write_packet(pcie, headers, value, false);
256 ret = tlp_read_packet(pcie, NULL);
257 if (ret != PCIBIOS_SUCCESSFUL)
261 * Monitor changes to PCI_PRIMARY_BUS register on root port
262 * and update local copy of root bus number accordingly.
264 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
265 pcie->root_bus_nr = (u8)(value);
267 return PCIBIOS_SUCCESSFUL;
270 static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,
271 unsigned int devfn, int where, int size,
280 byte_en = 1 << (where & 3);
283 byte_en = 3 << (where & 3);
290 ret = tlp_cfg_dword_read(pcie, busno, devfn,
291 (where & ~DWORD_MASK), byte_en, &data);
292 if (ret != PCIBIOS_SUCCESSFUL)
297 *value = (data >> (8 * (where & 0x3))) & 0xff;
300 *value = (data >> (8 * (where & 0x2))) & 0xffff;
307 return PCIBIOS_SUCCESSFUL;
310 static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,
311 unsigned int devfn, int where, int size,
315 u32 shift = 8 * (where & 3);
320 data32 = (value & 0xff) << shift;
321 byte_en = 1 << (where & 3);
324 data32 = (value & 0xffff) << shift;
325 byte_en = 3 << (where & 3);
333 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),
337 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
338 int where, int size, u32 *value)
340 struct altera_pcie *pcie = bus->sysdata;
342 if (altera_pcie_hide_rc_bar(bus, devfn, where))
343 return PCIBIOS_BAD_REGISTER_NUMBER;
345 if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
347 return PCIBIOS_DEVICE_NOT_FOUND;
350 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,
354 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
355 int where, int size, u32 value)
357 struct altera_pcie *pcie = bus->sysdata;
359 if (altera_pcie_hide_rc_bar(bus, devfn, where))
360 return PCIBIOS_BAD_REGISTER_NUMBER;
362 if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
363 return PCIBIOS_DEVICE_NOT_FOUND;
365 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,
369 static struct pci_ops altera_pcie_ops = {
370 .read = altera_pcie_cfg_read,
371 .write = altera_pcie_cfg_write,
374 static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,
375 unsigned int devfn, int offset, u16 *value)
380 ret = _altera_pcie_cfg_read(pcie, busno, devfn,
381 PCIE_CAP_OFFSET + offset, sizeof(*value),
387 static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,
388 unsigned int devfn, int offset, u16 value)
390 return _altera_pcie_cfg_write(pcie, busno, devfn,
391 PCIE_CAP_OFFSET + offset, sizeof(value),
395 static void altera_wait_link_retrain(struct altera_pcie *pcie)
398 unsigned long start_jiffies;
400 /* Wait for link training end. */
401 start_jiffies = jiffies;
403 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
404 PCI_EXP_LNKSTA, ®16);
405 if (!(reg16 & PCI_EXP_LNKSTA_LT))
408 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {
409 dev_err(&pcie->pdev->dev, "link retrain timeout\n");
415 /* Wait for link is up */
416 start_jiffies = jiffies;
418 if (altera_pcie_link_is_up(pcie))
421 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {
422 dev_err(&pcie->pdev->dev, "link up timeout\n");
429 static void altera_pcie_retrain(struct altera_pcie *pcie)
431 u16 linkcap, linkstat, linkctl;
433 if (!altera_pcie_link_is_up(pcie))
437 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
438 * current speed is 2.5 GB/s.
440 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,
442 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
445 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,
447 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
448 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
449 PCI_EXP_LNKCTL, &linkctl);
450 linkctl |= PCI_EXP_LNKCTL_RL;
451 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,
452 PCI_EXP_LNKCTL, linkctl);
454 altera_wait_link_retrain(pcie);
458 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
459 irq_hw_number_t hwirq)
461 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
462 irq_set_chip_data(irq, domain->host_data);
467 static const struct irq_domain_ops intx_domain_ops = {
468 .map = altera_pcie_intx_map,
471 static void altera_pcie_isr(struct irq_desc *desc)
473 struct irq_chip *chip = irq_desc_get_chip(desc);
474 struct altera_pcie *pcie;
475 unsigned long status;
479 chained_irq_enter(chip, desc);
480 pcie = irq_desc_get_handler_data(desc);
482 while ((status = cra_readl(pcie, P2A_INT_STATUS)
483 & P2A_INT_STS_ALL) != 0) {
484 for_each_set_bit(bit, &status, INTX_NUM) {
485 /* clear interrupts */
486 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
488 virq = irq_find_mapping(pcie->irq_domain, bit + 1);
490 generic_handle_irq(virq);
492 dev_err(&pcie->pdev->dev,
493 "unexpected IRQ, INT%d\n", bit);
497 chained_irq_exit(chip, desc);
500 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
502 int err, res_valid = 0;
503 struct device *dev = &pcie->pdev->dev;
504 struct device_node *np = dev->of_node;
505 struct resource_entry *win;
507 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
512 err = devm_request_pci_bus_resources(dev, &pcie->resources);
514 goto out_release_res;
516 resource_list_for_each_entry(win, &pcie->resources) {
517 struct resource *res = win->res;
519 if (resource_type(res) == IORESOURCE_MEM)
520 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
526 dev_err(dev, "non-prefetchable memory resource required\n");
530 pci_free_resource_list(&pcie->resources);
534 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
536 struct device *dev = &pcie->pdev->dev;
537 struct device_node *node = dev->of_node;
540 pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
541 &intx_domain_ops, pcie);
542 if (!pcie->irq_domain) {
543 dev_err(dev, "Failed to get a INTx IRQ domain\n");
550 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
552 struct resource *cra;
553 struct platform_device *pdev = pcie->pdev;
555 cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
557 dev_err(&pdev->dev, "no Cra memory resource defined\n");
561 pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
562 if (IS_ERR(pcie->cra_base)) {
563 dev_err(&pdev->dev, "failed to map cra memory\n");
564 return PTR_ERR(pcie->cra_base);
568 pcie->irq = platform_get_irq(pdev, 0);
569 if (pcie->irq <= 0) {
570 dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
574 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
579 static void altera_pcie_host_init(struct altera_pcie *pcie)
581 altera_pcie_retrain(pcie);
584 static int altera_pcie_probe(struct platform_device *pdev)
586 struct altera_pcie *pcie;
588 struct pci_bus *child;
591 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
597 ret = altera_pcie_parse_dt(pcie);
599 dev_err(&pdev->dev, "Parsing DT failed\n");
603 INIT_LIST_HEAD(&pcie->resources);
605 ret = altera_pcie_parse_request_of_pci_ranges(pcie);
607 dev_err(&pdev->dev, "Failed add resources\n");
611 ret = altera_pcie_init_irq_domain(pcie);
613 dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
617 /* clear all interrupts */
618 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
619 /* enable all interrupts */
620 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
621 altera_pcie_host_init(pcie);
623 bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
624 pcie, &pcie->resources);
628 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
629 pci_assign_unassigned_bus_resources(bus);
631 /* Configure PCI Express setting. */
632 list_for_each_entry(child, &bus->children, node)
633 pcie_bus_configure_settings(child);
635 pci_bus_add_devices(bus);
637 platform_set_drvdata(pdev, pcie);
641 static const struct of_device_id altera_pcie_of_match[] = {
642 { .compatible = "altr,pcie-root-port-1.0", },
646 static struct platform_driver altera_pcie_driver = {
647 .probe = altera_pcie_probe,
649 .name = "altera-pcie",
650 .of_match_table = altera_pcie_of_match,
651 .suppress_bind_attrs = true,
655 static int altera_pcie_init(void)
657 return platform_driver_register(&altera_pcie_driver);
659 device_initcall(altera_pcie_init);