2 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/irqchip/chained_irq.h>
20 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_pci.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
28 #define RP_TX_REG0 0x2000
29 #define RP_TX_REG1 0x2004
30 #define RP_TX_CNTRL 0x2008
33 #define RP_RXCPL_STATUS 0x2010
34 #define RP_RXCPL_EOP 0x2
35 #define RP_RXCPL_SOP 0x1
36 #define RP_RXCPL_REG0 0x2014
37 #define RP_RXCPL_REG1 0x2018
38 #define P2A_INT_STATUS 0x3060
39 #define P2A_INT_STS_ALL 0xf
40 #define P2A_INT_ENABLE 0x3070
41 #define P2A_INT_ENA_ALL 0xf
42 #define RP_LTSSM 0x3c64
43 #define RP_LTSSM_MASK 0x1f
46 /* TLP configuration type 0 and 1 */
47 #define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
48 #define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
49 #define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
50 #define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
51 #define TLP_PAYLOAD_SIZE 0x01
52 #define TLP_READ_TAG 0x1d
53 #define TLP_WRITE_TAG 0x10
54 #define TLP_CFG_DW0(fmttype) (((fmttype) << 24) | TLP_PAYLOAD_SIZE)
55 #define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) | (tag << 8) | (be))
56 #define TLP_CFG_DW2(bus, devfn, offset) \
57 (((bus) << 24) | ((devfn) << 16) | (offset))
58 #define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
59 #define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
60 #define TLP_HDR_SIZE 3
64 #define LINK_UP_TIMEOUT 5000
71 struct platform_device *pdev;
72 void __iomem *cra_base;
75 struct irq_domain *irq_domain;
76 struct resource bus_range;
77 struct list_head resources;
80 struct tlp_rp_regpair_t {
86 static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
89 writel_relaxed(value, pcie->cra_base + reg);
92 static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
94 return readl_relaxed(pcie->cra_base + reg);
97 static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
99 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
102 static void altera_pcie_retrain(struct pci_dev *dev)
104 u16 linkcap, linkstat;
105 struct altera_pcie *pcie = dev->bus->sysdata;
108 if (!altera_pcie_link_is_up(pcie))
112 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
113 * current speed is 2.5 GB/s.
115 pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
117 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
120 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
121 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
122 pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
124 while (!altera_pcie_link_is_up(pcie)) {
126 if (timeout > LINK_UP_TIMEOUT)
132 DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
135 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
136 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
137 * using these registers, so it can be reached by DMA from EP devices.
138 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
139 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
140 * should be hidden during enumeration to avoid the sizing and resource
141 * allocation by PCIe core.
143 static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
146 if (pci_is_root_bus(bus) && (devfn == 0) &&
147 (offset == PCI_BASE_ADDRESS_0))
153 static void tlp_write_tx(struct altera_pcie *pcie,
154 struct tlp_rp_regpair_t *tlp_rp_regdata)
156 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
157 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
158 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
161 static bool altera_pcie_valid_config(struct altera_pcie *pcie,
162 struct pci_bus *bus, int dev)
164 /* If there is no link, then there is no device */
165 if (bus->number != pcie->root_bus_nr) {
166 if (!altera_pcie_link_is_up(pcie))
170 /* access only one slot on each root port */
171 if (bus->number == pcie->root_bus_nr && dev > 0)
175 * Do not read more than one device on the bus directly attached
176 * to root port, root port can only attach to one downstream port.
178 if (bus->primary == pcie->root_bus_nr && dev > 0)
184 static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
193 * Minimum 2 loops to read TLP headers and 1 loop to read data
196 for (i = 0; i < TLP_LOOP; i++) {
197 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
198 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
199 reg0 = cra_readl(pcie, RP_RXCPL_REG0);
200 reg1 = cra_readl(pcie, RP_RXCPL_REG1);
202 if (ctrl & RP_RXCPL_SOP) {
204 comp_status = TLP_COMP_STATUS(reg1);
207 if (ctrl & RP_RXCPL_EOP) {
209 return PCIBIOS_DEVICE_NOT_FOUND;
214 return PCIBIOS_SUCCESSFUL;
220 return PCIBIOS_DEVICE_NOT_FOUND;
223 static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
224 u32 data, bool align)
226 struct tlp_rp_regpair_t tlp_rp_regdata;
228 tlp_rp_regdata.reg0 = headers[0];
229 tlp_rp_regdata.reg1 = headers[1];
230 tlp_rp_regdata.ctrl = RP_TX_SOP;
231 tlp_write_tx(pcie, &tlp_rp_regdata);
234 tlp_rp_regdata.reg0 = headers[2];
235 tlp_rp_regdata.reg1 = 0;
236 tlp_rp_regdata.ctrl = 0;
237 tlp_write_tx(pcie, &tlp_rp_regdata);
239 tlp_rp_regdata.reg0 = data;
240 tlp_rp_regdata.reg1 = 0;
242 tlp_rp_regdata.reg0 = headers[2];
243 tlp_rp_regdata.reg1 = data;
246 tlp_rp_regdata.ctrl = RP_TX_EOP;
247 tlp_write_tx(pcie, &tlp_rp_regdata);
250 static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
251 int where, u8 byte_en, u32 *value)
253 u32 headers[TLP_HDR_SIZE];
255 if (bus == pcie->root_bus_nr)
256 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
258 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
260 headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
261 TLP_READ_TAG, byte_en);
262 headers[2] = TLP_CFG_DW2(bus, devfn, where);
264 tlp_write_packet(pcie, headers, 0, false);
266 return tlp_read_packet(pcie, value);
269 static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
270 int where, u8 byte_en, u32 value)
272 u32 headers[TLP_HDR_SIZE];
275 if (bus == pcie->root_bus_nr)
276 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
278 headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
280 headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
281 TLP_WRITE_TAG, byte_en);
282 headers[2] = TLP_CFG_DW2(bus, devfn, where);
284 /* check alignment to Qword */
285 if ((where & 0x7) == 0)
286 tlp_write_packet(pcie, headers, value, true);
288 tlp_write_packet(pcie, headers, value, false);
290 ret = tlp_read_packet(pcie, NULL);
291 if (ret != PCIBIOS_SUCCESSFUL)
295 * Monitor changes to PCI_PRIMARY_BUS register on root port
296 * and update local copy of root bus number accordingly.
298 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
299 pcie->root_bus_nr = (u8)(value);
301 return PCIBIOS_SUCCESSFUL;
304 static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
305 int where, int size, u32 *value)
307 struct altera_pcie *pcie = bus->sysdata;
312 if (altera_pcie_hide_rc_bar(bus, devfn, where))
313 return PCIBIOS_BAD_REGISTER_NUMBER;
315 if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
317 return PCIBIOS_DEVICE_NOT_FOUND;
322 byte_en = 1 << (where & 3);
325 byte_en = 3 << (where & 3);
332 ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
333 (where & ~DWORD_MASK), byte_en, &data);
334 if (ret != PCIBIOS_SUCCESSFUL)
339 *value = (data >> (8 * (where & 0x3))) & 0xff;
342 *value = (data >> (8 * (where & 0x2))) & 0xffff;
349 return PCIBIOS_SUCCESSFUL;
352 static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
353 int where, int size, u32 value)
355 struct altera_pcie *pcie = bus->sysdata;
357 u32 shift = 8 * (where & 3);
360 if (altera_pcie_hide_rc_bar(bus, devfn, where))
361 return PCIBIOS_BAD_REGISTER_NUMBER;
363 if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
364 return PCIBIOS_DEVICE_NOT_FOUND;
368 data32 = (value & 0xff) << shift;
369 byte_en = 1 << (where & 3);
372 data32 = (value & 0xffff) << shift;
373 byte_en = 3 << (where & 3);
381 return tlp_cfg_dword_write(pcie, bus->number, devfn,
382 (where & ~DWORD_MASK), byte_en, data32);
385 static struct pci_ops altera_pcie_ops = {
386 .read = altera_pcie_cfg_read,
387 .write = altera_pcie_cfg_write,
390 static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
391 irq_hw_number_t hwirq)
393 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
394 irq_set_chip_data(irq, domain->host_data);
399 static const struct irq_domain_ops intx_domain_ops = {
400 .map = altera_pcie_intx_map,
403 static void altera_pcie_isr(struct irq_desc *desc)
405 struct irq_chip *chip = irq_desc_get_chip(desc);
406 struct altera_pcie *pcie;
407 unsigned long status;
411 chained_irq_enter(chip, desc);
412 pcie = irq_desc_get_handler_data(desc);
414 while ((status = cra_readl(pcie, P2A_INT_STATUS)
415 & P2A_INT_STS_ALL) != 0) {
416 for_each_set_bit(bit, &status, INTX_NUM) {
417 /* clear interrupts */
418 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
420 virq = irq_find_mapping(pcie->irq_domain, bit + 1);
422 generic_handle_irq(virq);
424 dev_err(&pcie->pdev->dev,
425 "unexpected IRQ, INT%d\n", bit);
429 chained_irq_exit(chip, desc);
432 static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
434 int err, res_valid = 0;
435 struct device *dev = &pcie->pdev->dev;
436 struct device_node *np = dev->of_node;
437 struct resource_entry *win;
439 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
444 err = devm_request_pci_bus_resources(dev, &pcie->resources);
446 goto out_release_res;
448 resource_list_for_each_entry(win, &pcie->resources) {
449 struct resource *res = win->res;
451 if (resource_type(res) == IORESOURCE_MEM)
452 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
458 dev_err(dev, "non-prefetchable memory resource required\n");
462 pci_free_resource_list(&pcie->resources);
466 static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
468 struct device *dev = &pcie->pdev->dev;
469 struct device_node *node = dev->of_node;
472 pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
473 &intx_domain_ops, pcie);
474 if (!pcie->irq_domain) {
475 dev_err(dev, "Failed to get a INTx IRQ domain\n");
482 static int altera_pcie_parse_dt(struct altera_pcie *pcie)
484 struct resource *cra;
485 struct platform_device *pdev = pcie->pdev;
487 cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
489 dev_err(&pdev->dev, "no Cra memory resource defined\n");
493 pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
494 if (IS_ERR(pcie->cra_base)) {
495 dev_err(&pdev->dev, "failed to map cra memory\n");
496 return PTR_ERR(pcie->cra_base);
500 pcie->irq = platform_get_irq(pdev, 0);
501 if (pcie->irq <= 0) {
502 dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
506 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
511 static int altera_pcie_probe(struct platform_device *pdev)
513 struct altera_pcie *pcie;
515 struct pci_bus *child;
518 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
524 ret = altera_pcie_parse_dt(pcie);
526 dev_err(&pdev->dev, "Parsing DT failed\n");
530 INIT_LIST_HEAD(&pcie->resources);
532 ret = altera_pcie_parse_request_of_pci_ranges(pcie);
534 dev_err(&pdev->dev, "Failed add resources\n");
538 ret = altera_pcie_init_irq_domain(pcie);
540 dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
544 /* clear all interrupts */
545 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
546 /* enable all interrupts */
547 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
549 bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
550 pcie, &pcie->resources);
554 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
555 pci_assign_unassigned_bus_resources(bus);
557 /* Configure PCI Express setting. */
558 list_for_each_entry(child, &bus->children, node)
559 pcie_bus_configure_settings(child);
561 pci_bus_add_devices(bus);
563 platform_set_drvdata(pdev, pcie);
567 static const struct of_device_id altera_pcie_of_match[] = {
568 { .compatible = "altr,pcie-root-port-1.0", },
571 MODULE_DEVICE_TABLE(of, altera_pcie_of_match);
573 static struct platform_driver altera_pcie_driver = {
574 .probe = altera_pcie_probe,
576 .name = "altera-pcie",
577 .of_match_table = altera_pcie_of_match,
578 .suppress_bind_attrs = true,
582 static int altera_pcie_init(void)
584 return platform_driver_register(&altera_pcie_driver);
586 module_init(altera_pcie_init);
588 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
589 MODULE_DESCRIPTION("Altera PCIe host controller driver");
590 MODULE_LICENSE("GPL v2");